kernel/cost.cc

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
   5  *
   6  *  Permission to use, copy, modify, and/or distribute this software for any
   7  *  purpose with or without fee is hereby granted, provided that the above
   8  *  copyright notice and this permission notice appear in all copies.
   9  *
  10  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  13  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  15  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  16  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  *
  18  */
  19
  20 #include "kernel/yosys.h"
  21 #include "kernel/cost.h"
  22
  23 YOSYS_NAMESPACE_BEGIN
  24
  25 int get_cell_cost(RTLIL::IdString type, const dict<RTLIL::IdString, RTLIL::Const> &parameters,
  26                 RTLIL::Design *design, dict<RTLIL::IdString, int> *mod_cost_cache)
  27 {
  28         static dict<RTLIL::IdString, int> gate_cost = {
  29                 { "$_BUF_",    1 },
  30                 { "$_NOT_",    2 },
  31                 { "$_AND_",    4 },
  32                 { "$_NAND_",   4 },
  33                 { "$_OR_",     4 },
  34                 { "$_NOR_",    4 },
  35                 { "$_ANDNOT_", 4 },
  36                 { "$_ORNOT_",  4 },
  37                 { "$_XOR_",    8 },
  38                 { "$_XNOR_",   8 },
  39                 { "$_AOI3_",   6 },
  40                 { "$_OAI3_",   6 },
  41                 { "$_AOI4_",   8 },
  42                 { "$_OAI4_",   8 },
  43                 { "$_MUX_",    4 }
  44         };
  45
  46         if (gate_cost.count(type))
  47                 return gate_cost.at(type);
  48
  49         if (parameters.empty() && design && design->module(type))
  50         {
  51                 RTLIL::Module *mod = design->module(type);
  52
  53                 if (mod->attributes.count("\\cost"))
  54                         return mod->attributes.at("\\cost").as_int();
  55
  56                 dict<RTLIL::IdString, int> local_mod_cost_cache;
  57                 if (mod_cost_cache == nullptr)
  58                         mod_cost_cache = &local_mod_cost_cache;
  59
  60                 if (mod_cost_cache->count(mod->name))
  61                         return mod_cost_cache->at(mod->name);
  62
  63                 int module_cost = 1;
  64                 for (auto c : mod->cells())
  65                         module_cost += get_cell_cost(c, mod_cost_cache);
  66
  67                 (*mod_cost_cache)[mod->name] = module_cost;
  68                 return module_cost;
  69         }
  70
  71         log_warning("Can't determine cost of %s cell (%d parameters).\n", log_id(type), GetSize(parameters));
  72         return 1;
  73 }
  74
  75 YOSYS_NAMESPACE_END