kernel/cost.h

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
   5  *
   6  *  Permission to use, copy, modify, and/or distribute this software for any
   7  *  purpose with or without fee is hereby granted, provided that the above
   8  *  copyright notice and this permission notice appear in all copies.
   9  *
  10  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  13  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  15  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  16  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  *
  18  */
  19
  20 #ifndef COST_H
  21 #define COST_H
  22
  23 #include "kernel/yosys.h"
  24
  25 YOSYS_NAMESPACE_BEGIN
  26
  27 struct CellCosts
  28 {
  29         static const dict<RTLIL::IdString, int>& default_gate_cost() {
  30                 static const dict<RTLIL::IdString, int> db = {
  31                         { ID($_BUF_),    1 },
  32                         { ID($_NOT_),    2 },
  33                         { ID($_AND_),    4 },
  34                         { ID($_NAND_),   4 },
  35                         { ID($_OR_),     4 },
  36                         { ID($_NOR_),    4 },
  37                         { ID($_ANDNOT_), 4 },
  38                         { ID($_ORNOT_),  4 },
  39                         { ID($_XOR_),    5 },
  40                         { ID($_XNOR_),   5 },
  41                         { ID($_AOI3_),   6 },
  42                         { ID($_OAI3_),   6 },
  43                         { ID($_AOI4_),   7 },
  44                         { ID($_OAI4_),   7 },
  45                         { ID($_MUX_),    4 },
  46                         { ID($_NMUX_),   4 }
  47                 };
  48                 return db;
  49         }
  50
  51         static const dict<RTLIL::IdString, int>& cmos_gate_cost() {
  52                 static const dict<RTLIL::IdString, int> db = {
  53                         { ID($_BUF_),     1 },
  54                         { ID($_NOT_),     2 },
  55                         { ID($_AND_),     6 },
  56                         { ID($_NAND_),    4 },
  57                         { ID($_OR_),      6 },
  58                         { ID($_NOR_),     4 },
  59                         { ID($_ANDNOT_),  6 },
  60                         { ID($_ORNOT_),   6 },
  61                         { ID($_XOR_),    12 },
  62                         { ID($_XNOR_),   12 },
  63                         { ID($_AOI3_),    6 },
  64                         { ID($_OAI3_),    6 },
  65                         { ID($_AOI4_),    8 },
  66                         { ID($_OAI4_),    8 },
  67                         { ID($_MUX_),    12 },
  68                         { ID($_NMUX_),   10 }
  69                 };
  70                 return db;
  71         }
  72
  73         dict<RTLIL::IdString, int> mod_cost_cache;
  74         const dict<RTLIL::IdString, int> *gate_cost = nullptr;
  75         Design *design = nullptr;
  76
  77         int get(RTLIL::IdString type) const
  78         {
  79                 if (gate_cost && gate_cost->count(type))
  80                         return gate_cost->at(type);
  81
  82                 log_warning("Can't determine cost of %s cell.\n", log_id(type));
  83                 return 1;
  84         }
  85
  86         int get(RTLIL::Cell *cell)
  87         {
  88                 if (gate_cost && gate_cost->count(cell->type))
  89                         return gate_cost->at(cell->type);
  90
  91                 if (design && design->module(cell->type) && cell->parameters.empty())
  92                 {
  93                         RTLIL::Module *mod = design->module(cell->type);
  94
  95                         if (mod->attributes.count(ID(cost)))
  96                                 return mod->attributes.at(ID(cost)).as_int();
  97
  98                         if (mod_cost_cache.count(mod->name))
  99                                 return mod_cost_cache.at(mod->name);
 100
 101                         int module_cost = 1;
 102                         for (auto c : mod->cells())
 103                                 module_cost += get(c);
 104
 105                         mod_cost_cache[mod->name] = module_cost;
 106                         return module_cost;
 107                 }
 108
 109                 log_warning("Can't determine cost of %s cell (%d parameters).\n", log_id(cell->type), GetSize(cell->parameters));
 110                 return 1;
 111         }
 112 };
 113
 114 YOSYS_NAMESPACE_END
 115
 116 #endif