kernel/cost.h

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
   5  *
   6  *  Permission to use, copy, modify, and/or distribute this software for any
   7  *  purpose with or without fee is hereby granted, provided that the above
   8  *  copyright notice and this permission notice appear in all copies.
   9  *
  10  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  13  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  15  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  16  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  *
  18  */
  19
  20 #ifndef COST_H
  21 #define COST_H
  22
  23 #include "kernel/yosys.h"
  24
  25 YOSYS_NAMESPACE_BEGIN
  26
  27 int get_cell_cost(RTLIL::Cell *cell, dict<RTLIL::IdString, int> *mod_cost_cache = nullptr, bool cmos_cost = false);
  28
  29 inline int get_cell_cost(RTLIL::IdString type, const dict<RTLIL::IdString, RTLIL::Const> &parameters = dict<RTLIL::IdString, RTLIL::Const>(),
  30                 RTLIL::Design *design = nullptr, dict<RTLIL::IdString, int> *mod_cost_cache = nullptr, bool cmos_cost = false)
  31 {
  32         static dict<RTLIL::IdString, int> gate_cost = {
  33                 { "$_BUF_",    1 },
  34                 { "$_NOT_",    2 },
  35                 { "$_AND_",    4 },
  36                 { "$_NAND_",   4 },
  37                 { "$_OR_",     4 },
  38                 { "$_NOR_",    4 },
  39                 { "$_ANDNOT_", 4 },
  40                 { "$_ORNOT_",  4 },
  41                 { "$_XOR_",    8 },
  42                 { "$_XNOR_",   8 },
  43                 { "$_AOI3_",   6 },
  44                 { "$_OAI3_",   6 },
  45                 { "$_AOI4_",   8 },
  46                 { "$_OAI4_",   8 },
  47                 { "$_MUX_",    4 },
  48                 { "$_NMUX_",   4 }
  49         };
  50
  51         // match costs in "stat -tech cmos"
  52         static dict<RTLIL::IdString, int> cmos_gate_cost = {
  53                 { "$_BUF_",     1 },
  54                 { "$_NOT_",     2 },
  55                 { "$_AND_",     6 },
  56                 { "$_NAND_",    4 },
  57                 { "$_OR_",      6 },
  58                 { "$_NOR_",     4 },
  59                 { "$_ANDNOT_",  6 },
  60                 { "$_ORNOT_",   6 },
  61                 { "$_XOR_",    12 },
  62                 { "$_XNOR_",   12 },
  63                 { "$_AOI3_",    6 },
  64                 { "$_OAI3_",    6 },
  65                 { "$_AOI4_",    8 },
  66                 { "$_OAI4_",    8 },
  67                 { "$_MUX_",    12 },
  68                 { "$_NMUX_",   10 }
  69         };
  70
  71         if (cmos_cost && cmos_gate_cost.count(type))
  72                 return cmos_gate_cost.at(type);
  73
  74         if (gate_cost.count(type))
  75                 return gate_cost.at(type);
  76
  77         if (parameters.empty() && design && design->module(type))
  78         {
  79                 RTLIL::Module *mod = design->module(type);
  80
  81                 if (mod->attributes.count("\\cost"))
  82                         return mod->attributes.at("\\cost").as_int();
  83
  84                 dict<RTLIL::IdString, int> local_mod_cost_cache;
  85                 if (mod_cost_cache == nullptr)
  86                         mod_cost_cache = &local_mod_cost_cache;
  87
  88                 if (mod_cost_cache->count(mod->name))
  89                         return mod_cost_cache->at(mod->name);
  90
  91                 int module_cost = 1;
  92                 for (auto c : mod->cells())
  93                         module_cost += get_cell_cost(c, mod_cost_cache);
  94
  95                 (*mod_cost_cache)[mod->name] = module_cost;
  96                 return module_cost;
  97         }
  98
  99         log_warning("Can't determine cost of %s cell (%d parameters).\n", log_id(type), GetSize(parameters));
 100         return 1;
 101 }
 102
 103 inline int get_cell_cost(RTLIL::Cell *cell, dict<RTLIL::IdString, int> *mod_cost_cache, bool cmos_cost)
 104 {
 105         return get_cell_cost(cell->type, cell->parameters, cell->module->design, mod_cost_cache, cmos_cost);
 106 }
 107
 108 YOSYS_NAMESPACE_END
 109
 110 #endif