2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
23 #include "kernel/yosys.h"
27 int get_cell_cost(RTLIL::Cell
*cell
, dict
<RTLIL::IdString
, int> *mod_cost_cache
= nullptr);
29 int get_cell_cost(RTLIL::IdString type
, const dict
<RTLIL::IdString
, RTLIL::Const
> ¶meters
= dict
<RTLIL::IdString
, RTLIL::Const
>(),
30 RTLIL::Design
*design
= nullptr, dict
<RTLIL::IdString
, int> *mod_cost_cache
= nullptr);
32 inline int get_cell_cost(RTLIL::Cell
*cell
, dict
<RTLIL::IdString
, int> *mod_cost_cache
)
34 return get_cell_cost(cell
->type
, cell
->parameters
, cell
->module
->design
, mod_cost_cache
);