2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
23 #include "kernel/yosys.h"
27 int get_cell_cost(RTLIL::Cell
*cell
, dict
<RTLIL::IdString
, int> *mod_cost_cache
= nullptr, bool cmos_cost
= false);
29 inline int get_cell_cost(RTLIL::IdString type
, const dict
<RTLIL::IdString
, RTLIL::Const
> ¶meters
= dict
<RTLIL::IdString
, RTLIL::Const
>(),
30 RTLIL::Design
*design
= nullptr, dict
<RTLIL::IdString
, int> *mod_cost_cache
= nullptr, bool cmos_cost
= false)
32 static dict
<RTLIL::IdString
, int> gate_cost
= {
51 // match costs in "stat -tech cmos"
52 static dict
<RTLIL::IdString
, int> cmos_gate_cost
= {
71 if (cmos_cost
&& cmos_gate_cost
.count(type
))
72 return cmos_gate_cost
.at(type
);
74 if (gate_cost
.count(type
))
75 return gate_cost
.at(type
);
77 if (parameters
.empty() && design
&& design
->module(type
))
79 RTLIL::Module
*mod
= design
->module(type
);
81 if (mod
->attributes
.count("\\cost"))
82 return mod
->attributes
.at("\\cost").as_int();
84 dict
<RTLIL::IdString
, int> local_mod_cost_cache
;
85 if (mod_cost_cache
== nullptr)
86 mod_cost_cache
= &local_mod_cost_cache
;
88 if (mod_cost_cache
->count(mod
->name
))
89 return mod_cost_cache
->at(mod
->name
);
92 for (auto c
: mod
->cells())
93 module_cost
+= get_cell_cost(c
, mod_cost_cache
);
95 (*mod_cost_cache
)[mod
->name
] = module_cost
;
99 log_warning("Can't determine cost of %s cell (%d parameters).\n", log_id(type
), GetSize(parameters
));
103 inline int get_cell_cost(RTLIL::Cell
*cell
, dict
<RTLIL::IdString
, int> *mod_cost_cache
, bool cmos_cost
)
105 return get_cell_cost(cell
->type
, cell
->parameters
, cell
->module
->design
, mod_cost_cache
, cmos_cost
);