kernel/mem.h

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2020  Marcelina Kościelnicka <mwk@0x04.net>
   5  *
   6  *  Permission to use, copy, modify, and/or distribute this software for any
   7  *  purpose with or without fee is hereby granted, provided that the above
   8  *  copyright notice and this permission notice appear in all copies.
   9  *
  10  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  13  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  15  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  16  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  *
  18  */
  19
  20 #ifndef MEM_H
  21 #define MEM_H
  22
  23 #include "kernel/yosys.h"
  24
  25 YOSYS_NAMESPACE_BEGIN
  26
  27 struct MemRd {
  28         dict<IdString, Const> attributes;
  29         Cell *cell;
  30         bool clk_enable, clk_polarity;
  31         bool transparent;
  32         SigSpec clk, en, addr, data;
  33         MemRd() : cell(nullptr) {}
  34 };
  35
  36 struct MemWr {
  37         dict<IdString, Const> attributes;
  38         Cell *cell;
  39         bool clk_enable, clk_polarity;
  40         SigSpec clk, en, addr, data;
  41         MemWr() : cell(nullptr) {}
  42 };
  43
  44 struct MemInit {
  45         dict<IdString, Const> attributes;
  46         Cell *cell;
  47         Const addr;
  48         Const data;
  49         MemInit() : cell(nullptr) {}
  50 };
  51
  52 struct Mem {
  53         Module *module;
  54         IdString memid;
  55         dict<IdString, Const> attributes;
  56         bool packed;
  57         RTLIL::Memory *mem;
  58         Cell *cell;
  59         int width, start_offset, size;
  60         std::vector<MemInit> inits;
  61         std::vector<MemRd> rd_ports;
  62         std::vector<MemWr> wr_ports;
  63
  64         void remove();
  65         void emit();
  66         void remove_wr_port(int idx);
  67         void remove_rd_port(int idx);
  68         void clear_inits();
  69         Const get_init_data() const;
  70         static std::vector<Mem> get_all_memories(Module *module);
  71         static std::vector<Mem> get_selected_memories(Module *module);
  72         Cell *extract_rdff(int idx);
  73         Mem(Module *module, IdString memid, int width, int start_offset, int size) : module(module), memid(memid), packed(false), mem(nullptr), cell(nullptr), width(width), start_offset(start_offset), size(size) {}
  74 };
  75
  76 YOSYS_NAMESPACE_END
  77
  78 #endif