2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2020 Marcelina KoĆcielnicka <mwk@0x04.net>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
23 #include "kernel/yosys.h"
29 dict
<IdString
, Const
> attributes
;
31 bool clk_enable
, clk_polarity
;
33 SigSpec clk
, en
, addr
, data
;
34 MemRd() : removed(false), cell(nullptr) {}
39 dict
<IdString
, Const
> attributes
;
41 bool clk_enable
, clk_polarity
;
42 SigSpec clk
, en
, addr
, data
;
43 MemWr() : removed(false), cell(nullptr) {}
47 dict
<IdString
, Const
> attributes
;
51 MemInit() : cell(nullptr) {}
57 dict
<IdString
, Const
> attributes
;
61 int width
, start_offset
, size
;
62 std::vector
<MemInit
> inits
;
63 std::vector
<MemRd
> rd_ports
;
64 std::vector
<MemWr
> wr_ports
;
70 Const
get_init_data() const;
71 static std::vector
<Mem
> get_all_memories(Module
*module
);
72 static std::vector
<Mem
> get_selected_memories(Module
*module
);
73 Cell
*extract_rdff(int idx
);
74 Mem(Module
*module
, IdString memid
, int width
, int start_offset
, int size
) : module(module
), memid(memid
), packed(false), mem(nullptr), cell(nullptr), width(width
), start_offset(start_offset
), size(size
) {}