kernel/modtools.h

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
   5  *
   6  *  Permission to use, copy, modify, and/or distribute this software for any
   7  *  purpose with or without fee is hereby granted, provided that the above
   8  *  copyright notice and this permission notice appear in all copies.
   9  *
  10  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  13  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  15  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  16  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  *
  18  */
  19
  20 #ifndef MODTOOLS_H
  21 #define MODTOOLS_H
  22
  23 #include "kernel/yosys.h"
  24 #include "kernel/sigtools.h"
  25 #include "kernel/celltypes.h"
  26
  27 YOSYS_NAMESPACE_BEGIN
  28
  29 struct ModIndex : public RTLIL::Monitor
  30 {
  31         struct PortInfo {
  32                 RTLIL::Cell* cell;
  33                 RTLIL::IdString port;
  34                 int offset;
  35
  36                 PortInfo() : cell(), port(), offset() { }
  37                 PortInfo(RTLIL::Cell* _c, RTLIL::IdString _p, int _o) : cell(_c), port(_p), offset(_o) { }
  38
  39                 bool operator<(const PortInfo &other) const {
  40                         if (cell != other.cell)
  41                                 return cell < other.cell;
  42                         if (offset != other.offset)
  43                                 return offset < other.offset;
  44                         return port < other.port;
  45                 }
  46
  47                 bool operator==(const PortInfo &other) const {
  48                         return cell == other.cell && port == other.port && offset == other.offset;
  49                 }
  50
  51                 unsigned int hash() const {
  52                         return mkhash_add(mkhash(cell->name.hash(), port.hash()), offset);
  53                 }
  54         };
  55
  56         struct SigBitInfo
  57         {
  58                 bool is_input, is_output;
  59                 pool<PortInfo> ports;
  60
  61                 SigBitInfo() : is_input(false), is_output(false) { }
  62
  63                 bool operator==(const SigBitInfo &other) const {
  64                         return is_input == other.is_input && is_output == other.is_output && ports == other.ports;
  65                 }
  66
  67                 void merge(const SigBitInfo &other)
  68                 {
  69                         is_input = is_input || other.is_input;
  70                         is_output = is_output || other.is_output;
  71                         ports.insert(other.ports.begin(), other.ports.end());
  72                 }
  73         };
  74
  75         SigMap sigmap;
  76         RTLIL::Module *module;
  77         std::map<RTLIL::SigBit, SigBitInfo> database;
  78         int auto_reload_counter;
  79         bool auto_reload_module;
  80
  81         void port_add(RTLIL::Cell *cell, RTLIL::IdString port, const RTLIL::SigSpec &sig)
  82         {
  83                 for (int i = 0; i < GetSize(sig); i++) {
  84                         RTLIL::SigBit bit = sigmap(sig[i]);
  85                         if (bit.wire)
  86                                 database[bit].ports.insert(PortInfo(cell, port, i));
  87                 }
  88         }
  89
  90         void port_del(RTLIL::Cell *cell, RTLIL::IdString port, const RTLIL::SigSpec &sig)
  91         {
  92                 for (int i = 0; i < GetSize(sig); i++) {
  93                         RTLIL::SigBit bit = sigmap(sig[i]);
  94                         if (bit.wire)
  95                                 database[bit].ports.erase(PortInfo(cell, port, i));
  96                 }
  97         }
  98
  99         const SigBitInfo &info(RTLIL::SigBit bit)
 100         {
 101                 return database[sigmap(bit)];
 102         }
 103
 104         void reload_module(bool reset_sigmap = true)
 105         {
 106                 if (reset_sigmap) {
 107                         sigmap.clear();
 108                         sigmap.set(module);
 109                 }
 110
 111                 database.clear();
 112                 for (auto wire : module->wires())
 113                         if (wire->port_input || wire->port_output)
 114                                 for (int i = 0; i < GetSize(wire); i++) {
 115                                         RTLIL::SigBit bit = sigmap(RTLIL::SigBit(wire, i));
 116                                         if (bit.wire && wire->port_input)
 117                                                 database[bit].is_input = true;
 118                                         if (bit.wire && wire->port_output)
 119                                                 database[bit].is_output = true;
 120                                 }
 121                 for (auto cell : module->cells())
 122                         for (auto &conn : cell->connections())
 123                                 port_add(cell, conn.first, conn.second);
 124
 125                 if (auto_reload_module) {
 126                         if (++auto_reload_counter > 2)
 127                                 log_warning("Auto-reload in ModIndex -- possible performance bug!\n");
 128                         auto_reload_module = false;
 129                 }
 130         }
 131
 132         void check()
 133         {
 134 #ifndef NDEBUG
 135                 if (auto_reload_module)
 136                         return;
 137
 138                 for (auto it : database)
 139                         log_assert(it.first == sigmap(it.first));
 140
 141                 auto database_bak = std::move(database);
 142                 reload_module(false);
 143
 144                 if (!(database == database_bak))
 145                 {
 146                         for (auto &it : database_bak)
 147                                 if (!database.count(it.first))
 148                                         log("ModuleIndex::check(): Only in database_bak, not database: %s\n", log_signal(it.first));
 149
 150                         for (auto &it : database)
 151                                 if (!database_bak.count(it.first))
 152                                         log("ModuleIndex::check(): Only in database, not database_bak: %s\n", log_signal(it.first));
 153                                 else if (!(it.second == database_bak.at(it.first)))
 154                                         log("ModuleIndex::check(): Different content for database[%s].\n", log_signal(it.first));
 155
 156                         log_assert(database == database_bak);
 157                 }
 158 #endif
 159         }
 160
 161         virtual void notify_connect(RTLIL::Cell *cell, const RTLIL::IdString &port, const RTLIL::SigSpec &old_sig, RTLIL::SigSpec &sig) YS_OVERRIDE
 162         {
 163                 log_assert(module == cell->module);
 164
 165                 if (auto_reload_module)
 166                         return;
 167
 168                 port_del(cell, port, old_sig);
 169                 port_add(cell, port, sig);
 170         }
 171
 172         virtual void notify_connect(RTLIL::Module *mod YS_ATTRIBUTE(unused), const RTLIL::SigSig &sigsig) YS_OVERRIDE
 173         {
 174                 log_assert(module == mod);
 175
 176                 if (auto_reload_module)
 177                         return;
 178
 179                 for (int i = 0; i < GetSize(sigsig.first); i++)
 180                 {
 181                         RTLIL::SigBit lhs = sigmap(sigsig.first[i]);
 182                         RTLIL::SigBit rhs = sigmap(sigsig.second[i]);
 183                         bool has_lhs = database.count(lhs);
 184                         bool has_rhs = database.count(rhs);
 185
 186                         if (!has_lhs && !has_rhs) {
 187                                 sigmap.add(lhs, rhs);
 188                         } else
 189                         if (!has_rhs) {
 190                                 SigBitInfo new_info = database.at(lhs);
 191                                 database.erase(lhs);
 192                                 sigmap.add(lhs, rhs);
 193                                 lhs = sigmap(lhs);
 194                                 if (lhs.wire)
 195                                         database[lhs] = new_info;
 196                         } else
 197                         if (!has_lhs) {
 198                                 SigBitInfo new_info = database.at(rhs);
 199                                 database.erase(rhs);
 200                                 sigmap.add(lhs, rhs);
 201                                 rhs = sigmap(rhs);
 202                                 if (rhs.wire)
 203                                         database[rhs] = new_info;
 204                         } else {
 205                                 SigBitInfo new_info = database.at(lhs);
 206                                 new_info.merge(database.at(rhs));
 207                                 database.erase(lhs);
 208                                 database.erase(rhs);
 209                                 sigmap.add(lhs, rhs);
 210                                 rhs = sigmap(rhs);
 211                                 if (rhs.wire)
 212                                         database[rhs] = new_info;
 213                         }
 214                 }
 215         }
 216
 217         virtual void notify_connect(RTLIL::Module *mod YS_ATTRIBUTE(unused), const std::vector<RTLIL::SigSig>&) YS_OVERRIDE
 218         {
 219                 log_assert(module == mod);
 220                 auto_reload_module = true;
 221         }
 222
 223         virtual void notify_blackout(RTLIL::Module *mod YS_ATTRIBUTE(unused)) YS_OVERRIDE
 224         {
 225                 log_assert(module == mod);
 226                 auto_reload_module = true;
 227         }
 228
 229         ModIndex(RTLIL::Module *_m) : module(_m)
 230         {
 231                 auto_reload_counter = 0;
 232                 auto_reload_module = true;
 233                 module->monitors.insert(this);
 234         }
 235
 236         ~ModIndex()
 237         {
 238                 module->monitors.erase(this);
 239         }
 240
 241         SigBitInfo *query(RTLIL::SigBit bit)
 242         {
 243                 if (auto_reload_module)
 244                         reload_module();
 245
 246                 auto it = database.find(sigmap(bit));
 247                 if (it == database.end())
 248                         return nullptr;
 249                 else
 250                         return &it->second;
 251         }
 252
 253         bool query_is_input(RTLIL::SigBit bit)
 254         {
 255                 const SigBitInfo *info = query(bit);
 256                 if (info == nullptr)
 257                         return false;
 258                 return info->is_input;
 259         }
 260
 261         bool query_is_output(RTLIL::SigBit bit)
 262         {
 263                 const SigBitInfo *info = query(bit);
 264                 if (info == nullptr)
 265                         return false;
 266                 return info->is_output;
 267         }
 268
 269         pool<PortInfo> &query_ports(RTLIL::SigBit bit)
 270         {
 271                 static pool<PortInfo> empty_result_set;
 272                 SigBitInfo *info = query(bit);
 273                 if (info == nullptr)
 274                         return empty_result_set;
 275                 return info->ports;
 276         }
 277 };
 278
 279 struct ModWalker
 280 {
 281         struct PortBit
 282         {
 283                 RTLIL::Cell *cell;
 284                 RTLIL::IdString port;
 285                 int offset;
 286
 287                 bool operator<(const PortBit &other) const {
 288                         if (cell != other.cell)
 289                                 return cell < other.cell;
 290                         if (port != other.port)
 291                                 return port < other.port;
 292                         return offset < other.offset;
 293                 }
 294
 295                 bool operator==(const PortBit &other) const {
 296                         return cell == other.cell && port == other.port && offset == other.offset;
 297                 }
 298
 299                 unsigned int hash() const {
 300                         return mkhash_add(mkhash(cell->name.hash(), port.hash()), offset);
 301                 }
 302         };
 303
 304         RTLIL::Design *design;
 305         RTLIL::Module *module;
 306
 307         CellTypes ct;
 308         SigMap sigmap;
 309
 310         dict<RTLIL::SigBit, pool<PortBit>> signal_drivers;
 311         dict<RTLIL::SigBit, pool<PortBit>> signal_consumers;
 312         pool<RTLIL::SigBit> signal_inputs, signal_outputs;
 313
 314         dict<RTLIL::Cell*, pool<RTLIL::SigBit>> cell_outputs, cell_inputs;
 315
 316         void add_wire(RTLIL::Wire *wire)
 317         {
 318                 if (wire->port_input) {
 319                         std::vector<RTLIL::SigBit> bits = sigmap(wire);
 320                         for (auto bit : bits)
 321                                 if (bit.wire != NULL)
 322                                         signal_inputs.insert(bit);
 323                 }
 324
 325                 if (wire->port_output) {
 326                         std::vector<RTLIL::SigBit> bits = sigmap(wire);
 327                         for (auto bit : bits)
 328                                 if (bit.wire != NULL)
 329                                         signal_outputs.insert(bit);
 330                 }
 331         }
 332
 333         void add_cell_port(RTLIL::Cell *cell, RTLIL::IdString port, std::vector<RTLIL::SigBit> bits, bool is_output, bool is_input)
 334         {
 335                 for (int i = 0; i < int(bits.size()); i++)
 336                         if (bits[i].wire != NULL) {
 337                                 PortBit pbit = { cell, port, i };
 338                                 if (is_output) {
 339                                         signal_drivers[bits[i]].insert(pbit);
 340                                         cell_outputs[cell].insert(bits[i]);
 341                                 }
 342                                 if (is_input) {
 343                                         signal_consumers[bits[i]].insert(pbit);
 344                                         cell_inputs[cell].insert(bits[i]);
 345                                 }
 346                         }
 347         }
 348
 349         void add_cell(RTLIL::Cell *cell)
 350         {
 351                 if (ct.cell_known(cell->type)) {
 352                         for (auto &conn : cell->connections())
 353                                 add_cell_port(cell, conn.first, sigmap(conn.second),
 354                                                 ct.cell_output(cell->type, conn.first),
 355                                                 ct.cell_input(cell->type, conn.first));
 356                 } else {
 357                         for (auto &conn : cell->connections())
 358                                 add_cell_port(cell, conn.first, sigmap(conn.second), true, true);
 359                 }
 360         }
 361
 362         ModWalker() : design(NULL), module(NULL)
 363         {
 364         }
 365
 366         ModWalker(RTLIL::Design *design, RTLIL::Module *module, CellTypes *filter_ct = NULL)
 367         {
 368                 setup(design, module, filter_ct);
 369         }
 370
 371         void setup(RTLIL::Design *design, RTLIL::Module *module, CellTypes *filter_ct = NULL)
 372         {
 373                 this->design = design;
 374                 this->module = module;
 375
 376                 ct.clear();
 377                 ct.setup(design);
 378                 sigmap.set(module);
 379
 380                 signal_drivers.clear();
 381                 signal_consumers.clear();
 382                 signal_inputs.clear();
 383                 signal_outputs.clear();
 384
 385                 for (auto &it : module->wires_)
 386                         add_wire(it.second);
 387                 for (auto &it : module->cells_)
 388                         if (filter_ct == NULL || filter_ct->cell_known(it.second->type))
 389                                 add_cell(it.second);
 390         }
 391
 392         // get_* methods -- single RTLIL::SigBit
 393
 394         template<typename T>
 395         inline bool get_drivers(pool<PortBit> &result, RTLIL::SigBit bit) const
 396         {
 397                 bool found = false;
 398                 if (signal_drivers.count(bit)) {
 399                         const pool<PortBit> &r = signal_drivers.at(bit);
 400                         result.insert(r.begin(), r.end());
 401                         found = true;
 402                 }
 403                 return found;
 404         }
 405
 406         template<typename T>
 407         inline bool get_consumers(pool<PortBit> &result, RTLIL::SigBit bit) const
 408         {
 409                 bool found = false;
 410                 if (signal_consumers.count(bit)) {
 411                         const pool<PortBit> &r = signal_consumers.at(bit);
 412                         result.insert(r.begin(), r.end());
 413                         found = true;
 414                 }
 415                 return found;
 416         }
 417
 418         template<typename T>
 419         inline bool get_inputs(pool<RTLIL::SigBit> &result, RTLIL::SigBit bit) const
 420         {
 421                 bool found = false;
 422                 if (signal_inputs.count(bit))
 423                         result.insert(bit), found = true;
 424                 return found;
 425         }
 426
 427         template<typename T>
 428         inline bool get_outputs(pool<RTLIL::SigBit> &result, RTLIL::SigBit bit) const
 429         {
 430                 bool found = false;
 431                 if (signal_outputs.count(bit))
 432                         result.insert(bit), found = true;
 433                 return found;
 434         }
 435
 436         // get_* methods -- container of RTLIL::SigBit's (always by reference)
 437
 438         template<typename T>
 439         inline bool get_drivers(pool<PortBit> &result, const T &bits) const
 440         {
 441                 bool found = false;
 442                 for (RTLIL::SigBit bit : bits)
 443                         if (signal_drivers.count(bit)) {
 444                                 const pool<PortBit> &r = signal_drivers.at(bit);
 445                                 result.insert(r.begin(), r.end());
 446                                 found = true;
 447                         }
 448                 return found;
 449         }
 450
 451         template<typename T>
 452         inline bool get_consumers(pool<PortBit> &result, const T &bits) const
 453         {
 454                 bool found = false;
 455                 for (RTLIL::SigBit bit : bits)
 456                         if (signal_consumers.count(bit)) {
 457                                 const pool<PortBit> &r = signal_consumers.at(bit);
 458                                 result.insert(r.begin(), r.end());
 459                                 found = true;
 460                         }
 461                 return found;
 462         }
 463
 464         template<typename T>
 465         inline bool get_inputs(pool<RTLIL::SigBit> &result, const T &bits) const
 466         {
 467                 bool found = false;
 468                 for (RTLIL::SigBit bit : bits)
 469                         if (signal_inputs.count(bit))
 470                                 result.insert(bit), found = true;
 471                 return found;
 472         }
 473
 474         template<typename T>
 475         inline bool get_outputs(pool<RTLIL::SigBit> &result, const T &bits) const
 476         {
 477                 bool found = false;
 478                 for (RTLIL::SigBit bit : bits)
 479                         if (signal_outputs.count(bit))
 480                                 result.insert(bit), found = true;
 481                 return found;
 482         }
 483
 484         // get_* methods -- call by RTLIL::SigSpec (always by value)
 485
 486         bool get_drivers(pool<PortBit> &result, RTLIL::SigSpec signal) const
 487         {
 488                 std::vector<RTLIL::SigBit> bits = sigmap(signal);
 489                 return get_drivers(result, bits);
 490         }
 491
 492         bool get_consumers(pool<PortBit> &result, RTLIL::SigSpec signal) const
 493         {
 494                 std::vector<RTLIL::SigBit> bits = sigmap(signal);
 495                 return get_consumers(result, bits);
 496         }
 497
 498         bool get_inputs(pool<RTLIL::SigBit> &result, RTLIL::SigSpec signal) const
 499         {
 500                 std::vector<RTLIL::SigBit> bits = sigmap(signal);
 501                 return get_inputs(result, bits);
 502         }
 503
 504         bool get_outputs(pool<RTLIL::SigBit> &result, RTLIL::SigSpec signal) const
 505         {
 506                 std::vector<RTLIL::SigBit> bits = sigmap(signal);
 507                 return get_outputs(result, bits);
 508         }
 509
 510         // has_* methods -- call by reference
 511
 512         template<typename T>
 513         inline bool has_drivers(const T &sig) const {
 514                 pool<PortBit> result;
 515                 return get_drivers(result, sig);
 516         }
 517
 518         template<typename T>
 519         inline bool has_consumers(const T &sig) const {
 520                 pool<PortBit> result;
 521                 return get_consumers(result, sig);
 522         }
 523
 524         template<typename T>
 525         inline bool has_inputs(const T &sig) const {
 526                 pool<RTLIL::SigBit> result;
 527                 return get_inputs(result, sig);
 528         }
 529
 530         template<typename T>
 531         inline bool has_outputs(const T &sig) const {
 532                 pool<RTLIL::SigBit> result;
 533                 return get_outputs(result, sig);
 534         }
 535
 536         // has_* methods -- call by value
 537
 538         inline bool has_drivers(RTLIL::SigSpec sig) const {
 539                 pool<PortBit> result;
 540                 return get_drivers(result, sig);
 541         }
 542
 543         inline bool has_consumers(RTLIL::SigSpec sig) const {
 544                 pool<PortBit> result;
 545                 return get_consumers(result, sig);
 546         }
 547
 548         inline bool has_inputs(RTLIL::SigSpec sig) const {
 549                 pool<RTLIL::SigBit> result;
 550                 return get_inputs(result, sig);
 551         }
 552
 553         inline bool has_outputs(RTLIL::SigSpec sig) const {
 554                 pool<RTLIL::SigBit> result;
 555                 return get_outputs(result, sig);
 556         }
 557 };
 558
 559 YOSYS_NAMESPACE_END
 560
 561 #endif