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ice40: split out cells_map.v into ff_map.v
[yosys.git] / kernel / rtlil.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 #include "kernel/yosys.h"
21 #include "kernel/macc.h"
22 #include "kernel/celltypes.h"
23 #include "frontends/verilog/verilog_frontend.h"
24 #include "frontends/verilog/preproc.h"
25 #include "backends/ilang/ilang_backend.h"
26
27 #include <string.h>
28 #include <algorithm>
29
30 YOSYS_NAMESPACE_BEGIN
31
32 RTLIL::IdString::destruct_guard_t RTLIL::IdString::destruct_guard;
33 std::vector<char*> RTLIL::IdString::global_id_storage_;
34 dict<char*, int, hash_cstr_ops> RTLIL::IdString::global_id_index_;
35 #ifndef YOSYS_NO_IDS_REFCNT
36 std::vector<int> RTLIL::IdString::global_refcount_storage_;
37 std::vector<int> RTLIL::IdString::global_free_idx_list_;
38 #endif
39 #ifdef YOSYS_USE_STICKY_IDS
40 int RTLIL::IdString::last_created_idx_[8];
41 int RTLIL::IdString::last_created_idx_ptr_;
42 #endif
43
44 #define X(_id) IdString RTLIL::ID::_id;
45 #include "kernel/constids.inc"
46 #undef X
47
48 dict<std::string, std::string> RTLIL::constpad;
49
50 const pool<IdString> &RTLIL::builtin_ff_cell_types() {
51 static const pool<IdString> res = {
52 ID($sr),
53 ID($ff),
54 ID($dff),
55 ID($dffe),
56 ID($dffsr),
57 ID($adff),
58 ID($dlatch),
59 ID($dlatchsr),
60 ID($_DFFE_NN_),
61 ID($_DFFE_NP_),
62 ID($_DFFE_PN_),
63 ID($_DFFE_PP_),
64 ID($_DFFSR_NNN_),
65 ID($_DFFSR_NNP_),
66 ID($_DFFSR_NPN_),
67 ID($_DFFSR_NPP_),
68 ID($_DFFSR_PNN_),
69 ID($_DFFSR_PNP_),
70 ID($_DFFSR_PPN_),
71 ID($_DFFSR_PPP_),
72 ID($_DFF_NN0_),
73 ID($_DFF_NN1_),
74 ID($_DFF_NP0_),
75 ID($_DFF_NP1_),
76 ID($_DFF_N_),
77 ID($_DFF_PN0_),
78 ID($_DFF_PN1_),
79 ID($_DFF_PP0_),
80 ID($_DFF_PP1_),
81 ID($_DFF_P_),
82 ID($_DLATCHSR_NNN_),
83 ID($_DLATCHSR_NNP_),
84 ID($_DLATCHSR_NPN_),
85 ID($_DLATCHSR_NPP_),
86 ID($_DLATCHSR_PNN_),
87 ID($_DLATCHSR_PNP_),
88 ID($_DLATCHSR_PPN_),
89 ID($_DLATCHSR_PPP_),
90 ID($_DLATCH_N_),
91 ID($_DLATCH_P_),
92 ID($_FF_),
93 };
94 return res;
95 }
96
97 RTLIL::Const::Const()
98 {
99 flags = RTLIL::CONST_FLAG_NONE;
100 }
101
102 RTLIL::Const::Const(std::string str)
103 {
104 flags = RTLIL::CONST_FLAG_STRING;
105 for (int i = str.size()-1; i >= 0; i--) {
106 unsigned char ch = str[i];
107 for (int j = 0; j < 8; j++) {
108 bits.push_back((ch & 1) != 0 ? State::S1 : State::S0);
109 ch = ch >> 1;
110 }
111 }
112 }
113
114 RTLIL::Const::Const(int val, int width)
115 {
116 flags = RTLIL::CONST_FLAG_NONE;
117 for (int i = 0; i < width; i++) {
118 bits.push_back((val & 1) != 0 ? State::S1 : State::S0);
119 val = val >> 1;
120 }
121 }
122
123 RTLIL::Const::Const(RTLIL::State bit, int width)
124 {
125 flags = RTLIL::CONST_FLAG_NONE;
126 for (int i = 0; i < width; i++)
127 bits.push_back(bit);
128 }
129
130 RTLIL::Const::Const(const std::vector<bool> &bits)
131 {
132 flags = RTLIL::CONST_FLAG_NONE;
133 for (const auto &b : bits)
134 this->bits.emplace_back(b ? State::S1 : State::S0);
135 }
136
137 RTLIL::Const::Const(const RTLIL::Const &c)
138 {
139 flags = c.flags;
140 for (const auto &b : c.bits)
141 this->bits.push_back(b);
142 }
143
144 bool RTLIL::Const::operator <(const RTLIL::Const &other) const
145 {
146 if (bits.size() != other.bits.size())
147 return bits.size() < other.bits.size();
148 for (size_t i = 0; i < bits.size(); i++)
149 if (bits[i] != other.bits[i])
150 return bits[i] < other.bits[i];
151 return false;
152 }
153
154 bool RTLIL::Const::operator ==(const RTLIL::Const &other) const
155 {
156 return bits == other.bits;
157 }
158
159 bool RTLIL::Const::operator !=(const RTLIL::Const &other) const
160 {
161 return bits != other.bits;
162 }
163
164 bool RTLIL::Const::as_bool() const
165 {
166 for (size_t i = 0; i < bits.size(); i++)
167 if (bits[i] == State::S1)
168 return true;
169 return false;
170 }
171
172 int RTLIL::Const::as_int(bool is_signed) const
173 {
174 int32_t ret = 0;
175 for (size_t i = 0; i < bits.size() && i < 32; i++)
176 if (bits[i] == State::S1)
177 ret |= 1 << i;
178 if (is_signed && bits.back() == State::S1)
179 for (size_t i = bits.size(); i < 32; i++)
180 ret |= 1 << i;
181 return ret;
182 }
183
184 std::string RTLIL::Const::as_string() const
185 {
186 std::string ret;
187 ret.reserve(bits.size());
188 for (size_t i = bits.size(); i > 0; i--)
189 switch (bits[i-1]) {
190 case S0: ret += "0"; break;
191 case S1: ret += "1"; break;
192 case Sx: ret += "x"; break;
193 case Sz: ret += "z"; break;
194 case Sa: ret += "-"; break;
195 case Sm: ret += "m"; break;
196 }
197 return ret;
198 }
199
200 RTLIL::Const RTLIL::Const::from_string(const std::string &str)
201 {
202 Const c;
203 c.bits.reserve(str.size());
204 for (auto it = str.rbegin(); it != str.rend(); it++)
205 switch (*it) {
206 case '0': c.bits.push_back(State::S0); break;
207 case '1': c.bits.push_back(State::S1); break;
208 case 'x': c.bits.push_back(State::Sx); break;
209 case 'z': c.bits.push_back(State::Sz); break;
210 case 'm': c.bits.push_back(State::Sm); break;
211 default: c.bits.push_back(State::Sa);
212 }
213 return c;
214 }
215
216 std::string RTLIL::Const::decode_string() const
217 {
218 std::string string;
219 string.reserve(GetSize(bits)/8);
220 for (int i = 0; i < GetSize(bits); i += 8) {
221 char ch = 0;
222 for (int j = 0; j < 8 && i + j < int (bits.size()); j++)
223 if (bits[i + j] == RTLIL::State::S1)
224 ch |= 1 << j;
225 if (ch != 0)
226 string.append({ch});
227 }
228 std::reverse(string.begin(), string.end());
229 return string;
230 }
231
232 bool RTLIL::Const::is_fully_zero() const
233 {
234 cover("kernel.rtlil.const.is_fully_zero");
235
236 for (const auto &bit : bits)
237 if (bit != RTLIL::State::S0)
238 return false;
239
240 return true;
241 }
242
243 bool RTLIL::Const::is_fully_ones() const
244 {
245 cover("kernel.rtlil.const.is_fully_ones");
246
247 for (const auto &bit : bits)
248 if (bit != RTLIL::State::S1)
249 return false;
250
251 return true;
252 }
253
254 bool RTLIL::Const::is_fully_def() const
255 {
256 cover("kernel.rtlil.const.is_fully_def");
257
258 for (const auto &bit : bits)
259 if (bit != RTLIL::State::S0 && bit != RTLIL::State::S1)
260 return false;
261
262 return true;
263 }
264
265 bool RTLIL::Const::is_fully_undef() const
266 {
267 cover("kernel.rtlil.const.is_fully_undef");
268
269 for (const auto &bit : bits)
270 if (bit != RTLIL::State::Sx && bit != RTLIL::State::Sz)
271 return false;
272
273 return true;
274 }
275
276 bool RTLIL::AttrObject::has_attribute(RTLIL::IdString id) const
277 {
278 return attributes.count(id);
279 }
280
281 void RTLIL::AttrObject::set_bool_attribute(RTLIL::IdString id, bool value)
282 {
283 if (value)
284 attributes[id] = RTLIL::Const(1);
285 else
286 attributes.erase(id);
287 }
288
289 bool RTLIL::AttrObject::get_bool_attribute(RTLIL::IdString id) const
290 {
291 const auto it = attributes.find(id);
292 if (it == attributes.end())
293 return false;
294 return it->second.as_bool();
295 }
296
297 void RTLIL::AttrObject::set_string_attribute(RTLIL::IdString id, string value)
298 {
299 if (value.empty())
300 attributes.erase(id);
301 else
302 attributes[id] = value;
303 }
304
305 string RTLIL::AttrObject::get_string_attribute(RTLIL::IdString id) const
306 {
307 std::string value;
308 const auto it = attributes.find(id);
309 if (it != attributes.end())
310 value = it->second.decode_string();
311 return value;
312 }
313
314 void RTLIL::AttrObject::set_strpool_attribute(RTLIL::IdString id, const pool<string> &data)
315 {
316 string attrval;
317 for (const auto &s : data) {
318 if (!attrval.empty())
319 attrval += "|";
320 attrval += s;
321 }
322 attributes[id] = RTLIL::Const(attrval);
323 }
324
325 void RTLIL::AttrObject::add_strpool_attribute(RTLIL::IdString id, const pool<string> &data)
326 {
327 pool<string> union_data = get_strpool_attribute(id);
328 union_data.insert(data.begin(), data.end());
329 if (!union_data.empty())
330 set_strpool_attribute(id, union_data);
331 }
332
333 pool<string> RTLIL::AttrObject::get_strpool_attribute(RTLIL::IdString id) const
334 {
335 pool<string> data;
336 if (attributes.count(id) != 0)
337 for (auto s : split_tokens(attributes.at(id).decode_string(), "|"))
338 data.insert(s);
339 return data;
340 }
341
342 bool RTLIL::Selection::selected_module(RTLIL::IdString mod_name) const
343 {
344 if (full_selection)
345 return true;
346 if (selected_modules.count(mod_name) > 0)
347 return true;
348 if (selected_members.count(mod_name) > 0)
349 return true;
350 return false;
351 }
352
353 bool RTLIL::Selection::selected_whole_module(RTLIL::IdString mod_name) const
354 {
355 if (full_selection)
356 return true;
357 if (selected_modules.count(mod_name) > 0)
358 return true;
359 return false;
360 }
361
362 bool RTLIL::Selection::selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const
363 {
364 if (full_selection)
365 return true;
366 if (selected_modules.count(mod_name) > 0)
367 return true;
368 if (selected_members.count(mod_name) > 0)
369 if (selected_members.at(mod_name).count(memb_name) > 0)
370 return true;
371 return false;
372 }
373
374 void RTLIL::Selection::optimize(RTLIL::Design *design)
375 {
376 if (full_selection) {
377 selected_modules.clear();
378 selected_members.clear();
379 return;
380 }
381
382 std::vector<RTLIL::IdString> del_list, add_list;
383
384 del_list.clear();
385 for (auto mod_name : selected_modules) {
386 if (design->modules_.count(mod_name) == 0)
387 del_list.push_back(mod_name);
388 selected_members.erase(mod_name);
389 }
390 for (auto mod_name : del_list)
391 selected_modules.erase(mod_name);
392
393 del_list.clear();
394 for (auto &it : selected_members)
395 if (design->modules_.count(it.first) == 0)
396 del_list.push_back(it.first);
397 for (auto mod_name : del_list)
398 selected_members.erase(mod_name);
399
400 for (auto &it : selected_members) {
401 del_list.clear();
402 for (auto memb_name : it.second)
403 if (design->modules_[it.first]->count_id(memb_name) == 0)
404 del_list.push_back(memb_name);
405 for (auto memb_name : del_list)
406 it.second.erase(memb_name);
407 }
408
409 del_list.clear();
410 add_list.clear();
411 for (auto &it : selected_members)
412 if (it.second.size() == 0)
413 del_list.push_back(it.first);
414 else if (it.second.size() == design->modules_[it.first]->wires_.size() + design->modules_[it.first]->memories.size() +
415 design->modules_[it.first]->cells_.size() + design->modules_[it.first]->processes.size())
416 add_list.push_back(it.first);
417 for (auto mod_name : del_list)
418 selected_members.erase(mod_name);
419 for (auto mod_name : add_list) {
420 selected_members.erase(mod_name);
421 selected_modules.insert(mod_name);
422 }
423
424 if (selected_modules.size() == design->modules_.size()) {
425 full_selection = true;
426 selected_modules.clear();
427 selected_members.clear();
428 }
429 }
430
431 RTLIL::Design::Design()
432 : verilog_defines (new define_map_t)
433 {
434 static unsigned int hashidx_count = 123456789;
435 hashidx_count = mkhash_xorshift(hashidx_count);
436 hashidx_ = hashidx_count;
437
438 refcount_modules_ = 0;
439 selection_stack.push_back(RTLIL::Selection());
440
441 #ifdef WITH_PYTHON
442 RTLIL::Design::get_all_designs()->insert(std::pair<unsigned int, RTLIL::Design*>(hashidx_, this));
443 #endif
444 }
445
446 RTLIL::Design::~Design()
447 {
448 for (auto it = modules_.begin(); it != modules_.end(); ++it)
449 delete it->second;
450 for (auto n : verilog_packages)
451 delete n;
452 for (auto n : verilog_globals)
453 delete n;
454 #ifdef WITH_PYTHON
455 RTLIL::Design::get_all_designs()->erase(hashidx_);
456 #endif
457 }
458
459 #ifdef WITH_PYTHON
460 static std::map<unsigned int, RTLIL::Design*> all_designs;
461 std::map<unsigned int, RTLIL::Design*> *RTLIL::Design::get_all_designs(void)
462 {
463 return &all_designs;
464 }
465 #endif
466
467 RTLIL::ObjRange<RTLIL::Module*> RTLIL::Design::modules()
468 {
469 return RTLIL::ObjRange<RTLIL::Module*>(&modules_, &refcount_modules_);
470 }
471
472 RTLIL::Module *RTLIL::Design::module(RTLIL::IdString name)
473 {
474 return modules_.count(name) ? modules_.at(name) : NULL;
475 }
476
477 RTLIL::Module *RTLIL::Design::top_module()
478 {
479 RTLIL::Module *module = nullptr;
480 int module_count = 0;
481
482 for (auto mod : selected_modules()) {
483 if (mod->get_bool_attribute(ID::top))
484 return mod;
485 module_count++;
486 module = mod;
487 }
488
489 return module_count == 1 ? module : nullptr;
490 }
491
492 void RTLIL::Design::add(RTLIL::Module *module)
493 {
494 log_assert(modules_.count(module->name) == 0);
495 log_assert(refcount_modules_ == 0);
496 modules_[module->name] = module;
497 module->design = this;
498
499 for (auto mon : monitors)
500 mon->notify_module_add(module);
501
502 if (yosys_xtrace) {
503 log("#X# New Module: %s\n", log_id(module));
504 log_backtrace("-X- ", yosys_xtrace-1);
505 }
506 }
507
508 RTLIL::Module *RTLIL::Design::addModule(RTLIL::IdString name)
509 {
510 log_assert(modules_.count(name) == 0);
511 log_assert(refcount_modules_ == 0);
512
513 RTLIL::Module *module = new RTLIL::Module;
514 modules_[name] = module;
515 module->design = this;
516 module->name = name;
517
518 for (auto mon : monitors)
519 mon->notify_module_add(module);
520
521 if (yosys_xtrace) {
522 log("#X# New Module: %s\n", log_id(module));
523 log_backtrace("-X- ", yosys_xtrace-1);
524 }
525
526 return module;
527 }
528
529 void RTLIL::Design::scratchpad_unset(const std::string &varname)
530 {
531 scratchpad.erase(varname);
532 }
533
534 void RTLIL::Design::scratchpad_set_int(const std::string &varname, int value)
535 {
536 scratchpad[varname] = stringf("%d", value);
537 }
538
539 void RTLIL::Design::scratchpad_set_bool(const std::string &varname, bool value)
540 {
541 scratchpad[varname] = value ? "true" : "false";
542 }
543
544 void RTLIL::Design::scratchpad_set_string(const std::string &varname, std::string value)
545 {
546 scratchpad[varname] = std::move(value);
547 }
548
549 int RTLIL::Design::scratchpad_get_int(const std::string &varname, int default_value) const
550 {
551 auto it = scratchpad.find(varname);
552 if (it == scratchpad.end())
553 return default_value;
554
555 const std::string &str = it->second;
556
557 if (str == "0" || str == "false")
558 return 0;
559
560 if (str == "1" || str == "true")
561 return 1;
562
563 char *endptr = nullptr;
564 long int parsed_value = strtol(str.c_str(), &endptr, 10);
565 return *endptr ? default_value : parsed_value;
566 }
567
568 bool RTLIL::Design::scratchpad_get_bool(const std::string &varname, bool default_value) const
569 {
570 auto it = scratchpad.find(varname);
571 if (it == scratchpad.end())
572 return default_value;
573
574 const std::string &str = it->second;
575
576 if (str == "0" || str == "false")
577 return false;
578
579 if (str == "1" || str == "true")
580 return true;
581
582 return default_value;
583 }
584
585 std::string RTLIL::Design::scratchpad_get_string(const std::string &varname, const std::string &default_value) const
586 {
587 auto it = scratchpad.find(varname);
588 if (it == scratchpad.end())
589 return default_value;
590
591 return it->second;
592 }
593
594 void RTLIL::Design::remove(RTLIL::Module *module)
595 {
596 for (auto mon : monitors)
597 mon->notify_module_del(module);
598
599 if (yosys_xtrace) {
600 log("#X# Remove Module: %s\n", log_id(module));
601 log_backtrace("-X- ", yosys_xtrace-1);
602 }
603
604 log_assert(modules_.at(module->name) == module);
605 log_assert(refcount_modules_ == 0);
606 modules_.erase(module->name);
607 delete module;
608 }
609
610 void RTLIL::Design::rename(RTLIL::Module *module, RTLIL::IdString new_name)
611 {
612 modules_.erase(module->name);
613 module->name = new_name;
614 add(module);
615 }
616
617 void RTLIL::Design::sort()
618 {
619 scratchpad.sort();
620 modules_.sort(sort_by_id_str());
621 for (auto &it : modules_)
622 it.second->sort();
623 }
624
625 void RTLIL::Design::check()
626 {
627 #ifndef NDEBUG
628 for (auto &it : modules_) {
629 log_assert(this == it.second->design);
630 log_assert(it.first == it.second->name);
631 log_assert(!it.first.empty());
632 it.second->check();
633 }
634 #endif
635 }
636
637 void RTLIL::Design::optimize()
638 {
639 for (auto &it : modules_)
640 it.second->optimize();
641 for (auto &it : selection_stack)
642 it.optimize(this);
643 for (auto &it : selection_vars)
644 it.second.optimize(this);
645 }
646
647 bool RTLIL::Design::selected_module(RTLIL::IdString mod_name) const
648 {
649 if (!selected_active_module.empty() && mod_name != selected_active_module)
650 return false;
651 if (selection_stack.size() == 0)
652 return true;
653 return selection_stack.back().selected_module(mod_name);
654 }
655
656 bool RTLIL::Design::selected_whole_module(RTLIL::IdString mod_name) const
657 {
658 if (!selected_active_module.empty() && mod_name != selected_active_module)
659 return false;
660 if (selection_stack.size() == 0)
661 return true;
662 return selection_stack.back().selected_whole_module(mod_name);
663 }
664
665 bool RTLIL::Design::selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const
666 {
667 if (!selected_active_module.empty() && mod_name != selected_active_module)
668 return false;
669 if (selection_stack.size() == 0)
670 return true;
671 return selection_stack.back().selected_member(mod_name, memb_name);
672 }
673
674 bool RTLIL::Design::selected_module(RTLIL::Module *mod) const
675 {
676 return selected_module(mod->name);
677 }
678
679 bool RTLIL::Design::selected_whole_module(RTLIL::Module *mod) const
680 {
681 return selected_whole_module(mod->name);
682 }
683
684 std::vector<RTLIL::Module*> RTLIL::Design::selected_modules() const
685 {
686 std::vector<RTLIL::Module*> result;
687 result.reserve(modules_.size());
688 for (auto &it : modules_)
689 if (selected_module(it.first) && !it.second->get_blackbox_attribute())
690 result.push_back(it.second);
691 return result;
692 }
693
694 std::vector<RTLIL::Module*> RTLIL::Design::selected_whole_modules() const
695 {
696 std::vector<RTLIL::Module*> result;
697 result.reserve(modules_.size());
698 for (auto &it : modules_)
699 if (selected_whole_module(it.first) && !it.second->get_blackbox_attribute())
700 result.push_back(it.second);
701 return result;
702 }
703
704 std::vector<RTLIL::Module*> RTLIL::Design::selected_whole_modules_warn() const
705 {
706 std::vector<RTLIL::Module*> result;
707 result.reserve(modules_.size());
708 for (auto &it : modules_)
709 if (it.second->get_blackbox_attribute())
710 continue;
711 else if (selected_whole_module(it.first))
712 result.push_back(it.second);
713 else if (selected_module(it.first))
714 log_warning("Ignoring partially selected module %s.\n", log_id(it.first));
715 return result;
716 }
717
718 RTLIL::Module::Module()
719 {
720 static unsigned int hashidx_count = 123456789;
721 hashidx_count = mkhash_xorshift(hashidx_count);
722 hashidx_ = hashidx_count;
723
724 design = nullptr;
725 refcount_wires_ = 0;
726 refcount_cells_ = 0;
727
728 #ifdef WITH_PYTHON
729 RTLIL::Module::get_all_modules()->insert(std::pair<unsigned int, RTLIL::Module*>(hashidx_, this));
730 #endif
731 }
732
733 RTLIL::Module::~Module()
734 {
735 for (auto it = wires_.begin(); it != wires_.end(); ++it)
736 delete it->second;
737 for (auto it = memories.begin(); it != memories.end(); ++it)
738 delete it->second;
739 for (auto it = cells_.begin(); it != cells_.end(); ++it)
740 delete it->second;
741 for (auto it = processes.begin(); it != processes.end(); ++it)
742 delete it->second;
743 #ifdef WITH_PYTHON
744 RTLIL::Module::get_all_modules()->erase(hashidx_);
745 #endif
746 }
747
748 #ifdef WITH_PYTHON
749 static std::map<unsigned int, RTLIL::Module*> all_modules;
750 std::map<unsigned int, RTLIL::Module*> *RTLIL::Module::get_all_modules(void)
751 {
752 return &all_modules;
753 }
754 #endif
755
756 void RTLIL::Module::makeblackbox()
757 {
758 pool<RTLIL::Wire*> delwires;
759
760 for (auto it = wires_.begin(); it != wires_.end(); ++it)
761 if (!it->second->port_input && !it->second->port_output)
762 delwires.insert(it->second);
763
764 for (auto it = memories.begin(); it != memories.end(); ++it)
765 delete it->second;
766 memories.clear();
767
768 for (auto it = cells_.begin(); it != cells_.end(); ++it)
769 delete it->second;
770 cells_.clear();
771
772 for (auto it = processes.begin(); it != processes.end(); ++it)
773 delete it->second;
774 processes.clear();
775
776 connections_.clear();
777
778 remove(delwires);
779 set_bool_attribute(ID::blackbox);
780 }
781
782 void RTLIL::Module::reprocess_module(RTLIL::Design *, const dict<RTLIL::IdString, RTLIL::Module *> &)
783 {
784 log_error("Cannot reprocess_module module `%s' !\n", id2cstr(name));
785 }
786
787 RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, const dict<RTLIL::IdString, RTLIL::Const> &, bool mayfail)
788 {
789 if (mayfail)
790 return RTLIL::IdString();
791 log_error("Module `%s' is used with parameters but is not parametric!\n", id2cstr(name));
792 }
793
794
795 RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, const dict<RTLIL::IdString, RTLIL::Const> &, const dict<RTLIL::IdString, RTLIL::Module*> &, const dict<RTLIL::IdString, RTLIL::IdString> &, bool mayfail)
796 {
797 if (mayfail)
798 return RTLIL::IdString();
799 log_error("Module `%s' is used with parameters but is not parametric!\n", id2cstr(name));
800 }
801
802 size_t RTLIL::Module::count_id(RTLIL::IdString id)
803 {
804 return wires_.count(id) + memories.count(id) + cells_.count(id) + processes.count(id);
805 }
806
807 #ifndef NDEBUG
808 namespace {
809 struct InternalCellChecker
810 {
811 RTLIL::Module *module;
812 RTLIL::Cell *cell;
813 pool<RTLIL::IdString> expected_params, expected_ports;
814
815 InternalCellChecker(RTLIL::Module *module, RTLIL::Cell *cell) : module(module), cell(cell) { }
816
817 void error(int linenr)
818 {
819 std::stringstream buf;
820 ILANG_BACKEND::dump_cell(buf, " ", cell);
821
822 log_error("Found error in internal cell %s%s%s (%s) at %s:%d:\n%s",
823 module ? module->name.c_str() : "", module ? "." : "",
824 cell->name.c_str(), cell->type.c_str(), __FILE__, linenr, buf.str().c_str());
825 }
826
827 int param(RTLIL::IdString name)
828 {
829 auto it = cell->parameters.find(name);
830 if (it == cell->parameters.end())
831 error(__LINE__);
832 expected_params.insert(name);
833 return it->second.as_int();
834 }
835
836 int param_bool(RTLIL::IdString name)
837 {
838 int v = param(name);
839 if (GetSize(cell->parameters.at(name)) > 32)
840 error(__LINE__);
841 if (v != 0 && v != 1)
842 error(__LINE__);
843 return v;
844 }
845
846 int param_bool(RTLIL::IdString name, bool expected)
847 {
848 int v = param_bool(name);
849 if (v != expected)
850 error(__LINE__);
851 return v;
852 }
853
854 void param_bits(RTLIL::IdString name, int width)
855 {
856 param(name);
857 if (GetSize(cell->parameters.at(name).bits) != width)
858 error(__LINE__);
859 }
860
861 void port(RTLIL::IdString name, int width)
862 {
863 auto it = cell->connections_.find(name);
864 if (it == cell->connections_.end())
865 error(__LINE__);
866 if (GetSize(it->second) != width)
867 error(__LINE__);
868 expected_ports.insert(name);
869 }
870
871 void check_expected(bool check_matched_sign = false)
872 {
873 for (auto &para : cell->parameters)
874 if (expected_params.count(para.first) == 0)
875 error(__LINE__);
876 for (auto &conn : cell->connections())
877 if (expected_ports.count(conn.first) == 0)
878 error(__LINE__);
879
880 if (check_matched_sign) {
881 log_assert(expected_params.count(ID::A_SIGNED) != 0 && expected_params.count(ID::B_SIGNED) != 0);
882 bool a_is_signed = cell->parameters.at(ID::A_SIGNED).as_bool();
883 bool b_is_signed = cell->parameters.at(ID::B_SIGNED).as_bool();
884 if (a_is_signed != b_is_signed)
885 error(__LINE__);
886 }
887 }
888
889 void check()
890 {
891 if (!cell->type.begins_with("$") || cell->type.begins_with("$__") || cell->type.begins_with("$paramod") || cell->type.begins_with("$fmcombine") ||
892 cell->type.begins_with("$verific$") || cell->type.begins_with("$array:") || cell->type.begins_with("$extern:"))
893 return;
894
895 if (cell->type.in(ID($not), ID($pos), ID($neg))) {
896 param_bool(ID::A_SIGNED);
897 port(ID::A, param(ID::A_WIDTH));
898 port(ID::Y, param(ID::Y_WIDTH));
899 check_expected();
900 return;
901 }
902
903 if (cell->type.in(ID($and), ID($or), ID($xor), ID($xnor))) {
904 param_bool(ID::A_SIGNED);
905 param_bool(ID::B_SIGNED);
906 port(ID::A, param(ID::A_WIDTH));
907 port(ID::B, param(ID::B_WIDTH));
908 port(ID::Y, param(ID::Y_WIDTH));
909 check_expected(true);
910 return;
911 }
912
913 if (cell->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor), ID($reduce_bool))) {
914 param_bool(ID::A_SIGNED);
915 port(ID::A, param(ID::A_WIDTH));
916 port(ID::Y, param(ID::Y_WIDTH));
917 check_expected();
918 return;
919 }
920
921 if (cell->type.in(ID($shl), ID($shr), ID($sshl), ID($sshr))) {
922 param_bool(ID::A_SIGNED);
923 param_bool(ID::B_SIGNED, /*expected=*/false);
924 port(ID::A, param(ID::A_WIDTH));
925 port(ID::B, param(ID::B_WIDTH));
926 port(ID::Y, param(ID::Y_WIDTH));
927 check_expected(/*check_matched_sign=*/false);
928 return;
929 }
930
931 if (cell->type.in(ID($shift), ID($shiftx))) {
932 param_bool(ID::A_SIGNED);
933 param_bool(ID::B_SIGNED);
934 port(ID::A, param(ID::A_WIDTH));
935 port(ID::B, param(ID::B_WIDTH));
936 port(ID::Y, param(ID::Y_WIDTH));
937 check_expected(/*check_matched_sign=*/false);
938 return;
939 }
940
941 if (cell->type.in(ID($lt), ID($le), ID($eq), ID($ne), ID($eqx), ID($nex), ID($ge), ID($gt))) {
942 param_bool(ID::A_SIGNED);
943 param_bool(ID::B_SIGNED);
944 port(ID::A, param(ID::A_WIDTH));
945 port(ID::B, param(ID::B_WIDTH));
946 port(ID::Y, param(ID::Y_WIDTH));
947 check_expected(true);
948 return;
949 }
950
951 if (cell->type.in(ID($add), ID($sub), ID($mul), ID($div), ID($mod), ID($pow))) {
952 param_bool(ID::A_SIGNED);
953 param_bool(ID::B_SIGNED);
954 port(ID::A, param(ID::A_WIDTH));
955 port(ID::B, param(ID::B_WIDTH));
956 port(ID::Y, param(ID::Y_WIDTH));
957 check_expected(cell->type != ID($pow));
958 return;
959 }
960
961 if (cell->type == ID($fa)) {
962 port(ID::A, param(ID::WIDTH));
963 port(ID::B, param(ID::WIDTH));
964 port(ID::C, param(ID::WIDTH));
965 port(ID::X, param(ID::WIDTH));
966 port(ID::Y, param(ID::WIDTH));
967 check_expected();
968 return;
969 }
970
971 if (cell->type == ID($lcu)) {
972 port(ID::P, param(ID::WIDTH));
973 port(ID::G, param(ID::WIDTH));
974 port(ID::CI, 1);
975 port(ID::CO, param(ID::WIDTH));
976 check_expected();
977 return;
978 }
979
980 if (cell->type == ID($alu)) {
981 param_bool(ID::A_SIGNED);
982 param_bool(ID::B_SIGNED);
983 port(ID::A, param(ID::A_WIDTH));
984 port(ID::B, param(ID::B_WIDTH));
985 port(ID::CI, 1);
986 port(ID::BI, 1);
987 port(ID::X, param(ID::Y_WIDTH));
988 port(ID::Y, param(ID::Y_WIDTH));
989 port(ID::CO, param(ID::Y_WIDTH));
990 check_expected(true);
991 return;
992 }
993
994 if (cell->type == ID($macc)) {
995 param(ID::CONFIG);
996 param(ID::CONFIG_WIDTH);
997 port(ID::A, param(ID::A_WIDTH));
998 port(ID::B, param(ID::B_WIDTH));
999 port(ID::Y, param(ID::Y_WIDTH));
1000 check_expected();
1001 Macc().from_cell(cell);
1002 return;
1003 }
1004
1005 if (cell->type == ID($logic_not)) {
1006 param_bool(ID::A_SIGNED);
1007 port(ID::A, param(ID::A_WIDTH));
1008 port(ID::Y, param(ID::Y_WIDTH));
1009 check_expected();
1010 return;
1011 }
1012
1013 if (cell->type.in(ID($logic_and), ID($logic_or))) {
1014 param_bool(ID::A_SIGNED);
1015 param_bool(ID::B_SIGNED);
1016 port(ID::A, param(ID::A_WIDTH));
1017 port(ID::B, param(ID::B_WIDTH));
1018 port(ID::Y, param(ID::Y_WIDTH));
1019 check_expected(/*check_matched_sign=*/false);
1020 return;
1021 }
1022
1023 if (cell->type == ID($slice)) {
1024 param(ID::OFFSET);
1025 port(ID::A, param(ID::A_WIDTH));
1026 port(ID::Y, param(ID::Y_WIDTH));
1027 if (param(ID::OFFSET) + param(ID::Y_WIDTH) > param(ID::A_WIDTH))
1028 error(__LINE__);
1029 check_expected();
1030 return;
1031 }
1032
1033 if (cell->type == ID($concat)) {
1034 port(ID::A, param(ID::A_WIDTH));
1035 port(ID::B, param(ID::B_WIDTH));
1036 port(ID::Y, param(ID::A_WIDTH) + param(ID::B_WIDTH));
1037 check_expected();
1038 return;
1039 }
1040
1041 if (cell->type == ID($mux)) {
1042 port(ID::A, param(ID::WIDTH));
1043 port(ID::B, param(ID::WIDTH));
1044 port(ID::S, 1);
1045 port(ID::Y, param(ID::WIDTH));
1046 check_expected();
1047 return;
1048 }
1049
1050 if (cell->type == ID($pmux)) {
1051 port(ID::A, param(ID::WIDTH));
1052 port(ID::B, param(ID::WIDTH) * param(ID::S_WIDTH));
1053 port(ID::S, param(ID::S_WIDTH));
1054 port(ID::Y, param(ID::WIDTH));
1055 check_expected();
1056 return;
1057 }
1058
1059 if (cell->type == ID($lut)) {
1060 param(ID::LUT);
1061 port(ID::A, param(ID::WIDTH));
1062 port(ID::Y, 1);
1063 check_expected();
1064 return;
1065 }
1066
1067 if (cell->type == ID($sop)) {
1068 param(ID::DEPTH);
1069 param(ID::TABLE);
1070 port(ID::A, param(ID::WIDTH));
1071 port(ID::Y, 1);
1072 check_expected();
1073 return;
1074 }
1075
1076 if (cell->type == ID($sr)) {
1077 param_bool(ID::SET_POLARITY);
1078 param_bool(ID::CLR_POLARITY);
1079 port(ID::SET, param(ID::WIDTH));
1080 port(ID::CLR, param(ID::WIDTH));
1081 port(ID::Q, param(ID::WIDTH));
1082 check_expected();
1083 return;
1084 }
1085
1086 if (cell->type == ID($ff)) {
1087 port(ID::D, param(ID::WIDTH));
1088 port(ID::Q, param(ID::WIDTH));
1089 check_expected();
1090 return;
1091 }
1092
1093 if (cell->type == ID($dff)) {
1094 param_bool(ID::CLK_POLARITY);
1095 port(ID::CLK, 1);
1096 port(ID::D, param(ID::WIDTH));
1097 port(ID::Q, param(ID::WIDTH));
1098 check_expected();
1099 return;
1100 }
1101
1102 if (cell->type == ID($dffe)) {
1103 param_bool(ID::CLK_POLARITY);
1104 param_bool(ID::EN_POLARITY);
1105 port(ID::CLK, 1);
1106 port(ID::EN, 1);
1107 port(ID::D, param(ID::WIDTH));
1108 port(ID::Q, param(ID::WIDTH));
1109 check_expected();
1110 return;
1111 }
1112
1113 if (cell->type == ID($dffsr)) {
1114 param_bool(ID::CLK_POLARITY);
1115 param_bool(ID::SET_POLARITY);
1116 param_bool(ID::CLR_POLARITY);
1117 port(ID::CLK, 1);
1118 port(ID::SET, param(ID::WIDTH));
1119 port(ID::CLR, param(ID::WIDTH));
1120 port(ID::D, param(ID::WIDTH));
1121 port(ID::Q, param(ID::WIDTH));
1122 check_expected();
1123 return;
1124 }
1125
1126 if (cell->type == ID($adff)) {
1127 param_bool(ID::CLK_POLARITY);
1128 param_bool(ID::ARST_POLARITY);
1129 param_bits(ID::ARST_VALUE, param(ID::WIDTH));
1130 port(ID::CLK, 1);
1131 port(ID::ARST, 1);
1132 port(ID::D, param(ID::WIDTH));
1133 port(ID::Q, param(ID::WIDTH));
1134 check_expected();
1135 return;
1136 }
1137
1138 if (cell->type == ID($dlatch)) {
1139 param_bool(ID::EN_POLARITY);
1140 port(ID::EN, 1);
1141 port(ID::D, param(ID::WIDTH));
1142 port(ID::Q, param(ID::WIDTH));
1143 check_expected();
1144 return;
1145 }
1146
1147 if (cell->type == ID($dlatchsr)) {
1148 param_bool(ID::EN_POLARITY);
1149 param_bool(ID::SET_POLARITY);
1150 param_bool(ID::CLR_POLARITY);
1151 port(ID::EN, 1);
1152 port(ID::SET, param(ID::WIDTH));
1153 port(ID::CLR, param(ID::WIDTH));
1154 port(ID::D, param(ID::WIDTH));
1155 port(ID::Q, param(ID::WIDTH));
1156 check_expected();
1157 return;
1158 }
1159
1160 if (cell->type == ID($fsm)) {
1161 param(ID::NAME);
1162 param_bool(ID::CLK_POLARITY);
1163 param_bool(ID::ARST_POLARITY);
1164 param(ID::STATE_BITS);
1165 param(ID::STATE_NUM);
1166 param(ID::STATE_NUM_LOG2);
1167 param(ID::STATE_RST);
1168 param_bits(ID::STATE_TABLE, param(ID::STATE_BITS) * param(ID::STATE_NUM));
1169 param(ID::TRANS_NUM);
1170 param_bits(ID::TRANS_TABLE, param(ID::TRANS_NUM) * (2*param(ID::STATE_NUM_LOG2) + param(ID::CTRL_IN_WIDTH) + param(ID::CTRL_OUT_WIDTH)));
1171 port(ID::CLK, 1);
1172 port(ID::ARST, 1);
1173 port(ID::CTRL_IN, param(ID::CTRL_IN_WIDTH));
1174 port(ID::CTRL_OUT, param(ID::CTRL_OUT_WIDTH));
1175 check_expected();
1176 return;
1177 }
1178
1179 if (cell->type == ID($memrd)) {
1180 param(ID::MEMID);
1181 param_bool(ID::CLK_ENABLE);
1182 param_bool(ID::CLK_POLARITY);
1183 param_bool(ID::TRANSPARENT);
1184 port(ID::CLK, 1);
1185 port(ID::EN, 1);
1186 port(ID::ADDR, param(ID::ABITS));
1187 port(ID::DATA, param(ID::WIDTH));
1188 check_expected();
1189 return;
1190 }
1191
1192 if (cell->type == ID($memwr)) {
1193 param(ID::MEMID);
1194 param_bool(ID::CLK_ENABLE);
1195 param_bool(ID::CLK_POLARITY);
1196 param(ID::PRIORITY);
1197 port(ID::CLK, 1);
1198 port(ID::EN, param(ID::WIDTH));
1199 port(ID::ADDR, param(ID::ABITS));
1200 port(ID::DATA, param(ID::WIDTH));
1201 check_expected();
1202 return;
1203 }
1204
1205 if (cell->type == ID($meminit)) {
1206 param(ID::MEMID);
1207 param(ID::PRIORITY);
1208 port(ID::ADDR, param(ID::ABITS));
1209 port(ID::DATA, param(ID::WIDTH) * param(ID::WORDS));
1210 check_expected();
1211 return;
1212 }
1213
1214 if (cell->type == ID($mem)) {
1215 param(ID::MEMID);
1216 param(ID::SIZE);
1217 param(ID::OFFSET);
1218 param(ID::INIT);
1219 param_bits(ID::RD_CLK_ENABLE, max(1, param(ID::RD_PORTS)));
1220 param_bits(ID::RD_CLK_POLARITY, max(1, param(ID::RD_PORTS)));
1221 param_bits(ID::RD_TRANSPARENT, max(1, param(ID::RD_PORTS)));
1222 param_bits(ID::WR_CLK_ENABLE, max(1, param(ID::WR_PORTS)));
1223 param_bits(ID::WR_CLK_POLARITY, max(1, param(ID::WR_PORTS)));
1224 port(ID::RD_CLK, param(ID::RD_PORTS));
1225 port(ID::RD_EN, param(ID::RD_PORTS));
1226 port(ID::RD_ADDR, param(ID::RD_PORTS) * param(ID::ABITS));
1227 port(ID::RD_DATA, param(ID::RD_PORTS) * param(ID::WIDTH));
1228 port(ID::WR_CLK, param(ID::WR_PORTS));
1229 port(ID::WR_EN, param(ID::WR_PORTS) * param(ID::WIDTH));
1230 port(ID::WR_ADDR, param(ID::WR_PORTS) * param(ID::ABITS));
1231 port(ID::WR_DATA, param(ID::WR_PORTS) * param(ID::WIDTH));
1232 check_expected();
1233 return;
1234 }
1235
1236 if (cell->type == ID($tribuf)) {
1237 port(ID::A, param(ID::WIDTH));
1238 port(ID::Y, param(ID::WIDTH));
1239 port(ID::EN, 1);
1240 check_expected();
1241 return;
1242 }
1243
1244 if (cell->type.in(ID($assert), ID($assume), ID($live), ID($fair), ID($cover))) {
1245 port(ID::A, 1);
1246 port(ID::EN, 1);
1247 check_expected();
1248 return;
1249 }
1250
1251 if (cell->type == ID($initstate)) {
1252 port(ID::Y, 1);
1253 check_expected();
1254 return;
1255 }
1256
1257 if (cell->type.in(ID($anyconst), ID($anyseq), ID($allconst), ID($allseq))) {
1258 port(ID::Y, param(ID::WIDTH));
1259 check_expected();
1260 return;
1261 }
1262
1263 if (cell->type == ID($equiv)) {
1264 port(ID::A, 1);
1265 port(ID::B, 1);
1266 port(ID::Y, 1);
1267 check_expected();
1268 return;
1269 }
1270
1271 if (cell->type.in(ID($specify2), ID($specify3))) {
1272 param_bool(ID::FULL);
1273 param_bool(ID::SRC_DST_PEN);
1274 param_bool(ID::SRC_DST_POL);
1275 param(ID::T_RISE_MIN);
1276 param(ID::T_RISE_TYP);
1277 param(ID::T_RISE_MAX);
1278 param(ID::T_FALL_MIN);
1279 param(ID::T_FALL_TYP);
1280 param(ID::T_FALL_MAX);
1281 port(ID::EN, 1);
1282 port(ID::SRC, param(ID::SRC_WIDTH));
1283 port(ID::DST, param(ID::DST_WIDTH));
1284 if (cell->type == ID($specify3)) {
1285 param_bool(ID::EDGE_EN);
1286 param_bool(ID::EDGE_POL);
1287 param_bool(ID::DAT_DST_PEN);
1288 param_bool(ID::DAT_DST_POL);
1289 port(ID::DAT, param(ID::DST_WIDTH));
1290 }
1291 check_expected();
1292 return;
1293 }
1294
1295 if (cell->type == ID($specrule)) {
1296 param(ID::TYPE);
1297 param_bool(ID::SRC_PEN);
1298 param_bool(ID::SRC_POL);
1299 param_bool(ID::DST_PEN);
1300 param_bool(ID::DST_POL);
1301 param(ID::T_LIMIT_MIN);
1302 param(ID::T_LIMIT_TYP);
1303 param(ID::T_LIMIT_MAX);
1304 param(ID::T_LIMIT2_MIN);
1305 param(ID::T_LIMIT2_TYP);
1306 param(ID::T_LIMIT2_MAX);
1307 port(ID::SRC_EN, 1);
1308 port(ID::DST_EN, 1);
1309 port(ID::SRC, param(ID::SRC_WIDTH));
1310 port(ID::DST, param(ID::DST_WIDTH));
1311 check_expected();
1312 return;
1313 }
1314
1315 if (cell->type == ID($_BUF_)) { port(ID::A,1); port(ID::Y,1); check_expected(); return; }
1316 if (cell->type == ID($_NOT_)) { port(ID::A,1); port(ID::Y,1); check_expected(); return; }
1317 if (cell->type == ID($_AND_)) { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; }
1318 if (cell->type == ID($_NAND_)) { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; }
1319 if (cell->type == ID($_OR_)) { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; }
1320 if (cell->type == ID($_NOR_)) { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; }
1321 if (cell->type == ID($_XOR_)) { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; }
1322 if (cell->type == ID($_XNOR_)) { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; }
1323 if (cell->type == ID($_ANDNOT_)) { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; }
1324 if (cell->type == ID($_ORNOT_)) { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; }
1325 if (cell->type == ID($_MUX_)) { port(ID::A,1); port(ID::B,1); port(ID::S,1); port(ID::Y,1); check_expected(); return; }
1326 if (cell->type == ID($_NMUX_)) { port(ID::A,1); port(ID::B,1); port(ID::S,1); port(ID::Y,1); check_expected(); return; }
1327 if (cell->type == ID($_AOI3_)) { port(ID::A,1); port(ID::B,1); port(ID::C,1); port(ID::Y,1); check_expected(); return; }
1328 if (cell->type == ID($_OAI3_)) { port(ID::A,1); port(ID::B,1); port(ID::C,1); port(ID::Y,1); check_expected(); return; }
1329 if (cell->type == ID($_AOI4_)) { port(ID::A,1); port(ID::B,1); port(ID::C,1); port(ID::D,1); port(ID::Y,1); check_expected(); return; }
1330 if (cell->type == ID($_OAI4_)) { port(ID::A,1); port(ID::B,1); port(ID::C,1); port(ID::D,1); port(ID::Y,1); check_expected(); return; }
1331
1332 if (cell->type == ID($_TBUF_)) { port(ID::A,1); port(ID::Y,1); port(ID::E,1); check_expected(); return; }
1333
1334 if (cell->type == ID($_MUX4_)) { port(ID::A,1); port(ID::B,1); port(ID::C,1); port(ID::D,1); port(ID::S,1); port(ID::T,1); port(ID::Y,1); check_expected(); return; }
1335 if (cell->type == ID($_MUX8_)) { port(ID::A,1); port(ID::B,1); port(ID::C,1); port(ID::D,1); port(ID::E,1); port(ID::F,1); port(ID::G,1); port(ID::H,1); port(ID::S,1); port(ID::T,1); port(ID::U,1); port(ID::Y,1); check_expected(); return; }
1336 if (cell->type == ID($_MUX16_)) { port(ID::A,1); port(ID::B,1); port(ID::C,1); port(ID::D,1); port(ID::E,1); port(ID::F,1); port(ID::G,1); port(ID::H,1); port(ID::I,1); port(ID::J,1); port(ID::K,1); port(ID::L,1); port(ID::M,1); port(ID::N,1); port(ID::O,1); port(ID::P,1); port(ID::S,1); port(ID::T,1); port(ID::U,1); port(ID::V,1); port(ID::Y,1); check_expected(); return; }
1337
1338 if (cell->type == ID($_SR_NN_)) { port(ID::S,1); port(ID::R,1); port(ID::Q,1); check_expected(); return; }
1339 if (cell->type == ID($_SR_NP_)) { port(ID::S,1); port(ID::R,1); port(ID::Q,1); check_expected(); return; }
1340 if (cell->type == ID($_SR_PN_)) { port(ID::S,1); port(ID::R,1); port(ID::Q,1); check_expected(); return; }
1341 if (cell->type == ID($_SR_PP_)) { port(ID::S,1); port(ID::R,1); port(ID::Q,1); check_expected(); return; }
1342
1343 if (cell->type == ID($_FF_)) { port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1344 if (cell->type == ID($_DFF_N_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); check_expected(); return; }
1345 if (cell->type == ID($_DFF_P_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); check_expected(); return; }
1346
1347 if (cell->type == ID($_DFFE_NN_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::E,1); check_expected(); return; }
1348 if (cell->type == ID($_DFFE_NP_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::E,1); check_expected(); return; }
1349 if (cell->type == ID($_DFFE_PN_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::E,1); check_expected(); return; }
1350 if (cell->type == ID($_DFFE_PP_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::E,1); check_expected(); return; }
1351
1352 if (cell->type == ID($_DFF_NN0_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::R,1); check_expected(); return; }
1353 if (cell->type == ID($_DFF_NN1_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::R,1); check_expected(); return; }
1354 if (cell->type == ID($_DFF_NP0_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::R,1); check_expected(); return; }
1355 if (cell->type == ID($_DFF_NP1_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::R,1); check_expected(); return; }
1356 if (cell->type == ID($_DFF_PN0_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::R,1); check_expected(); return; }
1357 if (cell->type == ID($_DFF_PN1_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::R,1); check_expected(); return; }
1358 if (cell->type == ID($_DFF_PP0_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::R,1); check_expected(); return; }
1359 if (cell->type == ID($_DFF_PP1_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::R,1); check_expected(); return; }
1360
1361 if (cell->type == ID($_DFFSR_NNN_)) { port(ID::C,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1362 if (cell->type == ID($_DFFSR_NNP_)) { port(ID::C,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1363 if (cell->type == ID($_DFFSR_NPN_)) { port(ID::C,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1364 if (cell->type == ID($_DFFSR_NPP_)) { port(ID::C,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1365 if (cell->type == ID($_DFFSR_PNN_)) { port(ID::C,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1366 if (cell->type == ID($_DFFSR_PNP_)) { port(ID::C,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1367 if (cell->type == ID($_DFFSR_PPN_)) { port(ID::C,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1368 if (cell->type == ID($_DFFSR_PPP_)) { port(ID::C,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1369
1370 if (cell->type == ID($_DLATCH_N_)) { port(ID::E,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1371 if (cell->type == ID($_DLATCH_P_)) { port(ID::E,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1372
1373 if (cell->type == ID($_DLATCHSR_NNN_)) { port(ID::E,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1374 if (cell->type == ID($_DLATCHSR_NNP_)) { port(ID::E,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1375 if (cell->type == ID($_DLATCHSR_NPN_)) { port(ID::E,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1376 if (cell->type == ID($_DLATCHSR_NPP_)) { port(ID::E,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1377 if (cell->type == ID($_DLATCHSR_PNN_)) { port(ID::E,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1378 if (cell->type == ID($_DLATCHSR_PNP_)) { port(ID::E,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1379 if (cell->type == ID($_DLATCHSR_PPN_)) { port(ID::E,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1380 if (cell->type == ID($_DLATCHSR_PPP_)) { port(ID::E,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1381
1382 error(__LINE__);
1383 }
1384 };
1385 }
1386 #endif
1387
1388 void RTLIL::Module::sort()
1389 {
1390 wires_.sort(sort_by_id_str());
1391 cells_.sort(sort_by_id_str());
1392 parameter_default_values.sort(sort_by_id_str());
1393 memories.sort(sort_by_id_str());
1394 processes.sort(sort_by_id_str());
1395 for (auto &it : cells_)
1396 it.second->sort();
1397 for (auto &it : wires_)
1398 it.second->attributes.sort(sort_by_id_str());
1399 for (auto &it : memories)
1400 it.second->attributes.sort(sort_by_id_str());
1401 }
1402
1403 void RTLIL::Module::check()
1404 {
1405 #ifndef NDEBUG
1406 std::vector<bool> ports_declared;
1407 for (auto &it : wires_) {
1408 log_assert(this == it.second->module);
1409 log_assert(it.first == it.second->name);
1410 log_assert(!it.first.empty());
1411 log_assert(it.second->width >= 0);
1412 log_assert(it.second->port_id >= 0);
1413 for (auto &it2 : it.second->attributes)
1414 log_assert(!it2.first.empty());
1415 if (it.second->port_id) {
1416 log_assert(GetSize(ports) >= it.second->port_id);
1417 log_assert(ports.at(it.second->port_id-1) == it.first);
1418 log_assert(it.second->port_input || it.second->port_output);
1419 if (GetSize(ports_declared) < it.second->port_id)
1420 ports_declared.resize(it.second->port_id);
1421 log_assert(ports_declared[it.second->port_id-1] == false);
1422 ports_declared[it.second->port_id-1] = true;
1423 } else
1424 log_assert(!it.second->port_input && !it.second->port_output);
1425 }
1426 for (auto port_declared : ports_declared)
1427 log_assert(port_declared == true);
1428 log_assert(GetSize(ports) == GetSize(ports_declared));
1429
1430 for (auto &it : memories) {
1431 log_assert(it.first == it.second->name);
1432 log_assert(!it.first.empty());
1433 log_assert(it.second->width >= 0);
1434 log_assert(it.second->size >= 0);
1435 for (auto &it2 : it.second->attributes)
1436 log_assert(!it2.first.empty());
1437 }
1438
1439 for (auto &it : cells_) {
1440 log_assert(this == it.second->module);
1441 log_assert(it.first == it.second->name);
1442 log_assert(!it.first.empty());
1443 log_assert(!it.second->type.empty());
1444 for (auto &it2 : it.second->connections()) {
1445 log_assert(!it2.first.empty());
1446 it2.second.check();
1447 }
1448 for (auto &it2 : it.second->attributes)
1449 log_assert(!it2.first.empty());
1450 for (auto &it2 : it.second->parameters)
1451 log_assert(!it2.first.empty());
1452 InternalCellChecker checker(this, it.second);
1453 checker.check();
1454 }
1455
1456 for (auto &it : processes) {
1457 log_assert(it.first == it.second->name);
1458 log_assert(!it.first.empty());
1459 log_assert(it.second->root_case.compare.empty());
1460 std::vector<CaseRule*> all_cases = {&it.second->root_case};
1461 for (size_t i = 0; i < all_cases.size(); i++) {
1462 for (auto &switch_it : all_cases[i]->switches) {
1463 for (auto &case_it : switch_it->cases) {
1464 for (auto &compare_it : case_it->compare) {
1465 log_assert(switch_it->signal.size() == compare_it.size());
1466 }
1467 all_cases.push_back(case_it);
1468 }
1469 }
1470 }
1471 for (auto &sync_it : it.second->syncs) {
1472 switch (sync_it->type) {
1473 case SyncType::ST0:
1474 case SyncType::ST1:
1475 case SyncType::STp:
1476 case SyncType::STn:
1477 case SyncType::STe:
1478 log_assert(!sync_it->signal.empty());
1479 break;
1480 case SyncType::STa:
1481 case SyncType::STg:
1482 case SyncType::STi:
1483 log_assert(sync_it->signal.empty());
1484 break;
1485 }
1486 }
1487 }
1488
1489 for (auto &it : connections_) {
1490 log_assert(it.first.size() == it.second.size());
1491 log_assert(!it.first.has_const());
1492 it.first.check();
1493 it.second.check();
1494 }
1495
1496 for (auto &it : attributes)
1497 log_assert(!it.first.empty());
1498 #endif
1499 }
1500
1501 void RTLIL::Module::optimize()
1502 {
1503 }
1504
1505 void RTLIL::Module::cloneInto(RTLIL::Module *new_mod) const
1506 {
1507 log_assert(new_mod->refcount_wires_ == 0);
1508 log_assert(new_mod->refcount_cells_ == 0);
1509
1510 new_mod->avail_parameters = avail_parameters;
1511 new_mod->parameter_default_values = parameter_default_values;
1512
1513 for (auto &conn : connections_)
1514 new_mod->connect(conn);
1515
1516 for (auto &attr : attributes)
1517 new_mod->attributes[attr.first] = attr.second;
1518
1519 for (auto &it : wires_)
1520 new_mod->addWire(it.first, it.second);
1521
1522 for (auto &it : memories)
1523 new_mod->memories[it.first] = new RTLIL::Memory(*it.second);
1524
1525 for (auto &it : cells_)
1526 new_mod->addCell(it.first, it.second);
1527
1528 for (auto &it : processes)
1529 new_mod->processes[it.first] = it.second->clone();
1530
1531 struct RewriteSigSpecWorker
1532 {
1533 RTLIL::Module *mod;
1534 void operator()(RTLIL::SigSpec &sig)
1535 {
1536 sig.pack();
1537 for (auto &c : sig.chunks_)
1538 if (c.wire != NULL)
1539 c.wire = mod->wires_.at(c.wire->name);
1540 }
1541 };
1542
1543 RewriteSigSpecWorker rewriteSigSpecWorker;
1544 rewriteSigSpecWorker.mod = new_mod;
1545 new_mod->rewrite_sigspecs(rewriteSigSpecWorker);
1546 new_mod->fixup_ports();
1547 }
1548
1549 RTLIL::Module *RTLIL::Module::clone() const
1550 {
1551 RTLIL::Module *new_mod = new RTLIL::Module;
1552 new_mod->name = name;
1553 cloneInto(new_mod);
1554 return new_mod;
1555 }
1556
1557 bool RTLIL::Module::has_memories() const
1558 {
1559 return !memories.empty();
1560 }
1561
1562 bool RTLIL::Module::has_processes() const
1563 {
1564 return !processes.empty();
1565 }
1566
1567 bool RTLIL::Module::has_memories_warn() const
1568 {
1569 if (!memories.empty())
1570 log_warning("Ignoring module %s because it contains memories (run 'memory' command first).\n", log_id(this));
1571 return !memories.empty();
1572 }
1573
1574 bool RTLIL::Module::has_processes_warn() const
1575 {
1576 if (!processes.empty())
1577 log_warning("Ignoring module %s because it contains processes (run 'proc' command first).\n", log_id(this));
1578 return !processes.empty();
1579 }
1580
1581 std::vector<RTLIL::Wire*> RTLIL::Module::selected_wires() const
1582 {
1583 std::vector<RTLIL::Wire*> result;
1584 result.reserve(wires_.size());
1585 for (auto &it : wires_)
1586 if (design->selected(this, it.second))
1587 result.push_back(it.second);
1588 return result;
1589 }
1590
1591 std::vector<RTLIL::Cell*> RTLIL::Module::selected_cells() const
1592 {
1593 std::vector<RTLIL::Cell*> result;
1594 result.reserve(cells_.size());
1595 for (auto &it : cells_)
1596 if (design->selected(this, it.second))
1597 result.push_back(it.second);
1598 return result;
1599 }
1600
1601 void RTLIL::Module::add(RTLIL::Wire *wire)
1602 {
1603 log_assert(!wire->name.empty());
1604 log_assert(count_id(wire->name) == 0);
1605 log_assert(refcount_wires_ == 0);
1606 wires_[wire->name] = wire;
1607 wire->module = this;
1608 }
1609
1610 void RTLIL::Module::add(RTLIL::Cell *cell)
1611 {
1612 log_assert(!cell->name.empty());
1613 log_assert(count_id(cell->name) == 0);
1614 log_assert(refcount_cells_ == 0);
1615 cells_[cell->name] = cell;
1616 cell->module = this;
1617 }
1618
1619 void RTLIL::Module::remove(const pool<RTLIL::Wire*> &wires)
1620 {
1621 log_assert(refcount_wires_ == 0);
1622
1623 struct DeleteWireWorker
1624 {
1625 RTLIL::Module *module;
1626 const pool<RTLIL::Wire*> *wires_p;
1627
1628 void operator()(RTLIL::SigSpec &sig) {
1629 sig.pack();
1630 for (auto &c : sig.chunks_)
1631 if (c.wire != NULL && wires_p->count(c.wire)) {
1632 c.wire = module->addWire(NEW_ID, c.width);
1633 c.offset = 0;
1634 }
1635 }
1636
1637 void operator()(RTLIL::SigSpec &lhs, RTLIL::SigSpec &rhs) {
1638 log_assert(GetSize(lhs) == GetSize(rhs));
1639 lhs.unpack();
1640 rhs.unpack();
1641 for (int i = 0; i < GetSize(lhs); i++) {
1642 RTLIL::SigBit &lhs_bit = lhs.bits_[i];
1643 RTLIL::SigBit &rhs_bit = rhs.bits_[i];
1644 if ((lhs_bit.wire != nullptr && wires_p->count(lhs_bit.wire)) || (rhs_bit.wire != nullptr && wires_p->count(rhs_bit.wire))) {
1645 lhs_bit = State::Sx;
1646 rhs_bit = State::Sx;
1647 }
1648 }
1649 }
1650 };
1651
1652 DeleteWireWorker delete_wire_worker;
1653 delete_wire_worker.module = this;
1654 delete_wire_worker.wires_p = &wires;
1655 rewrite_sigspecs2(delete_wire_worker);
1656
1657 for (auto &it : wires) {
1658 log_assert(wires_.count(it->name) != 0);
1659 wires_.erase(it->name);
1660 delete it;
1661 }
1662 }
1663
1664 void RTLIL::Module::remove(RTLIL::Cell *cell)
1665 {
1666 while (!cell->connections_.empty())
1667 cell->unsetPort(cell->connections_.begin()->first);
1668
1669 log_assert(cells_.count(cell->name) != 0);
1670 log_assert(refcount_cells_ == 0);
1671 cells_.erase(cell->name);
1672 delete cell;
1673 }
1674
1675 void RTLIL::Module::rename(RTLIL::Wire *wire, RTLIL::IdString new_name)
1676 {
1677 log_assert(wires_[wire->name] == wire);
1678 log_assert(refcount_wires_ == 0);
1679 wires_.erase(wire->name);
1680 wire->name = new_name;
1681 add(wire);
1682 }
1683
1684 void RTLIL::Module::rename(RTLIL::Cell *cell, RTLIL::IdString new_name)
1685 {
1686 log_assert(cells_[cell->name] == cell);
1687 log_assert(refcount_wires_ == 0);
1688 cells_.erase(cell->name);
1689 cell->name = new_name;
1690 add(cell);
1691 }
1692
1693 void RTLIL::Module::rename(RTLIL::IdString old_name, RTLIL::IdString new_name)
1694 {
1695 log_assert(count_id(old_name) != 0);
1696 if (wires_.count(old_name))
1697 rename(wires_.at(old_name), new_name);
1698 else if (cells_.count(old_name))
1699 rename(cells_.at(old_name), new_name);
1700 else
1701 log_abort();
1702 }
1703
1704 void RTLIL::Module::swap_names(RTLIL::Wire *w1, RTLIL::Wire *w2)
1705 {
1706 log_assert(wires_[w1->name] == w1);
1707 log_assert(wires_[w2->name] == w2);
1708 log_assert(refcount_wires_ == 0);
1709
1710 wires_.erase(w1->name);
1711 wires_.erase(w2->name);
1712
1713 std::swap(w1->name, w2->name);
1714
1715 wires_[w1->name] = w1;
1716 wires_[w2->name] = w2;
1717 }
1718
1719 void RTLIL::Module::swap_names(RTLIL::Cell *c1, RTLIL::Cell *c2)
1720 {
1721 log_assert(cells_[c1->name] == c1);
1722 log_assert(cells_[c2->name] == c2);
1723 log_assert(refcount_cells_ == 0);
1724
1725 cells_.erase(c1->name);
1726 cells_.erase(c2->name);
1727
1728 std::swap(c1->name, c2->name);
1729
1730 cells_[c1->name] = c1;
1731 cells_[c2->name] = c2;
1732 }
1733
1734 RTLIL::IdString RTLIL::Module::uniquify(RTLIL::IdString name)
1735 {
1736 int index = 0;
1737 return uniquify(name, index);
1738 }
1739
1740 RTLIL::IdString RTLIL::Module::uniquify(RTLIL::IdString name, int &index)
1741 {
1742 if (index == 0) {
1743 if (count_id(name) == 0)
1744 return name;
1745 index++;
1746 }
1747
1748 while (1) {
1749 RTLIL::IdString new_name = stringf("%s_%d", name.c_str(), index);
1750 if (count_id(new_name) == 0)
1751 return new_name;
1752 index++;
1753 }
1754 }
1755
1756 static bool fixup_ports_compare(const RTLIL::Wire *a, const RTLIL::Wire *b)
1757 {
1758 if (a->port_id && !b->port_id)
1759 return true;
1760 if (!a->port_id && b->port_id)
1761 return false;
1762
1763 if (a->port_id == b->port_id)
1764 return a->name < b->name;
1765 return a->port_id < b->port_id;
1766 }
1767
1768 void RTLIL::Module::connect(const RTLIL::SigSig &conn)
1769 {
1770 for (auto mon : monitors)
1771 mon->notify_connect(this, conn);
1772
1773 if (design)
1774 for (auto mon : design->monitors)
1775 mon->notify_connect(this, conn);
1776
1777 // ignore all attempts to assign constants to other constants
1778 if (conn.first.has_const()) {
1779 RTLIL::SigSig new_conn;
1780 for (int i = 0; i < GetSize(conn.first); i++)
1781 if (conn.first[i].wire) {
1782 new_conn.first.append(conn.first[i]);
1783 new_conn.second.append(conn.second[i]);
1784 }
1785 if (GetSize(new_conn.first))
1786 connect(new_conn);
1787 return;
1788 }
1789
1790 if (yosys_xtrace) {
1791 log("#X# Connect (SigSig) in %s: %s = %s (%d bits)\n", log_id(this), log_signal(conn.first), log_signal(conn.second), GetSize(conn.first));
1792 log_backtrace("-X- ", yosys_xtrace-1);
1793 }
1794
1795 log_assert(GetSize(conn.first) == GetSize(conn.second));
1796 connections_.push_back(conn);
1797 }
1798
1799 void RTLIL::Module::connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs)
1800 {
1801 connect(RTLIL::SigSig(lhs, rhs));
1802 }
1803
1804 void RTLIL::Module::new_connections(const std::vector<RTLIL::SigSig> &new_conn)
1805 {
1806 for (auto mon : monitors)
1807 mon->notify_connect(this, new_conn);
1808
1809 if (design)
1810 for (auto mon : design->monitors)
1811 mon->notify_connect(this, new_conn);
1812
1813 if (yosys_xtrace) {
1814 log("#X# New connections vector in %s:\n", log_id(this));
1815 for (auto &conn: new_conn)
1816 log("#X# %s = %s (%d bits)\n", log_signal(conn.first), log_signal(conn.second), GetSize(conn.first));
1817 log_backtrace("-X- ", yosys_xtrace-1);
1818 }
1819
1820 connections_ = new_conn;
1821 }
1822
1823 const std::vector<RTLIL::SigSig> &RTLIL::Module::connections() const
1824 {
1825 return connections_;
1826 }
1827
1828 void RTLIL::Module::fixup_ports()
1829 {
1830 std::vector<RTLIL::Wire*> all_ports;
1831
1832 for (auto &w : wires_)
1833 if (w.second->port_input || w.second->port_output)
1834 all_ports.push_back(w.second);
1835 else
1836 w.second->port_id = 0;
1837
1838 std::sort(all_ports.begin(), all_ports.end(), fixup_ports_compare);
1839
1840 ports.clear();
1841 for (size_t i = 0; i < all_ports.size(); i++) {
1842 ports.push_back(all_ports[i]->name);
1843 all_ports[i]->port_id = i+1;
1844 }
1845 }
1846
1847 RTLIL::Wire *RTLIL::Module::addWire(RTLIL::IdString name, int width)
1848 {
1849 RTLIL::Wire *wire = new RTLIL::Wire;
1850 wire->name = name;
1851 wire->width = width;
1852 add(wire);
1853 return wire;
1854 }
1855
1856 RTLIL::Wire *RTLIL::Module::addWire(RTLIL::IdString name, const RTLIL::Wire *other)
1857 {
1858 RTLIL::Wire *wire = addWire(name);
1859 wire->width = other->width;
1860 wire->start_offset = other->start_offset;
1861 wire->port_id = other->port_id;
1862 wire->port_input = other->port_input;
1863 wire->port_output = other->port_output;
1864 wire->upto = other->upto;
1865 wire->attributes = other->attributes;
1866 return wire;
1867 }
1868
1869 RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, RTLIL::IdString type)
1870 {
1871 RTLIL::Cell *cell = new RTLIL::Cell;
1872 cell->name = name;
1873 cell->type = type;
1874 add(cell);
1875 return cell;
1876 }
1877
1878 RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, const RTLIL::Cell *other)
1879 {
1880 RTLIL::Cell *cell = addCell(name, other->type);
1881 cell->connections_ = other->connections_;
1882 cell->parameters = other->parameters;
1883 cell->attributes = other->attributes;
1884 return cell;
1885 }
1886
1887 #define DEF_METHOD(_func, _y_size, _type) \
1888 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed, const std::string &src) { \
1889 RTLIL::Cell *cell = addCell(name, _type); \
1890 cell->parameters[ID::A_SIGNED] = is_signed; \
1891 cell->parameters[ID::A_WIDTH] = sig_a.size(); \
1892 cell->parameters[ID::Y_WIDTH] = sig_y.size(); \
1893 cell->setPort(ID::A, sig_a); \
1894 cell->setPort(ID::Y, sig_y); \
1895 cell->set_src_attribute(src); \
1896 return cell; \
1897 } \
1898 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed, const std::string &src) { \
1899 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
1900 add ## _func(name, sig_a, sig_y, is_signed, src); \
1901 return sig_y; \
1902 }
1903 DEF_METHOD(Not, sig_a.size(), ID($not))
1904 DEF_METHOD(Pos, sig_a.size(), ID($pos))
1905 DEF_METHOD(Neg, sig_a.size(), ID($neg))
1906 DEF_METHOD(ReduceAnd, 1, ID($reduce_and))
1907 DEF_METHOD(ReduceOr, 1, ID($reduce_or))
1908 DEF_METHOD(ReduceXor, 1, ID($reduce_xor))
1909 DEF_METHOD(ReduceXnor, 1, ID($reduce_xnor))
1910 DEF_METHOD(ReduceBool, 1, ID($reduce_bool))
1911 DEF_METHOD(LogicNot, 1, ID($logic_not))
1912 #undef DEF_METHOD
1913
1914 #define DEF_METHOD(_func, _y_size, _type) \
1915 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed, const std::string &src) { \
1916 RTLIL::Cell *cell = addCell(name, _type); \
1917 cell->parameters[ID::A_SIGNED] = is_signed; \
1918 cell->parameters[ID::B_SIGNED] = is_signed; \
1919 cell->parameters[ID::A_WIDTH] = sig_a.size(); \
1920 cell->parameters[ID::B_WIDTH] = sig_b.size(); \
1921 cell->parameters[ID::Y_WIDTH] = sig_y.size(); \
1922 cell->setPort(ID::A, sig_a); \
1923 cell->setPort(ID::B, sig_b); \
1924 cell->setPort(ID::Y, sig_y); \
1925 cell->set_src_attribute(src); \
1926 return cell; \
1927 } \
1928 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed, const std::string &src) { \
1929 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
1930 add ## _func(name, sig_a, sig_b, sig_y, is_signed, src); \
1931 return sig_y; \
1932 }
1933 DEF_METHOD(And, max(sig_a.size(), sig_b.size()), ID($and))
1934 DEF_METHOD(Or, max(sig_a.size(), sig_b.size()), ID($or))
1935 DEF_METHOD(Xor, max(sig_a.size(), sig_b.size()), ID($xor))
1936 DEF_METHOD(Xnor, max(sig_a.size(), sig_b.size()), ID($xnor))
1937 DEF_METHOD(Shift, sig_a.size(), ID($shift))
1938 DEF_METHOD(Shiftx, sig_a.size(), ID($shiftx))
1939 DEF_METHOD(Lt, 1, ID($lt))
1940 DEF_METHOD(Le, 1, ID($le))
1941 DEF_METHOD(Eq, 1, ID($eq))
1942 DEF_METHOD(Ne, 1, ID($ne))
1943 DEF_METHOD(Eqx, 1, ID($eqx))
1944 DEF_METHOD(Nex, 1, ID($nex))
1945 DEF_METHOD(Ge, 1, ID($ge))
1946 DEF_METHOD(Gt, 1, ID($gt))
1947 DEF_METHOD(Add, max(sig_a.size(), sig_b.size()), ID($add))
1948 DEF_METHOD(Sub, max(sig_a.size(), sig_b.size()), ID($sub))
1949 DEF_METHOD(Mul, max(sig_a.size(), sig_b.size()), ID($mul))
1950 DEF_METHOD(Div, max(sig_a.size(), sig_b.size()), ID($div))
1951 DEF_METHOD(Mod, max(sig_a.size(), sig_b.size()), ID($mod))
1952 DEF_METHOD(LogicAnd, 1, ID($logic_and))
1953 DEF_METHOD(LogicOr, 1, ID($logic_or))
1954 #undef DEF_METHOD
1955
1956 #define DEF_METHOD(_func, _y_size, _type) \
1957 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed, const std::string &src) { \
1958 RTLIL::Cell *cell = addCell(name, _type); \
1959 cell->parameters[ID::A_SIGNED] = is_signed; \
1960 cell->parameters[ID::B_SIGNED] = false; \
1961 cell->parameters[ID::A_WIDTH] = sig_a.size(); \
1962 cell->parameters[ID::B_WIDTH] = sig_b.size(); \
1963 cell->parameters[ID::Y_WIDTH] = sig_y.size(); \
1964 cell->setPort(ID::A, sig_a); \
1965 cell->setPort(ID::B, sig_b); \
1966 cell->setPort(ID::Y, sig_y); \
1967 cell->set_src_attribute(src); \
1968 return cell; \
1969 } \
1970 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed, const std::string &src) { \
1971 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
1972 add ## _func(name, sig_a, sig_b, sig_y, is_signed, src); \
1973 return sig_y; \
1974 }
1975 DEF_METHOD(Shl, sig_a.size(), ID($shl))
1976 DEF_METHOD(Shr, sig_a.size(), ID($shr))
1977 DEF_METHOD(Sshl, sig_a.size(), ID($sshl))
1978 DEF_METHOD(Sshr, sig_a.size(), ID($sshr))
1979 #undef DEF_METHOD
1980
1981 #define DEF_METHOD(_func, _type, _pmux) \
1982 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, const std::string &src) { \
1983 RTLIL::Cell *cell = addCell(name, _type); \
1984 cell->parameters[ID::WIDTH] = sig_a.size(); \
1985 if (_pmux) cell->parameters[ID::S_WIDTH] = sig_s.size(); \
1986 cell->setPort(ID::A, sig_a); \
1987 cell->setPort(ID::B, sig_b); \
1988 cell->setPort(ID::S, sig_s); \
1989 cell->setPort(ID::Y, sig_y); \
1990 cell->set_src_attribute(src); \
1991 return cell; \
1992 } \
1993 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const std::string &src) { \
1994 RTLIL::SigSpec sig_y = addWire(NEW_ID, sig_a.size()); \
1995 add ## _func(name, sig_a, sig_b, sig_s, sig_y, src); \
1996 return sig_y; \
1997 }
1998 DEF_METHOD(Mux, ID($mux), 0)
1999 DEF_METHOD(Pmux, ID($pmux), 1)
2000 #undef DEF_METHOD
2001
2002 #define DEF_METHOD_2(_func, _type, _P1, _P2) \
2003 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const std::string &src) { \
2004 RTLIL::Cell *cell = addCell(name, _type); \
2005 cell->setPort("\\" #_P1, sig1); \
2006 cell->setPort("\\" #_P2, sig2); \
2007 cell->set_src_attribute(src); \
2008 return cell; \
2009 } \
2010 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const std::string &src) { \
2011 RTLIL::SigBit sig2 = addWire(NEW_ID); \
2012 add ## _func(name, sig1, sig2, src); \
2013 return sig2; \
2014 }
2015 #define DEF_METHOD_3(_func, _type, _P1, _P2, _P3) \
2016 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const RTLIL::SigBit &sig3, const std::string &src) { \
2017 RTLIL::Cell *cell = addCell(name, _type); \
2018 cell->setPort("\\" #_P1, sig1); \
2019 cell->setPort("\\" #_P2, sig2); \
2020 cell->setPort("\\" #_P3, sig3); \
2021 cell->set_src_attribute(src); \
2022 return cell; \
2023 } \
2024 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const std::string &src) { \
2025 RTLIL::SigBit sig3 = addWire(NEW_ID); \
2026 add ## _func(name, sig1, sig2, sig3, src); \
2027 return sig3; \
2028 }
2029 #define DEF_METHOD_4(_func, _type, _P1, _P2, _P3, _P4) \
2030 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const RTLIL::SigBit &sig3, const RTLIL::SigBit &sig4, const std::string &src) { \
2031 RTLIL::Cell *cell = addCell(name, _type); \
2032 cell->setPort("\\" #_P1, sig1); \
2033 cell->setPort("\\" #_P2, sig2); \
2034 cell->setPort("\\" #_P3, sig3); \
2035 cell->setPort("\\" #_P4, sig4); \
2036 cell->set_src_attribute(src); \
2037 return cell; \
2038 } \
2039 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const RTLIL::SigBit &sig3, const std::string &src) { \
2040 RTLIL::SigBit sig4 = addWire(NEW_ID); \
2041 add ## _func(name, sig1, sig2, sig3, sig4, src); \
2042 return sig4; \
2043 }
2044 #define DEF_METHOD_5(_func, _type, _P1, _P2, _P3, _P4, _P5) \
2045 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const RTLIL::SigBit &sig3, const RTLIL::SigBit &sig4, const RTLIL::SigBit &sig5, const std::string &src) { \
2046 RTLIL::Cell *cell = addCell(name, _type); \
2047 cell->setPort("\\" #_P1, sig1); \
2048 cell->setPort("\\" #_P2, sig2); \
2049 cell->setPort("\\" #_P3, sig3); \
2050 cell->setPort("\\" #_P4, sig4); \
2051 cell->setPort("\\" #_P5, sig5); \
2052 cell->set_src_attribute(src); \
2053 return cell; \
2054 } \
2055 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const RTLIL::SigBit &sig3, const RTLIL::SigBit &sig4, const std::string &src) { \
2056 RTLIL::SigBit sig5 = addWire(NEW_ID); \
2057 add ## _func(name, sig1, sig2, sig3, sig4, sig5, src); \
2058 return sig5; \
2059 }
2060 DEF_METHOD_2(BufGate, ID($_BUF_), A, Y)
2061 DEF_METHOD_2(NotGate, ID($_NOT_), A, Y)
2062 DEF_METHOD_3(AndGate, ID($_AND_), A, B, Y)
2063 DEF_METHOD_3(NandGate, ID($_NAND_), A, B, Y)
2064 DEF_METHOD_3(OrGate, ID($_OR_), A, B, Y)
2065 DEF_METHOD_3(NorGate, ID($_NOR_), A, B, Y)
2066 DEF_METHOD_3(XorGate, ID($_XOR_), A, B, Y)
2067 DEF_METHOD_3(XnorGate, ID($_XNOR_), A, B, Y)
2068 DEF_METHOD_3(AndnotGate, ID($_ANDNOT_), A, B, Y)
2069 DEF_METHOD_3(OrnotGate, ID($_ORNOT_), A, B, Y)
2070 DEF_METHOD_4(MuxGate, ID($_MUX_), A, B, S, Y)
2071 DEF_METHOD_4(NmuxGate, ID($_NMUX_), A, B, S, Y)
2072 DEF_METHOD_4(Aoi3Gate, ID($_AOI3_), A, B, C, Y)
2073 DEF_METHOD_4(Oai3Gate, ID($_OAI3_), A, B, C, Y)
2074 DEF_METHOD_5(Aoi4Gate, ID($_AOI4_), A, B, C, D, Y)
2075 DEF_METHOD_5(Oai4Gate, ID($_OAI4_), A, B, C, D, Y)
2076 #undef DEF_METHOD_2
2077 #undef DEF_METHOD_3
2078 #undef DEF_METHOD_4
2079 #undef DEF_METHOD_5
2080
2081 RTLIL::Cell* RTLIL::Module::addPow(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool a_signed, bool b_signed, const std::string &src)
2082 {
2083 RTLIL::Cell *cell = addCell(name, ID($pow));
2084 cell->parameters[ID::A_SIGNED] = a_signed;
2085 cell->parameters[ID::B_SIGNED] = b_signed;
2086 cell->parameters[ID::A_WIDTH] = sig_a.size();
2087 cell->parameters[ID::B_WIDTH] = sig_b.size();
2088 cell->parameters[ID::Y_WIDTH] = sig_y.size();
2089 cell->setPort(ID::A, sig_a);
2090 cell->setPort(ID::B, sig_b);
2091 cell->setPort(ID::Y, sig_y);
2092 cell->set_src_attribute(src);
2093 return cell;
2094 }
2095
2096 RTLIL::Cell* RTLIL::Module::addSlice(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, RTLIL::Const offset, const std::string &src)
2097 {
2098 RTLIL::Cell *cell = addCell(name, ID($slice));
2099 cell->parameters[ID::A_WIDTH] = sig_a.size();
2100 cell->parameters[ID::Y_WIDTH] = sig_y.size();
2101 cell->parameters[ID::OFFSET] = offset;
2102 cell->setPort(ID::A, sig_a);
2103 cell->setPort(ID::Y, sig_y);
2104 cell->set_src_attribute(src);
2105 return cell;
2106 }
2107
2108 RTLIL::Cell* RTLIL::Module::addConcat(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, const std::string &src)
2109 {
2110 RTLIL::Cell *cell = addCell(name, ID($concat));
2111 cell->parameters[ID::A_WIDTH] = sig_a.size();
2112 cell->parameters[ID::B_WIDTH] = sig_b.size();
2113 cell->setPort(ID::A, sig_a);
2114 cell->setPort(ID::B, sig_b);
2115 cell->setPort(ID::Y, sig_y);
2116 cell->set_src_attribute(src);
2117 return cell;
2118 }
2119
2120 RTLIL::Cell* RTLIL::Module::addLut(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, RTLIL::Const lut, const std::string &src)
2121 {
2122 RTLIL::Cell *cell = addCell(name, ID($lut));
2123 cell->parameters[ID::LUT] = lut;
2124 cell->parameters[ID::WIDTH] = sig_a.size();
2125 cell->setPort(ID::A, sig_a);
2126 cell->setPort(ID::Y, sig_y);
2127 cell->set_src_attribute(src);
2128 return cell;
2129 }
2130
2131 RTLIL::Cell* RTLIL::Module::addTribuf(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_y, const std::string &src)
2132 {
2133 RTLIL::Cell *cell = addCell(name, ID($tribuf));
2134 cell->parameters[ID::WIDTH] = sig_a.size();
2135 cell->setPort(ID::A, sig_a);
2136 cell->setPort(ID::EN, sig_en);
2137 cell->setPort(ID::Y, sig_y);
2138 cell->set_src_attribute(src);
2139 return cell;
2140 }
2141
2142 RTLIL::Cell* RTLIL::Module::addAssert(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src)
2143 {
2144 RTLIL::Cell *cell = addCell(name, ID($assert));
2145 cell->setPort(ID::A, sig_a);
2146 cell->setPort(ID::EN, sig_en);
2147 cell->set_src_attribute(src);
2148 return cell;
2149 }
2150
2151 RTLIL::Cell* RTLIL::Module::addAssume(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src)
2152 {
2153 RTLIL::Cell *cell = addCell(name, ID($assume));
2154 cell->setPort(ID::A, sig_a);
2155 cell->setPort(ID::EN, sig_en);
2156 cell->set_src_attribute(src);
2157 return cell;
2158 }
2159
2160 RTLIL::Cell* RTLIL::Module::addLive(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src)
2161 {
2162 RTLIL::Cell *cell = addCell(name, ID($live));
2163 cell->setPort(ID::A, sig_a);
2164 cell->setPort(ID::EN, sig_en);
2165 cell->set_src_attribute(src);
2166 return cell;
2167 }
2168
2169 RTLIL::Cell* RTLIL::Module::addFair(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src)
2170 {
2171 RTLIL::Cell *cell = addCell(name, ID($fair));
2172 cell->setPort(ID::A, sig_a);
2173 cell->setPort(ID::EN, sig_en);
2174 cell->set_src_attribute(src);
2175 return cell;
2176 }
2177
2178 RTLIL::Cell* RTLIL::Module::addCover(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src)
2179 {
2180 RTLIL::Cell *cell = addCell(name, ID($cover));
2181 cell->setPort(ID::A, sig_a);
2182 cell->setPort(ID::EN, sig_en);
2183 cell->set_src_attribute(src);
2184 return cell;
2185 }
2186
2187 RTLIL::Cell* RTLIL::Module::addEquiv(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, const std::string &src)
2188 {
2189 RTLIL::Cell *cell = addCell(name, ID($equiv));
2190 cell->setPort(ID::A, sig_a);
2191 cell->setPort(ID::B, sig_b);
2192 cell->setPort(ID::Y, sig_y);
2193 cell->set_src_attribute(src);
2194 return cell;
2195 }
2196
2197 RTLIL::Cell* RTLIL::Module::addSr(RTLIL::IdString name, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, const RTLIL::SigSpec &sig_q, bool set_polarity, bool clr_polarity, const std::string &src)
2198 {
2199 RTLIL::Cell *cell = addCell(name, ID($sr));
2200 cell->parameters[ID::SET_POLARITY] = set_polarity;
2201 cell->parameters[ID::CLR_POLARITY] = clr_polarity;
2202 cell->parameters[ID::WIDTH] = sig_q.size();
2203 cell->setPort(ID::SET, sig_set);
2204 cell->setPort(ID::CLR, sig_clr);
2205 cell->setPort(ID::Q, sig_q);
2206 cell->set_src_attribute(src);
2207 return cell;
2208 }
2209
2210 RTLIL::Cell* RTLIL::Module::addFf(RTLIL::IdString name, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const std::string &src)
2211 {
2212 RTLIL::Cell *cell = addCell(name, ID($ff));
2213 cell->parameters[ID::WIDTH] = sig_q.size();
2214 cell->setPort(ID::D, sig_d);
2215 cell->setPort(ID::Q, sig_q);
2216 cell->set_src_attribute(src);
2217 return cell;
2218 }
2219
2220 RTLIL::Cell* RTLIL::Module::addDff(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, const std::string &src)
2221 {
2222 RTLIL::Cell *cell = addCell(name, ID($dff));
2223 cell->parameters[ID::CLK_POLARITY] = clk_polarity;
2224 cell->parameters[ID::WIDTH] = sig_q.size();
2225 cell->setPort(ID::CLK, sig_clk);
2226 cell->setPort(ID::D, sig_d);
2227 cell->setPort(ID::Q, sig_q);
2228 cell->set_src_attribute(src);
2229 return cell;
2230 }
2231
2232 RTLIL::Cell* RTLIL::Module::addDffe(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, bool en_polarity, const std::string &src)
2233 {
2234 RTLIL::Cell *cell = addCell(name, ID($dffe));
2235 cell->parameters[ID::CLK_POLARITY] = clk_polarity;
2236 cell->parameters[ID::EN_POLARITY] = en_polarity;
2237 cell->parameters[ID::WIDTH] = sig_q.size();
2238 cell->setPort(ID::CLK, sig_clk);
2239 cell->setPort(ID::EN, sig_en);
2240 cell->setPort(ID::D, sig_d);
2241 cell->setPort(ID::Q, sig_q);
2242 cell->set_src_attribute(src);
2243 return cell;
2244 }
2245
2246 RTLIL::Cell* RTLIL::Module::addDffsr(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,
2247 RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
2248 {
2249 RTLIL::Cell *cell = addCell(name, ID($dffsr));
2250 cell->parameters[ID::CLK_POLARITY] = clk_polarity;
2251 cell->parameters[ID::SET_POLARITY] = set_polarity;
2252 cell->parameters[ID::CLR_POLARITY] = clr_polarity;
2253 cell->parameters[ID::WIDTH] = sig_q.size();
2254 cell->setPort(ID::CLK, sig_clk);
2255 cell->setPort(ID::SET, sig_set);
2256 cell->setPort(ID::CLR, sig_clr);
2257 cell->setPort(ID::D, sig_d);
2258 cell->setPort(ID::Q, sig_q);
2259 cell->set_src_attribute(src);
2260 return cell;
2261 }
2262
2263 RTLIL::Cell* RTLIL::Module::addAdff(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
2264 RTLIL::Const arst_value, bool clk_polarity, bool arst_polarity, const std::string &src)
2265 {
2266 RTLIL::Cell *cell = addCell(name, ID($adff));
2267 cell->parameters[ID::CLK_POLARITY] = clk_polarity;
2268 cell->parameters[ID::ARST_POLARITY] = arst_polarity;
2269 cell->parameters[ID::ARST_VALUE] = arst_value;
2270 cell->parameters[ID::WIDTH] = sig_q.size();
2271 cell->setPort(ID::CLK, sig_clk);
2272 cell->setPort(ID::ARST, sig_arst);
2273 cell->setPort(ID::D, sig_d);
2274 cell->setPort(ID::Q, sig_q);
2275 cell->set_src_attribute(src);
2276 return cell;
2277 }
2278
2279 RTLIL::Cell* RTLIL::Module::addDlatch(RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity, const std::string &src)
2280 {
2281 RTLIL::Cell *cell = addCell(name, ID($dlatch));
2282 cell->parameters[ID::EN_POLARITY] = en_polarity;
2283 cell->parameters[ID::WIDTH] = sig_q.size();
2284 cell->setPort(ID::EN, sig_en);
2285 cell->setPort(ID::D, sig_d);
2286 cell->setPort(ID::Q, sig_q);
2287 cell->set_src_attribute(src);
2288 return cell;
2289 }
2290
2291 RTLIL::Cell* RTLIL::Module::addDlatchsr(RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,
2292 RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
2293 {
2294 RTLIL::Cell *cell = addCell(name, ID($dlatchsr));
2295 cell->parameters[ID::EN_POLARITY] = en_polarity;
2296 cell->parameters[ID::SET_POLARITY] = set_polarity;
2297 cell->parameters[ID::CLR_POLARITY] = clr_polarity;
2298 cell->parameters[ID::WIDTH] = sig_q.size();
2299 cell->setPort(ID::EN, sig_en);
2300 cell->setPort(ID::SET, sig_set);
2301 cell->setPort(ID::CLR, sig_clr);
2302 cell->setPort(ID::D, sig_d);
2303 cell->setPort(ID::Q, sig_q);
2304 cell->set_src_attribute(src);
2305 return cell;
2306 }
2307
2308 RTLIL::Cell* RTLIL::Module::addFfGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const std::string &src)
2309 {
2310 RTLIL::Cell *cell = addCell(name, ID($_FF_));
2311 cell->setPort(ID::D, sig_d);
2312 cell->setPort(ID::Q, sig_q);
2313 cell->set_src_attribute(src);
2314 return cell;
2315 }
2316
2317 RTLIL::Cell* RTLIL::Module::addDffGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, const std::string &src)
2318 {
2319 RTLIL::Cell *cell = addCell(name, stringf("$_DFF_%c_", clk_polarity ? 'P' : 'N'));
2320 cell->setPort(ID::C, sig_clk);
2321 cell->setPort(ID::D, sig_d);
2322 cell->setPort(ID::Q, sig_q);
2323 cell->set_src_attribute(src);
2324 return cell;
2325 }
2326
2327 RTLIL::Cell* RTLIL::Module::addDffeGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, bool en_polarity, const std::string &src)
2328 {
2329 RTLIL::Cell *cell = addCell(name, stringf("$_DFFE_%c%c_", clk_polarity ? 'P' : 'N', en_polarity ? 'P' : 'N'));
2330 cell->setPort(ID::C, sig_clk);
2331 cell->setPort(ID::E, sig_en);
2332 cell->setPort(ID::D, sig_d);
2333 cell->setPort(ID::Q, sig_q);
2334 cell->set_src_attribute(src);
2335 return cell;
2336 }
2337
2338 RTLIL::Cell* RTLIL::Module::addDffsrGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,
2339 RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
2340 {
2341 RTLIL::Cell *cell = addCell(name, stringf("$_DFFSR_%c%c%c_", clk_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N'));
2342 cell->setPort(ID::C, sig_clk);
2343 cell->setPort(ID::S, sig_set);
2344 cell->setPort(ID::R, sig_clr);
2345 cell->setPort(ID::D, sig_d);
2346 cell->setPort(ID::Q, sig_q);
2347 cell->set_src_attribute(src);
2348 return cell;
2349 }
2350
2351 RTLIL::Cell* RTLIL::Module::addAdffGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
2352 bool arst_value, bool clk_polarity, bool arst_polarity, const std::string &src)
2353 {
2354 RTLIL::Cell *cell = addCell(name, stringf("$_DFF_%c%c%c_", clk_polarity ? 'P' : 'N', arst_polarity ? 'P' : 'N', arst_value ? '1' : '0'));
2355 cell->setPort(ID::C, sig_clk);
2356 cell->setPort(ID::R, sig_arst);
2357 cell->setPort(ID::D, sig_d);
2358 cell->setPort(ID::Q, sig_q);
2359 cell->set_src_attribute(src);
2360 return cell;
2361 }
2362
2363 RTLIL::Cell* RTLIL::Module::addDlatchGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity, const std::string &src)
2364 {
2365 RTLIL::Cell *cell = addCell(name, stringf("$_DLATCH_%c_", en_polarity ? 'P' : 'N'));
2366 cell->setPort(ID::E, sig_en);
2367 cell->setPort(ID::D, sig_d);
2368 cell->setPort(ID::Q, sig_q);
2369 cell->set_src_attribute(src);
2370 return cell;
2371 }
2372
2373 RTLIL::Cell* RTLIL::Module::addDlatchsrGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,
2374 RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
2375 {
2376 RTLIL::Cell *cell = addCell(name, stringf("$_DLATCHSR_%c%c%c_", en_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N'));
2377 cell->setPort(ID::E, sig_en);
2378 cell->setPort(ID::S, sig_set);
2379 cell->setPort(ID::R, sig_clr);
2380 cell->setPort(ID::D, sig_d);
2381 cell->setPort(ID::Q, sig_q);
2382 cell->set_src_attribute(src);
2383 return cell;
2384 }
2385
2386 RTLIL::SigSpec RTLIL::Module::Anyconst(RTLIL::IdString name, int width, const std::string &src)
2387 {
2388 RTLIL::SigSpec sig = addWire(NEW_ID, width);
2389 Cell *cell = addCell(name, ID($anyconst));
2390 cell->setParam(ID::WIDTH, width);
2391 cell->setPort(ID::Y, sig);
2392 cell->set_src_attribute(src);
2393 return sig;
2394 }
2395
2396 RTLIL::SigSpec RTLIL::Module::Anyseq(RTLIL::IdString name, int width, const std::string &src)
2397 {
2398 RTLIL::SigSpec sig = addWire(NEW_ID, width);
2399 Cell *cell = addCell(name, ID($anyseq));
2400 cell->setParam(ID::WIDTH, width);
2401 cell->setPort(ID::Y, sig);
2402 cell->set_src_attribute(src);
2403 return sig;
2404 }
2405
2406 RTLIL::SigSpec RTLIL::Module::Allconst(RTLIL::IdString name, int width, const std::string &src)
2407 {
2408 RTLIL::SigSpec sig = addWire(NEW_ID, width);
2409 Cell *cell = addCell(name, ID($allconst));
2410 cell->setParam(ID::WIDTH, width);
2411 cell->setPort(ID::Y, sig);
2412 cell->set_src_attribute(src);
2413 return sig;
2414 }
2415
2416 RTLIL::SigSpec RTLIL::Module::Allseq(RTLIL::IdString name, int width, const std::string &src)
2417 {
2418 RTLIL::SigSpec sig = addWire(NEW_ID, width);
2419 Cell *cell = addCell(name, ID($allseq));
2420 cell->setParam(ID::WIDTH, width);
2421 cell->setPort(ID::Y, sig);
2422 cell->set_src_attribute(src);
2423 return sig;
2424 }
2425
2426 RTLIL::SigSpec RTLIL::Module::Initstate(RTLIL::IdString name, const std::string &src)
2427 {
2428 RTLIL::SigSpec sig = addWire(NEW_ID);
2429 Cell *cell = addCell(name, ID($initstate));
2430 cell->setPort(ID::Y, sig);
2431 cell->set_src_attribute(src);
2432 return sig;
2433 }
2434
2435 RTLIL::Wire::Wire()
2436 {
2437 static unsigned int hashidx_count = 123456789;
2438 hashidx_count = mkhash_xorshift(hashidx_count);
2439 hashidx_ = hashidx_count;
2440
2441 module = nullptr;
2442 width = 1;
2443 start_offset = 0;
2444 port_id = 0;
2445 port_input = false;
2446 port_output = false;
2447 upto = false;
2448
2449 #ifdef WITH_PYTHON
2450 RTLIL::Wire::get_all_wires()->insert(std::pair<unsigned int, RTLIL::Wire*>(hashidx_, this));
2451 #endif
2452 }
2453
2454 RTLIL::Wire::~Wire()
2455 {
2456 #ifdef WITH_PYTHON
2457 RTLIL::Wire::get_all_wires()->erase(hashidx_);
2458 #endif
2459 }
2460
2461 #ifdef WITH_PYTHON
2462 static std::map<unsigned int, RTLIL::Wire*> all_wires;
2463 std::map<unsigned int, RTLIL::Wire*> *RTLIL::Wire::get_all_wires(void)
2464 {
2465 return &all_wires;
2466 }
2467 #endif
2468
2469 RTLIL::Memory::Memory()
2470 {
2471 static unsigned int hashidx_count = 123456789;
2472 hashidx_count = mkhash_xorshift(hashidx_count);
2473 hashidx_ = hashidx_count;
2474
2475 width = 1;
2476 start_offset = 0;
2477 size = 0;
2478 #ifdef WITH_PYTHON
2479 RTLIL::Memory::get_all_memorys()->insert(std::pair<unsigned int, RTLIL::Memory*>(hashidx_, this));
2480 #endif
2481 }
2482
2483 RTLIL::Cell::Cell() : module(nullptr)
2484 {
2485 static unsigned int hashidx_count = 123456789;
2486 hashidx_count = mkhash_xorshift(hashidx_count);
2487 hashidx_ = hashidx_count;
2488
2489 // log("#memtrace# %p\n", this);
2490 memhasher();
2491
2492 #ifdef WITH_PYTHON
2493 RTLIL::Cell::get_all_cells()->insert(std::pair<unsigned int, RTLIL::Cell*>(hashidx_, this));
2494 #endif
2495 }
2496
2497 RTLIL::Cell::~Cell()
2498 {
2499 #ifdef WITH_PYTHON
2500 RTLIL::Cell::get_all_cells()->erase(hashidx_);
2501 #endif
2502 }
2503
2504 #ifdef WITH_PYTHON
2505 static std::map<unsigned int, RTLIL::Cell*> all_cells;
2506 std::map<unsigned int, RTLIL::Cell*> *RTLIL::Cell::get_all_cells(void)
2507 {
2508 return &all_cells;
2509 }
2510 #endif
2511
2512 bool RTLIL::Cell::hasPort(RTLIL::IdString portname) const
2513 {
2514 return connections_.count(portname) != 0;
2515 }
2516
2517 void RTLIL::Cell::unsetPort(RTLIL::IdString portname)
2518 {
2519 RTLIL::SigSpec signal;
2520 auto conn_it = connections_.find(portname);
2521
2522 if (conn_it != connections_.end())
2523 {
2524 for (auto mon : module->monitors)
2525 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
2526
2527 if (module->design)
2528 for (auto mon : module->design->monitors)
2529 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
2530
2531 if (yosys_xtrace) {
2532 log("#X# Unconnect %s.%s.%s\n", log_id(this->module), log_id(this), log_id(portname));
2533 log_backtrace("-X- ", yosys_xtrace-1);
2534 }
2535
2536 connections_.erase(conn_it);
2537 }
2538 }
2539
2540 void RTLIL::Cell::setPort(RTLIL::IdString portname, RTLIL::SigSpec signal)
2541 {
2542 auto r = connections_.insert(portname);
2543 auto conn_it = r.first;
2544 if (!r.second && conn_it->second == signal)
2545 return;
2546
2547 for (auto mon : module->monitors)
2548 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
2549
2550 if (module->design)
2551 for (auto mon : module->design->monitors)
2552 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
2553
2554 if (yosys_xtrace) {
2555 log("#X# Connect %s.%s.%s = %s (%d)\n", log_id(this->module), log_id(this), log_id(portname), log_signal(signal), GetSize(signal));
2556 log_backtrace("-X- ", yosys_xtrace-1);
2557 }
2558
2559 conn_it->second = std::move(signal);
2560 }
2561
2562 const RTLIL::SigSpec &RTLIL::Cell::getPort(RTLIL::IdString portname) const
2563 {
2564 return connections_.at(portname);
2565 }
2566
2567 const dict<RTLIL::IdString, RTLIL::SigSpec> &RTLIL::Cell::connections() const
2568 {
2569 return connections_;
2570 }
2571
2572 bool RTLIL::Cell::known() const
2573 {
2574 if (yosys_celltypes.cell_known(type))
2575 return true;
2576 if (module && module->design && module->design->module(type))
2577 return true;
2578 return false;
2579 }
2580
2581 bool RTLIL::Cell::input(RTLIL::IdString portname) const
2582 {
2583 if (yosys_celltypes.cell_known(type))
2584 return yosys_celltypes.cell_input(type, portname);
2585 if (module && module->design) {
2586 RTLIL::Module *m = module->design->module(type);
2587 RTLIL::Wire *w = m ? m->wire(portname) : nullptr;
2588 return w && w->port_input;
2589 }
2590 return false;
2591 }
2592
2593 bool RTLIL::Cell::output(RTLIL::IdString portname) const
2594 {
2595 if (yosys_celltypes.cell_known(type))
2596 return yosys_celltypes.cell_output(type, portname);
2597 if (module && module->design) {
2598 RTLIL::Module *m = module->design->module(type);
2599 RTLIL::Wire *w = m ? m->wire(portname) : nullptr;
2600 return w && w->port_output;
2601 }
2602 return false;
2603 }
2604
2605 bool RTLIL::Cell::hasParam(RTLIL::IdString paramname) const
2606 {
2607 return parameters.count(paramname) != 0;
2608 }
2609
2610 void RTLIL::Cell::unsetParam(RTLIL::IdString paramname)
2611 {
2612 parameters.erase(paramname);
2613 }
2614
2615 void RTLIL::Cell::setParam(RTLIL::IdString paramname, RTLIL::Const value)
2616 {
2617 parameters[paramname] = std::move(value);
2618 }
2619
2620 const RTLIL::Const &RTLIL::Cell::getParam(RTLIL::IdString paramname) const
2621 {
2622 const auto &it = parameters.find(paramname);
2623 if (it != parameters.end())
2624 return it->second;
2625 if (module && module->design) {
2626 RTLIL::Module *m = module->design->module(type);
2627 if (m)
2628 return m->parameter_default_values.at(paramname);
2629 }
2630 throw std::out_of_range("Cell::getParam()");
2631 }
2632
2633 void RTLIL::Cell::sort()
2634 {
2635 connections_.sort(sort_by_id_str());
2636 parameters.sort(sort_by_id_str());
2637 attributes.sort(sort_by_id_str());
2638 }
2639
2640 void RTLIL::Cell::check()
2641 {
2642 #ifndef NDEBUG
2643 InternalCellChecker checker(NULL, this);
2644 checker.check();
2645 #endif
2646 }
2647
2648 void RTLIL::Cell::fixup_parameters(bool set_a_signed, bool set_b_signed)
2649 {
2650 if (!type.begins_with("$") || type.begins_with("$_") || type.begins_with("$paramod") || type.begins_with("$fmcombine") ||
2651 type.begins_with("$verific$") || type.begins_with("$array:") || type.begins_with("$extern:"))
2652 return;
2653
2654 if (type == ID($mux) || type == ID($pmux)) {
2655 parameters[ID::WIDTH] = GetSize(connections_[ID::Y]);
2656 if (type == ID($pmux))
2657 parameters[ID::S_WIDTH] = GetSize(connections_[ID::S]);
2658 check();
2659 return;
2660 }
2661
2662 if (type == ID($lut) || type == ID($sop)) {
2663 parameters[ID::WIDTH] = GetSize(connections_[ID::A]);
2664 return;
2665 }
2666
2667 if (type == ID($fa)) {
2668 parameters[ID::WIDTH] = GetSize(connections_[ID::Y]);
2669 return;
2670 }
2671
2672 if (type == ID($lcu)) {
2673 parameters[ID::WIDTH] = GetSize(connections_[ID::CO]);
2674 return;
2675 }
2676
2677 bool signedness_ab = !type.in(ID($slice), ID($concat), ID($macc));
2678
2679 if (connections_.count(ID::A)) {
2680 if (signedness_ab) {
2681 if (set_a_signed)
2682 parameters[ID::A_SIGNED] = true;
2683 else if (parameters.count(ID::A_SIGNED) == 0)
2684 parameters[ID::A_SIGNED] = false;
2685 }
2686 parameters[ID::A_WIDTH] = GetSize(connections_[ID::A]);
2687 }
2688
2689 if (connections_.count(ID::B)) {
2690 if (signedness_ab) {
2691 if (set_b_signed)
2692 parameters[ID::B_SIGNED] = true;
2693 else if (parameters.count(ID::B_SIGNED) == 0)
2694 parameters[ID::B_SIGNED] = false;
2695 }
2696 parameters[ID::B_WIDTH] = GetSize(connections_[ID::B]);
2697 }
2698
2699 if (connections_.count(ID::Y))
2700 parameters[ID::Y_WIDTH] = GetSize(connections_[ID::Y]);
2701
2702 if (connections_.count(ID::Q))
2703 parameters[ID::WIDTH] = GetSize(connections_[ID::Q]);
2704
2705 check();
2706 }
2707
2708 RTLIL::SigChunk::SigChunk()
2709 {
2710 wire = NULL;
2711 width = 0;
2712 offset = 0;
2713 }
2714
2715 RTLIL::SigChunk::SigChunk(const RTLIL::Const &value)
2716 {
2717 wire = NULL;
2718 data = value.bits;
2719 width = GetSize(data);
2720 offset = 0;
2721 }
2722
2723 RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire)
2724 {
2725 log_assert(wire != nullptr);
2726 this->wire = wire;
2727 this->width = wire->width;
2728 this->offset = 0;
2729 }
2730
2731 RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire, int offset, int width)
2732 {
2733 log_assert(wire != nullptr);
2734 this->wire = wire;
2735 this->width = width;
2736 this->offset = offset;
2737 }
2738
2739 RTLIL::SigChunk::SigChunk(const std::string &str)
2740 {
2741 wire = NULL;
2742 data = RTLIL::Const(str).bits;
2743 width = GetSize(data);
2744 offset = 0;
2745 }
2746
2747 RTLIL::SigChunk::SigChunk(int val, int width)
2748 {
2749 wire = NULL;
2750 data = RTLIL::Const(val, width).bits;
2751 this->width = GetSize(data);
2752 offset = 0;
2753 }
2754
2755 RTLIL::SigChunk::SigChunk(RTLIL::State bit, int width)
2756 {
2757 wire = NULL;
2758 data = RTLIL::Const(bit, width).bits;
2759 this->width = GetSize(data);
2760 offset = 0;
2761 }
2762
2763 RTLIL::SigChunk::SigChunk(const RTLIL::SigBit &bit)
2764 {
2765 wire = bit.wire;
2766 offset = 0;
2767 if (wire == NULL)
2768 data = RTLIL::Const(bit.data).bits;
2769 else
2770 offset = bit.offset;
2771 width = 1;
2772 }
2773
2774 RTLIL::SigChunk::SigChunk(const RTLIL::SigChunk &sigchunk)
2775 {
2776 *this = sigchunk;
2777 }
2778
2779 RTLIL::SigChunk RTLIL::SigChunk::extract(int offset, int length) const
2780 {
2781 RTLIL::SigChunk ret;
2782 if (wire) {
2783 ret.wire = wire;
2784 ret.offset = this->offset + offset;
2785 ret.width = length;
2786 } else {
2787 for (int i = 0; i < length; i++)
2788 ret.data.push_back(data[offset+i]);
2789 ret.width = length;
2790 }
2791 return ret;
2792 }
2793
2794 bool RTLIL::SigChunk::operator <(const RTLIL::SigChunk &other) const
2795 {
2796 if (wire && other.wire)
2797 if (wire->name != other.wire->name)
2798 return wire->name < other.wire->name;
2799
2800 if (wire != other.wire)
2801 return wire < other.wire;
2802
2803 if (offset != other.offset)
2804 return offset < other.offset;
2805
2806 if (width != other.width)
2807 return width < other.width;
2808
2809 return data < other.data;
2810 }
2811
2812 bool RTLIL::SigChunk::operator ==(const RTLIL::SigChunk &other) const
2813 {
2814 return wire == other.wire && width == other.width && offset == other.offset && data == other.data;
2815 }
2816
2817 bool RTLIL::SigChunk::operator !=(const RTLIL::SigChunk &other) const
2818 {
2819 if (*this == other)
2820 return false;
2821 return true;
2822 }
2823
2824 RTLIL::SigSpec::SigSpec()
2825 {
2826 width_ = 0;
2827 hash_ = 0;
2828 }
2829
2830 RTLIL::SigSpec::SigSpec(const RTLIL::SigSpec &other)
2831 {
2832 *this = other;
2833 }
2834
2835 RTLIL::SigSpec::SigSpec(std::initializer_list<RTLIL::SigSpec> parts)
2836 {
2837 cover("kernel.rtlil.sigspec.init.list");
2838
2839 width_ = 0;
2840 hash_ = 0;
2841
2842 log_assert(parts.size() > 0);
2843 auto ie = parts.begin();
2844 auto it = ie + parts.size() - 1;
2845 while (it >= ie)
2846 append(*it--);
2847 }
2848
2849 RTLIL::SigSpec &RTLIL::SigSpec::operator=(const RTLIL::SigSpec &other)
2850 {
2851 cover("kernel.rtlil.sigspec.assign");
2852
2853 width_ = other.width_;
2854 hash_ = other.hash_;
2855 chunks_ = other.chunks_;
2856 bits_ = other.bits_;
2857 return *this;
2858 }
2859
2860 RTLIL::SigSpec::SigSpec(const RTLIL::Const &value)
2861 {
2862 cover("kernel.rtlil.sigspec.init.const");
2863
2864 chunks_.emplace_back(value);
2865 width_ = chunks_.back().width;
2866 hash_ = 0;
2867 check();
2868 }
2869
2870 RTLIL::SigSpec::SigSpec(const RTLIL::SigChunk &chunk)
2871 {
2872 cover("kernel.rtlil.sigspec.init.chunk");
2873
2874 chunks_.emplace_back(chunk);
2875 width_ = chunks_.back().width;
2876 hash_ = 0;
2877 check();
2878 }
2879
2880 RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire)
2881 {
2882 cover("kernel.rtlil.sigspec.init.wire");
2883
2884 chunks_.emplace_back(wire);
2885 width_ = chunks_.back().width;
2886 hash_ = 0;
2887 check();
2888 }
2889
2890 RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire, int offset, int width)
2891 {
2892 cover("kernel.rtlil.sigspec.init.wire_part");
2893
2894 chunks_.emplace_back(wire, offset, width);
2895 width_ = chunks_.back().width;
2896 hash_ = 0;
2897 check();
2898 }
2899
2900 RTLIL::SigSpec::SigSpec(const std::string &str)
2901 {
2902 cover("kernel.rtlil.sigspec.init.str");
2903
2904 chunks_.emplace_back(str);
2905 width_ = chunks_.back().width;
2906 hash_ = 0;
2907 check();
2908 }
2909
2910 RTLIL::SigSpec::SigSpec(int val, int width)
2911 {
2912 cover("kernel.rtlil.sigspec.init.int");
2913
2914 chunks_.emplace_back(val, width);
2915 width_ = width;
2916 hash_ = 0;
2917 check();
2918 }
2919
2920 RTLIL::SigSpec::SigSpec(RTLIL::State bit, int width)
2921 {
2922 cover("kernel.rtlil.sigspec.init.state");
2923
2924 chunks_.emplace_back(bit, width);
2925 width_ = width;
2926 hash_ = 0;
2927 check();
2928 }
2929
2930 RTLIL::SigSpec::SigSpec(const RTLIL::SigBit &bit, int width)
2931 {
2932 cover("kernel.rtlil.sigspec.init.bit");
2933
2934 if (bit.wire == NULL)
2935 chunks_.emplace_back(bit.data, width);
2936 else
2937 for (int i = 0; i < width; i++)
2938 chunks_.push_back(bit);
2939 width_ = width;
2940 hash_ = 0;
2941 check();
2942 }
2943
2944 RTLIL::SigSpec::SigSpec(const std::vector<RTLIL::SigChunk> &chunks)
2945 {
2946 cover("kernel.rtlil.sigspec.init.stdvec_chunks");
2947
2948 width_ = 0;
2949 hash_ = 0;
2950 for (const auto &c : chunks)
2951 append(c);
2952 check();
2953 }
2954
2955 RTLIL::SigSpec::SigSpec(const std::vector<RTLIL::SigBit> &bits)
2956 {
2957 cover("kernel.rtlil.sigspec.init.stdvec_bits");
2958
2959 width_ = 0;
2960 hash_ = 0;
2961 for (const auto &bit : bits)
2962 append(bit);
2963 check();
2964 }
2965
2966 RTLIL::SigSpec::SigSpec(const pool<RTLIL::SigBit> &bits)
2967 {
2968 cover("kernel.rtlil.sigspec.init.pool_bits");
2969
2970 width_ = 0;
2971 hash_ = 0;
2972 for (const auto &bit : bits)
2973 append(bit);
2974 check();
2975 }
2976
2977 RTLIL::SigSpec::SigSpec(const std::set<RTLIL::SigBit> &bits)
2978 {
2979 cover("kernel.rtlil.sigspec.init.stdset_bits");
2980
2981 width_ = 0;
2982 hash_ = 0;
2983 for (const auto &bit : bits)
2984 append(bit);
2985 check();
2986 }
2987
2988 RTLIL::SigSpec::SigSpec(bool bit)
2989 {
2990 cover("kernel.rtlil.sigspec.init.bool");
2991
2992 width_ = 0;
2993 hash_ = 0;
2994 append(SigBit(bit));
2995 check();
2996 }
2997
2998 void RTLIL::SigSpec::pack() const
2999 {
3000 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
3001
3002 if (that->bits_.empty())
3003 return;
3004
3005 cover("kernel.rtlil.sigspec.convert.pack");
3006 log_assert(that->chunks_.empty());
3007
3008 std::vector<RTLIL::SigBit> old_bits;
3009 old_bits.swap(that->bits_);
3010
3011 RTLIL::SigChunk *last = NULL;
3012 int last_end_offset = 0;
3013
3014 for (auto &bit : old_bits) {
3015 if (last && bit.wire == last->wire) {
3016 if (bit.wire == NULL) {
3017 last->data.push_back(bit.data);
3018 last->width++;
3019 continue;
3020 } else if (last_end_offset == bit.offset) {
3021 last_end_offset++;
3022 last->width++;
3023 continue;
3024 }
3025 }
3026 that->chunks_.push_back(bit);
3027 last = &that->chunks_.back();
3028 last_end_offset = bit.offset + 1;
3029 }
3030
3031 check();
3032 }
3033
3034 void RTLIL::SigSpec::unpack() const
3035 {
3036 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
3037
3038 if (that->chunks_.empty())
3039 return;
3040
3041 cover("kernel.rtlil.sigspec.convert.unpack");
3042 log_assert(that->bits_.empty());
3043
3044 that->bits_.reserve(that->width_);
3045 for (auto &c : that->chunks_)
3046 for (int i = 0; i < c.width; i++)
3047 that->bits_.emplace_back(c, i);
3048
3049 that->chunks_.clear();
3050 that->hash_ = 0;
3051 }
3052
3053 void RTLIL::SigSpec::updhash() const
3054 {
3055 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
3056
3057 if (that->hash_ != 0)
3058 return;
3059
3060 cover("kernel.rtlil.sigspec.hash");
3061 that->pack();
3062
3063 that->hash_ = mkhash_init;
3064 for (auto &c : that->chunks_)
3065 if (c.wire == NULL) {
3066 for (auto &v : c.data)
3067 that->hash_ = mkhash(that->hash_, v);
3068 } else {
3069 that->hash_ = mkhash(that->hash_, c.wire->name.index_);
3070 that->hash_ = mkhash(that->hash_, c.offset);
3071 that->hash_ = mkhash(that->hash_, c.width);
3072 }
3073
3074 if (that->hash_ == 0)
3075 that->hash_ = 1;
3076 }
3077
3078 void RTLIL::SigSpec::sort()
3079 {
3080 unpack();
3081 cover("kernel.rtlil.sigspec.sort");
3082 std::sort(bits_.begin(), bits_.end());
3083 }
3084
3085 void RTLIL::SigSpec::sort_and_unify()
3086 {
3087 unpack();
3088 cover("kernel.rtlil.sigspec.sort_and_unify");
3089
3090 // A copy of the bits vector is used to prevent duplicating the logic from
3091 // SigSpec::SigSpec(std::vector<SigBit>). This incurrs an extra copy but
3092 // that isn't showing up as significant in profiles.
3093 std::vector<SigBit> unique_bits = bits_;
3094 std::sort(unique_bits.begin(), unique_bits.end());
3095 auto last = std::unique(unique_bits.begin(), unique_bits.end());
3096 unique_bits.erase(last, unique_bits.end());
3097
3098 *this = unique_bits;
3099 }
3100
3101 void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with)
3102 {
3103 replace(pattern, with, this);
3104 }
3105
3106 void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with, RTLIL::SigSpec *other) const
3107 {
3108 log_assert(other != NULL);
3109 log_assert(width_ == other->width_);
3110 log_assert(pattern.width_ == with.width_);
3111
3112 pattern.unpack();
3113 with.unpack();
3114 unpack();
3115 other->unpack();
3116
3117 for (int i = 0; i < GetSize(pattern.bits_); i++) {
3118 if (pattern.bits_[i].wire != NULL) {
3119 for (int j = 0; j < GetSize(bits_); j++) {
3120 if (bits_[j] == pattern.bits_[i]) {
3121 other->bits_[j] = with.bits_[i];
3122 }
3123 }
3124 }
3125 }
3126
3127 other->check();
3128 }
3129
3130 void RTLIL::SigSpec::replace(const dict<RTLIL::SigBit, RTLIL::SigBit> &rules)
3131 {
3132 replace(rules, this);
3133 }
3134
3135 void RTLIL::SigSpec::replace(const dict<RTLIL::SigBit, RTLIL::SigBit> &rules, RTLIL::SigSpec *other) const
3136 {
3137 cover("kernel.rtlil.sigspec.replace_dict");
3138
3139 log_assert(other != NULL);
3140 log_assert(width_ == other->width_);
3141
3142 if (rules.empty()) return;
3143 unpack();
3144 other->unpack();
3145
3146 for (int i = 0; i < GetSize(bits_); i++) {
3147 auto it = rules.find(bits_[i]);
3148 if (it != rules.end())
3149 other->bits_[i] = it->second;
3150 }
3151
3152 other->check();
3153 }
3154
3155 void RTLIL::SigSpec::replace(const std::map<RTLIL::SigBit, RTLIL::SigBit> &rules)
3156 {
3157 replace(rules, this);
3158 }
3159
3160 void RTLIL::SigSpec::replace(const std::map<RTLIL::SigBit, RTLIL::SigBit> &rules, RTLIL::SigSpec *other) const
3161 {
3162 cover("kernel.rtlil.sigspec.replace_map");
3163
3164 log_assert(other != NULL);
3165 log_assert(width_ == other->width_);
3166
3167 if (rules.empty()) return;
3168 unpack();
3169 other->unpack();
3170
3171 for (int i = 0; i < GetSize(bits_); i++) {
3172 auto it = rules.find(bits_[i]);
3173 if (it != rules.end())
3174 other->bits_[i] = it->second;
3175 }
3176
3177 other->check();
3178 }
3179
3180 void RTLIL::SigSpec::remove(const RTLIL::SigSpec &pattern)
3181 {
3182 remove2(pattern, NULL);
3183 }
3184
3185 void RTLIL::SigSpec::remove(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other) const
3186 {
3187 RTLIL::SigSpec tmp = *this;
3188 tmp.remove2(pattern, other);
3189 }
3190
3191 void RTLIL::SigSpec::remove2(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other)
3192 {
3193 if (other)
3194 cover("kernel.rtlil.sigspec.remove_other");
3195 else
3196 cover("kernel.rtlil.sigspec.remove");
3197
3198 unpack();
3199 if (other != NULL) {
3200 log_assert(width_ == other->width_);
3201 other->unpack();
3202 }
3203
3204 for (int i = GetSize(bits_) - 1; i >= 0; i--)
3205 {
3206 if (bits_[i].wire == NULL) continue;
3207
3208 for (auto &pattern_chunk : pattern.chunks())
3209 if (bits_[i].wire == pattern_chunk.wire &&
3210 bits_[i].offset >= pattern_chunk.offset &&
3211 bits_[i].offset < pattern_chunk.offset + pattern_chunk.width) {
3212 bits_.erase(bits_.begin() + i);
3213 width_--;
3214 if (other != NULL) {
3215 other->bits_.erase(other->bits_.begin() + i);
3216 other->width_--;
3217 }
3218 break;
3219 }
3220 }
3221
3222 check();
3223 }
3224
3225 void RTLIL::SigSpec::remove(const pool<RTLIL::SigBit> &pattern)
3226 {
3227 remove2(pattern, NULL);
3228 }
3229
3230 void RTLIL::SigSpec::remove(const pool<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other) const
3231 {
3232 RTLIL::SigSpec tmp = *this;
3233 tmp.remove2(pattern, other);
3234 }
3235
3236 void RTLIL::SigSpec::remove2(const pool<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other)
3237 {
3238 if (other)
3239 cover("kernel.rtlil.sigspec.remove_other");
3240 else
3241 cover("kernel.rtlil.sigspec.remove");
3242
3243 unpack();
3244
3245 if (other != NULL) {
3246 log_assert(width_ == other->width_);
3247 other->unpack();
3248 }
3249
3250 for (int i = GetSize(bits_) - 1; i >= 0; i--) {
3251 if (bits_[i].wire != NULL && pattern.count(bits_[i])) {
3252 bits_.erase(bits_.begin() + i);
3253 width_--;
3254 if (other != NULL) {
3255 other->bits_.erase(other->bits_.begin() + i);
3256 other->width_--;
3257 }
3258 }
3259 }
3260
3261 check();
3262 }
3263
3264 void RTLIL::SigSpec::remove2(const std::set<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other)
3265 {
3266 if (other)
3267 cover("kernel.rtlil.sigspec.remove_other");
3268 else
3269 cover("kernel.rtlil.sigspec.remove");
3270
3271 unpack();
3272
3273 if (other != NULL) {
3274 log_assert(width_ == other->width_);
3275 other->unpack();
3276 }
3277
3278 for (int i = GetSize(bits_) - 1; i >= 0; i--) {
3279 if (bits_[i].wire != NULL && pattern.count(bits_[i])) {
3280 bits_.erase(bits_.begin() + i);
3281 width_--;
3282 if (other != NULL) {
3283 other->bits_.erase(other->bits_.begin() + i);
3284 other->width_--;
3285 }
3286 }
3287 }
3288
3289 check();
3290 }
3291
3292 RTLIL::SigSpec RTLIL::SigSpec::extract(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec *other) const
3293 {
3294 if (other)
3295 cover("kernel.rtlil.sigspec.extract_other");
3296 else
3297 cover("kernel.rtlil.sigspec.extract");
3298
3299 log_assert(other == NULL || width_ == other->width_);
3300
3301 RTLIL::SigSpec ret;
3302 std::vector<RTLIL::SigBit> bits_match = to_sigbit_vector();
3303
3304 for (auto& pattern_chunk : pattern.chunks()) {
3305 if (other) {
3306 std::vector<RTLIL::SigBit> bits_other = other->to_sigbit_vector();
3307 for (int i = 0; i < width_; i++)
3308 if (bits_match[i].wire &&
3309 bits_match[i].wire == pattern_chunk.wire &&
3310 bits_match[i].offset >= pattern_chunk.offset &&
3311 bits_match[i].offset < pattern_chunk.offset + pattern_chunk.width)
3312 ret.append(bits_other[i]);
3313 } else {
3314 for (int i = 0; i < width_; i++)
3315 if (bits_match[i].wire &&
3316 bits_match[i].wire == pattern_chunk.wire &&
3317 bits_match[i].offset >= pattern_chunk.offset &&
3318 bits_match[i].offset < pattern_chunk.offset + pattern_chunk.width)
3319 ret.append(bits_match[i]);
3320 }
3321 }
3322
3323 ret.check();
3324 return ret;
3325 }
3326
3327 RTLIL::SigSpec RTLIL::SigSpec::extract(const pool<RTLIL::SigBit> &pattern, const RTLIL::SigSpec *other) const
3328 {
3329 if (other)
3330 cover("kernel.rtlil.sigspec.extract_other");
3331 else
3332 cover("kernel.rtlil.sigspec.extract");
3333
3334 log_assert(other == NULL || width_ == other->width_);
3335
3336 std::vector<RTLIL::SigBit> bits_match = to_sigbit_vector();
3337 RTLIL::SigSpec ret;
3338
3339 if (other) {
3340 std::vector<RTLIL::SigBit> bits_other = other->to_sigbit_vector();
3341 for (int i = 0; i < width_; i++)
3342 if (bits_match[i].wire && pattern.count(bits_match[i]))
3343 ret.append(bits_other[i]);
3344 } else {
3345 for (int i = 0; i < width_; i++)
3346 if (bits_match[i].wire && pattern.count(bits_match[i]))
3347 ret.append(bits_match[i]);
3348 }
3349
3350 ret.check();
3351 return ret;
3352 }
3353
3354 void RTLIL::SigSpec::replace(int offset, const RTLIL::SigSpec &with)
3355 {
3356 cover("kernel.rtlil.sigspec.replace_pos");
3357
3358 unpack();
3359 with.unpack();
3360
3361 log_assert(offset >= 0);
3362 log_assert(with.width_ >= 0);
3363 log_assert(offset+with.width_ <= width_);
3364
3365 for (int i = 0; i < with.width_; i++)
3366 bits_.at(offset + i) = with.bits_.at(i);
3367
3368 check();
3369 }
3370
3371 void RTLIL::SigSpec::remove_const()
3372 {
3373 if (packed())
3374 {
3375 cover("kernel.rtlil.sigspec.remove_const.packed");
3376
3377 std::vector<RTLIL::SigChunk> new_chunks;
3378 new_chunks.reserve(GetSize(chunks_));
3379
3380 width_ = 0;
3381 for (auto &chunk : chunks_)
3382 if (chunk.wire != NULL) {
3383 new_chunks.push_back(chunk);
3384 width_ += chunk.width;
3385 }
3386
3387 chunks_.swap(new_chunks);
3388 }
3389 else
3390 {
3391 cover("kernel.rtlil.sigspec.remove_const.unpacked");
3392
3393 std::vector<RTLIL::SigBit> new_bits;
3394 new_bits.reserve(width_);
3395
3396 for (auto &bit : bits_)
3397 if (bit.wire != NULL)
3398 new_bits.push_back(bit);
3399
3400 bits_.swap(new_bits);
3401 width_ = bits_.size();
3402 }
3403
3404 check();
3405 }
3406
3407 void RTLIL::SigSpec::remove(int offset, int length)
3408 {
3409 cover("kernel.rtlil.sigspec.remove_pos");
3410
3411 unpack();
3412
3413 log_assert(offset >= 0);
3414 log_assert(length >= 0);
3415 log_assert(offset + length <= width_);
3416
3417 bits_.erase(bits_.begin() + offset, bits_.begin() + offset + length);
3418 width_ = bits_.size();
3419
3420 check();
3421 }
3422
3423 RTLIL::SigSpec RTLIL::SigSpec::extract(int offset, int length) const
3424 {
3425 unpack();
3426 cover("kernel.rtlil.sigspec.extract_pos");
3427 return std::vector<RTLIL::SigBit>(bits_.begin() + offset, bits_.begin() + offset + length);
3428 }
3429
3430 void RTLIL::SigSpec::append(const RTLIL::SigSpec &signal)
3431 {
3432 if (signal.width_ == 0)
3433 return;
3434
3435 if (width_ == 0) {
3436 *this = signal;
3437 return;
3438 }
3439
3440 cover("kernel.rtlil.sigspec.append");
3441
3442 if (packed() != signal.packed()) {
3443 pack();
3444 signal.pack();
3445 }
3446
3447 if (packed())
3448 for (auto &other_c : signal.chunks_)
3449 {
3450 auto &my_last_c = chunks_.back();
3451 if (my_last_c.wire == NULL && other_c.wire == NULL) {
3452 auto &this_data = my_last_c.data;
3453 auto &other_data = other_c.data;
3454 this_data.insert(this_data.end(), other_data.begin(), other_data.end());
3455 my_last_c.width += other_c.width;
3456 } else
3457 if (my_last_c.wire == other_c.wire && my_last_c.offset + my_last_c.width == other_c.offset) {
3458 my_last_c.width += other_c.width;
3459 } else
3460 chunks_.push_back(other_c);
3461 }
3462 else
3463 bits_.insert(bits_.end(), signal.bits_.begin(), signal.bits_.end());
3464
3465 width_ += signal.width_;
3466 check();
3467 }
3468
3469 void RTLIL::SigSpec::append(const RTLIL::SigBit &bit)
3470 {
3471 if (packed())
3472 {
3473 cover("kernel.rtlil.sigspec.append_bit.packed");
3474
3475 if (chunks_.size() == 0)
3476 chunks_.push_back(bit);
3477 else
3478 if (bit.wire == NULL)
3479 if (chunks_.back().wire == NULL) {
3480 chunks_.back().data.push_back(bit.data);
3481 chunks_.back().width++;
3482 } else
3483 chunks_.push_back(bit);
3484 else
3485 if (chunks_.back().wire == bit.wire && chunks_.back().offset + chunks_.back().width == bit.offset)
3486 chunks_.back().width++;
3487 else
3488 chunks_.push_back(bit);
3489 }
3490 else
3491 {
3492 cover("kernel.rtlil.sigspec.append_bit.unpacked");
3493 bits_.push_back(bit);
3494 }
3495
3496 width_++;
3497 check();
3498 }
3499
3500 void RTLIL::SigSpec::extend_u0(int width, bool is_signed)
3501 {
3502 cover("kernel.rtlil.sigspec.extend_u0");
3503
3504 pack();
3505
3506 if (width_ > width)
3507 remove(width, width_ - width);
3508
3509 if (width_ < width) {
3510 RTLIL::SigBit padding = width_ > 0 ? (*this)[width_ - 1] : RTLIL::State::Sx;
3511 if (!is_signed)
3512 padding = RTLIL::State::S0;
3513 while (width_ < width)
3514 append(padding);
3515 }
3516
3517 }
3518
3519 RTLIL::SigSpec RTLIL::SigSpec::repeat(int num) const
3520 {
3521 cover("kernel.rtlil.sigspec.repeat");
3522
3523 RTLIL::SigSpec sig;
3524 for (int i = 0; i < num; i++)
3525 sig.append(*this);
3526 return sig;
3527 }
3528
3529 #ifndef NDEBUG
3530 void RTLIL::SigSpec::check() const
3531 {
3532 if (width_ > 64)
3533 {
3534 cover("kernel.rtlil.sigspec.check.skip");
3535 }
3536 else if (packed())
3537 {
3538 cover("kernel.rtlil.sigspec.check.packed");
3539
3540 int w = 0;
3541 for (size_t i = 0; i < chunks_.size(); i++) {
3542 const RTLIL::SigChunk &chunk = chunks_[i];
3543 if (chunk.wire == NULL) {
3544 if (i > 0)
3545 log_assert(chunks_[i-1].wire != NULL);
3546 log_assert(chunk.offset == 0);
3547 log_assert(chunk.data.size() == (size_t)chunk.width);
3548 } else {
3549 if (i > 0 && chunks_[i-1].wire == chunk.wire)
3550 log_assert(chunk.offset != chunks_[i-1].offset + chunks_[i-1].width);
3551 log_assert(chunk.offset >= 0);
3552 log_assert(chunk.width >= 0);
3553 log_assert(chunk.offset + chunk.width <= chunk.wire->width);
3554 log_assert(chunk.data.size() == 0);
3555 }
3556 w += chunk.width;
3557 }
3558 log_assert(w == width_);
3559 log_assert(bits_.empty());
3560 }
3561 else
3562 {
3563 cover("kernel.rtlil.sigspec.check.unpacked");
3564
3565 log_assert(width_ == GetSize(bits_));
3566 log_assert(chunks_.empty());
3567 }
3568 }
3569 #endif
3570
3571 bool RTLIL::SigSpec::operator <(const RTLIL::SigSpec &other) const
3572 {
3573 cover("kernel.rtlil.sigspec.comp_lt");
3574
3575 if (this == &other)
3576 return false;
3577
3578 if (width_ != other.width_)
3579 return width_ < other.width_;
3580
3581 pack();
3582 other.pack();
3583
3584 if (chunks_.size() != other.chunks_.size())
3585 return chunks_.size() < other.chunks_.size();
3586
3587 updhash();
3588 other.updhash();
3589
3590 if (hash_ != other.hash_)
3591 return hash_ < other.hash_;
3592
3593 for (size_t i = 0; i < chunks_.size(); i++)
3594 if (chunks_[i] != other.chunks_[i]) {
3595 cover("kernel.rtlil.sigspec.comp_lt.hash_collision");
3596 return chunks_[i] < other.chunks_[i];
3597 }
3598
3599 cover("kernel.rtlil.sigspec.comp_lt.equal");
3600 return false;
3601 }
3602
3603 bool RTLIL::SigSpec::operator ==(const RTLIL::SigSpec &other) const
3604 {
3605 cover("kernel.rtlil.sigspec.comp_eq");
3606
3607 if (this == &other)
3608 return true;
3609
3610 if (width_ != other.width_)
3611 return false;
3612
3613 // Without this, SigSpec() == SigSpec(State::S0, 0) will fail
3614 // since the RHS will contain one SigChunk of width 0 causing
3615 // the size check below to fail
3616 if (width_ == 0)
3617 return true;
3618
3619 pack();
3620 other.pack();
3621
3622 if (chunks_.size() != other.chunks_.size())
3623 return false;
3624
3625 updhash();
3626 other.updhash();
3627
3628 if (hash_ != other.hash_)
3629 return false;
3630
3631 for (size_t i = 0; i < chunks_.size(); i++)
3632 if (chunks_[i] != other.chunks_[i]) {
3633 cover("kernel.rtlil.sigspec.comp_eq.hash_collision");
3634 return false;
3635 }
3636
3637 cover("kernel.rtlil.sigspec.comp_eq.equal");
3638 return true;
3639 }
3640
3641 bool RTLIL::SigSpec::is_wire() const
3642 {
3643 cover("kernel.rtlil.sigspec.is_wire");
3644
3645 pack();
3646 return GetSize(chunks_) == 1 && chunks_[0].wire && chunks_[0].wire->width == width_;
3647 }
3648
3649 bool RTLIL::SigSpec::is_chunk() const
3650 {
3651 cover("kernel.rtlil.sigspec.is_chunk");
3652
3653 pack();
3654 return GetSize(chunks_) == 1;
3655 }
3656
3657 bool RTLIL::SigSpec::is_fully_const() const
3658 {
3659 cover("kernel.rtlil.sigspec.is_fully_const");
3660
3661 pack();
3662 for (auto it = chunks_.begin(); it != chunks_.end(); it++)
3663 if (it->width > 0 && it->wire != NULL)
3664 return false;
3665 return true;
3666 }
3667
3668 bool RTLIL::SigSpec::is_fully_zero() const
3669 {
3670 cover("kernel.rtlil.sigspec.is_fully_zero");
3671
3672 pack();
3673 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
3674 if (it->width > 0 && it->wire != NULL)
3675 return false;
3676 for (size_t i = 0; i < it->data.size(); i++)
3677 if (it->data[i] != RTLIL::State::S0)
3678 return false;
3679 }
3680 return true;
3681 }
3682
3683 bool RTLIL::SigSpec::is_fully_ones() const
3684 {
3685 cover("kernel.rtlil.sigspec.is_fully_ones");
3686
3687 pack();
3688 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
3689 if (it->width > 0 && it->wire != NULL)
3690 return false;
3691 for (size_t i = 0; i < it->data.size(); i++)
3692 if (it->data[i] != RTLIL::State::S1)
3693 return false;
3694 }
3695 return true;
3696 }
3697
3698 bool RTLIL::SigSpec::is_fully_def() const
3699 {
3700 cover("kernel.rtlil.sigspec.is_fully_def");
3701
3702 pack();
3703 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
3704 if (it->width > 0 && it->wire != NULL)
3705 return false;
3706 for (size_t i = 0; i < it->data.size(); i++)
3707 if (it->data[i] != RTLIL::State::S0 && it->data[i] != RTLIL::State::S1)
3708 return false;
3709 }
3710 return true;
3711 }
3712
3713 bool RTLIL::SigSpec::is_fully_undef() const
3714 {
3715 cover("kernel.rtlil.sigspec.is_fully_undef");
3716
3717 pack();
3718 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
3719 if (it->width > 0 && it->wire != NULL)
3720 return false;
3721 for (size_t i = 0; i < it->data.size(); i++)
3722 if (it->data[i] != RTLIL::State::Sx && it->data[i] != RTLIL::State::Sz)
3723 return false;
3724 }
3725 return true;
3726 }
3727
3728 bool RTLIL::SigSpec::has_const() const
3729 {
3730 cover("kernel.rtlil.sigspec.has_const");
3731
3732 pack();
3733 for (auto it = chunks_.begin(); it != chunks_.end(); it++)
3734 if (it->width > 0 && it->wire == NULL)
3735 return true;
3736 return false;
3737 }
3738
3739 bool RTLIL::SigSpec::has_marked_bits() const
3740 {
3741 cover("kernel.rtlil.sigspec.has_marked_bits");
3742
3743 pack();
3744 for (auto it = chunks_.begin(); it != chunks_.end(); it++)
3745 if (it->width > 0 && it->wire == NULL) {
3746 for (size_t i = 0; i < it->data.size(); i++)
3747 if (it->data[i] == RTLIL::State::Sm)
3748 return true;
3749 }
3750 return false;
3751 }
3752
3753 bool RTLIL::SigSpec::as_bool() const
3754 {
3755 cover("kernel.rtlil.sigspec.as_bool");
3756
3757 pack();
3758 log_assert(is_fully_const() && GetSize(chunks_) <= 1);
3759 if (width_)
3760 return RTLIL::Const(chunks_[0].data).as_bool();
3761 return false;
3762 }
3763
3764 int RTLIL::SigSpec::as_int(bool is_signed) const
3765 {
3766 cover("kernel.rtlil.sigspec.as_int");
3767
3768 pack();
3769 log_assert(is_fully_const() && GetSize(chunks_) <= 1);
3770 if (width_)
3771 return RTLIL::Const(chunks_[0].data).as_int(is_signed);
3772 return 0;
3773 }
3774
3775 std::string RTLIL::SigSpec::as_string() const
3776 {
3777 cover("kernel.rtlil.sigspec.as_string");
3778
3779 pack();
3780 std::string str;
3781 str.reserve(size());
3782 for (size_t i = chunks_.size(); i > 0; i--) {
3783 const RTLIL::SigChunk &chunk = chunks_[i-1];
3784 if (chunk.wire != NULL)
3785 str.append(chunk.width, '?');
3786 else
3787 str += RTLIL::Const(chunk.data).as_string();
3788 }
3789 return str;
3790 }
3791
3792 RTLIL::Const RTLIL::SigSpec::as_const() const
3793 {
3794 cover("kernel.rtlil.sigspec.as_const");
3795
3796 pack();
3797 log_assert(is_fully_const() && GetSize(chunks_) <= 1);
3798 if (width_)
3799 return chunks_[0].data;
3800 return RTLIL::Const();
3801 }
3802
3803 RTLIL::Wire *RTLIL::SigSpec::as_wire() const
3804 {
3805 cover("kernel.rtlil.sigspec.as_wire");
3806
3807 pack();
3808 log_assert(is_wire());
3809 return chunks_[0].wire;
3810 }
3811
3812 RTLIL::SigChunk RTLIL::SigSpec::as_chunk() const
3813 {
3814 cover("kernel.rtlil.sigspec.as_chunk");
3815
3816 pack();
3817 log_assert(is_chunk());
3818 return chunks_[0];
3819 }
3820
3821 RTLIL::SigBit RTLIL::SigSpec::as_bit() const
3822 {
3823 cover("kernel.rtlil.sigspec.as_bit");
3824
3825 log_assert(width_ == 1);
3826 if (packed())
3827 return RTLIL::SigBit(*chunks_.begin());
3828 else
3829 return bits_[0];
3830 }
3831
3832 bool RTLIL::SigSpec::match(const char* pattern) const
3833 {
3834 cover("kernel.rtlil.sigspec.match");
3835
3836 unpack();
3837 log_assert(int(strlen(pattern)) == GetSize(bits_));
3838
3839 for (auto it = bits_.rbegin(); it != bits_.rend(); it++, pattern++) {
3840 if (*pattern == ' ')
3841 continue;
3842 if (*pattern == '*') {
3843 if (*it != State::Sz && *it != State::Sx)
3844 return false;
3845 continue;
3846 }
3847 if (*pattern == '0') {
3848 if (*it != State::S0)
3849 return false;
3850 } else
3851 if (*pattern == '1') {
3852 if (*it != State::S1)
3853 return false;
3854 } else
3855 log_abort();
3856 }
3857
3858 return true;
3859 }
3860
3861 std::set<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_set() const
3862 {
3863 cover("kernel.rtlil.sigspec.to_sigbit_set");
3864
3865 pack();
3866 std::set<RTLIL::SigBit> sigbits;
3867 for (auto &c : chunks_)
3868 for (int i = 0; i < c.width; i++)
3869 sigbits.insert(RTLIL::SigBit(c, i));
3870 return sigbits;
3871 }
3872
3873 pool<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_pool() const
3874 {
3875 cover("kernel.rtlil.sigspec.to_sigbit_pool");
3876
3877 pack();
3878 pool<RTLIL::SigBit> sigbits;
3879 sigbits.reserve(size());
3880 for (auto &c : chunks_)
3881 for (int i = 0; i < c.width; i++)
3882 sigbits.insert(RTLIL::SigBit(c, i));
3883 return sigbits;
3884 }
3885
3886 std::vector<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_vector() const
3887 {
3888 cover("kernel.rtlil.sigspec.to_sigbit_vector");
3889
3890 unpack();
3891 return bits_;
3892 }
3893
3894 std::map<RTLIL::SigBit, RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_map(const RTLIL::SigSpec &other) const
3895 {
3896 cover("kernel.rtlil.sigspec.to_sigbit_map");
3897
3898 unpack();
3899 other.unpack();
3900
3901 log_assert(width_ == other.width_);
3902
3903 std::map<RTLIL::SigBit, RTLIL::SigBit> new_map;
3904 for (int i = 0; i < width_; i++)
3905 new_map[bits_[i]] = other.bits_[i];
3906
3907 return new_map;
3908 }
3909
3910 dict<RTLIL::SigBit, RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_dict(const RTLIL::SigSpec &other) const
3911 {
3912 cover("kernel.rtlil.sigspec.to_sigbit_dict");
3913
3914 unpack();
3915 other.unpack();
3916
3917 log_assert(width_ == other.width_);
3918
3919 dict<RTLIL::SigBit, RTLIL::SigBit> new_map;
3920 new_map.reserve(size());
3921 for (int i = 0; i < width_; i++)
3922 new_map[bits_[i]] = other.bits_[i];
3923
3924 return new_map;
3925 }
3926
3927 static void sigspec_parse_split(std::vector<std::string> &tokens, const std::string &text, char sep)
3928 {
3929 size_t start = 0, end = 0;
3930 while ((end = text.find(sep, start)) != std::string::npos) {
3931 tokens.push_back(text.substr(start, end - start));
3932 start = end + 1;
3933 }
3934 tokens.push_back(text.substr(start));
3935 }
3936
3937 static int sigspec_parse_get_dummy_line_num()
3938 {
3939 return 0;
3940 }
3941
3942 bool RTLIL::SigSpec::parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str)
3943 {
3944 cover("kernel.rtlil.sigspec.parse");
3945
3946 AST::current_filename = "input";
3947
3948 std::vector<std::string> tokens;
3949 sigspec_parse_split(tokens, str, ',');
3950
3951 sig = RTLIL::SigSpec();
3952 for (int tokidx = int(tokens.size())-1; tokidx >= 0; tokidx--)
3953 {
3954 std::string netname = tokens[tokidx];
3955 std::string indices;
3956
3957 if (netname.size() == 0)
3958 continue;
3959
3960 if (('0' <= netname[0] && netname[0] <= '9') || netname[0] == '\'') {
3961 cover("kernel.rtlil.sigspec.parse.const");
3962 AST::get_line_num = sigspec_parse_get_dummy_line_num;
3963 AST::AstNode *ast = VERILOG_FRONTEND::const2ast(netname);
3964 if (ast == NULL)
3965 return false;
3966 sig.append(RTLIL::Const(ast->bits));
3967 delete ast;
3968 continue;
3969 }
3970
3971 if (module == NULL)
3972 return false;
3973
3974 cover("kernel.rtlil.sigspec.parse.net");
3975
3976 if (netname[0] != '$' && netname[0] != '\\')
3977 netname = "\\" + netname;
3978
3979 if (module->wires_.count(netname) == 0) {
3980 size_t indices_pos = netname.size()-1;
3981 if (indices_pos > 2 && netname[indices_pos] == ']')
3982 {
3983 indices_pos--;
3984 while (indices_pos > 0 && ('0' <= netname[indices_pos] && netname[indices_pos] <= '9')) indices_pos--;
3985 if (indices_pos > 0 && netname[indices_pos] == ':') {
3986 indices_pos--;
3987 while (indices_pos > 0 && ('0' <= netname[indices_pos] && netname[indices_pos] <= '9')) indices_pos--;
3988 }
3989 if (indices_pos > 0 && netname[indices_pos] == '[') {
3990 indices = netname.substr(indices_pos);
3991 netname = netname.substr(0, indices_pos);
3992 }
3993 }
3994 }
3995
3996 if (module->wires_.count(netname) == 0)
3997 return false;
3998
3999 RTLIL::Wire *wire = module->wires_.at(netname);
4000 if (!indices.empty()) {
4001 std::vector<std::string> index_tokens;
4002 sigspec_parse_split(index_tokens, indices.substr(1, indices.size()-2), ':');
4003 if (index_tokens.size() == 1) {
4004 cover("kernel.rtlil.sigspec.parse.bit_sel");
4005 int a = atoi(index_tokens.at(0).c_str());
4006 if (a < 0 || a >= wire->width)
4007 return false;
4008 sig.append(RTLIL::SigSpec(wire, a));
4009 } else {
4010 cover("kernel.rtlil.sigspec.parse.part_sel");
4011 int a = atoi(index_tokens.at(0).c_str());
4012 int b = atoi(index_tokens.at(1).c_str());
4013 if (a > b) {
4014 int tmp = a;
4015 a = b, b = tmp;
4016 }
4017 if (a < 0 || a >= wire->width)
4018 return false;
4019 if (b < 0 || b >= wire->width)
4020 return false;
4021 sig.append(RTLIL::SigSpec(wire, a, b-a+1));
4022 }
4023 } else
4024 sig.append(wire);
4025 }
4026
4027 return true;
4028 }
4029
4030 bool RTLIL::SigSpec::parse_sel(RTLIL::SigSpec &sig, RTLIL::Design *design, RTLIL::Module *module, std::string str)
4031 {
4032 if (str.empty() || str[0] != '@')
4033 return parse(sig, module, str);
4034
4035 cover("kernel.rtlil.sigspec.parse.sel");
4036
4037 str = RTLIL::escape_id(str.substr(1));
4038 if (design->selection_vars.count(str) == 0)
4039 return false;
4040
4041 sig = RTLIL::SigSpec();
4042 RTLIL::Selection &sel = design->selection_vars.at(str);
4043 for (auto &it : module->wires_)
4044 if (sel.selected_member(module->name, it.first))
4045 sig.append(it.second);
4046
4047 return true;
4048 }
4049
4050 bool RTLIL::SigSpec::parse_rhs(const RTLIL::SigSpec &lhs, RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str)
4051 {
4052 if (str == "0") {
4053 cover("kernel.rtlil.sigspec.parse.rhs_zeros");
4054 sig = RTLIL::SigSpec(RTLIL::State::S0, lhs.width_);
4055 return true;
4056 }
4057
4058 if (str == "~0") {
4059 cover("kernel.rtlil.sigspec.parse.rhs_ones");
4060 sig = RTLIL::SigSpec(RTLIL::State::S1, lhs.width_);
4061 return true;
4062 }
4063
4064 if (lhs.chunks_.size() == 1) {
4065 char *p = (char*)str.c_str(), *endptr;
4066 long int val = strtol(p, &endptr, 10);
4067 if (endptr && endptr != p && *endptr == 0) {
4068 sig = RTLIL::SigSpec(val, lhs.width_);
4069 cover("kernel.rtlil.sigspec.parse.rhs_dec");
4070 return true;
4071 }
4072 }
4073
4074 return parse(sig, module, str);
4075 }
4076
4077 RTLIL::CaseRule::~CaseRule()
4078 {
4079 for (auto it = switches.begin(); it != switches.end(); it++)
4080 delete *it;
4081 }
4082
4083 bool RTLIL::CaseRule::empty() const
4084 {
4085 return actions.empty() && switches.empty();
4086 }
4087
4088 RTLIL::CaseRule *RTLIL::CaseRule::clone() const
4089 {
4090 RTLIL::CaseRule *new_caserule = new RTLIL::CaseRule;
4091 new_caserule->compare = compare;
4092 new_caserule->actions = actions;
4093 for (auto &it : switches)
4094 new_caserule->switches.push_back(it->clone());
4095 return new_caserule;
4096 }
4097
4098 RTLIL::SwitchRule::~SwitchRule()
4099 {
4100 for (auto it = cases.begin(); it != cases.end(); it++)
4101 delete *it;
4102 }
4103
4104 bool RTLIL::SwitchRule::empty() const
4105 {
4106 return cases.empty();
4107 }
4108
4109 RTLIL::SwitchRule *RTLIL::SwitchRule::clone() const
4110 {
4111 RTLIL::SwitchRule *new_switchrule = new RTLIL::SwitchRule;
4112 new_switchrule->signal = signal;
4113 new_switchrule->attributes = attributes;
4114 for (auto &it : cases)
4115 new_switchrule->cases.push_back(it->clone());
4116 return new_switchrule;
4117
4118 }
4119
4120 RTLIL::SyncRule *RTLIL::SyncRule::clone() const
4121 {
4122 RTLIL::SyncRule *new_syncrule = new RTLIL::SyncRule;
4123 new_syncrule->type = type;
4124 new_syncrule->signal = signal;
4125 new_syncrule->actions = actions;
4126 return new_syncrule;
4127 }
4128
4129 RTLIL::Process::~Process()
4130 {
4131 for (auto it = syncs.begin(); it != syncs.end(); it++)
4132 delete *it;
4133 }
4134
4135 RTLIL::Process *RTLIL::Process::clone() const
4136 {
4137 RTLIL::Process *new_proc = new RTLIL::Process;
4138
4139 new_proc->name = name;
4140 new_proc->attributes = attributes;
4141
4142 RTLIL::CaseRule *rc_ptr = root_case.clone();
4143 new_proc->root_case = *rc_ptr;
4144 rc_ptr->switches.clear();
4145 delete rc_ptr;
4146
4147 for (auto &it : syncs)
4148 new_proc->syncs.push_back(it->clone());
4149
4150 return new_proc;
4151 }
4152
4153 #ifdef WITH_PYTHON
4154 RTLIL::Memory::~Memory()
4155 {
4156 RTLIL::Memory::get_all_memorys()->erase(hashidx_);
4157 }
4158 static std::map<unsigned int, RTLIL::Memory*> all_memorys;
4159 std::map<unsigned int, RTLIL::Memory*> *RTLIL::Memory::get_all_memorys(void)
4160 {
4161 return &all_memorys;
4162 }
4163 #endif
4164 YOSYS_NAMESPACE_END