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Update example for GW1NR-9
[yosys.git] / kernel / rtlil.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 #include "kernel/yosys.h"
21 #include "kernel/macc.h"
22 #include "kernel/celltypes.h"
23 #include "frontends/verilog/verilog_frontend.h"
24 #include "backends/ilang/ilang_backend.h"
25
26 #include <string.h>
27 #include <algorithm>
28
29 YOSYS_NAMESPACE_BEGIN
30
31 RTLIL::IdString::destruct_guard_t RTLIL::IdString::destruct_guard;
32 std::vector<char*> RTLIL::IdString::global_id_storage_;
33 dict<char*, int, hash_cstr_ops> RTLIL::IdString::global_id_index_;
34 #ifndef YOSYS_NO_IDS_REFCNT
35 std::vector<int> RTLIL::IdString::global_refcount_storage_;
36 std::vector<int> RTLIL::IdString::global_free_idx_list_;
37 #endif
38 #ifdef YOSYS_USE_STICKY_IDS
39 int RTLIL::IdString::last_created_idx_[8];
40 int RTLIL::IdString::last_created_idx_ptr_;
41 #endif
42
43 IdString RTLIL::ID::A;
44 IdString RTLIL::ID::B;
45 IdString RTLIL::ID::Y;
46 IdString RTLIL::ID::keep;
47 IdString RTLIL::ID::whitebox;
48 IdString RTLIL::ID::blackbox;
49
50 RTLIL::Const::Const()
51 {
52 flags = RTLIL::CONST_FLAG_NONE;
53 }
54
55 RTLIL::Const::Const(std::string str)
56 {
57 flags = RTLIL::CONST_FLAG_STRING;
58 for (int i = str.size()-1; i >= 0; i--) {
59 unsigned char ch = str[i];
60 for (int j = 0; j < 8; j++) {
61 bits.push_back((ch & 1) != 0 ? State::S1 : State::S0);
62 ch = ch >> 1;
63 }
64 }
65 }
66
67 RTLIL::Const::Const(int val, int width)
68 {
69 flags = RTLIL::CONST_FLAG_NONE;
70 for (int i = 0; i < width; i++) {
71 bits.push_back((val & 1) != 0 ? State::S1 : State::S0);
72 val = val >> 1;
73 }
74 }
75
76 RTLIL::Const::Const(RTLIL::State bit, int width)
77 {
78 flags = RTLIL::CONST_FLAG_NONE;
79 for (int i = 0; i < width; i++)
80 bits.push_back(bit);
81 }
82
83 RTLIL::Const::Const(const std::vector<bool> &bits)
84 {
85 flags = RTLIL::CONST_FLAG_NONE;
86 for (auto b : bits)
87 this->bits.push_back(b ? State::S1 : State::S0);
88 }
89
90 RTLIL::Const::Const(const RTLIL::Const &c)
91 {
92 flags = c.flags;
93 for (auto b : c.bits)
94 this->bits.push_back(b);
95 }
96
97 bool RTLIL::Const::operator <(const RTLIL::Const &other) const
98 {
99 if (bits.size() != other.bits.size())
100 return bits.size() < other.bits.size();
101 for (size_t i = 0; i < bits.size(); i++)
102 if (bits[i] != other.bits[i])
103 return bits[i] < other.bits[i];
104 return false;
105 }
106
107 bool RTLIL::Const::operator ==(const RTLIL::Const &other) const
108 {
109 return bits == other.bits;
110 }
111
112 bool RTLIL::Const::operator !=(const RTLIL::Const &other) const
113 {
114 return bits != other.bits;
115 }
116
117 bool RTLIL::Const::as_bool() const
118 {
119 for (size_t i = 0; i < bits.size(); i++)
120 if (bits[i] == State::S1)
121 return true;
122 return false;
123 }
124
125 int RTLIL::Const::as_int(bool is_signed) const
126 {
127 int32_t ret = 0;
128 for (size_t i = 0; i < bits.size() && i < 32; i++)
129 if (bits[i] == State::S1)
130 ret |= 1 << i;
131 if (is_signed && bits.back() == State::S1)
132 for (size_t i = bits.size(); i < 32; i++)
133 ret |= 1 << i;
134 return ret;
135 }
136
137 std::string RTLIL::Const::as_string() const
138 {
139 std::string ret;
140 for (size_t i = bits.size(); i > 0; i--)
141 switch (bits[i-1]) {
142 case S0: ret += "0"; break;
143 case S1: ret += "1"; break;
144 case Sx: ret += "x"; break;
145 case Sz: ret += "z"; break;
146 case Sa: ret += "-"; break;
147 case Sm: ret += "m"; break;
148 }
149 return ret;
150 }
151
152 RTLIL::Const RTLIL::Const::from_string(std::string str)
153 {
154 Const c;
155 for (auto it = str.rbegin(); it != str.rend(); it++)
156 switch (*it) {
157 case '0': c.bits.push_back(State::S0); break;
158 case '1': c.bits.push_back(State::S1); break;
159 case 'x': c.bits.push_back(State::Sx); break;
160 case 'z': c.bits.push_back(State::Sz); break;
161 case 'm': c.bits.push_back(State::Sm); break;
162 default: c.bits.push_back(State::Sa);
163 }
164 return c;
165 }
166
167 std::string RTLIL::Const::decode_string() const
168 {
169 std::string string;
170 std::vector<char> string_chars;
171 for (int i = 0; i < int (bits.size()); i += 8) {
172 char ch = 0;
173 for (int j = 0; j < 8 && i + j < int (bits.size()); j++)
174 if (bits[i + j] == RTLIL::State::S1)
175 ch |= 1 << j;
176 if (ch != 0)
177 string_chars.push_back(ch);
178 }
179 for (int i = int (string_chars.size()) - 1; i >= 0; i--)
180 string += string_chars[i];
181 return string;
182 }
183
184 bool RTLIL::Const::is_fully_zero() const
185 {
186 cover("kernel.rtlil.const.is_fully_zero");
187
188 for (auto bit : bits)
189 if (bit != RTLIL::State::S0)
190 return false;
191
192 return true;
193 }
194
195 bool RTLIL::Const::is_fully_ones() const
196 {
197 cover("kernel.rtlil.const.is_fully_ones");
198
199 for (auto bit : bits)
200 if (bit != RTLIL::State::S1)
201 return false;
202
203 return true;
204 }
205
206 bool RTLIL::Const::is_fully_def() const
207 {
208 cover("kernel.rtlil.const.is_fully_def");
209
210 for (auto bit : bits)
211 if (bit != RTLIL::State::S0 && bit != RTLIL::State::S1)
212 return false;
213
214 return true;
215 }
216
217 bool RTLIL::Const::is_fully_undef() const
218 {
219 cover("kernel.rtlil.const.is_fully_undef");
220
221 for (auto bit : bits)
222 if (bit != RTLIL::State::Sx && bit != RTLIL::State::Sz)
223 return false;
224
225 return true;
226 }
227
228 void RTLIL::AttrObject::set_bool_attribute(RTLIL::IdString id, bool value)
229 {
230 if (value)
231 attributes[id] = RTLIL::Const(1);
232 else {
233 const auto it = attributes.find(id);
234 if (it != attributes.end())
235 attributes.erase(it);
236 }
237 }
238
239 bool RTLIL::AttrObject::get_bool_attribute(RTLIL::IdString id) const
240 {
241 const auto it = attributes.find(id);
242 if (it == attributes.end())
243 return false;
244 return it->second.as_bool();
245 }
246
247 void RTLIL::AttrObject::set_strpool_attribute(RTLIL::IdString id, const pool<string> &data)
248 {
249 string attrval;
250 for (auto &s : data) {
251 if (!attrval.empty())
252 attrval += "|";
253 attrval += s;
254 }
255 attributes[id] = RTLIL::Const(attrval);
256 }
257
258 void RTLIL::AttrObject::add_strpool_attribute(RTLIL::IdString id, const pool<string> &data)
259 {
260 pool<string> union_data = get_strpool_attribute(id);
261 union_data.insert(data.begin(), data.end());
262 if (!union_data.empty())
263 set_strpool_attribute(id, union_data);
264 }
265
266 pool<string> RTLIL::AttrObject::get_strpool_attribute(RTLIL::IdString id) const
267 {
268 pool<string> data;
269 if (attributes.count(id) != 0)
270 for (auto s : split_tokens(attributes.at(id).decode_string(), "|"))
271 data.insert(s);
272 return data;
273 }
274
275 void RTLIL::AttrObject::set_src_attribute(const std::string &src)
276 {
277 if (src.empty())
278 attributes.erase(ID(src));
279 else
280 attributes[ID(src)] = src;
281 }
282
283 std::string RTLIL::AttrObject::get_src_attribute() const
284 {
285 std::string src;
286 if (attributes.count(ID(src)))
287 src = attributes.at(ID(src)).decode_string();
288 return src;
289 }
290
291 bool RTLIL::Selection::selected_module(RTLIL::IdString mod_name) const
292 {
293 if (full_selection)
294 return true;
295 if (selected_modules.count(mod_name) > 0)
296 return true;
297 if (selected_members.count(mod_name) > 0)
298 return true;
299 return false;
300 }
301
302 bool RTLIL::Selection::selected_whole_module(RTLIL::IdString mod_name) const
303 {
304 if (full_selection)
305 return true;
306 if (selected_modules.count(mod_name) > 0)
307 return true;
308 return false;
309 }
310
311 bool RTLIL::Selection::selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const
312 {
313 if (full_selection)
314 return true;
315 if (selected_modules.count(mod_name) > 0)
316 return true;
317 if (selected_members.count(mod_name) > 0)
318 if (selected_members.at(mod_name).count(memb_name) > 0)
319 return true;
320 return false;
321 }
322
323 void RTLIL::Selection::optimize(RTLIL::Design *design)
324 {
325 if (full_selection) {
326 selected_modules.clear();
327 selected_members.clear();
328 return;
329 }
330
331 std::vector<RTLIL::IdString> del_list, add_list;
332
333 del_list.clear();
334 for (auto mod_name : selected_modules) {
335 if (design->modules_.count(mod_name) == 0)
336 del_list.push_back(mod_name);
337 selected_members.erase(mod_name);
338 }
339 for (auto mod_name : del_list)
340 selected_modules.erase(mod_name);
341
342 del_list.clear();
343 for (auto &it : selected_members)
344 if (design->modules_.count(it.first) == 0)
345 del_list.push_back(it.first);
346 for (auto mod_name : del_list)
347 selected_members.erase(mod_name);
348
349 for (auto &it : selected_members) {
350 del_list.clear();
351 for (auto memb_name : it.second)
352 if (design->modules_[it.first]->count_id(memb_name) == 0)
353 del_list.push_back(memb_name);
354 for (auto memb_name : del_list)
355 it.second.erase(memb_name);
356 }
357
358 del_list.clear();
359 add_list.clear();
360 for (auto &it : selected_members)
361 if (it.second.size() == 0)
362 del_list.push_back(it.first);
363 else if (it.second.size() == design->modules_[it.first]->wires_.size() + design->modules_[it.first]->memories.size() +
364 design->modules_[it.first]->cells_.size() + design->modules_[it.first]->processes.size())
365 add_list.push_back(it.first);
366 for (auto mod_name : del_list)
367 selected_members.erase(mod_name);
368 for (auto mod_name : add_list) {
369 selected_members.erase(mod_name);
370 selected_modules.insert(mod_name);
371 }
372
373 if (selected_modules.size() == design->modules_.size()) {
374 full_selection = true;
375 selected_modules.clear();
376 selected_members.clear();
377 }
378 }
379
380 RTLIL::Design::Design()
381 {
382 static unsigned int hashidx_count = 123456789;
383 hashidx_count = mkhash_xorshift(hashidx_count);
384 hashidx_ = hashidx_count;
385
386 refcount_modules_ = 0;
387 selection_stack.push_back(RTLIL::Selection());
388
389 #ifdef WITH_PYTHON
390 RTLIL::Design::get_all_designs()->insert(std::pair<unsigned int, RTLIL::Design*>(hashidx_, this));
391 #endif
392 }
393
394 RTLIL::Design::~Design()
395 {
396 for (auto it = modules_.begin(); it != modules_.end(); ++it)
397 delete it->second;
398 for (auto n : verilog_packages)
399 delete n;
400 for (auto n : verilog_globals)
401 delete n;
402 #ifdef WITH_PYTHON
403 RTLIL::Design::get_all_designs()->erase(hashidx_);
404 #endif
405 }
406
407 #ifdef WITH_PYTHON
408 static std::map<unsigned int, RTLIL::Design*> all_designs;
409 std::map<unsigned int, RTLIL::Design*> *RTLIL::Design::get_all_designs(void)
410 {
411 return &all_designs;
412 }
413 #endif
414
415 RTLIL::ObjRange<RTLIL::Module*> RTLIL::Design::modules()
416 {
417 return RTLIL::ObjRange<RTLIL::Module*>(&modules_, &refcount_modules_);
418 }
419
420 RTLIL::Module *RTLIL::Design::module(RTLIL::IdString name)
421 {
422 return modules_.count(name) ? modules_.at(name) : NULL;
423 }
424
425 RTLIL::Module *RTLIL::Design::top_module()
426 {
427 RTLIL::Module *module = nullptr;
428 int module_count = 0;
429
430 for (auto mod : selected_modules()) {
431 if (mod->get_bool_attribute(ID(top)))
432 return mod;
433 module_count++;
434 module = mod;
435 }
436
437 return module_count == 1 ? module : nullptr;
438 }
439
440 void RTLIL::Design::add(RTLIL::Module *module)
441 {
442 log_assert(modules_.count(module->name) == 0);
443 log_assert(refcount_modules_ == 0);
444 modules_[module->name] = module;
445 module->design = this;
446
447 for (auto mon : monitors)
448 mon->notify_module_add(module);
449
450 if (yosys_xtrace) {
451 log("#X# New Module: %s\n", log_id(module));
452 log_backtrace("-X- ", yosys_xtrace-1);
453 }
454 }
455
456 RTLIL::Module *RTLIL::Design::addModule(RTLIL::IdString name)
457 {
458 log_assert(modules_.count(name) == 0);
459 log_assert(refcount_modules_ == 0);
460
461 RTLIL::Module *module = new RTLIL::Module;
462 modules_[name] = module;
463 module->design = this;
464 module->name = name;
465
466 for (auto mon : monitors)
467 mon->notify_module_add(module);
468
469 if (yosys_xtrace) {
470 log("#X# New Module: %s\n", log_id(module));
471 log_backtrace("-X- ", yosys_xtrace-1);
472 }
473
474 return module;
475 }
476
477 void RTLIL::Design::scratchpad_unset(std::string varname)
478 {
479 scratchpad.erase(varname);
480 }
481
482 void RTLIL::Design::scratchpad_set_int(std::string varname, int value)
483 {
484 scratchpad[varname] = stringf("%d", value);
485 }
486
487 void RTLIL::Design::scratchpad_set_bool(std::string varname, bool value)
488 {
489 scratchpad[varname] = value ? "true" : "false";
490 }
491
492 void RTLIL::Design::scratchpad_set_string(std::string varname, std::string value)
493 {
494 scratchpad[varname] = value;
495 }
496
497 int RTLIL::Design::scratchpad_get_int(std::string varname, int default_value) const
498 {
499 if (scratchpad.count(varname) == 0)
500 return default_value;
501
502 std::string str = scratchpad.at(varname);
503
504 if (str == "0" || str == "false")
505 return 0;
506
507 if (str == "1" || str == "true")
508 return 1;
509
510 char *endptr = nullptr;
511 long int parsed_value = strtol(str.c_str(), &endptr, 10);
512 return *endptr ? default_value : parsed_value;
513 }
514
515 bool RTLIL::Design::scratchpad_get_bool(std::string varname, bool default_value) const
516 {
517 if (scratchpad.count(varname) == 0)
518 return default_value;
519
520 std::string str = scratchpad.at(varname);
521
522 if (str == "0" || str == "false")
523 return false;
524
525 if (str == "1" || str == "true")
526 return true;
527
528 return default_value;
529 }
530
531 std::string RTLIL::Design::scratchpad_get_string(std::string varname, std::string default_value) const
532 {
533 if (scratchpad.count(varname) == 0)
534 return default_value;
535 return scratchpad.at(varname);
536 }
537
538 void RTLIL::Design::remove(RTLIL::Module *module)
539 {
540 for (auto mon : monitors)
541 mon->notify_module_del(module);
542
543 if (yosys_xtrace) {
544 log("#X# Remove Module: %s\n", log_id(module));
545 log_backtrace("-X- ", yosys_xtrace-1);
546 }
547
548 log_assert(modules_.at(module->name) == module);
549 modules_.erase(module->name);
550 delete module;
551 }
552
553 void RTLIL::Design::rename(RTLIL::Module *module, RTLIL::IdString new_name)
554 {
555 modules_.erase(module->name);
556 module->name = new_name;
557 add(module);
558 }
559
560 void RTLIL::Design::sort()
561 {
562 scratchpad.sort();
563 modules_.sort(sort_by_id_str());
564 for (auto &it : modules_)
565 it.second->sort();
566 }
567
568 void RTLIL::Design::check()
569 {
570 #ifndef NDEBUG
571 for (auto &it : modules_) {
572 log_assert(this == it.second->design);
573 log_assert(it.first == it.second->name);
574 log_assert(!it.first.empty());
575 it.second->check();
576 }
577 #endif
578 }
579
580 void RTLIL::Design::optimize()
581 {
582 for (auto &it : modules_)
583 it.second->optimize();
584 for (auto &it : selection_stack)
585 it.optimize(this);
586 for (auto &it : selection_vars)
587 it.second.optimize(this);
588 }
589
590 bool RTLIL::Design::selected_module(RTLIL::IdString mod_name) const
591 {
592 if (!selected_active_module.empty() && mod_name != selected_active_module)
593 return false;
594 if (selection_stack.size() == 0)
595 return true;
596 return selection_stack.back().selected_module(mod_name);
597 }
598
599 bool RTLIL::Design::selected_whole_module(RTLIL::IdString mod_name) const
600 {
601 if (!selected_active_module.empty() && mod_name != selected_active_module)
602 return false;
603 if (selection_stack.size() == 0)
604 return true;
605 return selection_stack.back().selected_whole_module(mod_name);
606 }
607
608 bool RTLIL::Design::selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const
609 {
610 if (!selected_active_module.empty() && mod_name != selected_active_module)
611 return false;
612 if (selection_stack.size() == 0)
613 return true;
614 return selection_stack.back().selected_member(mod_name, memb_name);
615 }
616
617 bool RTLIL::Design::selected_module(RTLIL::Module *mod) const
618 {
619 return selected_module(mod->name);
620 }
621
622 bool RTLIL::Design::selected_whole_module(RTLIL::Module *mod) const
623 {
624 return selected_whole_module(mod->name);
625 }
626
627 std::vector<RTLIL::Module*> RTLIL::Design::selected_modules() const
628 {
629 std::vector<RTLIL::Module*> result;
630 result.reserve(modules_.size());
631 for (auto &it : modules_)
632 if (selected_module(it.first) && !it.second->get_blackbox_attribute())
633 result.push_back(it.second);
634 return result;
635 }
636
637 std::vector<RTLIL::Module*> RTLIL::Design::selected_whole_modules() const
638 {
639 std::vector<RTLIL::Module*> result;
640 result.reserve(modules_.size());
641 for (auto &it : modules_)
642 if (selected_whole_module(it.first) && !it.second->get_blackbox_attribute())
643 result.push_back(it.second);
644 return result;
645 }
646
647 std::vector<RTLIL::Module*> RTLIL::Design::selected_whole_modules_warn() const
648 {
649 std::vector<RTLIL::Module*> result;
650 result.reserve(modules_.size());
651 for (auto &it : modules_)
652 if (it.second->get_blackbox_attribute())
653 continue;
654 else if (selected_whole_module(it.first))
655 result.push_back(it.second);
656 else if (selected_module(it.first))
657 log_warning("Ignoring partially selected module %s.\n", log_id(it.first));
658 return result;
659 }
660
661 RTLIL::Module::Module()
662 {
663 static unsigned int hashidx_count = 123456789;
664 hashidx_count = mkhash_xorshift(hashidx_count);
665 hashidx_ = hashidx_count;
666
667 design = nullptr;
668 refcount_wires_ = 0;
669 refcount_cells_ = 0;
670
671 #ifdef WITH_PYTHON
672 RTLIL::Module::get_all_modules()->insert(std::pair<unsigned int, RTLIL::Module*>(hashidx_, this));
673 #endif
674 }
675
676 RTLIL::Module::~Module()
677 {
678 for (auto it = wires_.begin(); it != wires_.end(); ++it)
679 delete it->second;
680 for (auto it = memories.begin(); it != memories.end(); ++it)
681 delete it->second;
682 for (auto it = cells_.begin(); it != cells_.end(); ++it)
683 delete it->second;
684 for (auto it = processes.begin(); it != processes.end(); ++it)
685 delete it->second;
686 #ifdef WITH_PYTHON
687 RTLIL::Module::get_all_modules()->erase(hashidx_);
688 #endif
689 }
690
691 #ifdef WITH_PYTHON
692 static std::map<unsigned int, RTLIL::Module*> all_modules;
693 std::map<unsigned int, RTLIL::Module*> *RTLIL::Module::get_all_modules(void)
694 {
695 return &all_modules;
696 }
697 #endif
698
699 void RTLIL::Module::makeblackbox()
700 {
701 pool<RTLIL::Wire*> delwires;
702
703 for (auto it = wires_.begin(); it != wires_.end(); ++it)
704 if (!it->second->port_input && !it->second->port_output)
705 delwires.insert(it->second);
706
707 for (auto it = memories.begin(); it != memories.end(); ++it)
708 delete it->second;
709 memories.clear();
710
711 for (auto it = cells_.begin(); it != cells_.end(); ++it)
712 delete it->second;
713 cells_.clear();
714
715 for (auto it = processes.begin(); it != processes.end(); ++it)
716 delete it->second;
717 processes.clear();
718
719 remove(delwires);
720 set_bool_attribute(ID::blackbox);
721 }
722
723 void RTLIL::Module::reprocess_module(RTLIL::Design *, dict<RTLIL::IdString, RTLIL::Module *>)
724 {
725 log_error("Cannot reprocess_module module `%s' !\n", id2cstr(name));
726 }
727
728 RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, dict<RTLIL::IdString, RTLIL::Const>, bool mayfail)
729 {
730 if (mayfail)
731 return RTLIL::IdString();
732 log_error("Module `%s' is used with parameters but is not parametric!\n", id2cstr(name));
733 }
734
735
736 RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, dict<RTLIL::IdString, RTLIL::Const>, dict<RTLIL::IdString, RTLIL::Module*>, dict<RTLIL::IdString, RTLIL::IdString>, bool mayfail)
737 {
738 if (mayfail)
739 return RTLIL::IdString();
740 log_error("Module `%s' is used with parameters but is not parametric!\n", id2cstr(name));
741 }
742
743 size_t RTLIL::Module::count_id(RTLIL::IdString id)
744 {
745 return wires_.count(id) + memories.count(id) + cells_.count(id) + processes.count(id);
746 }
747
748 #ifndef NDEBUG
749 namespace {
750 struct InternalCellChecker
751 {
752 RTLIL::Module *module;
753 RTLIL::Cell *cell;
754 pool<RTLIL::IdString> expected_params, expected_ports;
755
756 InternalCellChecker(RTLIL::Module *module, RTLIL::Cell *cell) : module(module), cell(cell) { }
757
758 void error(int linenr)
759 {
760 std::stringstream buf;
761 ILANG_BACKEND::dump_cell(buf, " ", cell);
762
763 log_error("Found error in internal cell %s%s%s (%s) at %s:%d:\n%s",
764 module ? module->name.c_str() : "", module ? "." : "",
765 cell->name.c_str(), cell->type.c_str(), __FILE__, linenr, buf.str().c_str());
766 }
767
768 int param(RTLIL::IdString name)
769 {
770 if (cell->parameters.count(name) == 0)
771 error(__LINE__);
772 expected_params.insert(name);
773 return cell->parameters.at(name).as_int();
774 }
775
776 int param_bool(RTLIL::IdString name)
777 {
778 int v = param(name);
779 if (cell->parameters.at(name).bits.size() > 32)
780 error(__LINE__);
781 if (v != 0 && v != 1)
782 error(__LINE__);
783 return v;
784 }
785
786 void param_bits(RTLIL::IdString name, int width)
787 {
788 param(name);
789 if (int(cell->parameters.at(name).bits.size()) != width)
790 error(__LINE__);
791 }
792
793 void port(RTLIL::IdString name, int width)
794 {
795 if (!cell->hasPort(name))
796 error(__LINE__);
797 if (cell->getPort(name).size() != width)
798 error(__LINE__);
799 expected_ports.insert(name);
800 }
801
802 void check_expected(bool check_matched_sign = true)
803 {
804 for (auto &para : cell->parameters)
805 if (expected_params.count(para.first) == 0)
806 error(__LINE__);
807 for (auto &conn : cell->connections())
808 if (expected_ports.count(conn.first) == 0)
809 error(__LINE__);
810
811 if (expected_params.count(ID(A_SIGNED)) != 0 && expected_params.count(ID(B_SIGNED)) && check_matched_sign) {
812 bool a_is_signed = param(ID(A_SIGNED)) != 0;
813 bool b_is_signed = param(ID(B_SIGNED)) != 0;
814 if (a_is_signed != b_is_signed)
815 error(__LINE__);
816 }
817 }
818
819 void check_gate(const char *ports)
820 {
821 if (cell->parameters.size() != 0)
822 error(__LINE__);
823
824 for (const char *p = ports; *p; p++) {
825 char portname[3] = { '\\', *p, 0 };
826 if (!cell->hasPort(portname))
827 error(__LINE__);
828 if (cell->getPort(portname).size() != 1)
829 error(__LINE__);
830 }
831
832 for (auto &conn : cell->connections()) {
833 if (conn.first.size() != 2 || conn.first[0] != '\\')
834 error(__LINE__);
835 if (strchr(ports, conn.first[1]) == NULL)
836 error(__LINE__);
837 }
838 }
839
840 void check()
841 {
842 if (!cell->type.begins_with("$") || cell->type.begins_with("$__") || cell->type.begins_with("$paramod") || cell->type.begins_with("$fmcombine") ||
843 cell->type.begins_with("$verific$") || cell->type.begins_with("$array:") || cell->type.begins_with("$extern:"))
844 return;
845
846 if (cell->type.in(ID($not), ID($pos), ID($neg))) {
847 param_bool(ID(A_SIGNED));
848 port(ID::A, param(ID(A_WIDTH)));
849 port(ID::Y, param(ID(Y_WIDTH)));
850 check_expected();
851 return;
852 }
853
854 if (cell->type.in(ID($and), ID($or), ID($xor), ID($xnor))) {
855 param_bool(ID(A_SIGNED));
856 param_bool(ID(B_SIGNED));
857 port(ID::A, param(ID(A_WIDTH)));
858 port(ID::B, param(ID(B_WIDTH)));
859 port(ID::Y, param(ID(Y_WIDTH)));
860 check_expected();
861 return;
862 }
863
864 if (cell->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor), ID($reduce_bool))) {
865 param_bool(ID(A_SIGNED));
866 port(ID::A, param(ID(A_WIDTH)));
867 port(ID::Y, param(ID(Y_WIDTH)));
868 check_expected();
869 return;
870 }
871
872 if (cell->type.in(ID($shl), ID($shr), ID($sshl), ID($sshr), ID($shift), ID($shiftx))) {
873 param_bool(ID(A_SIGNED));
874 param_bool(ID(B_SIGNED));
875 port(ID::A, param(ID(A_WIDTH)));
876 port(ID::B, param(ID(B_WIDTH)));
877 port(ID::Y, param(ID(Y_WIDTH)));
878 check_expected(false);
879 return;
880 }
881
882 if (cell->type.in(ID($lt), ID($le), ID($eq), ID($ne), ID($eqx), ID($nex), ID($ge), ID($gt))) {
883 param_bool(ID(A_SIGNED));
884 param_bool(ID(B_SIGNED));
885 port(ID::A, param(ID(A_WIDTH)));
886 port(ID::B, param(ID(B_WIDTH)));
887 port(ID::Y, param(ID(Y_WIDTH)));
888 check_expected();
889 return;
890 }
891
892 if (cell->type.in(ID($add), ID($sub), ID($mul), ID($div), ID($mod), ID($pow))) {
893 param_bool(ID(A_SIGNED));
894 param_bool(ID(B_SIGNED));
895 port(ID::A, param(ID(A_WIDTH)));
896 port(ID::B, param(ID(B_WIDTH)));
897 port(ID::Y, param(ID(Y_WIDTH)));
898 check_expected(cell->type != ID($pow));
899 return;
900 }
901
902 if (cell->type == ID($fa)) {
903 port(ID::A, param(ID(WIDTH)));
904 port(ID::B, param(ID(WIDTH)));
905 port(ID(C), param(ID(WIDTH)));
906 port(ID(X), param(ID(WIDTH)));
907 port(ID::Y, param(ID(WIDTH)));
908 check_expected();
909 return;
910 }
911
912 if (cell->type == ID($lcu)) {
913 port(ID(P), param(ID(WIDTH)));
914 port(ID(G), param(ID(WIDTH)));
915 port(ID(CI), 1);
916 port(ID(CO), param(ID(WIDTH)));
917 check_expected();
918 return;
919 }
920
921 if (cell->type == ID($alu)) {
922 param_bool(ID(A_SIGNED));
923 param_bool(ID(B_SIGNED));
924 port(ID::A, param(ID(A_WIDTH)));
925 port(ID::B, param(ID(B_WIDTH)));
926 port(ID(CI), 1);
927 port(ID(BI), 1);
928 port(ID(X), param(ID(Y_WIDTH)));
929 port(ID::Y, param(ID(Y_WIDTH)));
930 port(ID(CO), param(ID(Y_WIDTH)));
931 check_expected();
932 return;
933 }
934
935 if (cell->type == ID($macc)) {
936 param(ID(CONFIG));
937 param(ID(CONFIG_WIDTH));
938 port(ID::A, param(ID(A_WIDTH)));
939 port(ID::B, param(ID(B_WIDTH)));
940 port(ID::Y, param(ID(Y_WIDTH)));
941 check_expected();
942 Macc().from_cell(cell);
943 return;
944 }
945
946 if (cell->type == ID($logic_not)) {
947 param_bool(ID(A_SIGNED));
948 port(ID::A, param(ID(A_WIDTH)));
949 port(ID::Y, param(ID(Y_WIDTH)));
950 check_expected();
951 return;
952 }
953
954 if (cell->type.in(ID($logic_and), ID($logic_or))) {
955 param_bool(ID(A_SIGNED));
956 param_bool(ID(B_SIGNED));
957 port(ID::A, param(ID(A_WIDTH)));
958 port(ID::B, param(ID(B_WIDTH)));
959 port(ID::Y, param(ID(Y_WIDTH)));
960 check_expected(false);
961 return;
962 }
963
964 if (cell->type == ID($slice)) {
965 param(ID(OFFSET));
966 port(ID::A, param(ID(A_WIDTH)));
967 port(ID::Y, param(ID(Y_WIDTH)));
968 if (param(ID(OFFSET)) + param(ID(Y_WIDTH)) > param(ID(A_WIDTH)))
969 error(__LINE__);
970 check_expected();
971 return;
972 }
973
974 if (cell->type == ID($concat)) {
975 port(ID::A, param(ID(A_WIDTH)));
976 port(ID::B, param(ID(B_WIDTH)));
977 port(ID::Y, param(ID(A_WIDTH)) + param(ID(B_WIDTH)));
978 check_expected();
979 return;
980 }
981
982 if (cell->type == ID($mux)) {
983 port(ID::A, param(ID(WIDTH)));
984 port(ID::B, param(ID(WIDTH)));
985 port(ID(S), 1);
986 port(ID::Y, param(ID(WIDTH)));
987 check_expected();
988 return;
989 }
990
991 if (cell->type == ID($pmux)) {
992 port(ID::A, param(ID(WIDTH)));
993 port(ID::B, param(ID(WIDTH)) * param(ID(S_WIDTH)));
994 port(ID(S), param(ID(S_WIDTH)));
995 port(ID::Y, param(ID(WIDTH)));
996 check_expected();
997 return;
998 }
999
1000 if (cell->type == ID($lut)) {
1001 param(ID(LUT));
1002 port(ID::A, param(ID(WIDTH)));
1003 port(ID::Y, 1);
1004 check_expected();
1005 return;
1006 }
1007
1008 if (cell->type == ID($sop)) {
1009 param(ID(DEPTH));
1010 param(ID(TABLE));
1011 port(ID::A, param(ID(WIDTH)));
1012 port(ID::Y, 1);
1013 check_expected();
1014 return;
1015 }
1016
1017 if (cell->type == ID($sr)) {
1018 param_bool(ID(SET_POLARITY));
1019 param_bool(ID(CLR_POLARITY));
1020 port(ID(SET), param(ID(WIDTH)));
1021 port(ID(CLR), param(ID(WIDTH)));
1022 port(ID(Q), param(ID(WIDTH)));
1023 check_expected();
1024 return;
1025 }
1026
1027 if (cell->type == ID($ff)) {
1028 port(ID(D), param(ID(WIDTH)));
1029 port(ID(Q), param(ID(WIDTH)));
1030 check_expected();
1031 return;
1032 }
1033
1034 if (cell->type == ID($dff)) {
1035 param_bool(ID(CLK_POLARITY));
1036 port(ID(CLK), 1);
1037 port(ID(D), param(ID(WIDTH)));
1038 port(ID(Q), param(ID(WIDTH)));
1039 check_expected();
1040 return;
1041 }
1042
1043 if (cell->type == ID($dffe)) {
1044 param_bool(ID(CLK_POLARITY));
1045 param_bool(ID(EN_POLARITY));
1046 port(ID(CLK), 1);
1047 port(ID(EN), 1);
1048 port(ID(D), param(ID(WIDTH)));
1049 port(ID(Q), param(ID(WIDTH)));
1050 check_expected();
1051 return;
1052 }
1053
1054 if (cell->type == ID($dffsr)) {
1055 param_bool(ID(CLK_POLARITY));
1056 param_bool(ID(SET_POLARITY));
1057 param_bool(ID(CLR_POLARITY));
1058 port(ID(CLK), 1);
1059 port(ID(SET), param(ID(WIDTH)));
1060 port(ID(CLR), param(ID(WIDTH)));
1061 port(ID(D), param(ID(WIDTH)));
1062 port(ID(Q), param(ID(WIDTH)));
1063 check_expected();
1064 return;
1065 }
1066
1067 if (cell->type == ID($adff)) {
1068 param_bool(ID(CLK_POLARITY));
1069 param_bool(ID(ARST_POLARITY));
1070 param_bits(ID(ARST_VALUE), param(ID(WIDTH)));
1071 port(ID(CLK), 1);
1072 port(ID(ARST), 1);
1073 port(ID(D), param(ID(WIDTH)));
1074 port(ID(Q), param(ID(WIDTH)));
1075 check_expected();
1076 return;
1077 }
1078
1079 if (cell->type == ID($dlatch)) {
1080 param_bool(ID(EN_POLARITY));
1081 port(ID(EN), 1);
1082 port(ID(D), param(ID(WIDTH)));
1083 port(ID(Q), param(ID(WIDTH)));
1084 check_expected();
1085 return;
1086 }
1087
1088 if (cell->type == ID($dlatchsr)) {
1089 param_bool(ID(EN_POLARITY));
1090 param_bool(ID(SET_POLARITY));
1091 param_bool(ID(CLR_POLARITY));
1092 port(ID(EN), 1);
1093 port(ID(SET), param(ID(WIDTH)));
1094 port(ID(CLR), param(ID(WIDTH)));
1095 port(ID(D), param(ID(WIDTH)));
1096 port(ID(Q), param(ID(WIDTH)));
1097 check_expected();
1098 return;
1099 }
1100
1101 if (cell->type == ID($fsm)) {
1102 param(ID(NAME));
1103 param_bool(ID(CLK_POLARITY));
1104 param_bool(ID(ARST_POLARITY));
1105 param(ID(STATE_BITS));
1106 param(ID(STATE_NUM));
1107 param(ID(STATE_NUM_LOG2));
1108 param(ID(STATE_RST));
1109 param_bits(ID(STATE_TABLE), param(ID(STATE_BITS)) * param(ID(STATE_NUM)));
1110 param(ID(TRANS_NUM));
1111 param_bits(ID(TRANS_TABLE), param(ID(TRANS_NUM)) * (2*param(ID(STATE_NUM_LOG2)) + param(ID(CTRL_IN_WIDTH)) + param(ID(CTRL_OUT_WIDTH))));
1112 port(ID(CLK), 1);
1113 port(ID(ARST), 1);
1114 port(ID(CTRL_IN), param(ID(CTRL_IN_WIDTH)));
1115 port(ID(CTRL_OUT), param(ID(CTRL_OUT_WIDTH)));
1116 check_expected();
1117 return;
1118 }
1119
1120 if (cell->type == ID($memrd)) {
1121 param(ID(MEMID));
1122 param_bool(ID(CLK_ENABLE));
1123 param_bool(ID(CLK_POLARITY));
1124 param_bool(ID(TRANSPARENT));
1125 port(ID(CLK), 1);
1126 port(ID(EN), 1);
1127 port(ID(ADDR), param(ID(ABITS)));
1128 port(ID(DATA), param(ID(WIDTH)));
1129 check_expected();
1130 return;
1131 }
1132
1133 if (cell->type == ID($memwr)) {
1134 param(ID(MEMID));
1135 param_bool(ID(CLK_ENABLE));
1136 param_bool(ID(CLK_POLARITY));
1137 param(ID(PRIORITY));
1138 port(ID(CLK), 1);
1139 port(ID(EN), param(ID(WIDTH)));
1140 port(ID(ADDR), param(ID(ABITS)));
1141 port(ID(DATA), param(ID(WIDTH)));
1142 check_expected();
1143 return;
1144 }
1145
1146 if (cell->type == ID($meminit)) {
1147 param(ID(MEMID));
1148 param(ID(PRIORITY));
1149 port(ID(ADDR), param(ID(ABITS)));
1150 port(ID(DATA), param(ID(WIDTH)) * param(ID(WORDS)));
1151 check_expected();
1152 return;
1153 }
1154
1155 if (cell->type == ID($mem)) {
1156 param(ID(MEMID));
1157 param(ID(SIZE));
1158 param(ID(OFFSET));
1159 param(ID(INIT));
1160 param_bits(ID(RD_CLK_ENABLE), max(1, param(ID(RD_PORTS))));
1161 param_bits(ID(RD_CLK_POLARITY), max(1, param(ID(RD_PORTS))));
1162 param_bits(ID(RD_TRANSPARENT), max(1, param(ID(RD_PORTS))));
1163 param_bits(ID(WR_CLK_ENABLE), max(1, param(ID(WR_PORTS))));
1164 param_bits(ID(WR_CLK_POLARITY), max(1, param(ID(WR_PORTS))));
1165 port(ID(RD_CLK), param(ID(RD_PORTS)));
1166 port(ID(RD_EN), param(ID(RD_PORTS)));
1167 port(ID(RD_ADDR), param(ID(RD_PORTS)) * param(ID(ABITS)));
1168 port(ID(RD_DATA), param(ID(RD_PORTS)) * param(ID(WIDTH)));
1169 port(ID(WR_CLK), param(ID(WR_PORTS)));
1170 port(ID(WR_EN), param(ID(WR_PORTS)) * param(ID(WIDTH)));
1171 port(ID(WR_ADDR), param(ID(WR_PORTS)) * param(ID(ABITS)));
1172 port(ID(WR_DATA), param(ID(WR_PORTS)) * param(ID(WIDTH)));
1173 check_expected();
1174 return;
1175 }
1176
1177 if (cell->type == ID($tribuf)) {
1178 port(ID::A, param(ID(WIDTH)));
1179 port(ID::Y, param(ID(WIDTH)));
1180 port(ID(EN), 1);
1181 check_expected();
1182 return;
1183 }
1184
1185 if (cell->type.in(ID($assert), ID($assume), ID($live), ID($fair), ID($cover))) {
1186 port(ID::A, 1);
1187 port(ID(EN), 1);
1188 check_expected();
1189 return;
1190 }
1191
1192 if (cell->type == ID($initstate)) {
1193 port(ID::Y, 1);
1194 check_expected();
1195 return;
1196 }
1197
1198 if (cell->type.in(ID($anyconst), ID($anyseq), ID($allconst), ID($allseq))) {
1199 port(ID::Y, param(ID(WIDTH)));
1200 check_expected();
1201 return;
1202 }
1203
1204 if (cell->type == ID($equiv)) {
1205 port(ID::A, 1);
1206 port(ID::B, 1);
1207 port(ID::Y, 1);
1208 check_expected();
1209 return;
1210 }
1211
1212 if (cell->type.in(ID($specify2), ID($specify3))) {
1213 param_bool(ID(FULL));
1214 param_bool(ID(SRC_DST_PEN));
1215 param_bool(ID(SRC_DST_POL));
1216 param(ID(T_RISE_MIN));
1217 param(ID(T_RISE_TYP));
1218 param(ID(T_RISE_MAX));
1219 param(ID(T_FALL_MIN));
1220 param(ID(T_FALL_TYP));
1221 param(ID(T_FALL_MAX));
1222 port(ID(EN), 1);
1223 port(ID(SRC), param(ID(SRC_WIDTH)));
1224 port(ID(DST), param(ID(DST_WIDTH)));
1225 if (cell->type == ID($specify3)) {
1226 param_bool(ID(EDGE_EN));
1227 param_bool(ID(EDGE_POL));
1228 param_bool(ID(DAT_DST_PEN));
1229 param_bool(ID(DAT_DST_POL));
1230 port(ID(DAT), param(ID(DST_WIDTH)));
1231 }
1232 check_expected();
1233 return;
1234 }
1235
1236 if (cell->type == ID($specrule)) {
1237 param(ID(TYPE));
1238 param_bool(ID(SRC_PEN));
1239 param_bool(ID(SRC_POL));
1240 param_bool(ID(DST_PEN));
1241 param_bool(ID(DST_POL));
1242 param(ID(T_LIMIT));
1243 param(ID(T_LIMIT2));
1244 port(ID(SRC_EN), 1);
1245 port(ID(DST_EN), 1);
1246 port(ID(SRC), param(ID(SRC_WIDTH)));
1247 port(ID(DST), param(ID(DST_WIDTH)));
1248 check_expected();
1249 return;
1250 }
1251
1252 if (cell->type == ID($_BUF_)) { check_gate("AY"); return; }
1253 if (cell->type == ID($_NOT_)) { check_gate("AY"); return; }
1254 if (cell->type == ID($_AND_)) { check_gate("ABY"); return; }
1255 if (cell->type == ID($_NAND_)) { check_gate("ABY"); return; }
1256 if (cell->type == ID($_OR_)) { check_gate("ABY"); return; }
1257 if (cell->type == ID($_NOR_)) { check_gate("ABY"); return; }
1258 if (cell->type == ID($_XOR_)) { check_gate("ABY"); return; }
1259 if (cell->type == ID($_XNOR_)) { check_gate("ABY"); return; }
1260 if (cell->type == ID($_ANDNOT_)) { check_gate("ABY"); return; }
1261 if (cell->type == ID($_ORNOT_)) { check_gate("ABY"); return; }
1262 if (cell->type == ID($_MUX_)) { check_gate("ABSY"); return; }
1263 if (cell->type == ID($_NMUX_)) { check_gate("ABSY"); return; }
1264 if (cell->type == ID($_AOI3_)) { check_gate("ABCY"); return; }
1265 if (cell->type == ID($_OAI3_)) { check_gate("ABCY"); return; }
1266 if (cell->type == ID($_AOI4_)) { check_gate("ABCDY"); return; }
1267 if (cell->type == ID($_OAI4_)) { check_gate("ABCDY"); return; }
1268
1269 if (cell->type == ID($_TBUF_)) { check_gate("AYE"); return; }
1270
1271 if (cell->type == ID($_MUX4_)) { check_gate("ABCDSTY"); return; }
1272 if (cell->type == ID($_MUX8_)) { check_gate("ABCDEFGHSTUY"); return; }
1273 if (cell->type == ID($_MUX16_)) { check_gate("ABCDEFGHIJKLMNOPSTUVY"); return; }
1274
1275 if (cell->type == ID($_SR_NN_)) { check_gate("SRQ"); return; }
1276 if (cell->type == ID($_SR_NP_)) { check_gate("SRQ"); return; }
1277 if (cell->type == ID($_SR_PN_)) { check_gate("SRQ"); return; }
1278 if (cell->type == ID($_SR_PP_)) { check_gate("SRQ"); return; }
1279
1280 if (cell->type == ID($_FF_)) { check_gate("DQ"); return; }
1281 if (cell->type == ID($_DFF_N_)) { check_gate("DQC"); return; }
1282 if (cell->type == ID($_DFF_P_)) { check_gate("DQC"); return; }
1283
1284 if (cell->type == ID($_DFFE_NN_)) { check_gate("DQCE"); return; }
1285 if (cell->type == ID($_DFFE_NP_)) { check_gate("DQCE"); return; }
1286 if (cell->type == ID($_DFFE_PN_)) { check_gate("DQCE"); return; }
1287 if (cell->type == ID($_DFFE_PP_)) { check_gate("DQCE"); return; }
1288
1289 if (cell->type == ID($_DFF_NN0_)) { check_gate("DQCR"); return; }
1290 if (cell->type == ID($_DFF_NN1_)) { check_gate("DQCR"); return; }
1291 if (cell->type == ID($_DFF_NP0_)) { check_gate("DQCR"); return; }
1292 if (cell->type == ID($_DFF_NP1_)) { check_gate("DQCR"); return; }
1293 if (cell->type == ID($_DFF_PN0_)) { check_gate("DQCR"); return; }
1294 if (cell->type == ID($_DFF_PN1_)) { check_gate("DQCR"); return; }
1295 if (cell->type == ID($_DFF_PP0_)) { check_gate("DQCR"); return; }
1296 if (cell->type == ID($_DFF_PP1_)) { check_gate("DQCR"); return; }
1297
1298 if (cell->type == ID($_DFFSR_NNN_)) { check_gate("CSRDQ"); return; }
1299 if (cell->type == ID($_DFFSR_NNP_)) { check_gate("CSRDQ"); return; }
1300 if (cell->type == ID($_DFFSR_NPN_)) { check_gate("CSRDQ"); return; }
1301 if (cell->type == ID($_DFFSR_NPP_)) { check_gate("CSRDQ"); return; }
1302 if (cell->type == ID($_DFFSR_PNN_)) { check_gate("CSRDQ"); return; }
1303 if (cell->type == ID($_DFFSR_PNP_)) { check_gate("CSRDQ"); return; }
1304 if (cell->type == ID($_DFFSR_PPN_)) { check_gate("CSRDQ"); return; }
1305 if (cell->type == ID($_DFFSR_PPP_)) { check_gate("CSRDQ"); return; }
1306
1307 if (cell->type == ID($_DLATCH_N_)) { check_gate("EDQ"); return; }
1308 if (cell->type == ID($_DLATCH_P_)) { check_gate("EDQ"); return; }
1309
1310 if (cell->type == ID($_DLATCHSR_NNN_)) { check_gate("ESRDQ"); return; }
1311 if (cell->type == ID($_DLATCHSR_NNP_)) { check_gate("ESRDQ"); return; }
1312 if (cell->type == ID($_DLATCHSR_NPN_)) { check_gate("ESRDQ"); return; }
1313 if (cell->type == ID($_DLATCHSR_NPP_)) { check_gate("ESRDQ"); return; }
1314 if (cell->type == ID($_DLATCHSR_PNN_)) { check_gate("ESRDQ"); return; }
1315 if (cell->type == ID($_DLATCHSR_PNP_)) { check_gate("ESRDQ"); return; }
1316 if (cell->type == ID($_DLATCHSR_PPN_)) { check_gate("ESRDQ"); return; }
1317 if (cell->type == ID($_DLATCHSR_PPP_)) { check_gate("ESRDQ"); return; }
1318
1319 error(__LINE__);
1320 }
1321 };
1322 }
1323 #endif
1324
1325 void RTLIL::Module::sort()
1326 {
1327 wires_.sort(sort_by_id_str());
1328 cells_.sort(sort_by_id_str());
1329 avail_parameters.sort(sort_by_id_str());
1330 memories.sort(sort_by_id_str());
1331 processes.sort(sort_by_id_str());
1332 for (auto &it : cells_)
1333 it.second->sort();
1334 for (auto &it : wires_)
1335 it.second->attributes.sort(sort_by_id_str());
1336 for (auto &it : memories)
1337 it.second->attributes.sort(sort_by_id_str());
1338 }
1339
1340 void RTLIL::Module::check()
1341 {
1342 #ifndef NDEBUG
1343 std::vector<bool> ports_declared;
1344 for (auto &it : wires_) {
1345 log_assert(this == it.second->module);
1346 log_assert(it.first == it.second->name);
1347 log_assert(!it.first.empty());
1348 log_assert(it.second->width >= 0);
1349 log_assert(it.second->port_id >= 0);
1350 for (auto &it2 : it.second->attributes)
1351 log_assert(!it2.first.empty());
1352 if (it.second->port_id) {
1353 log_assert(GetSize(ports) >= it.second->port_id);
1354 log_assert(ports.at(it.second->port_id-1) == it.first);
1355 log_assert(it.second->port_input || it.second->port_output);
1356 if (GetSize(ports_declared) < it.second->port_id)
1357 ports_declared.resize(it.second->port_id);
1358 log_assert(ports_declared[it.second->port_id-1] == false);
1359 ports_declared[it.second->port_id-1] = true;
1360 } else
1361 log_assert(!it.second->port_input && !it.second->port_output);
1362 }
1363 for (auto port_declared : ports_declared)
1364 log_assert(port_declared == true);
1365 log_assert(GetSize(ports) == GetSize(ports_declared));
1366
1367 for (auto &it : memories) {
1368 log_assert(it.first == it.second->name);
1369 log_assert(!it.first.empty());
1370 log_assert(it.second->width >= 0);
1371 log_assert(it.second->size >= 0);
1372 for (auto &it2 : it.second->attributes)
1373 log_assert(!it2.first.empty());
1374 }
1375
1376 for (auto &it : cells_) {
1377 log_assert(this == it.second->module);
1378 log_assert(it.first == it.second->name);
1379 log_assert(!it.first.empty());
1380 log_assert(!it.second->type.empty());
1381 for (auto &it2 : it.second->connections()) {
1382 log_assert(!it2.first.empty());
1383 it2.second.check();
1384 }
1385 for (auto &it2 : it.second->attributes)
1386 log_assert(!it2.first.empty());
1387 for (auto &it2 : it.second->parameters)
1388 log_assert(!it2.first.empty());
1389 InternalCellChecker checker(this, it.second);
1390 checker.check();
1391 }
1392
1393 for (auto &it : processes) {
1394 log_assert(it.first == it.second->name);
1395 log_assert(!it.first.empty());
1396 log_assert(it.second->root_case.compare.empty());
1397 std::vector<CaseRule*> all_cases = {&it.second->root_case};
1398 for (size_t i = 0; i < all_cases.size(); i++) {
1399 for (auto &switch_it : all_cases[i]->switches) {
1400 for (auto &case_it : switch_it->cases) {
1401 for (auto &compare_it : case_it->compare) {
1402 log_assert(switch_it->signal.size() == compare_it.size());
1403 }
1404 all_cases.push_back(case_it);
1405 }
1406 }
1407 }
1408 for (auto &sync_it : it.second->syncs) {
1409 switch (sync_it->type) {
1410 case SyncType::ST0:
1411 case SyncType::ST1:
1412 case SyncType::STp:
1413 case SyncType::STn:
1414 case SyncType::STe:
1415 log_assert(!sync_it->signal.empty());
1416 break;
1417 case SyncType::STa:
1418 case SyncType::STg:
1419 case SyncType::STi:
1420 log_assert(sync_it->signal.empty());
1421 break;
1422 }
1423 }
1424 }
1425
1426 for (auto &it : connections_) {
1427 log_assert(it.first.size() == it.second.size());
1428 log_assert(!it.first.has_const());
1429 it.first.check();
1430 it.second.check();
1431 }
1432
1433 for (auto &it : attributes)
1434 log_assert(!it.first.empty());
1435 #endif
1436 }
1437
1438 void RTLIL::Module::optimize()
1439 {
1440 }
1441
1442 void RTLIL::Module::cloneInto(RTLIL::Module *new_mod) const
1443 {
1444 log_assert(new_mod->refcount_wires_ == 0);
1445 log_assert(new_mod->refcount_cells_ == 0);
1446
1447 new_mod->avail_parameters = avail_parameters;
1448
1449 for (auto &conn : connections_)
1450 new_mod->connect(conn);
1451
1452 for (auto &attr : attributes)
1453 new_mod->attributes[attr.first] = attr.second;
1454
1455 for (auto &it : wires_)
1456 new_mod->addWire(it.first, it.second);
1457
1458 for (auto &it : memories)
1459 new_mod->memories[it.first] = new RTLIL::Memory(*it.second);
1460
1461 for (auto &it : cells_)
1462 new_mod->addCell(it.first, it.second);
1463
1464 for (auto &it : processes)
1465 new_mod->processes[it.first] = it.second->clone();
1466
1467 struct RewriteSigSpecWorker
1468 {
1469 RTLIL::Module *mod;
1470 void operator()(RTLIL::SigSpec &sig)
1471 {
1472 std::vector<RTLIL::SigChunk> chunks = sig.chunks();
1473 for (auto &c : chunks)
1474 if (c.wire != NULL)
1475 c.wire = mod->wires_.at(c.wire->name);
1476 sig = chunks;
1477 }
1478 };
1479
1480 RewriteSigSpecWorker rewriteSigSpecWorker;
1481 rewriteSigSpecWorker.mod = new_mod;
1482 new_mod->rewrite_sigspecs(rewriteSigSpecWorker);
1483 new_mod->fixup_ports();
1484 }
1485
1486 RTLIL::Module *RTLIL::Module::clone() const
1487 {
1488 RTLIL::Module *new_mod = new RTLIL::Module;
1489 new_mod->name = name;
1490 cloneInto(new_mod);
1491 return new_mod;
1492 }
1493
1494 bool RTLIL::Module::has_memories() const
1495 {
1496 return !memories.empty();
1497 }
1498
1499 bool RTLIL::Module::has_processes() const
1500 {
1501 return !processes.empty();
1502 }
1503
1504 bool RTLIL::Module::has_memories_warn() const
1505 {
1506 if (!memories.empty())
1507 log_warning("Ignoring module %s because it contains memories (run 'memory' command first).\n", log_id(this));
1508 return !memories.empty();
1509 }
1510
1511 bool RTLIL::Module::has_processes_warn() const
1512 {
1513 if (!processes.empty())
1514 log_warning("Ignoring module %s because it contains processes (run 'proc' command first).\n", log_id(this));
1515 return !processes.empty();
1516 }
1517
1518 std::vector<RTLIL::Wire*> RTLIL::Module::selected_wires() const
1519 {
1520 std::vector<RTLIL::Wire*> result;
1521 result.reserve(wires_.size());
1522 for (auto &it : wires_)
1523 if (design->selected(this, it.second))
1524 result.push_back(it.second);
1525 return result;
1526 }
1527
1528 std::vector<RTLIL::Cell*> RTLIL::Module::selected_cells() const
1529 {
1530 std::vector<RTLIL::Cell*> result;
1531 result.reserve(wires_.size());
1532 for (auto &it : cells_)
1533 if (design->selected(this, it.second))
1534 result.push_back(it.second);
1535 return result;
1536 }
1537
1538 void RTLIL::Module::add(RTLIL::Wire *wire)
1539 {
1540 log_assert(!wire->name.empty());
1541 log_assert(count_id(wire->name) == 0);
1542 log_assert(refcount_wires_ == 0);
1543 wires_[wire->name] = wire;
1544 wire->module = this;
1545 }
1546
1547 void RTLIL::Module::add(RTLIL::Cell *cell)
1548 {
1549 log_assert(!cell->name.empty());
1550 log_assert(count_id(cell->name) == 0);
1551 log_assert(refcount_cells_ == 0);
1552 cells_[cell->name] = cell;
1553 cell->module = this;
1554 }
1555
1556 void RTLIL::Module::remove(const pool<RTLIL::Wire*> &wires)
1557 {
1558 log_assert(refcount_wires_ == 0);
1559
1560 struct DeleteWireWorker
1561 {
1562 RTLIL::Module *module;
1563 const pool<RTLIL::Wire*> *wires_p;
1564
1565 void operator()(RTLIL::SigSpec &sig) {
1566 std::vector<RTLIL::SigChunk> chunks = sig;
1567 for (auto &c : chunks)
1568 if (c.wire != NULL && wires_p->count(c.wire)) {
1569 c.wire = module->addWire(NEW_ID, c.width);
1570 c.offset = 0;
1571 }
1572 sig = chunks;
1573 }
1574
1575 void operator()(RTLIL::SigSpec &lhs, RTLIL::SigSpec &rhs) {
1576 log_assert(GetSize(lhs) == GetSize(rhs));
1577 RTLIL::SigSpec new_lhs, new_rhs;
1578 for (int i = 0; i < GetSize(lhs); i++) {
1579 RTLIL::SigBit lhs_bit = lhs[i];
1580 if (lhs_bit.wire != nullptr && wires_p->count(lhs_bit.wire))
1581 continue;
1582 RTLIL::SigBit rhs_bit = rhs[i];
1583 if (rhs_bit.wire != nullptr && wires_p->count(rhs_bit.wire))
1584 continue;
1585 new_lhs.append(lhs_bit);
1586 new_rhs.append(rhs_bit);
1587 }
1588 lhs = new_lhs;
1589 rhs = new_rhs;
1590 }
1591 };
1592
1593 DeleteWireWorker delete_wire_worker;
1594 delete_wire_worker.module = this;
1595 delete_wire_worker.wires_p = &wires;
1596 rewrite_sigspecs2(delete_wire_worker);
1597
1598 for (auto &it : wires) {
1599 log_assert(wires_.count(it->name) != 0);
1600 wires_.erase(it->name);
1601 delete it;
1602 }
1603 }
1604
1605 void RTLIL::Module::remove(RTLIL::Cell *cell)
1606 {
1607 while (!cell->connections_.empty())
1608 cell->unsetPort(cell->connections_.begin()->first);
1609
1610 log_assert(cells_.count(cell->name) != 0);
1611 log_assert(refcount_cells_ == 0);
1612 cells_.erase(cell->name);
1613 delete cell;
1614 }
1615
1616 void RTLIL::Module::rename(RTLIL::Wire *wire, RTLIL::IdString new_name)
1617 {
1618 log_assert(wires_[wire->name] == wire);
1619 log_assert(refcount_wires_ == 0);
1620 wires_.erase(wire->name);
1621 wire->name = new_name;
1622 add(wire);
1623 }
1624
1625 void RTLIL::Module::rename(RTLIL::Cell *cell, RTLIL::IdString new_name)
1626 {
1627 log_assert(cells_[cell->name] == cell);
1628 log_assert(refcount_wires_ == 0);
1629 cells_.erase(cell->name);
1630 cell->name = new_name;
1631 add(cell);
1632 }
1633
1634 void RTLIL::Module::rename(RTLIL::IdString old_name, RTLIL::IdString new_name)
1635 {
1636 log_assert(count_id(old_name) != 0);
1637 if (wires_.count(old_name))
1638 rename(wires_.at(old_name), new_name);
1639 else if (cells_.count(old_name))
1640 rename(cells_.at(old_name), new_name);
1641 else
1642 log_abort();
1643 }
1644
1645 void RTLIL::Module::swap_names(RTLIL::Wire *w1, RTLIL::Wire *w2)
1646 {
1647 log_assert(wires_[w1->name] == w1);
1648 log_assert(wires_[w2->name] == w2);
1649 log_assert(refcount_wires_ == 0);
1650
1651 wires_.erase(w1->name);
1652 wires_.erase(w2->name);
1653
1654 std::swap(w1->name, w2->name);
1655
1656 wires_[w1->name] = w1;
1657 wires_[w2->name] = w2;
1658 }
1659
1660 void RTLIL::Module::swap_names(RTLIL::Cell *c1, RTLIL::Cell *c2)
1661 {
1662 log_assert(cells_[c1->name] == c1);
1663 log_assert(cells_[c2->name] == c2);
1664 log_assert(refcount_cells_ == 0);
1665
1666 cells_.erase(c1->name);
1667 cells_.erase(c2->name);
1668
1669 std::swap(c1->name, c2->name);
1670
1671 cells_[c1->name] = c1;
1672 cells_[c2->name] = c2;
1673 }
1674
1675 RTLIL::IdString RTLIL::Module::uniquify(RTLIL::IdString name)
1676 {
1677 int index = 0;
1678 return uniquify(name, index);
1679 }
1680
1681 RTLIL::IdString RTLIL::Module::uniquify(RTLIL::IdString name, int &index)
1682 {
1683 if (index == 0) {
1684 if (count_id(name) == 0)
1685 return name;
1686 index++;
1687 }
1688
1689 while (1) {
1690 RTLIL::IdString new_name = stringf("%s_%d", name.c_str(), index);
1691 if (count_id(new_name) == 0)
1692 return new_name;
1693 index++;
1694 }
1695 }
1696
1697 static bool fixup_ports_compare(const RTLIL::Wire *a, const RTLIL::Wire *b)
1698 {
1699 if (a->port_id && !b->port_id)
1700 return true;
1701 if (!a->port_id && b->port_id)
1702 return false;
1703
1704 if (a->port_id == b->port_id)
1705 return a->name < b->name;
1706 return a->port_id < b->port_id;
1707 }
1708
1709 void RTLIL::Module::connect(const RTLIL::SigSig &conn)
1710 {
1711 for (auto mon : monitors)
1712 mon->notify_connect(this, conn);
1713
1714 if (design)
1715 for (auto mon : design->monitors)
1716 mon->notify_connect(this, conn);
1717
1718 // ignore all attempts to assign constants to other constants
1719 if (conn.first.has_const()) {
1720 RTLIL::SigSig new_conn;
1721 for (int i = 0; i < GetSize(conn.first); i++)
1722 if (conn.first[i].wire) {
1723 new_conn.first.append(conn.first[i]);
1724 new_conn.second.append(conn.second[i]);
1725 }
1726 if (GetSize(new_conn.first))
1727 connect(new_conn);
1728 return;
1729 }
1730
1731 if (yosys_xtrace) {
1732 log("#X# Connect (SigSig) in %s: %s = %s (%d bits)\n", log_id(this), log_signal(conn.first), log_signal(conn.second), GetSize(conn.first));
1733 log_backtrace("-X- ", yosys_xtrace-1);
1734 }
1735
1736 log_assert(GetSize(conn.first) == GetSize(conn.second));
1737 connections_.push_back(conn);
1738 }
1739
1740 void RTLIL::Module::connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs)
1741 {
1742 connect(RTLIL::SigSig(lhs, rhs));
1743 }
1744
1745 void RTLIL::Module::new_connections(const std::vector<RTLIL::SigSig> &new_conn)
1746 {
1747 for (auto mon : monitors)
1748 mon->notify_connect(this, new_conn);
1749
1750 if (design)
1751 for (auto mon : design->monitors)
1752 mon->notify_connect(this, new_conn);
1753
1754 if (yosys_xtrace) {
1755 log("#X# New connections vector in %s:\n", log_id(this));
1756 for (auto &conn: new_conn)
1757 log("#X# %s = %s (%d bits)\n", log_signal(conn.first), log_signal(conn.second), GetSize(conn.first));
1758 log_backtrace("-X- ", yosys_xtrace-1);
1759 }
1760
1761 connections_ = new_conn;
1762 }
1763
1764 const std::vector<RTLIL::SigSig> &RTLIL::Module::connections() const
1765 {
1766 return connections_;
1767 }
1768
1769 void RTLIL::Module::fixup_ports()
1770 {
1771 std::vector<RTLIL::Wire*> all_ports;
1772
1773 for (auto &w : wires_)
1774 if (w.second->port_input || w.second->port_output)
1775 all_ports.push_back(w.second);
1776 else
1777 w.second->port_id = 0;
1778
1779 std::sort(all_ports.begin(), all_ports.end(), fixup_ports_compare);
1780
1781 ports.clear();
1782 for (size_t i = 0; i < all_ports.size(); i++) {
1783 ports.push_back(all_ports[i]->name);
1784 all_ports[i]->port_id = i+1;
1785 }
1786 }
1787
1788 RTLIL::Wire *RTLIL::Module::addWire(RTLIL::IdString name, int width)
1789 {
1790 RTLIL::Wire *wire = new RTLIL::Wire;
1791 wire->name = name;
1792 wire->width = width;
1793 add(wire);
1794 return wire;
1795 }
1796
1797 RTLIL::Wire *RTLIL::Module::addWire(RTLIL::IdString name, const RTLIL::Wire *other)
1798 {
1799 RTLIL::Wire *wire = addWire(name);
1800 wire->width = other->width;
1801 wire->start_offset = other->start_offset;
1802 wire->port_id = other->port_id;
1803 wire->port_input = other->port_input;
1804 wire->port_output = other->port_output;
1805 wire->upto = other->upto;
1806 wire->attributes = other->attributes;
1807 return wire;
1808 }
1809
1810 RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, RTLIL::IdString type)
1811 {
1812 RTLIL::Cell *cell = new RTLIL::Cell;
1813 cell->name = name;
1814 cell->type = type;
1815 add(cell);
1816 return cell;
1817 }
1818
1819 RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, const RTLIL::Cell *other)
1820 {
1821 RTLIL::Cell *cell = addCell(name, other->type);
1822 cell->connections_ = other->connections_;
1823 cell->parameters = other->parameters;
1824 cell->attributes = other->attributes;
1825 return cell;
1826 }
1827
1828 #define DEF_METHOD(_func, _y_size, _type) \
1829 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed, const std::string &src) { \
1830 RTLIL::Cell *cell = addCell(name, _type); \
1831 cell->parameters[ID(A_SIGNED)] = is_signed; \
1832 cell->parameters[ID(A_WIDTH)] = sig_a.size(); \
1833 cell->parameters[ID(Y_WIDTH)] = sig_y.size(); \
1834 cell->setPort(ID::A, sig_a); \
1835 cell->setPort(ID::Y, sig_y); \
1836 cell->set_src_attribute(src); \
1837 return cell; \
1838 } \
1839 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed, const std::string &src) { \
1840 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
1841 add ## _func(name, sig_a, sig_y, is_signed, src); \
1842 return sig_y; \
1843 }
1844 DEF_METHOD(Not, sig_a.size(), ID($not))
1845 DEF_METHOD(Pos, sig_a.size(), ID($pos))
1846 DEF_METHOD(Neg, sig_a.size(), ID($neg))
1847 DEF_METHOD(ReduceAnd, 1, ID($reduce_and))
1848 DEF_METHOD(ReduceOr, 1, ID($reduce_or))
1849 DEF_METHOD(ReduceXor, 1, ID($reduce_xor))
1850 DEF_METHOD(ReduceXnor, 1, ID($reduce_xnor))
1851 DEF_METHOD(ReduceBool, 1, ID($reduce_bool))
1852 DEF_METHOD(LogicNot, 1, ID($logic_not))
1853 #undef DEF_METHOD
1854
1855 #define DEF_METHOD(_func, _y_size, _type) \
1856 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed, const std::string &src) { \
1857 RTLIL::Cell *cell = addCell(name, _type); \
1858 cell->parameters[ID(A_SIGNED)] = is_signed; \
1859 cell->parameters[ID(B_SIGNED)] = is_signed; \
1860 cell->parameters[ID(A_WIDTH)] = sig_a.size(); \
1861 cell->parameters[ID(B_WIDTH)] = sig_b.size(); \
1862 cell->parameters[ID(Y_WIDTH)] = sig_y.size(); \
1863 cell->setPort(ID::A, sig_a); \
1864 cell->setPort(ID::B, sig_b); \
1865 cell->setPort(ID::Y, sig_y); \
1866 cell->set_src_attribute(src); \
1867 return cell; \
1868 } \
1869 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed, const std::string &src) { \
1870 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
1871 add ## _func(name, sig_a, sig_b, sig_y, is_signed, src); \
1872 return sig_y; \
1873 }
1874 DEF_METHOD(And, max(sig_a.size(), sig_b.size()), ID($and))
1875 DEF_METHOD(Or, max(sig_a.size(), sig_b.size()), ID($or))
1876 DEF_METHOD(Xor, max(sig_a.size(), sig_b.size()), ID($xor))
1877 DEF_METHOD(Xnor, max(sig_a.size(), sig_b.size()), ID($xnor))
1878 DEF_METHOD(Shl, sig_a.size(), ID($shl))
1879 DEF_METHOD(Shr, sig_a.size(), ID($shr))
1880 DEF_METHOD(Sshl, sig_a.size(), ID($sshl))
1881 DEF_METHOD(Sshr, sig_a.size(), ID($sshr))
1882 DEF_METHOD(Shift, sig_a.size(), ID($shift))
1883 DEF_METHOD(Shiftx, sig_a.size(), ID($shiftx))
1884 DEF_METHOD(Lt, 1, ID($lt))
1885 DEF_METHOD(Le, 1, ID($le))
1886 DEF_METHOD(Eq, 1, ID($eq))
1887 DEF_METHOD(Ne, 1, ID($ne))
1888 DEF_METHOD(Eqx, 1, ID($eqx))
1889 DEF_METHOD(Nex, 1, ID($nex))
1890 DEF_METHOD(Ge, 1, ID($ge))
1891 DEF_METHOD(Gt, 1, ID($gt))
1892 DEF_METHOD(Add, max(sig_a.size(), sig_b.size()), ID($add))
1893 DEF_METHOD(Sub, max(sig_a.size(), sig_b.size()), ID($sub))
1894 DEF_METHOD(Mul, max(sig_a.size(), sig_b.size()), ID($mul))
1895 DEF_METHOD(Div, max(sig_a.size(), sig_b.size()), ID($div))
1896 DEF_METHOD(Mod, max(sig_a.size(), sig_b.size()), ID($mod))
1897 DEF_METHOD(LogicAnd, 1, ID($logic_and))
1898 DEF_METHOD(LogicOr, 1, ID($logic_or))
1899 #undef DEF_METHOD
1900
1901 #define DEF_METHOD(_func, _type, _pmux) \
1902 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, RTLIL::SigSpec sig_y, const std::string &src) { \
1903 RTLIL::Cell *cell = addCell(name, _type); \
1904 cell->parameters[ID(WIDTH)] = sig_a.size(); \
1905 if (_pmux) cell->parameters[ID(S_WIDTH)] = sig_s.size(); \
1906 cell->setPort(ID::A, sig_a); \
1907 cell->setPort(ID::B, sig_b); \
1908 cell->setPort(ID(S), sig_s); \
1909 cell->setPort(ID::Y, sig_y); \
1910 cell->set_src_attribute(src); \
1911 return cell; \
1912 } \
1913 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, const std::string &src) { \
1914 RTLIL::SigSpec sig_y = addWire(NEW_ID, sig_a.size()); \
1915 add ## _func(name, sig_a, sig_b, sig_s, sig_y, src); \
1916 return sig_y; \
1917 }
1918 DEF_METHOD(Mux, ID($mux), 0)
1919 DEF_METHOD(Pmux, ID($pmux), 1)
1920 #undef DEF_METHOD
1921
1922 #define DEF_METHOD_2(_func, _type, _P1, _P2) \
1923 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, const std::string &src) { \
1924 RTLIL::Cell *cell = addCell(name, _type); \
1925 cell->setPort("\\" #_P1, sig1); \
1926 cell->setPort("\\" #_P2, sig2); \
1927 cell->set_src_attribute(src); \
1928 return cell; \
1929 } \
1930 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, const std::string &src) { \
1931 RTLIL::SigBit sig2 = addWire(NEW_ID); \
1932 add ## _func(name, sig1, sig2, src); \
1933 return sig2; \
1934 }
1935 #define DEF_METHOD_3(_func, _type, _P1, _P2, _P3) \
1936 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, const std::string &src) { \
1937 RTLIL::Cell *cell = addCell(name, _type); \
1938 cell->setPort("\\" #_P1, sig1); \
1939 cell->setPort("\\" #_P2, sig2); \
1940 cell->setPort("\\" #_P3, sig3); \
1941 cell->set_src_attribute(src); \
1942 return cell; \
1943 } \
1944 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, const std::string &src) { \
1945 RTLIL::SigBit sig3 = addWire(NEW_ID); \
1946 add ## _func(name, sig1, sig2, sig3, src); \
1947 return sig3; \
1948 }
1949 #define DEF_METHOD_4(_func, _type, _P1, _P2, _P3, _P4) \
1950 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, RTLIL::SigBit sig4, const std::string &src) { \
1951 RTLIL::Cell *cell = addCell(name, _type); \
1952 cell->setPort("\\" #_P1, sig1); \
1953 cell->setPort("\\" #_P2, sig2); \
1954 cell->setPort("\\" #_P3, sig3); \
1955 cell->setPort("\\" #_P4, sig4); \
1956 cell->set_src_attribute(src); \
1957 return cell; \
1958 } \
1959 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, const std::string &src) { \
1960 RTLIL::SigBit sig4 = addWire(NEW_ID); \
1961 add ## _func(name, sig1, sig2, sig3, sig4, src); \
1962 return sig4; \
1963 }
1964 #define DEF_METHOD_5(_func, _type, _P1, _P2, _P3, _P4, _P5) \
1965 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, RTLIL::SigBit sig4, RTLIL::SigBit sig5, const std::string &src) { \
1966 RTLIL::Cell *cell = addCell(name, _type); \
1967 cell->setPort("\\" #_P1, sig1); \
1968 cell->setPort("\\" #_P2, sig2); \
1969 cell->setPort("\\" #_P3, sig3); \
1970 cell->setPort("\\" #_P4, sig4); \
1971 cell->setPort("\\" #_P5, sig5); \
1972 cell->set_src_attribute(src); \
1973 return cell; \
1974 } \
1975 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, RTLIL::SigBit sig4, const std::string &src) { \
1976 RTLIL::SigBit sig5 = addWire(NEW_ID); \
1977 add ## _func(name, sig1, sig2, sig3, sig4, sig5, src); \
1978 return sig5; \
1979 }
1980 DEF_METHOD_2(BufGate, ID($_BUF_), A, Y)
1981 DEF_METHOD_2(NotGate, ID($_NOT_), A, Y)
1982 DEF_METHOD_3(AndGate, ID($_AND_), A, B, Y)
1983 DEF_METHOD_3(NandGate, ID($_NAND_), A, B, Y)
1984 DEF_METHOD_3(OrGate, ID($_OR_), A, B, Y)
1985 DEF_METHOD_3(NorGate, ID($_NOR_), A, B, Y)
1986 DEF_METHOD_3(XorGate, ID($_XOR_), A, B, Y)
1987 DEF_METHOD_3(XnorGate, ID($_XNOR_), A, B, Y)
1988 DEF_METHOD_3(AndnotGate, ID($_ANDNOT_), A, B, Y)
1989 DEF_METHOD_3(OrnotGate, ID($_ORNOT_), A, B, Y)
1990 DEF_METHOD_4(MuxGate, ID($_MUX_), A, B, S, Y)
1991 DEF_METHOD_4(NmuxGate, ID($_NMUX_), A, B, S, Y)
1992 DEF_METHOD_4(Aoi3Gate, ID($_AOI3_), A, B, C, Y)
1993 DEF_METHOD_4(Oai3Gate, ID($_OAI3_), A, B, C, Y)
1994 DEF_METHOD_5(Aoi4Gate, ID($_AOI4_), A, B, C, D, Y)
1995 DEF_METHOD_5(Oai4Gate, ID($_OAI4_), A, B, C, D, Y)
1996 #undef DEF_METHOD_2
1997 #undef DEF_METHOD_3
1998 #undef DEF_METHOD_4
1999 #undef DEF_METHOD_5
2000
2001 RTLIL::Cell* RTLIL::Module::addPow(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool a_signed, bool b_signed, const std::string &src)
2002 {
2003 RTLIL::Cell *cell = addCell(name, ID($pow));
2004 cell->parameters[ID(A_SIGNED)] = a_signed;
2005 cell->parameters[ID(B_SIGNED)] = b_signed;
2006 cell->parameters[ID(A_WIDTH)] = sig_a.size();
2007 cell->parameters[ID(B_WIDTH)] = sig_b.size();
2008 cell->parameters[ID(Y_WIDTH)] = sig_y.size();
2009 cell->setPort(ID::A, sig_a);
2010 cell->setPort(ID::B, sig_b);
2011 cell->setPort(ID::Y, sig_y);
2012 cell->set_src_attribute(src);
2013 return cell;
2014 }
2015
2016 RTLIL::Cell* RTLIL::Module::addSlice(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, RTLIL::Const offset, const std::string &src)
2017 {
2018 RTLIL::Cell *cell = addCell(name, ID($slice));
2019 cell->parameters[ID(A_WIDTH)] = sig_a.size();
2020 cell->parameters[ID(Y_WIDTH)] = sig_y.size();
2021 cell->parameters[ID(OFFSET)] = offset;
2022 cell->setPort(ID::A, sig_a);
2023 cell->setPort(ID::Y, sig_y);
2024 cell->set_src_attribute(src);
2025 return cell;
2026 }
2027
2028 RTLIL::Cell* RTLIL::Module::addConcat(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, const std::string &src)
2029 {
2030 RTLIL::Cell *cell = addCell(name, ID($concat));
2031 cell->parameters[ID(A_WIDTH)] = sig_a.size();
2032 cell->parameters[ID(B_WIDTH)] = sig_b.size();
2033 cell->setPort(ID::A, sig_a);
2034 cell->setPort(ID::B, sig_b);
2035 cell->setPort(ID::Y, sig_y);
2036 cell->set_src_attribute(src);
2037 return cell;
2038 }
2039
2040 RTLIL::Cell* RTLIL::Module::addLut(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, RTLIL::Const lut, const std::string &src)
2041 {
2042 RTLIL::Cell *cell = addCell(name, ID($lut));
2043 cell->parameters[ID(LUT)] = lut;
2044 cell->parameters[ID(WIDTH)] = sig_a.size();
2045 cell->setPort(ID::A, sig_a);
2046 cell->setPort(ID::Y, sig_y);
2047 cell->set_src_attribute(src);
2048 return cell;
2049 }
2050
2051 RTLIL::Cell* RTLIL::Module::addTribuf(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_y, const std::string &src)
2052 {
2053 RTLIL::Cell *cell = addCell(name, ID($tribuf));
2054 cell->parameters[ID(WIDTH)] = sig_a.size();
2055 cell->setPort(ID::A, sig_a);
2056 cell->setPort(ID(EN), sig_en);
2057 cell->setPort(ID::Y, sig_y);
2058 cell->set_src_attribute(src);
2059 return cell;
2060 }
2061
2062 RTLIL::Cell* RTLIL::Module::addAssert(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src)
2063 {
2064 RTLIL::Cell *cell = addCell(name, ID($assert));
2065 cell->setPort(ID::A, sig_a);
2066 cell->setPort(ID(EN), sig_en);
2067 cell->set_src_attribute(src);
2068 return cell;
2069 }
2070
2071 RTLIL::Cell* RTLIL::Module::addAssume(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src)
2072 {
2073 RTLIL::Cell *cell = addCell(name, ID($assume));
2074 cell->setPort(ID::A, sig_a);
2075 cell->setPort(ID(EN), sig_en);
2076 cell->set_src_attribute(src);
2077 return cell;
2078 }
2079
2080 RTLIL::Cell* RTLIL::Module::addLive(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src)
2081 {
2082 RTLIL::Cell *cell = addCell(name, ID($live));
2083 cell->setPort(ID::A, sig_a);
2084 cell->setPort(ID(EN), sig_en);
2085 cell->set_src_attribute(src);
2086 return cell;
2087 }
2088
2089 RTLIL::Cell* RTLIL::Module::addFair(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src)
2090 {
2091 RTLIL::Cell *cell = addCell(name, ID($fair));
2092 cell->setPort(ID::A, sig_a);
2093 cell->setPort(ID(EN), sig_en);
2094 cell->set_src_attribute(src);
2095 return cell;
2096 }
2097
2098 RTLIL::Cell* RTLIL::Module::addCover(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src)
2099 {
2100 RTLIL::Cell *cell = addCell(name, ID($cover));
2101 cell->setPort(ID::A, sig_a);
2102 cell->setPort(ID(EN), sig_en);
2103 cell->set_src_attribute(src);
2104 return cell;
2105 }
2106
2107 RTLIL::Cell* RTLIL::Module::addEquiv(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, const std::string &src)
2108 {
2109 RTLIL::Cell *cell = addCell(name, ID($equiv));
2110 cell->setPort(ID::A, sig_a);
2111 cell->setPort(ID::B, sig_b);
2112 cell->setPort(ID::Y, sig_y);
2113 cell->set_src_attribute(src);
2114 return cell;
2115 }
2116
2117 RTLIL::Cell* RTLIL::Module::addSr(RTLIL::IdString name, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr, RTLIL::SigSpec sig_q, bool set_polarity, bool clr_polarity, const std::string &src)
2118 {
2119 RTLIL::Cell *cell = addCell(name, ID($sr));
2120 cell->parameters[ID(SET_POLARITY)] = set_polarity;
2121 cell->parameters[ID(CLR_POLARITY)] = clr_polarity;
2122 cell->parameters[ID(WIDTH)] = sig_q.size();
2123 cell->setPort(ID(SET), sig_set);
2124 cell->setPort(ID(CLR), sig_clr);
2125 cell->setPort(ID(Q), sig_q);
2126 cell->set_src_attribute(src);
2127 return cell;
2128 }
2129
2130 RTLIL::Cell* RTLIL::Module::addFf(RTLIL::IdString name, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, const std::string &src)
2131 {
2132 RTLIL::Cell *cell = addCell(name, ID($ff));
2133 cell->parameters[ID(WIDTH)] = sig_q.size();
2134 cell->setPort(ID(D), sig_d);
2135 cell->setPort(ID(Q), sig_q);
2136 cell->set_src_attribute(src);
2137 return cell;
2138 }
2139
2140 RTLIL::Cell* RTLIL::Module::addDff(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, const std::string &src)
2141 {
2142 RTLIL::Cell *cell = addCell(name, ID($dff));
2143 cell->parameters[ID(CLK_POLARITY)] = clk_polarity;
2144 cell->parameters[ID(WIDTH)] = sig_q.size();
2145 cell->setPort(ID(CLK), sig_clk);
2146 cell->setPort(ID(D), sig_d);
2147 cell->setPort(ID(Q), sig_q);
2148 cell->set_src_attribute(src);
2149 return cell;
2150 }
2151
2152 RTLIL::Cell* RTLIL::Module::addDffe(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, bool en_polarity, const std::string &src)
2153 {
2154 RTLIL::Cell *cell = addCell(name, ID($dffe));
2155 cell->parameters[ID(CLK_POLARITY)] = clk_polarity;
2156 cell->parameters[ID(EN_POLARITY)] = en_polarity;
2157 cell->parameters[ID(WIDTH)] = sig_q.size();
2158 cell->setPort(ID(CLK), sig_clk);
2159 cell->setPort(ID(EN), sig_en);
2160 cell->setPort(ID(D), sig_d);
2161 cell->setPort(ID(Q), sig_q);
2162 cell->set_src_attribute(src);
2163 return cell;
2164 }
2165
2166 RTLIL::Cell* RTLIL::Module::addDffsr(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
2167 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
2168 {
2169 RTLIL::Cell *cell = addCell(name, ID($dffsr));
2170 cell->parameters[ID(CLK_POLARITY)] = clk_polarity;
2171 cell->parameters[ID(SET_POLARITY)] = set_polarity;
2172 cell->parameters[ID(CLR_POLARITY)] = clr_polarity;
2173 cell->parameters[ID(WIDTH)] = sig_q.size();
2174 cell->setPort(ID(CLK), sig_clk);
2175 cell->setPort(ID(SET), sig_set);
2176 cell->setPort(ID(CLR), sig_clr);
2177 cell->setPort(ID(D), sig_d);
2178 cell->setPort(ID(Q), sig_q);
2179 cell->set_src_attribute(src);
2180 return cell;
2181 }
2182
2183 RTLIL::Cell* RTLIL::Module::addAdff(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_arst, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q,
2184 RTLIL::Const arst_value, bool clk_polarity, bool arst_polarity, const std::string &src)
2185 {
2186 RTLIL::Cell *cell = addCell(name, ID($adff));
2187 cell->parameters[ID(CLK_POLARITY)] = clk_polarity;
2188 cell->parameters[ID(ARST_POLARITY)] = arst_polarity;
2189 cell->parameters[ID(ARST_VALUE)] = arst_value;
2190 cell->parameters[ID(WIDTH)] = sig_q.size();
2191 cell->setPort(ID(CLK), sig_clk);
2192 cell->setPort(ID(ARST), sig_arst);
2193 cell->setPort(ID(D), sig_d);
2194 cell->setPort(ID(Q), sig_q);
2195 cell->set_src_attribute(src);
2196 return cell;
2197 }
2198
2199 RTLIL::Cell* RTLIL::Module::addDlatch(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity, const std::string &src)
2200 {
2201 RTLIL::Cell *cell = addCell(name, ID($dlatch));
2202 cell->parameters[ID(EN_POLARITY)] = en_polarity;
2203 cell->parameters[ID(WIDTH)] = sig_q.size();
2204 cell->setPort(ID(EN), sig_en);
2205 cell->setPort(ID(D), sig_d);
2206 cell->setPort(ID(Q), sig_q);
2207 cell->set_src_attribute(src);
2208 return cell;
2209 }
2210
2211 RTLIL::Cell* RTLIL::Module::addDlatchsr(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
2212 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
2213 {
2214 RTLIL::Cell *cell = addCell(name, ID($dlatchsr));
2215 cell->parameters[ID(EN_POLARITY)] = en_polarity;
2216 cell->parameters[ID(SET_POLARITY)] = set_polarity;
2217 cell->parameters[ID(CLR_POLARITY)] = clr_polarity;
2218 cell->parameters[ID(WIDTH)] = sig_q.size();
2219 cell->setPort(ID(EN), sig_en);
2220 cell->setPort(ID(SET), sig_set);
2221 cell->setPort(ID(CLR), sig_clr);
2222 cell->setPort(ID(D), sig_d);
2223 cell->setPort(ID(Q), sig_q);
2224 cell->set_src_attribute(src);
2225 return cell;
2226 }
2227
2228 RTLIL::Cell* RTLIL::Module::addFfGate(RTLIL::IdString name, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, const std::string &src)
2229 {
2230 RTLIL::Cell *cell = addCell(name, ID($_FF_));
2231 cell->setPort(ID(D), sig_d);
2232 cell->setPort(ID(Q), sig_q);
2233 cell->set_src_attribute(src);
2234 return cell;
2235 }
2236
2237 RTLIL::Cell* RTLIL::Module::addDffGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, const std::string &src)
2238 {
2239 RTLIL::Cell *cell = addCell(name, stringf("$_DFF_%c_", clk_polarity ? 'P' : 'N'));
2240 cell->setPort(ID(C), sig_clk);
2241 cell->setPort(ID(D), sig_d);
2242 cell->setPort(ID(Q), sig_q);
2243 cell->set_src_attribute(src);
2244 return cell;
2245 }
2246
2247 RTLIL::Cell* RTLIL::Module::addDffeGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, bool en_polarity, const std::string &src)
2248 {
2249 RTLIL::Cell *cell = addCell(name, stringf("$_DFFE_%c%c_", clk_polarity ? 'P' : 'N', en_polarity ? 'P' : 'N'));
2250 cell->setPort(ID(C), sig_clk);
2251 cell->setPort(ID(E), sig_en);
2252 cell->setPort(ID(D), sig_d);
2253 cell->setPort(ID(Q), sig_q);
2254 cell->set_src_attribute(src);
2255 return cell;
2256 }
2257
2258 RTLIL::Cell* RTLIL::Module::addDffsrGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
2259 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
2260 {
2261 RTLIL::Cell *cell = addCell(name, stringf("$_DFFSR_%c%c%c_", clk_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N'));
2262 cell->setPort(ID(C), sig_clk);
2263 cell->setPort(ID(S), sig_set);
2264 cell->setPort(ID(R), sig_clr);
2265 cell->setPort(ID(D), sig_d);
2266 cell->setPort(ID(Q), sig_q);
2267 cell->set_src_attribute(src);
2268 return cell;
2269 }
2270
2271 RTLIL::Cell* RTLIL::Module::addAdffGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_arst, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q,
2272 bool arst_value, bool clk_polarity, bool arst_polarity, const std::string &src)
2273 {
2274 RTLIL::Cell *cell = addCell(name, stringf("$_DFF_%c%c%c_", clk_polarity ? 'P' : 'N', arst_polarity ? 'P' : 'N', arst_value ? '1' : '0'));
2275 cell->setPort(ID(C), sig_clk);
2276 cell->setPort(ID(R), sig_arst);
2277 cell->setPort(ID(D), sig_d);
2278 cell->setPort(ID(Q), sig_q);
2279 cell->set_src_attribute(src);
2280 return cell;
2281 }
2282
2283 RTLIL::Cell* RTLIL::Module::addDlatchGate(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity, const std::string &src)
2284 {
2285 RTLIL::Cell *cell = addCell(name, stringf("$_DLATCH_%c_", en_polarity ? 'P' : 'N'));
2286 cell->setPort(ID(E), sig_en);
2287 cell->setPort(ID(D), sig_d);
2288 cell->setPort(ID(Q), sig_q);
2289 cell->set_src_attribute(src);
2290 return cell;
2291 }
2292
2293 RTLIL::Cell* RTLIL::Module::addDlatchsrGate(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
2294 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
2295 {
2296 RTLIL::Cell *cell = addCell(name, stringf("$_DLATCHSR_%c%c%c_", en_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N'));
2297 cell->setPort(ID(E), sig_en);
2298 cell->setPort(ID(S), sig_set);
2299 cell->setPort(ID(R), sig_clr);
2300 cell->setPort(ID(D), sig_d);
2301 cell->setPort(ID(Q), sig_q);
2302 cell->set_src_attribute(src);
2303 return cell;
2304 }
2305
2306 RTLIL::SigSpec RTLIL::Module::Anyconst(RTLIL::IdString name, int width, const std::string &src)
2307 {
2308 RTLIL::SigSpec sig = addWire(NEW_ID, width);
2309 Cell *cell = addCell(name, ID($anyconst));
2310 cell->setParam(ID(WIDTH), width);
2311 cell->setPort(ID::Y, sig);
2312 cell->set_src_attribute(src);
2313 return sig;
2314 }
2315
2316 RTLIL::SigSpec RTLIL::Module::Anyseq(RTLIL::IdString name, int width, const std::string &src)
2317 {
2318 RTLIL::SigSpec sig = addWire(NEW_ID, width);
2319 Cell *cell = addCell(name, ID($anyseq));
2320 cell->setParam(ID(WIDTH), width);
2321 cell->setPort(ID::Y, sig);
2322 cell->set_src_attribute(src);
2323 return sig;
2324 }
2325
2326 RTLIL::SigSpec RTLIL::Module::Allconst(RTLIL::IdString name, int width, const std::string &src)
2327 {
2328 RTLIL::SigSpec sig = addWire(NEW_ID, width);
2329 Cell *cell = addCell(name, ID($allconst));
2330 cell->setParam(ID(WIDTH), width);
2331 cell->setPort(ID::Y, sig);
2332 cell->set_src_attribute(src);
2333 return sig;
2334 }
2335
2336 RTLIL::SigSpec RTLIL::Module::Allseq(RTLIL::IdString name, int width, const std::string &src)
2337 {
2338 RTLIL::SigSpec sig = addWire(NEW_ID, width);
2339 Cell *cell = addCell(name, ID($allseq));
2340 cell->setParam(ID(WIDTH), width);
2341 cell->setPort(ID::Y, sig);
2342 cell->set_src_attribute(src);
2343 return sig;
2344 }
2345
2346 RTLIL::SigSpec RTLIL::Module::Initstate(RTLIL::IdString name, const std::string &src)
2347 {
2348 RTLIL::SigSpec sig = addWire(NEW_ID);
2349 Cell *cell = addCell(name, ID($initstate));
2350 cell->setPort(ID::Y, sig);
2351 cell->set_src_attribute(src);
2352 return sig;
2353 }
2354
2355 RTLIL::Wire::Wire()
2356 {
2357 static unsigned int hashidx_count = 123456789;
2358 hashidx_count = mkhash_xorshift(hashidx_count);
2359 hashidx_ = hashidx_count;
2360
2361 module = nullptr;
2362 width = 1;
2363 start_offset = 0;
2364 port_id = 0;
2365 port_input = false;
2366 port_output = false;
2367 upto = false;
2368
2369 #ifdef WITH_PYTHON
2370 RTLIL::Wire::get_all_wires()->insert(std::pair<unsigned int, RTLIL::Wire*>(hashidx_, this));
2371 #endif
2372 }
2373
2374 RTLIL::Wire::~Wire()
2375 {
2376 #ifdef WITH_PYTHON
2377 RTLIL::Wire::get_all_wires()->erase(hashidx_);
2378 #endif
2379 }
2380
2381 #ifdef WITH_PYTHON
2382 static std::map<unsigned int, RTLIL::Wire*> all_wires;
2383 std::map<unsigned int, RTLIL::Wire*> *RTLIL::Wire::get_all_wires(void)
2384 {
2385 return &all_wires;
2386 }
2387 #endif
2388
2389 RTLIL::Memory::Memory()
2390 {
2391 static unsigned int hashidx_count = 123456789;
2392 hashidx_count = mkhash_xorshift(hashidx_count);
2393 hashidx_ = hashidx_count;
2394
2395 width = 1;
2396 start_offset = 0;
2397 size = 0;
2398 #ifdef WITH_PYTHON
2399 RTLIL::Memory::get_all_memorys()->insert(std::pair<unsigned int, RTLIL::Memory*>(hashidx_, this));
2400 #endif
2401 }
2402
2403 RTLIL::Cell::Cell() : module(nullptr)
2404 {
2405 static unsigned int hashidx_count = 123456789;
2406 hashidx_count = mkhash_xorshift(hashidx_count);
2407 hashidx_ = hashidx_count;
2408
2409 // log("#memtrace# %p\n", this);
2410 memhasher();
2411
2412 #ifdef WITH_PYTHON
2413 RTLIL::Cell::get_all_cells()->insert(std::pair<unsigned int, RTLIL::Cell*>(hashidx_, this));
2414 #endif
2415 }
2416
2417 RTLIL::Cell::~Cell()
2418 {
2419 #ifdef WITH_PYTHON
2420 RTLIL::Cell::get_all_cells()->erase(hashidx_);
2421 #endif
2422 }
2423
2424 #ifdef WITH_PYTHON
2425 static std::map<unsigned int, RTLIL::Cell*> all_cells;
2426 std::map<unsigned int, RTLIL::Cell*> *RTLIL::Cell::get_all_cells(void)
2427 {
2428 return &all_cells;
2429 }
2430 #endif
2431
2432 bool RTLIL::Cell::hasPort(RTLIL::IdString portname) const
2433 {
2434 return connections_.count(portname) != 0;
2435 }
2436
2437 void RTLIL::Cell::unsetPort(RTLIL::IdString portname)
2438 {
2439 RTLIL::SigSpec signal;
2440 auto conn_it = connections_.find(portname);
2441
2442 if (conn_it != connections_.end())
2443 {
2444 for (auto mon : module->monitors)
2445 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
2446
2447 if (module->design)
2448 for (auto mon : module->design->monitors)
2449 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
2450
2451 if (yosys_xtrace) {
2452 log("#X# Unconnect %s.%s.%s\n", log_id(this->module), log_id(this), log_id(portname));
2453 log_backtrace("-X- ", yosys_xtrace-1);
2454 }
2455
2456 connections_.erase(conn_it);
2457 }
2458 }
2459
2460 void RTLIL::Cell::setPort(RTLIL::IdString portname, RTLIL::SigSpec signal)
2461 {
2462 auto conn_it = connections_.find(portname);
2463
2464 if (conn_it == connections_.end()) {
2465 connections_[portname] = RTLIL::SigSpec();
2466 conn_it = connections_.find(portname);
2467 log_assert(conn_it != connections_.end());
2468 } else
2469 if (conn_it->second == signal)
2470 return;
2471
2472 for (auto mon : module->monitors)
2473 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
2474
2475 if (module->design)
2476 for (auto mon : module->design->monitors)
2477 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
2478
2479 if (yosys_xtrace) {
2480 log("#X# Connect %s.%s.%s = %s (%d)\n", log_id(this->module), log_id(this), log_id(portname), log_signal(signal), GetSize(signal));
2481 log_backtrace("-X- ", yosys_xtrace-1);
2482 }
2483
2484 conn_it->second = signal;
2485 }
2486
2487 const RTLIL::SigSpec &RTLIL::Cell::getPort(RTLIL::IdString portname) const
2488 {
2489 return connections_.at(portname);
2490 }
2491
2492 const dict<RTLIL::IdString, RTLIL::SigSpec> &RTLIL::Cell::connections() const
2493 {
2494 return connections_;
2495 }
2496
2497 bool RTLIL::Cell::known() const
2498 {
2499 if (yosys_celltypes.cell_known(type))
2500 return true;
2501 if (module && module->design && module->design->module(type))
2502 return true;
2503 return false;
2504 }
2505
2506 bool RTLIL::Cell::input(RTLIL::IdString portname) const
2507 {
2508 if (yosys_celltypes.cell_known(type))
2509 return yosys_celltypes.cell_input(type, portname);
2510 if (module && module->design) {
2511 RTLIL::Module *m = module->design->module(type);
2512 RTLIL::Wire *w = m ? m->wire(portname) : nullptr;
2513 return w && w->port_input;
2514 }
2515 return false;
2516 }
2517
2518 bool RTLIL::Cell::output(RTLIL::IdString portname) const
2519 {
2520 if (yosys_celltypes.cell_known(type))
2521 return yosys_celltypes.cell_output(type, portname);
2522 if (module && module->design) {
2523 RTLIL::Module *m = module->design->module(type);
2524 RTLIL::Wire *w = m ? m->wire(portname) : nullptr;
2525 return w && w->port_output;
2526 }
2527 return false;
2528 }
2529
2530 bool RTLIL::Cell::hasParam(RTLIL::IdString paramname) const
2531 {
2532 return parameters.count(paramname) != 0;
2533 }
2534
2535 void RTLIL::Cell::unsetParam(RTLIL::IdString paramname)
2536 {
2537 parameters.erase(paramname);
2538 }
2539
2540 void RTLIL::Cell::setParam(RTLIL::IdString paramname, RTLIL::Const value)
2541 {
2542 parameters[paramname] = value;
2543 }
2544
2545 const RTLIL::Const &RTLIL::Cell::getParam(RTLIL::IdString paramname) const
2546 {
2547 return parameters.at(paramname);
2548 }
2549
2550 void RTLIL::Cell::sort()
2551 {
2552 connections_.sort(sort_by_id_str());
2553 parameters.sort(sort_by_id_str());
2554 attributes.sort(sort_by_id_str());
2555 }
2556
2557 void RTLIL::Cell::check()
2558 {
2559 #ifndef NDEBUG
2560 InternalCellChecker checker(NULL, this);
2561 checker.check();
2562 #endif
2563 }
2564
2565 void RTLIL::Cell::fixup_parameters(bool set_a_signed, bool set_b_signed)
2566 {
2567 if (!type.begins_with("$") || type.begins_with("$_") || type.begins_with("$paramod") || type.begins_with("$fmcombine") ||
2568 type.begins_with("$verific$") || type.begins_with("$array:") || type.begins_with("$extern:"))
2569 return;
2570
2571 if (type == ID($mux) || type == ID($pmux)) {
2572 parameters[ID(WIDTH)] = GetSize(connections_[ID::Y]);
2573 if (type == ID($pmux))
2574 parameters[ID(S_WIDTH)] = GetSize(connections_[ID(S)]);
2575 check();
2576 return;
2577 }
2578
2579 if (type == ID($lut) || type == ID($sop)) {
2580 parameters[ID(WIDTH)] = GetSize(connections_[ID::A]);
2581 return;
2582 }
2583
2584 if (type == ID($fa)) {
2585 parameters[ID(WIDTH)] = GetSize(connections_[ID::Y]);
2586 return;
2587 }
2588
2589 if (type == ID($lcu)) {
2590 parameters[ID(WIDTH)] = GetSize(connections_[ID(CO)]);
2591 return;
2592 }
2593
2594 bool signedness_ab = !type.in(ID($slice), ID($concat), ID($macc));
2595
2596 if (connections_.count(ID::A)) {
2597 if (signedness_ab) {
2598 if (set_a_signed)
2599 parameters[ID(A_SIGNED)] = true;
2600 else if (parameters.count(ID(A_SIGNED)) == 0)
2601 parameters[ID(A_SIGNED)] = false;
2602 }
2603 parameters[ID(A_WIDTH)] = GetSize(connections_[ID::A]);
2604 }
2605
2606 if (connections_.count(ID::B)) {
2607 if (signedness_ab) {
2608 if (set_b_signed)
2609 parameters[ID(B_SIGNED)] = true;
2610 else if (parameters.count(ID(B_SIGNED)) == 0)
2611 parameters[ID(B_SIGNED)] = false;
2612 }
2613 parameters[ID(B_WIDTH)] = GetSize(connections_[ID::B]);
2614 }
2615
2616 if (connections_.count(ID::Y))
2617 parameters[ID(Y_WIDTH)] = GetSize(connections_[ID::Y]);
2618
2619 if (connections_.count(ID(Q)))
2620 parameters[ID(WIDTH)] = GetSize(connections_[ID(Q)]);
2621
2622 check();
2623 }
2624
2625 RTLIL::SigChunk::SigChunk()
2626 {
2627 wire = NULL;
2628 width = 0;
2629 offset = 0;
2630 }
2631
2632 RTLIL::SigChunk::SigChunk(const RTLIL::Const &value)
2633 {
2634 wire = NULL;
2635 data = value.bits;
2636 width = GetSize(data);
2637 offset = 0;
2638 }
2639
2640 RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire)
2641 {
2642 log_assert(wire != nullptr);
2643 this->wire = wire;
2644 this->width = wire->width;
2645 this->offset = 0;
2646 }
2647
2648 RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire, int offset, int width)
2649 {
2650 log_assert(wire != nullptr);
2651 this->wire = wire;
2652 this->width = width;
2653 this->offset = offset;
2654 }
2655
2656 RTLIL::SigChunk::SigChunk(const std::string &str)
2657 {
2658 wire = NULL;
2659 data = RTLIL::Const(str).bits;
2660 width = GetSize(data);
2661 offset = 0;
2662 }
2663
2664 RTLIL::SigChunk::SigChunk(int val, int width)
2665 {
2666 wire = NULL;
2667 data = RTLIL::Const(val, width).bits;
2668 this->width = GetSize(data);
2669 offset = 0;
2670 }
2671
2672 RTLIL::SigChunk::SigChunk(RTLIL::State bit, int width)
2673 {
2674 wire = NULL;
2675 data = RTLIL::Const(bit, width).bits;
2676 this->width = GetSize(data);
2677 offset = 0;
2678 }
2679
2680 RTLIL::SigChunk::SigChunk(RTLIL::SigBit bit)
2681 {
2682 wire = bit.wire;
2683 offset = 0;
2684 if (wire == NULL)
2685 data = RTLIL::Const(bit.data).bits;
2686 else
2687 offset = bit.offset;
2688 width = 1;
2689 }
2690
2691 RTLIL::SigChunk::SigChunk(const RTLIL::SigChunk &sigchunk) : data(sigchunk.data)
2692 {
2693 wire = sigchunk.wire;
2694 data = sigchunk.data;
2695 width = sigchunk.width;
2696 offset = sigchunk.offset;
2697 }
2698
2699 RTLIL::SigChunk RTLIL::SigChunk::extract(int offset, int length) const
2700 {
2701 RTLIL::SigChunk ret;
2702 if (wire) {
2703 ret.wire = wire;
2704 ret.offset = this->offset + offset;
2705 ret.width = length;
2706 } else {
2707 for (int i = 0; i < length; i++)
2708 ret.data.push_back(data[offset+i]);
2709 ret.width = length;
2710 }
2711 return ret;
2712 }
2713
2714 bool RTLIL::SigChunk::operator <(const RTLIL::SigChunk &other) const
2715 {
2716 if (wire && other.wire)
2717 if (wire->name != other.wire->name)
2718 return wire->name < other.wire->name;
2719
2720 if (wire != other.wire)
2721 return wire < other.wire;
2722
2723 if (offset != other.offset)
2724 return offset < other.offset;
2725
2726 if (width != other.width)
2727 return width < other.width;
2728
2729 return data < other.data;
2730 }
2731
2732 bool RTLIL::SigChunk::operator ==(const RTLIL::SigChunk &other) const
2733 {
2734 return wire == other.wire && width == other.width && offset == other.offset && data == other.data;
2735 }
2736
2737 bool RTLIL::SigChunk::operator !=(const RTLIL::SigChunk &other) const
2738 {
2739 if (*this == other)
2740 return false;
2741 return true;
2742 }
2743
2744 RTLIL::SigSpec::SigSpec()
2745 {
2746 width_ = 0;
2747 hash_ = 0;
2748 }
2749
2750 RTLIL::SigSpec::SigSpec(const RTLIL::SigSpec &other)
2751 {
2752 *this = other;
2753 }
2754
2755 RTLIL::SigSpec::SigSpec(std::initializer_list<RTLIL::SigSpec> parts)
2756 {
2757 cover("kernel.rtlil.sigspec.init.list");
2758
2759 width_ = 0;
2760 hash_ = 0;
2761
2762 std::vector<RTLIL::SigSpec> parts_vec(parts.begin(), parts.end());
2763 for (auto it = parts_vec.rbegin(); it != parts_vec.rend(); it++)
2764 append(*it);
2765 }
2766
2767 const RTLIL::SigSpec &RTLIL::SigSpec::operator=(const RTLIL::SigSpec &other)
2768 {
2769 cover("kernel.rtlil.sigspec.assign");
2770
2771 width_ = other.width_;
2772 hash_ = other.hash_;
2773 chunks_ = other.chunks_;
2774 bits_.clear();
2775
2776 if (!other.bits_.empty())
2777 {
2778 RTLIL::SigChunk *last = NULL;
2779 int last_end_offset = 0;
2780
2781 for (auto &bit : other.bits_) {
2782 if (last && bit.wire == last->wire) {
2783 if (bit.wire == NULL) {
2784 last->data.push_back(bit.data);
2785 last->width++;
2786 continue;
2787 } else if (last_end_offset == bit.offset) {
2788 last_end_offset++;
2789 last->width++;
2790 continue;
2791 }
2792 }
2793 chunks_.push_back(bit);
2794 last = &chunks_.back();
2795 last_end_offset = bit.offset + 1;
2796 }
2797
2798 check();
2799 }
2800
2801 return *this;
2802 }
2803
2804 RTLIL::SigSpec::SigSpec(const RTLIL::Const &value)
2805 {
2806 cover("kernel.rtlil.sigspec.init.const");
2807
2808 chunks_.push_back(RTLIL::SigChunk(value));
2809 width_ = chunks_.back().width;
2810 hash_ = 0;
2811 check();
2812 }
2813
2814 RTLIL::SigSpec::SigSpec(const RTLIL::SigChunk &chunk)
2815 {
2816 cover("kernel.rtlil.sigspec.init.chunk");
2817
2818 chunks_.push_back(chunk);
2819 width_ = chunks_.back().width;
2820 hash_ = 0;
2821 check();
2822 }
2823
2824 RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire)
2825 {
2826 cover("kernel.rtlil.sigspec.init.wire");
2827
2828 chunks_.push_back(RTLIL::SigChunk(wire));
2829 width_ = chunks_.back().width;
2830 hash_ = 0;
2831 check();
2832 }
2833
2834 RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire, int offset, int width)
2835 {
2836 cover("kernel.rtlil.sigspec.init.wire_part");
2837
2838 chunks_.push_back(RTLIL::SigChunk(wire, offset, width));
2839 width_ = chunks_.back().width;
2840 hash_ = 0;
2841 check();
2842 }
2843
2844 RTLIL::SigSpec::SigSpec(const std::string &str)
2845 {
2846 cover("kernel.rtlil.sigspec.init.str");
2847
2848 chunks_.push_back(RTLIL::SigChunk(str));
2849 width_ = chunks_.back().width;
2850 hash_ = 0;
2851 check();
2852 }
2853
2854 RTLIL::SigSpec::SigSpec(int val, int width)
2855 {
2856 cover("kernel.rtlil.sigspec.init.int");
2857
2858 chunks_.push_back(RTLIL::SigChunk(val, width));
2859 width_ = width;
2860 hash_ = 0;
2861 check();
2862 }
2863
2864 RTLIL::SigSpec::SigSpec(RTLIL::State bit, int width)
2865 {
2866 cover("kernel.rtlil.sigspec.init.state");
2867
2868 chunks_.push_back(RTLIL::SigChunk(bit, width));
2869 width_ = width;
2870 hash_ = 0;
2871 check();
2872 }
2873
2874 RTLIL::SigSpec::SigSpec(RTLIL::SigBit bit, int width)
2875 {
2876 cover("kernel.rtlil.sigspec.init.bit");
2877
2878 if (bit.wire == NULL)
2879 chunks_.push_back(RTLIL::SigChunk(bit.data, width));
2880 else
2881 for (int i = 0; i < width; i++)
2882 chunks_.push_back(bit);
2883 width_ = width;
2884 hash_ = 0;
2885 check();
2886 }
2887
2888 RTLIL::SigSpec::SigSpec(std::vector<RTLIL::SigChunk> chunks)
2889 {
2890 cover("kernel.rtlil.sigspec.init.stdvec_chunks");
2891
2892 width_ = 0;
2893 hash_ = 0;
2894 for (auto &c : chunks)
2895 append(c);
2896 check();
2897 }
2898
2899 RTLIL::SigSpec::SigSpec(std::vector<RTLIL::SigBit> bits)
2900 {
2901 cover("kernel.rtlil.sigspec.init.stdvec_bits");
2902
2903 width_ = 0;
2904 hash_ = 0;
2905 for (auto &bit : bits)
2906 append_bit(bit);
2907 check();
2908 }
2909
2910 RTLIL::SigSpec::SigSpec(pool<RTLIL::SigBit> bits)
2911 {
2912 cover("kernel.rtlil.sigspec.init.pool_bits");
2913
2914 width_ = 0;
2915 hash_ = 0;
2916 for (auto &bit : bits)
2917 append_bit(bit);
2918 check();
2919 }
2920
2921 RTLIL::SigSpec::SigSpec(std::set<RTLIL::SigBit> bits)
2922 {
2923 cover("kernel.rtlil.sigspec.init.stdset_bits");
2924
2925 width_ = 0;
2926 hash_ = 0;
2927 for (auto &bit : bits)
2928 append_bit(bit);
2929 check();
2930 }
2931
2932 RTLIL::SigSpec::SigSpec(bool bit)
2933 {
2934 cover("kernel.rtlil.sigspec.init.bool");
2935
2936 width_ = 0;
2937 hash_ = 0;
2938 append_bit(bit);
2939 check();
2940 }
2941
2942 void RTLIL::SigSpec::pack() const
2943 {
2944 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
2945
2946 if (that->bits_.empty())
2947 return;
2948
2949 cover("kernel.rtlil.sigspec.convert.pack");
2950 log_assert(that->chunks_.empty());
2951
2952 std::vector<RTLIL::SigBit> old_bits;
2953 old_bits.swap(that->bits_);
2954
2955 RTLIL::SigChunk *last = NULL;
2956 int last_end_offset = 0;
2957
2958 for (auto &bit : old_bits) {
2959 if (last && bit.wire == last->wire) {
2960 if (bit.wire == NULL) {
2961 last->data.push_back(bit.data);
2962 last->width++;
2963 continue;
2964 } else if (last_end_offset == bit.offset) {
2965 last_end_offset++;
2966 last->width++;
2967 continue;
2968 }
2969 }
2970 that->chunks_.push_back(bit);
2971 last = &that->chunks_.back();
2972 last_end_offset = bit.offset + 1;
2973 }
2974
2975 check();
2976 }
2977
2978 void RTLIL::SigSpec::unpack() const
2979 {
2980 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
2981
2982 if (that->chunks_.empty())
2983 return;
2984
2985 cover("kernel.rtlil.sigspec.convert.unpack");
2986 log_assert(that->bits_.empty());
2987
2988 that->bits_.reserve(that->width_);
2989 for (auto &c : that->chunks_)
2990 for (int i = 0; i < c.width; i++)
2991 that->bits_.push_back(RTLIL::SigBit(c, i));
2992
2993 that->chunks_.clear();
2994 that->hash_ = 0;
2995 }
2996
2997 void RTLIL::SigSpec::updhash() const
2998 {
2999 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
3000
3001 if (that->hash_ != 0)
3002 return;
3003
3004 cover("kernel.rtlil.sigspec.hash");
3005 that->pack();
3006
3007 that->hash_ = mkhash_init;
3008 for (auto &c : that->chunks_)
3009 if (c.wire == NULL) {
3010 for (auto &v : c.data)
3011 that->hash_ = mkhash(that->hash_, v);
3012 } else {
3013 that->hash_ = mkhash(that->hash_, c.wire->name.index_);
3014 that->hash_ = mkhash(that->hash_, c.offset);
3015 that->hash_ = mkhash(that->hash_, c.width);
3016 }
3017
3018 if (that->hash_ == 0)
3019 that->hash_ = 1;
3020 }
3021
3022 void RTLIL::SigSpec::sort()
3023 {
3024 unpack();
3025 cover("kernel.rtlil.sigspec.sort");
3026 std::sort(bits_.begin(), bits_.end());
3027 }
3028
3029 void RTLIL::SigSpec::sort_and_unify()
3030 {
3031 unpack();
3032 cover("kernel.rtlil.sigspec.sort_and_unify");
3033
3034 // A copy of the bits vector is used to prevent duplicating the logic from
3035 // SigSpec::SigSpec(std::vector<SigBit>). This incurrs an extra copy but
3036 // that isn't showing up as significant in profiles.
3037 std::vector<SigBit> unique_bits = bits_;
3038 std::sort(unique_bits.begin(), unique_bits.end());
3039 auto last = std::unique(unique_bits.begin(), unique_bits.end());
3040 unique_bits.erase(last, unique_bits.end());
3041
3042 *this = unique_bits;
3043 }
3044
3045 void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with)
3046 {
3047 replace(pattern, with, this);
3048 }
3049
3050 void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with, RTLIL::SigSpec *other) const
3051 {
3052 log_assert(other != NULL);
3053 log_assert(width_ == other->width_);
3054 log_assert(pattern.width_ == with.width_);
3055
3056 pattern.unpack();
3057 with.unpack();
3058 unpack();
3059 other->unpack();
3060
3061 for (int i = 0; i < GetSize(pattern.bits_); i++) {
3062 if (pattern.bits_[i].wire != NULL) {
3063 for (int j = 0; j < GetSize(bits_); j++) {
3064 if (bits_[j] == pattern.bits_[i]) {
3065 other->bits_[j] = with.bits_[i];
3066 }
3067 }
3068 }
3069 }
3070
3071 other->check();
3072 }
3073
3074 void RTLIL::SigSpec::replace(const dict<RTLIL::SigBit, RTLIL::SigBit> &rules)
3075 {
3076 replace(rules, this);
3077 }
3078
3079 void RTLIL::SigSpec::replace(const dict<RTLIL::SigBit, RTLIL::SigBit> &rules, RTLIL::SigSpec *other) const
3080 {
3081 cover("kernel.rtlil.sigspec.replace_dict");
3082
3083 log_assert(other != NULL);
3084 log_assert(width_ == other->width_);
3085
3086 unpack();
3087 other->unpack();
3088
3089 for (int i = 0; i < GetSize(bits_); i++) {
3090 auto it = rules.find(bits_[i]);
3091 if (it != rules.end())
3092 other->bits_[i] = it->second;
3093 }
3094
3095 other->check();
3096 }
3097
3098 void RTLIL::SigSpec::replace(const std::map<RTLIL::SigBit, RTLIL::SigBit> &rules)
3099 {
3100 replace(rules, this);
3101 }
3102
3103 void RTLIL::SigSpec::replace(const std::map<RTLIL::SigBit, RTLIL::SigBit> &rules, RTLIL::SigSpec *other) const
3104 {
3105 cover("kernel.rtlil.sigspec.replace_map");
3106
3107 log_assert(other != NULL);
3108 log_assert(width_ == other->width_);
3109
3110 unpack();
3111 other->unpack();
3112
3113 for (int i = 0; i < GetSize(bits_); i++) {
3114 auto it = rules.find(bits_[i]);
3115 if (it != rules.end())
3116 other->bits_[i] = it->second;
3117 }
3118
3119 other->check();
3120 }
3121
3122 void RTLIL::SigSpec::remove(const RTLIL::SigSpec &pattern)
3123 {
3124 remove2(pattern, NULL);
3125 }
3126
3127 void RTLIL::SigSpec::remove(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other) const
3128 {
3129 RTLIL::SigSpec tmp = *this;
3130 tmp.remove2(pattern, other);
3131 }
3132
3133 void RTLIL::SigSpec::remove2(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other)
3134 {
3135 if (other)
3136 cover("kernel.rtlil.sigspec.remove_other");
3137 else
3138 cover("kernel.rtlil.sigspec.remove");
3139
3140 unpack();
3141 if (other != NULL) {
3142 log_assert(width_ == other->width_);
3143 other->unpack();
3144 }
3145
3146 for (int i = GetSize(bits_) - 1; i >= 0; i--)
3147 {
3148 if (bits_[i].wire == NULL) continue;
3149
3150 for (auto &pattern_chunk : pattern.chunks())
3151 if (bits_[i].wire == pattern_chunk.wire &&
3152 bits_[i].offset >= pattern_chunk.offset &&
3153 bits_[i].offset < pattern_chunk.offset + pattern_chunk.width) {
3154 bits_.erase(bits_.begin() + i);
3155 width_--;
3156 if (other != NULL) {
3157 other->bits_.erase(other->bits_.begin() + i);
3158 other->width_--;
3159 }
3160 break;
3161 }
3162 }
3163
3164 check();
3165 }
3166
3167 void RTLIL::SigSpec::remove(const pool<RTLIL::SigBit> &pattern)
3168 {
3169 remove2(pattern, NULL);
3170 }
3171
3172 void RTLIL::SigSpec::remove(const pool<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other) const
3173 {
3174 RTLIL::SigSpec tmp = *this;
3175 tmp.remove2(pattern, other);
3176 }
3177
3178 void RTLIL::SigSpec::remove2(const pool<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other)
3179 {
3180 if (other)
3181 cover("kernel.rtlil.sigspec.remove_other");
3182 else
3183 cover("kernel.rtlil.sigspec.remove");
3184
3185 unpack();
3186
3187 if (other != NULL) {
3188 log_assert(width_ == other->width_);
3189 other->unpack();
3190 }
3191
3192 for (int i = GetSize(bits_) - 1; i >= 0; i--) {
3193 if (bits_[i].wire != NULL && pattern.count(bits_[i])) {
3194 bits_.erase(bits_.begin() + i);
3195 width_--;
3196 if (other != NULL) {
3197 other->bits_.erase(other->bits_.begin() + i);
3198 other->width_--;
3199 }
3200 }
3201 }
3202
3203 check();
3204 }
3205
3206 void RTLIL::SigSpec::remove2(const std::set<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other)
3207 {
3208 if (other)
3209 cover("kernel.rtlil.sigspec.remove_other");
3210 else
3211 cover("kernel.rtlil.sigspec.remove");
3212
3213 unpack();
3214
3215 if (other != NULL) {
3216 log_assert(width_ == other->width_);
3217 other->unpack();
3218 }
3219
3220 for (int i = GetSize(bits_) - 1; i >= 0; i--) {
3221 if (bits_[i].wire != NULL && pattern.count(bits_[i])) {
3222 bits_.erase(bits_.begin() + i);
3223 width_--;
3224 if (other != NULL) {
3225 other->bits_.erase(other->bits_.begin() + i);
3226 other->width_--;
3227 }
3228 }
3229 }
3230
3231 check();
3232 }
3233
3234 RTLIL::SigSpec RTLIL::SigSpec::extract(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec *other) const
3235 {
3236 if (other)
3237 cover("kernel.rtlil.sigspec.extract_other");
3238 else
3239 cover("kernel.rtlil.sigspec.extract");
3240
3241 log_assert(other == NULL || width_ == other->width_);
3242
3243 RTLIL::SigSpec ret;
3244 std::vector<RTLIL::SigBit> bits_match = to_sigbit_vector();
3245
3246 for (auto& pattern_chunk : pattern.chunks()) {
3247 if (other) {
3248 std::vector<RTLIL::SigBit> bits_other = other->to_sigbit_vector();
3249 for (int i = 0; i < width_; i++)
3250 if (bits_match[i].wire &&
3251 bits_match[i].wire == pattern_chunk.wire &&
3252 bits_match[i].offset >= pattern_chunk.offset &&
3253 bits_match[i].offset < pattern_chunk.offset + pattern_chunk.width)
3254 ret.append_bit(bits_other[i]);
3255 } else {
3256 for (int i = 0; i < width_; i++)
3257 if (bits_match[i].wire &&
3258 bits_match[i].wire == pattern_chunk.wire &&
3259 bits_match[i].offset >= pattern_chunk.offset &&
3260 bits_match[i].offset < pattern_chunk.offset + pattern_chunk.width)
3261 ret.append_bit(bits_match[i]);
3262 }
3263 }
3264
3265 ret.check();
3266 return ret;
3267 }
3268
3269 RTLIL::SigSpec RTLIL::SigSpec::extract(const pool<RTLIL::SigBit> &pattern, const RTLIL::SigSpec *other) const
3270 {
3271 if (other)
3272 cover("kernel.rtlil.sigspec.extract_other");
3273 else
3274 cover("kernel.rtlil.sigspec.extract");
3275
3276 log_assert(other == NULL || width_ == other->width_);
3277
3278 std::vector<RTLIL::SigBit> bits_match = to_sigbit_vector();
3279 RTLIL::SigSpec ret;
3280
3281 if (other) {
3282 std::vector<RTLIL::SigBit> bits_other = other->to_sigbit_vector();
3283 for (int i = 0; i < width_; i++)
3284 if (bits_match[i].wire && pattern.count(bits_match[i]))
3285 ret.append_bit(bits_other[i]);
3286 } else {
3287 for (int i = 0; i < width_; i++)
3288 if (bits_match[i].wire && pattern.count(bits_match[i]))
3289 ret.append_bit(bits_match[i]);
3290 }
3291
3292 ret.check();
3293 return ret;
3294 }
3295
3296 void RTLIL::SigSpec::replace(int offset, const RTLIL::SigSpec &with)
3297 {
3298 cover("kernel.rtlil.sigspec.replace_pos");
3299
3300 unpack();
3301 with.unpack();
3302
3303 log_assert(offset >= 0);
3304 log_assert(with.width_ >= 0);
3305 log_assert(offset+with.width_ <= width_);
3306
3307 for (int i = 0; i < with.width_; i++)
3308 bits_.at(offset + i) = with.bits_.at(i);
3309
3310 check();
3311 }
3312
3313 void RTLIL::SigSpec::remove_const()
3314 {
3315 if (packed())
3316 {
3317 cover("kernel.rtlil.sigspec.remove_const.packed");
3318
3319 std::vector<RTLIL::SigChunk> new_chunks;
3320 new_chunks.reserve(GetSize(chunks_));
3321
3322 width_ = 0;
3323 for (auto &chunk : chunks_)
3324 if (chunk.wire != NULL) {
3325 new_chunks.push_back(chunk);
3326 width_ += chunk.width;
3327 }
3328
3329 chunks_.swap(new_chunks);
3330 }
3331 else
3332 {
3333 cover("kernel.rtlil.sigspec.remove_const.unpacked");
3334
3335 std::vector<RTLIL::SigBit> new_bits;
3336 new_bits.reserve(width_);
3337
3338 for (auto &bit : bits_)
3339 if (bit.wire != NULL)
3340 new_bits.push_back(bit);
3341
3342 bits_.swap(new_bits);
3343 width_ = bits_.size();
3344 }
3345
3346 check();
3347 }
3348
3349 void RTLIL::SigSpec::remove(int offset, int length)
3350 {
3351 cover("kernel.rtlil.sigspec.remove_pos");
3352
3353 unpack();
3354
3355 log_assert(offset >= 0);
3356 log_assert(length >= 0);
3357 log_assert(offset + length <= width_);
3358
3359 bits_.erase(bits_.begin() + offset, bits_.begin() + offset + length);
3360 width_ = bits_.size();
3361
3362 check();
3363 }
3364
3365 RTLIL::SigSpec RTLIL::SigSpec::extract(int offset, int length) const
3366 {
3367 unpack();
3368 cover("kernel.rtlil.sigspec.extract_pos");
3369 return std::vector<RTLIL::SigBit>(bits_.begin() + offset, bits_.begin() + offset + length);
3370 }
3371
3372 void RTLIL::SigSpec::append(const RTLIL::SigSpec &signal)
3373 {
3374 if (signal.width_ == 0)
3375 return;
3376
3377 if (width_ == 0) {
3378 *this = signal;
3379 return;
3380 }
3381
3382 cover("kernel.rtlil.sigspec.append");
3383
3384 if (packed() != signal.packed()) {
3385 pack();
3386 signal.pack();
3387 }
3388
3389 if (packed())
3390 for (auto &other_c : signal.chunks_)
3391 {
3392 auto &my_last_c = chunks_.back();
3393 if (my_last_c.wire == NULL && other_c.wire == NULL) {
3394 auto &this_data = my_last_c.data;
3395 auto &other_data = other_c.data;
3396 this_data.insert(this_data.end(), other_data.begin(), other_data.end());
3397 my_last_c.width += other_c.width;
3398 } else
3399 if (my_last_c.wire == other_c.wire && my_last_c.offset + my_last_c.width == other_c.offset) {
3400 my_last_c.width += other_c.width;
3401 } else
3402 chunks_.push_back(other_c);
3403 }
3404 else
3405 bits_.insert(bits_.end(), signal.bits_.begin(), signal.bits_.end());
3406
3407 width_ += signal.width_;
3408 check();
3409 }
3410
3411 void RTLIL::SigSpec::append_bit(const RTLIL::SigBit &bit)
3412 {
3413 if (packed())
3414 {
3415 cover("kernel.rtlil.sigspec.append_bit.packed");
3416
3417 if (chunks_.size() == 0)
3418 chunks_.push_back(bit);
3419 else
3420 if (bit.wire == NULL)
3421 if (chunks_.back().wire == NULL) {
3422 chunks_.back().data.push_back(bit.data);
3423 chunks_.back().width++;
3424 } else
3425 chunks_.push_back(bit);
3426 else
3427 if (chunks_.back().wire == bit.wire && chunks_.back().offset + chunks_.back().width == bit.offset)
3428 chunks_.back().width++;
3429 else
3430 chunks_.push_back(bit);
3431 }
3432 else
3433 {
3434 cover("kernel.rtlil.sigspec.append_bit.unpacked");
3435 bits_.push_back(bit);
3436 }
3437
3438 width_++;
3439 check();
3440 }
3441
3442 void RTLIL::SigSpec::extend_u0(int width, bool is_signed)
3443 {
3444 cover("kernel.rtlil.sigspec.extend_u0");
3445
3446 pack();
3447
3448 if (width_ > width)
3449 remove(width, width_ - width);
3450
3451 if (width_ < width) {
3452 RTLIL::SigBit padding = width_ > 0 ? (*this)[width_ - 1] : RTLIL::State::Sx;
3453 if (!is_signed)
3454 padding = RTLIL::State::S0;
3455 while (width_ < width)
3456 append(padding);
3457 }
3458
3459 }
3460
3461 RTLIL::SigSpec RTLIL::SigSpec::repeat(int num) const
3462 {
3463 cover("kernel.rtlil.sigspec.repeat");
3464
3465 RTLIL::SigSpec sig;
3466 for (int i = 0; i < num; i++)
3467 sig.append(*this);
3468 return sig;
3469 }
3470
3471 #ifndef NDEBUG
3472 void RTLIL::SigSpec::check() const
3473 {
3474 if (width_ > 64)
3475 {
3476 cover("kernel.rtlil.sigspec.check.skip");
3477 }
3478 else if (packed())
3479 {
3480 cover("kernel.rtlil.sigspec.check.packed");
3481
3482 int w = 0;
3483 for (size_t i = 0; i < chunks_.size(); i++) {
3484 const RTLIL::SigChunk chunk = chunks_[i];
3485 if (chunk.wire == NULL) {
3486 if (i > 0)
3487 log_assert(chunks_[i-1].wire != NULL);
3488 log_assert(chunk.offset == 0);
3489 log_assert(chunk.data.size() == (size_t)chunk.width);
3490 } else {
3491 if (i > 0 && chunks_[i-1].wire == chunk.wire)
3492 log_assert(chunk.offset != chunks_[i-1].offset + chunks_[i-1].width);
3493 log_assert(chunk.offset >= 0);
3494 log_assert(chunk.width >= 0);
3495 log_assert(chunk.offset + chunk.width <= chunk.wire->width);
3496 log_assert(chunk.data.size() == 0);
3497 }
3498 w += chunk.width;
3499 }
3500 log_assert(w == width_);
3501 log_assert(bits_.empty());
3502 }
3503 else
3504 {
3505 cover("kernel.rtlil.sigspec.check.unpacked");
3506
3507 log_assert(width_ == GetSize(bits_));
3508 log_assert(chunks_.empty());
3509 }
3510 }
3511 #endif
3512
3513 bool RTLIL::SigSpec::operator <(const RTLIL::SigSpec &other) const
3514 {
3515 cover("kernel.rtlil.sigspec.comp_lt");
3516
3517 if (this == &other)
3518 return false;
3519
3520 if (width_ != other.width_)
3521 return width_ < other.width_;
3522
3523 pack();
3524 other.pack();
3525
3526 if (chunks_.size() != other.chunks_.size())
3527 return chunks_.size() < other.chunks_.size();
3528
3529 updhash();
3530 other.updhash();
3531
3532 if (hash_ != other.hash_)
3533 return hash_ < other.hash_;
3534
3535 for (size_t i = 0; i < chunks_.size(); i++)
3536 if (chunks_[i] != other.chunks_[i]) {
3537 cover("kernel.rtlil.sigspec.comp_lt.hash_collision");
3538 return chunks_[i] < other.chunks_[i];
3539 }
3540
3541 cover("kernel.rtlil.sigspec.comp_lt.equal");
3542 return false;
3543 }
3544
3545 bool RTLIL::SigSpec::operator ==(const RTLIL::SigSpec &other) const
3546 {
3547 cover("kernel.rtlil.sigspec.comp_eq");
3548
3549 if (this == &other)
3550 return true;
3551
3552 if (width_ != other.width_)
3553 return false;
3554
3555 pack();
3556 other.pack();
3557
3558 if (chunks_.size() != other.chunks_.size())
3559 return false;
3560
3561 updhash();
3562 other.updhash();
3563
3564 if (hash_ != other.hash_)
3565 return false;
3566
3567 for (size_t i = 0; i < chunks_.size(); i++)
3568 if (chunks_[i] != other.chunks_[i]) {
3569 cover("kernel.rtlil.sigspec.comp_eq.hash_collision");
3570 return false;
3571 }
3572
3573 cover("kernel.rtlil.sigspec.comp_eq.equal");
3574 return true;
3575 }
3576
3577 bool RTLIL::SigSpec::is_wire() const
3578 {
3579 cover("kernel.rtlil.sigspec.is_wire");
3580
3581 pack();
3582 return GetSize(chunks_) == 1 && chunks_[0].wire && chunks_[0].wire->width == width_;
3583 }
3584
3585 bool RTLIL::SigSpec::is_chunk() const
3586 {
3587 cover("kernel.rtlil.sigspec.is_chunk");
3588
3589 pack();
3590 return GetSize(chunks_) == 1;
3591 }
3592
3593 bool RTLIL::SigSpec::is_fully_const() const
3594 {
3595 cover("kernel.rtlil.sigspec.is_fully_const");
3596
3597 pack();
3598 for (auto it = chunks_.begin(); it != chunks_.end(); it++)
3599 if (it->width > 0 && it->wire != NULL)
3600 return false;
3601 return true;
3602 }
3603
3604 bool RTLIL::SigSpec::is_fully_zero() const
3605 {
3606 cover("kernel.rtlil.sigspec.is_fully_zero");
3607
3608 pack();
3609 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
3610 if (it->width > 0 && it->wire != NULL)
3611 return false;
3612 for (size_t i = 0; i < it->data.size(); i++)
3613 if (it->data[i] != RTLIL::State::S0)
3614 return false;
3615 }
3616 return true;
3617 }
3618
3619 bool RTLIL::SigSpec::is_fully_ones() const
3620 {
3621 cover("kernel.rtlil.sigspec.is_fully_ones");
3622
3623 pack();
3624 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
3625 if (it->width > 0 && it->wire != NULL)
3626 return false;
3627 for (size_t i = 0; i < it->data.size(); i++)
3628 if (it->data[i] != RTLIL::State::S1)
3629 return false;
3630 }
3631 return true;
3632 }
3633
3634 bool RTLIL::SigSpec::is_fully_def() const
3635 {
3636 cover("kernel.rtlil.sigspec.is_fully_def");
3637
3638 pack();
3639 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
3640 if (it->width > 0 && it->wire != NULL)
3641 return false;
3642 for (size_t i = 0; i < it->data.size(); i++)
3643 if (it->data[i] != RTLIL::State::S0 && it->data[i] != RTLIL::State::S1)
3644 return false;
3645 }
3646 return true;
3647 }
3648
3649 bool RTLIL::SigSpec::is_fully_undef() const
3650 {
3651 cover("kernel.rtlil.sigspec.is_fully_undef");
3652
3653 pack();
3654 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
3655 if (it->width > 0 && it->wire != NULL)
3656 return false;
3657 for (size_t i = 0; i < it->data.size(); i++)
3658 if (it->data[i] != RTLIL::State::Sx && it->data[i] != RTLIL::State::Sz)
3659 return false;
3660 }
3661 return true;
3662 }
3663
3664 bool RTLIL::SigSpec::has_const() const
3665 {
3666 cover("kernel.rtlil.sigspec.has_const");
3667
3668 pack();
3669 for (auto it = chunks_.begin(); it != chunks_.end(); it++)
3670 if (it->width > 0 && it->wire == NULL)
3671 return true;
3672 return false;
3673 }
3674
3675 bool RTLIL::SigSpec::has_marked_bits() const
3676 {
3677 cover("kernel.rtlil.sigspec.has_marked_bits");
3678
3679 pack();
3680 for (auto it = chunks_.begin(); it != chunks_.end(); it++)
3681 if (it->width > 0 && it->wire == NULL) {
3682 for (size_t i = 0; i < it->data.size(); i++)
3683 if (it->data[i] == RTLIL::State::Sm)
3684 return true;
3685 }
3686 return false;
3687 }
3688
3689 bool RTLIL::SigSpec::as_bool() const
3690 {
3691 cover("kernel.rtlil.sigspec.as_bool");
3692
3693 pack();
3694 log_assert(is_fully_const() && GetSize(chunks_) <= 1);
3695 if (width_)
3696 return RTLIL::Const(chunks_[0].data).as_bool();
3697 return false;
3698 }
3699
3700 int RTLIL::SigSpec::as_int(bool is_signed) const
3701 {
3702 cover("kernel.rtlil.sigspec.as_int");
3703
3704 pack();
3705 log_assert(is_fully_const() && GetSize(chunks_) <= 1);
3706 if (width_)
3707 return RTLIL::Const(chunks_[0].data).as_int(is_signed);
3708 return 0;
3709 }
3710
3711 std::string RTLIL::SigSpec::as_string() const
3712 {
3713 cover("kernel.rtlil.sigspec.as_string");
3714
3715 pack();
3716 std::string str;
3717 for (size_t i = chunks_.size(); i > 0; i--) {
3718 const RTLIL::SigChunk &chunk = chunks_[i-1];
3719 if (chunk.wire != NULL)
3720 for (int j = 0; j < chunk.width; j++)
3721 str += "?";
3722 else
3723 str += RTLIL::Const(chunk.data).as_string();
3724 }
3725 return str;
3726 }
3727
3728 RTLIL::Const RTLIL::SigSpec::as_const() const
3729 {
3730 cover("kernel.rtlil.sigspec.as_const");
3731
3732 pack();
3733 log_assert(is_fully_const() && GetSize(chunks_) <= 1);
3734 if (width_)
3735 return chunks_[0].data;
3736 return RTLIL::Const();
3737 }
3738
3739 RTLIL::Wire *RTLIL::SigSpec::as_wire() const
3740 {
3741 cover("kernel.rtlil.sigspec.as_wire");
3742
3743 pack();
3744 log_assert(is_wire());
3745 return chunks_[0].wire;
3746 }
3747
3748 RTLIL::SigChunk RTLIL::SigSpec::as_chunk() const
3749 {
3750 cover("kernel.rtlil.sigspec.as_chunk");
3751
3752 pack();
3753 log_assert(is_chunk());
3754 return chunks_[0];
3755 }
3756
3757 RTLIL::SigBit RTLIL::SigSpec::as_bit() const
3758 {
3759 cover("kernel.rtlil.sigspec.as_bit");
3760
3761 log_assert(width_ == 1);
3762 if (packed())
3763 return RTLIL::SigBit(*chunks_.begin());
3764 else
3765 return bits_[0];
3766 }
3767
3768 bool RTLIL::SigSpec::match(std::string pattern) const
3769 {
3770 cover("kernel.rtlil.sigspec.match");
3771
3772 pack();
3773 std::string str = as_string();
3774 log_assert(pattern.size() == str.size());
3775
3776 for (size_t i = 0; i < pattern.size(); i++) {
3777 if (pattern[i] == ' ')
3778 continue;
3779 if (pattern[i] == '*') {
3780 if (str[i] != 'z' && str[i] != 'x')
3781 return false;
3782 continue;
3783 }
3784 if (pattern[i] != str[i])
3785 return false;
3786 }
3787
3788 return true;
3789 }
3790
3791 std::set<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_set() const
3792 {
3793 cover("kernel.rtlil.sigspec.to_sigbit_set");
3794
3795 pack();
3796 std::set<RTLIL::SigBit> sigbits;
3797 for (auto &c : chunks_)
3798 for (int i = 0; i < c.width; i++)
3799 sigbits.insert(RTLIL::SigBit(c, i));
3800 return sigbits;
3801 }
3802
3803 pool<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_pool() const
3804 {
3805 cover("kernel.rtlil.sigspec.to_sigbit_pool");
3806
3807 pack();
3808 pool<RTLIL::SigBit> sigbits;
3809 for (auto &c : chunks_)
3810 for (int i = 0; i < c.width; i++)
3811 sigbits.insert(RTLIL::SigBit(c, i));
3812 return sigbits;
3813 }
3814
3815 std::vector<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_vector() const
3816 {
3817 cover("kernel.rtlil.sigspec.to_sigbit_vector");
3818
3819 unpack();
3820 return bits_;
3821 }
3822
3823 std::map<RTLIL::SigBit, RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_map(const RTLIL::SigSpec &other) const
3824 {
3825 cover("kernel.rtlil.sigspec.to_sigbit_map");
3826
3827 unpack();
3828 other.unpack();
3829
3830 log_assert(width_ == other.width_);
3831
3832 std::map<RTLIL::SigBit, RTLIL::SigBit> new_map;
3833 for (int i = 0; i < width_; i++)
3834 new_map[bits_[i]] = other.bits_[i];
3835
3836 return new_map;
3837 }
3838
3839 dict<RTLIL::SigBit, RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_dict(const RTLIL::SigSpec &other) const
3840 {
3841 cover("kernel.rtlil.sigspec.to_sigbit_dict");
3842
3843 unpack();
3844 other.unpack();
3845
3846 log_assert(width_ == other.width_);
3847
3848 dict<RTLIL::SigBit, RTLIL::SigBit> new_map;
3849 for (int i = 0; i < width_; i++)
3850 new_map[bits_[i]] = other.bits_[i];
3851
3852 return new_map;
3853 }
3854
3855 static void sigspec_parse_split(std::vector<std::string> &tokens, const std::string &text, char sep)
3856 {
3857 size_t start = 0, end = 0;
3858 while ((end = text.find(sep, start)) != std::string::npos) {
3859 tokens.push_back(text.substr(start, end - start));
3860 start = end + 1;
3861 }
3862 tokens.push_back(text.substr(start));
3863 }
3864
3865 static int sigspec_parse_get_dummy_line_num()
3866 {
3867 return 0;
3868 }
3869
3870 bool RTLIL::SigSpec::parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str)
3871 {
3872 cover("kernel.rtlil.sigspec.parse");
3873
3874 AST::current_filename = "input";
3875 AST::use_internal_line_num();
3876 AST::set_line_num(0);
3877
3878 std::vector<std::string> tokens;
3879 sigspec_parse_split(tokens, str, ',');
3880
3881 sig = RTLIL::SigSpec();
3882 for (int tokidx = int(tokens.size())-1; tokidx >= 0; tokidx--)
3883 {
3884 std::string netname = tokens[tokidx];
3885 std::string indices;
3886
3887 if (netname.size() == 0)
3888 continue;
3889
3890 if (('0' <= netname[0] && netname[0] <= '9') || netname[0] == '\'') {
3891 cover("kernel.rtlil.sigspec.parse.const");
3892 AST::get_line_num = sigspec_parse_get_dummy_line_num;
3893 AST::AstNode *ast = VERILOG_FRONTEND::const2ast(netname);
3894 if (ast == NULL)
3895 return false;
3896 sig.append(RTLIL::Const(ast->bits));
3897 delete ast;
3898 continue;
3899 }
3900
3901 if (module == NULL)
3902 return false;
3903
3904 cover("kernel.rtlil.sigspec.parse.net");
3905
3906 if (netname[0] != '$' && netname[0] != '\\')
3907 netname = "\\" + netname;
3908
3909 if (module->wires_.count(netname) == 0) {
3910 size_t indices_pos = netname.size()-1;
3911 if (indices_pos > 2 && netname[indices_pos] == ']')
3912 {
3913 indices_pos--;
3914 while (indices_pos > 0 && ('0' <= netname[indices_pos] && netname[indices_pos] <= '9')) indices_pos--;
3915 if (indices_pos > 0 && netname[indices_pos] == ':') {
3916 indices_pos--;
3917 while (indices_pos > 0 && ('0' <= netname[indices_pos] && netname[indices_pos] <= '9')) indices_pos--;
3918 }
3919 if (indices_pos > 0 && netname[indices_pos] == '[') {
3920 indices = netname.substr(indices_pos);
3921 netname = netname.substr(0, indices_pos);
3922 }
3923 }
3924 }
3925
3926 if (module->wires_.count(netname) == 0)
3927 return false;
3928
3929 RTLIL::Wire *wire = module->wires_.at(netname);
3930 if (!indices.empty()) {
3931 std::vector<std::string> index_tokens;
3932 sigspec_parse_split(index_tokens, indices.substr(1, indices.size()-2), ':');
3933 if (index_tokens.size() == 1) {
3934 cover("kernel.rtlil.sigspec.parse.bit_sel");
3935 int a = atoi(index_tokens.at(0).c_str());
3936 if (a < 0 || a >= wire->width)
3937 return false;
3938 sig.append(RTLIL::SigSpec(wire, a));
3939 } else {
3940 cover("kernel.rtlil.sigspec.parse.part_sel");
3941 int a = atoi(index_tokens.at(0).c_str());
3942 int b = atoi(index_tokens.at(1).c_str());
3943 if (a > b) {
3944 int tmp = a;
3945 a = b, b = tmp;
3946 }
3947 if (a < 0 || a >= wire->width)
3948 return false;
3949 if (b < 0 || b >= wire->width)
3950 return false;
3951 sig.append(RTLIL::SigSpec(wire, a, b-a+1));
3952 }
3953 } else
3954 sig.append(wire);
3955 }
3956
3957 return true;
3958 }
3959
3960 bool RTLIL::SigSpec::parse_sel(RTLIL::SigSpec &sig, RTLIL::Design *design, RTLIL::Module *module, std::string str)
3961 {
3962 if (str.empty() || str[0] != '@')
3963 return parse(sig, module, str);
3964
3965 cover("kernel.rtlil.sigspec.parse.sel");
3966
3967 str = RTLIL::escape_id(str.substr(1));
3968 if (design->selection_vars.count(str) == 0)
3969 return false;
3970
3971 sig = RTLIL::SigSpec();
3972 RTLIL::Selection &sel = design->selection_vars.at(str);
3973 for (auto &it : module->wires_)
3974 if (sel.selected_member(module->name, it.first))
3975 sig.append(it.second);
3976
3977 return true;
3978 }
3979
3980 bool RTLIL::SigSpec::parse_rhs(const RTLIL::SigSpec &lhs, RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str)
3981 {
3982 if (str == "0") {
3983 cover("kernel.rtlil.sigspec.parse.rhs_zeros");
3984 sig = RTLIL::SigSpec(RTLIL::State::S0, lhs.width_);
3985 return true;
3986 }
3987
3988 if (str == "~0") {
3989 cover("kernel.rtlil.sigspec.parse.rhs_ones");
3990 sig = RTLIL::SigSpec(RTLIL::State::S1, lhs.width_);
3991 return true;
3992 }
3993
3994 if (lhs.chunks_.size() == 1) {
3995 char *p = (char*)str.c_str(), *endptr;
3996 long int val = strtol(p, &endptr, 10);
3997 if (endptr && endptr != p && *endptr == 0) {
3998 sig = RTLIL::SigSpec(val, lhs.width_);
3999 cover("kernel.rtlil.sigspec.parse.rhs_dec");
4000 return true;
4001 }
4002 }
4003
4004 return parse(sig, module, str);
4005 }
4006
4007 RTLIL::CaseRule::~CaseRule()
4008 {
4009 for (auto it = switches.begin(); it != switches.end(); it++)
4010 delete *it;
4011 }
4012
4013 bool RTLIL::CaseRule::empty() const
4014 {
4015 return actions.empty() && switches.empty();
4016 }
4017
4018 RTLIL::CaseRule *RTLIL::CaseRule::clone() const
4019 {
4020 RTLIL::CaseRule *new_caserule = new RTLIL::CaseRule;
4021 new_caserule->compare = compare;
4022 new_caserule->actions = actions;
4023 for (auto &it : switches)
4024 new_caserule->switches.push_back(it->clone());
4025 return new_caserule;
4026 }
4027
4028 RTLIL::SwitchRule::~SwitchRule()
4029 {
4030 for (auto it = cases.begin(); it != cases.end(); it++)
4031 delete *it;
4032 }
4033
4034 bool RTLIL::SwitchRule::empty() const
4035 {
4036 return cases.empty();
4037 }
4038
4039 RTLIL::SwitchRule *RTLIL::SwitchRule::clone() const
4040 {
4041 RTLIL::SwitchRule *new_switchrule = new RTLIL::SwitchRule;
4042 new_switchrule->signal = signal;
4043 new_switchrule->attributes = attributes;
4044 for (auto &it : cases)
4045 new_switchrule->cases.push_back(it->clone());
4046 return new_switchrule;
4047
4048 }
4049
4050 RTLIL::SyncRule *RTLIL::SyncRule::clone() const
4051 {
4052 RTLIL::SyncRule *new_syncrule = new RTLIL::SyncRule;
4053 new_syncrule->type = type;
4054 new_syncrule->signal = signal;
4055 new_syncrule->actions = actions;
4056 return new_syncrule;
4057 }
4058
4059 RTLIL::Process::~Process()
4060 {
4061 for (auto it = syncs.begin(); it != syncs.end(); it++)
4062 delete *it;
4063 }
4064
4065 RTLIL::Process *RTLIL::Process::clone() const
4066 {
4067 RTLIL::Process *new_proc = new RTLIL::Process;
4068
4069 new_proc->name = name;
4070 new_proc->attributes = attributes;
4071
4072 RTLIL::CaseRule *rc_ptr = root_case.clone();
4073 new_proc->root_case = *rc_ptr;
4074 rc_ptr->switches.clear();
4075 delete rc_ptr;
4076
4077 for (auto &it : syncs)
4078 new_proc->syncs.push_back(it->clone());
4079
4080 return new_proc;
4081 }
4082
4083 #ifdef WITH_PYTHON
4084 RTLIL::Memory::~Memory()
4085 {
4086 RTLIL::Memory::get_all_memorys()->erase(hashidx_);
4087 }
4088 static std::map<unsigned int, RTLIL::Memory*> all_memorys;
4089 std::map<unsigned int, RTLIL::Memory*> *RTLIL::Memory::get_all_memorys(void)
4090 {
4091 return &all_memorys;
4092 }
4093 #endif
4094 YOSYS_NAMESPACE_END