2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include "kernel/yosys.h"
21 #include "kernel/macc.h"
22 #include "kernel/celltypes.h"
23 #include "frontends/verilog/verilog_frontend.h"
24 #include "frontends/verilog/preproc.h"
25 #include "backends/rtlil/rtlil_backend.h"
32 RTLIL::IdString::destruct_guard_t
RTLIL::IdString::destruct_guard
;
33 std::vector
<char*> RTLIL::IdString::global_id_storage_
;
34 dict
<char*, int, hash_cstr_ops
> RTLIL::IdString::global_id_index_
;
35 #ifndef YOSYS_NO_IDS_REFCNT
36 std::vector
<int> RTLIL::IdString::global_refcount_storage_
;
37 std::vector
<int> RTLIL::IdString::global_free_idx_list_
;
39 #ifdef YOSYS_USE_STICKY_IDS
40 int RTLIL::IdString::last_created_idx_
[8];
41 int RTLIL::IdString::last_created_idx_ptr_
;
44 #define X(_id) IdString RTLIL::ID::_id;
45 #include "kernel/constids.inc"
48 dict
<std::string
, std::string
> RTLIL::constpad
;
50 const pool
<IdString
> &RTLIL::builtin_ff_cell_types() {
51 static const pool
<IdString
> res
= {
187 RTLIL::Const::Const()
189 flags
= RTLIL::CONST_FLAG_NONE
;
192 RTLIL::Const::Const(std::string str
)
194 flags
= RTLIL::CONST_FLAG_STRING
;
195 for (int i
= str
.size()-1; i
>= 0; i
--) {
196 unsigned char ch
= str
[i
];
197 for (int j
= 0; j
< 8; j
++) {
198 bits
.push_back((ch
& 1) != 0 ? State::S1
: State::S0
);
204 RTLIL::Const::Const(int val
, int width
)
206 flags
= RTLIL::CONST_FLAG_NONE
;
207 for (int i
= 0; i
< width
; i
++) {
208 bits
.push_back((val
& 1) != 0 ? State::S1
: State::S0
);
213 RTLIL::Const::Const(RTLIL::State bit
, int width
)
215 flags
= RTLIL::CONST_FLAG_NONE
;
216 for (int i
= 0; i
< width
; i
++)
220 RTLIL::Const::Const(const std::vector
<bool> &bits
)
222 flags
= RTLIL::CONST_FLAG_NONE
;
223 for (const auto &b
: bits
)
224 this->bits
.emplace_back(b
? State::S1
: State::S0
);
227 RTLIL::Const::Const(const RTLIL::Const
&c
)
230 for (const auto &b
: c
.bits
)
231 this->bits
.push_back(b
);
234 bool RTLIL::Const::operator <(const RTLIL::Const
&other
) const
236 if (bits
.size() != other
.bits
.size())
237 return bits
.size() < other
.bits
.size();
238 for (size_t i
= 0; i
< bits
.size(); i
++)
239 if (bits
[i
] != other
.bits
[i
])
240 return bits
[i
] < other
.bits
[i
];
244 bool RTLIL::Const::operator ==(const RTLIL::Const
&other
) const
246 return bits
== other
.bits
;
249 bool RTLIL::Const::operator !=(const RTLIL::Const
&other
) const
251 return bits
!= other
.bits
;
254 bool RTLIL::Const::as_bool() const
256 for (size_t i
= 0; i
< bits
.size(); i
++)
257 if (bits
[i
] == State::S1
)
262 int RTLIL::Const::as_int(bool is_signed
) const
265 for (size_t i
= 0; i
< bits
.size() && i
< 32; i
++)
266 if (bits
[i
] == State::S1
)
268 if (is_signed
&& bits
.back() == State::S1
)
269 for (size_t i
= bits
.size(); i
< 32; i
++)
274 std::string
RTLIL::Const::as_string() const
277 ret
.reserve(bits
.size());
278 for (size_t i
= bits
.size(); i
> 0; i
--)
280 case S0
: ret
+= "0"; break;
281 case S1
: ret
+= "1"; break;
282 case Sx
: ret
+= "x"; break;
283 case Sz
: ret
+= "z"; break;
284 case Sa
: ret
+= "-"; break;
285 case Sm
: ret
+= "m"; break;
290 RTLIL::Const
RTLIL::Const::from_string(const std::string
&str
)
293 c
.bits
.reserve(str
.size());
294 for (auto it
= str
.rbegin(); it
!= str
.rend(); it
++)
296 case '0': c
.bits
.push_back(State::S0
); break;
297 case '1': c
.bits
.push_back(State::S1
); break;
298 case 'x': c
.bits
.push_back(State::Sx
); break;
299 case 'z': c
.bits
.push_back(State::Sz
); break;
300 case 'm': c
.bits
.push_back(State::Sm
); break;
301 default: c
.bits
.push_back(State::Sa
);
306 std::string
RTLIL::Const::decode_string() const
309 string
.reserve(GetSize(bits
)/8);
310 for (int i
= 0; i
< GetSize(bits
); i
+= 8) {
312 for (int j
= 0; j
< 8 && i
+ j
< int (bits
.size()); j
++)
313 if (bits
[i
+ j
] == RTLIL::State::S1
)
318 std::reverse(string
.begin(), string
.end());
322 bool RTLIL::Const::is_fully_zero() const
324 cover("kernel.rtlil.const.is_fully_zero");
326 for (const auto &bit
: bits
)
327 if (bit
!= RTLIL::State::S0
)
333 bool RTLIL::Const::is_fully_ones() const
335 cover("kernel.rtlil.const.is_fully_ones");
337 for (const auto &bit
: bits
)
338 if (bit
!= RTLIL::State::S1
)
344 bool RTLIL::Const::is_fully_def() const
346 cover("kernel.rtlil.const.is_fully_def");
348 for (const auto &bit
: bits
)
349 if (bit
!= RTLIL::State::S0
&& bit
!= RTLIL::State::S1
)
355 bool RTLIL::Const::is_fully_undef() const
357 cover("kernel.rtlil.const.is_fully_undef");
359 for (const auto &bit
: bits
)
360 if (bit
!= RTLIL::State::Sx
&& bit
!= RTLIL::State::Sz
)
366 bool RTLIL::Const::is_onehot(int *pos
) const
368 cover("kernel.rtlil.const.is_onehot");
371 for (int i
= 0; i
< GetSize(*this); i
++) {
373 if (bit
!= RTLIL::State::S0
&& bit
!= RTLIL::State::S1
)
375 if (bit
== RTLIL::State::S1
) {
386 bool RTLIL::AttrObject::has_attribute(RTLIL::IdString id
) const
388 return attributes
.count(id
);
391 void RTLIL::AttrObject::set_bool_attribute(RTLIL::IdString id
, bool value
)
394 attributes
[id
] = RTLIL::Const(1);
396 attributes
.erase(id
);
399 bool RTLIL::AttrObject::get_bool_attribute(RTLIL::IdString id
) const
401 const auto it
= attributes
.find(id
);
402 if (it
== attributes
.end())
404 return it
->second
.as_bool();
407 void RTLIL::AttrObject::set_string_attribute(RTLIL::IdString id
, string value
)
410 attributes
.erase(id
);
412 attributes
[id
] = value
;
415 string
RTLIL::AttrObject::get_string_attribute(RTLIL::IdString id
) const
418 const auto it
= attributes
.find(id
);
419 if (it
!= attributes
.end())
420 value
= it
->second
.decode_string();
424 void RTLIL::AttrObject::set_strpool_attribute(RTLIL::IdString id
, const pool
<string
> &data
)
427 for (const auto &s
: data
) {
428 if (!attrval
.empty())
432 set_string_attribute(id
, attrval
);
435 void RTLIL::AttrObject::add_strpool_attribute(RTLIL::IdString id
, const pool
<string
> &data
)
437 pool
<string
> union_data
= get_strpool_attribute(id
);
438 union_data
.insert(data
.begin(), data
.end());
439 if (!union_data
.empty())
440 set_strpool_attribute(id
, union_data
);
443 pool
<string
> RTLIL::AttrObject::get_strpool_attribute(RTLIL::IdString id
) const
446 if (attributes
.count(id
) != 0)
447 for (auto s
: split_tokens(get_string_attribute(id
), "|"))
452 void RTLIL::AttrObject::set_hdlname_attribute(const vector
<string
> &hierarchy
)
455 for (const auto &ident
: hierarchy
) {
456 if (!attrval
.empty())
460 set_string_attribute(ID::hdlname
, attrval
);
463 vector
<string
> RTLIL::AttrObject::get_hdlname_attribute() const
465 return split_tokens(get_string_attribute(ID::hdlname
), " ");
468 bool RTLIL::Selection::selected_module(RTLIL::IdString mod_name
) const
472 if (selected_modules
.count(mod_name
) > 0)
474 if (selected_members
.count(mod_name
) > 0)
479 bool RTLIL::Selection::selected_whole_module(RTLIL::IdString mod_name
) const
483 if (selected_modules
.count(mod_name
) > 0)
488 bool RTLIL::Selection::selected_member(RTLIL::IdString mod_name
, RTLIL::IdString memb_name
) const
492 if (selected_modules
.count(mod_name
) > 0)
494 if (selected_members
.count(mod_name
) > 0)
495 if (selected_members
.at(mod_name
).count(memb_name
) > 0)
500 void RTLIL::Selection::optimize(RTLIL::Design
*design
)
502 if (full_selection
) {
503 selected_modules
.clear();
504 selected_members
.clear();
508 std::vector
<RTLIL::IdString
> del_list
, add_list
;
511 for (auto mod_name
: selected_modules
) {
512 if (design
->modules_
.count(mod_name
) == 0)
513 del_list
.push_back(mod_name
);
514 selected_members
.erase(mod_name
);
516 for (auto mod_name
: del_list
)
517 selected_modules
.erase(mod_name
);
520 for (auto &it
: selected_members
)
521 if (design
->modules_
.count(it
.first
) == 0)
522 del_list
.push_back(it
.first
);
523 for (auto mod_name
: del_list
)
524 selected_members
.erase(mod_name
);
526 for (auto &it
: selected_members
) {
528 for (auto memb_name
: it
.second
)
529 if (design
->modules_
[it
.first
]->count_id(memb_name
) == 0)
530 del_list
.push_back(memb_name
);
531 for (auto memb_name
: del_list
)
532 it
.second
.erase(memb_name
);
537 for (auto &it
: selected_members
)
538 if (it
.second
.size() == 0)
539 del_list
.push_back(it
.first
);
540 else if (it
.second
.size() == design
->modules_
[it
.first
]->wires_
.size() + design
->modules_
[it
.first
]->memories
.size() +
541 design
->modules_
[it
.first
]->cells_
.size() + design
->modules_
[it
.first
]->processes
.size())
542 add_list
.push_back(it
.first
);
543 for (auto mod_name
: del_list
)
544 selected_members
.erase(mod_name
);
545 for (auto mod_name
: add_list
) {
546 selected_members
.erase(mod_name
);
547 selected_modules
.insert(mod_name
);
550 if (selected_modules
.size() == design
->modules_
.size()) {
551 full_selection
= true;
552 selected_modules
.clear();
553 selected_members
.clear();
557 RTLIL::Design::Design()
558 : verilog_defines (new define_map_t
)
560 static unsigned int hashidx_count
= 123456789;
561 hashidx_count
= mkhash_xorshift(hashidx_count
);
562 hashidx_
= hashidx_count
;
564 refcount_modules_
= 0;
565 selection_stack
.push_back(RTLIL::Selection());
568 RTLIL::Design::get_all_designs()->insert(std::pair
<unsigned int, RTLIL::Design
*>(hashidx_
, this));
572 RTLIL::Design::~Design()
574 for (auto &pr
: modules_
)
576 for (auto n
: verilog_packages
)
578 for (auto n
: verilog_globals
)
581 RTLIL::Design::get_all_designs()->erase(hashidx_
);
586 static std::map
<unsigned int, RTLIL::Design
*> all_designs
;
587 std::map
<unsigned int, RTLIL::Design
*> *RTLIL::Design::get_all_designs(void)
593 RTLIL::ObjRange
<RTLIL::Module
*> RTLIL::Design::modules()
595 return RTLIL::ObjRange
<RTLIL::Module
*>(&modules_
, &refcount_modules_
);
598 RTLIL::Module
*RTLIL::Design::module(RTLIL::IdString name
)
600 return modules_
.count(name
) ? modules_
.at(name
) : NULL
;
603 const RTLIL::Module
*RTLIL::Design::module(RTLIL::IdString name
) const
605 return modules_
.count(name
) ? modules_
.at(name
) : NULL
;
608 RTLIL::Module
*RTLIL::Design::top_module()
610 RTLIL::Module
*module
= nullptr;
611 int module_count
= 0;
613 for (auto mod
: selected_modules()) {
614 if (mod
->get_bool_attribute(ID::top
))
620 return module_count
== 1 ? module
: nullptr;
623 void RTLIL::Design::add(RTLIL::Module
*module
)
625 log_assert(modules_
.count(module
->name
) == 0);
626 log_assert(refcount_modules_
== 0);
627 modules_
[module
->name
] = module
;
628 module
->design
= this;
630 for (auto mon
: monitors
)
631 mon
->notify_module_add(module
);
634 log("#X# New Module: %s\n", log_id(module
));
635 log_backtrace("-X- ", yosys_xtrace
-1);
639 RTLIL::Module
*RTLIL::Design::addModule(RTLIL::IdString name
)
641 if (modules_
.count(name
) != 0)
642 log_error("Attempted to add new module named '%s', but a module by that name already exists\n", name
.c_str());
643 log_assert(refcount_modules_
== 0);
645 RTLIL::Module
*module
= new RTLIL::Module
;
646 modules_
[name
] = module
;
647 module
->design
= this;
650 for (auto mon
: monitors
)
651 mon
->notify_module_add(module
);
654 log("#X# New Module: %s\n", log_id(module
));
655 log_backtrace("-X- ", yosys_xtrace
-1);
661 void RTLIL::Design::scratchpad_unset(const std::string
&varname
)
663 scratchpad
.erase(varname
);
666 void RTLIL::Design::scratchpad_set_int(const std::string
&varname
, int value
)
668 scratchpad
[varname
] = stringf("%d", value
);
671 void RTLIL::Design::scratchpad_set_bool(const std::string
&varname
, bool value
)
673 scratchpad
[varname
] = value
? "true" : "false";
676 void RTLIL::Design::scratchpad_set_string(const std::string
&varname
, std::string value
)
678 scratchpad
[varname
] = std::move(value
);
681 int RTLIL::Design::scratchpad_get_int(const std::string
&varname
, int default_value
) const
683 auto it
= scratchpad
.find(varname
);
684 if (it
== scratchpad
.end())
685 return default_value
;
687 const std::string
&str
= it
->second
;
689 if (str
== "0" || str
== "false")
692 if (str
== "1" || str
== "true")
695 char *endptr
= nullptr;
696 long int parsed_value
= strtol(str
.c_str(), &endptr
, 10);
697 return *endptr
? default_value
: parsed_value
;
700 bool RTLIL::Design::scratchpad_get_bool(const std::string
&varname
, bool default_value
) const
702 auto it
= scratchpad
.find(varname
);
703 if (it
== scratchpad
.end())
704 return default_value
;
706 const std::string
&str
= it
->second
;
708 if (str
== "0" || str
== "false")
711 if (str
== "1" || str
== "true")
714 return default_value
;
717 std::string
RTLIL::Design::scratchpad_get_string(const std::string
&varname
, const std::string
&default_value
) const
719 auto it
= scratchpad
.find(varname
);
720 if (it
== scratchpad
.end())
721 return default_value
;
726 void RTLIL::Design::remove(RTLIL::Module
*module
)
728 for (auto mon
: monitors
)
729 mon
->notify_module_del(module
);
732 log("#X# Remove Module: %s\n", log_id(module
));
733 log_backtrace("-X- ", yosys_xtrace
-1);
736 log_assert(modules_
.at(module
->name
) == module
);
737 log_assert(refcount_modules_
== 0);
738 modules_
.erase(module
->name
);
742 void RTLIL::Design::rename(RTLIL::Module
*module
, RTLIL::IdString new_name
)
744 modules_
.erase(module
->name
);
745 module
->name
= new_name
;
749 void RTLIL::Design::sort()
752 modules_
.sort(sort_by_id_str());
753 for (auto &it
: modules_
)
757 void RTLIL::Design::check()
760 for (auto &it
: modules_
) {
761 log_assert(this == it
.second
->design
);
762 log_assert(it
.first
== it
.second
->name
);
763 log_assert(!it
.first
.empty());
769 void RTLIL::Design::optimize()
771 for (auto &it
: modules_
)
772 it
.second
->optimize();
773 for (auto &it
: selection_stack
)
775 for (auto &it
: selection_vars
)
776 it
.second
.optimize(this);
779 bool RTLIL::Design::selected_module(RTLIL::IdString mod_name
) const
781 if (!selected_active_module
.empty() && mod_name
!= selected_active_module
)
783 if (selection_stack
.size() == 0)
785 return selection_stack
.back().selected_module(mod_name
);
788 bool RTLIL::Design::selected_whole_module(RTLIL::IdString mod_name
) const
790 if (!selected_active_module
.empty() && mod_name
!= selected_active_module
)
792 if (selection_stack
.size() == 0)
794 return selection_stack
.back().selected_whole_module(mod_name
);
797 bool RTLIL::Design::selected_member(RTLIL::IdString mod_name
, RTLIL::IdString memb_name
) const
799 if (!selected_active_module
.empty() && mod_name
!= selected_active_module
)
801 if (selection_stack
.size() == 0)
803 return selection_stack
.back().selected_member(mod_name
, memb_name
);
806 bool RTLIL::Design::selected_module(RTLIL::Module
*mod
) const
808 return selected_module(mod
->name
);
811 bool RTLIL::Design::selected_whole_module(RTLIL::Module
*mod
) const
813 return selected_whole_module(mod
->name
);
816 std::vector
<RTLIL::Module
*> RTLIL::Design::selected_modules() const
818 std::vector
<RTLIL::Module
*> result
;
819 result
.reserve(modules_
.size());
820 for (auto &it
: modules_
)
821 if (selected_module(it
.first
) && !it
.second
->get_blackbox_attribute())
822 result
.push_back(it
.second
);
826 std::vector
<RTLIL::Module
*> RTLIL::Design::selected_whole_modules() const
828 std::vector
<RTLIL::Module
*> result
;
829 result
.reserve(modules_
.size());
830 for (auto &it
: modules_
)
831 if (selected_whole_module(it
.first
) && !it
.second
->get_blackbox_attribute())
832 result
.push_back(it
.second
);
836 std::vector
<RTLIL::Module
*> RTLIL::Design::selected_whole_modules_warn(bool include_wb
) const
838 std::vector
<RTLIL::Module
*> result
;
839 result
.reserve(modules_
.size());
840 for (auto &it
: modules_
)
841 if (it
.second
->get_blackbox_attribute(include_wb
))
843 else if (selected_whole_module(it
.first
))
844 result
.push_back(it
.second
);
845 else if (selected_module(it
.first
))
846 log_warning("Ignoring partially selected module %s.\n", log_id(it
.first
));
850 RTLIL::Module::Module()
852 static unsigned int hashidx_count
= 123456789;
853 hashidx_count
= mkhash_xorshift(hashidx_count
);
854 hashidx_
= hashidx_count
;
861 RTLIL::Module::get_all_modules()->insert(std::pair
<unsigned int, RTLIL::Module
*>(hashidx_
, this));
865 RTLIL::Module::~Module()
867 for (auto &pr
: wires_
)
869 for (auto &pr
: memories
)
871 for (auto &pr
: cells_
)
873 for (auto &pr
: processes
)
876 RTLIL::Module::get_all_modules()->erase(hashidx_
);
881 static std::map
<unsigned int, RTLIL::Module
*> all_modules
;
882 std::map
<unsigned int, RTLIL::Module
*> *RTLIL::Module::get_all_modules(void)
888 void RTLIL::Module::makeblackbox()
890 pool
<RTLIL::Wire
*> delwires
;
892 for (auto it
= wires_
.begin(); it
!= wires_
.end(); ++it
)
893 if (!it
->second
->port_input
&& !it
->second
->port_output
)
894 delwires
.insert(it
->second
);
896 for (auto it
= memories
.begin(); it
!= memories
.end(); ++it
)
900 for (auto it
= cells_
.begin(); it
!= cells_
.end(); ++it
)
904 for (auto it
= processes
.begin(); it
!= processes
.end(); ++it
)
908 connections_
.clear();
911 set_bool_attribute(ID::blackbox
);
914 void RTLIL::Module::reprocess_module(RTLIL::Design
*, const dict
<RTLIL::IdString
, RTLIL::Module
*> &)
916 log_error("Cannot reprocess_module module `%s' !\n", id2cstr(name
));
919 RTLIL::IdString
RTLIL::Module::derive(RTLIL::Design
*, const dict
<RTLIL::IdString
, RTLIL::Const
> &, bool mayfail
)
922 return RTLIL::IdString();
923 log_error("Module `%s' is used with parameters but is not parametric!\n", id2cstr(name
));
927 RTLIL::IdString
RTLIL::Module::derive(RTLIL::Design
*, const dict
<RTLIL::IdString
, RTLIL::Const
> &, const dict
<RTLIL::IdString
, RTLIL::Module
*> &, const dict
<RTLIL::IdString
, RTLIL::IdString
> &, bool mayfail
)
930 return RTLIL::IdString();
931 log_error("Module `%s' is used with parameters but is not parametric!\n", id2cstr(name
));
934 size_t RTLIL::Module::count_id(RTLIL::IdString id
)
936 return wires_
.count(id
) + memories
.count(id
) + cells_
.count(id
) + processes
.count(id
);
941 struct InternalCellChecker
943 RTLIL::Module
*module
;
945 pool
<RTLIL::IdString
> expected_params
, expected_ports
;
947 InternalCellChecker(RTLIL::Module
*module
, RTLIL::Cell
*cell
) : module(module
), cell(cell
) { }
949 void error(int linenr
)
951 std::stringstream buf
;
952 RTLIL_BACKEND::dump_cell(buf
, " ", cell
);
954 log_error("Found error in internal cell %s%s%s (%s) at %s:%d:\n%s",
955 module
? module
->name
.c_str() : "", module
? "." : "",
956 cell
->name
.c_str(), cell
->type
.c_str(), __FILE__
, linenr
, buf
.str().c_str());
959 int param(RTLIL::IdString name
)
961 auto it
= cell
->parameters
.find(name
);
962 if (it
== cell
->parameters
.end())
964 expected_params
.insert(name
);
965 return it
->second
.as_int();
968 int param_bool(RTLIL::IdString name
)
971 if (GetSize(cell
->parameters
.at(name
)) > 32)
973 if (v
!= 0 && v
!= 1)
978 int param_bool(RTLIL::IdString name
, bool expected
)
980 int v
= param_bool(name
);
986 void param_bits(RTLIL::IdString name
, int width
)
989 if (GetSize(cell
->parameters
.at(name
).bits
) != width
)
993 void port(RTLIL::IdString name
, int width
)
995 auto it
= cell
->connections_
.find(name
);
996 if (it
== cell
->connections_
.end())
998 if (GetSize(it
->second
) != width
)
1000 expected_ports
.insert(name
);
1003 void check_expected(bool check_matched_sign
= false)
1005 for (auto ¶
: cell
->parameters
)
1006 if (expected_params
.count(para
.first
) == 0)
1008 for (auto &conn
: cell
->connections())
1009 if (expected_ports
.count(conn
.first
) == 0)
1012 if (check_matched_sign
) {
1013 log_assert(expected_params
.count(ID::A_SIGNED
) != 0 && expected_params
.count(ID::B_SIGNED
) != 0);
1014 bool a_is_signed
= cell
->parameters
.at(ID::A_SIGNED
).as_bool();
1015 bool b_is_signed
= cell
->parameters
.at(ID::B_SIGNED
).as_bool();
1016 if (a_is_signed
!= b_is_signed
)
1023 if (!cell
->type
.begins_with("$") || cell
->type
.begins_with("$__") || cell
->type
.begins_with("$paramod") || cell
->type
.begins_with("$fmcombine") ||
1024 cell
->type
.begins_with("$verific$") || cell
->type
.begins_with("$array:") || cell
->type
.begins_with("$extern:"))
1027 if (cell
->type
.in(ID($
not), ID($pos
), ID($neg
))) {
1028 param_bool(ID::A_SIGNED
);
1029 port(ID::A
, param(ID::A_WIDTH
));
1030 port(ID::Y
, param(ID::Y_WIDTH
));
1035 if (cell
->type
.in(ID($
and), ID($
or), ID($
xor), ID($xnor
))) {
1036 param_bool(ID::A_SIGNED
);
1037 param_bool(ID::B_SIGNED
);
1038 port(ID::A
, param(ID::A_WIDTH
));
1039 port(ID::B
, param(ID::B_WIDTH
));
1040 port(ID::Y
, param(ID::Y_WIDTH
));
1041 check_expected(true);
1045 if (cell
->type
.in(ID($reduce_and
), ID($reduce_or
), ID($reduce_xor
), ID($reduce_xnor
), ID($reduce_bool
))) {
1046 param_bool(ID::A_SIGNED
);
1047 port(ID::A
, param(ID::A_WIDTH
));
1048 port(ID::Y
, param(ID::Y_WIDTH
));
1053 if (cell
->type
.in(ID($shl
), ID($shr
), ID($sshl
), ID($sshr
))) {
1054 param_bool(ID::A_SIGNED
);
1055 param_bool(ID::B_SIGNED
, /*expected=*/false);
1056 port(ID::A
, param(ID::A_WIDTH
));
1057 port(ID::B
, param(ID::B_WIDTH
));
1058 port(ID::Y
, param(ID::Y_WIDTH
));
1059 check_expected(/*check_matched_sign=*/false);
1063 if (cell
->type
.in(ID($shift
), ID($shiftx
))) {
1064 if (cell
->type
== ID($shiftx
)) {
1065 param_bool(ID::A_SIGNED
, /*expected=*/false);
1067 param_bool(ID::A_SIGNED
);
1069 param_bool(ID::B_SIGNED
);
1070 port(ID::A
, param(ID::A_WIDTH
));
1071 port(ID::B
, param(ID::B_WIDTH
));
1072 port(ID::Y
, param(ID::Y_WIDTH
));
1073 check_expected(/*check_matched_sign=*/false);
1077 if (cell
->type
.in(ID($lt
), ID($le
), ID($eq
), ID($ne
), ID($eqx
), ID($nex
), ID($ge
), ID($gt
))) {
1078 param_bool(ID::A_SIGNED
);
1079 param_bool(ID::B_SIGNED
);
1080 port(ID::A
, param(ID::A_WIDTH
));
1081 port(ID::B
, param(ID::B_WIDTH
));
1082 port(ID::Y
, param(ID::Y_WIDTH
));
1083 check_expected(true);
1087 if (cell
->type
.in(ID($add
), ID($sub
), ID($mul
), ID($div
), ID($mod
), ID($divfloor
), ID($modfloor
), ID($pow
))) {
1088 param_bool(ID::A_SIGNED
);
1089 param_bool(ID::B_SIGNED
);
1090 port(ID::A
, param(ID::A_WIDTH
));
1091 port(ID::B
, param(ID::B_WIDTH
));
1092 port(ID::Y
, param(ID::Y_WIDTH
));
1093 check_expected(cell
->type
!= ID($pow
));
1097 if (cell
->type
== ID($fa
)) {
1098 port(ID::A
, param(ID::WIDTH
));
1099 port(ID::B
, param(ID::WIDTH
));
1100 port(ID::C
, param(ID::WIDTH
));
1101 port(ID::X
, param(ID::WIDTH
));
1102 port(ID::Y
, param(ID::WIDTH
));
1107 if (cell
->type
== ID($lcu
)) {
1108 port(ID::P
, param(ID::WIDTH
));
1109 port(ID::G
, param(ID::WIDTH
));
1111 port(ID::CO
, param(ID::WIDTH
));
1116 if (cell
->type
== ID($alu
)) {
1117 param_bool(ID::A_SIGNED
);
1118 param_bool(ID::B_SIGNED
);
1119 port(ID::A
, param(ID::A_WIDTH
));
1120 port(ID::B
, param(ID::B_WIDTH
));
1123 port(ID::X
, param(ID::Y_WIDTH
));
1124 port(ID::Y
, param(ID::Y_WIDTH
));
1125 port(ID::CO
, param(ID::Y_WIDTH
));
1126 check_expected(true);
1130 if (cell
->type
== ID($macc
)) {
1132 param(ID::CONFIG_WIDTH
);
1133 port(ID::A
, param(ID::A_WIDTH
));
1134 port(ID::B
, param(ID::B_WIDTH
));
1135 port(ID::Y
, param(ID::Y_WIDTH
));
1137 Macc().from_cell(cell
);
1141 if (cell
->type
== ID($logic_not
)) {
1142 param_bool(ID::A_SIGNED
);
1143 port(ID::A
, param(ID::A_WIDTH
));
1144 port(ID::Y
, param(ID::Y_WIDTH
));
1149 if (cell
->type
.in(ID($logic_and
), ID($logic_or
))) {
1150 param_bool(ID::A_SIGNED
);
1151 param_bool(ID::B_SIGNED
);
1152 port(ID::A
, param(ID::A_WIDTH
));
1153 port(ID::B
, param(ID::B_WIDTH
));
1154 port(ID::Y
, param(ID::Y_WIDTH
));
1155 check_expected(/*check_matched_sign=*/false);
1159 if (cell
->type
== ID($slice
)) {
1161 port(ID::A
, param(ID::A_WIDTH
));
1162 port(ID::Y
, param(ID::Y_WIDTH
));
1163 if (param(ID::OFFSET
) + param(ID::Y_WIDTH
) > param(ID::A_WIDTH
))
1169 if (cell
->type
== ID($concat
)) {
1170 port(ID::A
, param(ID::A_WIDTH
));
1171 port(ID::B
, param(ID::B_WIDTH
));
1172 port(ID::Y
, param(ID::A_WIDTH
) + param(ID::B_WIDTH
));
1177 if (cell
->type
== ID($mux
)) {
1178 port(ID::A
, param(ID::WIDTH
));
1179 port(ID::B
, param(ID::WIDTH
));
1181 port(ID::Y
, param(ID::WIDTH
));
1186 if (cell
->type
== ID($pmux
)) {
1187 port(ID::A
, param(ID::WIDTH
));
1188 port(ID::B
, param(ID::WIDTH
) * param(ID::S_WIDTH
));
1189 port(ID::S
, param(ID::S_WIDTH
));
1190 port(ID::Y
, param(ID::WIDTH
));
1195 if (cell
->type
== ID($lut
)) {
1197 port(ID::A
, param(ID::WIDTH
));
1203 if (cell
->type
== ID($sop
)) {
1206 port(ID::A
, param(ID::WIDTH
));
1212 if (cell
->type
== ID($sr
)) {
1213 param_bool(ID::SET_POLARITY
);
1214 param_bool(ID::CLR_POLARITY
);
1215 port(ID::SET
, param(ID::WIDTH
));
1216 port(ID::CLR
, param(ID::WIDTH
));
1217 port(ID::Q
, param(ID::WIDTH
));
1222 if (cell
->type
== ID($ff
)) {
1223 port(ID::D
, param(ID::WIDTH
));
1224 port(ID::Q
, param(ID::WIDTH
));
1229 if (cell
->type
== ID($dff
)) {
1230 param_bool(ID::CLK_POLARITY
);
1232 port(ID::D
, param(ID::WIDTH
));
1233 port(ID::Q
, param(ID::WIDTH
));
1238 if (cell
->type
== ID($dffe
)) {
1239 param_bool(ID::CLK_POLARITY
);
1240 param_bool(ID::EN_POLARITY
);
1243 port(ID::D
, param(ID::WIDTH
));
1244 port(ID::Q
, param(ID::WIDTH
));
1249 if (cell
->type
== ID($dffsr
)) {
1250 param_bool(ID::CLK_POLARITY
);
1251 param_bool(ID::SET_POLARITY
);
1252 param_bool(ID::CLR_POLARITY
);
1254 port(ID::SET
, param(ID::WIDTH
));
1255 port(ID::CLR
, param(ID::WIDTH
));
1256 port(ID::D
, param(ID::WIDTH
));
1257 port(ID::Q
, param(ID::WIDTH
));
1262 if (cell
->type
== ID($dffsre
)) {
1263 param_bool(ID::CLK_POLARITY
);
1264 param_bool(ID::SET_POLARITY
);
1265 param_bool(ID::CLR_POLARITY
);
1266 param_bool(ID::EN_POLARITY
);
1269 port(ID::SET
, param(ID::WIDTH
));
1270 port(ID::CLR
, param(ID::WIDTH
));
1271 port(ID::D
, param(ID::WIDTH
));
1272 port(ID::Q
, param(ID::WIDTH
));
1277 if (cell
->type
== ID($adff
)) {
1278 param_bool(ID::CLK_POLARITY
);
1279 param_bool(ID::ARST_POLARITY
);
1280 param_bits(ID::ARST_VALUE
, param(ID::WIDTH
));
1283 port(ID::D
, param(ID::WIDTH
));
1284 port(ID::Q
, param(ID::WIDTH
));
1289 if (cell
->type
== ID($sdff
)) {
1290 param_bool(ID::CLK_POLARITY
);
1291 param_bool(ID::SRST_POLARITY
);
1292 param_bits(ID::SRST_VALUE
, param(ID::WIDTH
));
1295 port(ID::D
, param(ID::WIDTH
));
1296 port(ID::Q
, param(ID::WIDTH
));
1301 if (cell
->type
.in(ID($sdffe
), ID($sdffce
))) {
1302 param_bool(ID::CLK_POLARITY
);
1303 param_bool(ID::EN_POLARITY
);
1304 param_bool(ID::SRST_POLARITY
);
1305 param_bits(ID::SRST_VALUE
, param(ID::WIDTH
));
1309 port(ID::D
, param(ID::WIDTH
));
1310 port(ID::Q
, param(ID::WIDTH
));
1315 if (cell
->type
== ID($adffe
)) {
1316 param_bool(ID::CLK_POLARITY
);
1317 param_bool(ID::EN_POLARITY
);
1318 param_bool(ID::ARST_POLARITY
);
1319 param_bits(ID::ARST_VALUE
, param(ID::WIDTH
));
1323 port(ID::D
, param(ID::WIDTH
));
1324 port(ID::Q
, param(ID::WIDTH
));
1329 if (cell
->type
== ID($dlatch
)) {
1330 param_bool(ID::EN_POLARITY
);
1332 port(ID::D
, param(ID::WIDTH
));
1333 port(ID::Q
, param(ID::WIDTH
));
1338 if (cell
->type
== ID($adlatch
)) {
1339 param_bool(ID::EN_POLARITY
);
1340 param_bool(ID::ARST_POLARITY
);
1341 param_bits(ID::ARST_VALUE
, param(ID::WIDTH
));
1344 port(ID::D
, param(ID::WIDTH
));
1345 port(ID::Q
, param(ID::WIDTH
));
1350 if (cell
->type
== ID($dlatchsr
)) {
1351 param_bool(ID::EN_POLARITY
);
1352 param_bool(ID::SET_POLARITY
);
1353 param_bool(ID::CLR_POLARITY
);
1355 port(ID::SET
, param(ID::WIDTH
));
1356 port(ID::CLR
, param(ID::WIDTH
));
1357 port(ID::D
, param(ID::WIDTH
));
1358 port(ID::Q
, param(ID::WIDTH
));
1363 if (cell
->type
== ID($fsm
)) {
1365 param_bool(ID::CLK_POLARITY
);
1366 param_bool(ID::ARST_POLARITY
);
1367 param(ID::STATE_BITS
);
1368 param(ID::STATE_NUM
);
1369 param(ID::STATE_NUM_LOG2
);
1370 param(ID::STATE_RST
);
1371 param_bits(ID::STATE_TABLE
, param(ID::STATE_BITS
) * param(ID::STATE_NUM
));
1372 param(ID::TRANS_NUM
);
1373 param_bits(ID::TRANS_TABLE
, param(ID::TRANS_NUM
) * (2*param(ID::STATE_NUM_LOG2
) + param(ID::CTRL_IN_WIDTH
) + param(ID::CTRL_OUT_WIDTH
)));
1376 port(ID::CTRL_IN
, param(ID::CTRL_IN_WIDTH
));
1377 port(ID::CTRL_OUT
, param(ID::CTRL_OUT_WIDTH
));
1382 if (cell
->type
== ID($memrd
)) {
1384 param_bool(ID::CLK_ENABLE
);
1385 param_bool(ID::CLK_POLARITY
);
1386 param_bool(ID::TRANSPARENT
);
1389 port(ID::ADDR
, param(ID::ABITS
));
1390 port(ID::DATA
, param(ID::WIDTH
));
1395 if (cell
->type
== ID($memwr
)) {
1397 param_bool(ID::CLK_ENABLE
);
1398 param_bool(ID::CLK_POLARITY
);
1399 param(ID::PRIORITY
);
1401 port(ID::EN
, param(ID::WIDTH
));
1402 port(ID::ADDR
, param(ID::ABITS
));
1403 port(ID::DATA
, param(ID::WIDTH
));
1408 if (cell
->type
== ID($meminit
)) {
1410 param(ID::PRIORITY
);
1411 port(ID::ADDR
, param(ID::ABITS
));
1412 port(ID::DATA
, param(ID::WIDTH
) * param(ID::WORDS
));
1417 if (cell
->type
== ID($mem
)) {
1422 param_bits(ID::RD_CLK_ENABLE
, max(1, param(ID::RD_PORTS
)));
1423 param_bits(ID::RD_CLK_POLARITY
, max(1, param(ID::RD_PORTS
)));
1424 param_bits(ID::RD_TRANSPARENT
, max(1, param(ID::RD_PORTS
)));
1425 param_bits(ID::WR_CLK_ENABLE
, max(1, param(ID::WR_PORTS
)));
1426 param_bits(ID::WR_CLK_POLARITY
, max(1, param(ID::WR_PORTS
)));
1427 port(ID::RD_CLK
, param(ID::RD_PORTS
));
1428 port(ID::RD_EN
, param(ID::RD_PORTS
));
1429 port(ID::RD_ADDR
, param(ID::RD_PORTS
) * param(ID::ABITS
));
1430 port(ID::RD_DATA
, param(ID::RD_PORTS
) * param(ID::WIDTH
));
1431 port(ID::WR_CLK
, param(ID::WR_PORTS
));
1432 port(ID::WR_EN
, param(ID::WR_PORTS
) * param(ID::WIDTH
));
1433 port(ID::WR_ADDR
, param(ID::WR_PORTS
) * param(ID::ABITS
));
1434 port(ID::WR_DATA
, param(ID::WR_PORTS
) * param(ID::WIDTH
));
1439 if (cell
->type
== ID($tribuf
)) {
1440 port(ID::A
, param(ID::WIDTH
));
1441 port(ID::Y
, param(ID::WIDTH
));
1447 if (cell
->type
.in(ID($
assert), ID($assume
), ID($live
), ID($fair
), ID($cover
))) {
1454 if (cell
->type
== ID($initstate
)) {
1460 if (cell
->type
.in(ID($anyconst
), ID($anyseq
), ID($allconst
), ID($allseq
))) {
1461 port(ID::Y
, param(ID::WIDTH
));
1466 if (cell
->type
== ID($equiv
)) {
1474 if (cell
->type
.in(ID($specify2
), ID($specify3
))) {
1475 param_bool(ID::FULL
);
1476 param_bool(ID::SRC_DST_PEN
);
1477 param_bool(ID::SRC_DST_POL
);
1478 param(ID::T_RISE_MIN
);
1479 param(ID::T_RISE_TYP
);
1480 param(ID::T_RISE_MAX
);
1481 param(ID::T_FALL_MIN
);
1482 param(ID::T_FALL_TYP
);
1483 param(ID::T_FALL_MAX
);
1485 port(ID::SRC
, param(ID::SRC_WIDTH
));
1486 port(ID::DST
, param(ID::DST_WIDTH
));
1487 if (cell
->type
== ID($specify3
)) {
1488 param_bool(ID::EDGE_EN
);
1489 param_bool(ID::EDGE_POL
);
1490 param_bool(ID::DAT_DST_PEN
);
1491 param_bool(ID::DAT_DST_POL
);
1492 port(ID::DAT
, param(ID::DST_WIDTH
));
1498 if (cell
->type
== ID($specrule
)) {
1500 param_bool(ID::SRC_PEN
);
1501 param_bool(ID::SRC_POL
);
1502 param_bool(ID::DST_PEN
);
1503 param_bool(ID::DST_POL
);
1504 param(ID::T_LIMIT_MIN
);
1505 param(ID::T_LIMIT_TYP
);
1506 param(ID::T_LIMIT_MAX
);
1507 param(ID::T_LIMIT2_MIN
);
1508 param(ID::T_LIMIT2_TYP
);
1509 param(ID::T_LIMIT2_MAX
);
1510 port(ID::SRC_EN
, 1);
1511 port(ID::DST_EN
, 1);
1512 port(ID::SRC
, param(ID::SRC_WIDTH
));
1513 port(ID::DST
, param(ID::DST_WIDTH
));
1518 if (cell
->type
== ID($_BUF_
)) { port(ID::A
,1); port(ID::Y
,1); check_expected(); return; }
1519 if (cell
->type
== ID($_NOT_
)) { port(ID::A
,1); port(ID::Y
,1); check_expected(); return; }
1520 if (cell
->type
== ID($_AND_
)) { port(ID::A
,1); port(ID::B
,1); port(ID::Y
,1); check_expected(); return; }
1521 if (cell
->type
== ID($_NAND_
)) { port(ID::A
,1); port(ID::B
,1); port(ID::Y
,1); check_expected(); return; }
1522 if (cell
->type
== ID($_OR_
)) { port(ID::A
,1); port(ID::B
,1); port(ID::Y
,1); check_expected(); return; }
1523 if (cell
->type
== ID($_NOR_
)) { port(ID::A
,1); port(ID::B
,1); port(ID::Y
,1); check_expected(); return; }
1524 if (cell
->type
== ID($_XOR_
)) { port(ID::A
,1); port(ID::B
,1); port(ID::Y
,1); check_expected(); return; }
1525 if (cell
->type
== ID($_XNOR_
)) { port(ID::A
,1); port(ID::B
,1); port(ID::Y
,1); check_expected(); return; }
1526 if (cell
->type
== ID($_ANDNOT_
)) { port(ID::A
,1); port(ID::B
,1); port(ID::Y
,1); check_expected(); return; }
1527 if (cell
->type
== ID($_ORNOT_
)) { port(ID::A
,1); port(ID::B
,1); port(ID::Y
,1); check_expected(); return; }
1528 if (cell
->type
== ID($_MUX_
)) { port(ID::A
,1); port(ID::B
,1); port(ID::S
,1); port(ID::Y
,1); check_expected(); return; }
1529 if (cell
->type
== ID($_NMUX_
)) { port(ID::A
,1); port(ID::B
,1); port(ID::S
,1); port(ID::Y
,1); check_expected(); return; }
1530 if (cell
->type
== ID($_AOI3_
)) { port(ID::A
,1); port(ID::B
,1); port(ID::C
,1); port(ID::Y
,1); check_expected(); return; }
1531 if (cell
->type
== ID($_OAI3_
)) { port(ID::A
,1); port(ID::B
,1); port(ID::C
,1); port(ID::Y
,1); check_expected(); return; }
1532 if (cell
->type
== ID($_AOI4_
)) { port(ID::A
,1); port(ID::B
,1); port(ID::C
,1); port(ID::D
,1); port(ID::Y
,1); check_expected(); return; }
1533 if (cell
->type
== ID($_OAI4_
)) { port(ID::A
,1); port(ID::B
,1); port(ID::C
,1); port(ID::D
,1); port(ID::Y
,1); check_expected(); return; }
1535 if (cell
->type
== ID($_TBUF_
)) { port(ID::A
,1); port(ID::Y
,1); port(ID::E
,1); check_expected(); return; }
1537 if (cell
->type
== ID($_MUX4_
)) { port(ID::A
,1); port(ID::B
,1); port(ID::C
,1); port(ID::D
,1); port(ID::S
,1); port(ID::T
,1); port(ID::Y
,1); check_expected(); return; }
1538 if (cell
->type
== ID($_MUX8_
)) { port(ID::A
,1); port(ID::B
,1); port(ID::C
,1); port(ID::D
,1); port(ID::E
,1); port(ID::F
,1); port(ID::G
,1); port(ID::H
,1); port(ID::S
,1); port(ID::T
,1); port(ID::U
,1); port(ID::Y
,1); check_expected(); return; }
1539 if (cell
->type
== ID($_MUX16_
)) { port(ID::A
,1); port(ID::B
,1); port(ID::C
,1); port(ID::D
,1); port(ID::E
,1); port(ID::F
,1); port(ID::G
,1); port(ID::H
,1); port(ID::I
,1); port(ID::J
,1); port(ID::K
,1); port(ID::L
,1); port(ID::M
,1); port(ID::N
,1); port(ID::O
,1); port(ID::P
,1); port(ID::S
,1); port(ID::T
,1); port(ID::U
,1); port(ID::V
,1); port(ID::Y
,1); check_expected(); return; }
1541 if (cell
->type
.in(ID($_SR_NN_
), ID($_SR_NP_
), ID($_SR_PN_
), ID($_SR_PP_
)))
1542 { port(ID::S
,1); port(ID::R
,1); port(ID::Q
,1); check_expected(); return; }
1544 if (cell
->type
== ID($_FF_
)) { port(ID::D
,1); port(ID::Q
,1); check_expected(); return; }
1546 if (cell
->type
.in(ID($_DFF_N_
), ID($_DFF_P_
)))
1547 { port(ID::D
,1); port(ID::Q
,1); port(ID::C
,1); check_expected(); return; }
1549 if (cell
->type
.in(ID($_DFFE_NN_
), ID($_DFFE_NP_
), ID($_DFFE_PN_
), ID($_DFFE_PP_
)))
1550 { port(ID::D
,1); port(ID::Q
,1); port(ID::C
,1); port(ID::E
,1); check_expected(); return; }
1553 ID($_DFF_NN0_
), ID($_DFF_NN1_
), ID($_DFF_NP0_
), ID($_DFF_NP1_
),
1554 ID($_DFF_PN0_
), ID($_DFF_PN1_
), ID($_DFF_PP0_
), ID($_DFF_PP1_
)))
1555 { port(ID::D
,1); port(ID::Q
,1); port(ID::C
,1); port(ID::R
,1); check_expected(); return; }
1558 ID($_DFFE_NN0N_
), ID($_DFFE_NN0P_
), ID($_DFFE_NN1N_
), ID($_DFFE_NN1P_
),
1559 ID($_DFFE_NP0N_
), ID($_DFFE_NP0P_
), ID($_DFFE_NP1N_
), ID($_DFFE_NP1P_
),
1560 ID($_DFFE_PN0N_
), ID($_DFFE_PN0P_
), ID($_DFFE_PN1N_
), ID($_DFFE_PN1P_
),
1561 ID($_DFFE_PP0N_
), ID($_DFFE_PP0P_
), ID($_DFFE_PP1N_
), ID($_DFFE_PP1P_
)))
1562 { port(ID::D
,1); port(ID::Q
,1); port(ID::C
,1); port(ID::R
,1); port(ID::E
,1); check_expected(); return; }
1565 ID($_DFFSR_NNN_
), ID($_DFFSR_NNP_
), ID($_DFFSR_NPN_
), ID($_DFFSR_NPP_
),
1566 ID($_DFFSR_PNN_
), ID($_DFFSR_PNP_
), ID($_DFFSR_PPN_
), ID($_DFFSR_PPP_
)))
1567 { port(ID::C
,1); port(ID::S
,1); port(ID::R
,1); port(ID::D
,1); port(ID::Q
,1); check_expected(); return; }
1570 ID($_DFFSRE_NNNN_
), ID($_DFFSRE_NNNP_
), ID($_DFFSRE_NNPN_
), ID($_DFFSRE_NNPP_
),
1571 ID($_DFFSRE_NPNN_
), ID($_DFFSRE_NPNP_
), ID($_DFFSRE_NPPN_
), ID($_DFFSRE_NPPP_
),
1572 ID($_DFFSRE_PNNN_
), ID($_DFFSRE_PNNP_
), ID($_DFFSRE_PNPN_
), ID($_DFFSRE_PNPP_
),
1573 ID($_DFFSRE_PPNN_
), ID($_DFFSRE_PPNP_
), ID($_DFFSRE_PPPN_
), ID($_DFFSRE_PPPP_
)))
1574 { port(ID::C
,1); port(ID::S
,1); port(ID::R
,1); port(ID::D
,1); port(ID::E
,1); port(ID::Q
,1); check_expected(); return; }
1577 ID($_SDFF_NN0_
), ID($_SDFF_NN1_
), ID($_SDFF_NP0_
), ID($_SDFF_NP1_
),
1578 ID($_SDFF_PN0_
), ID($_SDFF_PN1_
), ID($_SDFF_PP0_
), ID($_SDFF_PP1_
)))
1579 { port(ID::D
,1); port(ID::Q
,1); port(ID::C
,1); port(ID::R
,1); check_expected(); return; }
1582 ID($_SDFFE_NN0N_
), ID($_SDFFE_NN0P_
), ID($_SDFFE_NN1N_
), ID($_SDFFE_NN1P_
),
1583 ID($_SDFFE_NP0N_
), ID($_SDFFE_NP0P_
), ID($_SDFFE_NP1N_
), ID($_SDFFE_NP1P_
),
1584 ID($_SDFFE_PN0N_
), ID($_SDFFE_PN0P_
), ID($_SDFFE_PN1N_
), ID($_SDFFE_PN1P_
),
1585 ID($_SDFFE_PP0N_
), ID($_SDFFE_PP0P_
), ID($_SDFFE_PP1N_
), ID($_SDFFE_PP1P_
),
1586 ID($_SDFFCE_NN0N_
), ID($_SDFFCE_NN0P_
), ID($_SDFFCE_NN1N_
), ID($_SDFFCE_NN1P_
),
1587 ID($_SDFFCE_NP0N_
), ID($_SDFFCE_NP0P_
), ID($_SDFFCE_NP1N_
), ID($_SDFFCE_NP1P_
),
1588 ID($_SDFFCE_PN0N_
), ID($_SDFFCE_PN0P_
), ID($_SDFFCE_PN1N_
), ID($_SDFFCE_PN1P_
),
1589 ID($_SDFFCE_PP0N_
), ID($_SDFFCE_PP0P_
), ID($_SDFFCE_PP1N_
), ID($_SDFFCE_PP1P_
)))
1590 { port(ID::D
,1); port(ID::Q
,1); port(ID::C
,1); port(ID::R
,1); port(ID::E
,1); check_expected(); return; }
1592 if (cell
->type
.in(ID($_DLATCH_N_
), ID($_DLATCH_P_
)))
1593 { port(ID::E
,1); port(ID::D
,1); port(ID::Q
,1); check_expected(); return; }
1596 ID($_DLATCH_NN0_
), ID($_DLATCH_NN1_
), ID($_DLATCH_NP0_
), ID($_DLATCH_NP1_
),
1597 ID($_DLATCH_PN0_
), ID($_DLATCH_PN1_
), ID($_DLATCH_PP0_
), ID($_DLATCH_PP1_
)))
1598 { port(ID::E
,1); port(ID::R
,1); port(ID::D
,1); port(ID::Q
,1); check_expected(); return; }
1601 ID($_DLATCHSR_NNN_
), ID($_DLATCHSR_NNP_
), ID($_DLATCHSR_NPN_
), ID($_DLATCHSR_NPP_
),
1602 ID($_DLATCHSR_PNN_
), ID($_DLATCHSR_PNP_
), ID($_DLATCHSR_PPN_
), ID($_DLATCHSR_PPP_
)))
1603 { port(ID::E
,1); port(ID::S
,1); port(ID::R
,1); port(ID::D
,1); port(ID::Q
,1); check_expected(); return; }
1611 void RTLIL::Module::sort()
1613 wires_
.sort(sort_by_id_str());
1614 cells_
.sort(sort_by_id_str());
1615 parameter_default_values
.sort(sort_by_id_str());
1616 memories
.sort(sort_by_id_str());
1617 processes
.sort(sort_by_id_str());
1618 for (auto &it
: cells_
)
1620 for (auto &it
: wires_
)
1621 it
.second
->attributes
.sort(sort_by_id_str());
1622 for (auto &it
: memories
)
1623 it
.second
->attributes
.sort(sort_by_id_str());
1626 void RTLIL::Module::check()
1629 std::vector
<bool> ports_declared
;
1630 for (auto &it
: wires_
) {
1631 log_assert(this == it
.second
->module
);
1632 log_assert(it
.first
== it
.second
->name
);
1633 log_assert(!it
.first
.empty());
1634 log_assert(it
.second
->width
>= 0);
1635 log_assert(it
.second
->port_id
>= 0);
1636 for (auto &it2
: it
.second
->attributes
)
1637 log_assert(!it2
.first
.empty());
1638 if (it
.second
->port_id
) {
1639 log_assert(GetSize(ports
) >= it
.second
->port_id
);
1640 log_assert(ports
.at(it
.second
->port_id
-1) == it
.first
);
1641 log_assert(it
.second
->port_input
|| it
.second
->port_output
);
1642 if (GetSize(ports_declared
) < it
.second
->port_id
)
1643 ports_declared
.resize(it
.second
->port_id
);
1644 log_assert(ports_declared
[it
.second
->port_id
-1] == false);
1645 ports_declared
[it
.second
->port_id
-1] = true;
1647 log_assert(!it
.second
->port_input
&& !it
.second
->port_output
);
1649 for (auto port_declared
: ports_declared
)
1650 log_assert(port_declared
== true);
1651 log_assert(GetSize(ports
) == GetSize(ports_declared
));
1653 for (auto &it
: memories
) {
1654 log_assert(it
.first
== it
.second
->name
);
1655 log_assert(!it
.first
.empty());
1656 log_assert(it
.second
->width
>= 0);
1657 log_assert(it
.second
->size
>= 0);
1658 for (auto &it2
: it
.second
->attributes
)
1659 log_assert(!it2
.first
.empty());
1662 for (auto &it
: cells_
) {
1663 log_assert(this == it
.second
->module
);
1664 log_assert(it
.first
== it
.second
->name
);
1665 log_assert(!it
.first
.empty());
1666 log_assert(!it
.second
->type
.empty());
1667 for (auto &it2
: it
.second
->connections()) {
1668 log_assert(!it2
.first
.empty());
1671 for (auto &it2
: it
.second
->attributes
)
1672 log_assert(!it2
.first
.empty());
1673 for (auto &it2
: it
.second
->parameters
)
1674 log_assert(!it2
.first
.empty());
1675 InternalCellChecker
checker(this, it
.second
);
1679 for (auto &it
: processes
) {
1680 log_assert(it
.first
== it
.second
->name
);
1681 log_assert(!it
.first
.empty());
1682 log_assert(it
.second
->root_case
.compare
.empty());
1683 std::vector
<CaseRule
*> all_cases
= {&it
.second
->root_case
};
1684 for (size_t i
= 0; i
< all_cases
.size(); i
++) {
1685 for (auto &switch_it
: all_cases
[i
]->switches
) {
1686 for (auto &case_it
: switch_it
->cases
) {
1687 for (auto &compare_it
: case_it
->compare
) {
1688 log_assert(switch_it
->signal
.size() == compare_it
.size());
1690 all_cases
.push_back(case_it
);
1694 for (auto &sync_it
: it
.second
->syncs
) {
1695 switch (sync_it
->type
) {
1701 log_assert(!sync_it
->signal
.empty());
1706 log_assert(sync_it
->signal
.empty());
1712 for (auto &it
: connections_
) {
1713 log_assert(it
.first
.size() == it
.second
.size());
1714 log_assert(!it
.first
.has_const());
1719 for (auto &it
: attributes
)
1720 log_assert(!it
.first
.empty());
1724 void RTLIL::Module::optimize()
1728 void RTLIL::Module::cloneInto(RTLIL::Module
*new_mod
) const
1730 log_assert(new_mod
->refcount_wires_
== 0);
1731 log_assert(new_mod
->refcount_cells_
== 0);
1733 new_mod
->avail_parameters
= avail_parameters
;
1734 new_mod
->parameter_default_values
= parameter_default_values
;
1736 for (auto &conn
: connections_
)
1737 new_mod
->connect(conn
);
1739 for (auto &attr
: attributes
)
1740 new_mod
->attributes
[attr
.first
] = attr
.second
;
1742 for (auto &it
: wires_
)
1743 new_mod
->addWire(it
.first
, it
.second
);
1745 for (auto &it
: memories
)
1746 new_mod
->addMemory(it
.first
, it
.second
);
1748 for (auto &it
: cells_
)
1749 new_mod
->addCell(it
.first
, it
.second
);
1751 for (auto &it
: processes
)
1752 new_mod
->addProcess(it
.first
, it
.second
);
1754 struct RewriteSigSpecWorker
1757 void operator()(RTLIL::SigSpec
&sig
)
1760 for (auto &c
: sig
.chunks_
)
1762 c
.wire
= mod
->wires_
.at(c
.wire
->name
);
1766 RewriteSigSpecWorker rewriteSigSpecWorker
;
1767 rewriteSigSpecWorker
.mod
= new_mod
;
1768 new_mod
->rewrite_sigspecs(rewriteSigSpecWorker
);
1769 new_mod
->fixup_ports();
1772 RTLIL::Module
*RTLIL::Module::clone() const
1774 RTLIL::Module
*new_mod
= new RTLIL::Module
;
1775 new_mod
->name
= name
;
1780 bool RTLIL::Module::has_memories() const
1782 return !memories
.empty();
1785 bool RTLIL::Module::has_processes() const
1787 return !processes
.empty();
1790 bool RTLIL::Module::has_memories_warn() const
1792 if (!memories
.empty())
1793 log_warning("Ignoring module %s because it contains memories (run 'memory' command first).\n", log_id(this));
1794 return !memories
.empty();
1797 bool RTLIL::Module::has_processes_warn() const
1799 if (!processes
.empty())
1800 log_warning("Ignoring module %s because it contains processes (run 'proc' command first).\n", log_id(this));
1801 return !processes
.empty();
1804 std::vector
<RTLIL::Wire
*> RTLIL::Module::selected_wires() const
1806 std::vector
<RTLIL::Wire
*> result
;
1807 result
.reserve(wires_
.size());
1808 for (auto &it
: wires_
)
1809 if (design
->selected(this, it
.second
))
1810 result
.push_back(it
.second
);
1814 std::vector
<RTLIL::Cell
*> RTLIL::Module::selected_cells() const
1816 std::vector
<RTLIL::Cell
*> result
;
1817 result
.reserve(cells_
.size());
1818 for (auto &it
: cells_
)
1819 if (design
->selected(this, it
.second
))
1820 result
.push_back(it
.second
);
1824 void RTLIL::Module::add(RTLIL::Wire
*wire
)
1826 log_assert(!wire
->name
.empty());
1827 log_assert(count_id(wire
->name
) == 0);
1828 log_assert(refcount_wires_
== 0);
1829 wires_
[wire
->name
] = wire
;
1830 wire
->module
= this;
1833 void RTLIL::Module::add(RTLIL::Cell
*cell
)
1835 log_assert(!cell
->name
.empty());
1836 log_assert(count_id(cell
->name
) == 0);
1837 log_assert(refcount_cells_
== 0);
1838 cells_
[cell
->name
] = cell
;
1839 cell
->module
= this;
1842 void RTLIL::Module::add(RTLIL::Process
*process
)
1844 log_assert(!process
->name
.empty());
1845 log_assert(count_id(process
->name
) == 0);
1846 processes
[process
->name
] = process
;
1847 process
->module
= this;
1850 void RTLIL::Module::remove(const pool
<RTLIL::Wire
*> &wires
)
1852 log_assert(refcount_wires_
== 0);
1854 struct DeleteWireWorker
1856 RTLIL::Module
*module
;
1857 const pool
<RTLIL::Wire
*> *wires_p
;
1859 void operator()(RTLIL::SigSpec
&sig
) {
1861 for (auto &c
: sig
.chunks_
)
1862 if (c
.wire
!= NULL
&& wires_p
->count(c
.wire
)) {
1863 c
.wire
= module
->addWire(stringf("$delete_wire$%d", autoidx
++), c
.width
);
1868 void operator()(RTLIL::SigSpec
&lhs
, RTLIL::SigSpec
&rhs
) {
1869 log_assert(GetSize(lhs
) == GetSize(rhs
));
1872 for (int i
= 0; i
< GetSize(lhs
); i
++) {
1873 RTLIL::SigBit
&lhs_bit
= lhs
.bits_
[i
];
1874 RTLIL::SigBit
&rhs_bit
= rhs
.bits_
[i
];
1875 if ((lhs_bit
.wire
!= nullptr && wires_p
->count(lhs_bit
.wire
)) || (rhs_bit
.wire
!= nullptr && wires_p
->count(rhs_bit
.wire
))) {
1876 lhs_bit
= State::Sx
;
1877 rhs_bit
= State::Sx
;
1883 DeleteWireWorker delete_wire_worker
;
1884 delete_wire_worker
.module
= this;
1885 delete_wire_worker
.wires_p
= &wires
;
1886 rewrite_sigspecs2(delete_wire_worker
);
1888 for (auto &it
: wires
) {
1889 log_assert(wires_
.count(it
->name
) != 0);
1890 wires_
.erase(it
->name
);
1895 void RTLIL::Module::remove(RTLIL::Cell
*cell
)
1897 while (!cell
->connections_
.empty())
1898 cell
->unsetPort(cell
->connections_
.begin()->first
);
1900 log_assert(cells_
.count(cell
->name
) != 0);
1901 log_assert(refcount_cells_
== 0);
1902 cells_
.erase(cell
->name
);
1906 void RTLIL::Module::remove(RTLIL::Process
*process
)
1908 log_assert(processes
.count(process
->name
) != 0);
1909 processes
.erase(process
->name
);
1913 void RTLIL::Module::rename(RTLIL::Wire
*wire
, RTLIL::IdString new_name
)
1915 log_assert(wires_
[wire
->name
] == wire
);
1916 log_assert(refcount_wires_
== 0);
1917 wires_
.erase(wire
->name
);
1918 wire
->name
= new_name
;
1922 void RTLIL::Module::rename(RTLIL::Cell
*cell
, RTLIL::IdString new_name
)
1924 log_assert(cells_
[cell
->name
] == cell
);
1925 log_assert(refcount_wires_
== 0);
1926 cells_
.erase(cell
->name
);
1927 cell
->name
= new_name
;
1931 void RTLIL::Module::rename(RTLIL::IdString old_name
, RTLIL::IdString new_name
)
1933 log_assert(count_id(old_name
) != 0);
1934 if (wires_
.count(old_name
))
1935 rename(wires_
.at(old_name
), new_name
);
1936 else if (cells_
.count(old_name
))
1937 rename(cells_
.at(old_name
), new_name
);
1942 void RTLIL::Module::swap_names(RTLIL::Wire
*w1
, RTLIL::Wire
*w2
)
1944 log_assert(wires_
[w1
->name
] == w1
);
1945 log_assert(wires_
[w2
->name
] == w2
);
1946 log_assert(refcount_wires_
== 0);
1948 wires_
.erase(w1
->name
);
1949 wires_
.erase(w2
->name
);
1951 std::swap(w1
->name
, w2
->name
);
1953 wires_
[w1
->name
] = w1
;
1954 wires_
[w2
->name
] = w2
;
1957 void RTLIL::Module::swap_names(RTLIL::Cell
*c1
, RTLIL::Cell
*c2
)
1959 log_assert(cells_
[c1
->name
] == c1
);
1960 log_assert(cells_
[c2
->name
] == c2
);
1961 log_assert(refcount_cells_
== 0);
1963 cells_
.erase(c1
->name
);
1964 cells_
.erase(c2
->name
);
1966 std::swap(c1
->name
, c2
->name
);
1968 cells_
[c1
->name
] = c1
;
1969 cells_
[c2
->name
] = c2
;
1972 RTLIL::IdString
RTLIL::Module::uniquify(RTLIL::IdString name
)
1975 return uniquify(name
, index
);
1978 RTLIL::IdString
RTLIL::Module::uniquify(RTLIL::IdString name
, int &index
)
1981 if (count_id(name
) == 0)
1987 RTLIL::IdString new_name
= stringf("%s_%d", name
.c_str(), index
);
1988 if (count_id(new_name
) == 0)
1994 static bool fixup_ports_compare(const RTLIL::Wire
*a
, const RTLIL::Wire
*b
)
1996 if (a
->port_id
&& !b
->port_id
)
1998 if (!a
->port_id
&& b
->port_id
)
2001 if (a
->port_id
== b
->port_id
)
2002 return a
->name
< b
->name
;
2003 return a
->port_id
< b
->port_id
;
2006 void RTLIL::Module::connect(const RTLIL::SigSig
&conn
)
2008 for (auto mon
: monitors
)
2009 mon
->notify_connect(this, conn
);
2012 for (auto mon
: design
->monitors
)
2013 mon
->notify_connect(this, conn
);
2015 // ignore all attempts to assign constants to other constants
2016 if (conn
.first
.has_const()) {
2017 RTLIL::SigSig new_conn
;
2018 for (int i
= 0; i
< GetSize(conn
.first
); i
++)
2019 if (conn
.first
[i
].wire
) {
2020 new_conn
.first
.append(conn
.first
[i
]);
2021 new_conn
.second
.append(conn
.second
[i
]);
2023 if (GetSize(new_conn
.first
))
2029 log("#X# Connect (SigSig) in %s: %s = %s (%d bits)\n", log_id(this), log_signal(conn
.first
), log_signal(conn
.second
), GetSize(conn
.first
));
2030 log_backtrace("-X- ", yosys_xtrace
-1);
2033 log_assert(GetSize(conn
.first
) == GetSize(conn
.second
));
2034 connections_
.push_back(conn
);
2037 void RTLIL::Module::connect(const RTLIL::SigSpec
&lhs
, const RTLIL::SigSpec
&rhs
)
2039 connect(RTLIL::SigSig(lhs
, rhs
));
2042 void RTLIL::Module::new_connections(const std::vector
<RTLIL::SigSig
> &new_conn
)
2044 for (auto mon
: monitors
)
2045 mon
->notify_connect(this, new_conn
);
2048 for (auto mon
: design
->monitors
)
2049 mon
->notify_connect(this, new_conn
);
2052 log("#X# New connections vector in %s:\n", log_id(this));
2053 for (auto &conn
: new_conn
)
2054 log("#X# %s = %s (%d bits)\n", log_signal(conn
.first
), log_signal(conn
.second
), GetSize(conn
.first
));
2055 log_backtrace("-X- ", yosys_xtrace
-1);
2058 connections_
= new_conn
;
2061 const std::vector
<RTLIL::SigSig
> &RTLIL::Module::connections() const
2063 return connections_
;
2066 void RTLIL::Module::fixup_ports()
2068 std::vector
<RTLIL::Wire
*> all_ports
;
2070 for (auto &w
: wires_
)
2071 if (w
.second
->port_input
|| w
.second
->port_output
)
2072 all_ports
.push_back(w
.second
);
2074 w
.second
->port_id
= 0;
2076 std::sort(all_ports
.begin(), all_ports
.end(), fixup_ports_compare
);
2079 for (size_t i
= 0; i
< all_ports
.size(); i
++) {
2080 ports
.push_back(all_ports
[i
]->name
);
2081 all_ports
[i
]->port_id
= i
+1;
2085 RTLIL::Wire
*RTLIL::Module::addWire(RTLIL::IdString name
, int width
)
2087 RTLIL::Wire
*wire
= new RTLIL::Wire
;
2089 wire
->width
= width
;
2094 RTLIL::Wire
*RTLIL::Module::addWire(RTLIL::IdString name
, const RTLIL::Wire
*other
)
2096 RTLIL::Wire
*wire
= addWire(name
);
2097 wire
->width
= other
->width
;
2098 wire
->start_offset
= other
->start_offset
;
2099 wire
->port_id
= other
->port_id
;
2100 wire
->port_input
= other
->port_input
;
2101 wire
->port_output
= other
->port_output
;
2102 wire
->upto
= other
->upto
;
2103 wire
->is_signed
= other
->is_signed
;
2104 wire
->attributes
= other
->attributes
;
2108 RTLIL::Cell
*RTLIL::Module::addCell(RTLIL::IdString name
, RTLIL::IdString type
)
2110 RTLIL::Cell
*cell
= new RTLIL::Cell
;
2117 RTLIL::Cell
*RTLIL::Module::addCell(RTLIL::IdString name
, const RTLIL::Cell
*other
)
2119 RTLIL::Cell
*cell
= addCell(name
, other
->type
);
2120 cell
->connections_
= other
->connections_
;
2121 cell
->parameters
= other
->parameters
;
2122 cell
->attributes
= other
->attributes
;
2126 RTLIL::Memory
*RTLIL::Module::addMemory(RTLIL::IdString name
, const RTLIL::Memory
*other
)
2128 RTLIL::Memory
*mem
= new RTLIL::Memory
;
2130 mem
->width
= other
->width
;
2131 mem
->start_offset
= other
->start_offset
;
2132 mem
->size
= other
->size
;
2133 mem
->attributes
= other
->attributes
;
2134 memories
[mem
->name
] = mem
;
2138 RTLIL::Process
*RTLIL::Module::addProcess(RTLIL::IdString name
)
2140 RTLIL::Process
*proc
= new RTLIL::Process
;
2146 RTLIL::Process
*RTLIL::Module::addProcess(RTLIL::IdString name
, const RTLIL::Process
*other
)
2148 RTLIL::Process
*proc
= other
->clone();
2154 #define DEF_METHOD(_func, _y_size, _type) \
2155 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed, const std::string &src) { \
2156 RTLIL::Cell *cell = addCell(name, _type); \
2157 cell->parameters[ID::A_SIGNED] = is_signed; \
2158 cell->parameters[ID::A_WIDTH] = sig_a.size(); \
2159 cell->parameters[ID::Y_WIDTH] = sig_y.size(); \
2160 cell->setPort(ID::A, sig_a); \
2161 cell->setPort(ID::Y, sig_y); \
2162 cell->set_src_attribute(src); \
2165 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed, const std::string &src) { \
2166 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
2167 add ## _func(name, sig_a, sig_y, is_signed, src); \
2170 DEF_METHOD(Not
, sig_a
.size(), ID($
not))
2171 DEF_METHOD(Pos
, sig_a
.size(), ID($pos
))
2172 DEF_METHOD(Neg
, sig_a
.size(), ID($neg
))
2173 DEF_METHOD(ReduceAnd
, 1, ID($reduce_and
))
2174 DEF_METHOD(ReduceOr
, 1, ID($reduce_or
))
2175 DEF_METHOD(ReduceXor
, 1, ID($reduce_xor
))
2176 DEF_METHOD(ReduceXnor
, 1, ID($reduce_xnor
))
2177 DEF_METHOD(ReduceBool
, 1, ID($reduce_bool
))
2178 DEF_METHOD(LogicNot
, 1, ID($logic_not
))
2181 #define DEF_METHOD(_func, _y_size, _type) \
2182 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed, const std::string &src) { \
2183 RTLIL::Cell *cell = addCell(name, _type); \
2184 cell->parameters[ID::A_SIGNED] = is_signed; \
2185 cell->parameters[ID::B_SIGNED] = is_signed; \
2186 cell->parameters[ID::A_WIDTH] = sig_a.size(); \
2187 cell->parameters[ID::B_WIDTH] = sig_b.size(); \
2188 cell->parameters[ID::Y_WIDTH] = sig_y.size(); \
2189 cell->setPort(ID::A, sig_a); \
2190 cell->setPort(ID::B, sig_b); \
2191 cell->setPort(ID::Y, sig_y); \
2192 cell->set_src_attribute(src); \
2195 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed, const std::string &src) { \
2196 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
2197 add ## _func(name, sig_a, sig_b, sig_y, is_signed, src); \
2200 DEF_METHOD(And
, max(sig_a
.size(), sig_b
.size()), ID($
and))
2201 DEF_METHOD(Or
, max(sig_a
.size(), sig_b
.size()), ID($
or))
2202 DEF_METHOD(Xor
, max(sig_a
.size(), sig_b
.size()), ID($
xor))
2203 DEF_METHOD(Xnor
, max(sig_a
.size(), sig_b
.size()), ID($xnor
))
2204 DEF_METHOD(Shift
, sig_a
.size(), ID($shift
))
2205 DEF_METHOD(Shiftx
, sig_a
.size(), ID($shiftx
))
2206 DEF_METHOD(Lt
, 1, ID($lt
))
2207 DEF_METHOD(Le
, 1, ID($le
))
2208 DEF_METHOD(Eq
, 1, ID($eq
))
2209 DEF_METHOD(Ne
, 1, ID($ne
))
2210 DEF_METHOD(Eqx
, 1, ID($eqx
))
2211 DEF_METHOD(Nex
, 1, ID($nex
))
2212 DEF_METHOD(Ge
, 1, ID($ge
))
2213 DEF_METHOD(Gt
, 1, ID($gt
))
2214 DEF_METHOD(Add
, max(sig_a
.size(), sig_b
.size()), ID($add
))
2215 DEF_METHOD(Sub
, max(sig_a
.size(), sig_b
.size()), ID($sub
))
2216 DEF_METHOD(Mul
, max(sig_a
.size(), sig_b
.size()), ID($mul
))
2217 DEF_METHOD(Div
, max(sig_a
.size(), sig_b
.size()), ID($div
))
2218 DEF_METHOD(Mod
, max(sig_a
.size(), sig_b
.size()), ID($mod
))
2219 DEF_METHOD(DivFloor
, max(sig_a
.size(), sig_b
.size()), ID($divfloor
))
2220 DEF_METHOD(ModFloor
, max(sig_a
.size(), sig_b
.size()), ID($modfloor
))
2221 DEF_METHOD(LogicAnd
, 1, ID($logic_and
))
2222 DEF_METHOD(LogicOr
, 1, ID($logic_or
))
2225 #define DEF_METHOD(_func, _y_size, _type) \
2226 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed, const std::string &src) { \
2227 RTLIL::Cell *cell = addCell(name, _type); \
2228 cell->parameters[ID::A_SIGNED] = is_signed; \
2229 cell->parameters[ID::B_SIGNED] = false; \
2230 cell->parameters[ID::A_WIDTH] = sig_a.size(); \
2231 cell->parameters[ID::B_WIDTH] = sig_b.size(); \
2232 cell->parameters[ID::Y_WIDTH] = sig_y.size(); \
2233 cell->setPort(ID::A, sig_a); \
2234 cell->setPort(ID::B, sig_b); \
2235 cell->setPort(ID::Y, sig_y); \
2236 cell->set_src_attribute(src); \
2239 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed, const std::string &src) { \
2240 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
2241 add ## _func(name, sig_a, sig_b, sig_y, is_signed, src); \
2244 DEF_METHOD(Shl
, sig_a
.size(), ID($shl
))
2245 DEF_METHOD(Shr
, sig_a
.size(), ID($shr
))
2246 DEF_METHOD(Sshl
, sig_a
.size(), ID($sshl
))
2247 DEF_METHOD(Sshr
, sig_a
.size(), ID($sshr
))
2250 #define DEF_METHOD(_func, _type, _pmux) \
2251 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, const std::string &src) { \
2252 RTLIL::Cell *cell = addCell(name, _type); \
2253 cell->parameters[ID::WIDTH] = sig_a.size(); \
2254 if (_pmux) cell->parameters[ID::S_WIDTH] = sig_s.size(); \
2255 cell->setPort(ID::A, sig_a); \
2256 cell->setPort(ID::B, sig_b); \
2257 cell->setPort(ID::S, sig_s); \
2258 cell->setPort(ID::Y, sig_y); \
2259 cell->set_src_attribute(src); \
2262 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const std::string &src) { \
2263 RTLIL::SigSpec sig_y = addWire(NEW_ID, sig_a.size()); \
2264 add ## _func(name, sig_a, sig_b, sig_s, sig_y, src); \
2267 DEF_METHOD(Mux
, ID($mux
), 0)
2268 DEF_METHOD(Pmux
, ID($pmux
), 1)
2271 #define DEF_METHOD_2(_func, _type, _P1, _P2) \
2272 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const std::string &src) { \
2273 RTLIL::Cell *cell = addCell(name, _type); \
2274 cell->setPort("\\" #_P1, sig1); \
2275 cell->setPort("\\" #_P2, sig2); \
2276 cell->set_src_attribute(src); \
2279 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const std::string &src) { \
2280 RTLIL::SigBit sig2 = addWire(NEW_ID); \
2281 add ## _func(name, sig1, sig2, src); \
2284 #define DEF_METHOD_3(_func, _type, _P1, _P2, _P3) \
2285 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const RTLIL::SigBit &sig3, const std::string &src) { \
2286 RTLIL::Cell *cell = addCell(name, _type); \
2287 cell->setPort("\\" #_P1, sig1); \
2288 cell->setPort("\\" #_P2, sig2); \
2289 cell->setPort("\\" #_P3, sig3); \
2290 cell->set_src_attribute(src); \
2293 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const std::string &src) { \
2294 RTLIL::SigBit sig3 = addWire(NEW_ID); \
2295 add ## _func(name, sig1, sig2, sig3, src); \
2298 #define DEF_METHOD_4(_func, _type, _P1, _P2, _P3, _P4) \
2299 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const RTLIL::SigBit &sig3, const RTLIL::SigBit &sig4, const std::string &src) { \
2300 RTLIL::Cell *cell = addCell(name, _type); \
2301 cell->setPort("\\" #_P1, sig1); \
2302 cell->setPort("\\" #_P2, sig2); \
2303 cell->setPort("\\" #_P3, sig3); \
2304 cell->setPort("\\" #_P4, sig4); \
2305 cell->set_src_attribute(src); \
2308 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const RTLIL::SigBit &sig3, const std::string &src) { \
2309 RTLIL::SigBit sig4 = addWire(NEW_ID); \
2310 add ## _func(name, sig1, sig2, sig3, sig4, src); \
2313 #define DEF_METHOD_5(_func, _type, _P1, _P2, _P3, _P4, _P5) \
2314 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const RTLIL::SigBit &sig3, const RTLIL::SigBit &sig4, const RTLIL::SigBit &sig5, const std::string &src) { \
2315 RTLIL::Cell *cell = addCell(name, _type); \
2316 cell->setPort("\\" #_P1, sig1); \
2317 cell->setPort("\\" #_P2, sig2); \
2318 cell->setPort("\\" #_P3, sig3); \
2319 cell->setPort("\\" #_P4, sig4); \
2320 cell->setPort("\\" #_P5, sig5); \
2321 cell->set_src_attribute(src); \
2324 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const RTLIL::SigBit &sig3, const RTLIL::SigBit &sig4, const std::string &src) { \
2325 RTLIL::SigBit sig5 = addWire(NEW_ID); \
2326 add ## _func(name, sig1, sig2, sig3, sig4, sig5, src); \
2329 DEF_METHOD_2(BufGate
, ID($_BUF_
), A
, Y
)
2330 DEF_METHOD_2(NotGate
, ID($_NOT_
), A
, Y
)
2331 DEF_METHOD_3(AndGate
, ID($_AND_
), A
, B
, Y
)
2332 DEF_METHOD_3(NandGate
, ID($_NAND_
), A
, B
, Y
)
2333 DEF_METHOD_3(OrGate
, ID($_OR_
), A
, B
, Y
)
2334 DEF_METHOD_3(NorGate
, ID($_NOR_
), A
, B
, Y
)
2335 DEF_METHOD_3(XorGate
, ID($_XOR_
), A
, B
, Y
)
2336 DEF_METHOD_3(XnorGate
, ID($_XNOR_
), A
, B
, Y
)
2337 DEF_METHOD_3(AndnotGate
, ID($_ANDNOT_
), A
, B
, Y
)
2338 DEF_METHOD_3(OrnotGate
, ID($_ORNOT_
), A
, B
, Y
)
2339 DEF_METHOD_4(MuxGate
, ID($_MUX_
), A
, B
, S
, Y
)
2340 DEF_METHOD_4(NmuxGate
, ID($_NMUX_
), A
, B
, S
, Y
)
2341 DEF_METHOD_4(Aoi3Gate
, ID($_AOI3_
), A
, B
, C
, Y
)
2342 DEF_METHOD_4(Oai3Gate
, ID($_OAI3_
), A
, B
, C
, Y
)
2343 DEF_METHOD_5(Aoi4Gate
, ID($_AOI4_
), A
, B
, C
, D
, Y
)
2344 DEF_METHOD_5(Oai4Gate
, ID($_OAI4_
), A
, B
, C
, D
, Y
)
2350 RTLIL::Cell
* RTLIL::Module::addPow(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_a
, const RTLIL::SigSpec
&sig_b
, const RTLIL::SigSpec
&sig_y
, bool a_signed
, bool b_signed
, const std::string
&src
)
2352 RTLIL::Cell
*cell
= addCell(name
, ID($pow
));
2353 cell
->parameters
[ID::A_SIGNED
] = a_signed
;
2354 cell
->parameters
[ID::B_SIGNED
] = b_signed
;
2355 cell
->parameters
[ID::A_WIDTH
] = sig_a
.size();
2356 cell
->parameters
[ID::B_WIDTH
] = sig_b
.size();
2357 cell
->parameters
[ID::Y_WIDTH
] = sig_y
.size();
2358 cell
->setPort(ID::A
, sig_a
);
2359 cell
->setPort(ID::B
, sig_b
);
2360 cell
->setPort(ID::Y
, sig_y
);
2361 cell
->set_src_attribute(src
);
2365 RTLIL::Cell
* RTLIL::Module::addSlice(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_a
, const RTLIL::SigSpec
&sig_y
, RTLIL::Const offset
, const std::string
&src
)
2367 RTLIL::Cell
*cell
= addCell(name
, ID($slice
));
2368 cell
->parameters
[ID::A_WIDTH
] = sig_a
.size();
2369 cell
->parameters
[ID::Y_WIDTH
] = sig_y
.size();
2370 cell
->parameters
[ID::OFFSET
] = offset
;
2371 cell
->setPort(ID::A
, sig_a
);
2372 cell
->setPort(ID::Y
, sig_y
);
2373 cell
->set_src_attribute(src
);
2377 RTLIL::Cell
* RTLIL::Module::addConcat(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_a
, const RTLIL::SigSpec
&sig_b
, const RTLIL::SigSpec
&sig_y
, const std::string
&src
)
2379 RTLIL::Cell
*cell
= addCell(name
, ID($concat
));
2380 cell
->parameters
[ID::A_WIDTH
] = sig_a
.size();
2381 cell
->parameters
[ID::B_WIDTH
] = sig_b
.size();
2382 cell
->setPort(ID::A
, sig_a
);
2383 cell
->setPort(ID::B
, sig_b
);
2384 cell
->setPort(ID::Y
, sig_y
);
2385 cell
->set_src_attribute(src
);
2389 RTLIL::Cell
* RTLIL::Module::addLut(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_a
, const RTLIL::SigSpec
&sig_y
, RTLIL::Const lut
, const std::string
&src
)
2391 RTLIL::Cell
*cell
= addCell(name
, ID($lut
));
2392 cell
->parameters
[ID::LUT
] = lut
;
2393 cell
->parameters
[ID::WIDTH
] = sig_a
.size();
2394 cell
->setPort(ID::A
, sig_a
);
2395 cell
->setPort(ID::Y
, sig_y
);
2396 cell
->set_src_attribute(src
);
2400 RTLIL::Cell
* RTLIL::Module::addTribuf(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_a
, const RTLIL::SigSpec
&sig_en
, const RTLIL::SigSpec
&sig_y
, const std::string
&src
)
2402 RTLIL::Cell
*cell
= addCell(name
, ID($tribuf
));
2403 cell
->parameters
[ID::WIDTH
] = sig_a
.size();
2404 cell
->setPort(ID::A
, sig_a
);
2405 cell
->setPort(ID::EN
, sig_en
);
2406 cell
->setPort(ID::Y
, sig_y
);
2407 cell
->set_src_attribute(src
);
2411 RTLIL::Cell
* RTLIL::Module::addAssert(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_a
, const RTLIL::SigSpec
&sig_en
, const std::string
&src
)
2413 RTLIL::Cell
*cell
= addCell(name
, ID($
assert));
2414 cell
->setPort(ID::A
, sig_a
);
2415 cell
->setPort(ID::EN
, sig_en
);
2416 cell
->set_src_attribute(src
);
2420 RTLIL::Cell
* RTLIL::Module::addAssume(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_a
, const RTLIL::SigSpec
&sig_en
, const std::string
&src
)
2422 RTLIL::Cell
*cell
= addCell(name
, ID($assume
));
2423 cell
->setPort(ID::A
, sig_a
);
2424 cell
->setPort(ID::EN
, sig_en
);
2425 cell
->set_src_attribute(src
);
2429 RTLIL::Cell
* RTLIL::Module::addLive(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_a
, const RTLIL::SigSpec
&sig_en
, const std::string
&src
)
2431 RTLIL::Cell
*cell
= addCell(name
, ID($live
));
2432 cell
->setPort(ID::A
, sig_a
);
2433 cell
->setPort(ID::EN
, sig_en
);
2434 cell
->set_src_attribute(src
);
2438 RTLIL::Cell
* RTLIL::Module::addFair(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_a
, const RTLIL::SigSpec
&sig_en
, const std::string
&src
)
2440 RTLIL::Cell
*cell
= addCell(name
, ID($fair
));
2441 cell
->setPort(ID::A
, sig_a
);
2442 cell
->setPort(ID::EN
, sig_en
);
2443 cell
->set_src_attribute(src
);
2447 RTLIL::Cell
* RTLIL::Module::addCover(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_a
, const RTLIL::SigSpec
&sig_en
, const std::string
&src
)
2449 RTLIL::Cell
*cell
= addCell(name
, ID($cover
));
2450 cell
->setPort(ID::A
, sig_a
);
2451 cell
->setPort(ID::EN
, sig_en
);
2452 cell
->set_src_attribute(src
);
2456 RTLIL::Cell
* RTLIL::Module::addEquiv(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_a
, const RTLIL::SigSpec
&sig_b
, const RTLIL::SigSpec
&sig_y
, const std::string
&src
)
2458 RTLIL::Cell
*cell
= addCell(name
, ID($equiv
));
2459 cell
->setPort(ID::A
, sig_a
);
2460 cell
->setPort(ID::B
, sig_b
);
2461 cell
->setPort(ID::Y
, sig_y
);
2462 cell
->set_src_attribute(src
);
2466 RTLIL::Cell
* RTLIL::Module::addSr(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_set
, const RTLIL::SigSpec
&sig_clr
, const RTLIL::SigSpec
&sig_q
, bool set_polarity
, bool clr_polarity
, const std::string
&src
)
2468 RTLIL::Cell
*cell
= addCell(name
, ID($sr
));
2469 cell
->parameters
[ID::SET_POLARITY
] = set_polarity
;
2470 cell
->parameters
[ID::CLR_POLARITY
] = clr_polarity
;
2471 cell
->parameters
[ID::WIDTH
] = sig_q
.size();
2472 cell
->setPort(ID::SET
, sig_set
);
2473 cell
->setPort(ID::CLR
, sig_clr
);
2474 cell
->setPort(ID::Q
, sig_q
);
2475 cell
->set_src_attribute(src
);
2479 RTLIL::Cell
* RTLIL::Module::addFf(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_d
, const RTLIL::SigSpec
&sig_q
, const std::string
&src
)
2481 RTLIL::Cell
*cell
= addCell(name
, ID($ff
));
2482 cell
->parameters
[ID::WIDTH
] = sig_q
.size();
2483 cell
->setPort(ID::D
, sig_d
);
2484 cell
->setPort(ID::Q
, sig_q
);
2485 cell
->set_src_attribute(src
);
2489 RTLIL::Cell
* RTLIL::Module::addDff(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_clk
, const RTLIL::SigSpec
&sig_d
, const RTLIL::SigSpec
&sig_q
, bool clk_polarity
, const std::string
&src
)
2491 RTLIL::Cell
*cell
= addCell(name
, ID($dff
));
2492 cell
->parameters
[ID::CLK_POLARITY
] = clk_polarity
;
2493 cell
->parameters
[ID::WIDTH
] = sig_q
.size();
2494 cell
->setPort(ID::CLK
, sig_clk
);
2495 cell
->setPort(ID::D
, sig_d
);
2496 cell
->setPort(ID::Q
, sig_q
);
2497 cell
->set_src_attribute(src
);
2501 RTLIL::Cell
* RTLIL::Module::addDffe(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_clk
, const RTLIL::SigSpec
&sig_en
, const RTLIL::SigSpec
&sig_d
, const RTLIL::SigSpec
&sig_q
, bool clk_polarity
, bool en_polarity
, const std::string
&src
)
2503 RTLIL::Cell
*cell
= addCell(name
, ID($dffe
));
2504 cell
->parameters
[ID::CLK_POLARITY
] = clk_polarity
;
2505 cell
->parameters
[ID::EN_POLARITY
] = en_polarity
;
2506 cell
->parameters
[ID::WIDTH
] = sig_q
.size();
2507 cell
->setPort(ID::CLK
, sig_clk
);
2508 cell
->setPort(ID::EN
, sig_en
);
2509 cell
->setPort(ID::D
, sig_d
);
2510 cell
->setPort(ID::Q
, sig_q
);
2511 cell
->set_src_attribute(src
);
2515 RTLIL::Cell
* RTLIL::Module::addDffsr(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_clk
, const RTLIL::SigSpec
&sig_set
, const RTLIL::SigSpec
&sig_clr
,
2516 RTLIL::SigSpec sig_d
, const RTLIL::SigSpec
&sig_q
, bool clk_polarity
, bool set_polarity
, bool clr_polarity
, const std::string
&src
)
2518 RTLIL::Cell
*cell
= addCell(name
, ID($dffsr
));
2519 cell
->parameters
[ID::CLK_POLARITY
] = clk_polarity
;
2520 cell
->parameters
[ID::SET_POLARITY
] = set_polarity
;
2521 cell
->parameters
[ID::CLR_POLARITY
] = clr_polarity
;
2522 cell
->parameters
[ID::WIDTH
] = sig_q
.size();
2523 cell
->setPort(ID::CLK
, sig_clk
);
2524 cell
->setPort(ID::SET
, sig_set
);
2525 cell
->setPort(ID::CLR
, sig_clr
);
2526 cell
->setPort(ID::D
, sig_d
);
2527 cell
->setPort(ID::Q
, sig_q
);
2528 cell
->set_src_attribute(src
);
2532 RTLIL::Cell
* RTLIL::Module::addDffsre(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_clk
, const RTLIL::SigSpec
&sig_en
, const RTLIL::SigSpec
&sig_set
, const RTLIL::SigSpec
&sig_clr
,
2533 RTLIL::SigSpec sig_d
, const RTLIL::SigSpec
&sig_q
, bool clk_polarity
, bool en_polarity
, bool set_polarity
, bool clr_polarity
, const std::string
&src
)
2535 RTLIL::Cell
*cell
= addCell(name
, ID($dffsre
));
2536 cell
->parameters
[ID::CLK_POLARITY
] = clk_polarity
;
2537 cell
->parameters
[ID::EN_POLARITY
] = en_polarity
;
2538 cell
->parameters
[ID::SET_POLARITY
] = set_polarity
;
2539 cell
->parameters
[ID::CLR_POLARITY
] = clr_polarity
;
2540 cell
->parameters
[ID::WIDTH
] = sig_q
.size();
2541 cell
->setPort(ID::CLK
, sig_clk
);
2542 cell
->setPort(ID::EN
, sig_en
);
2543 cell
->setPort(ID::SET
, sig_set
);
2544 cell
->setPort(ID::CLR
, sig_clr
);
2545 cell
->setPort(ID::D
, sig_d
);
2546 cell
->setPort(ID::Q
, sig_q
);
2547 cell
->set_src_attribute(src
);
2551 RTLIL::Cell
* RTLIL::Module::addAdff(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_clk
, const RTLIL::SigSpec
&sig_arst
, const RTLIL::SigSpec
&sig_d
, const RTLIL::SigSpec
&sig_q
,
2552 RTLIL::Const arst_value
, bool clk_polarity
, bool arst_polarity
, const std::string
&src
)
2554 RTLIL::Cell
*cell
= addCell(name
, ID($adff
));
2555 cell
->parameters
[ID::CLK_POLARITY
] = clk_polarity
;
2556 cell
->parameters
[ID::ARST_POLARITY
] = arst_polarity
;
2557 cell
->parameters
[ID::ARST_VALUE
] = arst_value
;
2558 cell
->parameters
[ID::WIDTH
] = sig_q
.size();
2559 cell
->setPort(ID::CLK
, sig_clk
);
2560 cell
->setPort(ID::ARST
, sig_arst
);
2561 cell
->setPort(ID::D
, sig_d
);
2562 cell
->setPort(ID::Q
, sig_q
);
2563 cell
->set_src_attribute(src
);
2567 RTLIL::Cell
* RTLIL::Module::addAdffe(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_clk
, const RTLIL::SigSpec
&sig_en
, const RTLIL::SigSpec
&sig_arst
, const RTLIL::SigSpec
&sig_d
, const RTLIL::SigSpec
&sig_q
,
2568 RTLIL::Const arst_value
, bool clk_polarity
, bool en_polarity
, bool arst_polarity
, const std::string
&src
)
2570 RTLIL::Cell
*cell
= addCell(name
, ID($adffe
));
2571 cell
->parameters
[ID::CLK_POLARITY
] = clk_polarity
;
2572 cell
->parameters
[ID::EN_POLARITY
] = en_polarity
;
2573 cell
->parameters
[ID::ARST_POLARITY
] = arst_polarity
;
2574 cell
->parameters
[ID::ARST_VALUE
] = arst_value
;
2575 cell
->parameters
[ID::WIDTH
] = sig_q
.size();
2576 cell
->setPort(ID::CLK
, sig_clk
);
2577 cell
->setPort(ID::EN
, sig_en
);
2578 cell
->setPort(ID::ARST
, sig_arst
);
2579 cell
->setPort(ID::D
, sig_d
);
2580 cell
->setPort(ID::Q
, sig_q
);
2581 cell
->set_src_attribute(src
);
2585 RTLIL::Cell
* RTLIL::Module::addSdff(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_clk
, const RTLIL::SigSpec
&sig_srst
, const RTLIL::SigSpec
&sig_d
, const RTLIL::SigSpec
&sig_q
,
2586 RTLIL::Const srst_value
, bool clk_polarity
, bool srst_polarity
, const std::string
&src
)
2588 RTLIL::Cell
*cell
= addCell(name
, ID($sdff
));
2589 cell
->parameters
[ID::CLK_POLARITY
] = clk_polarity
;
2590 cell
->parameters
[ID::SRST_POLARITY
] = srst_polarity
;
2591 cell
->parameters
[ID::SRST_VALUE
] = srst_value
;
2592 cell
->parameters
[ID::WIDTH
] = sig_q
.size();
2593 cell
->setPort(ID::CLK
, sig_clk
);
2594 cell
->setPort(ID::SRST
, sig_srst
);
2595 cell
->setPort(ID::D
, sig_d
);
2596 cell
->setPort(ID::Q
, sig_q
);
2597 cell
->set_src_attribute(src
);
2601 RTLIL::Cell
* RTLIL::Module::addSdffe(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_clk
, const RTLIL::SigSpec
&sig_en
, const RTLIL::SigSpec
&sig_srst
, const RTLIL::SigSpec
&sig_d
, const RTLIL::SigSpec
&sig_q
,
2602 RTLIL::Const srst_value
, bool clk_polarity
, bool en_polarity
, bool srst_polarity
, const std::string
&src
)
2604 RTLIL::Cell
*cell
= addCell(name
, ID($sdffe
));
2605 cell
->parameters
[ID::CLK_POLARITY
] = clk_polarity
;
2606 cell
->parameters
[ID::EN_POLARITY
] = en_polarity
;
2607 cell
->parameters
[ID::SRST_POLARITY
] = srst_polarity
;
2608 cell
->parameters
[ID::SRST_VALUE
] = srst_value
;
2609 cell
->parameters
[ID::WIDTH
] = sig_q
.size();
2610 cell
->setPort(ID::CLK
, sig_clk
);
2611 cell
->setPort(ID::EN
, sig_en
);
2612 cell
->setPort(ID::SRST
, sig_srst
);
2613 cell
->setPort(ID::D
, sig_d
);
2614 cell
->setPort(ID::Q
, sig_q
);
2615 cell
->set_src_attribute(src
);
2619 RTLIL::Cell
* RTLIL::Module::addSdffce(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_clk
, const RTLIL::SigSpec
&sig_en
, const RTLIL::SigSpec
&sig_srst
, const RTLIL::SigSpec
&sig_d
, const RTLIL::SigSpec
&sig_q
,
2620 RTLIL::Const srst_value
, bool clk_polarity
, bool en_polarity
, bool srst_polarity
, const std::string
&src
)
2622 RTLIL::Cell
*cell
= addCell(name
, ID($sdffce
));
2623 cell
->parameters
[ID::CLK_POLARITY
] = clk_polarity
;
2624 cell
->parameters
[ID::EN_POLARITY
] = en_polarity
;
2625 cell
->parameters
[ID::SRST_POLARITY
] = srst_polarity
;
2626 cell
->parameters
[ID::SRST_VALUE
] = srst_value
;
2627 cell
->parameters
[ID::WIDTH
] = sig_q
.size();
2628 cell
->setPort(ID::CLK
, sig_clk
);
2629 cell
->setPort(ID::EN
, sig_en
);
2630 cell
->setPort(ID::SRST
, sig_srst
);
2631 cell
->setPort(ID::D
, sig_d
);
2632 cell
->setPort(ID::Q
, sig_q
);
2633 cell
->set_src_attribute(src
);
2637 RTLIL::Cell
* RTLIL::Module::addDlatch(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_en
, const RTLIL::SigSpec
&sig_d
, const RTLIL::SigSpec
&sig_q
, bool en_polarity
, const std::string
&src
)
2639 RTLIL::Cell
*cell
= addCell(name
, ID($dlatch
));
2640 cell
->parameters
[ID::EN_POLARITY
] = en_polarity
;
2641 cell
->parameters
[ID::WIDTH
] = sig_q
.size();
2642 cell
->setPort(ID::EN
, sig_en
);
2643 cell
->setPort(ID::D
, sig_d
);
2644 cell
->setPort(ID::Q
, sig_q
);
2645 cell
->set_src_attribute(src
);
2649 RTLIL::Cell
* RTLIL::Module::addAdlatch(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_en
, const RTLIL::SigSpec
&sig_arst
, const RTLIL::SigSpec
&sig_d
, const RTLIL::SigSpec
&sig_q
,
2650 RTLIL::Const arst_value
, bool en_polarity
, bool arst_polarity
, const std::string
&src
)
2652 RTLIL::Cell
*cell
= addCell(name
, ID($adlatch
));
2653 cell
->parameters
[ID::EN_POLARITY
] = en_polarity
;
2654 cell
->parameters
[ID::ARST_POLARITY
] = arst_polarity
;
2655 cell
->parameters
[ID::ARST_VALUE
] = arst_value
;
2656 cell
->parameters
[ID::WIDTH
] = sig_q
.size();
2657 cell
->setPort(ID::EN
, sig_en
);
2658 cell
->setPort(ID::ARST
, sig_arst
);
2659 cell
->setPort(ID::D
, sig_d
);
2660 cell
->setPort(ID::Q
, sig_q
);
2661 cell
->set_src_attribute(src
);
2665 RTLIL::Cell
* RTLIL::Module::addDlatchsr(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_en
, const RTLIL::SigSpec
&sig_set
, const RTLIL::SigSpec
&sig_clr
,
2666 RTLIL::SigSpec sig_d
, const RTLIL::SigSpec
&sig_q
, bool en_polarity
, bool set_polarity
, bool clr_polarity
, const std::string
&src
)
2668 RTLIL::Cell
*cell
= addCell(name
, ID($dlatchsr
));
2669 cell
->parameters
[ID::EN_POLARITY
] = en_polarity
;
2670 cell
->parameters
[ID::SET_POLARITY
] = set_polarity
;
2671 cell
->parameters
[ID::CLR_POLARITY
] = clr_polarity
;
2672 cell
->parameters
[ID::WIDTH
] = sig_q
.size();
2673 cell
->setPort(ID::EN
, sig_en
);
2674 cell
->setPort(ID::SET
, sig_set
);
2675 cell
->setPort(ID::CLR
, sig_clr
);
2676 cell
->setPort(ID::D
, sig_d
);
2677 cell
->setPort(ID::Q
, sig_q
);
2678 cell
->set_src_attribute(src
);
2682 RTLIL::Cell
* RTLIL::Module::addSrGate(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_set
, const RTLIL::SigSpec
&sig_clr
,
2683 const RTLIL::SigSpec
&sig_q
, bool set_polarity
, bool clr_polarity
, const std::string
&src
)
2685 RTLIL::Cell
*cell
= addCell(name
, stringf("$_SR_%c%c_", set_polarity
? 'P' : 'N', clr_polarity
? 'P' : 'N'));
2686 cell
->setPort(ID::S
, sig_set
);
2687 cell
->setPort(ID::R
, sig_clr
);
2688 cell
->setPort(ID::Q
, sig_q
);
2689 cell
->set_src_attribute(src
);
2693 RTLIL::Cell
* RTLIL::Module::addFfGate(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_d
, const RTLIL::SigSpec
&sig_q
, const std::string
&src
)
2695 RTLIL::Cell
*cell
= addCell(name
, ID($_FF_
));
2696 cell
->setPort(ID::D
, sig_d
);
2697 cell
->setPort(ID::Q
, sig_q
);
2698 cell
->set_src_attribute(src
);
2702 RTLIL::Cell
* RTLIL::Module::addDffGate(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_clk
, const RTLIL::SigSpec
&sig_d
, const RTLIL::SigSpec
&sig_q
, bool clk_polarity
, const std::string
&src
)
2704 RTLIL::Cell
*cell
= addCell(name
, stringf("$_DFF_%c_", clk_polarity
? 'P' : 'N'));
2705 cell
->setPort(ID::C
, sig_clk
);
2706 cell
->setPort(ID::D
, sig_d
);
2707 cell
->setPort(ID::Q
, sig_q
);
2708 cell
->set_src_attribute(src
);
2712 RTLIL::Cell
* RTLIL::Module::addDffeGate(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_clk
, const RTLIL::SigSpec
&sig_en
, const RTLIL::SigSpec
&sig_d
, const RTLIL::SigSpec
&sig_q
, bool clk_polarity
, bool en_polarity
, const std::string
&src
)
2714 RTLIL::Cell
*cell
= addCell(name
, stringf("$_DFFE_%c%c_", clk_polarity
? 'P' : 'N', en_polarity
? 'P' : 'N'));
2715 cell
->setPort(ID::C
, sig_clk
);
2716 cell
->setPort(ID::E
, sig_en
);
2717 cell
->setPort(ID::D
, sig_d
);
2718 cell
->setPort(ID::Q
, sig_q
);
2719 cell
->set_src_attribute(src
);
2723 RTLIL::Cell
* RTLIL::Module::addDffsrGate(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_clk
, const RTLIL::SigSpec
&sig_set
, const RTLIL::SigSpec
&sig_clr
,
2724 RTLIL::SigSpec sig_d
, const RTLIL::SigSpec
&sig_q
, bool clk_polarity
, bool set_polarity
, bool clr_polarity
, const std::string
&src
)
2726 RTLIL::Cell
*cell
= addCell(name
, stringf("$_DFFSR_%c%c%c_", clk_polarity
? 'P' : 'N', set_polarity
? 'P' : 'N', clr_polarity
? 'P' : 'N'));
2727 cell
->setPort(ID::C
, sig_clk
);
2728 cell
->setPort(ID::S
, sig_set
);
2729 cell
->setPort(ID::R
, sig_clr
);
2730 cell
->setPort(ID::D
, sig_d
);
2731 cell
->setPort(ID::Q
, sig_q
);
2732 cell
->set_src_attribute(src
);
2736 RTLIL::Cell
* RTLIL::Module::addDffsreGate(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_clk
, const RTLIL::SigSpec
&sig_en
, const RTLIL::SigSpec
&sig_set
, const RTLIL::SigSpec
&sig_clr
,
2737 RTLIL::SigSpec sig_d
, const RTLIL::SigSpec
&sig_q
, bool clk_polarity
, bool en_polarity
, bool set_polarity
, bool clr_polarity
, const std::string
&src
)
2739 RTLIL::Cell
*cell
= addCell(name
, stringf("$_DFFSRE_%c%c%c%c_", clk_polarity
? 'P' : 'N', set_polarity
? 'P' : 'N', clr_polarity
? 'P' : 'N', en_polarity
? 'P' : 'N'));
2740 cell
->setPort(ID::C
, sig_clk
);
2741 cell
->setPort(ID::S
, sig_set
);
2742 cell
->setPort(ID::R
, sig_clr
);
2743 cell
->setPort(ID::E
, sig_en
);
2744 cell
->setPort(ID::D
, sig_d
);
2745 cell
->setPort(ID::Q
, sig_q
);
2746 cell
->set_src_attribute(src
);
2750 RTLIL::Cell
* RTLIL::Module::addAdffGate(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_clk
, const RTLIL::SigSpec
&sig_arst
, const RTLIL::SigSpec
&sig_d
, const RTLIL::SigSpec
&sig_q
,
2751 bool arst_value
, bool clk_polarity
, bool arst_polarity
, const std::string
&src
)
2753 RTLIL::Cell
*cell
= addCell(name
, stringf("$_DFF_%c%c%c_", clk_polarity
? 'P' : 'N', arst_polarity
? 'P' : 'N', arst_value
? '1' : '0'));
2754 cell
->setPort(ID::C
, sig_clk
);
2755 cell
->setPort(ID::R
, sig_arst
);
2756 cell
->setPort(ID::D
, sig_d
);
2757 cell
->setPort(ID::Q
, sig_q
);
2758 cell
->set_src_attribute(src
);
2762 RTLIL::Cell
* RTLIL::Module::addAdffeGate(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_clk
, const RTLIL::SigSpec
&sig_en
, const RTLIL::SigSpec
&sig_arst
, const RTLIL::SigSpec
&sig_d
, const RTLIL::SigSpec
&sig_q
,
2763 bool arst_value
, bool clk_polarity
, bool en_polarity
, bool arst_polarity
, const std::string
&src
)
2765 RTLIL::Cell
*cell
= addCell(name
, stringf("$_DFFE_%c%c%c%c_", clk_polarity
? 'P' : 'N', arst_polarity
? 'P' : 'N', arst_value
? '1' : '0', en_polarity
? 'P' : 'N'));
2766 cell
->setPort(ID::C
, sig_clk
);
2767 cell
->setPort(ID::R
, sig_arst
);
2768 cell
->setPort(ID::E
, sig_en
);
2769 cell
->setPort(ID::D
, sig_d
);
2770 cell
->setPort(ID::Q
, sig_q
);
2771 cell
->set_src_attribute(src
);
2775 RTLIL::Cell
* RTLIL::Module::addSdffGate(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_clk
, const RTLIL::SigSpec
&sig_srst
, const RTLIL::SigSpec
&sig_d
, const RTLIL::SigSpec
&sig_q
,
2776 bool srst_value
, bool clk_polarity
, bool srst_polarity
, const std::string
&src
)
2778 RTLIL::Cell
*cell
= addCell(name
, stringf("$_SDFF_%c%c%c_", clk_polarity
? 'P' : 'N', srst_polarity
? 'P' : 'N', srst_value
? '1' : '0'));
2779 cell
->setPort(ID::C
, sig_clk
);
2780 cell
->setPort(ID::R
, sig_srst
);
2781 cell
->setPort(ID::D
, sig_d
);
2782 cell
->setPort(ID::Q
, sig_q
);
2783 cell
->set_src_attribute(src
);
2787 RTLIL::Cell
* RTLIL::Module::addSdffeGate(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_clk
, const RTLIL::SigSpec
&sig_en
, const RTLIL::SigSpec
&sig_srst
, const RTLIL::SigSpec
&sig_d
, const RTLIL::SigSpec
&sig_q
,
2788 bool srst_value
, bool clk_polarity
, bool en_polarity
, bool srst_polarity
, const std::string
&src
)
2790 RTLIL::Cell
*cell
= addCell(name
, stringf("$_SDFFE_%c%c%c%c_", clk_polarity
? 'P' : 'N', srst_polarity
? 'P' : 'N', srst_value
? '1' : '0', en_polarity
? 'P' : 'N'));
2791 cell
->setPort(ID::C
, sig_clk
);
2792 cell
->setPort(ID::R
, sig_srst
);
2793 cell
->setPort(ID::E
, sig_en
);
2794 cell
->setPort(ID::D
, sig_d
);
2795 cell
->setPort(ID::Q
, sig_q
);
2796 cell
->set_src_attribute(src
);
2800 RTLIL::Cell
* RTLIL::Module::addSdffceGate(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_clk
, const RTLIL::SigSpec
&sig_en
, const RTLIL::SigSpec
&sig_srst
, const RTLIL::SigSpec
&sig_d
, const RTLIL::SigSpec
&sig_q
,
2801 bool srst_value
, bool clk_polarity
, bool en_polarity
, bool srst_polarity
, const std::string
&src
)
2803 RTLIL::Cell
*cell
= addCell(name
, stringf("$_SDFFCE_%c%c%c%c_", clk_polarity
? 'P' : 'N', srst_polarity
? 'P' : 'N', srst_value
? '1' : '0', en_polarity
? 'P' : 'N'));
2804 cell
->setPort(ID::C
, sig_clk
);
2805 cell
->setPort(ID::R
, sig_srst
);
2806 cell
->setPort(ID::E
, sig_en
);
2807 cell
->setPort(ID::D
, sig_d
);
2808 cell
->setPort(ID::Q
, sig_q
);
2809 cell
->set_src_attribute(src
);
2813 RTLIL::Cell
* RTLIL::Module::addDlatchGate(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_en
, const RTLIL::SigSpec
&sig_d
, const RTLIL::SigSpec
&sig_q
, bool en_polarity
, const std::string
&src
)
2815 RTLIL::Cell
*cell
= addCell(name
, stringf("$_DLATCH_%c_", en_polarity
? 'P' : 'N'));
2816 cell
->setPort(ID::E
, sig_en
);
2817 cell
->setPort(ID::D
, sig_d
);
2818 cell
->setPort(ID::Q
, sig_q
);
2819 cell
->set_src_attribute(src
);
2823 RTLIL::Cell
* RTLIL::Module::addAdlatchGate(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_en
, const RTLIL::SigSpec
&sig_arst
, const RTLIL::SigSpec
&sig_d
, const RTLIL::SigSpec
&sig_q
,
2824 bool arst_value
, bool en_polarity
, bool arst_polarity
, const std::string
&src
)
2826 RTLIL::Cell
*cell
= addCell(name
, stringf("$_DLATCH_%c%c%c_", en_polarity
? 'P' : 'N', arst_polarity
? 'P' : 'N', arst_value
? '1' : '0'));
2827 cell
->setPort(ID::E
, sig_en
);
2828 cell
->setPort(ID::R
, sig_arst
);
2829 cell
->setPort(ID::D
, sig_d
);
2830 cell
->setPort(ID::Q
, sig_q
);
2831 cell
->set_src_attribute(src
);
2835 RTLIL::Cell
* RTLIL::Module::addDlatchsrGate(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_en
, const RTLIL::SigSpec
&sig_set
, const RTLIL::SigSpec
&sig_clr
,
2836 RTLIL::SigSpec sig_d
, const RTLIL::SigSpec
&sig_q
, bool en_polarity
, bool set_polarity
, bool clr_polarity
, const std::string
&src
)
2838 RTLIL::Cell
*cell
= addCell(name
, stringf("$_DLATCHSR_%c%c%c_", en_polarity
? 'P' : 'N', set_polarity
? 'P' : 'N', clr_polarity
? 'P' : 'N'));
2839 cell
->setPort(ID::E
, sig_en
);
2840 cell
->setPort(ID::S
, sig_set
);
2841 cell
->setPort(ID::R
, sig_clr
);
2842 cell
->setPort(ID::D
, sig_d
);
2843 cell
->setPort(ID::Q
, sig_q
);
2844 cell
->set_src_attribute(src
);
2848 RTLIL::SigSpec
RTLIL::Module::Anyconst(RTLIL::IdString name
, int width
, const std::string
&src
)
2850 RTLIL::SigSpec sig
= addWire(NEW_ID
, width
);
2851 Cell
*cell
= addCell(name
, ID($anyconst
));
2852 cell
->setParam(ID::WIDTH
, width
);
2853 cell
->setPort(ID::Y
, sig
);
2854 cell
->set_src_attribute(src
);
2858 RTLIL::SigSpec
RTLIL::Module::Anyseq(RTLIL::IdString name
, int width
, const std::string
&src
)
2860 RTLIL::SigSpec sig
= addWire(NEW_ID
, width
);
2861 Cell
*cell
= addCell(name
, ID($anyseq
));
2862 cell
->setParam(ID::WIDTH
, width
);
2863 cell
->setPort(ID::Y
, sig
);
2864 cell
->set_src_attribute(src
);
2868 RTLIL::SigSpec
RTLIL::Module::Allconst(RTLIL::IdString name
, int width
, const std::string
&src
)
2870 RTLIL::SigSpec sig
= addWire(NEW_ID
, width
);
2871 Cell
*cell
= addCell(name
, ID($allconst
));
2872 cell
->setParam(ID::WIDTH
, width
);
2873 cell
->setPort(ID::Y
, sig
);
2874 cell
->set_src_attribute(src
);
2878 RTLIL::SigSpec
RTLIL::Module::Allseq(RTLIL::IdString name
, int width
, const std::string
&src
)
2880 RTLIL::SigSpec sig
= addWire(NEW_ID
, width
);
2881 Cell
*cell
= addCell(name
, ID($allseq
));
2882 cell
->setParam(ID::WIDTH
, width
);
2883 cell
->setPort(ID::Y
, sig
);
2884 cell
->set_src_attribute(src
);
2888 RTLIL::SigSpec
RTLIL::Module::Initstate(RTLIL::IdString name
, const std::string
&src
)
2890 RTLIL::SigSpec sig
= addWire(NEW_ID
);
2891 Cell
*cell
= addCell(name
, ID($initstate
));
2892 cell
->setPort(ID::Y
, sig
);
2893 cell
->set_src_attribute(src
);
2899 static unsigned int hashidx_count
= 123456789;
2900 hashidx_count
= mkhash_xorshift(hashidx_count
);
2901 hashidx_
= hashidx_count
;
2908 port_output
= false;
2913 RTLIL::Wire::get_all_wires()->insert(std::pair
<unsigned int, RTLIL::Wire
*>(hashidx_
, this));
2917 RTLIL::Wire::~Wire()
2920 RTLIL::Wire::get_all_wires()->erase(hashidx_
);
2925 static std::map
<unsigned int, RTLIL::Wire
*> all_wires
;
2926 std::map
<unsigned int, RTLIL::Wire
*> *RTLIL::Wire::get_all_wires(void)
2932 RTLIL::Memory::Memory()
2934 static unsigned int hashidx_count
= 123456789;
2935 hashidx_count
= mkhash_xorshift(hashidx_count
);
2936 hashidx_
= hashidx_count
;
2942 RTLIL::Memory::get_all_memorys()->insert(std::pair
<unsigned int, RTLIL::Memory
*>(hashidx_
, this));
2946 RTLIL::Process::Process() : module(nullptr)
2948 static unsigned int hashidx_count
= 123456789;
2949 hashidx_count
= mkhash_xorshift(hashidx_count
);
2950 hashidx_
= hashidx_count
;
2953 RTLIL::Cell::Cell() : module(nullptr)
2955 static unsigned int hashidx_count
= 123456789;
2956 hashidx_count
= mkhash_xorshift(hashidx_count
);
2957 hashidx_
= hashidx_count
;
2959 // log("#memtrace# %p\n", this);
2963 RTLIL::Cell::get_all_cells()->insert(std::pair
<unsigned int, RTLIL::Cell
*>(hashidx_
, this));
2967 RTLIL::Cell::~Cell()
2970 RTLIL::Cell::get_all_cells()->erase(hashidx_
);
2975 static std::map
<unsigned int, RTLIL::Cell
*> all_cells
;
2976 std::map
<unsigned int, RTLIL::Cell
*> *RTLIL::Cell::get_all_cells(void)
2982 bool RTLIL::Cell::hasPort(RTLIL::IdString portname
) const
2984 return connections_
.count(portname
) != 0;
2987 void RTLIL::Cell::unsetPort(RTLIL::IdString portname
)
2989 RTLIL::SigSpec signal
;
2990 auto conn_it
= connections_
.find(portname
);
2992 if (conn_it
!= connections_
.end())
2994 for (auto mon
: module
->monitors
)
2995 mon
->notify_connect(this, conn_it
->first
, conn_it
->second
, signal
);
2998 for (auto mon
: module
->design
->monitors
)
2999 mon
->notify_connect(this, conn_it
->first
, conn_it
->second
, signal
);
3002 log("#X# Unconnect %s.%s.%s\n", log_id(this->module
), log_id(this), log_id(portname
));
3003 log_backtrace("-X- ", yosys_xtrace
-1);
3006 connections_
.erase(conn_it
);
3010 void RTLIL::Cell::setPort(RTLIL::IdString portname
, RTLIL::SigSpec signal
)
3012 auto r
= connections_
.insert(portname
);
3013 auto conn_it
= r
.first
;
3014 if (!r
.second
&& conn_it
->second
== signal
)
3017 for (auto mon
: module
->monitors
)
3018 mon
->notify_connect(this, conn_it
->first
, conn_it
->second
, signal
);
3021 for (auto mon
: module
->design
->monitors
)
3022 mon
->notify_connect(this, conn_it
->first
, conn_it
->second
, signal
);
3025 log("#X# Connect %s.%s.%s = %s (%d)\n", log_id(this->module
), log_id(this), log_id(portname
), log_signal(signal
), GetSize(signal
));
3026 log_backtrace("-X- ", yosys_xtrace
-1);
3029 conn_it
->second
= std::move(signal
);
3032 const RTLIL::SigSpec
&RTLIL::Cell::getPort(RTLIL::IdString portname
) const
3034 return connections_
.at(portname
);
3037 const dict
<RTLIL::IdString
, RTLIL::SigSpec
> &RTLIL::Cell::connections() const
3039 return connections_
;
3042 bool RTLIL::Cell::known() const
3044 if (yosys_celltypes
.cell_known(type
))
3046 if (module
&& module
->design
&& module
->design
->module(type
))
3051 bool RTLIL::Cell::input(RTLIL::IdString portname
) const
3053 if (yosys_celltypes
.cell_known(type
))
3054 return yosys_celltypes
.cell_input(type
, portname
);
3055 if (module
&& module
->design
) {
3056 RTLIL::Module
*m
= module
->design
->module(type
);
3057 RTLIL::Wire
*w
= m
? m
->wire(portname
) : nullptr;
3058 return w
&& w
->port_input
;
3063 bool RTLIL::Cell::output(RTLIL::IdString portname
) const
3065 if (yosys_celltypes
.cell_known(type
))
3066 return yosys_celltypes
.cell_output(type
, portname
);
3067 if (module
&& module
->design
) {
3068 RTLIL::Module
*m
= module
->design
->module(type
);
3069 RTLIL::Wire
*w
= m
? m
->wire(portname
) : nullptr;
3070 return w
&& w
->port_output
;
3075 bool RTLIL::Cell::hasParam(RTLIL::IdString paramname
) const
3077 return parameters
.count(paramname
) != 0;
3080 void RTLIL::Cell::unsetParam(RTLIL::IdString paramname
)
3082 parameters
.erase(paramname
);
3085 void RTLIL::Cell::setParam(RTLIL::IdString paramname
, RTLIL::Const value
)
3087 parameters
[paramname
] = std::move(value
);
3090 const RTLIL::Const
&RTLIL::Cell::getParam(RTLIL::IdString paramname
) const
3092 const auto &it
= parameters
.find(paramname
);
3093 if (it
!= parameters
.end())
3095 if (module
&& module
->design
) {
3096 RTLIL::Module
*m
= module
->design
->module(type
);
3098 return m
->parameter_default_values
.at(paramname
);
3100 throw std::out_of_range("Cell::getParam()");
3103 void RTLIL::Cell::sort()
3105 connections_
.sort(sort_by_id_str());
3106 parameters
.sort(sort_by_id_str());
3107 attributes
.sort(sort_by_id_str());
3110 void RTLIL::Cell::check()
3113 InternalCellChecker
checker(NULL
, this);
3118 void RTLIL::Cell::fixup_parameters(bool set_a_signed
, bool set_b_signed
)
3120 if (!type
.begins_with("$") || type
.begins_with("$_") || type
.begins_with("$paramod") || type
.begins_with("$fmcombine") ||
3121 type
.begins_with("$verific$") || type
.begins_with("$array:") || type
.begins_with("$extern:"))
3124 if (type
== ID($mux
) || type
== ID($pmux
)) {
3125 parameters
[ID::WIDTH
] = GetSize(connections_
[ID::Y
]);
3126 if (type
== ID($pmux
))
3127 parameters
[ID::S_WIDTH
] = GetSize(connections_
[ID::S
]);
3132 if (type
== ID($lut
) || type
== ID($sop
)) {
3133 parameters
[ID::WIDTH
] = GetSize(connections_
[ID::A
]);
3137 if (type
== ID($fa
)) {
3138 parameters
[ID::WIDTH
] = GetSize(connections_
[ID::Y
]);
3142 if (type
== ID($lcu
)) {
3143 parameters
[ID::WIDTH
] = GetSize(connections_
[ID::CO
]);
3147 bool signedness_ab
= !type
.in(ID($slice
), ID($concat
), ID($macc
));
3149 if (connections_
.count(ID::A
)) {
3150 if (signedness_ab
) {
3152 parameters
[ID::A_SIGNED
] = true;
3153 else if (parameters
.count(ID::A_SIGNED
) == 0)
3154 parameters
[ID::A_SIGNED
] = false;
3156 parameters
[ID::A_WIDTH
] = GetSize(connections_
[ID::A
]);
3159 if (connections_
.count(ID::B
)) {
3160 if (signedness_ab
) {
3162 parameters
[ID::B_SIGNED
] = true;
3163 else if (parameters
.count(ID::B_SIGNED
) == 0)
3164 parameters
[ID::B_SIGNED
] = false;
3166 parameters
[ID::B_WIDTH
] = GetSize(connections_
[ID::B
]);
3169 if (connections_
.count(ID::Y
))
3170 parameters
[ID::Y_WIDTH
] = GetSize(connections_
[ID::Y
]);
3172 if (connections_
.count(ID::Q
))
3173 parameters
[ID::WIDTH
] = GetSize(connections_
[ID::Q
]);
3178 bool RTLIL::Cell::has_memid() const
3180 return type
.in(ID($memwr
), ID($memrd
), ID($meminit
));
3183 bool RTLIL::Cell::is_mem_cell() const
3185 return type
== ID($mem
) || has_memid();
3188 RTLIL::SigChunk::SigChunk()
3195 RTLIL::SigChunk::SigChunk(const RTLIL::Const
&value
)
3199 width
= GetSize(data
);
3203 RTLIL::SigChunk::SigChunk(RTLIL::Wire
*wire
)
3205 log_assert(wire
!= nullptr);
3207 this->width
= wire
->width
;
3211 RTLIL::SigChunk::SigChunk(RTLIL::Wire
*wire
, int offset
, int width
)
3213 log_assert(wire
!= nullptr);
3215 this->width
= width
;
3216 this->offset
= offset
;
3219 RTLIL::SigChunk::SigChunk(const std::string
&str
)
3222 data
= RTLIL::Const(str
).bits
;
3223 width
= GetSize(data
);
3227 RTLIL::SigChunk::SigChunk(int val
, int width
)
3230 data
= RTLIL::Const(val
, width
).bits
;
3231 this->width
= GetSize(data
);
3235 RTLIL::SigChunk::SigChunk(RTLIL::State bit
, int width
)
3238 data
= RTLIL::Const(bit
, width
).bits
;
3239 this->width
= GetSize(data
);
3243 RTLIL::SigChunk::SigChunk(const RTLIL::SigBit
&bit
)
3248 data
= RTLIL::Const(bit
.data
).bits
;
3250 offset
= bit
.offset
;
3254 RTLIL::SigChunk::SigChunk(const RTLIL::SigChunk
&sigchunk
)
3259 RTLIL::SigChunk
RTLIL::SigChunk::extract(int offset
, int length
) const
3261 RTLIL::SigChunk ret
;
3264 ret
.offset
= this->offset
+ offset
;
3267 for (int i
= 0; i
< length
; i
++)
3268 ret
.data
.push_back(data
[offset
+i
]);
3274 bool RTLIL::SigChunk::operator <(const RTLIL::SigChunk
&other
) const
3276 if (wire
&& other
.wire
)
3277 if (wire
->name
!= other
.wire
->name
)
3278 return wire
->name
< other
.wire
->name
;
3280 if (wire
!= other
.wire
)
3281 return wire
< other
.wire
;
3283 if (offset
!= other
.offset
)
3284 return offset
< other
.offset
;
3286 if (width
!= other
.width
)
3287 return width
< other
.width
;
3289 return data
< other
.data
;
3292 bool RTLIL::SigChunk::operator ==(const RTLIL::SigChunk
&other
) const
3294 return wire
== other
.wire
&& width
== other
.width
&& offset
== other
.offset
&& data
== other
.data
;
3297 bool RTLIL::SigChunk::operator !=(const RTLIL::SigChunk
&other
) const
3304 RTLIL::SigSpec::SigSpec()
3310 RTLIL::SigSpec::SigSpec(const RTLIL::SigSpec
&other
)
3315 RTLIL::SigSpec::SigSpec(std::initializer_list
<RTLIL::SigSpec
> parts
)
3317 cover("kernel.rtlil.sigspec.init.list");
3322 log_assert(parts
.size() > 0);
3323 auto ie
= parts
.begin();
3324 auto it
= ie
+ parts
.size() - 1;
3329 RTLIL::SigSpec
&RTLIL::SigSpec::operator=(const RTLIL::SigSpec
&other
)
3331 cover("kernel.rtlil.sigspec.assign");
3333 width_
= other
.width_
;
3334 hash_
= other
.hash_
;
3335 chunks_
= other
.chunks_
;
3336 bits_
= other
.bits_
;
3340 RTLIL::SigSpec::SigSpec(const RTLIL::Const
&value
)
3342 cover("kernel.rtlil.sigspec.init.const");
3344 if (GetSize(value
) != 0) {
3345 chunks_
.emplace_back(value
);
3346 width_
= chunks_
.back().width
;
3354 RTLIL::SigSpec::SigSpec(const RTLIL::SigChunk
&chunk
)
3356 cover("kernel.rtlil.sigspec.init.chunk");
3358 if (chunk
.width
!= 0) {
3359 chunks_
.emplace_back(chunk
);
3360 width_
= chunks_
.back().width
;
3368 RTLIL::SigSpec::SigSpec(RTLIL::Wire
*wire
)
3370 cover("kernel.rtlil.sigspec.init.wire");
3372 if (wire
->width
!= 0) {
3373 chunks_
.emplace_back(wire
);
3374 width_
= chunks_
.back().width
;
3382 RTLIL::SigSpec::SigSpec(RTLIL::Wire
*wire
, int offset
, int width
)
3384 cover("kernel.rtlil.sigspec.init.wire_part");
3387 chunks_
.emplace_back(wire
, offset
, width
);
3388 width_
= chunks_
.back().width
;
3396 RTLIL::SigSpec::SigSpec(const std::string
&str
)
3398 cover("kernel.rtlil.sigspec.init.str");
3400 if (str
.size() != 0) {
3401 chunks_
.emplace_back(str
);
3402 width_
= chunks_
.back().width
;
3410 RTLIL::SigSpec::SigSpec(int val
, int width
)
3412 cover("kernel.rtlil.sigspec.init.int");
3415 chunks_
.emplace_back(val
, width
);
3421 RTLIL::SigSpec::SigSpec(RTLIL::State bit
, int width
)
3423 cover("kernel.rtlil.sigspec.init.state");
3426 chunks_
.emplace_back(bit
, width
);
3432 RTLIL::SigSpec::SigSpec(const RTLIL::SigBit
&bit
, int width
)
3434 cover("kernel.rtlil.sigspec.init.bit");
3437 if (bit
.wire
== NULL
)
3438 chunks_
.emplace_back(bit
.data
, width
);
3440 for (int i
= 0; i
< width
; i
++)
3441 chunks_
.push_back(bit
);
3448 RTLIL::SigSpec::SigSpec(const std::vector
<RTLIL::SigChunk
> &chunks
)
3450 cover("kernel.rtlil.sigspec.init.stdvec_chunks");
3454 for (const auto &c
: chunks
)
3459 RTLIL::SigSpec::SigSpec(const std::vector
<RTLIL::SigBit
> &bits
)
3461 cover("kernel.rtlil.sigspec.init.stdvec_bits");
3465 for (const auto &bit
: bits
)
3470 RTLIL::SigSpec::SigSpec(const pool
<RTLIL::SigBit
> &bits
)
3472 cover("kernel.rtlil.sigspec.init.pool_bits");
3476 for (const auto &bit
: bits
)
3481 RTLIL::SigSpec::SigSpec(const std::set
<RTLIL::SigBit
> &bits
)
3483 cover("kernel.rtlil.sigspec.init.stdset_bits");
3487 for (const auto &bit
: bits
)
3492 RTLIL::SigSpec::SigSpec(bool bit
)
3494 cover("kernel.rtlil.sigspec.init.bool");
3498 append(SigBit(bit
));
3502 void RTLIL::SigSpec::pack() const
3504 RTLIL::SigSpec
*that
= (RTLIL::SigSpec
*)this;
3506 if (that
->bits_
.empty())
3509 cover("kernel.rtlil.sigspec.convert.pack");
3510 log_assert(that
->chunks_
.empty());
3512 std::vector
<RTLIL::SigBit
> old_bits
;
3513 old_bits
.swap(that
->bits_
);
3515 RTLIL::SigChunk
*last
= NULL
;
3516 int last_end_offset
= 0;
3518 for (auto &bit
: old_bits
) {
3519 if (last
&& bit
.wire
== last
->wire
) {
3520 if (bit
.wire
== NULL
) {
3521 last
->data
.push_back(bit
.data
);
3524 } else if (last_end_offset
== bit
.offset
) {
3530 that
->chunks_
.push_back(bit
);
3531 last
= &that
->chunks_
.back();
3532 last_end_offset
= bit
.offset
+ 1;
3538 void RTLIL::SigSpec::unpack() const
3540 RTLIL::SigSpec
*that
= (RTLIL::SigSpec
*)this;
3542 if (that
->chunks_
.empty())
3545 cover("kernel.rtlil.sigspec.convert.unpack");
3546 log_assert(that
->bits_
.empty());
3548 that
->bits_
.reserve(that
->width_
);
3549 for (auto &c
: that
->chunks_
)
3550 for (int i
= 0; i
< c
.width
; i
++)
3551 that
->bits_
.emplace_back(c
, i
);
3553 that
->chunks_
.clear();
3557 void RTLIL::SigSpec::updhash() const
3559 RTLIL::SigSpec
*that
= (RTLIL::SigSpec
*)this;
3561 if (that
->hash_
!= 0)
3564 cover("kernel.rtlil.sigspec.hash");
3567 that
->hash_
= mkhash_init
;
3568 for (auto &c
: that
->chunks_
)
3569 if (c
.wire
== NULL
) {
3570 for (auto &v
: c
.data
)
3571 that
->hash_
= mkhash(that
->hash_
, v
);
3573 that
->hash_
= mkhash(that
->hash_
, c
.wire
->name
.index_
);
3574 that
->hash_
= mkhash(that
->hash_
, c
.offset
);
3575 that
->hash_
= mkhash(that
->hash_
, c
.width
);
3578 if (that
->hash_
== 0)
3582 void RTLIL::SigSpec::sort()
3585 cover("kernel.rtlil.sigspec.sort");
3586 std::sort(bits_
.begin(), bits_
.end());
3589 void RTLIL::SigSpec::sort_and_unify()
3592 cover("kernel.rtlil.sigspec.sort_and_unify");
3594 // A copy of the bits vector is used to prevent duplicating the logic from
3595 // SigSpec::SigSpec(std::vector<SigBit>). This incurrs an extra copy but
3596 // that isn't showing up as significant in profiles.
3597 std::vector
<SigBit
> unique_bits
= bits_
;
3598 std::sort(unique_bits
.begin(), unique_bits
.end());
3599 auto last
= std::unique(unique_bits
.begin(), unique_bits
.end());
3600 unique_bits
.erase(last
, unique_bits
.end());
3602 *this = unique_bits
;
3605 void RTLIL::SigSpec::replace(const RTLIL::SigSpec
&pattern
, const RTLIL::SigSpec
&with
)
3607 replace(pattern
, with
, this);
3610 void RTLIL::SigSpec::replace(const RTLIL::SigSpec
&pattern
, const RTLIL::SigSpec
&with
, RTLIL::SigSpec
*other
) const
3612 log_assert(other
!= NULL
);
3613 log_assert(width_
== other
->width_
);
3614 log_assert(pattern
.width_
== with
.width_
);
3621 for (int i
= 0; i
< GetSize(pattern
.bits_
); i
++) {
3622 if (pattern
.bits_
[i
].wire
!= NULL
) {
3623 for (int j
= 0; j
< GetSize(bits_
); j
++) {
3624 if (bits_
[j
] == pattern
.bits_
[i
]) {
3625 other
->bits_
[j
] = with
.bits_
[i
];
3634 void RTLIL::SigSpec::replace(const dict
<RTLIL::SigBit
, RTLIL::SigBit
> &rules
)
3636 replace(rules
, this);
3639 void RTLIL::SigSpec::replace(const dict
<RTLIL::SigBit
, RTLIL::SigBit
> &rules
, RTLIL::SigSpec
*other
) const
3641 cover("kernel.rtlil.sigspec.replace_dict");
3643 log_assert(other
!= NULL
);
3644 log_assert(width_
== other
->width_
);
3646 if (rules
.empty()) return;
3650 for (int i
= 0; i
< GetSize(bits_
); i
++) {
3651 auto it
= rules
.find(bits_
[i
]);
3652 if (it
!= rules
.end())
3653 other
->bits_
[i
] = it
->second
;
3659 void RTLIL::SigSpec::replace(const std::map
<RTLIL::SigBit
, RTLIL::SigBit
> &rules
)
3661 replace(rules
, this);
3664 void RTLIL::SigSpec::replace(const std::map
<RTLIL::SigBit
, RTLIL::SigBit
> &rules
, RTLIL::SigSpec
*other
) const
3666 cover("kernel.rtlil.sigspec.replace_map");
3668 log_assert(other
!= NULL
);
3669 log_assert(width_
== other
->width_
);
3671 if (rules
.empty()) return;
3675 for (int i
= 0; i
< GetSize(bits_
); i
++) {
3676 auto it
= rules
.find(bits_
[i
]);
3677 if (it
!= rules
.end())
3678 other
->bits_
[i
] = it
->second
;
3684 void RTLIL::SigSpec::remove(const RTLIL::SigSpec
&pattern
)
3686 remove2(pattern
, NULL
);
3689 void RTLIL::SigSpec::remove(const RTLIL::SigSpec
&pattern
, RTLIL::SigSpec
*other
) const
3691 RTLIL::SigSpec tmp
= *this;
3692 tmp
.remove2(pattern
, other
);
3695 void RTLIL::SigSpec::remove2(const RTLIL::SigSpec
&pattern
, RTLIL::SigSpec
*other
)
3698 cover("kernel.rtlil.sigspec.remove_other");
3700 cover("kernel.rtlil.sigspec.remove");
3703 if (other
!= NULL
) {
3704 log_assert(width_
== other
->width_
);
3708 for (int i
= GetSize(bits_
) - 1; i
>= 0; i
--)
3710 if (bits_
[i
].wire
== NULL
) continue;
3712 for (auto &pattern_chunk
: pattern
.chunks())
3713 if (bits_
[i
].wire
== pattern_chunk
.wire
&&
3714 bits_
[i
].offset
>= pattern_chunk
.offset
&&
3715 bits_
[i
].offset
< pattern_chunk
.offset
+ pattern_chunk
.width
) {
3716 bits_
.erase(bits_
.begin() + i
);
3718 if (other
!= NULL
) {
3719 other
->bits_
.erase(other
->bits_
.begin() + i
);
3729 void RTLIL::SigSpec::remove(const pool
<RTLIL::SigBit
> &pattern
)
3731 remove2(pattern
, NULL
);
3734 void RTLIL::SigSpec::remove(const pool
<RTLIL::SigBit
> &pattern
, RTLIL::SigSpec
*other
) const
3736 RTLIL::SigSpec tmp
= *this;
3737 tmp
.remove2(pattern
, other
);
3740 void RTLIL::SigSpec::remove2(const pool
<RTLIL::SigBit
> &pattern
, RTLIL::SigSpec
*other
)
3743 cover("kernel.rtlil.sigspec.remove_other");
3745 cover("kernel.rtlil.sigspec.remove");
3749 if (other
!= NULL
) {
3750 log_assert(width_
== other
->width_
);
3754 for (int i
= GetSize(bits_
) - 1; i
>= 0; i
--) {
3755 if (bits_
[i
].wire
!= NULL
&& pattern
.count(bits_
[i
])) {
3756 bits_
.erase(bits_
.begin() + i
);
3758 if (other
!= NULL
) {
3759 other
->bits_
.erase(other
->bits_
.begin() + i
);
3768 void RTLIL::SigSpec::remove2(const std::set
<RTLIL::SigBit
> &pattern
, RTLIL::SigSpec
*other
)
3771 cover("kernel.rtlil.sigspec.remove_other");
3773 cover("kernel.rtlil.sigspec.remove");
3777 if (other
!= NULL
) {
3778 log_assert(width_
== other
->width_
);
3782 for (int i
= GetSize(bits_
) - 1; i
>= 0; i
--) {
3783 if (bits_
[i
].wire
!= NULL
&& pattern
.count(bits_
[i
])) {
3784 bits_
.erase(bits_
.begin() + i
);
3786 if (other
!= NULL
) {
3787 other
->bits_
.erase(other
->bits_
.begin() + i
);
3796 RTLIL::SigSpec
RTLIL::SigSpec::extract(const RTLIL::SigSpec
&pattern
, const RTLIL::SigSpec
*other
) const
3799 cover("kernel.rtlil.sigspec.extract_other");
3801 cover("kernel.rtlil.sigspec.extract");
3803 log_assert(other
== NULL
|| width_
== other
->width_
);
3806 std::vector
<RTLIL::SigBit
> bits_match
= to_sigbit_vector();
3808 for (auto& pattern_chunk
: pattern
.chunks()) {
3810 std::vector
<RTLIL::SigBit
> bits_other
= other
->to_sigbit_vector();
3811 for (int i
= 0; i
< width_
; i
++)
3812 if (bits_match
[i
].wire
&&
3813 bits_match
[i
].wire
== pattern_chunk
.wire
&&
3814 bits_match
[i
].offset
>= pattern_chunk
.offset
&&
3815 bits_match
[i
].offset
< pattern_chunk
.offset
+ pattern_chunk
.width
)
3816 ret
.append(bits_other
[i
]);
3818 for (int i
= 0; i
< width_
; i
++)
3819 if (bits_match
[i
].wire
&&
3820 bits_match
[i
].wire
== pattern_chunk
.wire
&&
3821 bits_match
[i
].offset
>= pattern_chunk
.offset
&&
3822 bits_match
[i
].offset
< pattern_chunk
.offset
+ pattern_chunk
.width
)
3823 ret
.append(bits_match
[i
]);
3831 RTLIL::SigSpec
RTLIL::SigSpec::extract(const pool
<RTLIL::SigBit
> &pattern
, const RTLIL::SigSpec
*other
) const
3834 cover("kernel.rtlil.sigspec.extract_other");
3836 cover("kernel.rtlil.sigspec.extract");
3838 log_assert(other
== NULL
|| width_
== other
->width_
);
3840 std::vector
<RTLIL::SigBit
> bits_match
= to_sigbit_vector();
3844 std::vector
<RTLIL::SigBit
> bits_other
= other
->to_sigbit_vector();
3845 for (int i
= 0; i
< width_
; i
++)
3846 if (bits_match
[i
].wire
&& pattern
.count(bits_match
[i
]))
3847 ret
.append(bits_other
[i
]);
3849 for (int i
= 0; i
< width_
; i
++)
3850 if (bits_match
[i
].wire
&& pattern
.count(bits_match
[i
]))
3851 ret
.append(bits_match
[i
]);
3858 void RTLIL::SigSpec::replace(int offset
, const RTLIL::SigSpec
&with
)
3860 cover("kernel.rtlil.sigspec.replace_pos");
3865 log_assert(offset
>= 0);
3866 log_assert(with
.width_
>= 0);
3867 log_assert(offset
+with
.width_
<= width_
);
3869 for (int i
= 0; i
< with
.width_
; i
++)
3870 bits_
.at(offset
+ i
) = with
.bits_
.at(i
);
3875 void RTLIL::SigSpec::remove_const()
3879 cover("kernel.rtlil.sigspec.remove_const.packed");
3881 std::vector
<RTLIL::SigChunk
> new_chunks
;
3882 new_chunks
.reserve(GetSize(chunks_
));
3885 for (auto &chunk
: chunks_
)
3886 if (chunk
.wire
!= NULL
) {
3887 if (!new_chunks
.empty() &&
3888 new_chunks
.back().wire
== chunk
.wire
&&
3889 new_chunks
.back().offset
+ new_chunks
.back().width
== chunk
.offset
) {
3890 new_chunks
.back().width
+= chunk
.width
;
3892 new_chunks
.push_back(chunk
);
3894 width_
+= chunk
.width
;
3897 chunks_
.swap(new_chunks
);
3901 cover("kernel.rtlil.sigspec.remove_const.unpacked");
3903 std::vector
<RTLIL::SigBit
> new_bits
;
3904 new_bits
.reserve(width_
);
3906 for (auto &bit
: bits_
)
3907 if (bit
.wire
!= NULL
)
3908 new_bits
.push_back(bit
);
3910 bits_
.swap(new_bits
);
3911 width_
= bits_
.size();
3917 void RTLIL::SigSpec::remove(int offset
, int length
)
3919 cover("kernel.rtlil.sigspec.remove_pos");
3923 log_assert(offset
>= 0);
3924 log_assert(length
>= 0);
3925 log_assert(offset
+ length
<= width_
);
3927 bits_
.erase(bits_
.begin() + offset
, bits_
.begin() + offset
+ length
);
3928 width_
= bits_
.size();
3933 RTLIL::SigSpec
RTLIL::SigSpec::extract(int offset
, int length
) const
3936 cover("kernel.rtlil.sigspec.extract_pos");
3937 return std::vector
<RTLIL::SigBit
>(bits_
.begin() + offset
, bits_
.begin() + offset
+ length
);
3940 void RTLIL::SigSpec::append(const RTLIL::SigSpec
&signal
)
3942 if (signal
.width_
== 0)
3950 cover("kernel.rtlil.sigspec.append");
3952 if (packed() != signal
.packed()) {
3958 for (auto &other_c
: signal
.chunks_
)
3960 auto &my_last_c
= chunks_
.back();
3961 if (my_last_c
.wire
== NULL
&& other_c
.wire
== NULL
) {
3962 auto &this_data
= my_last_c
.data
;
3963 auto &other_data
= other_c
.data
;
3964 this_data
.insert(this_data
.end(), other_data
.begin(), other_data
.end());
3965 my_last_c
.width
+= other_c
.width
;
3967 if (my_last_c
.wire
== other_c
.wire
&& my_last_c
.offset
+ my_last_c
.width
== other_c
.offset
) {
3968 my_last_c
.width
+= other_c
.width
;
3970 chunks_
.push_back(other_c
);
3973 bits_
.insert(bits_
.end(), signal
.bits_
.begin(), signal
.bits_
.end());
3975 width_
+= signal
.width_
;
3979 void RTLIL::SigSpec::append(const RTLIL::SigBit
&bit
)
3983 cover("kernel.rtlil.sigspec.append_bit.packed");
3985 if (chunks_
.size() == 0)
3986 chunks_
.push_back(bit
);
3988 if (bit
.wire
== NULL
)
3989 if (chunks_
.back().wire
== NULL
) {
3990 chunks_
.back().data
.push_back(bit
.data
);
3991 chunks_
.back().width
++;
3993 chunks_
.push_back(bit
);
3995 if (chunks_
.back().wire
== bit
.wire
&& chunks_
.back().offset
+ chunks_
.back().width
== bit
.offset
)
3996 chunks_
.back().width
++;
3998 chunks_
.push_back(bit
);
4002 cover("kernel.rtlil.sigspec.append_bit.unpacked");
4003 bits_
.push_back(bit
);
4010 void RTLIL::SigSpec::extend_u0(int width
, bool is_signed
)
4012 cover("kernel.rtlil.sigspec.extend_u0");
4017 remove(width
, width_
- width
);
4019 if (width_
< width
) {
4020 RTLIL::SigBit padding
= width_
> 0 ? (*this)[width_
- 1] : RTLIL::State::Sx
;
4022 padding
= RTLIL::State::S0
;
4023 while (width_
< width
)
4029 RTLIL::SigSpec
RTLIL::SigSpec::repeat(int num
) const
4031 cover("kernel.rtlil.sigspec.repeat");
4034 for (int i
= 0; i
< num
; i
++)
4040 void RTLIL::SigSpec::check() const
4044 cover("kernel.rtlil.sigspec.check.skip");
4048 cover("kernel.rtlil.sigspec.check.packed");
4051 for (size_t i
= 0; i
< chunks_
.size(); i
++) {
4052 const RTLIL::SigChunk
&chunk
= chunks_
[i
];
4053 log_assert(chunk
.width
!= 0);
4054 if (chunk
.wire
== NULL
) {
4056 log_assert(chunks_
[i
-1].wire
!= NULL
);
4057 log_assert(chunk
.offset
== 0);
4058 log_assert(chunk
.data
.size() == (size_t)chunk
.width
);
4060 if (i
> 0 && chunks_
[i
-1].wire
== chunk
.wire
)
4061 log_assert(chunk
.offset
!= chunks_
[i
-1].offset
+ chunks_
[i
-1].width
);
4062 log_assert(chunk
.offset
>= 0);
4063 log_assert(chunk
.width
>= 0);
4064 log_assert(chunk
.offset
+ chunk
.width
<= chunk
.wire
->width
);
4065 log_assert(chunk
.data
.size() == 0);
4069 log_assert(w
== width_
);
4070 log_assert(bits_
.empty());
4074 cover("kernel.rtlil.sigspec.check.unpacked");
4076 log_assert(width_
== GetSize(bits_
));
4077 log_assert(chunks_
.empty());
4082 bool RTLIL::SigSpec::operator <(const RTLIL::SigSpec
&other
) const
4084 cover("kernel.rtlil.sigspec.comp_lt");
4089 if (width_
!= other
.width_
)
4090 return width_
< other
.width_
;
4095 if (chunks_
.size() != other
.chunks_
.size())
4096 return chunks_
.size() < other
.chunks_
.size();
4101 if (hash_
!= other
.hash_
)
4102 return hash_
< other
.hash_
;
4104 for (size_t i
= 0; i
< chunks_
.size(); i
++)
4105 if (chunks_
[i
] != other
.chunks_
[i
]) {
4106 cover("kernel.rtlil.sigspec.comp_lt.hash_collision");
4107 return chunks_
[i
] < other
.chunks_
[i
];
4110 cover("kernel.rtlil.sigspec.comp_lt.equal");
4114 bool RTLIL::SigSpec::operator ==(const RTLIL::SigSpec
&other
) const
4116 cover("kernel.rtlil.sigspec.comp_eq");
4121 if (width_
!= other
.width_
)
4124 // Without this, SigSpec() == SigSpec(State::S0, 0) will fail
4125 // since the RHS will contain one SigChunk of width 0 causing
4126 // the size check below to fail
4133 if (chunks_
.size() != other
.chunks_
.size())
4139 if (hash_
!= other
.hash_
)
4142 for (size_t i
= 0; i
< chunks_
.size(); i
++)
4143 if (chunks_
[i
] != other
.chunks_
[i
]) {
4144 cover("kernel.rtlil.sigspec.comp_eq.hash_collision");
4148 cover("kernel.rtlil.sigspec.comp_eq.equal");
4152 bool RTLIL::SigSpec::is_wire() const
4154 cover("kernel.rtlil.sigspec.is_wire");
4157 return GetSize(chunks_
) == 1 && chunks_
[0].wire
&& chunks_
[0].wire
->width
== width_
;
4160 bool RTLIL::SigSpec::is_chunk() const
4162 cover("kernel.rtlil.sigspec.is_chunk");
4165 return GetSize(chunks_
) == 1;
4168 bool RTLIL::SigSpec::is_fully_const() const
4170 cover("kernel.rtlil.sigspec.is_fully_const");
4173 for (auto it
= chunks_
.begin(); it
!= chunks_
.end(); it
++)
4174 if (it
->width
> 0 && it
->wire
!= NULL
)
4179 bool RTLIL::SigSpec::is_fully_zero() const
4181 cover("kernel.rtlil.sigspec.is_fully_zero");
4184 for (auto it
= chunks_
.begin(); it
!= chunks_
.end(); it
++) {
4185 if (it
->width
> 0 && it
->wire
!= NULL
)
4187 for (size_t i
= 0; i
< it
->data
.size(); i
++)
4188 if (it
->data
[i
] != RTLIL::State::S0
)
4194 bool RTLIL::SigSpec::is_fully_ones() const
4196 cover("kernel.rtlil.sigspec.is_fully_ones");
4199 for (auto it
= chunks_
.begin(); it
!= chunks_
.end(); it
++) {
4200 if (it
->width
> 0 && it
->wire
!= NULL
)
4202 for (size_t i
= 0; i
< it
->data
.size(); i
++)
4203 if (it
->data
[i
] != RTLIL::State::S1
)
4209 bool RTLIL::SigSpec::is_fully_def() const
4211 cover("kernel.rtlil.sigspec.is_fully_def");
4214 for (auto it
= chunks_
.begin(); it
!= chunks_
.end(); it
++) {
4215 if (it
->width
> 0 && it
->wire
!= NULL
)
4217 for (size_t i
= 0; i
< it
->data
.size(); i
++)
4218 if (it
->data
[i
] != RTLIL::State::S0
&& it
->data
[i
] != RTLIL::State::S1
)
4224 bool RTLIL::SigSpec::is_fully_undef() const
4226 cover("kernel.rtlil.sigspec.is_fully_undef");
4229 for (auto it
= chunks_
.begin(); it
!= chunks_
.end(); it
++) {
4230 if (it
->width
> 0 && it
->wire
!= NULL
)
4232 for (size_t i
= 0; i
< it
->data
.size(); i
++)
4233 if (it
->data
[i
] != RTLIL::State::Sx
&& it
->data
[i
] != RTLIL::State::Sz
)
4239 bool RTLIL::SigSpec::has_const() const
4241 cover("kernel.rtlil.sigspec.has_const");
4244 for (auto it
= chunks_
.begin(); it
!= chunks_
.end(); it
++)
4245 if (it
->width
> 0 && it
->wire
== NULL
)
4250 bool RTLIL::SigSpec::has_marked_bits() const
4252 cover("kernel.rtlil.sigspec.has_marked_bits");
4255 for (auto it
= chunks_
.begin(); it
!= chunks_
.end(); it
++)
4256 if (it
->width
> 0 && it
->wire
== NULL
) {
4257 for (size_t i
= 0; i
< it
->data
.size(); i
++)
4258 if (it
->data
[i
] == RTLIL::State::Sm
)
4264 bool RTLIL::SigSpec::is_onehot(int *pos
) const
4266 cover("kernel.rtlil.sigspec.is_onehot");
4269 if (!is_fully_const())
4271 log_assert(GetSize(chunks_
) <= 1);
4273 return RTLIL::Const(chunks_
[0].data
).is_onehot(pos
);
4277 bool RTLIL::SigSpec::as_bool() const
4279 cover("kernel.rtlil.sigspec.as_bool");
4282 log_assert(is_fully_const() && GetSize(chunks_
) <= 1);
4284 return RTLIL::Const(chunks_
[0].data
).as_bool();
4288 int RTLIL::SigSpec::as_int(bool is_signed
) const
4290 cover("kernel.rtlil.sigspec.as_int");
4293 log_assert(is_fully_const() && GetSize(chunks_
) <= 1);
4295 return RTLIL::Const(chunks_
[0].data
).as_int(is_signed
);
4299 std::string
RTLIL::SigSpec::as_string() const
4301 cover("kernel.rtlil.sigspec.as_string");
4305 str
.reserve(size());
4306 for (size_t i
= chunks_
.size(); i
> 0; i
--) {
4307 const RTLIL::SigChunk
&chunk
= chunks_
[i
-1];
4308 if (chunk
.wire
!= NULL
)
4309 str
.append(chunk
.width
, '?');
4311 str
+= RTLIL::Const(chunk
.data
).as_string();
4316 RTLIL::Const
RTLIL::SigSpec::as_const() const
4318 cover("kernel.rtlil.sigspec.as_const");
4321 log_assert(is_fully_const() && GetSize(chunks_
) <= 1);
4323 return chunks_
[0].data
;
4324 return RTLIL::Const();
4327 RTLIL::Wire
*RTLIL::SigSpec::as_wire() const
4329 cover("kernel.rtlil.sigspec.as_wire");
4332 log_assert(is_wire());
4333 return chunks_
[0].wire
;
4336 RTLIL::SigChunk
RTLIL::SigSpec::as_chunk() const
4338 cover("kernel.rtlil.sigspec.as_chunk");
4341 log_assert(is_chunk());
4345 RTLIL::SigBit
RTLIL::SigSpec::as_bit() const
4347 cover("kernel.rtlil.sigspec.as_bit");
4349 log_assert(width_
== 1);
4351 return RTLIL::SigBit(*chunks_
.begin());
4356 bool RTLIL::SigSpec::match(const char* pattern
) const
4358 cover("kernel.rtlil.sigspec.match");
4361 log_assert(int(strlen(pattern
)) == GetSize(bits_
));
4363 for (auto it
= bits_
.rbegin(); it
!= bits_
.rend(); it
++, pattern
++) {
4364 if (*pattern
== ' ')
4366 if (*pattern
== '*') {
4367 if (*it
!= State::Sz
&& *it
!= State::Sx
)
4371 if (*pattern
== '0') {
4372 if (*it
!= State::S0
)
4375 if (*pattern
== '1') {
4376 if (*it
!= State::S1
)
4385 std::set
<RTLIL::SigBit
> RTLIL::SigSpec::to_sigbit_set() const
4387 cover("kernel.rtlil.sigspec.to_sigbit_set");
4390 std::set
<RTLIL::SigBit
> sigbits
;
4391 for (auto &c
: chunks_
)
4392 for (int i
= 0; i
< c
.width
; i
++)
4393 sigbits
.insert(RTLIL::SigBit(c
, i
));
4397 pool
<RTLIL::SigBit
> RTLIL::SigSpec::to_sigbit_pool() const
4399 cover("kernel.rtlil.sigspec.to_sigbit_pool");
4402 pool
<RTLIL::SigBit
> sigbits
;
4403 sigbits
.reserve(size());
4404 for (auto &c
: chunks_
)
4405 for (int i
= 0; i
< c
.width
; i
++)
4406 sigbits
.insert(RTLIL::SigBit(c
, i
));
4410 std::vector
<RTLIL::SigBit
> RTLIL::SigSpec::to_sigbit_vector() const
4412 cover("kernel.rtlil.sigspec.to_sigbit_vector");
4418 std::map
<RTLIL::SigBit
, RTLIL::SigBit
> RTLIL::SigSpec::to_sigbit_map(const RTLIL::SigSpec
&other
) const
4420 cover("kernel.rtlil.sigspec.to_sigbit_map");
4425 log_assert(width_
== other
.width_
);
4427 std::map
<RTLIL::SigBit
, RTLIL::SigBit
> new_map
;
4428 for (int i
= 0; i
< width_
; i
++)
4429 new_map
[bits_
[i
]] = other
.bits_
[i
];
4434 dict
<RTLIL::SigBit
, RTLIL::SigBit
> RTLIL::SigSpec::to_sigbit_dict(const RTLIL::SigSpec
&other
) const
4436 cover("kernel.rtlil.sigspec.to_sigbit_dict");
4441 log_assert(width_
== other
.width_
);
4443 dict
<RTLIL::SigBit
, RTLIL::SigBit
> new_map
;
4444 new_map
.reserve(size());
4445 for (int i
= 0; i
< width_
; i
++)
4446 new_map
[bits_
[i
]] = other
.bits_
[i
];
4451 static void sigspec_parse_split(std::vector
<std::string
> &tokens
, const std::string
&text
, char sep
)
4453 size_t start
= 0, end
= 0;
4454 while ((end
= text
.find(sep
, start
)) != std::string::npos
) {
4455 tokens
.push_back(text
.substr(start
, end
- start
));
4458 tokens
.push_back(text
.substr(start
));
4461 static int sigspec_parse_get_dummy_line_num()
4466 bool RTLIL::SigSpec::parse(RTLIL::SigSpec
&sig
, RTLIL::Module
*module
, std::string str
)
4468 cover("kernel.rtlil.sigspec.parse");
4470 AST::current_filename
= "input";
4472 std::vector
<std::string
> tokens
;
4473 sigspec_parse_split(tokens
, str
, ',');
4475 sig
= RTLIL::SigSpec();
4476 for (int tokidx
= int(tokens
.size())-1; tokidx
>= 0; tokidx
--)
4478 std::string netname
= tokens
[tokidx
];
4479 std::string indices
;
4481 if (netname
.size() == 0)
4484 if (('0' <= netname
[0] && netname
[0] <= '9') || netname
[0] == '\'') {
4485 cover("kernel.rtlil.sigspec.parse.const");
4486 AST::get_line_num
= sigspec_parse_get_dummy_line_num
;
4487 AST::AstNode
*ast
= VERILOG_FRONTEND::const2ast(netname
);
4490 sig
.append(RTLIL::Const(ast
->bits
));
4498 cover("kernel.rtlil.sigspec.parse.net");
4500 if (netname
[0] != '$' && netname
[0] != '\\')
4501 netname
= "\\" + netname
;
4503 if (module
->wires_
.count(netname
) == 0) {
4504 size_t indices_pos
= netname
.size()-1;
4505 if (indices_pos
> 2 && netname
[indices_pos
] == ']')
4508 while (indices_pos
> 0 && ('0' <= netname
[indices_pos
] && netname
[indices_pos
] <= '9')) indices_pos
--;
4509 if (indices_pos
> 0 && netname
[indices_pos
] == ':') {
4511 while (indices_pos
> 0 && ('0' <= netname
[indices_pos
] && netname
[indices_pos
] <= '9')) indices_pos
--;
4513 if (indices_pos
> 0 && netname
[indices_pos
] == '[') {
4514 indices
= netname
.substr(indices_pos
);
4515 netname
= netname
.substr(0, indices_pos
);
4520 if (module
->wires_
.count(netname
) == 0)
4523 RTLIL::Wire
*wire
= module
->wires_
.at(netname
);
4524 if (!indices
.empty()) {
4525 std::vector
<std::string
> index_tokens
;
4526 sigspec_parse_split(index_tokens
, indices
.substr(1, indices
.size()-2), ':');
4527 if (index_tokens
.size() == 1) {
4528 cover("kernel.rtlil.sigspec.parse.bit_sel");
4529 int a
= atoi(index_tokens
.at(0).c_str());
4530 if (a
< 0 || a
>= wire
->width
)
4532 sig
.append(RTLIL::SigSpec(wire
, a
));
4534 cover("kernel.rtlil.sigspec.parse.part_sel");
4535 int a
= atoi(index_tokens
.at(0).c_str());
4536 int b
= atoi(index_tokens
.at(1).c_str());
4541 if (a
< 0 || a
>= wire
->width
)
4543 if (b
< 0 || b
>= wire
->width
)
4545 sig
.append(RTLIL::SigSpec(wire
, a
, b
-a
+1));
4554 bool RTLIL::SigSpec::parse_sel(RTLIL::SigSpec
&sig
, RTLIL::Design
*design
, RTLIL::Module
*module
, std::string str
)
4556 if (str
.empty() || str
[0] != '@')
4557 return parse(sig
, module
, str
);
4559 cover("kernel.rtlil.sigspec.parse.sel");
4561 str
= RTLIL::escape_id(str
.substr(1));
4562 if (design
->selection_vars
.count(str
) == 0)
4565 sig
= RTLIL::SigSpec();
4566 RTLIL::Selection
&sel
= design
->selection_vars
.at(str
);
4567 for (auto &it
: module
->wires_
)
4568 if (sel
.selected_member(module
->name
, it
.first
))
4569 sig
.append(it
.second
);
4574 bool RTLIL::SigSpec::parse_rhs(const RTLIL::SigSpec
&lhs
, RTLIL::SigSpec
&sig
, RTLIL::Module
*module
, std::string str
)
4577 cover("kernel.rtlil.sigspec.parse.rhs_zeros");
4578 sig
= RTLIL::SigSpec(RTLIL::State::S0
, lhs
.width_
);
4583 cover("kernel.rtlil.sigspec.parse.rhs_ones");
4584 sig
= RTLIL::SigSpec(RTLIL::State::S1
, lhs
.width_
);
4588 if (lhs
.chunks_
.size() == 1) {
4589 char *p
= (char*)str
.c_str(), *endptr
;
4590 long int val
= strtol(p
, &endptr
, 10);
4591 if (endptr
&& endptr
!= p
&& *endptr
== 0) {
4592 sig
= RTLIL::SigSpec(val
, lhs
.width_
);
4593 cover("kernel.rtlil.sigspec.parse.rhs_dec");
4598 return parse(sig
, module
, str
);
4601 RTLIL::CaseRule::~CaseRule()
4603 for (auto it
= switches
.begin(); it
!= switches
.end(); it
++)
4607 bool RTLIL::CaseRule::empty() const
4609 return actions
.empty() && switches
.empty();
4612 RTLIL::CaseRule
*RTLIL::CaseRule::clone() const
4614 RTLIL::CaseRule
*new_caserule
= new RTLIL::CaseRule
;
4615 new_caserule
->compare
= compare
;
4616 new_caserule
->actions
= actions
;
4617 for (auto &it
: switches
)
4618 new_caserule
->switches
.push_back(it
->clone());
4619 return new_caserule
;
4622 RTLIL::SwitchRule::~SwitchRule()
4624 for (auto it
= cases
.begin(); it
!= cases
.end(); it
++)
4628 bool RTLIL::SwitchRule::empty() const
4630 return cases
.empty();
4633 RTLIL::SwitchRule
*RTLIL::SwitchRule::clone() const
4635 RTLIL::SwitchRule
*new_switchrule
= new RTLIL::SwitchRule
;
4636 new_switchrule
->signal
= signal
;
4637 new_switchrule
->attributes
= attributes
;
4638 for (auto &it
: cases
)
4639 new_switchrule
->cases
.push_back(it
->clone());
4640 return new_switchrule
;
4644 RTLIL::SyncRule
*RTLIL::SyncRule::clone() const
4646 RTLIL::SyncRule
*new_syncrule
= new RTLIL::SyncRule
;
4647 new_syncrule
->type
= type
;
4648 new_syncrule
->signal
= signal
;
4649 new_syncrule
->actions
= actions
;
4650 new_syncrule
->mem_write_actions
= mem_write_actions
;
4651 return new_syncrule
;
4654 RTLIL::Process::~Process()
4656 for (auto it
= syncs
.begin(); it
!= syncs
.end(); it
++)
4660 RTLIL::Process
*RTLIL::Process::clone() const
4662 RTLIL::Process
*new_proc
= new RTLIL::Process
;
4664 new_proc
->name
= name
;
4665 new_proc
->attributes
= attributes
;
4667 RTLIL::CaseRule
*rc_ptr
= root_case
.clone();
4668 new_proc
->root_case
= *rc_ptr
;
4669 rc_ptr
->switches
.clear();
4672 for (auto &it
: syncs
)
4673 new_proc
->syncs
.push_back(it
->clone());
4679 RTLIL::Memory::~Memory()
4681 RTLIL::Memory::get_all_memorys()->erase(hashidx_
);
4683 static std::map
<unsigned int, RTLIL::Memory
*> all_memorys
;
4684 std::map
<unsigned int, RTLIL::Memory
*> *RTLIL::Memory::get_all_memorys(void)
4686 return &all_memorys
;