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Remember global declarations and defines accross read_verilog calls
[yosys.git] / kernel / rtlil.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 #include "kernel/yosys.h"
21 #include "kernel/macc.h"
22 #include "kernel/celltypes.h"
23 #include "frontends/verilog/verilog_frontend.h"
24 #include "backends/ilang/ilang_backend.h"
25
26 #include <string.h>
27 #include <algorithm>
28
29 YOSYS_NAMESPACE_BEGIN
30
31 RTLIL::IdString::destruct_guard_t RTLIL::IdString::destruct_guard;
32 std::vector<int> RTLIL::IdString::global_refcount_storage_;
33 std::vector<char*> RTLIL::IdString::global_id_storage_;
34 dict<char*, int, hash_cstr_ops> RTLIL::IdString::global_id_index_;
35 std::vector<int> RTLIL::IdString::global_free_idx_list_;
36
37 RTLIL::Const::Const()
38 {
39 flags = RTLIL::CONST_FLAG_NONE;
40 }
41
42 RTLIL::Const::Const(std::string str)
43 {
44 flags = RTLIL::CONST_FLAG_STRING;
45 for (int i = str.size()-1; i >= 0; i--) {
46 unsigned char ch = str[i];
47 for (int j = 0; j < 8; j++) {
48 bits.push_back((ch & 1) != 0 ? RTLIL::S1 : RTLIL::S0);
49 ch = ch >> 1;
50 }
51 }
52 }
53
54 RTLIL::Const::Const(int val, int width)
55 {
56 flags = RTLIL::CONST_FLAG_NONE;
57 for (int i = 0; i < width; i++) {
58 bits.push_back((val & 1) != 0 ? RTLIL::S1 : RTLIL::S0);
59 val = val >> 1;
60 }
61 }
62
63 RTLIL::Const::Const(RTLIL::State bit, int width)
64 {
65 flags = RTLIL::CONST_FLAG_NONE;
66 for (int i = 0; i < width; i++)
67 bits.push_back(bit);
68 }
69
70 RTLIL::Const::Const(const std::vector<bool> &bits)
71 {
72 flags = RTLIL::CONST_FLAG_NONE;
73 for (auto b : bits)
74 this->bits.push_back(b ? RTLIL::S1 : RTLIL::S0);
75 }
76
77 bool RTLIL::Const::operator <(const RTLIL::Const &other) const
78 {
79 if (bits.size() != other.bits.size())
80 return bits.size() < other.bits.size();
81 for (size_t i = 0; i < bits.size(); i++)
82 if (bits[i] != other.bits[i])
83 return bits[i] < other.bits[i];
84 return false;
85 }
86
87 bool RTLIL::Const::operator ==(const RTLIL::Const &other) const
88 {
89 return bits == other.bits;
90 }
91
92 bool RTLIL::Const::operator !=(const RTLIL::Const &other) const
93 {
94 return bits != other.bits;
95 }
96
97 bool RTLIL::Const::as_bool() const
98 {
99 for (size_t i = 0; i < bits.size(); i++)
100 if (bits[i] == RTLIL::S1)
101 return true;
102 return false;
103 }
104
105 int RTLIL::Const::as_int(bool is_signed) const
106 {
107 int32_t ret = 0;
108 for (size_t i = 0; i < bits.size() && i < 32; i++)
109 if (bits[i] == RTLIL::S1)
110 ret |= 1 << i;
111 if (is_signed && bits.back() == RTLIL::S1)
112 for (size_t i = bits.size(); i < 32; i++)
113 ret |= 1 << i;
114 return ret;
115 }
116
117 std::string RTLIL::Const::as_string() const
118 {
119 std::string ret;
120 for (size_t i = bits.size(); i > 0; i--)
121 switch (bits[i-1]) {
122 case S0: ret += "0"; break;
123 case S1: ret += "1"; break;
124 case Sx: ret += "x"; break;
125 case Sz: ret += "z"; break;
126 case Sa: ret += "-"; break;
127 case Sm: ret += "m"; break;
128 }
129 return ret;
130 }
131
132 RTLIL::Const RTLIL::Const::from_string(std::string str)
133 {
134 Const c;
135 for (auto it = str.rbegin(); it != str.rend(); it++)
136 switch (*it) {
137 case '0': c.bits.push_back(State::S0); break;
138 case '1': c.bits.push_back(State::S1); break;
139 case 'x': c.bits.push_back(State::Sx); break;
140 case 'z': c.bits.push_back(State::Sz); break;
141 case 'm': c.bits.push_back(State::Sm); break;
142 default: c.bits.push_back(State::Sa);
143 }
144 return c;
145 }
146
147 std::string RTLIL::Const::decode_string() const
148 {
149 std::string string;
150 std::vector<char> string_chars;
151 for (int i = 0; i < int (bits.size()); i += 8) {
152 char ch = 0;
153 for (int j = 0; j < 8 && i + j < int (bits.size()); j++)
154 if (bits[i + j] == RTLIL::State::S1)
155 ch |= 1 << j;
156 if (ch != 0)
157 string_chars.push_back(ch);
158 }
159 for (int i = int (string_chars.size()) - 1; i >= 0; i--)
160 string += string_chars[i];
161 return string;
162 }
163
164 void RTLIL::AttrObject::set_bool_attribute(RTLIL::IdString id)
165 {
166 attributes[id] = RTLIL::Const(1);
167 }
168
169 bool RTLIL::AttrObject::get_bool_attribute(RTLIL::IdString id) const
170 {
171 if (attributes.count(id) == 0)
172 return false;
173 return attributes.at(id).as_bool();
174 }
175
176 void RTLIL::AttrObject::set_strpool_attribute(RTLIL::IdString id, const pool<string> &data)
177 {
178 string attrval;
179 for (auto &s : data) {
180 if (!attrval.empty())
181 attrval += "|";
182 attrval += s;
183 }
184 attributes[id] = RTLIL::Const(attrval);
185 }
186
187 void RTLIL::AttrObject::add_strpool_attribute(RTLIL::IdString id, const pool<string> &data)
188 {
189 pool<string> union_data = get_strpool_attribute(id);
190 union_data.insert(data.begin(), data.end());
191 if (!union_data.empty())
192 set_strpool_attribute(id, union_data);
193 }
194
195 pool<string> RTLIL::AttrObject::get_strpool_attribute(RTLIL::IdString id) const
196 {
197 pool<string> data;
198 if (attributes.count(id) != 0)
199 for (auto s : split_tokens(attributes.at(id).decode_string(), "|"))
200 data.insert(s);
201 return data;
202 }
203
204 bool RTLIL::Selection::selected_module(RTLIL::IdString mod_name) const
205 {
206 if (full_selection)
207 return true;
208 if (selected_modules.count(mod_name) > 0)
209 return true;
210 if (selected_members.count(mod_name) > 0)
211 return true;
212 return false;
213 }
214
215 bool RTLIL::Selection::selected_whole_module(RTLIL::IdString mod_name) const
216 {
217 if (full_selection)
218 return true;
219 if (selected_modules.count(mod_name) > 0)
220 return true;
221 return false;
222 }
223
224 bool RTLIL::Selection::selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const
225 {
226 if (full_selection)
227 return true;
228 if (selected_modules.count(mod_name) > 0)
229 return true;
230 if (selected_members.count(mod_name) > 0)
231 if (selected_members.at(mod_name).count(memb_name) > 0)
232 return true;
233 return false;
234 }
235
236 void RTLIL::Selection::optimize(RTLIL::Design *design)
237 {
238 if (full_selection) {
239 selected_modules.clear();
240 selected_members.clear();
241 return;
242 }
243
244 std::vector<RTLIL::IdString> del_list, add_list;
245
246 del_list.clear();
247 for (auto mod_name : selected_modules) {
248 if (design->modules_.count(mod_name) == 0)
249 del_list.push_back(mod_name);
250 selected_members.erase(mod_name);
251 }
252 for (auto mod_name : del_list)
253 selected_modules.erase(mod_name);
254
255 del_list.clear();
256 for (auto &it : selected_members)
257 if (design->modules_.count(it.first) == 0)
258 del_list.push_back(it.first);
259 for (auto mod_name : del_list)
260 selected_members.erase(mod_name);
261
262 for (auto &it : selected_members) {
263 del_list.clear();
264 for (auto memb_name : it.second)
265 if (design->modules_[it.first]->count_id(memb_name) == 0)
266 del_list.push_back(memb_name);
267 for (auto memb_name : del_list)
268 it.second.erase(memb_name);
269 }
270
271 del_list.clear();
272 add_list.clear();
273 for (auto &it : selected_members)
274 if (it.second.size() == 0)
275 del_list.push_back(it.first);
276 else if (it.second.size() == design->modules_[it.first]->wires_.size() + design->modules_[it.first]->memories.size() +
277 design->modules_[it.first]->cells_.size() + design->modules_[it.first]->processes.size())
278 add_list.push_back(it.first);
279 for (auto mod_name : del_list)
280 selected_members.erase(mod_name);
281 for (auto mod_name : add_list) {
282 selected_members.erase(mod_name);
283 selected_modules.insert(mod_name);
284 }
285
286 if (selected_modules.size() == design->modules_.size()) {
287 full_selection = true;
288 selected_modules.clear();
289 selected_members.clear();
290 }
291 }
292
293 RTLIL::Design::Design()
294 {
295 static unsigned int hashidx_count = 123456789;
296 hashidx_count = mkhash_xorshift(hashidx_count);
297 hashidx_ = hashidx_count;
298
299 refcount_modules_ = 0;
300 selection_stack.push_back(RTLIL::Selection());
301 }
302
303 RTLIL::Design::~Design()
304 {
305 for (auto it = modules_.begin(); it != modules_.end(); ++it)
306 delete it->second;
307 for (auto n : verilog_packages)
308 delete n;
309 for (auto n : verilog_globals)
310 delete n;
311 }
312
313 RTLIL::ObjRange<RTLIL::Module*> RTLIL::Design::modules()
314 {
315 return RTLIL::ObjRange<RTLIL::Module*>(&modules_, &refcount_modules_);
316 }
317
318 RTLIL::Module *RTLIL::Design::module(RTLIL::IdString name)
319 {
320 return modules_.count(name) ? modules_.at(name) : NULL;
321 }
322
323 RTLIL::Module *RTLIL::Design::top_module()
324 {
325 RTLIL::Module *module = nullptr;
326 int module_count = 0;
327
328 for (auto mod : selected_modules()) {
329 if (mod->get_bool_attribute("\\top"))
330 return mod;
331 module_count++;
332 module = mod;
333 }
334
335 return module_count == 1 ? module : nullptr;
336 }
337
338 void RTLIL::Design::add(RTLIL::Module *module)
339 {
340 log_assert(modules_.count(module->name) == 0);
341 log_assert(refcount_modules_ == 0);
342 modules_[module->name] = module;
343 module->design = this;
344
345 for (auto mon : monitors)
346 mon->notify_module_add(module);
347
348 if (yosys_xtrace) {
349 log("#X# New Module: %s\n", log_id(module));
350 log_backtrace("-X- ", yosys_xtrace-1);
351 }
352 }
353
354 RTLIL::Module *RTLIL::Design::addModule(RTLIL::IdString name)
355 {
356 log_assert(modules_.count(name) == 0);
357 log_assert(refcount_modules_ == 0);
358
359 RTLIL::Module *module = new RTLIL::Module;
360 modules_[name] = module;
361 module->design = this;
362 module->name = name;
363
364 for (auto mon : monitors)
365 mon->notify_module_add(module);
366
367 if (yosys_xtrace) {
368 log("#X# New Module: %s\n", log_id(module));
369 log_backtrace("-X- ", yosys_xtrace-1);
370 }
371
372 return module;
373 }
374
375 void RTLIL::Design::scratchpad_unset(std::string varname)
376 {
377 scratchpad.erase(varname);
378 }
379
380 void RTLIL::Design::scratchpad_set_int(std::string varname, int value)
381 {
382 scratchpad[varname] = stringf("%d", value);
383 }
384
385 void RTLIL::Design::scratchpad_set_bool(std::string varname, bool value)
386 {
387 scratchpad[varname] = value ? "true" : "false";
388 }
389
390 void RTLIL::Design::scratchpad_set_string(std::string varname, std::string value)
391 {
392 scratchpad[varname] = value;
393 }
394
395 int RTLIL::Design::scratchpad_get_int(std::string varname, int default_value) const
396 {
397 if (scratchpad.count(varname) == 0)
398 return default_value;
399
400 std::string str = scratchpad.at(varname);
401
402 if (str == "0" || str == "false")
403 return 0;
404
405 if (str == "1" || str == "true")
406 return 1;
407
408 char *endptr = nullptr;
409 long int parsed_value = strtol(str.c_str(), &endptr, 10);
410 return *endptr ? default_value : parsed_value;
411 }
412
413 bool RTLIL::Design::scratchpad_get_bool(std::string varname, bool default_value) const
414 {
415 if (scratchpad.count(varname) == 0)
416 return default_value;
417
418 std::string str = scratchpad.at(varname);
419
420 if (str == "0" || str == "false")
421 return false;
422
423 if (str == "1" || str == "true")
424 return true;
425
426 return default_value;
427 }
428
429 std::string RTLIL::Design::scratchpad_get_string(std::string varname, std::string default_value) const
430 {
431 if (scratchpad.count(varname) == 0)
432 return default_value;
433 return scratchpad.at(varname);
434 }
435
436 void RTLIL::Design::remove(RTLIL::Module *module)
437 {
438 for (auto mon : monitors)
439 mon->notify_module_del(module);
440
441 if (yosys_xtrace) {
442 log("#X# Remove Module: %s\n", log_id(module));
443 log_backtrace("-X- ", yosys_xtrace-1);
444 }
445
446 log_assert(modules_.at(module->name) == module);
447 modules_.erase(module->name);
448 delete module;
449 }
450
451 void RTLIL::Design::rename(RTLIL::Module *module, RTLIL::IdString new_name)
452 {
453 modules_.erase(module->name);
454 module->name = new_name;
455 add(module);
456 }
457
458 void RTLIL::Design::sort()
459 {
460 scratchpad.sort();
461 modules_.sort(sort_by_id_str());
462 for (auto &it : modules_)
463 it.second->sort();
464 }
465
466 void RTLIL::Design::check()
467 {
468 #ifndef NDEBUG
469 for (auto &it : modules_) {
470 log_assert(this == it.second->design);
471 log_assert(it.first == it.second->name);
472 log_assert(!it.first.empty());
473 it.second->check();
474 }
475 #endif
476 }
477
478 void RTLIL::Design::optimize()
479 {
480 for (auto &it : modules_)
481 it.second->optimize();
482 for (auto &it : selection_stack)
483 it.optimize(this);
484 for (auto &it : selection_vars)
485 it.second.optimize(this);
486 }
487
488 bool RTLIL::Design::selected_module(RTLIL::IdString mod_name) const
489 {
490 if (!selected_active_module.empty() && mod_name != selected_active_module)
491 return false;
492 if (selection_stack.size() == 0)
493 return true;
494 return selection_stack.back().selected_module(mod_name);
495 }
496
497 bool RTLIL::Design::selected_whole_module(RTLIL::IdString mod_name) const
498 {
499 if (!selected_active_module.empty() && mod_name != selected_active_module)
500 return false;
501 if (selection_stack.size() == 0)
502 return true;
503 return selection_stack.back().selected_whole_module(mod_name);
504 }
505
506 bool RTLIL::Design::selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const
507 {
508 if (!selected_active_module.empty() && mod_name != selected_active_module)
509 return false;
510 if (selection_stack.size() == 0)
511 return true;
512 return selection_stack.back().selected_member(mod_name, memb_name);
513 }
514
515 bool RTLIL::Design::selected_module(RTLIL::Module *mod) const
516 {
517 return selected_module(mod->name);
518 }
519
520 bool RTLIL::Design::selected_whole_module(RTLIL::Module *mod) const
521 {
522 return selected_whole_module(mod->name);
523 }
524
525 std::vector<RTLIL::Module*> RTLIL::Design::selected_modules() const
526 {
527 std::vector<RTLIL::Module*> result;
528 result.reserve(modules_.size());
529 for (auto &it : modules_)
530 if (selected_module(it.first) && !it.second->get_bool_attribute("\\blackbox"))
531 result.push_back(it.second);
532 return result;
533 }
534
535 std::vector<RTLIL::Module*> RTLIL::Design::selected_whole_modules() const
536 {
537 std::vector<RTLIL::Module*> result;
538 result.reserve(modules_.size());
539 for (auto &it : modules_)
540 if (selected_whole_module(it.first) && !it.second->get_bool_attribute("\\blackbox"))
541 result.push_back(it.second);
542 return result;
543 }
544
545 std::vector<RTLIL::Module*> RTLIL::Design::selected_whole_modules_warn() const
546 {
547 std::vector<RTLIL::Module*> result;
548 result.reserve(modules_.size());
549 for (auto &it : modules_)
550 if (it.second->get_bool_attribute("\\blackbox"))
551 continue;
552 else if (selected_whole_module(it.first))
553 result.push_back(it.second);
554 else if (selected_module(it.first))
555 log_warning("Ignoring partially selected module %s.\n", log_id(it.first));
556 return result;
557 }
558
559 RTLIL::Module::Module()
560 {
561 static unsigned int hashidx_count = 123456789;
562 hashidx_count = mkhash_xorshift(hashidx_count);
563 hashidx_ = hashidx_count;
564
565 design = nullptr;
566 refcount_wires_ = 0;
567 refcount_cells_ = 0;
568 }
569
570 RTLIL::Module::~Module()
571 {
572 for (auto it = wires_.begin(); it != wires_.end(); ++it)
573 delete it->second;
574 for (auto it = memories.begin(); it != memories.end(); ++it)
575 delete it->second;
576 for (auto it = cells_.begin(); it != cells_.end(); ++it)
577 delete it->second;
578 for (auto it = processes.begin(); it != processes.end(); ++it)
579 delete it->second;
580 }
581
582 RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, dict<RTLIL::IdString, RTLIL::Const>)
583 {
584 log_error("Module `%s' is used with parameters but is not parametric!\n", id2cstr(name));
585 }
586
587 size_t RTLIL::Module::count_id(RTLIL::IdString id)
588 {
589 return wires_.count(id) + memories.count(id) + cells_.count(id) + processes.count(id);
590 }
591
592 #ifndef NDEBUG
593 namespace {
594 struct InternalCellChecker
595 {
596 RTLIL::Module *module;
597 RTLIL::Cell *cell;
598 pool<RTLIL::IdString> expected_params, expected_ports;
599
600 InternalCellChecker(RTLIL::Module *module, RTLIL::Cell *cell) : module(module), cell(cell) { }
601
602 void error(int linenr)
603 {
604 std::stringstream buf;
605 ILANG_BACKEND::dump_cell(buf, " ", cell);
606
607 log_error("Found error in internal cell %s%s%s (%s) at %s:%d:\n%s",
608 module ? module->name.c_str() : "", module ? "." : "",
609 cell->name.c_str(), cell->type.c_str(), __FILE__, linenr, buf.str().c_str());
610 }
611
612 int param(const char *name)
613 {
614 if (cell->parameters.count(name) == 0)
615 error(__LINE__);
616 expected_params.insert(name);
617 return cell->parameters.at(name).as_int();
618 }
619
620 int param_bool(const char *name)
621 {
622 int v = param(name);
623 if (cell->parameters.at(name).bits.size() > 32)
624 error(__LINE__);
625 if (v != 0 && v != 1)
626 error(__LINE__);
627 return v;
628 }
629
630 void param_bits(const char *name, int width)
631 {
632 param(name);
633 if (int(cell->parameters.at(name).bits.size()) != width)
634 error(__LINE__);
635 }
636
637 void port(const char *name, int width)
638 {
639 if (!cell->hasPort(name))
640 error(__LINE__);
641 if (cell->getPort(name).size() != width)
642 error(__LINE__);
643 expected_ports.insert(name);
644 }
645
646 void check_expected(bool check_matched_sign = true)
647 {
648 for (auto &para : cell->parameters)
649 if (expected_params.count(para.first) == 0)
650 error(__LINE__);
651 for (auto &conn : cell->connections())
652 if (expected_ports.count(conn.first) == 0)
653 error(__LINE__);
654
655 if (expected_params.count("\\A_SIGNED") != 0 && expected_params.count("\\B_SIGNED") && check_matched_sign) {
656 bool a_is_signed = param("\\A_SIGNED") != 0;
657 bool b_is_signed = param("\\B_SIGNED") != 0;
658 if (a_is_signed != b_is_signed)
659 error(__LINE__);
660 }
661 }
662
663 void check_gate(const char *ports)
664 {
665 if (cell->parameters.size() != 0)
666 error(__LINE__);
667
668 for (const char *p = ports; *p; p++) {
669 char portname[3] = { '\\', *p, 0 };
670 if (!cell->hasPort(portname))
671 error(__LINE__);
672 if (cell->getPort(portname).size() != 1)
673 error(__LINE__);
674 }
675
676 for (auto &conn : cell->connections()) {
677 if (conn.first.size() != 2 || conn.first[0] != '\\')
678 error(__LINE__);
679 if (strchr(ports, conn.first[1]) == NULL)
680 error(__LINE__);
681 }
682 }
683
684 void check()
685 {
686 if (cell->type.substr(0, 1) != "$" || cell->type.substr(0, 3) == "$__" || cell->type.substr(0, 8) == "$paramod" ||
687 cell->type.substr(0, 9) == "$verific$" || cell->type.substr(0, 7) == "$array:" || cell->type.substr(0, 8) == "$extern:")
688 return;
689
690 if (cell->type.in("$not", "$pos", "$neg")) {
691 param_bool("\\A_SIGNED");
692 port("\\A", param("\\A_WIDTH"));
693 port("\\Y", param("\\Y_WIDTH"));
694 check_expected();
695 return;
696 }
697
698 if (cell->type.in("$and", "$or", "$xor", "$xnor")) {
699 param_bool("\\A_SIGNED");
700 param_bool("\\B_SIGNED");
701 port("\\A", param("\\A_WIDTH"));
702 port("\\B", param("\\B_WIDTH"));
703 port("\\Y", param("\\Y_WIDTH"));
704 check_expected();
705 return;
706 }
707
708 if (cell->type.in("$reduce_and", "$reduce_or", "$reduce_xor", "$reduce_xnor", "$reduce_bool")) {
709 param_bool("\\A_SIGNED");
710 port("\\A", param("\\A_WIDTH"));
711 port("\\Y", param("\\Y_WIDTH"));
712 check_expected();
713 return;
714 }
715
716 if (cell->type.in("$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx")) {
717 param_bool("\\A_SIGNED");
718 param_bool("\\B_SIGNED");
719 port("\\A", param("\\A_WIDTH"));
720 port("\\B", param("\\B_WIDTH"));
721 port("\\Y", param("\\Y_WIDTH"));
722 check_expected(false);
723 return;
724 }
725
726 if (cell->type.in("$lt", "$le", "$eq", "$ne", "$eqx", "$nex", "$ge", "$gt")) {
727 param_bool("\\A_SIGNED");
728 param_bool("\\B_SIGNED");
729 port("\\A", param("\\A_WIDTH"));
730 port("\\B", param("\\B_WIDTH"));
731 port("\\Y", param("\\Y_WIDTH"));
732 check_expected();
733 return;
734 }
735
736 if (cell->type.in("$add", "$sub", "$mul", "$div", "$mod", "$pow")) {
737 param_bool("\\A_SIGNED");
738 param_bool("\\B_SIGNED");
739 port("\\A", param("\\A_WIDTH"));
740 port("\\B", param("\\B_WIDTH"));
741 port("\\Y", param("\\Y_WIDTH"));
742 check_expected(cell->type != "$pow");
743 return;
744 }
745
746 if (cell->type == "$fa") {
747 port("\\A", param("\\WIDTH"));
748 port("\\B", param("\\WIDTH"));
749 port("\\C", param("\\WIDTH"));
750 port("\\X", param("\\WIDTH"));
751 port("\\Y", param("\\WIDTH"));
752 check_expected();
753 return;
754 }
755
756 if (cell->type == "$lcu") {
757 port("\\P", param("\\WIDTH"));
758 port("\\G", param("\\WIDTH"));
759 port("\\CI", 1);
760 port("\\CO", param("\\WIDTH"));
761 check_expected();
762 return;
763 }
764
765 if (cell->type == "$alu") {
766 param_bool("\\A_SIGNED");
767 param_bool("\\B_SIGNED");
768 port("\\A", param("\\A_WIDTH"));
769 port("\\B", param("\\B_WIDTH"));
770 port("\\CI", 1);
771 port("\\BI", 1);
772 port("\\X", param("\\Y_WIDTH"));
773 port("\\Y", param("\\Y_WIDTH"));
774 port("\\CO", param("\\Y_WIDTH"));
775 check_expected();
776 return;
777 }
778
779 if (cell->type == "$macc") {
780 param("\\CONFIG");
781 param("\\CONFIG_WIDTH");
782 port("\\A", param("\\A_WIDTH"));
783 port("\\B", param("\\B_WIDTH"));
784 port("\\Y", param("\\Y_WIDTH"));
785 check_expected();
786 Macc().from_cell(cell);
787 return;
788 }
789
790 if (cell->type == "$logic_not") {
791 param_bool("\\A_SIGNED");
792 port("\\A", param("\\A_WIDTH"));
793 port("\\Y", param("\\Y_WIDTH"));
794 check_expected();
795 return;
796 }
797
798 if (cell->type == "$logic_and" || cell->type == "$logic_or") {
799 param_bool("\\A_SIGNED");
800 param_bool("\\B_SIGNED");
801 port("\\A", param("\\A_WIDTH"));
802 port("\\B", param("\\B_WIDTH"));
803 port("\\Y", param("\\Y_WIDTH"));
804 check_expected(false);
805 return;
806 }
807
808 if (cell->type == "$slice") {
809 param("\\OFFSET");
810 port("\\A", param("\\A_WIDTH"));
811 port("\\Y", param("\\Y_WIDTH"));
812 if (param("\\OFFSET") + param("\\Y_WIDTH") > param("\\A_WIDTH"))
813 error(__LINE__);
814 check_expected();
815 return;
816 }
817
818 if (cell->type == "$concat") {
819 port("\\A", param("\\A_WIDTH"));
820 port("\\B", param("\\B_WIDTH"));
821 port("\\Y", param("\\A_WIDTH") + param("\\B_WIDTH"));
822 check_expected();
823 return;
824 }
825
826 if (cell->type == "$mux") {
827 port("\\A", param("\\WIDTH"));
828 port("\\B", param("\\WIDTH"));
829 port("\\S", 1);
830 port("\\Y", param("\\WIDTH"));
831 check_expected();
832 return;
833 }
834
835 if (cell->type == "$pmux") {
836 port("\\A", param("\\WIDTH"));
837 port("\\B", param("\\WIDTH") * param("\\S_WIDTH"));
838 port("\\S", param("\\S_WIDTH"));
839 port("\\Y", param("\\WIDTH"));
840 check_expected();
841 return;
842 }
843
844 if (cell->type == "$lut") {
845 param("\\LUT");
846 port("\\A", param("\\WIDTH"));
847 port("\\Y", 1);
848 check_expected();
849 return;
850 }
851
852 if (cell->type == "$sop") {
853 param("\\DEPTH");
854 param("\\TABLE");
855 port("\\A", param("\\WIDTH"));
856 port("\\Y", 1);
857 check_expected();
858 return;
859 }
860
861 if (cell->type == "$sr") {
862 param_bool("\\SET_POLARITY");
863 param_bool("\\CLR_POLARITY");
864 port("\\SET", param("\\WIDTH"));
865 port("\\CLR", param("\\WIDTH"));
866 port("\\Q", param("\\WIDTH"));
867 check_expected();
868 return;
869 }
870
871 if (cell->type == "$ff") {
872 port("\\D", param("\\WIDTH"));
873 port("\\Q", param("\\WIDTH"));
874 check_expected();
875 return;
876 }
877
878 if (cell->type == "$dff") {
879 param_bool("\\CLK_POLARITY");
880 port("\\CLK", 1);
881 port("\\D", param("\\WIDTH"));
882 port("\\Q", param("\\WIDTH"));
883 check_expected();
884 return;
885 }
886
887 if (cell->type == "$dffe") {
888 param_bool("\\CLK_POLARITY");
889 param_bool("\\EN_POLARITY");
890 port("\\CLK", 1);
891 port("\\EN", 1);
892 port("\\D", param("\\WIDTH"));
893 port("\\Q", param("\\WIDTH"));
894 check_expected();
895 return;
896 }
897
898 if (cell->type == "$dffsr") {
899 param_bool("\\CLK_POLARITY");
900 param_bool("\\SET_POLARITY");
901 param_bool("\\CLR_POLARITY");
902 port("\\CLK", 1);
903 port("\\SET", param("\\WIDTH"));
904 port("\\CLR", param("\\WIDTH"));
905 port("\\D", param("\\WIDTH"));
906 port("\\Q", param("\\WIDTH"));
907 check_expected();
908 return;
909 }
910
911 if (cell->type == "$adff") {
912 param_bool("\\CLK_POLARITY");
913 param_bool("\\ARST_POLARITY");
914 param_bits("\\ARST_VALUE", param("\\WIDTH"));
915 port("\\CLK", 1);
916 port("\\ARST", 1);
917 port("\\D", param("\\WIDTH"));
918 port("\\Q", param("\\WIDTH"));
919 check_expected();
920 return;
921 }
922
923 if (cell->type == "$dlatch") {
924 param_bool("\\EN_POLARITY");
925 port("\\EN", 1);
926 port("\\D", param("\\WIDTH"));
927 port("\\Q", param("\\WIDTH"));
928 check_expected();
929 return;
930 }
931
932 if (cell->type == "$dlatchsr") {
933 param_bool("\\EN_POLARITY");
934 param_bool("\\SET_POLARITY");
935 param_bool("\\CLR_POLARITY");
936 port("\\EN", 1);
937 port("\\SET", param("\\WIDTH"));
938 port("\\CLR", param("\\WIDTH"));
939 port("\\D", param("\\WIDTH"));
940 port("\\Q", param("\\WIDTH"));
941 check_expected();
942 return;
943 }
944
945 if (cell->type == "$fsm") {
946 param("\\NAME");
947 param_bool("\\CLK_POLARITY");
948 param_bool("\\ARST_POLARITY");
949 param("\\STATE_BITS");
950 param("\\STATE_NUM");
951 param("\\STATE_NUM_LOG2");
952 param("\\STATE_RST");
953 param_bits("\\STATE_TABLE", param("\\STATE_BITS") * param("\\STATE_NUM"));
954 param("\\TRANS_NUM");
955 param_bits("\\TRANS_TABLE", param("\\TRANS_NUM") * (2*param("\\STATE_NUM_LOG2") + param("\\CTRL_IN_WIDTH") + param("\\CTRL_OUT_WIDTH")));
956 port("\\CLK", 1);
957 port("\\ARST", 1);
958 port("\\CTRL_IN", param("\\CTRL_IN_WIDTH"));
959 port("\\CTRL_OUT", param("\\CTRL_OUT_WIDTH"));
960 check_expected();
961 return;
962 }
963
964 if (cell->type == "$memrd") {
965 param("\\MEMID");
966 param_bool("\\CLK_ENABLE");
967 param_bool("\\CLK_POLARITY");
968 param_bool("\\TRANSPARENT");
969 port("\\CLK", 1);
970 port("\\EN", 1);
971 port("\\ADDR", param("\\ABITS"));
972 port("\\DATA", param("\\WIDTH"));
973 check_expected();
974 return;
975 }
976
977 if (cell->type == "$memwr") {
978 param("\\MEMID");
979 param_bool("\\CLK_ENABLE");
980 param_bool("\\CLK_POLARITY");
981 param("\\PRIORITY");
982 port("\\CLK", 1);
983 port("\\EN", param("\\WIDTH"));
984 port("\\ADDR", param("\\ABITS"));
985 port("\\DATA", param("\\WIDTH"));
986 check_expected();
987 return;
988 }
989
990 if (cell->type == "$meminit") {
991 param("\\MEMID");
992 param("\\PRIORITY");
993 port("\\ADDR", param("\\ABITS"));
994 port("\\DATA", param("\\WIDTH") * param("\\WORDS"));
995 check_expected();
996 return;
997 }
998
999 if (cell->type == "$mem") {
1000 param("\\MEMID");
1001 param("\\SIZE");
1002 param("\\OFFSET");
1003 param("\\INIT");
1004 param_bits("\\RD_CLK_ENABLE", max(1, param("\\RD_PORTS")));
1005 param_bits("\\RD_CLK_POLARITY", max(1, param("\\RD_PORTS")));
1006 param_bits("\\RD_TRANSPARENT", max(1, param("\\RD_PORTS")));
1007 param_bits("\\WR_CLK_ENABLE", max(1, param("\\WR_PORTS")));
1008 param_bits("\\WR_CLK_POLARITY", max(1, param("\\WR_PORTS")));
1009 port("\\RD_CLK", param("\\RD_PORTS"));
1010 port("\\RD_EN", param("\\RD_PORTS"));
1011 port("\\RD_ADDR", param("\\RD_PORTS") * param("\\ABITS"));
1012 port("\\RD_DATA", param("\\RD_PORTS") * param("\\WIDTH"));
1013 port("\\WR_CLK", param("\\WR_PORTS"));
1014 port("\\WR_EN", param("\\WR_PORTS") * param("\\WIDTH"));
1015 port("\\WR_ADDR", param("\\WR_PORTS") * param("\\ABITS"));
1016 port("\\WR_DATA", param("\\WR_PORTS") * param("\\WIDTH"));
1017 check_expected();
1018 return;
1019 }
1020
1021 if (cell->type == "$tribuf") {
1022 port("\\A", param("\\WIDTH"));
1023 port("\\Y", param("\\WIDTH"));
1024 port("\\EN", 1);
1025 check_expected();
1026 return;
1027 }
1028
1029 if (cell->type.in("$assert", "$assume")) {
1030 port("\\A", 1);
1031 port("\\EN", 1);
1032 check_expected();
1033 return;
1034 }
1035
1036 if (cell->type == "$initstate") {
1037 port("\\Y", 1);
1038 check_expected();
1039 return;
1040 }
1041
1042 if (cell->type.in("$anyconst", "$anyseq")) {
1043 port("\\Y", param("\\WIDTH"));
1044 check_expected();
1045 return;
1046 }
1047
1048 if (cell->type == "$equiv") {
1049 port("\\A", 1);
1050 port("\\B", 1);
1051 port("\\Y", 1);
1052 check_expected();
1053 return;
1054 }
1055
1056 if (cell->type == "$_BUF_") { check_gate("AY"); return; }
1057 if (cell->type == "$_NOT_") { check_gate("AY"); return; }
1058 if (cell->type == "$_AND_") { check_gate("ABY"); return; }
1059 if (cell->type == "$_NAND_") { check_gate("ABY"); return; }
1060 if (cell->type == "$_OR_") { check_gate("ABY"); return; }
1061 if (cell->type == "$_NOR_") { check_gate("ABY"); return; }
1062 if (cell->type == "$_XOR_") { check_gate("ABY"); return; }
1063 if (cell->type == "$_XNOR_") { check_gate("ABY"); return; }
1064 if (cell->type == "$_MUX_") { check_gate("ABSY"); return; }
1065 if (cell->type == "$_AOI3_") { check_gate("ABCY"); return; }
1066 if (cell->type == "$_OAI3_") { check_gate("ABCY"); return; }
1067 if (cell->type == "$_AOI4_") { check_gate("ABCDY"); return; }
1068 if (cell->type == "$_OAI4_") { check_gate("ABCDY"); return; }
1069
1070 if (cell->type == "$_TBUF_") { check_gate("AYE"); return; }
1071
1072 if (cell->type == "$_MUX4_") { check_gate("ABCDSTY"); return; }
1073 if (cell->type == "$_MUX8_") { check_gate("ABCDEFGHSTUY"); return; }
1074 if (cell->type == "$_MUX16_") { check_gate("ABCDEFGHIJKLMNOPSTUVY"); return; }
1075
1076 if (cell->type == "$_SR_NN_") { check_gate("SRQ"); return; }
1077 if (cell->type == "$_SR_NP_") { check_gate("SRQ"); return; }
1078 if (cell->type == "$_SR_PN_") { check_gate("SRQ"); return; }
1079 if (cell->type == "$_SR_PP_") { check_gate("SRQ"); return; }
1080
1081 if (cell->type == "$_FF_") { check_gate("DQ"); return; }
1082 if (cell->type == "$_DFF_N_") { check_gate("DQC"); return; }
1083 if (cell->type == "$_DFF_P_") { check_gate("DQC"); return; }
1084
1085 if (cell->type == "$_DFFE_NN_") { check_gate("DQCE"); return; }
1086 if (cell->type == "$_DFFE_NP_") { check_gate("DQCE"); return; }
1087 if (cell->type == "$_DFFE_PN_") { check_gate("DQCE"); return; }
1088 if (cell->type == "$_DFFE_PP_") { check_gate("DQCE"); return; }
1089
1090 if (cell->type == "$_DFF_NN0_") { check_gate("DQCR"); return; }
1091 if (cell->type == "$_DFF_NN1_") { check_gate("DQCR"); return; }
1092 if (cell->type == "$_DFF_NP0_") { check_gate("DQCR"); return; }
1093 if (cell->type == "$_DFF_NP1_") { check_gate("DQCR"); return; }
1094 if (cell->type == "$_DFF_PN0_") { check_gate("DQCR"); return; }
1095 if (cell->type == "$_DFF_PN1_") { check_gate("DQCR"); return; }
1096 if (cell->type == "$_DFF_PP0_") { check_gate("DQCR"); return; }
1097 if (cell->type == "$_DFF_PP1_") { check_gate("DQCR"); return; }
1098
1099 if (cell->type == "$_DFFSR_NNN_") { check_gate("CSRDQ"); return; }
1100 if (cell->type == "$_DFFSR_NNP_") { check_gate("CSRDQ"); return; }
1101 if (cell->type == "$_DFFSR_NPN_") { check_gate("CSRDQ"); return; }
1102 if (cell->type == "$_DFFSR_NPP_") { check_gate("CSRDQ"); return; }
1103 if (cell->type == "$_DFFSR_PNN_") { check_gate("CSRDQ"); return; }
1104 if (cell->type == "$_DFFSR_PNP_") { check_gate("CSRDQ"); return; }
1105 if (cell->type == "$_DFFSR_PPN_") { check_gate("CSRDQ"); return; }
1106 if (cell->type == "$_DFFSR_PPP_") { check_gate("CSRDQ"); return; }
1107
1108 if (cell->type == "$_DLATCH_N_") { check_gate("EDQ"); return; }
1109 if (cell->type == "$_DLATCH_P_") { check_gate("EDQ"); return; }
1110
1111 if (cell->type == "$_DLATCHSR_NNN_") { check_gate("ESRDQ"); return; }
1112 if (cell->type == "$_DLATCHSR_NNP_") { check_gate("ESRDQ"); return; }
1113 if (cell->type == "$_DLATCHSR_NPN_") { check_gate("ESRDQ"); return; }
1114 if (cell->type == "$_DLATCHSR_NPP_") { check_gate("ESRDQ"); return; }
1115 if (cell->type == "$_DLATCHSR_PNN_") { check_gate("ESRDQ"); return; }
1116 if (cell->type == "$_DLATCHSR_PNP_") { check_gate("ESRDQ"); return; }
1117 if (cell->type == "$_DLATCHSR_PPN_") { check_gate("ESRDQ"); return; }
1118 if (cell->type == "$_DLATCHSR_PPP_") { check_gate("ESRDQ"); return; }
1119
1120 error(__LINE__);
1121 }
1122 };
1123 }
1124 #endif
1125
1126 void RTLIL::Module::sort()
1127 {
1128 wires_.sort(sort_by_id_str());
1129 cells_.sort(sort_by_id_str());
1130 avail_parameters.sort(sort_by_id_str());
1131 memories.sort(sort_by_id_str());
1132 processes.sort(sort_by_id_str());
1133 for (auto &it : cells_)
1134 it.second->sort();
1135 for (auto &it : wires_)
1136 it.second->attributes.sort(sort_by_id_str());
1137 for (auto &it : memories)
1138 it.second->attributes.sort(sort_by_id_str());
1139 }
1140
1141 void RTLIL::Module::check()
1142 {
1143 #ifndef NDEBUG
1144 std::vector<bool> ports_declared;
1145 for (auto &it : wires_) {
1146 log_assert(this == it.second->module);
1147 log_assert(it.first == it.second->name);
1148 log_assert(!it.first.empty());
1149 log_assert(it.second->width >= 0);
1150 log_assert(it.second->port_id >= 0);
1151 for (auto &it2 : it.second->attributes)
1152 log_assert(!it2.first.empty());
1153 if (it.second->port_id) {
1154 log_assert(GetSize(ports) >= it.second->port_id);
1155 log_assert(ports.at(it.second->port_id-1) == it.first);
1156 log_assert(it.second->port_input || it.second->port_output);
1157 if (GetSize(ports_declared) < it.second->port_id)
1158 ports_declared.resize(it.second->port_id);
1159 log_assert(ports_declared[it.second->port_id-1] == false);
1160 ports_declared[it.second->port_id-1] = true;
1161 } else
1162 log_assert(!it.second->port_input && !it.second->port_output);
1163 }
1164 for (auto port_declared : ports_declared)
1165 log_assert(port_declared == true);
1166 log_assert(GetSize(ports) == GetSize(ports_declared));
1167
1168 for (auto &it : memories) {
1169 log_assert(it.first == it.second->name);
1170 log_assert(!it.first.empty());
1171 log_assert(it.second->width >= 0);
1172 log_assert(it.second->size >= 0);
1173 for (auto &it2 : it.second->attributes)
1174 log_assert(!it2.first.empty());
1175 }
1176
1177 for (auto &it : cells_) {
1178 log_assert(this == it.second->module);
1179 log_assert(it.first == it.second->name);
1180 log_assert(!it.first.empty());
1181 log_assert(!it.second->type.empty());
1182 for (auto &it2 : it.second->connections()) {
1183 log_assert(!it2.first.empty());
1184 it2.second.check();
1185 }
1186 for (auto &it2 : it.second->attributes)
1187 log_assert(!it2.first.empty());
1188 for (auto &it2 : it.second->parameters)
1189 log_assert(!it2.first.empty());
1190 InternalCellChecker checker(this, it.second);
1191 checker.check();
1192 }
1193
1194 for (auto &it : processes) {
1195 log_assert(it.first == it.second->name);
1196 log_assert(!it.first.empty());
1197 // FIXME: More checks here..
1198 }
1199
1200 for (auto &it : connections_) {
1201 log_assert(it.first.size() == it.second.size());
1202 log_assert(!it.first.has_const());
1203 it.first.check();
1204 it.second.check();
1205 }
1206
1207 for (auto &it : attributes)
1208 log_assert(!it.first.empty());
1209 #endif
1210 }
1211
1212 void RTLIL::Module::optimize()
1213 {
1214 }
1215
1216 void RTLIL::Module::cloneInto(RTLIL::Module *new_mod) const
1217 {
1218 log_assert(new_mod->refcount_wires_ == 0);
1219 log_assert(new_mod->refcount_cells_ == 0);
1220
1221 new_mod->avail_parameters = avail_parameters;
1222
1223 for (auto &conn : connections_)
1224 new_mod->connect(conn);
1225
1226 for (auto &attr : attributes)
1227 new_mod->attributes[attr.first] = attr.second;
1228
1229 for (auto &it : wires_)
1230 new_mod->addWire(it.first, it.second);
1231
1232 for (auto &it : memories)
1233 new_mod->memories[it.first] = new RTLIL::Memory(*it.second);
1234
1235 for (auto &it : cells_)
1236 new_mod->addCell(it.first, it.second);
1237
1238 for (auto &it : processes)
1239 new_mod->processes[it.first] = it.second->clone();
1240
1241 struct RewriteSigSpecWorker
1242 {
1243 RTLIL::Module *mod;
1244 void operator()(RTLIL::SigSpec &sig)
1245 {
1246 std::vector<RTLIL::SigChunk> chunks = sig.chunks();
1247 for (auto &c : chunks)
1248 if (c.wire != NULL)
1249 c.wire = mod->wires_.at(c.wire->name);
1250 sig = chunks;
1251 }
1252 };
1253
1254 RewriteSigSpecWorker rewriteSigSpecWorker;
1255 rewriteSigSpecWorker.mod = new_mod;
1256 new_mod->rewrite_sigspecs(rewriteSigSpecWorker);
1257 new_mod->fixup_ports();
1258 }
1259
1260 RTLIL::Module *RTLIL::Module::clone() const
1261 {
1262 RTLIL::Module *new_mod = new RTLIL::Module;
1263 new_mod->name = name;
1264 cloneInto(new_mod);
1265 return new_mod;
1266 }
1267
1268 bool RTLIL::Module::has_memories() const
1269 {
1270 return !memories.empty();
1271 }
1272
1273 bool RTLIL::Module::has_processes() const
1274 {
1275 return !processes.empty();
1276 }
1277
1278 bool RTLIL::Module::has_memories_warn() const
1279 {
1280 if (!memories.empty())
1281 log_warning("Ignoring module %s because it contains memories (run 'memory' command first).\n", log_id(this));
1282 return !memories.empty();
1283 }
1284
1285 bool RTLIL::Module::has_processes_warn() const
1286 {
1287 if (!processes.empty())
1288 log_warning("Ignoring module %s because it contains processes (run 'proc' command first).\n", log_id(this));
1289 return !processes.empty();
1290 }
1291
1292 std::vector<RTLIL::Wire*> RTLIL::Module::selected_wires() const
1293 {
1294 std::vector<RTLIL::Wire*> result;
1295 result.reserve(wires_.size());
1296 for (auto &it : wires_)
1297 if (design->selected(this, it.second))
1298 result.push_back(it.second);
1299 return result;
1300 }
1301
1302 std::vector<RTLIL::Cell*> RTLIL::Module::selected_cells() const
1303 {
1304 std::vector<RTLIL::Cell*> result;
1305 result.reserve(wires_.size());
1306 for (auto &it : cells_)
1307 if (design->selected(this, it.second))
1308 result.push_back(it.second);
1309 return result;
1310 }
1311
1312 void RTLIL::Module::add(RTLIL::Wire *wire)
1313 {
1314 log_assert(!wire->name.empty());
1315 log_assert(count_id(wire->name) == 0);
1316 log_assert(refcount_wires_ == 0);
1317 wires_[wire->name] = wire;
1318 wire->module = this;
1319 }
1320
1321 void RTLIL::Module::add(RTLIL::Cell *cell)
1322 {
1323 log_assert(!cell->name.empty());
1324 log_assert(count_id(cell->name) == 0);
1325 log_assert(refcount_cells_ == 0);
1326 cells_[cell->name] = cell;
1327 cell->module = this;
1328 }
1329
1330 namespace {
1331 struct DeleteWireWorker
1332 {
1333 RTLIL::Module *module;
1334 const pool<RTLIL::Wire*> *wires_p;
1335
1336 void operator()(RTLIL::SigSpec &sig) {
1337 std::vector<RTLIL::SigChunk> chunks = sig;
1338 for (auto &c : chunks)
1339 if (c.wire != NULL && wires_p->count(c.wire)) {
1340 c.wire = module->addWire(NEW_ID, c.width);
1341 c.offset = 0;
1342 }
1343 sig = chunks;
1344 }
1345 };
1346 }
1347
1348 void RTLIL::Module::remove(const pool<RTLIL::Wire*> &wires)
1349 {
1350 log_assert(refcount_wires_ == 0);
1351
1352 DeleteWireWorker delete_wire_worker;
1353 delete_wire_worker.module = this;
1354 delete_wire_worker.wires_p = &wires;
1355 rewrite_sigspecs(delete_wire_worker);
1356
1357 for (auto &it : wires) {
1358 log_assert(wires_.count(it->name) != 0);
1359 wires_.erase(it->name);
1360 delete it;
1361 }
1362 }
1363
1364 void RTLIL::Module::remove(RTLIL::Cell *cell)
1365 {
1366 while (!cell->connections_.empty())
1367 cell->unsetPort(cell->connections_.begin()->first);
1368
1369 log_assert(cells_.count(cell->name) != 0);
1370 log_assert(refcount_cells_ == 0);
1371 cells_.erase(cell->name);
1372 delete cell;
1373 }
1374
1375 void RTLIL::Module::rename(RTLIL::Wire *wire, RTLIL::IdString new_name)
1376 {
1377 log_assert(wires_[wire->name] == wire);
1378 log_assert(refcount_wires_ == 0);
1379 wires_.erase(wire->name);
1380 wire->name = new_name;
1381 add(wire);
1382 }
1383
1384 void RTLIL::Module::rename(RTLIL::Cell *cell, RTLIL::IdString new_name)
1385 {
1386 log_assert(cells_[cell->name] == cell);
1387 log_assert(refcount_wires_ == 0);
1388 cells_.erase(cell->name);
1389 cell->name = new_name;
1390 add(cell);
1391 }
1392
1393 void RTLIL::Module::rename(RTLIL::IdString old_name, RTLIL::IdString new_name)
1394 {
1395 log_assert(count_id(old_name) != 0);
1396 if (wires_.count(old_name))
1397 rename(wires_.at(old_name), new_name);
1398 else if (cells_.count(old_name))
1399 rename(cells_.at(old_name), new_name);
1400 else
1401 log_abort();
1402 }
1403
1404 void RTLIL::Module::swap_names(RTLIL::Wire *w1, RTLIL::Wire *w2)
1405 {
1406 log_assert(wires_[w1->name] == w1);
1407 log_assert(wires_[w2->name] == w2);
1408 log_assert(refcount_wires_ == 0);
1409
1410 wires_.erase(w1->name);
1411 wires_.erase(w2->name);
1412
1413 std::swap(w1->name, w2->name);
1414
1415 wires_[w1->name] = w1;
1416 wires_[w2->name] = w2;
1417 }
1418
1419 void RTLIL::Module::swap_names(RTLIL::Cell *c1, RTLIL::Cell *c2)
1420 {
1421 log_assert(cells_[c1->name] == c1);
1422 log_assert(cells_[c2->name] == c2);
1423 log_assert(refcount_cells_ == 0);
1424
1425 cells_.erase(c1->name);
1426 cells_.erase(c2->name);
1427
1428 std::swap(c1->name, c2->name);
1429
1430 cells_[c1->name] = c1;
1431 cells_[c2->name] = c2;
1432 }
1433
1434 RTLIL::IdString RTLIL::Module::uniquify(RTLIL::IdString name)
1435 {
1436 int index = 0;
1437 return uniquify(name, index);
1438 }
1439
1440 RTLIL::IdString RTLIL::Module::uniquify(RTLIL::IdString name, int &index)
1441 {
1442 if (index == 0) {
1443 if (count_id(name) == 0)
1444 return name;
1445 index++;
1446 }
1447
1448 while (1) {
1449 RTLIL::IdString new_name = stringf("%s_%d", name.c_str(), index);
1450 if (count_id(new_name) == 0)
1451 return new_name;
1452 index++;
1453 }
1454 }
1455
1456 static bool fixup_ports_compare(const RTLIL::Wire *a, const RTLIL::Wire *b)
1457 {
1458 if (a->port_id && !b->port_id)
1459 return true;
1460 if (!a->port_id && b->port_id)
1461 return false;
1462
1463 if (a->port_id == b->port_id)
1464 return a->name < b->name;
1465 return a->port_id < b->port_id;
1466 }
1467
1468 void RTLIL::Module::connect(const RTLIL::SigSig &conn)
1469 {
1470 for (auto mon : monitors)
1471 mon->notify_connect(this, conn);
1472
1473 if (design)
1474 for (auto mon : design->monitors)
1475 mon->notify_connect(this, conn);
1476
1477 // ignore all attempts to assign constants to other constants
1478 if (conn.first.has_const()) {
1479 RTLIL::SigSig new_conn;
1480 for (int i = 0; i < GetSize(conn.first); i++)
1481 if (conn.first[i].wire) {
1482 new_conn.first.append(conn.first[i]);
1483 new_conn.second.append(conn.second[i]);
1484 }
1485 if (GetSize(new_conn.first))
1486 connect(new_conn);
1487 return;
1488 }
1489
1490 if (yosys_xtrace) {
1491 log("#X# Connect (SigSig) in %s: %s = %s (%d bits)\n", log_id(this), log_signal(conn.first), log_signal(conn.second), GetSize(conn.first));
1492 log_backtrace("-X- ", yosys_xtrace-1);
1493 }
1494
1495 log_assert(GetSize(conn.first) == GetSize(conn.second));
1496 connections_.push_back(conn);
1497 }
1498
1499 void RTLIL::Module::connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs)
1500 {
1501 connect(RTLIL::SigSig(lhs, rhs));
1502 }
1503
1504 void RTLIL::Module::new_connections(const std::vector<RTLIL::SigSig> &new_conn)
1505 {
1506 for (auto mon : monitors)
1507 mon->notify_connect(this, new_conn);
1508
1509 if (design)
1510 for (auto mon : design->monitors)
1511 mon->notify_connect(this, new_conn);
1512
1513 if (yosys_xtrace) {
1514 log("#X# New connections vector in %s:\n", log_id(this));
1515 for (auto &conn: new_conn)
1516 log("#X# %s = %s (%d bits)\n", log_signal(conn.first), log_signal(conn.second), GetSize(conn.first));
1517 log_backtrace("-X- ", yosys_xtrace-1);
1518 }
1519
1520 connections_ = new_conn;
1521 }
1522
1523 const std::vector<RTLIL::SigSig> &RTLIL::Module::connections() const
1524 {
1525 return connections_;
1526 }
1527
1528 void RTLIL::Module::fixup_ports()
1529 {
1530 std::vector<RTLIL::Wire*> all_ports;
1531
1532 for (auto &w : wires_)
1533 if (w.second->port_input || w.second->port_output)
1534 all_ports.push_back(w.second);
1535 else
1536 w.second->port_id = 0;
1537
1538 std::sort(all_ports.begin(), all_ports.end(), fixup_ports_compare);
1539
1540 ports.clear();
1541 for (size_t i = 0; i < all_ports.size(); i++) {
1542 ports.push_back(all_ports[i]->name);
1543 all_ports[i]->port_id = i+1;
1544 }
1545 }
1546
1547 RTLIL::Wire *RTLIL::Module::addWire(RTLIL::IdString name, int width)
1548 {
1549 RTLIL::Wire *wire = new RTLIL::Wire;
1550 wire->name = name;
1551 wire->width = width;
1552 add(wire);
1553 return wire;
1554 }
1555
1556 RTLIL::Wire *RTLIL::Module::addWire(RTLIL::IdString name, const RTLIL::Wire *other)
1557 {
1558 RTLIL::Wire *wire = addWire(name);
1559 wire->width = other->width;
1560 wire->start_offset = other->start_offset;
1561 wire->port_id = other->port_id;
1562 wire->port_input = other->port_input;
1563 wire->port_output = other->port_output;
1564 wire->upto = other->upto;
1565 wire->attributes = other->attributes;
1566 return wire;
1567 }
1568
1569 RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, RTLIL::IdString type)
1570 {
1571 RTLIL::Cell *cell = new RTLIL::Cell;
1572 cell->name = name;
1573 cell->type = type;
1574 add(cell);
1575 return cell;
1576 }
1577
1578 RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, const RTLIL::Cell *other)
1579 {
1580 RTLIL::Cell *cell = addCell(name, other->type);
1581 cell->connections_ = other->connections_;
1582 cell->parameters = other->parameters;
1583 cell->attributes = other->attributes;
1584 return cell;
1585 }
1586
1587 #define DEF_METHOD(_func, _y_size, _type) \
1588 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed) { \
1589 RTLIL::Cell *cell = addCell(name, _type); \
1590 cell->parameters["\\A_SIGNED"] = is_signed; \
1591 cell->parameters["\\A_WIDTH"] = sig_a.size(); \
1592 cell->parameters["\\Y_WIDTH"] = sig_y.size(); \
1593 cell->setPort("\\A", sig_a); \
1594 cell->setPort("\\Y", sig_y); \
1595 return cell; \
1596 } \
1597 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed) { \
1598 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
1599 add ## _func(name, sig_a, sig_y, is_signed); \
1600 return sig_y; \
1601 }
1602 DEF_METHOD(Not, sig_a.size(), "$not")
1603 DEF_METHOD(Pos, sig_a.size(), "$pos")
1604 DEF_METHOD(Neg, sig_a.size(), "$neg")
1605 DEF_METHOD(ReduceAnd, 1, "$reduce_and")
1606 DEF_METHOD(ReduceOr, 1, "$reduce_or")
1607 DEF_METHOD(ReduceXor, 1, "$reduce_xor")
1608 DEF_METHOD(ReduceXnor, 1, "$reduce_xnor")
1609 DEF_METHOD(ReduceBool, 1, "$reduce_bool")
1610 DEF_METHOD(LogicNot, 1, "$logic_not")
1611 #undef DEF_METHOD
1612
1613 #define DEF_METHOD(_func, _y_size, _type) \
1614 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed) { \
1615 RTLIL::Cell *cell = addCell(name, _type); \
1616 cell->parameters["\\A_SIGNED"] = is_signed; \
1617 cell->parameters["\\B_SIGNED"] = is_signed; \
1618 cell->parameters["\\A_WIDTH"] = sig_a.size(); \
1619 cell->parameters["\\B_WIDTH"] = sig_b.size(); \
1620 cell->parameters["\\Y_WIDTH"] = sig_y.size(); \
1621 cell->setPort("\\A", sig_a); \
1622 cell->setPort("\\B", sig_b); \
1623 cell->setPort("\\Y", sig_y); \
1624 return cell; \
1625 } \
1626 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed) { \
1627 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
1628 add ## _func(name, sig_a, sig_b, sig_y, is_signed); \
1629 return sig_y; \
1630 }
1631 DEF_METHOD(And, max(sig_a.size(), sig_b.size()), "$and")
1632 DEF_METHOD(Or, max(sig_a.size(), sig_b.size()), "$or")
1633 DEF_METHOD(Xor, max(sig_a.size(), sig_b.size()), "$xor")
1634 DEF_METHOD(Xnor, max(sig_a.size(), sig_b.size()), "$xnor")
1635 DEF_METHOD(Shl, sig_a.size(), "$shl")
1636 DEF_METHOD(Shr, sig_a.size(), "$shr")
1637 DEF_METHOD(Sshl, sig_a.size(), "$sshl")
1638 DEF_METHOD(Sshr, sig_a.size(), "$sshr")
1639 DEF_METHOD(Shift, sig_a.size(), "$shift")
1640 DEF_METHOD(Shiftx, sig_a.size(), "$shiftx")
1641 DEF_METHOD(Lt, 1, "$lt")
1642 DEF_METHOD(Le, 1, "$le")
1643 DEF_METHOD(Eq, 1, "$eq")
1644 DEF_METHOD(Ne, 1, "$ne")
1645 DEF_METHOD(Eqx, 1, "$eqx")
1646 DEF_METHOD(Nex, 1, "$nex")
1647 DEF_METHOD(Ge, 1, "$ge")
1648 DEF_METHOD(Gt, 1, "$gt")
1649 DEF_METHOD(Add, max(sig_a.size(), sig_b.size()), "$add")
1650 DEF_METHOD(Sub, max(sig_a.size(), sig_b.size()), "$sub")
1651 DEF_METHOD(Mul, max(sig_a.size(), sig_b.size()), "$mul")
1652 DEF_METHOD(Div, max(sig_a.size(), sig_b.size()), "$div")
1653 DEF_METHOD(Mod, max(sig_a.size(), sig_b.size()), "$mod")
1654 DEF_METHOD(LogicAnd, 1, "$logic_and")
1655 DEF_METHOD(LogicOr, 1, "$logic_or")
1656 #undef DEF_METHOD
1657
1658 #define DEF_METHOD(_func, _type, _pmux) \
1659 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, RTLIL::SigSpec sig_y) { \
1660 RTLIL::Cell *cell = addCell(name, _type); \
1661 cell->parameters["\\WIDTH"] = sig_a.size(); \
1662 if (_pmux) cell->parameters["\\S_WIDTH"] = sig_s.size(); \
1663 cell->setPort("\\A", sig_a); \
1664 cell->setPort("\\B", sig_b); \
1665 cell->setPort("\\S", sig_s); \
1666 cell->setPort("\\Y", sig_y); \
1667 return cell; \
1668 } \
1669 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s) { \
1670 RTLIL::SigSpec sig_y = addWire(NEW_ID, sig_a.size()); \
1671 add ## _func(name, sig_a, sig_b, sig_s, sig_y); \
1672 return sig_y; \
1673 }
1674 DEF_METHOD(Mux, "$mux", 0)
1675 DEF_METHOD(Pmux, "$pmux", 1)
1676 #undef DEF_METHOD
1677
1678 #define DEF_METHOD_2(_func, _type, _P1, _P2) \
1679 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2) { \
1680 RTLIL::Cell *cell = addCell(name, _type); \
1681 cell->setPort("\\" #_P1, sig1); \
1682 cell->setPort("\\" #_P2, sig2); \
1683 return cell; \
1684 } \
1685 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1) { \
1686 RTLIL::SigBit sig2 = addWire(NEW_ID); \
1687 add ## _func(name, sig1, sig2); \
1688 return sig2; \
1689 }
1690 #define DEF_METHOD_3(_func, _type, _P1, _P2, _P3) \
1691 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3) { \
1692 RTLIL::Cell *cell = addCell(name, _type); \
1693 cell->setPort("\\" #_P1, sig1); \
1694 cell->setPort("\\" #_P2, sig2); \
1695 cell->setPort("\\" #_P3, sig3); \
1696 return cell; \
1697 } \
1698 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2) { \
1699 RTLIL::SigBit sig3 = addWire(NEW_ID); \
1700 add ## _func(name, sig1, sig2, sig3); \
1701 return sig3; \
1702 }
1703 #define DEF_METHOD_4(_func, _type, _P1, _P2, _P3, _P4) \
1704 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, RTLIL::SigBit sig4) { \
1705 RTLIL::Cell *cell = addCell(name, _type); \
1706 cell->setPort("\\" #_P1, sig1); \
1707 cell->setPort("\\" #_P2, sig2); \
1708 cell->setPort("\\" #_P3, sig3); \
1709 cell->setPort("\\" #_P4, sig4); \
1710 return cell; \
1711 } \
1712 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3) { \
1713 RTLIL::SigBit sig4 = addWire(NEW_ID); \
1714 add ## _func(name, sig1, sig2, sig3, sig4); \
1715 return sig4; \
1716 }
1717 #define DEF_METHOD_5(_func, _type, _P1, _P2, _P3, _P4, _P5) \
1718 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, RTLIL::SigBit sig4, RTLIL::SigBit sig5) { \
1719 RTLIL::Cell *cell = addCell(name, _type); \
1720 cell->setPort("\\" #_P1, sig1); \
1721 cell->setPort("\\" #_P2, sig2); \
1722 cell->setPort("\\" #_P3, sig3); \
1723 cell->setPort("\\" #_P4, sig4); \
1724 cell->setPort("\\" #_P5, sig5); \
1725 return cell; \
1726 } \
1727 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, RTLIL::SigBit sig4) { \
1728 RTLIL::SigBit sig5 = addWire(NEW_ID); \
1729 add ## _func(name, sig1, sig2, sig3, sig4, sig5); \
1730 return sig5; \
1731 }
1732 DEF_METHOD_2(BufGate, "$_BUF_", A, Y)
1733 DEF_METHOD_2(NotGate, "$_NOT_", A, Y)
1734 DEF_METHOD_3(AndGate, "$_AND_", A, B, Y)
1735 DEF_METHOD_3(NandGate, "$_NAND_", A, B, Y)
1736 DEF_METHOD_3(OrGate, "$_OR_", A, B, Y)
1737 DEF_METHOD_3(NorGate, "$_NOR_", A, B, Y)
1738 DEF_METHOD_3(XorGate, "$_XOR_", A, B, Y)
1739 DEF_METHOD_3(XnorGate, "$_XNOR_", A, B, Y)
1740 DEF_METHOD_4(MuxGate, "$_MUX_", A, B, S, Y)
1741 DEF_METHOD_4(Aoi3Gate, "$_AOI3_", A, B, C, Y)
1742 DEF_METHOD_4(Oai3Gate, "$_OAI3_", A, B, C, Y)
1743 DEF_METHOD_5(Aoi4Gate, "$_AOI4_", A, B, C, D, Y)
1744 DEF_METHOD_5(Oai4Gate, "$_OAI4_", A, B, C, D, Y)
1745 #undef DEF_METHOD_2
1746 #undef DEF_METHOD_3
1747 #undef DEF_METHOD_4
1748 #undef DEF_METHOD_5
1749
1750 RTLIL::Cell* RTLIL::Module::addPow(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool a_signed, bool b_signed)
1751 {
1752 RTLIL::Cell *cell = addCell(name, "$pow");
1753 cell->parameters["\\A_SIGNED"] = a_signed;
1754 cell->parameters["\\B_SIGNED"] = b_signed;
1755 cell->parameters["\\A_WIDTH"] = sig_a.size();
1756 cell->parameters["\\B_WIDTH"] = sig_b.size();
1757 cell->parameters["\\Y_WIDTH"] = sig_y.size();
1758 cell->setPort("\\A", sig_a);
1759 cell->setPort("\\B", sig_b);
1760 cell->setPort("\\Y", sig_y);
1761 return cell;
1762 }
1763
1764 RTLIL::Cell* RTLIL::Module::addSlice(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, RTLIL::Const offset)
1765 {
1766 RTLIL::Cell *cell = addCell(name, "$slice");
1767 cell->parameters["\\A_WIDTH"] = sig_a.size();
1768 cell->parameters["\\Y_WIDTH"] = sig_y.size();
1769 cell->parameters["\\OFFSET"] = offset;
1770 cell->setPort("\\A", sig_a);
1771 cell->setPort("\\Y", sig_y);
1772 return cell;
1773 }
1774
1775 RTLIL::Cell* RTLIL::Module::addConcat(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y)
1776 {
1777 RTLIL::Cell *cell = addCell(name, "$concat");
1778 cell->parameters["\\A_WIDTH"] = sig_a.size();
1779 cell->parameters["\\B_WIDTH"] = sig_b.size();
1780 cell->setPort("\\A", sig_a);
1781 cell->setPort("\\B", sig_b);
1782 cell->setPort("\\Y", sig_y);
1783 return cell;
1784 }
1785
1786 RTLIL::Cell* RTLIL::Module::addLut(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, RTLIL::Const lut)
1787 {
1788 RTLIL::Cell *cell = addCell(name, "$lut");
1789 cell->parameters["\\LUT"] = lut;
1790 cell->parameters["\\WIDTH"] = sig_a.size();
1791 cell->setPort("\\A", sig_a);
1792 cell->setPort("\\Y", sig_y);
1793 return cell;
1794 }
1795
1796 RTLIL::Cell* RTLIL::Module::addTribuf(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_y)
1797 {
1798 RTLIL::Cell *cell = addCell(name, "$tribuf");
1799 cell->parameters["\\WIDTH"] = sig_a.size();
1800 cell->setPort("\\A", sig_a);
1801 cell->setPort("\\EN", sig_en);
1802 cell->setPort("\\Y", sig_y);
1803 return cell;
1804 }
1805
1806 RTLIL::Cell* RTLIL::Module::addAssert(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en)
1807 {
1808 RTLIL::Cell *cell = addCell(name, "$assert");
1809 cell->setPort("\\A", sig_a);
1810 cell->setPort("\\EN", sig_en);
1811 return cell;
1812 }
1813
1814 RTLIL::Cell* RTLIL::Module::addAssume(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en)
1815 {
1816 RTLIL::Cell *cell = addCell(name, "$assume");
1817 cell->setPort("\\A", sig_a);
1818 cell->setPort("\\EN", sig_en);
1819 return cell;
1820 }
1821
1822 RTLIL::Cell* RTLIL::Module::addEquiv(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y)
1823 {
1824 RTLIL::Cell *cell = addCell(name, "$equiv");
1825 cell->setPort("\\A", sig_a);
1826 cell->setPort("\\B", sig_b);
1827 cell->setPort("\\Y", sig_y);
1828 return cell;
1829 }
1830
1831 RTLIL::Cell* RTLIL::Module::addSr(RTLIL::IdString name, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr, RTLIL::SigSpec sig_q, bool set_polarity, bool clr_polarity)
1832 {
1833 RTLIL::Cell *cell = addCell(name, "$sr");
1834 cell->parameters["\\SET_POLARITY"] = set_polarity;
1835 cell->parameters["\\CLR_POLARITY"] = clr_polarity;
1836 cell->parameters["\\WIDTH"] = sig_q.size();
1837 cell->setPort("\\SET", sig_set);
1838 cell->setPort("\\CLR", sig_clr);
1839 cell->setPort("\\Q", sig_q);
1840 return cell;
1841 }
1842
1843 RTLIL::Cell* RTLIL::Module::addFf(RTLIL::IdString name, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q)
1844 {
1845 RTLIL::Cell *cell = addCell(name, "$ff");
1846 cell->parameters["\\WIDTH"] = sig_q.size();
1847 cell->setPort("\\D", sig_d);
1848 cell->setPort("\\Q", sig_q);
1849 return cell;
1850 }
1851
1852 RTLIL::Cell* RTLIL::Module::addDff(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity)
1853 {
1854 RTLIL::Cell *cell = addCell(name, "$dff");
1855 cell->parameters["\\CLK_POLARITY"] = clk_polarity;
1856 cell->parameters["\\WIDTH"] = sig_q.size();
1857 cell->setPort("\\CLK", sig_clk);
1858 cell->setPort("\\D", sig_d);
1859 cell->setPort("\\Q", sig_q);
1860 return cell;
1861 }
1862
1863 RTLIL::Cell* RTLIL::Module::addDffe(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, bool en_polarity)
1864 {
1865 RTLIL::Cell *cell = addCell(name, "$dffe");
1866 cell->parameters["\\CLK_POLARITY"] = clk_polarity;
1867 cell->parameters["\\EN_POLARITY"] = en_polarity;
1868 cell->parameters["\\WIDTH"] = sig_q.size();
1869 cell->setPort("\\CLK", sig_clk);
1870 cell->setPort("\\EN", sig_en);
1871 cell->setPort("\\D", sig_d);
1872 cell->setPort("\\Q", sig_q);
1873 return cell;
1874 }
1875
1876 RTLIL::Cell* RTLIL::Module::addDffsr(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
1877 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity)
1878 {
1879 RTLIL::Cell *cell = addCell(name, "$dffsr");
1880 cell->parameters["\\CLK_POLARITY"] = clk_polarity;
1881 cell->parameters["\\SET_POLARITY"] = set_polarity;
1882 cell->parameters["\\CLR_POLARITY"] = clr_polarity;
1883 cell->parameters["\\WIDTH"] = sig_q.size();
1884 cell->setPort("\\CLK", sig_clk);
1885 cell->setPort("\\SET", sig_set);
1886 cell->setPort("\\CLR", sig_clr);
1887 cell->setPort("\\D", sig_d);
1888 cell->setPort("\\Q", sig_q);
1889 return cell;
1890 }
1891
1892 RTLIL::Cell* RTLIL::Module::addAdff(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_arst, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q,
1893 RTLIL::Const arst_value, bool clk_polarity, bool arst_polarity)
1894 {
1895 RTLIL::Cell *cell = addCell(name, "$adff");
1896 cell->parameters["\\CLK_POLARITY"] = clk_polarity;
1897 cell->parameters["\\ARST_POLARITY"] = arst_polarity;
1898 cell->parameters["\\ARST_VALUE"] = arst_value;
1899 cell->parameters["\\WIDTH"] = sig_q.size();
1900 cell->setPort("\\CLK", sig_clk);
1901 cell->setPort("\\ARST", sig_arst);
1902 cell->setPort("\\D", sig_d);
1903 cell->setPort("\\Q", sig_q);
1904 return cell;
1905 }
1906
1907 RTLIL::Cell* RTLIL::Module::addDlatch(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity)
1908 {
1909 RTLIL::Cell *cell = addCell(name, "$dlatch");
1910 cell->parameters["\\EN_POLARITY"] = en_polarity;
1911 cell->parameters["\\WIDTH"] = sig_q.size();
1912 cell->setPort("\\EN", sig_en);
1913 cell->setPort("\\D", sig_d);
1914 cell->setPort("\\Q", sig_q);
1915 return cell;
1916 }
1917
1918 RTLIL::Cell* RTLIL::Module::addDlatchsr(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
1919 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity, bool set_polarity, bool clr_polarity)
1920 {
1921 RTLIL::Cell *cell = addCell(name, "$dlatchsr");
1922 cell->parameters["\\EN_POLARITY"] = en_polarity;
1923 cell->parameters["\\SET_POLARITY"] = set_polarity;
1924 cell->parameters["\\CLR_POLARITY"] = clr_polarity;
1925 cell->parameters["\\WIDTH"] = sig_q.size();
1926 cell->setPort("\\EN", sig_en);
1927 cell->setPort("\\SET", sig_set);
1928 cell->setPort("\\CLR", sig_clr);
1929 cell->setPort("\\D", sig_d);
1930 cell->setPort("\\Q", sig_q);
1931 return cell;
1932 }
1933
1934 RTLIL::Cell* RTLIL::Module::addFfGate(RTLIL::IdString name, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q)
1935 {
1936 RTLIL::Cell *cell = addCell(name, "$_FF_");
1937 cell->setPort("\\D", sig_d);
1938 cell->setPort("\\Q", sig_q);
1939 return cell;
1940 }
1941
1942 RTLIL::Cell* RTLIL::Module::addDffGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity)
1943 {
1944 RTLIL::Cell *cell = addCell(name, stringf("$_DFF_%c_", clk_polarity ? 'P' : 'N'));
1945 cell->setPort("\\C", sig_clk);
1946 cell->setPort("\\D", sig_d);
1947 cell->setPort("\\Q", sig_q);
1948 return cell;
1949 }
1950
1951 RTLIL::Cell* RTLIL::Module::addDffeGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, bool en_polarity)
1952 {
1953 RTLIL::Cell *cell = addCell(name, stringf("$_DFFE_%c%c_", clk_polarity ? 'P' : 'N', en_polarity ? 'P' : 'N'));
1954 cell->setPort("\\C", sig_clk);
1955 cell->setPort("\\E", sig_en);
1956 cell->setPort("\\D", sig_d);
1957 cell->setPort("\\Q", sig_q);
1958 return cell;
1959 }
1960
1961 RTLIL::Cell* RTLIL::Module::addDffsrGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
1962 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity)
1963 {
1964 RTLIL::Cell *cell = addCell(name, stringf("$_DFFSR_%c%c%c_", clk_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N'));
1965 cell->setPort("\\C", sig_clk);
1966 cell->setPort("\\S", sig_set);
1967 cell->setPort("\\R", sig_clr);
1968 cell->setPort("\\D", sig_d);
1969 cell->setPort("\\Q", sig_q);
1970 return cell;
1971 }
1972
1973 RTLIL::Cell* RTLIL::Module::addAdffGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_arst, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q,
1974 bool arst_value, bool clk_polarity, bool arst_polarity)
1975 {
1976 RTLIL::Cell *cell = addCell(name, stringf("$_DFF_%c%c%c_", clk_polarity ? 'P' : 'N', arst_polarity ? 'P' : 'N', arst_value ? '1' : '0'));
1977 cell->setPort("\\C", sig_clk);
1978 cell->setPort("\\R", sig_arst);
1979 cell->setPort("\\D", sig_d);
1980 cell->setPort("\\Q", sig_q);
1981 return cell;
1982 }
1983
1984 RTLIL::Cell* RTLIL::Module::addDlatchGate(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity)
1985 {
1986 RTLIL::Cell *cell = addCell(name, stringf("$_DLATCH_%c_", en_polarity ? 'P' : 'N'));
1987 cell->setPort("\\E", sig_en);
1988 cell->setPort("\\D", sig_d);
1989 cell->setPort("\\Q", sig_q);
1990 return cell;
1991 }
1992
1993 RTLIL::Cell* RTLIL::Module::addDlatchsrGate(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
1994 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity, bool set_polarity, bool clr_polarity)
1995 {
1996 RTLIL::Cell *cell = addCell(name, stringf("$_DLATCHSR_%c%c%c_", en_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N'));
1997 cell->setPort("\\E", sig_en);
1998 cell->setPort("\\S", sig_set);
1999 cell->setPort("\\R", sig_clr);
2000 cell->setPort("\\D", sig_d);
2001 cell->setPort("\\Q", sig_q);
2002 return cell;
2003 }
2004
2005 RTLIL::SigSpec RTLIL::Module::Anyconst(RTLIL::IdString name, int width)
2006 {
2007 RTLIL::SigSpec sig = addWire(NEW_ID, width);
2008 Cell *cell = addCell(name, "$anyconst");
2009 cell->setParam("\\WIDTH", width);
2010 cell->setPort("\\Y", sig);
2011 return sig;
2012 }
2013
2014 RTLIL::SigSpec RTLIL::Module::Anyseq(RTLIL::IdString name, int width)
2015 {
2016 RTLIL::SigSpec sig = addWire(NEW_ID, width);
2017 Cell *cell = addCell(name, "$anyseq");
2018 cell->setParam("\\WIDTH", width);
2019 cell->setPort("\\Y", sig);
2020 return sig;
2021 }
2022
2023 RTLIL::SigSpec RTLIL::Module::Initstate(RTLIL::IdString name)
2024 {
2025 RTLIL::SigSpec sig = addWire(NEW_ID);
2026 Cell *cell = addCell(name, "$initstate");
2027 cell->setPort("\\Y", sig);
2028 return sig;
2029 }
2030
2031 RTLIL::Wire::Wire()
2032 {
2033 static unsigned int hashidx_count = 123456789;
2034 hashidx_count = mkhash_xorshift(hashidx_count);
2035 hashidx_ = hashidx_count;
2036
2037 module = nullptr;
2038 width = 1;
2039 start_offset = 0;
2040 port_id = 0;
2041 port_input = false;
2042 port_output = false;
2043 upto = false;
2044 }
2045
2046 RTLIL::Memory::Memory()
2047 {
2048 static unsigned int hashidx_count = 123456789;
2049 hashidx_count = mkhash_xorshift(hashidx_count);
2050 hashidx_ = hashidx_count;
2051
2052 width = 1;
2053 size = 0;
2054 }
2055
2056 RTLIL::Cell::Cell() : module(nullptr)
2057 {
2058 static unsigned int hashidx_count = 123456789;
2059 hashidx_count = mkhash_xorshift(hashidx_count);
2060 hashidx_ = hashidx_count;
2061
2062 // log("#memtrace# %p\n", this);
2063 memhasher();
2064 }
2065
2066 bool RTLIL::Cell::hasPort(RTLIL::IdString portname) const
2067 {
2068 return connections_.count(portname) != 0;
2069 }
2070
2071 void RTLIL::Cell::unsetPort(RTLIL::IdString portname)
2072 {
2073 RTLIL::SigSpec signal;
2074 auto conn_it = connections_.find(portname);
2075
2076 if (conn_it != connections_.end())
2077 {
2078 for (auto mon : module->monitors)
2079 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
2080
2081 if (module->design)
2082 for (auto mon : module->design->monitors)
2083 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
2084
2085 if (yosys_xtrace) {
2086 log("#X# Unconnect %s.%s.%s\n", log_id(this->module), log_id(this), log_id(portname));
2087 log_backtrace("-X- ", yosys_xtrace-1);
2088 }
2089
2090 connections_.erase(conn_it);
2091 }
2092 }
2093
2094 void RTLIL::Cell::setPort(RTLIL::IdString portname, RTLIL::SigSpec signal)
2095 {
2096 auto conn_it = connections_.find(portname);
2097
2098 if (conn_it == connections_.end()) {
2099 connections_[portname] = RTLIL::SigSpec();
2100 conn_it = connections_.find(portname);
2101 log_assert(conn_it != connections_.end());
2102 } else
2103 if (conn_it->second == signal)
2104 return;
2105
2106 for (auto mon : module->monitors)
2107 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
2108
2109 if (module->design)
2110 for (auto mon : module->design->monitors)
2111 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
2112
2113 if (yosys_xtrace) {
2114 log("#X# Connect %s.%s.%s = %s (%d)\n", log_id(this->module), log_id(this), log_id(portname), log_signal(signal), GetSize(signal));
2115 log_backtrace("-X- ", yosys_xtrace-1);
2116 }
2117
2118 conn_it->second = signal;
2119 }
2120
2121 const RTLIL::SigSpec &RTLIL::Cell::getPort(RTLIL::IdString portname) const
2122 {
2123 return connections_.at(portname);
2124 }
2125
2126 const dict<RTLIL::IdString, RTLIL::SigSpec> &RTLIL::Cell::connections() const
2127 {
2128 return connections_;
2129 }
2130
2131 bool RTLIL::Cell::known() const
2132 {
2133 if (yosys_celltypes.cell_known(type))
2134 return true;
2135 if (module && module->design && module->design->module(type))
2136 return true;
2137 return false;
2138 }
2139
2140 bool RTLIL::Cell::input(RTLIL::IdString portname) const
2141 {
2142 if (yosys_celltypes.cell_known(type))
2143 return yosys_celltypes.cell_input(type, portname);
2144 if (module && module->design) {
2145 RTLIL::Module *m = module->design->module(type);
2146 RTLIL::Wire *w = m ? m->wire(portname) : nullptr;
2147 return w && w->port_input;
2148 }
2149 return false;
2150 }
2151
2152 bool RTLIL::Cell::output(RTLIL::IdString portname) const
2153 {
2154 if (yosys_celltypes.cell_known(type))
2155 return yosys_celltypes.cell_output(type, portname);
2156 if (module && module->design) {
2157 RTLIL::Module *m = module->design->module(type);
2158 RTLIL::Wire *w = m ? m->wire(portname) : nullptr;
2159 return w && w->port_output;
2160 }
2161 return false;
2162 }
2163
2164 bool RTLIL::Cell::hasParam(RTLIL::IdString paramname) const
2165 {
2166 return parameters.count(paramname) != 0;
2167 }
2168
2169 void RTLIL::Cell::unsetParam(RTLIL::IdString paramname)
2170 {
2171 parameters.erase(paramname);
2172 }
2173
2174 void RTLIL::Cell::setParam(RTLIL::IdString paramname, RTLIL::Const value)
2175 {
2176 parameters[paramname] = value;
2177 }
2178
2179 const RTLIL::Const &RTLIL::Cell::getParam(RTLIL::IdString paramname) const
2180 {
2181 return parameters.at(paramname);
2182 }
2183
2184 void RTLIL::Cell::sort()
2185 {
2186 connections_.sort(sort_by_id_str());
2187 parameters.sort(sort_by_id_str());
2188 attributes.sort(sort_by_id_str());
2189 }
2190
2191 void RTLIL::Cell::check()
2192 {
2193 #ifndef NDEBUG
2194 InternalCellChecker checker(NULL, this);
2195 checker.check();
2196 #endif
2197 }
2198
2199 void RTLIL::Cell::fixup_parameters(bool set_a_signed, bool set_b_signed)
2200 {
2201 if (type.substr(0, 1) != "$" || type.substr(0, 2) == "$_" || type.substr(0, 8) == "$paramod" ||
2202 type.substr(0, 9) == "$verific$" || type.substr(0, 7) == "$array:" || type.substr(0, 8) == "$extern:")
2203 return;
2204
2205 if (type == "$mux" || type == "$pmux") {
2206 parameters["\\WIDTH"] = GetSize(connections_["\\Y"]);
2207 if (type == "$pmux")
2208 parameters["\\S_WIDTH"] = GetSize(connections_["\\S"]);
2209 check();
2210 return;
2211 }
2212
2213 if (type == "$lut" || type == "$sop") {
2214 parameters["\\WIDTH"] = GetSize(connections_["\\A"]);
2215 return;
2216 }
2217
2218 if (type == "$fa") {
2219 parameters["\\WIDTH"] = GetSize(connections_["\\Y"]);
2220 return;
2221 }
2222
2223 if (type == "$lcu") {
2224 parameters["\\WIDTH"] = GetSize(connections_["\\CO"]);
2225 return;
2226 }
2227
2228 bool signedness_ab = !type.in("$slice", "$concat", "$macc");
2229
2230 if (connections_.count("\\A")) {
2231 if (signedness_ab) {
2232 if (set_a_signed)
2233 parameters["\\A_SIGNED"] = true;
2234 else if (parameters.count("\\A_SIGNED") == 0)
2235 parameters["\\A_SIGNED"] = false;
2236 }
2237 parameters["\\A_WIDTH"] = GetSize(connections_["\\A"]);
2238 }
2239
2240 if (connections_.count("\\B")) {
2241 if (signedness_ab) {
2242 if (set_b_signed)
2243 parameters["\\B_SIGNED"] = true;
2244 else if (parameters.count("\\B_SIGNED") == 0)
2245 parameters["\\B_SIGNED"] = false;
2246 }
2247 parameters["\\B_WIDTH"] = GetSize(connections_["\\B"]);
2248 }
2249
2250 if (connections_.count("\\Y"))
2251 parameters["\\Y_WIDTH"] = GetSize(connections_["\\Y"]);
2252
2253 check();
2254 }
2255
2256 RTLIL::SigChunk::SigChunk()
2257 {
2258 wire = NULL;
2259 width = 0;
2260 offset = 0;
2261 }
2262
2263 RTLIL::SigChunk::SigChunk(const RTLIL::Const &value)
2264 {
2265 wire = NULL;
2266 data = value.bits;
2267 width = GetSize(data);
2268 offset = 0;
2269 }
2270
2271 RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire)
2272 {
2273 log_assert(wire != nullptr);
2274 this->wire = wire;
2275 this->width = wire->width;
2276 this->offset = 0;
2277 }
2278
2279 RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire, int offset, int width)
2280 {
2281 log_assert(wire != nullptr);
2282 this->wire = wire;
2283 this->width = width;
2284 this->offset = offset;
2285 }
2286
2287 RTLIL::SigChunk::SigChunk(const std::string &str)
2288 {
2289 wire = NULL;
2290 data = RTLIL::Const(str).bits;
2291 width = GetSize(data);
2292 offset = 0;
2293 }
2294
2295 RTLIL::SigChunk::SigChunk(int val, int width)
2296 {
2297 wire = NULL;
2298 data = RTLIL::Const(val, width).bits;
2299 this->width = GetSize(data);
2300 offset = 0;
2301 }
2302
2303 RTLIL::SigChunk::SigChunk(RTLIL::State bit, int width)
2304 {
2305 wire = NULL;
2306 data = RTLIL::Const(bit, width).bits;
2307 this->width = GetSize(data);
2308 offset = 0;
2309 }
2310
2311 RTLIL::SigChunk::SigChunk(RTLIL::SigBit bit)
2312 {
2313 wire = bit.wire;
2314 offset = 0;
2315 if (wire == NULL)
2316 data = RTLIL::Const(bit.data).bits;
2317 else
2318 offset = bit.offset;
2319 width = 1;
2320 }
2321
2322 RTLIL::SigChunk RTLIL::SigChunk::extract(int offset, int length) const
2323 {
2324 RTLIL::SigChunk ret;
2325 if (wire) {
2326 ret.wire = wire;
2327 ret.offset = this->offset + offset;
2328 ret.width = length;
2329 } else {
2330 for (int i = 0; i < length; i++)
2331 ret.data.push_back(data[offset+i]);
2332 ret.width = length;
2333 }
2334 return ret;
2335 }
2336
2337 bool RTLIL::SigChunk::operator <(const RTLIL::SigChunk &other) const
2338 {
2339 if (wire && other.wire)
2340 if (wire->name != other.wire->name)
2341 return wire->name < other.wire->name;
2342
2343 if (wire != other.wire)
2344 return wire < other.wire;
2345
2346 if (offset != other.offset)
2347 return offset < other.offset;
2348
2349 if (width != other.width)
2350 return width < other.width;
2351
2352 return data < other.data;
2353 }
2354
2355 bool RTLIL::SigChunk::operator ==(const RTLIL::SigChunk &other) const
2356 {
2357 return wire == other.wire && width == other.width && offset == other.offset && data == other.data;
2358 }
2359
2360 bool RTLIL::SigChunk::operator !=(const RTLIL::SigChunk &other) const
2361 {
2362 if (*this == other)
2363 return false;
2364 return true;
2365 }
2366
2367 RTLIL::SigSpec::SigSpec()
2368 {
2369 width_ = 0;
2370 hash_ = 0;
2371 }
2372
2373 RTLIL::SigSpec::SigSpec(const RTLIL::SigSpec &other)
2374 {
2375 *this = other;
2376 }
2377
2378 RTLIL::SigSpec::SigSpec(std::initializer_list<RTLIL::SigSpec> parts)
2379 {
2380 cover("kernel.rtlil.sigspec.init.list");
2381
2382 width_ = 0;
2383 hash_ = 0;
2384
2385 std::vector<RTLIL::SigSpec> parts_vec(parts.begin(), parts.end());
2386 for (auto it = parts_vec.rbegin(); it != parts_vec.rend(); it++)
2387 append(*it);
2388 }
2389
2390 const RTLIL::SigSpec &RTLIL::SigSpec::operator=(const RTLIL::SigSpec &other)
2391 {
2392 cover("kernel.rtlil.sigspec.assign");
2393
2394 width_ = other.width_;
2395 hash_ = other.hash_;
2396 chunks_ = other.chunks_;
2397 bits_.clear();
2398
2399 if (!other.bits_.empty())
2400 {
2401 RTLIL::SigChunk *last = NULL;
2402 int last_end_offset = 0;
2403
2404 for (auto &bit : other.bits_) {
2405 if (last && bit.wire == last->wire) {
2406 if (bit.wire == NULL) {
2407 last->data.push_back(bit.data);
2408 last->width++;
2409 continue;
2410 } else if (last_end_offset == bit.offset) {
2411 last_end_offset++;
2412 last->width++;
2413 continue;
2414 }
2415 }
2416 chunks_.push_back(bit);
2417 last = &chunks_.back();
2418 last_end_offset = bit.offset + 1;
2419 }
2420
2421 check();
2422 }
2423
2424 return *this;
2425 }
2426
2427 RTLIL::SigSpec::SigSpec(const RTLIL::Const &value)
2428 {
2429 cover("kernel.rtlil.sigspec.init.const");
2430
2431 chunks_.push_back(RTLIL::SigChunk(value));
2432 width_ = chunks_.back().width;
2433 hash_ = 0;
2434 check();
2435 }
2436
2437 RTLIL::SigSpec::SigSpec(const RTLIL::SigChunk &chunk)
2438 {
2439 cover("kernel.rtlil.sigspec.init.chunk");
2440
2441 chunks_.push_back(chunk);
2442 width_ = chunks_.back().width;
2443 hash_ = 0;
2444 check();
2445 }
2446
2447 RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire)
2448 {
2449 cover("kernel.rtlil.sigspec.init.wire");
2450
2451 chunks_.push_back(RTLIL::SigChunk(wire));
2452 width_ = chunks_.back().width;
2453 hash_ = 0;
2454 check();
2455 }
2456
2457 RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire, int offset, int width)
2458 {
2459 cover("kernel.rtlil.sigspec.init.wire_part");
2460
2461 chunks_.push_back(RTLIL::SigChunk(wire, offset, width));
2462 width_ = chunks_.back().width;
2463 hash_ = 0;
2464 check();
2465 }
2466
2467 RTLIL::SigSpec::SigSpec(const std::string &str)
2468 {
2469 cover("kernel.rtlil.sigspec.init.str");
2470
2471 chunks_.push_back(RTLIL::SigChunk(str));
2472 width_ = chunks_.back().width;
2473 hash_ = 0;
2474 check();
2475 }
2476
2477 RTLIL::SigSpec::SigSpec(int val, int width)
2478 {
2479 cover("kernel.rtlil.sigspec.init.int");
2480
2481 chunks_.push_back(RTLIL::SigChunk(val, width));
2482 width_ = width;
2483 hash_ = 0;
2484 check();
2485 }
2486
2487 RTLIL::SigSpec::SigSpec(RTLIL::State bit, int width)
2488 {
2489 cover("kernel.rtlil.sigspec.init.state");
2490
2491 chunks_.push_back(RTLIL::SigChunk(bit, width));
2492 width_ = width;
2493 hash_ = 0;
2494 check();
2495 }
2496
2497 RTLIL::SigSpec::SigSpec(RTLIL::SigBit bit, int width)
2498 {
2499 cover("kernel.rtlil.sigspec.init.bit");
2500
2501 if (bit.wire == NULL)
2502 chunks_.push_back(RTLIL::SigChunk(bit.data, width));
2503 else
2504 for (int i = 0; i < width; i++)
2505 chunks_.push_back(bit);
2506 width_ = width;
2507 hash_ = 0;
2508 check();
2509 }
2510
2511 RTLIL::SigSpec::SigSpec(std::vector<RTLIL::SigChunk> chunks)
2512 {
2513 cover("kernel.rtlil.sigspec.init.stdvec_chunks");
2514
2515 width_ = 0;
2516 hash_ = 0;
2517 for (auto &c : chunks)
2518 append(c);
2519 check();
2520 }
2521
2522 RTLIL::SigSpec::SigSpec(std::vector<RTLIL::SigBit> bits)
2523 {
2524 cover("kernel.rtlil.sigspec.init.stdvec_bits");
2525
2526 width_ = 0;
2527 hash_ = 0;
2528 for (auto &bit : bits)
2529 append_bit(bit);
2530 check();
2531 }
2532
2533 RTLIL::SigSpec::SigSpec(pool<RTLIL::SigBit> bits)
2534 {
2535 cover("kernel.rtlil.sigspec.init.pool_bits");
2536
2537 width_ = 0;
2538 hash_ = 0;
2539 for (auto &bit : bits)
2540 append_bit(bit);
2541 check();
2542 }
2543
2544 RTLIL::SigSpec::SigSpec(std::set<RTLIL::SigBit> bits)
2545 {
2546 cover("kernel.rtlil.sigspec.init.stdset_bits");
2547
2548 width_ = 0;
2549 hash_ = 0;
2550 for (auto &bit : bits)
2551 append_bit(bit);
2552 check();
2553 }
2554
2555 RTLIL::SigSpec::SigSpec(bool bit)
2556 {
2557 cover("kernel.rtlil.sigspec.init.bool");
2558
2559 width_ = 0;
2560 hash_ = 0;
2561 append_bit(bit);
2562 check();
2563 }
2564
2565 void RTLIL::SigSpec::pack() const
2566 {
2567 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
2568
2569 if (that->bits_.empty())
2570 return;
2571
2572 cover("kernel.rtlil.sigspec.convert.pack");
2573 log_assert(that->chunks_.empty());
2574
2575 std::vector<RTLIL::SigBit> old_bits;
2576 old_bits.swap(that->bits_);
2577
2578 RTLIL::SigChunk *last = NULL;
2579 int last_end_offset = 0;
2580
2581 for (auto &bit : old_bits) {
2582 if (last && bit.wire == last->wire) {
2583 if (bit.wire == NULL) {
2584 last->data.push_back(bit.data);
2585 last->width++;
2586 continue;
2587 } else if (last_end_offset == bit.offset) {
2588 last_end_offset++;
2589 last->width++;
2590 continue;
2591 }
2592 }
2593 that->chunks_.push_back(bit);
2594 last = &that->chunks_.back();
2595 last_end_offset = bit.offset + 1;
2596 }
2597
2598 check();
2599 }
2600
2601 void RTLIL::SigSpec::unpack() const
2602 {
2603 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
2604
2605 if (that->chunks_.empty())
2606 return;
2607
2608 cover("kernel.rtlil.sigspec.convert.unpack");
2609 log_assert(that->bits_.empty());
2610
2611 that->bits_.reserve(that->width_);
2612 for (auto &c : that->chunks_)
2613 for (int i = 0; i < c.width; i++)
2614 that->bits_.push_back(RTLIL::SigBit(c, i));
2615
2616 that->chunks_.clear();
2617 that->hash_ = 0;
2618 }
2619
2620 void RTLIL::SigSpec::updhash() const
2621 {
2622 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
2623
2624 if (that->hash_ != 0)
2625 return;
2626
2627 cover("kernel.rtlil.sigspec.hash");
2628 that->pack();
2629
2630 that->hash_ = mkhash_init;
2631 for (auto &c : that->chunks_)
2632 if (c.wire == NULL) {
2633 for (auto &v : c.data)
2634 that->hash_ = mkhash(that->hash_, v);
2635 } else {
2636 that->hash_ = mkhash(that->hash_, c.wire->name.index_);
2637 that->hash_ = mkhash(that->hash_, c.offset);
2638 that->hash_ = mkhash(that->hash_, c.width);
2639 }
2640
2641 if (that->hash_ == 0)
2642 that->hash_ = 1;
2643 }
2644
2645 void RTLIL::SigSpec::sort()
2646 {
2647 unpack();
2648 cover("kernel.rtlil.sigspec.sort");
2649 std::sort(bits_.begin(), bits_.end());
2650 }
2651
2652 void RTLIL::SigSpec::sort_and_unify()
2653 {
2654 unpack();
2655 cover("kernel.rtlil.sigspec.sort_and_unify");
2656
2657 // A copy of the bits vector is used to prevent duplicating the logic from
2658 // SigSpec::SigSpec(std::vector<SigBit>). This incurrs an extra copy but
2659 // that isn't showing up as significant in profiles.
2660 std::vector<SigBit> unique_bits = bits_;
2661 std::sort(unique_bits.begin(), unique_bits.end());
2662 auto last = std::unique(unique_bits.begin(), unique_bits.end());
2663 unique_bits.erase(last, unique_bits.end());
2664
2665 *this = unique_bits;
2666 }
2667
2668 void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with)
2669 {
2670 replace(pattern, with, this);
2671 }
2672
2673 void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with, RTLIL::SigSpec *other) const
2674 {
2675 log_assert(other != NULL);
2676 log_assert(width_ == other->width_);
2677 log_assert(pattern.width_ == with.width_);
2678
2679 pattern.unpack();
2680 with.unpack();
2681 unpack();
2682 other->unpack();
2683
2684 for (int i = 0; i < GetSize(pattern.bits_); i++) {
2685 if (pattern.bits_[i].wire != NULL) {
2686 for (int j = 0; j < GetSize(bits_); j++) {
2687 if (bits_[j] == pattern.bits_[i]) {
2688 other->bits_[j] = with.bits_[i];
2689 }
2690 }
2691 }
2692 }
2693
2694 other->check();
2695 }
2696
2697 void RTLIL::SigSpec::replace(const dict<RTLIL::SigBit, RTLIL::SigBit> &rules)
2698 {
2699 replace(rules, this);
2700 }
2701
2702 void RTLIL::SigSpec::replace(const dict<RTLIL::SigBit, RTLIL::SigBit> &rules, RTLIL::SigSpec *other) const
2703 {
2704 cover("kernel.rtlil.sigspec.replace_dict");
2705
2706 log_assert(other != NULL);
2707 log_assert(width_ == other->width_);
2708
2709 unpack();
2710 other->unpack();
2711
2712 for (int i = 0; i < GetSize(bits_); i++) {
2713 auto it = rules.find(bits_[i]);
2714 if (it != rules.end())
2715 other->bits_[i] = it->second;
2716 }
2717
2718 other->check();
2719 }
2720
2721 void RTLIL::SigSpec::replace(const std::map<RTLIL::SigBit, RTLIL::SigBit> &rules)
2722 {
2723 replace(rules, this);
2724 }
2725
2726 void RTLIL::SigSpec::replace(const std::map<RTLIL::SigBit, RTLIL::SigBit> &rules, RTLIL::SigSpec *other) const
2727 {
2728 cover("kernel.rtlil.sigspec.replace_map");
2729
2730 log_assert(other != NULL);
2731 log_assert(width_ == other->width_);
2732
2733 unpack();
2734 other->unpack();
2735
2736 for (int i = 0; i < GetSize(bits_); i++) {
2737 auto it = rules.find(bits_[i]);
2738 if (it != rules.end())
2739 other->bits_[i] = it->second;
2740 }
2741
2742 other->check();
2743 }
2744
2745 void RTLIL::SigSpec::remove(const RTLIL::SigSpec &pattern)
2746 {
2747 remove2(pattern, NULL);
2748 }
2749
2750 void RTLIL::SigSpec::remove(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other) const
2751 {
2752 RTLIL::SigSpec tmp = *this;
2753 tmp.remove2(pattern, other);
2754 }
2755
2756 void RTLIL::SigSpec::remove2(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other)
2757 {
2758 if (other)
2759 cover("kernel.rtlil.sigspec.remove_other");
2760 else
2761 cover("kernel.rtlil.sigspec.remove");
2762
2763 unpack();
2764 if (other != NULL) {
2765 log_assert(width_ == other->width_);
2766 other->unpack();
2767 }
2768
2769 for (int i = GetSize(bits_) - 1; i >= 0; i--) {
2770 if (bits_[i].wire == NULL) continue;
2771
2772 for (auto &pattern_chunk : pattern.chunks()) {
2773 if (bits_[i].wire == pattern_chunk.wire &&
2774 bits_[i].offset >= pattern_chunk.offset &&
2775 bits_[i].offset < pattern_chunk.offset + pattern_chunk.width) {
2776 bits_.erase(bits_.begin() + i);
2777 width_--;
2778 if (other != NULL) {
2779 other->bits_.erase(other->bits_.begin() + i);
2780 other->width_--;
2781 }
2782 }
2783 }
2784 }
2785
2786 check();
2787 }
2788
2789 void RTLIL::SigSpec::remove(const pool<RTLIL::SigBit> &pattern)
2790 {
2791 remove2(pattern, NULL);
2792 }
2793
2794 void RTLIL::SigSpec::remove(const pool<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other) const
2795 {
2796 RTLIL::SigSpec tmp = *this;
2797 tmp.remove2(pattern, other);
2798 }
2799
2800 void RTLIL::SigSpec::remove2(const pool<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other)
2801 {
2802 if (other)
2803 cover("kernel.rtlil.sigspec.remove_other");
2804 else
2805 cover("kernel.rtlil.sigspec.remove");
2806
2807 unpack();
2808
2809 if (other != NULL) {
2810 log_assert(width_ == other->width_);
2811 other->unpack();
2812 }
2813
2814 for (int i = GetSize(bits_) - 1; i >= 0; i--) {
2815 if (bits_[i].wire != NULL && pattern.count(bits_[i])) {
2816 bits_.erase(bits_.begin() + i);
2817 width_--;
2818 if (other != NULL) {
2819 other->bits_.erase(other->bits_.begin() + i);
2820 other->width_--;
2821 }
2822 }
2823 }
2824
2825 check();
2826 }
2827
2828 void RTLIL::SigSpec::remove2(const std::set<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other)
2829 {
2830 if (other)
2831 cover("kernel.rtlil.sigspec.remove_other");
2832 else
2833 cover("kernel.rtlil.sigspec.remove");
2834
2835 unpack();
2836
2837 if (other != NULL) {
2838 log_assert(width_ == other->width_);
2839 other->unpack();
2840 }
2841
2842 for (int i = GetSize(bits_) - 1; i >= 0; i--) {
2843 if (bits_[i].wire != NULL && pattern.count(bits_[i])) {
2844 bits_.erase(bits_.begin() + i);
2845 width_--;
2846 if (other != NULL) {
2847 other->bits_.erase(other->bits_.begin() + i);
2848 other->width_--;
2849 }
2850 }
2851 }
2852
2853 check();
2854 }
2855
2856 RTLIL::SigSpec RTLIL::SigSpec::extract(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec *other) const
2857 {
2858 if (other)
2859 cover("kernel.rtlil.sigspec.extract_other");
2860 else
2861 cover("kernel.rtlil.sigspec.extract");
2862
2863 log_assert(other == NULL || width_ == other->width_);
2864
2865 RTLIL::SigSpec ret;
2866 std::vector<RTLIL::SigBit> bits_match = to_sigbit_vector();
2867
2868 for (auto& pattern_chunk : pattern.chunks()) {
2869 if (other) {
2870 std::vector<RTLIL::SigBit> bits_other = other->to_sigbit_vector();
2871 for (int i = 0; i < width_; i++)
2872 if (bits_match[i].wire &&
2873 bits_match[i].wire == pattern_chunk.wire &&
2874 bits_match[i].offset >= pattern_chunk.offset &&
2875 bits_match[i].offset < pattern_chunk.offset + pattern_chunk.width)
2876 ret.append_bit(bits_other[i]);
2877 } else {
2878 for (int i = 0; i < width_; i++)
2879 if (bits_match[i].wire &&
2880 bits_match[i].wire == pattern_chunk.wire &&
2881 bits_match[i].offset >= pattern_chunk.offset &&
2882 bits_match[i].offset < pattern_chunk.offset + pattern_chunk.width)
2883 ret.append_bit(bits_match[i]);
2884 }
2885 }
2886
2887 ret.check();
2888 return ret;
2889 }
2890
2891 RTLIL::SigSpec RTLIL::SigSpec::extract(const pool<RTLIL::SigBit> &pattern, const RTLIL::SigSpec *other) const
2892 {
2893 if (other)
2894 cover("kernel.rtlil.sigspec.extract_other");
2895 else
2896 cover("kernel.rtlil.sigspec.extract");
2897
2898 log_assert(other == NULL || width_ == other->width_);
2899
2900 std::vector<RTLIL::SigBit> bits_match = to_sigbit_vector();
2901 RTLIL::SigSpec ret;
2902
2903 if (other) {
2904 std::vector<RTLIL::SigBit> bits_other = other->to_sigbit_vector();
2905 for (int i = 0; i < width_; i++)
2906 if (bits_match[i].wire && pattern.count(bits_match[i]))
2907 ret.append_bit(bits_other[i]);
2908 } else {
2909 for (int i = 0; i < width_; i++)
2910 if (bits_match[i].wire && pattern.count(bits_match[i]))
2911 ret.append_bit(bits_match[i]);
2912 }
2913
2914 ret.check();
2915 return ret;
2916 }
2917
2918 void RTLIL::SigSpec::replace(int offset, const RTLIL::SigSpec &with)
2919 {
2920 cover("kernel.rtlil.sigspec.replace_pos");
2921
2922 unpack();
2923 with.unpack();
2924
2925 log_assert(offset >= 0);
2926 log_assert(with.width_ >= 0);
2927 log_assert(offset+with.width_ <= width_);
2928
2929 for (int i = 0; i < with.width_; i++)
2930 bits_.at(offset + i) = with.bits_.at(i);
2931
2932 check();
2933 }
2934
2935 void RTLIL::SigSpec::remove_const()
2936 {
2937 if (packed())
2938 {
2939 cover("kernel.rtlil.sigspec.remove_const.packed");
2940
2941 std::vector<RTLIL::SigChunk> new_chunks;
2942 new_chunks.reserve(GetSize(chunks_));
2943
2944 width_ = 0;
2945 for (auto &chunk : chunks_)
2946 if (chunk.wire != NULL) {
2947 new_chunks.push_back(chunk);
2948 width_ += chunk.width;
2949 }
2950
2951 chunks_.swap(new_chunks);
2952 }
2953 else
2954 {
2955 cover("kernel.rtlil.sigspec.remove_const.unpacked");
2956
2957 std::vector<RTLIL::SigBit> new_bits;
2958 new_bits.reserve(width_);
2959
2960 for (auto &bit : bits_)
2961 if (bit.wire != NULL)
2962 new_bits.push_back(bit);
2963
2964 bits_.swap(new_bits);
2965 width_ = bits_.size();
2966 }
2967
2968 check();
2969 }
2970
2971 void RTLIL::SigSpec::remove(int offset, int length)
2972 {
2973 cover("kernel.rtlil.sigspec.remove_pos");
2974
2975 unpack();
2976
2977 log_assert(offset >= 0);
2978 log_assert(length >= 0);
2979 log_assert(offset + length <= width_);
2980
2981 bits_.erase(bits_.begin() + offset, bits_.begin() + offset + length);
2982 width_ = bits_.size();
2983
2984 check();
2985 }
2986
2987 RTLIL::SigSpec RTLIL::SigSpec::extract(int offset, int length) const
2988 {
2989 unpack();
2990 cover("kernel.rtlil.sigspec.extract_pos");
2991 return std::vector<RTLIL::SigBit>(bits_.begin() + offset, bits_.begin() + offset + length);
2992 }
2993
2994 void RTLIL::SigSpec::append(const RTLIL::SigSpec &signal)
2995 {
2996 if (signal.width_ == 0)
2997 return;
2998
2999 if (width_ == 0) {
3000 *this = signal;
3001 return;
3002 }
3003
3004 cover("kernel.rtlil.sigspec.append");
3005
3006 if (packed() != signal.packed()) {
3007 pack();
3008 signal.pack();
3009 }
3010
3011 if (packed())
3012 for (auto &other_c : signal.chunks_)
3013 {
3014 auto &my_last_c = chunks_.back();
3015 if (my_last_c.wire == NULL && other_c.wire == NULL) {
3016 auto &this_data = my_last_c.data;
3017 auto &other_data = other_c.data;
3018 this_data.insert(this_data.end(), other_data.begin(), other_data.end());
3019 my_last_c.width += other_c.width;
3020 } else
3021 if (my_last_c.wire == other_c.wire && my_last_c.offset + my_last_c.width == other_c.offset) {
3022 my_last_c.width += other_c.width;
3023 } else
3024 chunks_.push_back(other_c);
3025 }
3026 else
3027 bits_.insert(bits_.end(), signal.bits_.begin(), signal.bits_.end());
3028
3029 width_ += signal.width_;
3030 check();
3031 }
3032
3033 void RTLIL::SigSpec::append_bit(const RTLIL::SigBit &bit)
3034 {
3035 if (packed())
3036 {
3037 cover("kernel.rtlil.sigspec.append_bit.packed");
3038
3039 if (chunks_.size() == 0)
3040 chunks_.push_back(bit);
3041 else
3042 if (bit.wire == NULL)
3043 if (chunks_.back().wire == NULL) {
3044 chunks_.back().data.push_back(bit.data);
3045 chunks_.back().width++;
3046 } else
3047 chunks_.push_back(bit);
3048 else
3049 if (chunks_.back().wire == bit.wire && chunks_.back().offset + chunks_.back().width == bit.offset)
3050 chunks_.back().width++;
3051 else
3052 chunks_.push_back(bit);
3053 }
3054 else
3055 {
3056 cover("kernel.rtlil.sigspec.append_bit.unpacked");
3057 bits_.push_back(bit);
3058 }
3059
3060 width_++;
3061 check();
3062 }
3063
3064 void RTLIL::SigSpec::extend_u0(int width, bool is_signed)
3065 {
3066 cover("kernel.rtlil.sigspec.extend_u0");
3067
3068 pack();
3069
3070 if (width_ > width)
3071 remove(width, width_ - width);
3072
3073 if (width_ < width) {
3074 RTLIL::SigBit padding = width_ > 0 ? (*this)[width_ - 1] : RTLIL::State::S0;
3075 if (!is_signed)
3076 padding = RTLIL::State::S0;
3077 while (width_ < width)
3078 append(padding);
3079 }
3080
3081 }
3082
3083 RTLIL::SigSpec RTLIL::SigSpec::repeat(int num) const
3084 {
3085 cover("kernel.rtlil.sigspec.repeat");
3086
3087 RTLIL::SigSpec sig;
3088 for (int i = 0; i < num; i++)
3089 sig.append(*this);
3090 return sig;
3091 }
3092
3093 #ifndef NDEBUG
3094 void RTLIL::SigSpec::check() const
3095 {
3096 if (width_ > 64)
3097 {
3098 cover("kernel.rtlil.sigspec.check.skip");
3099 }
3100 else if (packed())
3101 {
3102 cover("kernel.rtlil.sigspec.check.packed");
3103
3104 int w = 0;
3105 for (size_t i = 0; i < chunks_.size(); i++) {
3106 const RTLIL::SigChunk chunk = chunks_[i];
3107 if (chunk.wire == NULL) {
3108 if (i > 0)
3109 log_assert(chunks_[i-1].wire != NULL);
3110 log_assert(chunk.offset == 0);
3111 log_assert(chunk.data.size() == (size_t)chunk.width);
3112 } else {
3113 if (i > 0 && chunks_[i-1].wire == chunk.wire)
3114 log_assert(chunk.offset != chunks_[i-1].offset + chunks_[i-1].width);
3115 log_assert(chunk.offset >= 0);
3116 log_assert(chunk.width >= 0);
3117 log_assert(chunk.offset + chunk.width <= chunk.wire->width);
3118 log_assert(chunk.data.size() == 0);
3119 }
3120 w += chunk.width;
3121 }
3122 log_assert(w == width_);
3123 log_assert(bits_.empty());
3124 }
3125 else
3126 {
3127 cover("kernel.rtlil.sigspec.check.unpacked");
3128
3129 log_assert(width_ == GetSize(bits_));
3130 log_assert(chunks_.empty());
3131 }
3132 }
3133 #endif
3134
3135 bool RTLIL::SigSpec::operator <(const RTLIL::SigSpec &other) const
3136 {
3137 cover("kernel.rtlil.sigspec.comp_lt");
3138
3139 if (this == &other)
3140 return false;
3141
3142 if (width_ != other.width_)
3143 return width_ < other.width_;
3144
3145 pack();
3146 other.pack();
3147
3148 if (chunks_.size() != other.chunks_.size())
3149 return chunks_.size() < other.chunks_.size();
3150
3151 updhash();
3152 other.updhash();
3153
3154 if (hash_ != other.hash_)
3155 return hash_ < other.hash_;
3156
3157 for (size_t i = 0; i < chunks_.size(); i++)
3158 if (chunks_[i] != other.chunks_[i]) {
3159 cover("kernel.rtlil.sigspec.comp_lt.hash_collision");
3160 return chunks_[i] < other.chunks_[i];
3161 }
3162
3163 cover("kernel.rtlil.sigspec.comp_lt.equal");
3164 return false;
3165 }
3166
3167 bool RTLIL::SigSpec::operator ==(const RTLIL::SigSpec &other) const
3168 {
3169 cover("kernel.rtlil.sigspec.comp_eq");
3170
3171 if (this == &other)
3172 return true;
3173
3174 if (width_ != other.width_)
3175 return false;
3176
3177 pack();
3178 other.pack();
3179
3180 if (chunks_.size() != chunks_.size())
3181 return false;
3182
3183 updhash();
3184 other.updhash();
3185
3186 if (hash_ != other.hash_)
3187 return false;
3188
3189 for (size_t i = 0; i < chunks_.size(); i++)
3190 if (chunks_[i] != other.chunks_[i]) {
3191 cover("kernel.rtlil.sigspec.comp_eq.hash_collision");
3192 return false;
3193 }
3194
3195 cover("kernel.rtlil.sigspec.comp_eq.equal");
3196 return true;
3197 }
3198
3199 bool RTLIL::SigSpec::is_wire() const
3200 {
3201 cover("kernel.rtlil.sigspec.is_wire");
3202
3203 pack();
3204 return GetSize(chunks_) == 1 && chunks_[0].wire && chunks_[0].wire->width == width_;
3205 }
3206
3207 bool RTLIL::SigSpec::is_chunk() const
3208 {
3209 cover("kernel.rtlil.sigspec.is_chunk");
3210
3211 pack();
3212 return GetSize(chunks_) == 1;
3213 }
3214
3215 bool RTLIL::SigSpec::is_fully_const() const
3216 {
3217 cover("kernel.rtlil.sigspec.is_fully_const");
3218
3219 pack();
3220 for (auto it = chunks_.begin(); it != chunks_.end(); it++)
3221 if (it->width > 0 && it->wire != NULL)
3222 return false;
3223 return true;
3224 }
3225
3226 bool RTLIL::SigSpec::is_fully_zero() const
3227 {
3228 cover("kernel.rtlil.sigspec.is_fully_zero");
3229
3230 pack();
3231 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
3232 if (it->width > 0 && it->wire != NULL)
3233 return false;
3234 for (size_t i = 0; i < it->data.size(); i++)
3235 if (it->data[i] != RTLIL::State::S0)
3236 return false;
3237 }
3238 return true;
3239 }
3240
3241 bool RTLIL::SigSpec::is_fully_def() const
3242 {
3243 cover("kernel.rtlil.sigspec.is_fully_def");
3244
3245 pack();
3246 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
3247 if (it->width > 0 && it->wire != NULL)
3248 return false;
3249 for (size_t i = 0; i < it->data.size(); i++)
3250 if (it->data[i] != RTLIL::State::S0 && it->data[i] != RTLIL::State::S1)
3251 return false;
3252 }
3253 return true;
3254 }
3255
3256 bool RTLIL::SigSpec::is_fully_undef() const
3257 {
3258 cover("kernel.rtlil.sigspec.is_fully_undef");
3259
3260 pack();
3261 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
3262 if (it->width > 0 && it->wire != NULL)
3263 return false;
3264 for (size_t i = 0; i < it->data.size(); i++)
3265 if (it->data[i] != RTLIL::State::Sx && it->data[i] != RTLIL::State::Sz)
3266 return false;
3267 }
3268 return true;
3269 }
3270
3271 bool RTLIL::SigSpec::has_const() const
3272 {
3273 cover("kernel.rtlil.sigspec.has_const");
3274
3275 pack();
3276 for (auto it = chunks_.begin(); it != chunks_.end(); it++)
3277 if (it->width > 0 && it->wire == NULL)
3278 return true;
3279 return false;
3280 }
3281
3282 bool RTLIL::SigSpec::has_marked_bits() const
3283 {
3284 cover("kernel.rtlil.sigspec.has_marked_bits");
3285
3286 pack();
3287 for (auto it = chunks_.begin(); it != chunks_.end(); it++)
3288 if (it->width > 0 && it->wire == NULL) {
3289 for (size_t i = 0; i < it->data.size(); i++)
3290 if (it->data[i] == RTLIL::State::Sm)
3291 return true;
3292 }
3293 return false;
3294 }
3295
3296 bool RTLIL::SigSpec::as_bool() const
3297 {
3298 cover("kernel.rtlil.sigspec.as_bool");
3299
3300 pack();
3301 log_assert(is_fully_const() && GetSize(chunks_) <= 1);
3302 if (width_)
3303 return RTLIL::Const(chunks_[0].data).as_bool();
3304 return false;
3305 }
3306
3307 int RTLIL::SigSpec::as_int(bool is_signed) const
3308 {
3309 cover("kernel.rtlil.sigspec.as_int");
3310
3311 pack();
3312 log_assert(is_fully_const() && GetSize(chunks_) <= 1);
3313 if (width_)
3314 return RTLIL::Const(chunks_[0].data).as_int(is_signed);
3315 return 0;
3316 }
3317
3318 std::string RTLIL::SigSpec::as_string() const
3319 {
3320 cover("kernel.rtlil.sigspec.as_string");
3321
3322 pack();
3323 std::string str;
3324 for (size_t i = chunks_.size(); i > 0; i--) {
3325 const RTLIL::SigChunk &chunk = chunks_[i-1];
3326 if (chunk.wire != NULL)
3327 for (int j = 0; j < chunk.width; j++)
3328 str += "?";
3329 else
3330 str += RTLIL::Const(chunk.data).as_string();
3331 }
3332 return str;
3333 }
3334
3335 RTLIL::Const RTLIL::SigSpec::as_const() const
3336 {
3337 cover("kernel.rtlil.sigspec.as_const");
3338
3339 pack();
3340 log_assert(is_fully_const() && GetSize(chunks_) <= 1);
3341 if (width_)
3342 return chunks_[0].data;
3343 return RTLIL::Const();
3344 }
3345
3346 RTLIL::Wire *RTLIL::SigSpec::as_wire() const
3347 {
3348 cover("kernel.rtlil.sigspec.as_wire");
3349
3350 pack();
3351 log_assert(is_wire());
3352 return chunks_[0].wire;
3353 }
3354
3355 RTLIL::SigChunk RTLIL::SigSpec::as_chunk() const
3356 {
3357 cover("kernel.rtlil.sigspec.as_chunk");
3358
3359 pack();
3360 log_assert(is_chunk());
3361 return chunks_[0];
3362 }
3363
3364 RTLIL::SigBit RTLIL::SigSpec::as_bit() const
3365 {
3366 cover("kernel.rtlil.sigspec.as_bit");
3367
3368 log_assert(width_ == 1);
3369 if (packed())
3370 return RTLIL::SigBit(*chunks_.begin());
3371 else
3372 return bits_[0];
3373 }
3374
3375 bool RTLIL::SigSpec::match(std::string pattern) const
3376 {
3377 cover("kernel.rtlil.sigspec.match");
3378
3379 pack();
3380 std::string str = as_string();
3381 log_assert(pattern.size() == str.size());
3382
3383 for (size_t i = 0; i < pattern.size(); i++) {
3384 if (pattern[i] == ' ')
3385 continue;
3386 if (pattern[i] == '*') {
3387 if (str[i] != 'z' && str[i] != 'x')
3388 return false;
3389 continue;
3390 }
3391 if (pattern[i] != str[i])
3392 return false;
3393 }
3394
3395 return true;
3396 }
3397
3398 std::set<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_set() const
3399 {
3400 cover("kernel.rtlil.sigspec.to_sigbit_set");
3401
3402 pack();
3403 std::set<RTLIL::SigBit> sigbits;
3404 for (auto &c : chunks_)
3405 for (int i = 0; i < c.width; i++)
3406 sigbits.insert(RTLIL::SigBit(c, i));
3407 return sigbits;
3408 }
3409
3410 pool<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_pool() const
3411 {
3412 cover("kernel.rtlil.sigspec.to_sigbit_pool");
3413
3414 pack();
3415 pool<RTLIL::SigBit> sigbits;
3416 for (auto &c : chunks_)
3417 for (int i = 0; i < c.width; i++)
3418 sigbits.insert(RTLIL::SigBit(c, i));
3419 return sigbits;
3420 }
3421
3422 std::vector<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_vector() const
3423 {
3424 cover("kernel.rtlil.sigspec.to_sigbit_vector");
3425
3426 unpack();
3427 return bits_;
3428 }
3429
3430 std::map<RTLIL::SigBit, RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_map(const RTLIL::SigSpec &other) const
3431 {
3432 cover("kernel.rtlil.sigspec.to_sigbit_map");
3433
3434 unpack();
3435 other.unpack();
3436
3437 log_assert(width_ == other.width_);
3438
3439 std::map<RTLIL::SigBit, RTLIL::SigBit> new_map;
3440 for (int i = 0; i < width_; i++)
3441 new_map[bits_[i]] = other.bits_[i];
3442
3443 return new_map;
3444 }
3445
3446 dict<RTLIL::SigBit, RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_dict(const RTLIL::SigSpec &other) const
3447 {
3448 cover("kernel.rtlil.sigspec.to_sigbit_dict");
3449
3450 unpack();
3451 other.unpack();
3452
3453 log_assert(width_ == other.width_);
3454
3455 dict<RTLIL::SigBit, RTLIL::SigBit> new_map;
3456 for (int i = 0; i < width_; i++)
3457 new_map[bits_[i]] = other.bits_[i];
3458
3459 return new_map;
3460 }
3461
3462 static void sigspec_parse_split(std::vector<std::string> &tokens, const std::string &text, char sep)
3463 {
3464 size_t start = 0, end = 0;
3465 while ((end = text.find(sep, start)) != std::string::npos) {
3466 tokens.push_back(text.substr(start, end - start));
3467 start = end + 1;
3468 }
3469 tokens.push_back(text.substr(start));
3470 }
3471
3472 static int sigspec_parse_get_dummy_line_num()
3473 {
3474 return 0;
3475 }
3476
3477 bool RTLIL::SigSpec::parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str)
3478 {
3479 cover("kernel.rtlil.sigspec.parse");
3480
3481 AST::current_filename = "input";
3482 AST::use_internal_line_num();
3483 AST::set_line_num(0);
3484
3485 std::vector<std::string> tokens;
3486 sigspec_parse_split(tokens, str, ',');
3487
3488 sig = RTLIL::SigSpec();
3489 for (int tokidx = int(tokens.size())-1; tokidx >= 0; tokidx--)
3490 {
3491 std::string netname = tokens[tokidx];
3492 std::string indices;
3493
3494 if (netname.size() == 0)
3495 continue;
3496
3497 if (('0' <= netname[0] && netname[0] <= '9') || netname[0] == '\'') {
3498 cover("kernel.rtlil.sigspec.parse.const");
3499 AST::get_line_num = sigspec_parse_get_dummy_line_num;
3500 AST::AstNode *ast = VERILOG_FRONTEND::const2ast(netname);
3501 if (ast == NULL)
3502 return false;
3503 sig.append(RTLIL::Const(ast->bits));
3504 delete ast;
3505 continue;
3506 }
3507
3508 if (module == NULL)
3509 return false;
3510
3511 cover("kernel.rtlil.sigspec.parse.net");
3512
3513 if (netname[0] != '$' && netname[0] != '\\')
3514 netname = "\\" + netname;
3515
3516 if (module->wires_.count(netname) == 0) {
3517 size_t indices_pos = netname.size()-1;
3518 if (indices_pos > 2 && netname[indices_pos] == ']')
3519 {
3520 indices_pos--;
3521 while (indices_pos > 0 && ('0' <= netname[indices_pos] && netname[indices_pos] <= '9')) indices_pos--;
3522 if (indices_pos > 0 && netname[indices_pos] == ':') {
3523 indices_pos--;
3524 while (indices_pos > 0 && ('0' <= netname[indices_pos] && netname[indices_pos] <= '9')) indices_pos--;
3525 }
3526 if (indices_pos > 0 && netname[indices_pos] == '[') {
3527 indices = netname.substr(indices_pos);
3528 netname = netname.substr(0, indices_pos);
3529 }
3530 }
3531 }
3532
3533 if (module->wires_.count(netname) == 0)
3534 return false;
3535
3536 RTLIL::Wire *wire = module->wires_.at(netname);
3537 if (!indices.empty()) {
3538 std::vector<std::string> index_tokens;
3539 sigspec_parse_split(index_tokens, indices.substr(1, indices.size()-2), ':');
3540 if (index_tokens.size() == 1) {
3541 cover("kernel.rtlil.sigspec.parse.bit_sel");
3542 int a = atoi(index_tokens.at(0).c_str());
3543 if (a < 0 || a >= wire->width)
3544 return false;
3545 sig.append(RTLIL::SigSpec(wire, a));
3546 } else {
3547 cover("kernel.rtlil.sigspec.parse.part_sel");
3548 int a = atoi(index_tokens.at(0).c_str());
3549 int b = atoi(index_tokens.at(1).c_str());
3550 if (a > b) {
3551 int tmp = a;
3552 a = b, b = tmp;
3553 }
3554 if (a < 0 || a >= wire->width)
3555 return false;
3556 if (b < 0 || b >= wire->width)
3557 return false;
3558 sig.append(RTLIL::SigSpec(wire, a, b-a+1));
3559 }
3560 } else
3561 sig.append(wire);
3562 }
3563
3564 return true;
3565 }
3566
3567 bool RTLIL::SigSpec::parse_sel(RTLIL::SigSpec &sig, RTLIL::Design *design, RTLIL::Module *module, std::string str)
3568 {
3569 if (str.empty() || str[0] != '@')
3570 return parse(sig, module, str);
3571
3572 cover("kernel.rtlil.sigspec.parse.sel");
3573
3574 str = RTLIL::escape_id(str.substr(1));
3575 if (design->selection_vars.count(str) == 0)
3576 return false;
3577
3578 sig = RTLIL::SigSpec();
3579 RTLIL::Selection &sel = design->selection_vars.at(str);
3580 for (auto &it : module->wires_)
3581 if (sel.selected_member(module->name, it.first))
3582 sig.append(it.second);
3583
3584 return true;
3585 }
3586
3587 bool RTLIL::SigSpec::parse_rhs(const RTLIL::SigSpec &lhs, RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str)
3588 {
3589 if (str == "0") {
3590 cover("kernel.rtlil.sigspec.parse.rhs_zeros");
3591 sig = RTLIL::SigSpec(RTLIL::State::S0, lhs.width_);
3592 return true;
3593 }
3594
3595 if (str == "~0") {
3596 cover("kernel.rtlil.sigspec.parse.rhs_ones");
3597 sig = RTLIL::SigSpec(RTLIL::State::S1, lhs.width_);
3598 return true;
3599 }
3600
3601 if (lhs.chunks_.size() == 1) {
3602 char *p = (char*)str.c_str(), *endptr;
3603 long int val = strtol(p, &endptr, 10);
3604 if (endptr && endptr != p && *endptr == 0) {
3605 sig = RTLIL::SigSpec(val, lhs.width_);
3606 cover("kernel.rtlil.sigspec.parse.rhs_dec");
3607 return true;
3608 }
3609 }
3610
3611 return parse(sig, module, str);
3612 }
3613
3614 RTLIL::CaseRule::~CaseRule()
3615 {
3616 for (auto it = switches.begin(); it != switches.end(); it++)
3617 delete *it;
3618 }
3619
3620 RTLIL::CaseRule *RTLIL::CaseRule::clone() const
3621 {
3622 RTLIL::CaseRule *new_caserule = new RTLIL::CaseRule;
3623 new_caserule->compare = compare;
3624 new_caserule->actions = actions;
3625 for (auto &it : switches)
3626 new_caserule->switches.push_back(it->clone());
3627 return new_caserule;
3628 }
3629
3630 RTLIL::SwitchRule::~SwitchRule()
3631 {
3632 for (auto it = cases.begin(); it != cases.end(); it++)
3633 delete *it;
3634 }
3635
3636 RTLIL::SwitchRule *RTLIL::SwitchRule::clone() const
3637 {
3638 RTLIL::SwitchRule *new_switchrule = new RTLIL::SwitchRule;
3639 new_switchrule->signal = signal;
3640 new_switchrule->attributes = attributes;
3641 for (auto &it : cases)
3642 new_switchrule->cases.push_back(it->clone());
3643 return new_switchrule;
3644
3645 }
3646
3647 RTLIL::SyncRule *RTLIL::SyncRule::clone() const
3648 {
3649 RTLIL::SyncRule *new_syncrule = new RTLIL::SyncRule;
3650 new_syncrule->type = type;
3651 new_syncrule->signal = signal;
3652 new_syncrule->actions = actions;
3653 return new_syncrule;
3654 }
3655
3656 RTLIL::Process::~Process()
3657 {
3658 for (auto it = syncs.begin(); it != syncs.end(); it++)
3659 delete *it;
3660 }
3661
3662 RTLIL::Process *RTLIL::Process::clone() const
3663 {
3664 RTLIL::Process *new_proc = new RTLIL::Process;
3665
3666 new_proc->name = name;
3667 new_proc->attributes = attributes;
3668
3669 RTLIL::CaseRule *rc_ptr = root_case.clone();
3670 new_proc->root_case = *rc_ptr;
3671 rc_ptr->switches.clear();
3672 delete rc_ptr;
3673
3674 for (auto &it : syncs)
3675 new_proc->syncs.push_back(it->clone());
3676
3677 return new_proc;
3678 }
3679
3680 YOSYS_NAMESPACE_END
3681