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Fix handling of warning and error messages within log_make_debug-blocks
[yosys.git] / kernel / rtlil.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 #include "kernel/yosys.h"
21 #include "kernel/macc.h"
22 #include "kernel/celltypes.h"
23 #include "frontends/verilog/verilog_frontend.h"
24 #include "backends/ilang/ilang_backend.h"
25
26 #include <string.h>
27 #include <algorithm>
28
29 YOSYS_NAMESPACE_BEGIN
30
31 RTLIL::IdString::destruct_guard_t RTLIL::IdString::destruct_guard;
32 std::vector<int> RTLIL::IdString::global_refcount_storage_;
33 std::vector<char*> RTLIL::IdString::global_id_storage_;
34 dict<char*, int, hash_cstr_ops> RTLIL::IdString::global_id_index_;
35 std::vector<int> RTLIL::IdString::global_free_idx_list_;
36 int RTLIL::IdString::last_created_idx_[8];
37 int RTLIL::IdString::last_created_idx_ptr_;
38
39 RTLIL::Const::Const()
40 {
41 flags = RTLIL::CONST_FLAG_NONE;
42 }
43
44 RTLIL::Const::Const(std::string str)
45 {
46 flags = RTLIL::CONST_FLAG_STRING;
47 for (int i = str.size()-1; i >= 0; i--) {
48 unsigned char ch = str[i];
49 for (int j = 0; j < 8; j++) {
50 bits.push_back((ch & 1) != 0 ? RTLIL::S1 : RTLIL::S0);
51 ch = ch >> 1;
52 }
53 }
54 }
55
56 RTLIL::Const::Const(int val, int width)
57 {
58 flags = RTLIL::CONST_FLAG_NONE;
59 for (int i = 0; i < width; i++) {
60 bits.push_back((val & 1) != 0 ? RTLIL::S1 : RTLIL::S0);
61 val = val >> 1;
62 }
63 }
64
65 RTLIL::Const::Const(RTLIL::State bit, int width)
66 {
67 flags = RTLIL::CONST_FLAG_NONE;
68 for (int i = 0; i < width; i++)
69 bits.push_back(bit);
70 }
71
72 RTLIL::Const::Const(const std::vector<bool> &bits)
73 {
74 flags = RTLIL::CONST_FLAG_NONE;
75 for (auto b : bits)
76 this->bits.push_back(b ? RTLIL::S1 : RTLIL::S0);
77 }
78
79 RTLIL::Const::Const(const RTLIL::Const &c)
80 {
81 flags = c.flags;
82 for (auto b : c.bits)
83 this->bits.push_back(b);
84 }
85
86 bool RTLIL::Const::operator <(const RTLIL::Const &other) const
87 {
88 if (bits.size() != other.bits.size())
89 return bits.size() < other.bits.size();
90 for (size_t i = 0; i < bits.size(); i++)
91 if (bits[i] != other.bits[i])
92 return bits[i] < other.bits[i];
93 return false;
94 }
95
96 bool RTLIL::Const::operator ==(const RTLIL::Const &other) const
97 {
98 return bits == other.bits;
99 }
100
101 bool RTLIL::Const::operator !=(const RTLIL::Const &other) const
102 {
103 return bits != other.bits;
104 }
105
106 bool RTLIL::Const::as_bool() const
107 {
108 for (size_t i = 0; i < bits.size(); i++)
109 if (bits[i] == RTLIL::S1)
110 return true;
111 return false;
112 }
113
114 int RTLIL::Const::as_int(bool is_signed) const
115 {
116 int32_t ret = 0;
117 for (size_t i = 0; i < bits.size() && i < 32; i++)
118 if (bits[i] == RTLIL::S1)
119 ret |= 1 << i;
120 if (is_signed && bits.back() == RTLIL::S1)
121 for (size_t i = bits.size(); i < 32; i++)
122 ret |= 1 << i;
123 return ret;
124 }
125
126 std::string RTLIL::Const::as_string() const
127 {
128 std::string ret;
129 for (size_t i = bits.size(); i > 0; i--)
130 switch (bits[i-1]) {
131 case S0: ret += "0"; break;
132 case S1: ret += "1"; break;
133 case Sx: ret += "x"; break;
134 case Sz: ret += "z"; break;
135 case Sa: ret += "-"; break;
136 case Sm: ret += "m"; break;
137 }
138 return ret;
139 }
140
141 RTLIL::Const RTLIL::Const::from_string(std::string str)
142 {
143 Const c;
144 for (auto it = str.rbegin(); it != str.rend(); it++)
145 switch (*it) {
146 case '0': c.bits.push_back(State::S0); break;
147 case '1': c.bits.push_back(State::S1); break;
148 case 'x': c.bits.push_back(State::Sx); break;
149 case 'z': c.bits.push_back(State::Sz); break;
150 case 'm': c.bits.push_back(State::Sm); break;
151 default: c.bits.push_back(State::Sa);
152 }
153 return c;
154 }
155
156 std::string RTLIL::Const::decode_string() const
157 {
158 std::string string;
159 std::vector<char> string_chars;
160 for (int i = 0; i < int (bits.size()); i += 8) {
161 char ch = 0;
162 for (int j = 0; j < 8 && i + j < int (bits.size()); j++)
163 if (bits[i + j] == RTLIL::State::S1)
164 ch |= 1 << j;
165 if (ch != 0)
166 string_chars.push_back(ch);
167 }
168 for (int i = int (string_chars.size()) - 1; i >= 0; i--)
169 string += string_chars[i];
170 return string;
171 }
172
173 bool RTLIL::Const::is_fully_zero() const
174 {
175 cover("kernel.rtlil.const.is_fully_zero");
176
177 for (auto bit : bits)
178 if (bit != RTLIL::State::S0)
179 return false;
180
181 return true;
182 }
183
184 bool RTLIL::Const::is_fully_ones() const
185 {
186 cover("kernel.rtlil.const.is_fully_ones");
187
188 for (auto bit : bits)
189 if (bit != RTLIL::State::S1)
190 return false;
191
192 return true;
193 }
194
195 bool RTLIL::Const::is_fully_def() const
196 {
197 cover("kernel.rtlil.const.is_fully_def");
198
199 for (auto bit : bits)
200 if (bit != RTLIL::State::S0 && bit != RTLIL::State::S1)
201 return false;
202
203 return true;
204 }
205
206 bool RTLIL::Const::is_fully_undef() const
207 {
208 cover("kernel.rtlil.const.is_fully_undef");
209
210 for (auto bit : bits)
211 if (bit != RTLIL::State::Sx && bit != RTLIL::State::Sz)
212 return false;
213
214 return true;
215 }
216
217 void RTLIL::AttrObject::set_bool_attribute(RTLIL::IdString id, bool value)
218 {
219 if (value)
220 attributes[id] = RTLIL::Const(1);
221 else {
222 const auto it = attributes.find(id);
223 if (it != attributes.end())
224 attributes.erase(it);
225 }
226 }
227
228 bool RTLIL::AttrObject::get_bool_attribute(RTLIL::IdString id) const
229 {
230 const auto it = attributes.find(id);
231 if (it == attributes.end())
232 return false;
233 return it->second.as_bool();
234 }
235
236 void RTLIL::AttrObject::set_strpool_attribute(RTLIL::IdString id, const pool<string> &data)
237 {
238 string attrval;
239 for (auto &s : data) {
240 if (!attrval.empty())
241 attrval += "|";
242 attrval += s;
243 }
244 attributes[id] = RTLIL::Const(attrval);
245 }
246
247 void RTLIL::AttrObject::add_strpool_attribute(RTLIL::IdString id, const pool<string> &data)
248 {
249 pool<string> union_data = get_strpool_attribute(id);
250 union_data.insert(data.begin(), data.end());
251 if (!union_data.empty())
252 set_strpool_attribute(id, union_data);
253 }
254
255 pool<string> RTLIL::AttrObject::get_strpool_attribute(RTLIL::IdString id) const
256 {
257 pool<string> data;
258 if (attributes.count(id) != 0)
259 for (auto s : split_tokens(attributes.at(id).decode_string(), "|"))
260 data.insert(s);
261 return data;
262 }
263
264 void RTLIL::AttrObject::set_src_attribute(const std::string &src)
265 {
266 if (src.empty())
267 attributes.erase("\\src");
268 else
269 attributes["\\src"] = src;
270 }
271
272 std::string RTLIL::AttrObject::get_src_attribute() const
273 {
274 std::string src;
275 if (attributes.count("\\src"))
276 src = attributes.at("\\src").decode_string();
277 return src;
278 }
279
280 bool RTLIL::Selection::selected_module(RTLIL::IdString mod_name) const
281 {
282 if (full_selection)
283 return true;
284 if (selected_modules.count(mod_name) > 0)
285 return true;
286 if (selected_members.count(mod_name) > 0)
287 return true;
288 return false;
289 }
290
291 bool RTLIL::Selection::selected_whole_module(RTLIL::IdString mod_name) const
292 {
293 if (full_selection)
294 return true;
295 if (selected_modules.count(mod_name) > 0)
296 return true;
297 return false;
298 }
299
300 bool RTLIL::Selection::selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const
301 {
302 if (full_selection)
303 return true;
304 if (selected_modules.count(mod_name) > 0)
305 return true;
306 if (selected_members.count(mod_name) > 0)
307 if (selected_members.at(mod_name).count(memb_name) > 0)
308 return true;
309 return false;
310 }
311
312 void RTLIL::Selection::optimize(RTLIL::Design *design)
313 {
314 if (full_selection) {
315 selected_modules.clear();
316 selected_members.clear();
317 return;
318 }
319
320 std::vector<RTLIL::IdString> del_list, add_list;
321
322 del_list.clear();
323 for (auto mod_name : selected_modules) {
324 if (design->modules_.count(mod_name) == 0)
325 del_list.push_back(mod_name);
326 selected_members.erase(mod_name);
327 }
328 for (auto mod_name : del_list)
329 selected_modules.erase(mod_name);
330
331 del_list.clear();
332 for (auto &it : selected_members)
333 if (design->modules_.count(it.first) == 0)
334 del_list.push_back(it.first);
335 for (auto mod_name : del_list)
336 selected_members.erase(mod_name);
337
338 for (auto &it : selected_members) {
339 del_list.clear();
340 for (auto memb_name : it.second)
341 if (design->modules_[it.first]->count_id(memb_name) == 0)
342 del_list.push_back(memb_name);
343 for (auto memb_name : del_list)
344 it.second.erase(memb_name);
345 }
346
347 del_list.clear();
348 add_list.clear();
349 for (auto &it : selected_members)
350 if (it.second.size() == 0)
351 del_list.push_back(it.first);
352 else if (it.second.size() == design->modules_[it.first]->wires_.size() + design->modules_[it.first]->memories.size() +
353 design->modules_[it.first]->cells_.size() + design->modules_[it.first]->processes.size())
354 add_list.push_back(it.first);
355 for (auto mod_name : del_list)
356 selected_members.erase(mod_name);
357 for (auto mod_name : add_list) {
358 selected_members.erase(mod_name);
359 selected_modules.insert(mod_name);
360 }
361
362 if (selected_modules.size() == design->modules_.size()) {
363 full_selection = true;
364 selected_modules.clear();
365 selected_members.clear();
366 }
367 }
368
369 RTLIL::Design::Design()
370 {
371 static unsigned int hashidx_count = 123456789;
372 hashidx_count = mkhash_xorshift(hashidx_count);
373 hashidx_ = hashidx_count;
374
375 refcount_modules_ = 0;
376 selection_stack.push_back(RTLIL::Selection());
377
378 #ifdef WITH_PYTHON
379 RTLIL::Design::get_all_designs()->insert(std::pair<unsigned int, RTLIL::Design*>(hashidx_, this));
380 #endif
381 }
382
383 RTLIL::Design::~Design()
384 {
385 for (auto it = modules_.begin(); it != modules_.end(); ++it)
386 delete it->second;
387 for (auto n : verilog_packages)
388 delete n;
389 for (auto n : verilog_globals)
390 delete n;
391 #ifdef WITH_PYTHON
392 RTLIL::Design::get_all_designs()->erase(hashidx_);
393 #endif
394 }
395
396 #ifdef WITH_PYTHON
397 static std::map<unsigned int, RTLIL::Design*> all_designs;
398 std::map<unsigned int, RTLIL::Design*> *RTLIL::Design::get_all_designs(void)
399 {
400 return &all_designs;
401 }
402 #endif
403
404 RTLIL::ObjRange<RTLIL::Module*> RTLIL::Design::modules()
405 {
406 return RTLIL::ObjRange<RTLIL::Module*>(&modules_, &refcount_modules_);
407 }
408
409 RTLIL::Module *RTLIL::Design::module(RTLIL::IdString name)
410 {
411 return modules_.count(name) ? modules_.at(name) : NULL;
412 }
413
414 RTLIL::Module *RTLIL::Design::top_module()
415 {
416 RTLIL::Module *module = nullptr;
417 int module_count = 0;
418
419 for (auto mod : selected_modules()) {
420 if (mod->get_bool_attribute("\\top"))
421 return mod;
422 module_count++;
423 module = mod;
424 }
425
426 return module_count == 1 ? module : nullptr;
427 }
428
429 void RTLIL::Design::add(RTLIL::Module *module)
430 {
431 log_assert(modules_.count(module->name) == 0);
432 log_assert(refcount_modules_ == 0);
433 modules_[module->name] = module;
434 module->design = this;
435
436 for (auto mon : monitors)
437 mon->notify_module_add(module);
438
439 if (yosys_xtrace) {
440 log("#X# New Module: %s\n", log_id(module));
441 log_backtrace("-X- ", yosys_xtrace-1);
442 }
443 }
444
445 RTLIL::Module *RTLIL::Design::addModule(RTLIL::IdString name)
446 {
447 log_assert(modules_.count(name) == 0);
448 log_assert(refcount_modules_ == 0);
449
450 RTLIL::Module *module = new RTLIL::Module;
451 modules_[name] = module;
452 module->design = this;
453 module->name = name;
454
455 for (auto mon : monitors)
456 mon->notify_module_add(module);
457
458 if (yosys_xtrace) {
459 log("#X# New Module: %s\n", log_id(module));
460 log_backtrace("-X- ", yosys_xtrace-1);
461 }
462
463 return module;
464 }
465
466 void RTLIL::Design::scratchpad_unset(std::string varname)
467 {
468 scratchpad.erase(varname);
469 }
470
471 void RTLIL::Design::scratchpad_set_int(std::string varname, int value)
472 {
473 scratchpad[varname] = stringf("%d", value);
474 }
475
476 void RTLIL::Design::scratchpad_set_bool(std::string varname, bool value)
477 {
478 scratchpad[varname] = value ? "true" : "false";
479 }
480
481 void RTLIL::Design::scratchpad_set_string(std::string varname, std::string value)
482 {
483 scratchpad[varname] = value;
484 }
485
486 int RTLIL::Design::scratchpad_get_int(std::string varname, int default_value) const
487 {
488 if (scratchpad.count(varname) == 0)
489 return default_value;
490
491 std::string str = scratchpad.at(varname);
492
493 if (str == "0" || str == "false")
494 return 0;
495
496 if (str == "1" || str == "true")
497 return 1;
498
499 char *endptr = nullptr;
500 long int parsed_value = strtol(str.c_str(), &endptr, 10);
501 return *endptr ? default_value : parsed_value;
502 }
503
504 bool RTLIL::Design::scratchpad_get_bool(std::string varname, bool default_value) const
505 {
506 if (scratchpad.count(varname) == 0)
507 return default_value;
508
509 std::string str = scratchpad.at(varname);
510
511 if (str == "0" || str == "false")
512 return false;
513
514 if (str == "1" || str == "true")
515 return true;
516
517 return default_value;
518 }
519
520 std::string RTLIL::Design::scratchpad_get_string(std::string varname, std::string default_value) const
521 {
522 if (scratchpad.count(varname) == 0)
523 return default_value;
524 return scratchpad.at(varname);
525 }
526
527 void RTLIL::Design::remove(RTLIL::Module *module)
528 {
529 for (auto mon : monitors)
530 mon->notify_module_del(module);
531
532 if (yosys_xtrace) {
533 log("#X# Remove Module: %s\n", log_id(module));
534 log_backtrace("-X- ", yosys_xtrace-1);
535 }
536
537 log_assert(modules_.at(module->name) == module);
538 modules_.erase(module->name);
539 delete module;
540 }
541
542 void RTLIL::Design::rename(RTLIL::Module *module, RTLIL::IdString new_name)
543 {
544 modules_.erase(module->name);
545 module->name = new_name;
546 add(module);
547 }
548
549 void RTLIL::Design::sort()
550 {
551 scratchpad.sort();
552 modules_.sort(sort_by_id_str());
553 for (auto &it : modules_)
554 it.second->sort();
555 }
556
557 void RTLIL::Design::check()
558 {
559 #ifndef NDEBUG
560 for (auto &it : modules_) {
561 log_assert(this == it.second->design);
562 log_assert(it.first == it.second->name);
563 log_assert(!it.first.empty());
564 it.second->check();
565 }
566 #endif
567 }
568
569 void RTLIL::Design::optimize()
570 {
571 for (auto &it : modules_)
572 it.second->optimize();
573 for (auto &it : selection_stack)
574 it.optimize(this);
575 for (auto &it : selection_vars)
576 it.second.optimize(this);
577 }
578
579 bool RTLIL::Design::selected_module(RTLIL::IdString mod_name) const
580 {
581 if (!selected_active_module.empty() && mod_name != selected_active_module)
582 return false;
583 if (selection_stack.size() == 0)
584 return true;
585 return selection_stack.back().selected_module(mod_name);
586 }
587
588 bool RTLIL::Design::selected_whole_module(RTLIL::IdString mod_name) const
589 {
590 if (!selected_active_module.empty() && mod_name != selected_active_module)
591 return false;
592 if (selection_stack.size() == 0)
593 return true;
594 return selection_stack.back().selected_whole_module(mod_name);
595 }
596
597 bool RTLIL::Design::selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const
598 {
599 if (!selected_active_module.empty() && mod_name != selected_active_module)
600 return false;
601 if (selection_stack.size() == 0)
602 return true;
603 return selection_stack.back().selected_member(mod_name, memb_name);
604 }
605
606 bool RTLIL::Design::selected_module(RTLIL::Module *mod) const
607 {
608 return selected_module(mod->name);
609 }
610
611 bool RTLIL::Design::selected_whole_module(RTLIL::Module *mod) const
612 {
613 return selected_whole_module(mod->name);
614 }
615
616 std::vector<RTLIL::Module*> RTLIL::Design::selected_modules() const
617 {
618 std::vector<RTLIL::Module*> result;
619 result.reserve(modules_.size());
620 for (auto &it : modules_)
621 if (selected_module(it.first) && !it.second->get_blackbox_attribute())
622 result.push_back(it.second);
623 return result;
624 }
625
626 std::vector<RTLIL::Module*> RTLIL::Design::selected_whole_modules() const
627 {
628 std::vector<RTLIL::Module*> result;
629 result.reserve(modules_.size());
630 for (auto &it : modules_)
631 if (selected_whole_module(it.first) && !it.second->get_blackbox_attribute())
632 result.push_back(it.second);
633 return result;
634 }
635
636 std::vector<RTLIL::Module*> RTLIL::Design::selected_whole_modules_warn() const
637 {
638 std::vector<RTLIL::Module*> result;
639 result.reserve(modules_.size());
640 for (auto &it : modules_)
641 if (it.second->get_blackbox_attribute())
642 continue;
643 else if (selected_whole_module(it.first))
644 result.push_back(it.second);
645 else if (selected_module(it.first))
646 log_warning("Ignoring partially selected module %s.\n", log_id(it.first));
647 return result;
648 }
649
650 RTLIL::Module::Module()
651 {
652 static unsigned int hashidx_count = 123456789;
653 hashidx_count = mkhash_xorshift(hashidx_count);
654 hashidx_ = hashidx_count;
655
656 design = nullptr;
657 refcount_wires_ = 0;
658 refcount_cells_ = 0;
659
660 #ifdef WITH_PYTHON
661 RTLIL::Module::get_all_modules()->insert(std::pair<unsigned int, RTLIL::Module*>(hashidx_, this));
662 #endif
663 }
664
665 RTLIL::Module::~Module()
666 {
667 for (auto it = wires_.begin(); it != wires_.end(); ++it)
668 delete it->second;
669 for (auto it = memories.begin(); it != memories.end(); ++it)
670 delete it->second;
671 for (auto it = cells_.begin(); it != cells_.end(); ++it)
672 delete it->second;
673 for (auto it = processes.begin(); it != processes.end(); ++it)
674 delete it->second;
675 #ifdef WITH_PYTHON
676 RTLIL::Module::get_all_modules()->erase(hashidx_);
677 #endif
678 }
679
680 #ifdef WITH_PYTHON
681 static std::map<unsigned int, RTLIL::Module*> all_modules;
682 std::map<unsigned int, RTLIL::Module*> *RTLIL::Module::get_all_modules(void)
683 {
684 return &all_modules;
685 }
686 #endif
687
688 void RTLIL::Module::makeblackbox()
689 {
690 pool<RTLIL::Wire*> delwires;
691
692 for (auto it = wires_.begin(); it != wires_.end(); ++it)
693 if (!it->second->port_input && !it->second->port_output)
694 delwires.insert(it->second);
695
696 for (auto it = memories.begin(); it != memories.end(); ++it)
697 delete it->second;
698 memories.clear();
699
700 for (auto it = cells_.begin(); it != cells_.end(); ++it)
701 delete it->second;
702 cells_.clear();
703
704 for (auto it = processes.begin(); it != processes.end(); ++it)
705 delete it->second;
706 processes.clear();
707
708 remove(delwires);
709 set_bool_attribute("\\blackbox");
710 }
711
712 void RTLIL::Module::reprocess_module(RTLIL::Design *, dict<RTLIL::IdString, RTLIL::Module *>)
713 {
714 log_error("Cannot reprocess_module module `%s' !\n", id2cstr(name));
715 }
716
717 RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, dict<RTLIL::IdString, RTLIL::Const>, bool mayfail)
718 {
719 if (mayfail)
720 return RTLIL::IdString();
721 log_error("Module `%s' is used with parameters but is not parametric!\n", id2cstr(name));
722 }
723
724
725 RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, dict<RTLIL::IdString, RTLIL::Const>, dict<RTLIL::IdString, RTLIL::Module*>, dict<RTLIL::IdString, RTLIL::IdString>, bool mayfail)
726 {
727 if (mayfail)
728 return RTLIL::IdString();
729 log_error("Module `%s' is used with parameters but is not parametric!\n", id2cstr(name));
730 }
731
732 size_t RTLIL::Module::count_id(RTLIL::IdString id)
733 {
734 return wires_.count(id) + memories.count(id) + cells_.count(id) + processes.count(id);
735 }
736
737 #ifndef NDEBUG
738 namespace {
739 struct InternalCellChecker
740 {
741 RTLIL::Module *module;
742 RTLIL::Cell *cell;
743 pool<RTLIL::IdString> expected_params, expected_ports;
744
745 InternalCellChecker(RTLIL::Module *module, RTLIL::Cell *cell) : module(module), cell(cell) { }
746
747 void error(int linenr)
748 {
749 std::stringstream buf;
750 ILANG_BACKEND::dump_cell(buf, " ", cell);
751
752 log_error("Found error in internal cell %s%s%s (%s) at %s:%d:\n%s",
753 module ? module->name.c_str() : "", module ? "." : "",
754 cell->name.c_str(), cell->type.c_str(), __FILE__, linenr, buf.str().c_str());
755 }
756
757 int param(const char *name)
758 {
759 if (cell->parameters.count(name) == 0)
760 error(__LINE__);
761 expected_params.insert(name);
762 return cell->parameters.at(name).as_int();
763 }
764
765 int param_bool(const char *name)
766 {
767 int v = param(name);
768 if (cell->parameters.at(name).bits.size() > 32)
769 error(__LINE__);
770 if (v != 0 && v != 1)
771 error(__LINE__);
772 return v;
773 }
774
775 void param_bits(const char *name, int width)
776 {
777 param(name);
778 if (int(cell->parameters.at(name).bits.size()) != width)
779 error(__LINE__);
780 }
781
782 void port(const char *name, int width)
783 {
784 if (!cell->hasPort(name))
785 error(__LINE__);
786 if (cell->getPort(name).size() != width)
787 error(__LINE__);
788 expected_ports.insert(name);
789 }
790
791 void check_expected(bool check_matched_sign = true)
792 {
793 for (auto &para : cell->parameters)
794 if (expected_params.count(para.first) == 0)
795 error(__LINE__);
796 for (auto &conn : cell->connections())
797 if (expected_ports.count(conn.first) == 0)
798 error(__LINE__);
799
800 if (expected_params.count("\\A_SIGNED") != 0 && expected_params.count("\\B_SIGNED") && check_matched_sign) {
801 bool a_is_signed = param("\\A_SIGNED") != 0;
802 bool b_is_signed = param("\\B_SIGNED") != 0;
803 if (a_is_signed != b_is_signed)
804 error(__LINE__);
805 }
806 }
807
808 void check_gate(const char *ports)
809 {
810 if (cell->parameters.size() != 0)
811 error(__LINE__);
812
813 for (const char *p = ports; *p; p++) {
814 char portname[3] = { '\\', *p, 0 };
815 if (!cell->hasPort(portname))
816 error(__LINE__);
817 if (cell->getPort(portname).size() != 1)
818 error(__LINE__);
819 }
820
821 for (auto &conn : cell->connections()) {
822 if (conn.first.size() != 2 || conn.first[0] != '\\')
823 error(__LINE__);
824 if (strchr(ports, conn.first[1]) == NULL)
825 error(__LINE__);
826 }
827 }
828
829 void check()
830 {
831 if (cell->type.substr(0, 1) != "$" || cell->type.substr(0, 3) == "$__" || cell->type.substr(0, 8) == "$paramod" || cell->type.substr(0,10) == "$fmcombine" ||
832 cell->type.substr(0, 9) == "$verific$" || cell->type.substr(0, 7) == "$array:" || cell->type.substr(0, 8) == "$extern:")
833 return;
834
835 if (cell->type.in("$not", "$pos", "$neg")) {
836 param_bool("\\A_SIGNED");
837 port("\\A", param("\\A_WIDTH"));
838 port("\\Y", param("\\Y_WIDTH"));
839 check_expected();
840 return;
841 }
842
843 if (cell->type.in("$and", "$or", "$xor", "$xnor")) {
844 param_bool("\\A_SIGNED");
845 param_bool("\\B_SIGNED");
846 port("\\A", param("\\A_WIDTH"));
847 port("\\B", param("\\B_WIDTH"));
848 port("\\Y", param("\\Y_WIDTH"));
849 check_expected();
850 return;
851 }
852
853 if (cell->type.in("$reduce_and", "$reduce_or", "$reduce_xor", "$reduce_xnor", "$reduce_bool")) {
854 param_bool("\\A_SIGNED");
855 port("\\A", param("\\A_WIDTH"));
856 port("\\Y", param("\\Y_WIDTH"));
857 check_expected();
858 return;
859 }
860
861 if (cell->type.in("$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx")) {
862 param_bool("\\A_SIGNED");
863 param_bool("\\B_SIGNED");
864 port("\\A", param("\\A_WIDTH"));
865 port("\\B", param("\\B_WIDTH"));
866 port("\\Y", param("\\Y_WIDTH"));
867 check_expected(false);
868 return;
869 }
870
871 if (cell->type.in("$lt", "$le", "$eq", "$ne", "$eqx", "$nex", "$ge", "$gt")) {
872 param_bool("\\A_SIGNED");
873 param_bool("\\B_SIGNED");
874 port("\\A", param("\\A_WIDTH"));
875 port("\\B", param("\\B_WIDTH"));
876 port("\\Y", param("\\Y_WIDTH"));
877 check_expected();
878 return;
879 }
880
881 if (cell->type.in("$add", "$sub", "$mul", "$div", "$mod", "$pow")) {
882 param_bool("\\A_SIGNED");
883 param_bool("\\B_SIGNED");
884 port("\\A", param("\\A_WIDTH"));
885 port("\\B", param("\\B_WIDTH"));
886 port("\\Y", param("\\Y_WIDTH"));
887 check_expected(cell->type != "$pow");
888 return;
889 }
890
891 if (cell->type == "$fa") {
892 port("\\A", param("\\WIDTH"));
893 port("\\B", param("\\WIDTH"));
894 port("\\C", param("\\WIDTH"));
895 port("\\X", param("\\WIDTH"));
896 port("\\Y", param("\\WIDTH"));
897 check_expected();
898 return;
899 }
900
901 if (cell->type == "$lcu") {
902 port("\\P", param("\\WIDTH"));
903 port("\\G", param("\\WIDTH"));
904 port("\\CI", 1);
905 port("\\CO", param("\\WIDTH"));
906 check_expected();
907 return;
908 }
909
910 if (cell->type == "$alu") {
911 param_bool("\\A_SIGNED");
912 param_bool("\\B_SIGNED");
913 port("\\A", param("\\A_WIDTH"));
914 port("\\B", param("\\B_WIDTH"));
915 port("\\CI", 1);
916 port("\\BI", 1);
917 port("\\X", param("\\Y_WIDTH"));
918 port("\\Y", param("\\Y_WIDTH"));
919 port("\\CO", param("\\Y_WIDTH"));
920 check_expected();
921 return;
922 }
923
924 if (cell->type == "$macc") {
925 param("\\CONFIG");
926 param("\\CONFIG_WIDTH");
927 port("\\A", param("\\A_WIDTH"));
928 port("\\B", param("\\B_WIDTH"));
929 port("\\Y", param("\\Y_WIDTH"));
930 check_expected();
931 Macc().from_cell(cell);
932 return;
933 }
934
935 if (cell->type == "$logic_not") {
936 param_bool("\\A_SIGNED");
937 port("\\A", param("\\A_WIDTH"));
938 port("\\Y", param("\\Y_WIDTH"));
939 check_expected();
940 return;
941 }
942
943 if (cell->type == "$logic_and" || cell->type == "$logic_or") {
944 param_bool("\\A_SIGNED");
945 param_bool("\\B_SIGNED");
946 port("\\A", param("\\A_WIDTH"));
947 port("\\B", param("\\B_WIDTH"));
948 port("\\Y", param("\\Y_WIDTH"));
949 check_expected(false);
950 return;
951 }
952
953 if (cell->type == "$slice") {
954 param("\\OFFSET");
955 port("\\A", param("\\A_WIDTH"));
956 port("\\Y", param("\\Y_WIDTH"));
957 if (param("\\OFFSET") + param("\\Y_WIDTH") > param("\\A_WIDTH"))
958 error(__LINE__);
959 check_expected();
960 return;
961 }
962
963 if (cell->type == "$concat") {
964 port("\\A", param("\\A_WIDTH"));
965 port("\\B", param("\\B_WIDTH"));
966 port("\\Y", param("\\A_WIDTH") + param("\\B_WIDTH"));
967 check_expected();
968 return;
969 }
970
971 if (cell->type == "$mux") {
972 port("\\A", param("\\WIDTH"));
973 port("\\B", param("\\WIDTH"));
974 port("\\S", 1);
975 port("\\Y", param("\\WIDTH"));
976 check_expected();
977 return;
978 }
979
980 if (cell->type == "$pmux") {
981 port("\\A", param("\\WIDTH"));
982 port("\\B", param("\\WIDTH") * param("\\S_WIDTH"));
983 port("\\S", param("\\S_WIDTH"));
984 port("\\Y", param("\\WIDTH"));
985 check_expected();
986 return;
987 }
988
989 if (cell->type == "$lut") {
990 param("\\LUT");
991 port("\\A", param("\\WIDTH"));
992 port("\\Y", 1);
993 check_expected();
994 return;
995 }
996
997 if (cell->type == "$sop") {
998 param("\\DEPTH");
999 param("\\TABLE");
1000 port("\\A", param("\\WIDTH"));
1001 port("\\Y", 1);
1002 check_expected();
1003 return;
1004 }
1005
1006 if (cell->type == "$sr") {
1007 param_bool("\\SET_POLARITY");
1008 param_bool("\\CLR_POLARITY");
1009 port("\\SET", param("\\WIDTH"));
1010 port("\\CLR", param("\\WIDTH"));
1011 port("\\Q", param("\\WIDTH"));
1012 check_expected();
1013 return;
1014 }
1015
1016 if (cell->type == "$ff") {
1017 port("\\D", param("\\WIDTH"));
1018 port("\\Q", param("\\WIDTH"));
1019 check_expected();
1020 return;
1021 }
1022
1023 if (cell->type == "$dff") {
1024 param_bool("\\CLK_POLARITY");
1025 port("\\CLK", 1);
1026 port("\\D", param("\\WIDTH"));
1027 port("\\Q", param("\\WIDTH"));
1028 check_expected();
1029 return;
1030 }
1031
1032 if (cell->type == "$dffe") {
1033 param_bool("\\CLK_POLARITY");
1034 param_bool("\\EN_POLARITY");
1035 port("\\CLK", 1);
1036 port("\\EN", 1);
1037 port("\\D", param("\\WIDTH"));
1038 port("\\Q", param("\\WIDTH"));
1039 check_expected();
1040 return;
1041 }
1042
1043 if (cell->type == "$dffsr") {
1044 param_bool("\\CLK_POLARITY");
1045 param_bool("\\SET_POLARITY");
1046 param_bool("\\CLR_POLARITY");
1047 port("\\CLK", 1);
1048 port("\\SET", param("\\WIDTH"));
1049 port("\\CLR", param("\\WIDTH"));
1050 port("\\D", param("\\WIDTH"));
1051 port("\\Q", param("\\WIDTH"));
1052 check_expected();
1053 return;
1054 }
1055
1056 if (cell->type == "$adff") {
1057 param_bool("\\CLK_POLARITY");
1058 param_bool("\\ARST_POLARITY");
1059 param_bits("\\ARST_VALUE", param("\\WIDTH"));
1060 port("\\CLK", 1);
1061 port("\\ARST", 1);
1062 port("\\D", param("\\WIDTH"));
1063 port("\\Q", param("\\WIDTH"));
1064 check_expected();
1065 return;
1066 }
1067
1068 if (cell->type == "$dlatch") {
1069 param_bool("\\EN_POLARITY");
1070 port("\\EN", 1);
1071 port("\\D", param("\\WIDTH"));
1072 port("\\Q", param("\\WIDTH"));
1073 check_expected();
1074 return;
1075 }
1076
1077 if (cell->type == "$dlatchsr") {
1078 param_bool("\\EN_POLARITY");
1079 param_bool("\\SET_POLARITY");
1080 param_bool("\\CLR_POLARITY");
1081 port("\\EN", 1);
1082 port("\\SET", param("\\WIDTH"));
1083 port("\\CLR", param("\\WIDTH"));
1084 port("\\D", param("\\WIDTH"));
1085 port("\\Q", param("\\WIDTH"));
1086 check_expected();
1087 return;
1088 }
1089
1090 if (cell->type == "$fsm") {
1091 param("\\NAME");
1092 param_bool("\\CLK_POLARITY");
1093 param_bool("\\ARST_POLARITY");
1094 param("\\STATE_BITS");
1095 param("\\STATE_NUM");
1096 param("\\STATE_NUM_LOG2");
1097 param("\\STATE_RST");
1098 param_bits("\\STATE_TABLE", param("\\STATE_BITS") * param("\\STATE_NUM"));
1099 param("\\TRANS_NUM");
1100 param_bits("\\TRANS_TABLE", param("\\TRANS_NUM") * (2*param("\\STATE_NUM_LOG2") + param("\\CTRL_IN_WIDTH") + param("\\CTRL_OUT_WIDTH")));
1101 port("\\CLK", 1);
1102 port("\\ARST", 1);
1103 port("\\CTRL_IN", param("\\CTRL_IN_WIDTH"));
1104 port("\\CTRL_OUT", param("\\CTRL_OUT_WIDTH"));
1105 check_expected();
1106 return;
1107 }
1108
1109 if (cell->type == "$memrd") {
1110 param("\\MEMID");
1111 param_bool("\\CLK_ENABLE");
1112 param_bool("\\CLK_POLARITY");
1113 param_bool("\\TRANSPARENT");
1114 port("\\CLK", 1);
1115 port("\\EN", 1);
1116 port("\\ADDR", param("\\ABITS"));
1117 port("\\DATA", param("\\WIDTH"));
1118 check_expected();
1119 return;
1120 }
1121
1122 if (cell->type == "$memwr") {
1123 param("\\MEMID");
1124 param_bool("\\CLK_ENABLE");
1125 param_bool("\\CLK_POLARITY");
1126 param("\\PRIORITY");
1127 port("\\CLK", 1);
1128 port("\\EN", param("\\WIDTH"));
1129 port("\\ADDR", param("\\ABITS"));
1130 port("\\DATA", param("\\WIDTH"));
1131 check_expected();
1132 return;
1133 }
1134
1135 if (cell->type == "$meminit") {
1136 param("\\MEMID");
1137 param("\\PRIORITY");
1138 port("\\ADDR", param("\\ABITS"));
1139 port("\\DATA", param("\\WIDTH") * param("\\WORDS"));
1140 check_expected();
1141 return;
1142 }
1143
1144 if (cell->type == "$mem") {
1145 param("\\MEMID");
1146 param("\\SIZE");
1147 param("\\OFFSET");
1148 param("\\INIT");
1149 param_bits("\\RD_CLK_ENABLE", max(1, param("\\RD_PORTS")));
1150 param_bits("\\RD_CLK_POLARITY", max(1, param("\\RD_PORTS")));
1151 param_bits("\\RD_TRANSPARENT", max(1, param("\\RD_PORTS")));
1152 param_bits("\\WR_CLK_ENABLE", max(1, param("\\WR_PORTS")));
1153 param_bits("\\WR_CLK_POLARITY", max(1, param("\\WR_PORTS")));
1154 port("\\RD_CLK", param("\\RD_PORTS"));
1155 port("\\RD_EN", param("\\RD_PORTS"));
1156 port("\\RD_ADDR", param("\\RD_PORTS") * param("\\ABITS"));
1157 port("\\RD_DATA", param("\\RD_PORTS") * param("\\WIDTH"));
1158 port("\\WR_CLK", param("\\WR_PORTS"));
1159 port("\\WR_EN", param("\\WR_PORTS") * param("\\WIDTH"));
1160 port("\\WR_ADDR", param("\\WR_PORTS") * param("\\ABITS"));
1161 port("\\WR_DATA", param("\\WR_PORTS") * param("\\WIDTH"));
1162 check_expected();
1163 return;
1164 }
1165
1166 if (cell->type == "$tribuf") {
1167 port("\\A", param("\\WIDTH"));
1168 port("\\Y", param("\\WIDTH"));
1169 port("\\EN", 1);
1170 check_expected();
1171 return;
1172 }
1173
1174 if (cell->type.in("$assert", "$assume", "$live", "$fair", "$cover")) {
1175 port("\\A", 1);
1176 port("\\EN", 1);
1177 check_expected();
1178 return;
1179 }
1180
1181 if (cell->type == "$initstate") {
1182 port("\\Y", 1);
1183 check_expected();
1184 return;
1185 }
1186
1187 if (cell->type.in("$anyconst", "$anyseq", "$allconst", "$allseq")) {
1188 port("\\Y", param("\\WIDTH"));
1189 check_expected();
1190 return;
1191 }
1192
1193 if (cell->type == "$equiv") {
1194 port("\\A", 1);
1195 port("\\B", 1);
1196 port("\\Y", 1);
1197 check_expected();
1198 return;
1199 }
1200
1201 if (cell->type.in("$specify2", "$specify3")) {
1202 param_bool("\\FULL");
1203 param_bool("\\SRC_DST_PEN");
1204 param_bool("\\SRC_DST_POL");
1205 param("\\T_RISE_MIN");
1206 param("\\T_RISE_TYP");
1207 param("\\T_RISE_MAX");
1208 param("\\T_FALL_MIN");
1209 param("\\T_FALL_TYP");
1210 param("\\T_FALL_MAX");
1211 port("\\EN", 1);
1212 port("\\SRC", param("\\SRC_WIDTH"));
1213 port("\\DST", param("\\DST_WIDTH"));
1214 if (cell->type == "$specify3") {
1215 param_bool("\\EDGE_EN");
1216 param_bool("\\EDGE_POL");
1217 param_bool("\\DAT_DST_PEN");
1218 param_bool("\\DAT_DST_POL");
1219 port("\\DAT", param("\\DST_WIDTH"));
1220 }
1221 check_expected();
1222 return;
1223 }
1224
1225 if (cell->type == "$specrule") {
1226 param("\\TYPE");
1227 param_bool("\\SRC_PEN");
1228 param_bool("\\SRC_POL");
1229 param_bool("\\DST_PEN");
1230 param_bool("\\DST_POL");
1231 param("\\T_LIMIT");
1232 param("\\T_LIMIT2");
1233 port("\\SRC_EN", 1);
1234 port("\\DST_EN", 1);
1235 port("\\SRC", param("\\SRC_WIDTH"));
1236 port("\\DST", param("\\DST_WIDTH"));
1237 check_expected();
1238 return;
1239 }
1240
1241 if (cell->type == "$_BUF_") { check_gate("AY"); return; }
1242 if (cell->type == "$_NOT_") { check_gate("AY"); return; }
1243 if (cell->type == "$_AND_") { check_gate("ABY"); return; }
1244 if (cell->type == "$_NAND_") { check_gate("ABY"); return; }
1245 if (cell->type == "$_OR_") { check_gate("ABY"); return; }
1246 if (cell->type == "$_NOR_") { check_gate("ABY"); return; }
1247 if (cell->type == "$_XOR_") { check_gate("ABY"); return; }
1248 if (cell->type == "$_XNOR_") { check_gate("ABY"); return; }
1249 if (cell->type == "$_ANDNOT_") { check_gate("ABY"); return; }
1250 if (cell->type == "$_ORNOT_") { check_gate("ABY"); return; }
1251 if (cell->type == "$_MUX_") { check_gate("ABSY"); return; }
1252 if (cell->type == "$_AOI3_") { check_gate("ABCY"); return; }
1253 if (cell->type == "$_OAI3_") { check_gate("ABCY"); return; }
1254 if (cell->type == "$_AOI4_") { check_gate("ABCDY"); return; }
1255 if (cell->type == "$_OAI4_") { check_gate("ABCDY"); return; }
1256
1257 if (cell->type == "$_TBUF_") { check_gate("AYE"); return; }
1258
1259 if (cell->type == "$_MUX4_") { check_gate("ABCDSTY"); return; }
1260 if (cell->type == "$_MUX8_") { check_gate("ABCDEFGHSTUY"); return; }
1261 if (cell->type == "$_MUX16_") { check_gate("ABCDEFGHIJKLMNOPSTUVY"); return; }
1262
1263 if (cell->type == "$_SR_NN_") { check_gate("SRQ"); return; }
1264 if (cell->type == "$_SR_NP_") { check_gate("SRQ"); return; }
1265 if (cell->type == "$_SR_PN_") { check_gate("SRQ"); return; }
1266 if (cell->type == "$_SR_PP_") { check_gate("SRQ"); return; }
1267
1268 if (cell->type == "$_FF_") { check_gate("DQ"); return; }
1269 if (cell->type == "$_DFF_N_") { check_gate("DQC"); return; }
1270 if (cell->type == "$_DFF_P_") { check_gate("DQC"); return; }
1271
1272 if (cell->type == "$_DFFE_NN_") { check_gate("DQCE"); return; }
1273 if (cell->type == "$_DFFE_NP_") { check_gate("DQCE"); return; }
1274 if (cell->type == "$_DFFE_PN_") { check_gate("DQCE"); return; }
1275 if (cell->type == "$_DFFE_PP_") { check_gate("DQCE"); return; }
1276
1277 if (cell->type == "$_DFF_NN0_") { check_gate("DQCR"); return; }
1278 if (cell->type == "$_DFF_NN1_") { check_gate("DQCR"); return; }
1279 if (cell->type == "$_DFF_NP0_") { check_gate("DQCR"); return; }
1280 if (cell->type == "$_DFF_NP1_") { check_gate("DQCR"); return; }
1281 if (cell->type == "$_DFF_PN0_") { check_gate("DQCR"); return; }
1282 if (cell->type == "$_DFF_PN1_") { check_gate("DQCR"); return; }
1283 if (cell->type == "$_DFF_PP0_") { check_gate("DQCR"); return; }
1284 if (cell->type == "$_DFF_PP1_") { check_gate("DQCR"); return; }
1285
1286 if (cell->type == "$_DFFSR_NNN_") { check_gate("CSRDQ"); return; }
1287 if (cell->type == "$_DFFSR_NNP_") { check_gate("CSRDQ"); return; }
1288 if (cell->type == "$_DFFSR_NPN_") { check_gate("CSRDQ"); return; }
1289 if (cell->type == "$_DFFSR_NPP_") { check_gate("CSRDQ"); return; }
1290 if (cell->type == "$_DFFSR_PNN_") { check_gate("CSRDQ"); return; }
1291 if (cell->type == "$_DFFSR_PNP_") { check_gate("CSRDQ"); return; }
1292 if (cell->type == "$_DFFSR_PPN_") { check_gate("CSRDQ"); return; }
1293 if (cell->type == "$_DFFSR_PPP_") { check_gate("CSRDQ"); return; }
1294
1295 if (cell->type == "$_DLATCH_N_") { check_gate("EDQ"); return; }
1296 if (cell->type == "$_DLATCH_P_") { check_gate("EDQ"); return; }
1297
1298 if (cell->type == "$_DLATCHSR_NNN_") { check_gate("ESRDQ"); return; }
1299 if (cell->type == "$_DLATCHSR_NNP_") { check_gate("ESRDQ"); return; }
1300 if (cell->type == "$_DLATCHSR_NPN_") { check_gate("ESRDQ"); return; }
1301 if (cell->type == "$_DLATCHSR_NPP_") { check_gate("ESRDQ"); return; }
1302 if (cell->type == "$_DLATCHSR_PNN_") { check_gate("ESRDQ"); return; }
1303 if (cell->type == "$_DLATCHSR_PNP_") { check_gate("ESRDQ"); return; }
1304 if (cell->type == "$_DLATCHSR_PPN_") { check_gate("ESRDQ"); return; }
1305 if (cell->type == "$_DLATCHSR_PPP_") { check_gate("ESRDQ"); return; }
1306
1307 error(__LINE__);
1308 }
1309 };
1310 }
1311 #endif
1312
1313 void RTLIL::Module::sort()
1314 {
1315 wires_.sort(sort_by_id_str());
1316 cells_.sort(sort_by_id_str());
1317 avail_parameters.sort(sort_by_id_str());
1318 memories.sort(sort_by_id_str());
1319 processes.sort(sort_by_id_str());
1320 for (auto &it : cells_)
1321 it.second->sort();
1322 for (auto &it : wires_)
1323 it.second->attributes.sort(sort_by_id_str());
1324 for (auto &it : memories)
1325 it.second->attributes.sort(sort_by_id_str());
1326 }
1327
1328 void RTLIL::Module::check()
1329 {
1330 #ifndef NDEBUG
1331 std::vector<bool> ports_declared;
1332 for (auto &it : wires_) {
1333 log_assert(this == it.second->module);
1334 log_assert(it.first == it.second->name);
1335 log_assert(!it.first.empty());
1336 log_assert(it.second->width >= 0);
1337 log_assert(it.second->port_id >= 0);
1338 for (auto &it2 : it.second->attributes)
1339 log_assert(!it2.first.empty());
1340 if (it.second->port_id) {
1341 log_assert(GetSize(ports) >= it.second->port_id);
1342 log_assert(ports.at(it.second->port_id-1) == it.first);
1343 log_assert(it.second->port_input || it.second->port_output);
1344 if (GetSize(ports_declared) < it.second->port_id)
1345 ports_declared.resize(it.second->port_id);
1346 log_assert(ports_declared[it.second->port_id-1] == false);
1347 ports_declared[it.second->port_id-1] = true;
1348 } else
1349 log_assert(!it.second->port_input && !it.second->port_output);
1350 }
1351 for (auto port_declared : ports_declared)
1352 log_assert(port_declared == true);
1353 log_assert(GetSize(ports) == GetSize(ports_declared));
1354
1355 for (auto &it : memories) {
1356 log_assert(it.first == it.second->name);
1357 log_assert(!it.first.empty());
1358 log_assert(it.second->width >= 0);
1359 log_assert(it.second->size >= 0);
1360 for (auto &it2 : it.second->attributes)
1361 log_assert(!it2.first.empty());
1362 }
1363
1364 for (auto &it : cells_) {
1365 log_assert(this == it.second->module);
1366 log_assert(it.first == it.second->name);
1367 log_assert(!it.first.empty());
1368 log_assert(!it.second->type.empty());
1369 for (auto &it2 : it.second->connections()) {
1370 log_assert(!it2.first.empty());
1371 it2.second.check();
1372 }
1373 for (auto &it2 : it.second->attributes)
1374 log_assert(!it2.first.empty());
1375 for (auto &it2 : it.second->parameters)
1376 log_assert(!it2.first.empty());
1377 InternalCellChecker checker(this, it.second);
1378 checker.check();
1379 }
1380
1381 for (auto &it : processes) {
1382 log_assert(it.first == it.second->name);
1383 log_assert(!it.first.empty());
1384 // FIXME: More checks here..
1385 }
1386
1387 for (auto &it : connections_) {
1388 log_assert(it.first.size() == it.second.size());
1389 log_assert(!it.first.has_const());
1390 it.first.check();
1391 it.second.check();
1392 }
1393
1394 for (auto &it : attributes)
1395 log_assert(!it.first.empty());
1396 #endif
1397 }
1398
1399 void RTLIL::Module::optimize()
1400 {
1401 }
1402
1403 void RTLIL::Module::cloneInto(RTLIL::Module *new_mod) const
1404 {
1405 log_assert(new_mod->refcount_wires_ == 0);
1406 log_assert(new_mod->refcount_cells_ == 0);
1407
1408 new_mod->avail_parameters = avail_parameters;
1409
1410 for (auto &conn : connections_)
1411 new_mod->connect(conn);
1412
1413 for (auto &attr : attributes)
1414 new_mod->attributes[attr.first] = attr.second;
1415
1416 for (auto &it : wires_)
1417 new_mod->addWire(it.first, it.second);
1418
1419 for (auto &it : memories)
1420 new_mod->memories[it.first] = new RTLIL::Memory(*it.second);
1421
1422 for (auto &it : cells_)
1423 new_mod->addCell(it.first, it.second);
1424
1425 for (auto &it : processes)
1426 new_mod->processes[it.first] = it.second->clone();
1427
1428 struct RewriteSigSpecWorker
1429 {
1430 RTLIL::Module *mod;
1431 void operator()(RTLIL::SigSpec &sig)
1432 {
1433 std::vector<RTLIL::SigChunk> chunks = sig.chunks();
1434 for (auto &c : chunks)
1435 if (c.wire != NULL)
1436 c.wire = mod->wires_.at(c.wire->name);
1437 sig = chunks;
1438 }
1439 };
1440
1441 RewriteSigSpecWorker rewriteSigSpecWorker;
1442 rewriteSigSpecWorker.mod = new_mod;
1443 new_mod->rewrite_sigspecs(rewriteSigSpecWorker);
1444 new_mod->fixup_ports();
1445 }
1446
1447 RTLIL::Module *RTLIL::Module::clone() const
1448 {
1449 RTLIL::Module *new_mod = new RTLIL::Module;
1450 new_mod->name = name;
1451 cloneInto(new_mod);
1452 return new_mod;
1453 }
1454
1455 bool RTLIL::Module::has_memories() const
1456 {
1457 return !memories.empty();
1458 }
1459
1460 bool RTLIL::Module::has_processes() const
1461 {
1462 return !processes.empty();
1463 }
1464
1465 bool RTLIL::Module::has_memories_warn() const
1466 {
1467 if (!memories.empty())
1468 log_warning("Ignoring module %s because it contains memories (run 'memory' command first).\n", log_id(this));
1469 return !memories.empty();
1470 }
1471
1472 bool RTLIL::Module::has_processes_warn() const
1473 {
1474 if (!processes.empty())
1475 log_warning("Ignoring module %s because it contains processes (run 'proc' command first).\n", log_id(this));
1476 return !processes.empty();
1477 }
1478
1479 std::vector<RTLIL::Wire*> RTLIL::Module::selected_wires() const
1480 {
1481 std::vector<RTLIL::Wire*> result;
1482 result.reserve(wires_.size());
1483 for (auto &it : wires_)
1484 if (design->selected(this, it.second))
1485 result.push_back(it.second);
1486 return result;
1487 }
1488
1489 std::vector<RTLIL::Cell*> RTLIL::Module::selected_cells() const
1490 {
1491 std::vector<RTLIL::Cell*> result;
1492 result.reserve(wires_.size());
1493 for (auto &it : cells_)
1494 if (design->selected(this, it.second))
1495 result.push_back(it.second);
1496 return result;
1497 }
1498
1499 void RTLIL::Module::add(RTLIL::Wire *wire)
1500 {
1501 log_assert(!wire->name.empty());
1502 log_assert(count_id(wire->name) == 0);
1503 log_assert(refcount_wires_ == 0);
1504 wires_[wire->name] = wire;
1505 wire->module = this;
1506 }
1507
1508 void RTLIL::Module::add(RTLIL::Cell *cell)
1509 {
1510 log_assert(!cell->name.empty());
1511 log_assert(count_id(cell->name) == 0);
1512 log_assert(refcount_cells_ == 0);
1513 cells_[cell->name] = cell;
1514 cell->module = this;
1515 }
1516
1517 void RTLIL::Module::remove(const pool<RTLIL::Wire*> &wires)
1518 {
1519 log_assert(refcount_wires_ == 0);
1520
1521 struct DeleteWireWorker
1522 {
1523 RTLIL::Module *module;
1524 const pool<RTLIL::Wire*> *wires_p;
1525
1526 void operator()(RTLIL::SigSpec &sig) {
1527 std::vector<RTLIL::SigChunk> chunks = sig;
1528 for (auto &c : chunks)
1529 if (c.wire != NULL && wires_p->count(c.wire)) {
1530 c.wire = module->addWire(NEW_ID, c.width);
1531 c.offset = 0;
1532 }
1533 sig = chunks;
1534 }
1535
1536 void operator()(RTLIL::SigSpec &lhs, RTLIL::SigSpec &rhs) {
1537 log_assert(GetSize(lhs) == GetSize(rhs));
1538 RTLIL::SigSpec new_lhs, new_rhs;
1539 for (int i = 0; i < GetSize(lhs); i++) {
1540 RTLIL::SigBit lhs_bit = lhs[i];
1541 if (lhs_bit.wire != nullptr && wires_p->count(lhs_bit.wire))
1542 continue;
1543 RTLIL::SigBit rhs_bit = rhs[i];
1544 if (rhs_bit.wire != nullptr && wires_p->count(rhs_bit.wire))
1545 continue;
1546 new_lhs.append(lhs_bit);
1547 new_rhs.append(rhs_bit);
1548 }
1549 lhs = new_lhs;
1550 rhs = new_rhs;
1551 }
1552 };
1553
1554 DeleteWireWorker delete_wire_worker;
1555 delete_wire_worker.module = this;
1556 delete_wire_worker.wires_p = &wires;
1557 rewrite_sigspecs2(delete_wire_worker);
1558
1559 for (auto &it : wires) {
1560 log_assert(wires_.count(it->name) != 0);
1561 wires_.erase(it->name);
1562 delete it;
1563 }
1564 }
1565
1566 void RTLIL::Module::remove(RTLIL::Cell *cell)
1567 {
1568 while (!cell->connections_.empty())
1569 cell->unsetPort(cell->connections_.begin()->first);
1570
1571 log_assert(cells_.count(cell->name) != 0);
1572 log_assert(refcount_cells_ == 0);
1573 cells_.erase(cell->name);
1574 delete cell;
1575 }
1576
1577 void RTLIL::Module::rename(RTLIL::Wire *wire, RTLIL::IdString new_name)
1578 {
1579 log_assert(wires_[wire->name] == wire);
1580 log_assert(refcount_wires_ == 0);
1581 wires_.erase(wire->name);
1582 wire->name = new_name;
1583 add(wire);
1584 }
1585
1586 void RTLIL::Module::rename(RTLIL::Cell *cell, RTLIL::IdString new_name)
1587 {
1588 log_assert(cells_[cell->name] == cell);
1589 log_assert(refcount_wires_ == 0);
1590 cells_.erase(cell->name);
1591 cell->name = new_name;
1592 add(cell);
1593 }
1594
1595 void RTLIL::Module::rename(RTLIL::IdString old_name, RTLIL::IdString new_name)
1596 {
1597 log_assert(count_id(old_name) != 0);
1598 if (wires_.count(old_name))
1599 rename(wires_.at(old_name), new_name);
1600 else if (cells_.count(old_name))
1601 rename(cells_.at(old_name), new_name);
1602 else
1603 log_abort();
1604 }
1605
1606 void RTLIL::Module::swap_names(RTLIL::Wire *w1, RTLIL::Wire *w2)
1607 {
1608 log_assert(wires_[w1->name] == w1);
1609 log_assert(wires_[w2->name] == w2);
1610 log_assert(refcount_wires_ == 0);
1611
1612 wires_.erase(w1->name);
1613 wires_.erase(w2->name);
1614
1615 std::swap(w1->name, w2->name);
1616
1617 wires_[w1->name] = w1;
1618 wires_[w2->name] = w2;
1619 }
1620
1621 void RTLIL::Module::swap_names(RTLIL::Cell *c1, RTLIL::Cell *c2)
1622 {
1623 log_assert(cells_[c1->name] == c1);
1624 log_assert(cells_[c2->name] == c2);
1625 log_assert(refcount_cells_ == 0);
1626
1627 cells_.erase(c1->name);
1628 cells_.erase(c2->name);
1629
1630 std::swap(c1->name, c2->name);
1631
1632 cells_[c1->name] = c1;
1633 cells_[c2->name] = c2;
1634 }
1635
1636 RTLIL::IdString RTLIL::Module::uniquify(RTLIL::IdString name)
1637 {
1638 int index = 0;
1639 return uniquify(name, index);
1640 }
1641
1642 RTLIL::IdString RTLIL::Module::uniquify(RTLIL::IdString name, int &index)
1643 {
1644 if (index == 0) {
1645 if (count_id(name) == 0)
1646 return name;
1647 index++;
1648 }
1649
1650 while (1) {
1651 RTLIL::IdString new_name = stringf("%s_%d", name.c_str(), index);
1652 if (count_id(new_name) == 0)
1653 return new_name;
1654 index++;
1655 }
1656 }
1657
1658 static bool fixup_ports_compare(const RTLIL::Wire *a, const RTLIL::Wire *b)
1659 {
1660 if (a->port_id && !b->port_id)
1661 return true;
1662 if (!a->port_id && b->port_id)
1663 return false;
1664
1665 if (a->port_id == b->port_id)
1666 return a->name < b->name;
1667 return a->port_id < b->port_id;
1668 }
1669
1670 void RTLIL::Module::connect(const RTLIL::SigSig &conn)
1671 {
1672 for (auto mon : monitors)
1673 mon->notify_connect(this, conn);
1674
1675 if (design)
1676 for (auto mon : design->monitors)
1677 mon->notify_connect(this, conn);
1678
1679 // ignore all attempts to assign constants to other constants
1680 if (conn.first.has_const()) {
1681 RTLIL::SigSig new_conn;
1682 for (int i = 0; i < GetSize(conn.first); i++)
1683 if (conn.first[i].wire) {
1684 new_conn.first.append(conn.first[i]);
1685 new_conn.second.append(conn.second[i]);
1686 }
1687 if (GetSize(new_conn.first))
1688 connect(new_conn);
1689 return;
1690 }
1691
1692 if (yosys_xtrace) {
1693 log("#X# Connect (SigSig) in %s: %s = %s (%d bits)\n", log_id(this), log_signal(conn.first), log_signal(conn.second), GetSize(conn.first));
1694 log_backtrace("-X- ", yosys_xtrace-1);
1695 }
1696
1697 log_assert(GetSize(conn.first) == GetSize(conn.second));
1698 connections_.push_back(conn);
1699 }
1700
1701 void RTLIL::Module::connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs)
1702 {
1703 connect(RTLIL::SigSig(lhs, rhs));
1704 }
1705
1706 void RTLIL::Module::new_connections(const std::vector<RTLIL::SigSig> &new_conn)
1707 {
1708 for (auto mon : monitors)
1709 mon->notify_connect(this, new_conn);
1710
1711 if (design)
1712 for (auto mon : design->monitors)
1713 mon->notify_connect(this, new_conn);
1714
1715 if (yosys_xtrace) {
1716 log("#X# New connections vector in %s:\n", log_id(this));
1717 for (auto &conn: new_conn)
1718 log("#X# %s = %s (%d bits)\n", log_signal(conn.first), log_signal(conn.second), GetSize(conn.first));
1719 log_backtrace("-X- ", yosys_xtrace-1);
1720 }
1721
1722 connections_ = new_conn;
1723 }
1724
1725 const std::vector<RTLIL::SigSig> &RTLIL::Module::connections() const
1726 {
1727 return connections_;
1728 }
1729
1730 void RTLIL::Module::fixup_ports()
1731 {
1732 std::vector<RTLIL::Wire*> all_ports;
1733
1734 for (auto &w : wires_)
1735 if (w.second->port_input || w.second->port_output)
1736 all_ports.push_back(w.second);
1737 else
1738 w.second->port_id = 0;
1739
1740 std::sort(all_ports.begin(), all_ports.end(), fixup_ports_compare);
1741
1742 ports.clear();
1743 for (size_t i = 0; i < all_ports.size(); i++) {
1744 ports.push_back(all_ports[i]->name);
1745 all_ports[i]->port_id = i+1;
1746 }
1747 }
1748
1749 RTLIL::Wire *RTLIL::Module::addWire(RTLIL::IdString name, int width)
1750 {
1751 RTLIL::Wire *wire = new RTLIL::Wire;
1752 wire->name = name;
1753 wire->width = width;
1754 add(wire);
1755 return wire;
1756 }
1757
1758 RTLIL::Wire *RTLIL::Module::addWire(RTLIL::IdString name, const RTLIL::Wire *other)
1759 {
1760 RTLIL::Wire *wire = addWire(name);
1761 wire->width = other->width;
1762 wire->start_offset = other->start_offset;
1763 wire->port_id = other->port_id;
1764 wire->port_input = other->port_input;
1765 wire->port_output = other->port_output;
1766 wire->upto = other->upto;
1767 wire->attributes = other->attributes;
1768 return wire;
1769 }
1770
1771 RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, RTLIL::IdString type)
1772 {
1773 RTLIL::Cell *cell = new RTLIL::Cell;
1774 cell->name = name;
1775 cell->type = type;
1776 add(cell);
1777 return cell;
1778 }
1779
1780 RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, const RTLIL::Cell *other)
1781 {
1782 RTLIL::Cell *cell = addCell(name, other->type);
1783 cell->connections_ = other->connections_;
1784 cell->parameters = other->parameters;
1785 cell->attributes = other->attributes;
1786 return cell;
1787 }
1788
1789 #define DEF_METHOD(_func, _y_size, _type) \
1790 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed, const std::string &src) { \
1791 RTLIL::Cell *cell = addCell(name, _type); \
1792 cell->parameters["\\A_SIGNED"] = is_signed; \
1793 cell->parameters["\\A_WIDTH"] = sig_a.size(); \
1794 cell->parameters["\\Y_WIDTH"] = sig_y.size(); \
1795 cell->setPort("\\A", sig_a); \
1796 cell->setPort("\\Y", sig_y); \
1797 cell->set_src_attribute(src); \
1798 return cell; \
1799 } \
1800 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed, const std::string &src) { \
1801 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
1802 add ## _func(name, sig_a, sig_y, is_signed, src); \
1803 return sig_y; \
1804 }
1805 DEF_METHOD(Not, sig_a.size(), "$not")
1806 DEF_METHOD(Pos, sig_a.size(), "$pos")
1807 DEF_METHOD(Neg, sig_a.size(), "$neg")
1808 DEF_METHOD(ReduceAnd, 1, "$reduce_and")
1809 DEF_METHOD(ReduceOr, 1, "$reduce_or")
1810 DEF_METHOD(ReduceXor, 1, "$reduce_xor")
1811 DEF_METHOD(ReduceXnor, 1, "$reduce_xnor")
1812 DEF_METHOD(ReduceBool, 1, "$reduce_bool")
1813 DEF_METHOD(LogicNot, 1, "$logic_not")
1814 #undef DEF_METHOD
1815
1816 #define DEF_METHOD(_func, _y_size, _type) \
1817 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed, const std::string &src) { \
1818 RTLIL::Cell *cell = addCell(name, _type); \
1819 cell->parameters["\\A_SIGNED"] = is_signed; \
1820 cell->parameters["\\B_SIGNED"] = is_signed; \
1821 cell->parameters["\\A_WIDTH"] = sig_a.size(); \
1822 cell->parameters["\\B_WIDTH"] = sig_b.size(); \
1823 cell->parameters["\\Y_WIDTH"] = sig_y.size(); \
1824 cell->setPort("\\A", sig_a); \
1825 cell->setPort("\\B", sig_b); \
1826 cell->setPort("\\Y", sig_y); \
1827 cell->set_src_attribute(src); \
1828 return cell; \
1829 } \
1830 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed, const std::string &src) { \
1831 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
1832 add ## _func(name, sig_a, sig_b, sig_y, is_signed, src); \
1833 return sig_y; \
1834 }
1835 DEF_METHOD(And, max(sig_a.size(), sig_b.size()), "$and")
1836 DEF_METHOD(Or, max(sig_a.size(), sig_b.size()), "$or")
1837 DEF_METHOD(Xor, max(sig_a.size(), sig_b.size()), "$xor")
1838 DEF_METHOD(Xnor, max(sig_a.size(), sig_b.size()), "$xnor")
1839 DEF_METHOD(Shl, sig_a.size(), "$shl")
1840 DEF_METHOD(Shr, sig_a.size(), "$shr")
1841 DEF_METHOD(Sshl, sig_a.size(), "$sshl")
1842 DEF_METHOD(Sshr, sig_a.size(), "$sshr")
1843 DEF_METHOD(Shift, sig_a.size(), "$shift")
1844 DEF_METHOD(Shiftx, sig_a.size(), "$shiftx")
1845 DEF_METHOD(Lt, 1, "$lt")
1846 DEF_METHOD(Le, 1, "$le")
1847 DEF_METHOD(Eq, 1, "$eq")
1848 DEF_METHOD(Ne, 1, "$ne")
1849 DEF_METHOD(Eqx, 1, "$eqx")
1850 DEF_METHOD(Nex, 1, "$nex")
1851 DEF_METHOD(Ge, 1, "$ge")
1852 DEF_METHOD(Gt, 1, "$gt")
1853 DEF_METHOD(Add, max(sig_a.size(), sig_b.size()), "$add")
1854 DEF_METHOD(Sub, max(sig_a.size(), sig_b.size()), "$sub")
1855 DEF_METHOD(Mul, max(sig_a.size(), sig_b.size()), "$mul")
1856 DEF_METHOD(Div, max(sig_a.size(), sig_b.size()), "$div")
1857 DEF_METHOD(Mod, max(sig_a.size(), sig_b.size()), "$mod")
1858 DEF_METHOD(LogicAnd, 1, "$logic_and")
1859 DEF_METHOD(LogicOr, 1, "$logic_or")
1860 #undef DEF_METHOD
1861
1862 #define DEF_METHOD(_func, _type, _pmux) \
1863 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, RTLIL::SigSpec sig_y, const std::string &src) { \
1864 RTLIL::Cell *cell = addCell(name, _type); \
1865 cell->parameters["\\WIDTH"] = sig_a.size(); \
1866 if (_pmux) cell->parameters["\\S_WIDTH"] = sig_s.size(); \
1867 cell->setPort("\\A", sig_a); \
1868 cell->setPort("\\B", sig_b); \
1869 cell->setPort("\\S", sig_s); \
1870 cell->setPort("\\Y", sig_y); \
1871 cell->set_src_attribute(src); \
1872 return cell; \
1873 } \
1874 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, const std::string &src) { \
1875 RTLIL::SigSpec sig_y = addWire(NEW_ID, sig_a.size()); \
1876 add ## _func(name, sig_a, sig_b, sig_s, sig_y, src); \
1877 return sig_y; \
1878 }
1879 DEF_METHOD(Mux, "$mux", 0)
1880 DEF_METHOD(Pmux, "$pmux", 1)
1881 #undef DEF_METHOD
1882
1883 #define DEF_METHOD_2(_func, _type, _P1, _P2) \
1884 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, const std::string &src) { \
1885 RTLIL::Cell *cell = addCell(name, _type); \
1886 cell->setPort("\\" #_P1, sig1); \
1887 cell->setPort("\\" #_P2, sig2); \
1888 cell->set_src_attribute(src); \
1889 return cell; \
1890 } \
1891 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, const std::string &src) { \
1892 RTLIL::SigBit sig2 = addWire(NEW_ID); \
1893 add ## _func(name, sig1, sig2, src); \
1894 return sig2; \
1895 }
1896 #define DEF_METHOD_3(_func, _type, _P1, _P2, _P3) \
1897 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, const std::string &src) { \
1898 RTLIL::Cell *cell = addCell(name, _type); \
1899 cell->setPort("\\" #_P1, sig1); \
1900 cell->setPort("\\" #_P2, sig2); \
1901 cell->setPort("\\" #_P3, sig3); \
1902 cell->set_src_attribute(src); \
1903 return cell; \
1904 } \
1905 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, const std::string &src) { \
1906 RTLIL::SigBit sig3 = addWire(NEW_ID); \
1907 add ## _func(name, sig1, sig2, sig3, src); \
1908 return sig3; \
1909 }
1910 #define DEF_METHOD_4(_func, _type, _P1, _P2, _P3, _P4) \
1911 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, RTLIL::SigBit sig4, const std::string &src) { \
1912 RTLIL::Cell *cell = addCell(name, _type); \
1913 cell->setPort("\\" #_P1, sig1); \
1914 cell->setPort("\\" #_P2, sig2); \
1915 cell->setPort("\\" #_P3, sig3); \
1916 cell->setPort("\\" #_P4, sig4); \
1917 cell->set_src_attribute(src); \
1918 return cell; \
1919 } \
1920 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, const std::string &src) { \
1921 RTLIL::SigBit sig4 = addWire(NEW_ID); \
1922 add ## _func(name, sig1, sig2, sig3, sig4, src); \
1923 return sig4; \
1924 }
1925 #define DEF_METHOD_5(_func, _type, _P1, _P2, _P3, _P4, _P5) \
1926 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, RTLIL::SigBit sig4, RTLIL::SigBit sig5, const std::string &src) { \
1927 RTLIL::Cell *cell = addCell(name, _type); \
1928 cell->setPort("\\" #_P1, sig1); \
1929 cell->setPort("\\" #_P2, sig2); \
1930 cell->setPort("\\" #_P3, sig3); \
1931 cell->setPort("\\" #_P4, sig4); \
1932 cell->setPort("\\" #_P5, sig5); \
1933 cell->set_src_attribute(src); \
1934 return cell; \
1935 } \
1936 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, RTLIL::SigBit sig4, const std::string &src) { \
1937 RTLIL::SigBit sig5 = addWire(NEW_ID); \
1938 add ## _func(name, sig1, sig2, sig3, sig4, sig5, src); \
1939 return sig5; \
1940 }
1941 DEF_METHOD_2(BufGate, "$_BUF_", A, Y)
1942 DEF_METHOD_2(NotGate, "$_NOT_", A, Y)
1943 DEF_METHOD_3(AndGate, "$_AND_", A, B, Y)
1944 DEF_METHOD_3(NandGate, "$_NAND_", A, B, Y)
1945 DEF_METHOD_3(OrGate, "$_OR_", A, B, Y)
1946 DEF_METHOD_3(NorGate, "$_NOR_", A, B, Y)
1947 DEF_METHOD_3(XorGate, "$_XOR_", A, B, Y)
1948 DEF_METHOD_3(XnorGate, "$_XNOR_", A, B, Y)
1949 DEF_METHOD_3(AndnotGate, "$_ANDNOT_", A, B, Y)
1950 DEF_METHOD_3(OrnotGate, "$_ORNOT_", A, B, Y)
1951 DEF_METHOD_4(MuxGate, "$_MUX_", A, B, S, Y)
1952 DEF_METHOD_4(Aoi3Gate, "$_AOI3_", A, B, C, Y)
1953 DEF_METHOD_4(Oai3Gate, "$_OAI3_", A, B, C, Y)
1954 DEF_METHOD_5(Aoi4Gate, "$_AOI4_", A, B, C, D, Y)
1955 DEF_METHOD_5(Oai4Gate, "$_OAI4_", A, B, C, D, Y)
1956 #undef DEF_METHOD_2
1957 #undef DEF_METHOD_3
1958 #undef DEF_METHOD_4
1959 #undef DEF_METHOD_5
1960
1961 RTLIL::Cell* RTLIL::Module::addPow(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool a_signed, bool b_signed, const std::string &src)
1962 {
1963 RTLIL::Cell *cell = addCell(name, "$pow");
1964 cell->parameters["\\A_SIGNED"] = a_signed;
1965 cell->parameters["\\B_SIGNED"] = b_signed;
1966 cell->parameters["\\A_WIDTH"] = sig_a.size();
1967 cell->parameters["\\B_WIDTH"] = sig_b.size();
1968 cell->parameters["\\Y_WIDTH"] = sig_y.size();
1969 cell->setPort("\\A", sig_a);
1970 cell->setPort("\\B", sig_b);
1971 cell->setPort("\\Y", sig_y);
1972 cell->set_src_attribute(src);
1973 return cell;
1974 }
1975
1976 RTLIL::Cell* RTLIL::Module::addSlice(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, RTLIL::Const offset, const std::string &src)
1977 {
1978 RTLIL::Cell *cell = addCell(name, "$slice");
1979 cell->parameters["\\A_WIDTH"] = sig_a.size();
1980 cell->parameters["\\Y_WIDTH"] = sig_y.size();
1981 cell->parameters["\\OFFSET"] = offset;
1982 cell->setPort("\\A", sig_a);
1983 cell->setPort("\\Y", sig_y);
1984 cell->set_src_attribute(src);
1985 return cell;
1986 }
1987
1988 RTLIL::Cell* RTLIL::Module::addConcat(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, const std::string &src)
1989 {
1990 RTLIL::Cell *cell = addCell(name, "$concat");
1991 cell->parameters["\\A_WIDTH"] = sig_a.size();
1992 cell->parameters["\\B_WIDTH"] = sig_b.size();
1993 cell->setPort("\\A", sig_a);
1994 cell->setPort("\\B", sig_b);
1995 cell->setPort("\\Y", sig_y);
1996 cell->set_src_attribute(src);
1997 return cell;
1998 }
1999
2000 RTLIL::Cell* RTLIL::Module::addLut(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, RTLIL::Const lut, const std::string &src)
2001 {
2002 RTLIL::Cell *cell = addCell(name, "$lut");
2003 cell->parameters["\\LUT"] = lut;
2004 cell->parameters["\\WIDTH"] = sig_a.size();
2005 cell->setPort("\\A", sig_a);
2006 cell->setPort("\\Y", sig_y);
2007 cell->set_src_attribute(src);
2008 return cell;
2009 }
2010
2011 RTLIL::Cell* RTLIL::Module::addTribuf(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_y, const std::string &src)
2012 {
2013 RTLIL::Cell *cell = addCell(name, "$tribuf");
2014 cell->parameters["\\WIDTH"] = sig_a.size();
2015 cell->setPort("\\A", sig_a);
2016 cell->setPort("\\EN", sig_en);
2017 cell->setPort("\\Y", sig_y);
2018 cell->set_src_attribute(src);
2019 return cell;
2020 }
2021
2022 RTLIL::Cell* RTLIL::Module::addAssert(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src)
2023 {
2024 RTLIL::Cell *cell = addCell(name, "$assert");
2025 cell->setPort("\\A", sig_a);
2026 cell->setPort("\\EN", sig_en);
2027 cell->set_src_attribute(src);
2028 return cell;
2029 }
2030
2031 RTLIL::Cell* RTLIL::Module::addAssume(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src)
2032 {
2033 RTLIL::Cell *cell = addCell(name, "$assume");
2034 cell->setPort("\\A", sig_a);
2035 cell->setPort("\\EN", sig_en);
2036 cell->set_src_attribute(src);
2037 return cell;
2038 }
2039
2040 RTLIL::Cell* RTLIL::Module::addLive(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src)
2041 {
2042 RTLIL::Cell *cell = addCell(name, "$live");
2043 cell->setPort("\\A", sig_a);
2044 cell->setPort("\\EN", sig_en);
2045 cell->set_src_attribute(src);
2046 return cell;
2047 }
2048
2049 RTLIL::Cell* RTLIL::Module::addFair(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src)
2050 {
2051 RTLIL::Cell *cell = addCell(name, "$fair");
2052 cell->setPort("\\A", sig_a);
2053 cell->setPort("\\EN", sig_en);
2054 cell->set_src_attribute(src);
2055 return cell;
2056 }
2057
2058 RTLIL::Cell* RTLIL::Module::addCover(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src)
2059 {
2060 RTLIL::Cell *cell = addCell(name, "$cover");
2061 cell->setPort("\\A", sig_a);
2062 cell->setPort("\\EN", sig_en);
2063 cell->set_src_attribute(src);
2064 return cell;
2065 }
2066
2067 RTLIL::Cell* RTLIL::Module::addEquiv(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, const std::string &src)
2068 {
2069 RTLIL::Cell *cell = addCell(name, "$equiv");
2070 cell->setPort("\\A", sig_a);
2071 cell->setPort("\\B", sig_b);
2072 cell->setPort("\\Y", sig_y);
2073 cell->set_src_attribute(src);
2074 return cell;
2075 }
2076
2077 RTLIL::Cell* RTLIL::Module::addSr(RTLIL::IdString name, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr, RTLIL::SigSpec sig_q, bool set_polarity, bool clr_polarity, const std::string &src)
2078 {
2079 RTLIL::Cell *cell = addCell(name, "$sr");
2080 cell->parameters["\\SET_POLARITY"] = set_polarity;
2081 cell->parameters["\\CLR_POLARITY"] = clr_polarity;
2082 cell->parameters["\\WIDTH"] = sig_q.size();
2083 cell->setPort("\\SET", sig_set);
2084 cell->setPort("\\CLR", sig_clr);
2085 cell->setPort("\\Q", sig_q);
2086 cell->set_src_attribute(src);
2087 return cell;
2088 }
2089
2090 RTLIL::Cell* RTLIL::Module::addFf(RTLIL::IdString name, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, const std::string &src)
2091 {
2092 RTLIL::Cell *cell = addCell(name, "$ff");
2093 cell->parameters["\\WIDTH"] = sig_q.size();
2094 cell->setPort("\\D", sig_d);
2095 cell->setPort("\\Q", sig_q);
2096 cell->set_src_attribute(src);
2097 return cell;
2098 }
2099
2100 RTLIL::Cell* RTLIL::Module::addDff(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, const std::string &src)
2101 {
2102 RTLIL::Cell *cell = addCell(name, "$dff");
2103 cell->parameters["\\CLK_POLARITY"] = clk_polarity;
2104 cell->parameters["\\WIDTH"] = sig_q.size();
2105 cell->setPort("\\CLK", sig_clk);
2106 cell->setPort("\\D", sig_d);
2107 cell->setPort("\\Q", sig_q);
2108 cell->set_src_attribute(src);
2109 return cell;
2110 }
2111
2112 RTLIL::Cell* RTLIL::Module::addDffe(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, bool en_polarity, const std::string &src)
2113 {
2114 RTLIL::Cell *cell = addCell(name, "$dffe");
2115 cell->parameters["\\CLK_POLARITY"] = clk_polarity;
2116 cell->parameters["\\EN_POLARITY"] = en_polarity;
2117 cell->parameters["\\WIDTH"] = sig_q.size();
2118 cell->setPort("\\CLK", sig_clk);
2119 cell->setPort("\\EN", sig_en);
2120 cell->setPort("\\D", sig_d);
2121 cell->setPort("\\Q", sig_q);
2122 cell->set_src_attribute(src);
2123 return cell;
2124 }
2125
2126 RTLIL::Cell* RTLIL::Module::addDffsr(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
2127 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
2128 {
2129 RTLIL::Cell *cell = addCell(name, "$dffsr");
2130 cell->parameters["\\CLK_POLARITY"] = clk_polarity;
2131 cell->parameters["\\SET_POLARITY"] = set_polarity;
2132 cell->parameters["\\CLR_POLARITY"] = clr_polarity;
2133 cell->parameters["\\WIDTH"] = sig_q.size();
2134 cell->setPort("\\CLK", sig_clk);
2135 cell->setPort("\\SET", sig_set);
2136 cell->setPort("\\CLR", sig_clr);
2137 cell->setPort("\\D", sig_d);
2138 cell->setPort("\\Q", sig_q);
2139 cell->set_src_attribute(src);
2140 return cell;
2141 }
2142
2143 RTLIL::Cell* RTLIL::Module::addAdff(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_arst, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q,
2144 RTLIL::Const arst_value, bool clk_polarity, bool arst_polarity, const std::string &src)
2145 {
2146 RTLIL::Cell *cell = addCell(name, "$adff");
2147 cell->parameters["\\CLK_POLARITY"] = clk_polarity;
2148 cell->parameters["\\ARST_POLARITY"] = arst_polarity;
2149 cell->parameters["\\ARST_VALUE"] = arst_value;
2150 cell->parameters["\\WIDTH"] = sig_q.size();
2151 cell->setPort("\\CLK", sig_clk);
2152 cell->setPort("\\ARST", sig_arst);
2153 cell->setPort("\\D", sig_d);
2154 cell->setPort("\\Q", sig_q);
2155 cell->set_src_attribute(src);
2156 return cell;
2157 }
2158
2159 RTLIL::Cell* RTLIL::Module::addDlatch(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity, const std::string &src)
2160 {
2161 RTLIL::Cell *cell = addCell(name, "$dlatch");
2162 cell->parameters["\\EN_POLARITY"] = en_polarity;
2163 cell->parameters["\\WIDTH"] = sig_q.size();
2164 cell->setPort("\\EN", sig_en);
2165 cell->setPort("\\D", sig_d);
2166 cell->setPort("\\Q", sig_q);
2167 cell->set_src_attribute(src);
2168 return cell;
2169 }
2170
2171 RTLIL::Cell* RTLIL::Module::addDlatchsr(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
2172 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
2173 {
2174 RTLIL::Cell *cell = addCell(name, "$dlatchsr");
2175 cell->parameters["\\EN_POLARITY"] = en_polarity;
2176 cell->parameters["\\SET_POLARITY"] = set_polarity;
2177 cell->parameters["\\CLR_POLARITY"] = clr_polarity;
2178 cell->parameters["\\WIDTH"] = sig_q.size();
2179 cell->setPort("\\EN", sig_en);
2180 cell->setPort("\\SET", sig_set);
2181 cell->setPort("\\CLR", sig_clr);
2182 cell->setPort("\\D", sig_d);
2183 cell->setPort("\\Q", sig_q);
2184 cell->set_src_attribute(src);
2185 return cell;
2186 }
2187
2188 RTLIL::Cell* RTLIL::Module::addFfGate(RTLIL::IdString name, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, const std::string &src)
2189 {
2190 RTLIL::Cell *cell = addCell(name, "$_FF_");
2191 cell->setPort("\\D", sig_d);
2192 cell->setPort("\\Q", sig_q);
2193 cell->set_src_attribute(src);
2194 return cell;
2195 }
2196
2197 RTLIL::Cell* RTLIL::Module::addDffGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, const std::string &src)
2198 {
2199 RTLIL::Cell *cell = addCell(name, stringf("$_DFF_%c_", clk_polarity ? 'P' : 'N'));
2200 cell->setPort("\\C", sig_clk);
2201 cell->setPort("\\D", sig_d);
2202 cell->setPort("\\Q", sig_q);
2203 cell->set_src_attribute(src);
2204 return cell;
2205 }
2206
2207 RTLIL::Cell* RTLIL::Module::addDffeGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, bool en_polarity, const std::string &src)
2208 {
2209 RTLIL::Cell *cell = addCell(name, stringf("$_DFFE_%c%c_", clk_polarity ? 'P' : 'N', en_polarity ? 'P' : 'N'));
2210 cell->setPort("\\C", sig_clk);
2211 cell->setPort("\\E", sig_en);
2212 cell->setPort("\\D", sig_d);
2213 cell->setPort("\\Q", sig_q);
2214 cell->set_src_attribute(src);
2215 return cell;
2216 }
2217
2218 RTLIL::Cell* RTLIL::Module::addDffsrGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
2219 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
2220 {
2221 RTLIL::Cell *cell = addCell(name, stringf("$_DFFSR_%c%c%c_", clk_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N'));
2222 cell->setPort("\\C", sig_clk);
2223 cell->setPort("\\S", sig_set);
2224 cell->setPort("\\R", sig_clr);
2225 cell->setPort("\\D", sig_d);
2226 cell->setPort("\\Q", sig_q);
2227 cell->set_src_attribute(src);
2228 return cell;
2229 }
2230
2231 RTLIL::Cell* RTLIL::Module::addAdffGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_arst, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q,
2232 bool arst_value, bool clk_polarity, bool arst_polarity, const std::string &src)
2233 {
2234 RTLIL::Cell *cell = addCell(name, stringf("$_DFF_%c%c%c_", clk_polarity ? 'P' : 'N', arst_polarity ? 'P' : 'N', arst_value ? '1' : '0'));
2235 cell->setPort("\\C", sig_clk);
2236 cell->setPort("\\R", sig_arst);
2237 cell->setPort("\\D", sig_d);
2238 cell->setPort("\\Q", sig_q);
2239 cell->set_src_attribute(src);
2240 return cell;
2241 }
2242
2243 RTLIL::Cell* RTLIL::Module::addDlatchGate(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity, const std::string &src)
2244 {
2245 RTLIL::Cell *cell = addCell(name, stringf("$_DLATCH_%c_", en_polarity ? 'P' : 'N'));
2246 cell->setPort("\\E", sig_en);
2247 cell->setPort("\\D", sig_d);
2248 cell->setPort("\\Q", sig_q);
2249 cell->set_src_attribute(src);
2250 return cell;
2251 }
2252
2253 RTLIL::Cell* RTLIL::Module::addDlatchsrGate(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
2254 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
2255 {
2256 RTLIL::Cell *cell = addCell(name, stringf("$_DLATCHSR_%c%c%c_", en_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N'));
2257 cell->setPort("\\E", sig_en);
2258 cell->setPort("\\S", sig_set);
2259 cell->setPort("\\R", sig_clr);
2260 cell->setPort("\\D", sig_d);
2261 cell->setPort("\\Q", sig_q);
2262 cell->set_src_attribute(src);
2263 return cell;
2264 }
2265
2266 RTLIL::SigSpec RTLIL::Module::Anyconst(RTLIL::IdString name, int width, const std::string &src)
2267 {
2268 RTLIL::SigSpec sig = addWire(NEW_ID, width);
2269 Cell *cell = addCell(name, "$anyconst");
2270 cell->setParam("\\WIDTH", width);
2271 cell->setPort("\\Y", sig);
2272 cell->set_src_attribute(src);
2273 return sig;
2274 }
2275
2276 RTLIL::SigSpec RTLIL::Module::Anyseq(RTLIL::IdString name, int width, const std::string &src)
2277 {
2278 RTLIL::SigSpec sig = addWire(NEW_ID, width);
2279 Cell *cell = addCell(name, "$anyseq");
2280 cell->setParam("\\WIDTH", width);
2281 cell->setPort("\\Y", sig);
2282 cell->set_src_attribute(src);
2283 return sig;
2284 }
2285
2286 RTLIL::SigSpec RTLIL::Module::Allconst(RTLIL::IdString name, int width, const std::string &src)
2287 {
2288 RTLIL::SigSpec sig = addWire(NEW_ID, width);
2289 Cell *cell = addCell(name, "$allconst");
2290 cell->setParam("\\WIDTH", width);
2291 cell->setPort("\\Y", sig);
2292 cell->set_src_attribute(src);
2293 return sig;
2294 }
2295
2296 RTLIL::SigSpec RTLIL::Module::Allseq(RTLIL::IdString name, int width, const std::string &src)
2297 {
2298 RTLIL::SigSpec sig = addWire(NEW_ID, width);
2299 Cell *cell = addCell(name, "$allseq");
2300 cell->setParam("\\WIDTH", width);
2301 cell->setPort("\\Y", sig);
2302 cell->set_src_attribute(src);
2303 return sig;
2304 }
2305
2306 RTLIL::SigSpec RTLIL::Module::Initstate(RTLIL::IdString name, const std::string &src)
2307 {
2308 RTLIL::SigSpec sig = addWire(NEW_ID);
2309 Cell *cell = addCell(name, "$initstate");
2310 cell->setPort("\\Y", sig);
2311 cell->set_src_attribute(src);
2312 return sig;
2313 }
2314
2315 RTLIL::Wire::Wire()
2316 {
2317 static unsigned int hashidx_count = 123456789;
2318 hashidx_count = mkhash_xorshift(hashidx_count);
2319 hashidx_ = hashidx_count;
2320
2321 module = nullptr;
2322 width = 1;
2323 start_offset = 0;
2324 port_id = 0;
2325 port_input = false;
2326 port_output = false;
2327 upto = false;
2328
2329 #ifdef WITH_PYTHON
2330 RTLIL::Wire::get_all_wires()->insert(std::pair<unsigned int, RTLIL::Wire*>(hashidx_, this));
2331 #endif
2332 }
2333
2334 RTLIL::Wire::~Wire()
2335 {
2336 #ifdef WITH_PYTHON
2337 RTLIL::Wire::get_all_wires()->erase(hashidx_);
2338 #endif
2339 }
2340
2341 #ifdef WITH_PYTHON
2342 static std::map<unsigned int, RTLIL::Wire*> all_wires;
2343 std::map<unsigned int, RTLIL::Wire*> *RTLIL::Wire::get_all_wires(void)
2344 {
2345 return &all_wires;
2346 }
2347 #endif
2348
2349 RTLIL::Memory::Memory()
2350 {
2351 static unsigned int hashidx_count = 123456789;
2352 hashidx_count = mkhash_xorshift(hashidx_count);
2353 hashidx_ = hashidx_count;
2354
2355 width = 1;
2356 start_offset = 0;
2357 size = 0;
2358 #ifdef WITH_PYTHON
2359 RTLIL::Memory::get_all_memorys()->insert(std::pair<unsigned int, RTLIL::Memory*>(hashidx_, this));
2360 #endif
2361 }
2362
2363 RTLIL::Cell::Cell() : module(nullptr)
2364 {
2365 static unsigned int hashidx_count = 123456789;
2366 hashidx_count = mkhash_xorshift(hashidx_count);
2367 hashidx_ = hashidx_count;
2368
2369 // log("#memtrace# %p\n", this);
2370 memhasher();
2371
2372 #ifdef WITH_PYTHON
2373 RTLIL::Cell::get_all_cells()->insert(std::pair<unsigned int, RTLIL::Cell*>(hashidx_, this));
2374 #endif
2375 }
2376
2377 RTLIL::Cell::~Cell()
2378 {
2379 #ifdef WITH_PYTHON
2380 RTLIL::Cell::get_all_cells()->erase(hashidx_);
2381 #endif
2382 }
2383
2384 #ifdef WITH_PYTHON
2385 static std::map<unsigned int, RTLIL::Cell*> all_cells;
2386 std::map<unsigned int, RTLIL::Cell*> *RTLIL::Cell::get_all_cells(void)
2387 {
2388 return &all_cells;
2389 }
2390 #endif
2391
2392 bool RTLIL::Cell::hasPort(RTLIL::IdString portname) const
2393 {
2394 return connections_.count(portname) != 0;
2395 }
2396
2397 void RTLIL::Cell::unsetPort(RTLIL::IdString portname)
2398 {
2399 RTLIL::SigSpec signal;
2400 auto conn_it = connections_.find(portname);
2401
2402 if (conn_it != connections_.end())
2403 {
2404 for (auto mon : module->monitors)
2405 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
2406
2407 if (module->design)
2408 for (auto mon : module->design->monitors)
2409 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
2410
2411 if (yosys_xtrace) {
2412 log("#X# Unconnect %s.%s.%s\n", log_id(this->module), log_id(this), log_id(portname));
2413 log_backtrace("-X- ", yosys_xtrace-1);
2414 }
2415
2416 connections_.erase(conn_it);
2417 }
2418 }
2419
2420 void RTLIL::Cell::setPort(RTLIL::IdString portname, RTLIL::SigSpec signal)
2421 {
2422 auto conn_it = connections_.find(portname);
2423
2424 if (conn_it == connections_.end()) {
2425 connections_[portname] = RTLIL::SigSpec();
2426 conn_it = connections_.find(portname);
2427 log_assert(conn_it != connections_.end());
2428 } else
2429 if (conn_it->second == signal)
2430 return;
2431
2432 for (auto mon : module->monitors)
2433 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
2434
2435 if (module->design)
2436 for (auto mon : module->design->monitors)
2437 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
2438
2439 if (yosys_xtrace) {
2440 log("#X# Connect %s.%s.%s = %s (%d)\n", log_id(this->module), log_id(this), log_id(portname), log_signal(signal), GetSize(signal));
2441 log_backtrace("-X- ", yosys_xtrace-1);
2442 }
2443
2444 conn_it->second = signal;
2445 }
2446
2447 const RTLIL::SigSpec &RTLIL::Cell::getPort(RTLIL::IdString portname) const
2448 {
2449 return connections_.at(portname);
2450 }
2451
2452 const dict<RTLIL::IdString, RTLIL::SigSpec> &RTLIL::Cell::connections() const
2453 {
2454 return connections_;
2455 }
2456
2457 bool RTLIL::Cell::known() const
2458 {
2459 if (yosys_celltypes.cell_known(type))
2460 return true;
2461 if (module && module->design && module->design->module(type))
2462 return true;
2463 return false;
2464 }
2465
2466 bool RTLIL::Cell::input(RTLIL::IdString portname) const
2467 {
2468 if (yosys_celltypes.cell_known(type))
2469 return yosys_celltypes.cell_input(type, portname);
2470 if (module && module->design) {
2471 RTLIL::Module *m = module->design->module(type);
2472 RTLIL::Wire *w = m ? m->wire(portname) : nullptr;
2473 return w && w->port_input;
2474 }
2475 return false;
2476 }
2477
2478 bool RTLIL::Cell::output(RTLIL::IdString portname) const
2479 {
2480 if (yosys_celltypes.cell_known(type))
2481 return yosys_celltypes.cell_output(type, portname);
2482 if (module && module->design) {
2483 RTLIL::Module *m = module->design->module(type);
2484 RTLIL::Wire *w = m ? m->wire(portname) : nullptr;
2485 return w && w->port_output;
2486 }
2487 return false;
2488 }
2489
2490 bool RTLIL::Cell::hasParam(RTLIL::IdString paramname) const
2491 {
2492 return parameters.count(paramname) != 0;
2493 }
2494
2495 void RTLIL::Cell::unsetParam(RTLIL::IdString paramname)
2496 {
2497 parameters.erase(paramname);
2498 }
2499
2500 void RTLIL::Cell::setParam(RTLIL::IdString paramname, RTLIL::Const value)
2501 {
2502 parameters[paramname] = value;
2503 }
2504
2505 const RTLIL::Const &RTLIL::Cell::getParam(RTLIL::IdString paramname) const
2506 {
2507 return parameters.at(paramname);
2508 }
2509
2510 void RTLIL::Cell::sort()
2511 {
2512 connections_.sort(sort_by_id_str());
2513 parameters.sort(sort_by_id_str());
2514 attributes.sort(sort_by_id_str());
2515 }
2516
2517 void RTLIL::Cell::check()
2518 {
2519 #ifndef NDEBUG
2520 InternalCellChecker checker(NULL, this);
2521 checker.check();
2522 #endif
2523 }
2524
2525 void RTLIL::Cell::fixup_parameters(bool set_a_signed, bool set_b_signed)
2526 {
2527 if (type.substr(0, 1) != "$" || type.substr(0, 2) == "$_" || type.substr(0, 8) == "$paramod" || type.substr(0,10) == "$fmcombine" ||
2528 type.substr(0, 9) == "$verific$" || type.substr(0, 7) == "$array:" || type.substr(0, 8) == "$extern:")
2529 return;
2530
2531 if (type == "$mux" || type == "$pmux") {
2532 parameters["\\WIDTH"] = GetSize(connections_["\\Y"]);
2533 if (type == "$pmux")
2534 parameters["\\S_WIDTH"] = GetSize(connections_["\\S"]);
2535 check();
2536 return;
2537 }
2538
2539 if (type == "$lut" || type == "$sop") {
2540 parameters["\\WIDTH"] = GetSize(connections_["\\A"]);
2541 return;
2542 }
2543
2544 if (type == "$fa") {
2545 parameters["\\WIDTH"] = GetSize(connections_["\\Y"]);
2546 return;
2547 }
2548
2549 if (type == "$lcu") {
2550 parameters["\\WIDTH"] = GetSize(connections_["\\CO"]);
2551 return;
2552 }
2553
2554 bool signedness_ab = !type.in("$slice", "$concat", "$macc");
2555
2556 if (connections_.count("\\A")) {
2557 if (signedness_ab) {
2558 if (set_a_signed)
2559 parameters["\\A_SIGNED"] = true;
2560 else if (parameters.count("\\A_SIGNED") == 0)
2561 parameters["\\A_SIGNED"] = false;
2562 }
2563 parameters["\\A_WIDTH"] = GetSize(connections_["\\A"]);
2564 }
2565
2566 if (connections_.count("\\B")) {
2567 if (signedness_ab) {
2568 if (set_b_signed)
2569 parameters["\\B_SIGNED"] = true;
2570 else if (parameters.count("\\B_SIGNED") == 0)
2571 parameters["\\B_SIGNED"] = false;
2572 }
2573 parameters["\\B_WIDTH"] = GetSize(connections_["\\B"]);
2574 }
2575
2576 if (connections_.count("\\Y"))
2577 parameters["\\Y_WIDTH"] = GetSize(connections_["\\Y"]);
2578
2579 if (connections_.count("\\Q"))
2580 parameters["\\WIDTH"] = GetSize(connections_["\\Q"]);
2581
2582 check();
2583 }
2584
2585 RTLIL::SigChunk::SigChunk()
2586 {
2587 wire = NULL;
2588 width = 0;
2589 offset = 0;
2590 }
2591
2592 RTLIL::SigChunk::SigChunk(const RTLIL::Const &value)
2593 {
2594 wire = NULL;
2595 data = value.bits;
2596 width = GetSize(data);
2597 offset = 0;
2598 }
2599
2600 RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire)
2601 {
2602 log_assert(wire != nullptr);
2603 this->wire = wire;
2604 this->width = wire->width;
2605 this->offset = 0;
2606 }
2607
2608 RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire, int offset, int width)
2609 {
2610 log_assert(wire != nullptr);
2611 this->wire = wire;
2612 this->width = width;
2613 this->offset = offset;
2614 }
2615
2616 RTLIL::SigChunk::SigChunk(const std::string &str)
2617 {
2618 wire = NULL;
2619 data = RTLIL::Const(str).bits;
2620 width = GetSize(data);
2621 offset = 0;
2622 }
2623
2624 RTLIL::SigChunk::SigChunk(int val, int width)
2625 {
2626 wire = NULL;
2627 data = RTLIL::Const(val, width).bits;
2628 this->width = GetSize(data);
2629 offset = 0;
2630 }
2631
2632 RTLIL::SigChunk::SigChunk(RTLIL::State bit, int width)
2633 {
2634 wire = NULL;
2635 data = RTLIL::Const(bit, width).bits;
2636 this->width = GetSize(data);
2637 offset = 0;
2638 }
2639
2640 RTLIL::SigChunk::SigChunk(RTLIL::SigBit bit)
2641 {
2642 wire = bit.wire;
2643 offset = 0;
2644 if (wire == NULL)
2645 data = RTLIL::Const(bit.data).bits;
2646 else
2647 offset = bit.offset;
2648 width = 1;
2649 }
2650
2651 RTLIL::SigChunk::SigChunk(const RTLIL::SigChunk &sigchunk) : data(sigchunk.data)
2652 {
2653 wire = sigchunk.wire;
2654 data = sigchunk.data;
2655 width = sigchunk.width;
2656 offset = sigchunk.offset;
2657 }
2658
2659 RTLIL::SigChunk RTLIL::SigChunk::extract(int offset, int length) const
2660 {
2661 RTLIL::SigChunk ret;
2662 if (wire) {
2663 ret.wire = wire;
2664 ret.offset = this->offset + offset;
2665 ret.width = length;
2666 } else {
2667 for (int i = 0; i < length; i++)
2668 ret.data.push_back(data[offset+i]);
2669 ret.width = length;
2670 }
2671 return ret;
2672 }
2673
2674 bool RTLIL::SigChunk::operator <(const RTLIL::SigChunk &other) const
2675 {
2676 if (wire && other.wire)
2677 if (wire->name != other.wire->name)
2678 return wire->name < other.wire->name;
2679
2680 if (wire != other.wire)
2681 return wire < other.wire;
2682
2683 if (offset != other.offset)
2684 return offset < other.offset;
2685
2686 if (width != other.width)
2687 return width < other.width;
2688
2689 return data < other.data;
2690 }
2691
2692 bool RTLIL::SigChunk::operator ==(const RTLIL::SigChunk &other) const
2693 {
2694 return wire == other.wire && width == other.width && offset == other.offset && data == other.data;
2695 }
2696
2697 bool RTLIL::SigChunk::operator !=(const RTLIL::SigChunk &other) const
2698 {
2699 if (*this == other)
2700 return false;
2701 return true;
2702 }
2703
2704 RTLIL::SigSpec::SigSpec()
2705 {
2706 width_ = 0;
2707 hash_ = 0;
2708 }
2709
2710 RTLIL::SigSpec::SigSpec(const RTLIL::SigSpec &other)
2711 {
2712 *this = other;
2713 }
2714
2715 RTLIL::SigSpec::SigSpec(std::initializer_list<RTLIL::SigSpec> parts)
2716 {
2717 cover("kernel.rtlil.sigspec.init.list");
2718
2719 width_ = 0;
2720 hash_ = 0;
2721
2722 std::vector<RTLIL::SigSpec> parts_vec(parts.begin(), parts.end());
2723 for (auto it = parts_vec.rbegin(); it != parts_vec.rend(); it++)
2724 append(*it);
2725 }
2726
2727 const RTLIL::SigSpec &RTLIL::SigSpec::operator=(const RTLIL::SigSpec &other)
2728 {
2729 cover("kernel.rtlil.sigspec.assign");
2730
2731 width_ = other.width_;
2732 hash_ = other.hash_;
2733 chunks_ = other.chunks_;
2734 bits_.clear();
2735
2736 if (!other.bits_.empty())
2737 {
2738 RTLIL::SigChunk *last = NULL;
2739 int last_end_offset = 0;
2740
2741 for (auto &bit : other.bits_) {
2742 if (last && bit.wire == last->wire) {
2743 if (bit.wire == NULL) {
2744 last->data.push_back(bit.data);
2745 last->width++;
2746 continue;
2747 } else if (last_end_offset == bit.offset) {
2748 last_end_offset++;
2749 last->width++;
2750 continue;
2751 }
2752 }
2753 chunks_.push_back(bit);
2754 last = &chunks_.back();
2755 last_end_offset = bit.offset + 1;
2756 }
2757
2758 check();
2759 }
2760
2761 return *this;
2762 }
2763
2764 RTLIL::SigSpec::SigSpec(const RTLIL::Const &value)
2765 {
2766 cover("kernel.rtlil.sigspec.init.const");
2767
2768 chunks_.push_back(RTLIL::SigChunk(value));
2769 width_ = chunks_.back().width;
2770 hash_ = 0;
2771 check();
2772 }
2773
2774 RTLIL::SigSpec::SigSpec(const RTLIL::SigChunk &chunk)
2775 {
2776 cover("kernel.rtlil.sigspec.init.chunk");
2777
2778 chunks_.push_back(chunk);
2779 width_ = chunks_.back().width;
2780 hash_ = 0;
2781 check();
2782 }
2783
2784 RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire)
2785 {
2786 cover("kernel.rtlil.sigspec.init.wire");
2787
2788 chunks_.push_back(RTLIL::SigChunk(wire));
2789 width_ = chunks_.back().width;
2790 hash_ = 0;
2791 check();
2792 }
2793
2794 RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire, int offset, int width)
2795 {
2796 cover("kernel.rtlil.sigspec.init.wire_part");
2797
2798 chunks_.push_back(RTLIL::SigChunk(wire, offset, width));
2799 width_ = chunks_.back().width;
2800 hash_ = 0;
2801 check();
2802 }
2803
2804 RTLIL::SigSpec::SigSpec(const std::string &str)
2805 {
2806 cover("kernel.rtlil.sigspec.init.str");
2807
2808 chunks_.push_back(RTLIL::SigChunk(str));
2809 width_ = chunks_.back().width;
2810 hash_ = 0;
2811 check();
2812 }
2813
2814 RTLIL::SigSpec::SigSpec(int val, int width)
2815 {
2816 cover("kernel.rtlil.sigspec.init.int");
2817
2818 chunks_.push_back(RTLIL::SigChunk(val, width));
2819 width_ = width;
2820 hash_ = 0;
2821 check();
2822 }
2823
2824 RTLIL::SigSpec::SigSpec(RTLIL::State bit, int width)
2825 {
2826 cover("kernel.rtlil.sigspec.init.state");
2827
2828 chunks_.push_back(RTLIL::SigChunk(bit, width));
2829 width_ = width;
2830 hash_ = 0;
2831 check();
2832 }
2833
2834 RTLIL::SigSpec::SigSpec(RTLIL::SigBit bit, int width)
2835 {
2836 cover("kernel.rtlil.sigspec.init.bit");
2837
2838 if (bit.wire == NULL)
2839 chunks_.push_back(RTLIL::SigChunk(bit.data, width));
2840 else
2841 for (int i = 0; i < width; i++)
2842 chunks_.push_back(bit);
2843 width_ = width;
2844 hash_ = 0;
2845 check();
2846 }
2847
2848 RTLIL::SigSpec::SigSpec(std::vector<RTLIL::SigChunk> chunks)
2849 {
2850 cover("kernel.rtlil.sigspec.init.stdvec_chunks");
2851
2852 width_ = 0;
2853 hash_ = 0;
2854 for (auto &c : chunks)
2855 append(c);
2856 check();
2857 }
2858
2859 RTLIL::SigSpec::SigSpec(std::vector<RTLIL::SigBit> bits)
2860 {
2861 cover("kernel.rtlil.sigspec.init.stdvec_bits");
2862
2863 width_ = 0;
2864 hash_ = 0;
2865 for (auto &bit : bits)
2866 append_bit(bit);
2867 check();
2868 }
2869
2870 RTLIL::SigSpec::SigSpec(pool<RTLIL::SigBit> bits)
2871 {
2872 cover("kernel.rtlil.sigspec.init.pool_bits");
2873
2874 width_ = 0;
2875 hash_ = 0;
2876 for (auto &bit : bits)
2877 append_bit(bit);
2878 check();
2879 }
2880
2881 RTLIL::SigSpec::SigSpec(std::set<RTLIL::SigBit> bits)
2882 {
2883 cover("kernel.rtlil.sigspec.init.stdset_bits");
2884
2885 width_ = 0;
2886 hash_ = 0;
2887 for (auto &bit : bits)
2888 append_bit(bit);
2889 check();
2890 }
2891
2892 RTLIL::SigSpec::SigSpec(bool bit)
2893 {
2894 cover("kernel.rtlil.sigspec.init.bool");
2895
2896 width_ = 0;
2897 hash_ = 0;
2898 append_bit(bit);
2899 check();
2900 }
2901
2902 void RTLIL::SigSpec::pack() const
2903 {
2904 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
2905
2906 if (that->bits_.empty())
2907 return;
2908
2909 cover("kernel.rtlil.sigspec.convert.pack");
2910 log_assert(that->chunks_.empty());
2911
2912 std::vector<RTLIL::SigBit> old_bits;
2913 old_bits.swap(that->bits_);
2914
2915 RTLIL::SigChunk *last = NULL;
2916 int last_end_offset = 0;
2917
2918 for (auto &bit : old_bits) {
2919 if (last && bit.wire == last->wire) {
2920 if (bit.wire == NULL) {
2921 last->data.push_back(bit.data);
2922 last->width++;
2923 continue;
2924 } else if (last_end_offset == bit.offset) {
2925 last_end_offset++;
2926 last->width++;
2927 continue;
2928 }
2929 }
2930 that->chunks_.push_back(bit);
2931 last = &that->chunks_.back();
2932 last_end_offset = bit.offset + 1;
2933 }
2934
2935 check();
2936 }
2937
2938 void RTLIL::SigSpec::unpack() const
2939 {
2940 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
2941
2942 if (that->chunks_.empty())
2943 return;
2944
2945 cover("kernel.rtlil.sigspec.convert.unpack");
2946 log_assert(that->bits_.empty());
2947
2948 that->bits_.reserve(that->width_);
2949 for (auto &c : that->chunks_)
2950 for (int i = 0; i < c.width; i++)
2951 that->bits_.push_back(RTLIL::SigBit(c, i));
2952
2953 that->chunks_.clear();
2954 that->hash_ = 0;
2955 }
2956
2957 void RTLIL::SigSpec::updhash() const
2958 {
2959 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
2960
2961 if (that->hash_ != 0)
2962 return;
2963
2964 cover("kernel.rtlil.sigspec.hash");
2965 that->pack();
2966
2967 that->hash_ = mkhash_init;
2968 for (auto &c : that->chunks_)
2969 if (c.wire == NULL) {
2970 for (auto &v : c.data)
2971 that->hash_ = mkhash(that->hash_, v);
2972 } else {
2973 that->hash_ = mkhash(that->hash_, c.wire->name.index_);
2974 that->hash_ = mkhash(that->hash_, c.offset);
2975 that->hash_ = mkhash(that->hash_, c.width);
2976 }
2977
2978 if (that->hash_ == 0)
2979 that->hash_ = 1;
2980 }
2981
2982 void RTLIL::SigSpec::sort()
2983 {
2984 unpack();
2985 cover("kernel.rtlil.sigspec.sort");
2986 std::sort(bits_.begin(), bits_.end());
2987 }
2988
2989 void RTLIL::SigSpec::sort_and_unify()
2990 {
2991 unpack();
2992 cover("kernel.rtlil.sigspec.sort_and_unify");
2993
2994 // A copy of the bits vector is used to prevent duplicating the logic from
2995 // SigSpec::SigSpec(std::vector<SigBit>). This incurrs an extra copy but
2996 // that isn't showing up as significant in profiles.
2997 std::vector<SigBit> unique_bits = bits_;
2998 std::sort(unique_bits.begin(), unique_bits.end());
2999 auto last = std::unique(unique_bits.begin(), unique_bits.end());
3000 unique_bits.erase(last, unique_bits.end());
3001
3002 *this = unique_bits;
3003 }
3004
3005 void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with)
3006 {
3007 replace(pattern, with, this);
3008 }
3009
3010 void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with, RTLIL::SigSpec *other) const
3011 {
3012 log_assert(other != NULL);
3013 log_assert(width_ == other->width_);
3014 log_assert(pattern.width_ == with.width_);
3015
3016 pattern.unpack();
3017 with.unpack();
3018 unpack();
3019 other->unpack();
3020
3021 for (int i = 0; i < GetSize(pattern.bits_); i++) {
3022 if (pattern.bits_[i].wire != NULL) {
3023 for (int j = 0; j < GetSize(bits_); j++) {
3024 if (bits_[j] == pattern.bits_[i]) {
3025 other->bits_[j] = with.bits_[i];
3026 }
3027 }
3028 }
3029 }
3030
3031 other->check();
3032 }
3033
3034 void RTLIL::SigSpec::replace(const dict<RTLIL::SigBit, RTLIL::SigBit> &rules)
3035 {
3036 replace(rules, this);
3037 }
3038
3039 void RTLIL::SigSpec::replace(const dict<RTLIL::SigBit, RTLIL::SigBit> &rules, RTLIL::SigSpec *other) const
3040 {
3041 cover("kernel.rtlil.sigspec.replace_dict");
3042
3043 log_assert(other != NULL);
3044 log_assert(width_ == other->width_);
3045
3046 unpack();
3047 other->unpack();
3048
3049 for (int i = 0; i < GetSize(bits_); i++) {
3050 auto it = rules.find(bits_[i]);
3051 if (it != rules.end())
3052 other->bits_[i] = it->second;
3053 }
3054
3055 other->check();
3056 }
3057
3058 void RTLIL::SigSpec::replace(const std::map<RTLIL::SigBit, RTLIL::SigBit> &rules)
3059 {
3060 replace(rules, this);
3061 }
3062
3063 void RTLIL::SigSpec::replace(const std::map<RTLIL::SigBit, RTLIL::SigBit> &rules, RTLIL::SigSpec *other) const
3064 {
3065 cover("kernel.rtlil.sigspec.replace_map");
3066
3067 log_assert(other != NULL);
3068 log_assert(width_ == other->width_);
3069
3070 unpack();
3071 other->unpack();
3072
3073 for (int i = 0; i < GetSize(bits_); i++) {
3074 auto it = rules.find(bits_[i]);
3075 if (it != rules.end())
3076 other->bits_[i] = it->second;
3077 }
3078
3079 other->check();
3080 }
3081
3082 void RTLIL::SigSpec::remove(const RTLIL::SigSpec &pattern)
3083 {
3084 remove2(pattern, NULL);
3085 }
3086
3087 void RTLIL::SigSpec::remove(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other) const
3088 {
3089 RTLIL::SigSpec tmp = *this;
3090 tmp.remove2(pattern, other);
3091 }
3092
3093 void RTLIL::SigSpec::remove2(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other)
3094 {
3095 if (other)
3096 cover("kernel.rtlil.sigspec.remove_other");
3097 else
3098 cover("kernel.rtlil.sigspec.remove");
3099
3100 unpack();
3101 if (other != NULL) {
3102 log_assert(width_ == other->width_);
3103 other->unpack();
3104 }
3105
3106 for (int i = GetSize(bits_) - 1; i >= 0; i--)
3107 {
3108 if (bits_[i].wire == NULL) continue;
3109
3110 for (auto &pattern_chunk : pattern.chunks())
3111 if (bits_[i].wire == pattern_chunk.wire &&
3112 bits_[i].offset >= pattern_chunk.offset &&
3113 bits_[i].offset < pattern_chunk.offset + pattern_chunk.width) {
3114 bits_.erase(bits_.begin() + i);
3115 width_--;
3116 if (other != NULL) {
3117 other->bits_.erase(other->bits_.begin() + i);
3118 other->width_--;
3119 }
3120 break;
3121 }
3122 }
3123
3124 check();
3125 }
3126
3127 void RTLIL::SigSpec::remove(const pool<RTLIL::SigBit> &pattern)
3128 {
3129 remove2(pattern, NULL);
3130 }
3131
3132 void RTLIL::SigSpec::remove(const pool<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other) const
3133 {
3134 RTLIL::SigSpec tmp = *this;
3135 tmp.remove2(pattern, other);
3136 }
3137
3138 void RTLIL::SigSpec::remove2(const pool<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other)
3139 {
3140 if (other)
3141 cover("kernel.rtlil.sigspec.remove_other");
3142 else
3143 cover("kernel.rtlil.sigspec.remove");
3144
3145 unpack();
3146
3147 if (other != NULL) {
3148 log_assert(width_ == other->width_);
3149 other->unpack();
3150 }
3151
3152 for (int i = GetSize(bits_) - 1; i >= 0; i--) {
3153 if (bits_[i].wire != NULL && pattern.count(bits_[i])) {
3154 bits_.erase(bits_.begin() + i);
3155 width_--;
3156 if (other != NULL) {
3157 other->bits_.erase(other->bits_.begin() + i);
3158 other->width_--;
3159 }
3160 }
3161 }
3162
3163 check();
3164 }
3165
3166 void RTLIL::SigSpec::remove2(const std::set<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other)
3167 {
3168 if (other)
3169 cover("kernel.rtlil.sigspec.remove_other");
3170 else
3171 cover("kernel.rtlil.sigspec.remove");
3172
3173 unpack();
3174
3175 if (other != NULL) {
3176 log_assert(width_ == other->width_);
3177 other->unpack();
3178 }
3179
3180 for (int i = GetSize(bits_) - 1; i >= 0; i--) {
3181 if (bits_[i].wire != NULL && pattern.count(bits_[i])) {
3182 bits_.erase(bits_.begin() + i);
3183 width_--;
3184 if (other != NULL) {
3185 other->bits_.erase(other->bits_.begin() + i);
3186 other->width_--;
3187 }
3188 }
3189 }
3190
3191 check();
3192 }
3193
3194 RTLIL::SigSpec RTLIL::SigSpec::extract(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec *other) const
3195 {
3196 if (other)
3197 cover("kernel.rtlil.sigspec.extract_other");
3198 else
3199 cover("kernel.rtlil.sigspec.extract");
3200
3201 log_assert(other == NULL || width_ == other->width_);
3202
3203 RTLIL::SigSpec ret;
3204 std::vector<RTLIL::SigBit> bits_match = to_sigbit_vector();
3205
3206 for (auto& pattern_chunk : pattern.chunks()) {
3207 if (other) {
3208 std::vector<RTLIL::SigBit> bits_other = other->to_sigbit_vector();
3209 for (int i = 0; i < width_; i++)
3210 if (bits_match[i].wire &&
3211 bits_match[i].wire == pattern_chunk.wire &&
3212 bits_match[i].offset >= pattern_chunk.offset &&
3213 bits_match[i].offset < pattern_chunk.offset + pattern_chunk.width)
3214 ret.append_bit(bits_other[i]);
3215 } else {
3216 for (int i = 0; i < width_; i++)
3217 if (bits_match[i].wire &&
3218 bits_match[i].wire == pattern_chunk.wire &&
3219 bits_match[i].offset >= pattern_chunk.offset &&
3220 bits_match[i].offset < pattern_chunk.offset + pattern_chunk.width)
3221 ret.append_bit(bits_match[i]);
3222 }
3223 }
3224
3225 ret.check();
3226 return ret;
3227 }
3228
3229 RTLIL::SigSpec RTLIL::SigSpec::extract(const pool<RTLIL::SigBit> &pattern, const RTLIL::SigSpec *other) const
3230 {
3231 if (other)
3232 cover("kernel.rtlil.sigspec.extract_other");
3233 else
3234 cover("kernel.rtlil.sigspec.extract");
3235
3236 log_assert(other == NULL || width_ == other->width_);
3237
3238 std::vector<RTLIL::SigBit> bits_match = to_sigbit_vector();
3239 RTLIL::SigSpec ret;
3240
3241 if (other) {
3242 std::vector<RTLIL::SigBit> bits_other = other->to_sigbit_vector();
3243 for (int i = 0; i < width_; i++)
3244 if (bits_match[i].wire && pattern.count(bits_match[i]))
3245 ret.append_bit(bits_other[i]);
3246 } else {
3247 for (int i = 0; i < width_; i++)
3248 if (bits_match[i].wire && pattern.count(bits_match[i]))
3249 ret.append_bit(bits_match[i]);
3250 }
3251
3252 ret.check();
3253 return ret;
3254 }
3255
3256 void RTLIL::SigSpec::replace(int offset, const RTLIL::SigSpec &with)
3257 {
3258 cover("kernel.rtlil.sigspec.replace_pos");
3259
3260 unpack();
3261 with.unpack();
3262
3263 log_assert(offset >= 0);
3264 log_assert(with.width_ >= 0);
3265 log_assert(offset+with.width_ <= width_);
3266
3267 for (int i = 0; i < with.width_; i++)
3268 bits_.at(offset + i) = with.bits_.at(i);
3269
3270 check();
3271 }
3272
3273 void RTLIL::SigSpec::remove_const()
3274 {
3275 if (packed())
3276 {
3277 cover("kernel.rtlil.sigspec.remove_const.packed");
3278
3279 std::vector<RTLIL::SigChunk> new_chunks;
3280 new_chunks.reserve(GetSize(chunks_));
3281
3282 width_ = 0;
3283 for (auto &chunk : chunks_)
3284 if (chunk.wire != NULL) {
3285 new_chunks.push_back(chunk);
3286 width_ += chunk.width;
3287 }
3288
3289 chunks_.swap(new_chunks);
3290 }
3291 else
3292 {
3293 cover("kernel.rtlil.sigspec.remove_const.unpacked");
3294
3295 std::vector<RTLIL::SigBit> new_bits;
3296 new_bits.reserve(width_);
3297
3298 for (auto &bit : bits_)
3299 if (bit.wire != NULL)
3300 new_bits.push_back(bit);
3301
3302 bits_.swap(new_bits);
3303 width_ = bits_.size();
3304 }
3305
3306 check();
3307 }
3308
3309 void RTLIL::SigSpec::remove(int offset, int length)
3310 {
3311 cover("kernel.rtlil.sigspec.remove_pos");
3312
3313 unpack();
3314
3315 log_assert(offset >= 0);
3316 log_assert(length >= 0);
3317 log_assert(offset + length <= width_);
3318
3319 bits_.erase(bits_.begin() + offset, bits_.begin() + offset + length);
3320 width_ = bits_.size();
3321
3322 check();
3323 }
3324
3325 RTLIL::SigSpec RTLIL::SigSpec::extract(int offset, int length) const
3326 {
3327 unpack();
3328 cover("kernel.rtlil.sigspec.extract_pos");
3329 return std::vector<RTLIL::SigBit>(bits_.begin() + offset, bits_.begin() + offset + length);
3330 }
3331
3332 void RTLIL::SigSpec::append(const RTLIL::SigSpec &signal)
3333 {
3334 if (signal.width_ == 0)
3335 return;
3336
3337 if (width_ == 0) {
3338 *this = signal;
3339 return;
3340 }
3341
3342 cover("kernel.rtlil.sigspec.append");
3343
3344 if (packed() != signal.packed()) {
3345 pack();
3346 signal.pack();
3347 }
3348
3349 if (packed())
3350 for (auto &other_c : signal.chunks_)
3351 {
3352 auto &my_last_c = chunks_.back();
3353 if (my_last_c.wire == NULL && other_c.wire == NULL) {
3354 auto &this_data = my_last_c.data;
3355 auto &other_data = other_c.data;
3356 this_data.insert(this_data.end(), other_data.begin(), other_data.end());
3357 my_last_c.width += other_c.width;
3358 } else
3359 if (my_last_c.wire == other_c.wire && my_last_c.offset + my_last_c.width == other_c.offset) {
3360 my_last_c.width += other_c.width;
3361 } else
3362 chunks_.push_back(other_c);
3363 }
3364 else
3365 bits_.insert(bits_.end(), signal.bits_.begin(), signal.bits_.end());
3366
3367 width_ += signal.width_;
3368 check();
3369 }
3370
3371 void RTLIL::SigSpec::append_bit(const RTLIL::SigBit &bit)
3372 {
3373 if (packed())
3374 {
3375 cover("kernel.rtlil.sigspec.append_bit.packed");
3376
3377 if (chunks_.size() == 0)
3378 chunks_.push_back(bit);
3379 else
3380 if (bit.wire == NULL)
3381 if (chunks_.back().wire == NULL) {
3382 chunks_.back().data.push_back(bit.data);
3383 chunks_.back().width++;
3384 } else
3385 chunks_.push_back(bit);
3386 else
3387 if (chunks_.back().wire == bit.wire && chunks_.back().offset + chunks_.back().width == bit.offset)
3388 chunks_.back().width++;
3389 else
3390 chunks_.push_back(bit);
3391 }
3392 else
3393 {
3394 cover("kernel.rtlil.sigspec.append_bit.unpacked");
3395 bits_.push_back(bit);
3396 }
3397
3398 width_++;
3399 check();
3400 }
3401
3402 void RTLIL::SigSpec::extend_u0(int width, bool is_signed)
3403 {
3404 cover("kernel.rtlil.sigspec.extend_u0");
3405
3406 pack();
3407
3408 if (width_ > width)
3409 remove(width, width_ - width);
3410
3411 if (width_ < width) {
3412 RTLIL::SigBit padding = width_ > 0 ? (*this)[width_ - 1] : RTLIL::State::Sx;
3413 if (!is_signed)
3414 padding = RTLIL::State::S0;
3415 while (width_ < width)
3416 append(padding);
3417 }
3418
3419 }
3420
3421 RTLIL::SigSpec RTLIL::SigSpec::repeat(int num) const
3422 {
3423 cover("kernel.rtlil.sigspec.repeat");
3424
3425 RTLIL::SigSpec sig;
3426 for (int i = 0; i < num; i++)
3427 sig.append(*this);
3428 return sig;
3429 }
3430
3431 #ifndef NDEBUG
3432 void RTLIL::SigSpec::check() const
3433 {
3434 if (width_ > 64)
3435 {
3436 cover("kernel.rtlil.sigspec.check.skip");
3437 }
3438 else if (packed())
3439 {
3440 cover("kernel.rtlil.sigspec.check.packed");
3441
3442 int w = 0;
3443 for (size_t i = 0; i < chunks_.size(); i++) {
3444 const RTLIL::SigChunk chunk = chunks_[i];
3445 if (chunk.wire == NULL) {
3446 if (i > 0)
3447 log_assert(chunks_[i-1].wire != NULL);
3448 log_assert(chunk.offset == 0);
3449 log_assert(chunk.data.size() == (size_t)chunk.width);
3450 } else {
3451 if (i > 0 && chunks_[i-1].wire == chunk.wire)
3452 log_assert(chunk.offset != chunks_[i-1].offset + chunks_[i-1].width);
3453 log_assert(chunk.offset >= 0);
3454 log_assert(chunk.width >= 0);
3455 log_assert(chunk.offset + chunk.width <= chunk.wire->width);
3456 log_assert(chunk.data.size() == 0);
3457 }
3458 w += chunk.width;
3459 }
3460 log_assert(w == width_);
3461 log_assert(bits_.empty());
3462 }
3463 else
3464 {
3465 cover("kernel.rtlil.sigspec.check.unpacked");
3466
3467 log_assert(width_ == GetSize(bits_));
3468 log_assert(chunks_.empty());
3469 }
3470 }
3471 #endif
3472
3473 bool RTLIL::SigSpec::operator <(const RTLIL::SigSpec &other) const
3474 {
3475 cover("kernel.rtlil.sigspec.comp_lt");
3476
3477 if (this == &other)
3478 return false;
3479
3480 if (width_ != other.width_)
3481 return width_ < other.width_;
3482
3483 pack();
3484 other.pack();
3485
3486 if (chunks_.size() != other.chunks_.size())
3487 return chunks_.size() < other.chunks_.size();
3488
3489 updhash();
3490 other.updhash();
3491
3492 if (hash_ != other.hash_)
3493 return hash_ < other.hash_;
3494
3495 for (size_t i = 0; i < chunks_.size(); i++)
3496 if (chunks_[i] != other.chunks_[i]) {
3497 cover("kernel.rtlil.sigspec.comp_lt.hash_collision");
3498 return chunks_[i] < other.chunks_[i];
3499 }
3500
3501 cover("kernel.rtlil.sigspec.comp_lt.equal");
3502 return false;
3503 }
3504
3505 bool RTLIL::SigSpec::operator ==(const RTLIL::SigSpec &other) const
3506 {
3507 cover("kernel.rtlil.sigspec.comp_eq");
3508
3509 if (this == &other)
3510 return true;
3511
3512 if (width_ != other.width_)
3513 return false;
3514
3515 pack();
3516 other.pack();
3517
3518 if (chunks_.size() != other.chunks_.size())
3519 return false;
3520
3521 updhash();
3522 other.updhash();
3523
3524 if (hash_ != other.hash_)
3525 return false;
3526
3527 for (size_t i = 0; i < chunks_.size(); i++)
3528 if (chunks_[i] != other.chunks_[i]) {
3529 cover("kernel.rtlil.sigspec.comp_eq.hash_collision");
3530 return false;
3531 }
3532
3533 cover("kernel.rtlil.sigspec.comp_eq.equal");
3534 return true;
3535 }
3536
3537 bool RTLIL::SigSpec::is_wire() const
3538 {
3539 cover("kernel.rtlil.sigspec.is_wire");
3540
3541 pack();
3542 return GetSize(chunks_) == 1 && chunks_[0].wire && chunks_[0].wire->width == width_;
3543 }
3544
3545 bool RTLIL::SigSpec::is_chunk() const
3546 {
3547 cover("kernel.rtlil.sigspec.is_chunk");
3548
3549 pack();
3550 return GetSize(chunks_) == 1;
3551 }
3552
3553 bool RTLIL::SigSpec::is_fully_const() const
3554 {
3555 cover("kernel.rtlil.sigspec.is_fully_const");
3556
3557 pack();
3558 for (auto it = chunks_.begin(); it != chunks_.end(); it++)
3559 if (it->width > 0 && it->wire != NULL)
3560 return false;
3561 return true;
3562 }
3563
3564 bool RTLIL::SigSpec::is_fully_zero() const
3565 {
3566 cover("kernel.rtlil.sigspec.is_fully_zero");
3567
3568 pack();
3569 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
3570 if (it->width > 0 && it->wire != NULL)
3571 return false;
3572 for (size_t i = 0; i < it->data.size(); i++)
3573 if (it->data[i] != RTLIL::State::S0)
3574 return false;
3575 }
3576 return true;
3577 }
3578
3579 bool RTLIL::SigSpec::is_fully_ones() const
3580 {
3581 cover("kernel.rtlil.sigspec.is_fully_ones");
3582
3583 pack();
3584 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
3585 if (it->width > 0 && it->wire != NULL)
3586 return false;
3587 for (size_t i = 0; i < it->data.size(); i++)
3588 if (it->data[i] != RTLIL::State::S1)
3589 return false;
3590 }
3591 return true;
3592 }
3593
3594 bool RTLIL::SigSpec::is_fully_def() const
3595 {
3596 cover("kernel.rtlil.sigspec.is_fully_def");
3597
3598 pack();
3599 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
3600 if (it->width > 0 && it->wire != NULL)
3601 return false;
3602 for (size_t i = 0; i < it->data.size(); i++)
3603 if (it->data[i] != RTLIL::State::S0 && it->data[i] != RTLIL::State::S1)
3604 return false;
3605 }
3606 return true;
3607 }
3608
3609 bool RTLIL::SigSpec::is_fully_undef() const
3610 {
3611 cover("kernel.rtlil.sigspec.is_fully_undef");
3612
3613 pack();
3614 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
3615 if (it->width > 0 && it->wire != NULL)
3616 return false;
3617 for (size_t i = 0; i < it->data.size(); i++)
3618 if (it->data[i] != RTLIL::State::Sx && it->data[i] != RTLIL::State::Sz)
3619 return false;
3620 }
3621 return true;
3622 }
3623
3624 bool RTLIL::SigSpec::has_const() const
3625 {
3626 cover("kernel.rtlil.sigspec.has_const");
3627
3628 pack();
3629 for (auto it = chunks_.begin(); it != chunks_.end(); it++)
3630 if (it->width > 0 && it->wire == NULL)
3631 return true;
3632 return false;
3633 }
3634
3635 bool RTLIL::SigSpec::has_marked_bits() const
3636 {
3637 cover("kernel.rtlil.sigspec.has_marked_bits");
3638
3639 pack();
3640 for (auto it = chunks_.begin(); it != chunks_.end(); it++)
3641 if (it->width > 0 && it->wire == NULL) {
3642 for (size_t i = 0; i < it->data.size(); i++)
3643 if (it->data[i] == RTLIL::State::Sm)
3644 return true;
3645 }
3646 return false;
3647 }
3648
3649 bool RTLIL::SigSpec::as_bool() const
3650 {
3651 cover("kernel.rtlil.sigspec.as_bool");
3652
3653 pack();
3654 log_assert(is_fully_const() && GetSize(chunks_) <= 1);
3655 if (width_)
3656 return RTLIL::Const(chunks_[0].data).as_bool();
3657 return false;
3658 }
3659
3660 int RTLIL::SigSpec::as_int(bool is_signed) const
3661 {
3662 cover("kernel.rtlil.sigspec.as_int");
3663
3664 pack();
3665 log_assert(is_fully_const() && GetSize(chunks_) <= 1);
3666 if (width_)
3667 return RTLIL::Const(chunks_[0].data).as_int(is_signed);
3668 return 0;
3669 }
3670
3671 std::string RTLIL::SigSpec::as_string() const
3672 {
3673 cover("kernel.rtlil.sigspec.as_string");
3674
3675 pack();
3676 std::string str;
3677 for (size_t i = chunks_.size(); i > 0; i--) {
3678 const RTLIL::SigChunk &chunk = chunks_[i-1];
3679 if (chunk.wire != NULL)
3680 for (int j = 0; j < chunk.width; j++)
3681 str += "?";
3682 else
3683 str += RTLIL::Const(chunk.data).as_string();
3684 }
3685 return str;
3686 }
3687
3688 RTLIL::Const RTLIL::SigSpec::as_const() const
3689 {
3690 cover("kernel.rtlil.sigspec.as_const");
3691
3692 pack();
3693 log_assert(is_fully_const() && GetSize(chunks_) <= 1);
3694 if (width_)
3695 return chunks_[0].data;
3696 return RTLIL::Const();
3697 }
3698
3699 RTLIL::Wire *RTLIL::SigSpec::as_wire() const
3700 {
3701 cover("kernel.rtlil.sigspec.as_wire");
3702
3703 pack();
3704 log_assert(is_wire());
3705 return chunks_[0].wire;
3706 }
3707
3708 RTLIL::SigChunk RTLIL::SigSpec::as_chunk() const
3709 {
3710 cover("kernel.rtlil.sigspec.as_chunk");
3711
3712 pack();
3713 log_assert(is_chunk());
3714 return chunks_[0];
3715 }
3716
3717 RTLIL::SigBit RTLIL::SigSpec::as_bit() const
3718 {
3719 cover("kernel.rtlil.sigspec.as_bit");
3720
3721 log_assert(width_ == 1);
3722 if (packed())
3723 return RTLIL::SigBit(*chunks_.begin());
3724 else
3725 return bits_[0];
3726 }
3727
3728 bool RTLIL::SigSpec::match(std::string pattern) const
3729 {
3730 cover("kernel.rtlil.sigspec.match");
3731
3732 pack();
3733 std::string str = as_string();
3734 log_assert(pattern.size() == str.size());
3735
3736 for (size_t i = 0; i < pattern.size(); i++) {
3737 if (pattern[i] == ' ')
3738 continue;
3739 if (pattern[i] == '*') {
3740 if (str[i] != 'z' && str[i] != 'x')
3741 return false;
3742 continue;
3743 }
3744 if (pattern[i] != str[i])
3745 return false;
3746 }
3747
3748 return true;
3749 }
3750
3751 std::set<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_set() const
3752 {
3753 cover("kernel.rtlil.sigspec.to_sigbit_set");
3754
3755 pack();
3756 std::set<RTLIL::SigBit> sigbits;
3757 for (auto &c : chunks_)
3758 for (int i = 0; i < c.width; i++)
3759 sigbits.insert(RTLIL::SigBit(c, i));
3760 return sigbits;
3761 }
3762
3763 pool<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_pool() const
3764 {
3765 cover("kernel.rtlil.sigspec.to_sigbit_pool");
3766
3767 pack();
3768 pool<RTLIL::SigBit> sigbits;
3769 for (auto &c : chunks_)
3770 for (int i = 0; i < c.width; i++)
3771 sigbits.insert(RTLIL::SigBit(c, i));
3772 return sigbits;
3773 }
3774
3775 std::vector<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_vector() const
3776 {
3777 cover("kernel.rtlil.sigspec.to_sigbit_vector");
3778
3779 unpack();
3780 return bits_;
3781 }
3782
3783 std::map<RTLIL::SigBit, RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_map(const RTLIL::SigSpec &other) const
3784 {
3785 cover("kernel.rtlil.sigspec.to_sigbit_map");
3786
3787 unpack();
3788 other.unpack();
3789
3790 log_assert(width_ == other.width_);
3791
3792 std::map<RTLIL::SigBit, RTLIL::SigBit> new_map;
3793 for (int i = 0; i < width_; i++)
3794 new_map[bits_[i]] = other.bits_[i];
3795
3796 return new_map;
3797 }
3798
3799 dict<RTLIL::SigBit, RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_dict(const RTLIL::SigSpec &other) const
3800 {
3801 cover("kernel.rtlil.sigspec.to_sigbit_dict");
3802
3803 unpack();
3804 other.unpack();
3805
3806 log_assert(width_ == other.width_);
3807
3808 dict<RTLIL::SigBit, RTLIL::SigBit> new_map;
3809 for (int i = 0; i < width_; i++)
3810 new_map[bits_[i]] = other.bits_[i];
3811
3812 return new_map;
3813 }
3814
3815 static void sigspec_parse_split(std::vector<std::string> &tokens, const std::string &text, char sep)
3816 {
3817 size_t start = 0, end = 0;
3818 while ((end = text.find(sep, start)) != std::string::npos) {
3819 tokens.push_back(text.substr(start, end - start));
3820 start = end + 1;
3821 }
3822 tokens.push_back(text.substr(start));
3823 }
3824
3825 static int sigspec_parse_get_dummy_line_num()
3826 {
3827 return 0;
3828 }
3829
3830 bool RTLIL::SigSpec::parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str)
3831 {
3832 cover("kernel.rtlil.sigspec.parse");
3833
3834 AST::current_filename = "input";
3835 AST::use_internal_line_num();
3836 AST::set_line_num(0);
3837
3838 std::vector<std::string> tokens;
3839 sigspec_parse_split(tokens, str, ',');
3840
3841 sig = RTLIL::SigSpec();
3842 for (int tokidx = int(tokens.size())-1; tokidx >= 0; tokidx--)
3843 {
3844 std::string netname = tokens[tokidx];
3845 std::string indices;
3846
3847 if (netname.size() == 0)
3848 continue;
3849
3850 if (('0' <= netname[0] && netname[0] <= '9') || netname[0] == '\'') {
3851 cover("kernel.rtlil.sigspec.parse.const");
3852 AST::get_line_num = sigspec_parse_get_dummy_line_num;
3853 AST::AstNode *ast = VERILOG_FRONTEND::const2ast(netname);
3854 if (ast == NULL)
3855 return false;
3856 sig.append(RTLIL::Const(ast->bits));
3857 delete ast;
3858 continue;
3859 }
3860
3861 if (module == NULL)
3862 return false;
3863
3864 cover("kernel.rtlil.sigspec.parse.net");
3865
3866 if (netname[0] != '$' && netname[0] != '\\')
3867 netname = "\\" + netname;
3868
3869 if (module->wires_.count(netname) == 0) {
3870 size_t indices_pos = netname.size()-1;
3871 if (indices_pos > 2 && netname[indices_pos] == ']')
3872 {
3873 indices_pos--;
3874 while (indices_pos > 0 && ('0' <= netname[indices_pos] && netname[indices_pos] <= '9')) indices_pos--;
3875 if (indices_pos > 0 && netname[indices_pos] == ':') {
3876 indices_pos--;
3877 while (indices_pos > 0 && ('0' <= netname[indices_pos] && netname[indices_pos] <= '9')) indices_pos--;
3878 }
3879 if (indices_pos > 0 && netname[indices_pos] == '[') {
3880 indices = netname.substr(indices_pos);
3881 netname = netname.substr(0, indices_pos);
3882 }
3883 }
3884 }
3885
3886 if (module->wires_.count(netname) == 0)
3887 return false;
3888
3889 RTLIL::Wire *wire = module->wires_.at(netname);
3890 if (!indices.empty()) {
3891 std::vector<std::string> index_tokens;
3892 sigspec_parse_split(index_tokens, indices.substr(1, indices.size()-2), ':');
3893 if (index_tokens.size() == 1) {
3894 cover("kernel.rtlil.sigspec.parse.bit_sel");
3895 int a = atoi(index_tokens.at(0).c_str());
3896 if (a < 0 || a >= wire->width)
3897 return false;
3898 sig.append(RTLIL::SigSpec(wire, a));
3899 } else {
3900 cover("kernel.rtlil.sigspec.parse.part_sel");
3901 int a = atoi(index_tokens.at(0).c_str());
3902 int b = atoi(index_tokens.at(1).c_str());
3903 if (a > b) {
3904 int tmp = a;
3905 a = b, b = tmp;
3906 }
3907 if (a < 0 || a >= wire->width)
3908 return false;
3909 if (b < 0 || b >= wire->width)
3910 return false;
3911 sig.append(RTLIL::SigSpec(wire, a, b-a+1));
3912 }
3913 } else
3914 sig.append(wire);
3915 }
3916
3917 return true;
3918 }
3919
3920 bool RTLIL::SigSpec::parse_sel(RTLIL::SigSpec &sig, RTLIL::Design *design, RTLIL::Module *module, std::string str)
3921 {
3922 if (str.empty() || str[0] != '@')
3923 return parse(sig, module, str);
3924
3925 cover("kernel.rtlil.sigspec.parse.sel");
3926
3927 str = RTLIL::escape_id(str.substr(1));
3928 if (design->selection_vars.count(str) == 0)
3929 return false;
3930
3931 sig = RTLIL::SigSpec();
3932 RTLIL::Selection &sel = design->selection_vars.at(str);
3933 for (auto &it : module->wires_)
3934 if (sel.selected_member(module->name, it.first))
3935 sig.append(it.second);
3936
3937 return true;
3938 }
3939
3940 bool RTLIL::SigSpec::parse_rhs(const RTLIL::SigSpec &lhs, RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str)
3941 {
3942 if (str == "0") {
3943 cover("kernel.rtlil.sigspec.parse.rhs_zeros");
3944 sig = RTLIL::SigSpec(RTLIL::State::S0, lhs.width_);
3945 return true;
3946 }
3947
3948 if (str == "~0") {
3949 cover("kernel.rtlil.sigspec.parse.rhs_ones");
3950 sig = RTLIL::SigSpec(RTLIL::State::S1, lhs.width_);
3951 return true;
3952 }
3953
3954 if (lhs.chunks_.size() == 1) {
3955 char *p = (char*)str.c_str(), *endptr;
3956 long int val = strtol(p, &endptr, 10);
3957 if (endptr && endptr != p && *endptr == 0) {
3958 sig = RTLIL::SigSpec(val, lhs.width_);
3959 cover("kernel.rtlil.sigspec.parse.rhs_dec");
3960 return true;
3961 }
3962 }
3963
3964 return parse(sig, module, str);
3965 }
3966
3967 RTLIL::CaseRule::~CaseRule()
3968 {
3969 for (auto it = switches.begin(); it != switches.end(); it++)
3970 delete *it;
3971 }
3972
3973 bool RTLIL::CaseRule::empty() const
3974 {
3975 return actions.empty() && switches.empty();
3976 }
3977
3978 RTLIL::CaseRule *RTLIL::CaseRule::clone() const
3979 {
3980 RTLIL::CaseRule *new_caserule = new RTLIL::CaseRule;
3981 new_caserule->compare = compare;
3982 new_caserule->actions = actions;
3983 for (auto &it : switches)
3984 new_caserule->switches.push_back(it->clone());
3985 return new_caserule;
3986 }
3987
3988 RTLIL::SwitchRule::~SwitchRule()
3989 {
3990 for (auto it = cases.begin(); it != cases.end(); it++)
3991 delete *it;
3992 }
3993
3994 bool RTLIL::SwitchRule::empty() const
3995 {
3996 return cases.empty();
3997 }
3998
3999 RTLIL::SwitchRule *RTLIL::SwitchRule::clone() const
4000 {
4001 RTLIL::SwitchRule *new_switchrule = new RTLIL::SwitchRule;
4002 new_switchrule->signal = signal;
4003 new_switchrule->attributes = attributes;
4004 for (auto &it : cases)
4005 new_switchrule->cases.push_back(it->clone());
4006 return new_switchrule;
4007
4008 }
4009
4010 RTLIL::SyncRule *RTLIL::SyncRule::clone() const
4011 {
4012 RTLIL::SyncRule *new_syncrule = new RTLIL::SyncRule;
4013 new_syncrule->type = type;
4014 new_syncrule->signal = signal;
4015 new_syncrule->actions = actions;
4016 return new_syncrule;
4017 }
4018
4019 RTLIL::Process::~Process()
4020 {
4021 for (auto it = syncs.begin(); it != syncs.end(); it++)
4022 delete *it;
4023 }
4024
4025 RTLIL::Process *RTLIL::Process::clone() const
4026 {
4027 RTLIL::Process *new_proc = new RTLIL::Process;
4028
4029 new_proc->name = name;
4030 new_proc->attributes = attributes;
4031
4032 RTLIL::CaseRule *rc_ptr = root_case.clone();
4033 new_proc->root_case = *rc_ptr;
4034 rc_ptr->switches.clear();
4035 delete rc_ptr;
4036
4037 for (auto &it : syncs)
4038 new_proc->syncs.push_back(it->clone());
4039
4040 return new_proc;
4041 }
4042
4043 #ifdef WITH_PYTHON
4044 RTLIL::Memory::~Memory()
4045 {
4046 RTLIL::Memory::get_all_memorys()->erase(hashidx_);
4047 }
4048 static std::map<unsigned int, RTLIL::Memory*> all_memorys;
4049 std::map<unsigned int, RTLIL::Memory*> *RTLIL::Memory::get_all_memorys(void)
4050 {
4051 return &all_memorys;
4052 }
4053 #endif
4054 YOSYS_NAMESPACE_END