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Merge remote-tracking branch 'origin/clifford/fix1132' into xc7mux
[yosys.git] / kernel / rtlil.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 #include "kernel/yosys.h"
21 #include "kernel/macc.h"
22 #include "kernel/celltypes.h"
23 #include "frontends/verilog/verilog_frontend.h"
24 #include "backends/ilang/ilang_backend.h"
25
26 #include <string.h>
27 #include <algorithm>
28
29 YOSYS_NAMESPACE_BEGIN
30
31 RTLIL::IdString::destruct_guard_t RTLIL::IdString::destruct_guard;
32 std::vector<int> RTLIL::IdString::global_refcount_storage_;
33 std::vector<char*> RTLIL::IdString::global_id_storage_;
34 dict<char*, int, hash_cstr_ops> RTLIL::IdString::global_id_index_;
35 std::vector<int> RTLIL::IdString::global_free_idx_list_;
36 int RTLIL::IdString::last_created_idx_[8];
37 int RTLIL::IdString::last_created_idx_ptr_;
38
39 RTLIL::Const::Const()
40 {
41 flags = RTLIL::CONST_FLAG_NONE;
42 }
43
44 RTLIL::Const::Const(std::string str)
45 {
46 flags = RTLIL::CONST_FLAG_STRING;
47 for (int i = str.size()-1; i >= 0; i--) {
48 unsigned char ch = str[i];
49 for (int j = 0; j < 8; j++) {
50 bits.push_back((ch & 1) != 0 ? RTLIL::S1 : RTLIL::S0);
51 ch = ch >> 1;
52 }
53 }
54 }
55
56 RTLIL::Const::Const(int val, int width)
57 {
58 flags = RTLIL::CONST_FLAG_NONE;
59 for (int i = 0; i < width; i++) {
60 bits.push_back((val & 1) != 0 ? RTLIL::S1 : RTLIL::S0);
61 val = val >> 1;
62 }
63 }
64
65 RTLIL::Const::Const(RTLIL::State bit, int width)
66 {
67 flags = RTLIL::CONST_FLAG_NONE;
68 for (int i = 0; i < width; i++)
69 bits.push_back(bit);
70 }
71
72 RTLIL::Const::Const(const std::vector<bool> &bits)
73 {
74 flags = RTLIL::CONST_FLAG_NONE;
75 for (auto b : bits)
76 this->bits.push_back(b ? RTLIL::S1 : RTLIL::S0);
77 }
78
79 RTLIL::Const::Const(const RTLIL::Const &c)
80 {
81 flags = c.flags;
82 for (auto b : c.bits)
83 this->bits.push_back(b);
84 }
85
86 bool RTLIL::Const::operator <(const RTLIL::Const &other) const
87 {
88 if (bits.size() != other.bits.size())
89 return bits.size() < other.bits.size();
90 for (size_t i = 0; i < bits.size(); i++)
91 if (bits[i] != other.bits[i])
92 return bits[i] < other.bits[i];
93 return false;
94 }
95
96 bool RTLIL::Const::operator ==(const RTLIL::Const &other) const
97 {
98 return bits == other.bits;
99 }
100
101 bool RTLIL::Const::operator !=(const RTLIL::Const &other) const
102 {
103 return bits != other.bits;
104 }
105
106 bool RTLIL::Const::as_bool() const
107 {
108 for (size_t i = 0; i < bits.size(); i++)
109 if (bits[i] == RTLIL::S1)
110 return true;
111 return false;
112 }
113
114 int RTLIL::Const::as_int(bool is_signed) const
115 {
116 int32_t ret = 0;
117 for (size_t i = 0; i < bits.size() && i < 32; i++)
118 if (bits[i] == RTLIL::S1)
119 ret |= 1 << i;
120 if (is_signed && bits.back() == RTLIL::S1)
121 for (size_t i = bits.size(); i < 32; i++)
122 ret |= 1 << i;
123 return ret;
124 }
125
126 std::string RTLIL::Const::as_string() const
127 {
128 std::string ret;
129 for (size_t i = bits.size(); i > 0; i--)
130 switch (bits[i-1]) {
131 case S0: ret += "0"; break;
132 case S1: ret += "1"; break;
133 case Sx: ret += "x"; break;
134 case Sz: ret += "z"; break;
135 case Sa: ret += "-"; break;
136 case Sm: ret += "m"; break;
137 }
138 return ret;
139 }
140
141 RTLIL::Const RTLIL::Const::from_string(std::string str)
142 {
143 Const c;
144 for (auto it = str.rbegin(); it != str.rend(); it++)
145 switch (*it) {
146 case '0': c.bits.push_back(State::S0); break;
147 case '1': c.bits.push_back(State::S1); break;
148 case 'x': c.bits.push_back(State::Sx); break;
149 case 'z': c.bits.push_back(State::Sz); break;
150 case 'm': c.bits.push_back(State::Sm); break;
151 default: c.bits.push_back(State::Sa);
152 }
153 return c;
154 }
155
156 std::string RTLIL::Const::decode_string() const
157 {
158 std::string string;
159 std::vector<char> string_chars;
160 for (int i = 0; i < int (bits.size()); i += 8) {
161 char ch = 0;
162 for (int j = 0; j < 8 && i + j < int (bits.size()); j++)
163 if (bits[i + j] == RTLIL::State::S1)
164 ch |= 1 << j;
165 if (ch != 0)
166 string_chars.push_back(ch);
167 }
168 for (int i = int (string_chars.size()) - 1; i >= 0; i--)
169 string += string_chars[i];
170 return string;
171 }
172
173 bool RTLIL::Const::is_fully_zero() const
174 {
175 cover("kernel.rtlil.const.is_fully_zero");
176
177 for (auto bit : bits)
178 if (bit != RTLIL::State::S0)
179 return false;
180
181 return true;
182 }
183
184 bool RTLIL::Const::is_fully_ones() const
185 {
186 cover("kernel.rtlil.const.is_fully_ones");
187
188 for (auto bit : bits)
189 if (bit != RTLIL::State::S1)
190 return false;
191
192 return true;
193 }
194
195 bool RTLIL::Const::is_fully_def() const
196 {
197 cover("kernel.rtlil.const.is_fully_def");
198
199 for (auto bit : bits)
200 if (bit != RTLIL::State::S0 && bit != RTLIL::State::S1)
201 return false;
202
203 return true;
204 }
205
206 bool RTLIL::Const::is_fully_undef() const
207 {
208 cover("kernel.rtlil.const.is_fully_undef");
209
210 for (auto bit : bits)
211 if (bit != RTLIL::State::Sx && bit != RTLIL::State::Sz)
212 return false;
213
214 return true;
215 }
216
217 void RTLIL::AttrObject::set_bool_attribute(RTLIL::IdString id, bool value)
218 {
219 if (value)
220 attributes[id] = RTLIL::Const(1);
221 else {
222 const auto it = attributes.find(id);
223 if (it != attributes.end())
224 attributes.erase(it);
225 }
226 }
227
228 bool RTLIL::AttrObject::get_bool_attribute(RTLIL::IdString id) const
229 {
230 const auto it = attributes.find(id);
231 if (it == attributes.end())
232 return false;
233 return it->second.as_bool();
234 }
235
236 void RTLIL::AttrObject::set_strpool_attribute(RTLIL::IdString id, const pool<string> &data)
237 {
238 string attrval;
239 for (auto &s : data) {
240 if (!attrval.empty())
241 attrval += "|";
242 attrval += s;
243 }
244 attributes[id] = RTLIL::Const(attrval);
245 }
246
247 void RTLIL::AttrObject::add_strpool_attribute(RTLIL::IdString id, const pool<string> &data)
248 {
249 pool<string> union_data = get_strpool_attribute(id);
250 union_data.insert(data.begin(), data.end());
251 if (!union_data.empty())
252 set_strpool_attribute(id, union_data);
253 }
254
255 pool<string> RTLIL::AttrObject::get_strpool_attribute(RTLIL::IdString id) const
256 {
257 pool<string> data;
258 if (attributes.count(id) != 0)
259 for (auto s : split_tokens(attributes.at(id).decode_string(), "|"))
260 data.insert(s);
261 return data;
262 }
263
264 void RTLIL::AttrObject::set_src_attribute(const std::string &src)
265 {
266 if (src.empty())
267 attributes.erase("\\src");
268 else
269 attributes["\\src"] = src;
270 }
271
272 std::string RTLIL::AttrObject::get_src_attribute() const
273 {
274 std::string src;
275 if (attributes.count("\\src"))
276 src = attributes.at("\\src").decode_string();
277 return src;
278 }
279
280 bool RTLIL::Selection::selected_module(RTLIL::IdString mod_name) const
281 {
282 if (full_selection)
283 return true;
284 if (selected_modules.count(mod_name) > 0)
285 return true;
286 if (selected_members.count(mod_name) > 0)
287 return true;
288 return false;
289 }
290
291 bool RTLIL::Selection::selected_whole_module(RTLIL::IdString mod_name) const
292 {
293 if (full_selection)
294 return true;
295 if (selected_modules.count(mod_name) > 0)
296 return true;
297 return false;
298 }
299
300 bool RTLIL::Selection::selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const
301 {
302 if (full_selection)
303 return true;
304 if (selected_modules.count(mod_name) > 0)
305 return true;
306 if (selected_members.count(mod_name) > 0)
307 if (selected_members.at(mod_name).count(memb_name) > 0)
308 return true;
309 return false;
310 }
311
312 void RTLIL::Selection::optimize(RTLIL::Design *design)
313 {
314 if (full_selection) {
315 selected_modules.clear();
316 selected_members.clear();
317 return;
318 }
319
320 std::vector<RTLIL::IdString> del_list, add_list;
321
322 del_list.clear();
323 for (auto mod_name : selected_modules) {
324 if (design->modules_.count(mod_name) == 0)
325 del_list.push_back(mod_name);
326 selected_members.erase(mod_name);
327 }
328 for (auto mod_name : del_list)
329 selected_modules.erase(mod_name);
330
331 del_list.clear();
332 for (auto &it : selected_members)
333 if (design->modules_.count(it.first) == 0)
334 del_list.push_back(it.first);
335 for (auto mod_name : del_list)
336 selected_members.erase(mod_name);
337
338 for (auto &it : selected_members) {
339 del_list.clear();
340 for (auto memb_name : it.second)
341 if (design->modules_[it.first]->count_id(memb_name) == 0)
342 del_list.push_back(memb_name);
343 for (auto memb_name : del_list)
344 it.second.erase(memb_name);
345 }
346
347 del_list.clear();
348 add_list.clear();
349 for (auto &it : selected_members)
350 if (it.second.size() == 0)
351 del_list.push_back(it.first);
352 else if (it.second.size() == design->modules_[it.first]->wires_.size() + design->modules_[it.first]->memories.size() +
353 design->modules_[it.first]->cells_.size() + design->modules_[it.first]->processes.size())
354 add_list.push_back(it.first);
355 for (auto mod_name : del_list)
356 selected_members.erase(mod_name);
357 for (auto mod_name : add_list) {
358 selected_members.erase(mod_name);
359 selected_modules.insert(mod_name);
360 }
361
362 if (selected_modules.size() == design->modules_.size()) {
363 full_selection = true;
364 selected_modules.clear();
365 selected_members.clear();
366 }
367 }
368
369 RTLIL::Design::Design()
370 {
371 static unsigned int hashidx_count = 123456789;
372 hashidx_count = mkhash_xorshift(hashidx_count);
373 hashidx_ = hashidx_count;
374
375 refcount_modules_ = 0;
376 selection_stack.push_back(RTLIL::Selection());
377
378 #ifdef WITH_PYTHON
379 RTLIL::Design::get_all_designs()->insert(std::pair<unsigned int, RTLIL::Design*>(hashidx_, this));
380 #endif
381 }
382
383 RTLIL::Design::~Design()
384 {
385 for (auto it = modules_.begin(); it != modules_.end(); ++it)
386 delete it->second;
387 for (auto n : verilog_packages)
388 delete n;
389 for (auto n : verilog_globals)
390 delete n;
391 #ifdef WITH_PYTHON
392 RTLIL::Design::get_all_designs()->erase(hashidx_);
393 #endif
394 }
395
396 #ifdef WITH_PYTHON
397 static std::map<unsigned int, RTLIL::Design*> all_designs;
398 std::map<unsigned int, RTLIL::Design*> *RTLIL::Design::get_all_designs(void)
399 {
400 return &all_designs;
401 }
402 #endif
403
404 RTLIL::ObjRange<RTLIL::Module*> RTLIL::Design::modules()
405 {
406 return RTLIL::ObjRange<RTLIL::Module*>(&modules_, &refcount_modules_);
407 }
408
409 RTLIL::Module *RTLIL::Design::module(RTLIL::IdString name)
410 {
411 return modules_.count(name) ? modules_.at(name) : NULL;
412 }
413
414 RTLIL::Module *RTLIL::Design::top_module()
415 {
416 RTLIL::Module *module = nullptr;
417 int module_count = 0;
418
419 for (auto mod : selected_modules()) {
420 if (mod->get_bool_attribute("\\top"))
421 return mod;
422 module_count++;
423 module = mod;
424 }
425
426 return module_count == 1 ? module : nullptr;
427 }
428
429 void RTLIL::Design::add(RTLIL::Module *module)
430 {
431 log_assert(modules_.count(module->name) == 0);
432 log_assert(refcount_modules_ == 0);
433 modules_[module->name] = module;
434 module->design = this;
435
436 for (auto mon : monitors)
437 mon->notify_module_add(module);
438
439 if (yosys_xtrace) {
440 log("#X# New Module: %s\n", log_id(module));
441 log_backtrace("-X- ", yosys_xtrace-1);
442 }
443 }
444
445 RTLIL::Module *RTLIL::Design::addModule(RTLIL::IdString name)
446 {
447 log_assert(modules_.count(name) == 0);
448 log_assert(refcount_modules_ == 0);
449
450 RTLIL::Module *module = new RTLIL::Module;
451 modules_[name] = module;
452 module->design = this;
453 module->name = name;
454
455 for (auto mon : monitors)
456 mon->notify_module_add(module);
457
458 if (yosys_xtrace) {
459 log("#X# New Module: %s\n", log_id(module));
460 log_backtrace("-X- ", yosys_xtrace-1);
461 }
462
463 return module;
464 }
465
466 void RTLIL::Design::scratchpad_unset(std::string varname)
467 {
468 scratchpad.erase(varname);
469 }
470
471 void RTLIL::Design::scratchpad_set_int(std::string varname, int value)
472 {
473 scratchpad[varname] = stringf("%d", value);
474 }
475
476 void RTLIL::Design::scratchpad_set_bool(std::string varname, bool value)
477 {
478 scratchpad[varname] = value ? "true" : "false";
479 }
480
481 void RTLIL::Design::scratchpad_set_string(std::string varname, std::string value)
482 {
483 scratchpad[varname] = value;
484 }
485
486 int RTLIL::Design::scratchpad_get_int(std::string varname, int default_value) const
487 {
488 if (scratchpad.count(varname) == 0)
489 return default_value;
490
491 std::string str = scratchpad.at(varname);
492
493 if (str == "0" || str == "false")
494 return 0;
495
496 if (str == "1" || str == "true")
497 return 1;
498
499 char *endptr = nullptr;
500 long int parsed_value = strtol(str.c_str(), &endptr, 10);
501 return *endptr ? default_value : parsed_value;
502 }
503
504 bool RTLIL::Design::scratchpad_get_bool(std::string varname, bool default_value) const
505 {
506 if (scratchpad.count(varname) == 0)
507 return default_value;
508
509 std::string str = scratchpad.at(varname);
510
511 if (str == "0" || str == "false")
512 return false;
513
514 if (str == "1" || str == "true")
515 return true;
516
517 return default_value;
518 }
519
520 std::string RTLIL::Design::scratchpad_get_string(std::string varname, std::string default_value) const
521 {
522 if (scratchpad.count(varname) == 0)
523 return default_value;
524 return scratchpad.at(varname);
525 }
526
527 void RTLIL::Design::remove(RTLIL::Module *module)
528 {
529 for (auto mon : monitors)
530 mon->notify_module_del(module);
531
532 if (yosys_xtrace) {
533 log("#X# Remove Module: %s\n", log_id(module));
534 log_backtrace("-X- ", yosys_xtrace-1);
535 }
536
537 log_assert(modules_.at(module->name) == module);
538 modules_.erase(module->name);
539 delete module;
540 }
541
542 void RTLIL::Design::rename(RTLIL::Module *module, RTLIL::IdString new_name)
543 {
544 modules_.erase(module->name);
545 module->name = new_name;
546 add(module);
547 }
548
549 void RTLIL::Design::sort()
550 {
551 scratchpad.sort();
552 modules_.sort(sort_by_id_str());
553 for (auto &it : modules_)
554 it.second->sort();
555 }
556
557 void RTLIL::Design::check()
558 {
559 #ifndef NDEBUG
560 for (auto &it : modules_) {
561 log_assert(this == it.second->design);
562 log_assert(it.first == it.second->name);
563 log_assert(!it.first.empty());
564 it.second->check();
565 }
566 #endif
567 }
568
569 void RTLIL::Design::optimize()
570 {
571 for (auto &it : modules_)
572 it.second->optimize();
573 for (auto &it : selection_stack)
574 it.optimize(this);
575 for (auto &it : selection_vars)
576 it.second.optimize(this);
577 }
578
579 bool RTLIL::Design::selected_module(RTLIL::IdString mod_name) const
580 {
581 if (!selected_active_module.empty() && mod_name != selected_active_module)
582 return false;
583 if (selection_stack.size() == 0)
584 return true;
585 return selection_stack.back().selected_module(mod_name);
586 }
587
588 bool RTLIL::Design::selected_whole_module(RTLIL::IdString mod_name) const
589 {
590 if (!selected_active_module.empty() && mod_name != selected_active_module)
591 return false;
592 if (selection_stack.size() == 0)
593 return true;
594 return selection_stack.back().selected_whole_module(mod_name);
595 }
596
597 bool RTLIL::Design::selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const
598 {
599 if (!selected_active_module.empty() && mod_name != selected_active_module)
600 return false;
601 if (selection_stack.size() == 0)
602 return true;
603 return selection_stack.back().selected_member(mod_name, memb_name);
604 }
605
606 bool RTLIL::Design::selected_module(RTLIL::Module *mod) const
607 {
608 return selected_module(mod->name);
609 }
610
611 bool RTLIL::Design::selected_whole_module(RTLIL::Module *mod) const
612 {
613 return selected_whole_module(mod->name);
614 }
615
616 std::vector<RTLIL::Module*> RTLIL::Design::selected_modules() const
617 {
618 std::vector<RTLIL::Module*> result;
619 result.reserve(modules_.size());
620 for (auto &it : modules_)
621 if (selected_module(it.first) && !it.second->get_blackbox_attribute())
622 result.push_back(it.second);
623 return result;
624 }
625
626 std::vector<RTLIL::Module*> RTLIL::Design::selected_whole_modules() const
627 {
628 std::vector<RTLIL::Module*> result;
629 result.reserve(modules_.size());
630 for (auto &it : modules_)
631 if (selected_whole_module(it.first) && !it.second->get_blackbox_attribute())
632 result.push_back(it.second);
633 return result;
634 }
635
636 std::vector<RTLIL::Module*> RTLIL::Design::selected_whole_modules_warn() const
637 {
638 std::vector<RTLIL::Module*> result;
639 result.reserve(modules_.size());
640 for (auto &it : modules_)
641 if (it.second->get_blackbox_attribute())
642 continue;
643 else if (selected_whole_module(it.first))
644 result.push_back(it.second);
645 else if (selected_module(it.first))
646 log_warning("Ignoring partially selected module %s.\n", log_id(it.first));
647 return result;
648 }
649
650 RTLIL::Module::Module()
651 {
652 static unsigned int hashidx_count = 123456789;
653 hashidx_count = mkhash_xorshift(hashidx_count);
654 hashidx_ = hashidx_count;
655
656 design = nullptr;
657 refcount_wires_ = 0;
658 refcount_cells_ = 0;
659
660 #ifdef WITH_PYTHON
661 RTLIL::Module::get_all_modules()->insert(std::pair<unsigned int, RTLIL::Module*>(hashidx_, this));
662 #endif
663 }
664
665 RTLIL::Module::~Module()
666 {
667 for (auto it = wires_.begin(); it != wires_.end(); ++it)
668 delete it->second;
669 for (auto it = memories.begin(); it != memories.end(); ++it)
670 delete it->second;
671 for (auto it = cells_.begin(); it != cells_.end(); ++it)
672 delete it->second;
673 for (auto it = processes.begin(); it != processes.end(); ++it)
674 delete it->second;
675 #ifdef WITH_PYTHON
676 RTLIL::Module::get_all_modules()->erase(hashidx_);
677 #endif
678 }
679
680 #ifdef WITH_PYTHON
681 static std::map<unsigned int, RTLIL::Module*> all_modules;
682 std::map<unsigned int, RTLIL::Module*> *RTLIL::Module::get_all_modules(void)
683 {
684 return &all_modules;
685 }
686 #endif
687
688 void RTLIL::Module::makeblackbox()
689 {
690 pool<RTLIL::Wire*> delwires;
691
692 for (auto it = wires_.begin(); it != wires_.end(); ++it)
693 if (!it->second->port_input && !it->second->port_output)
694 delwires.insert(it->second);
695
696 for (auto it = memories.begin(); it != memories.end(); ++it)
697 delete it->second;
698 memories.clear();
699
700 for (auto it = cells_.begin(); it != cells_.end(); ++it)
701 delete it->second;
702 cells_.clear();
703
704 for (auto it = processes.begin(); it != processes.end(); ++it)
705 delete it->second;
706 processes.clear();
707
708 remove(delwires);
709 set_bool_attribute("\\blackbox");
710 }
711
712 void RTLIL::Module::reprocess_module(RTLIL::Design *, dict<RTLIL::IdString, RTLIL::Module *>)
713 {
714 log_error("Cannot reprocess_module module `%s' !\n", id2cstr(name));
715 }
716
717 RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, dict<RTLIL::IdString, RTLIL::Const>, bool mayfail)
718 {
719 if (mayfail)
720 return RTLIL::IdString();
721 log_error("Module `%s' is used with parameters but is not parametric!\n", id2cstr(name));
722 }
723
724
725 RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, dict<RTLIL::IdString, RTLIL::Const>, dict<RTLIL::IdString, RTLIL::Module*>, dict<RTLIL::IdString, RTLIL::IdString>, bool mayfail)
726 {
727 if (mayfail)
728 return RTLIL::IdString();
729 log_error("Module `%s' is used with parameters but is not parametric!\n", id2cstr(name));
730 }
731
732 size_t RTLIL::Module::count_id(RTLIL::IdString id)
733 {
734 return wires_.count(id) + memories.count(id) + cells_.count(id) + processes.count(id);
735 }
736
737 #ifndef NDEBUG
738 namespace {
739 struct InternalCellChecker
740 {
741 RTLIL::Module *module;
742 RTLIL::Cell *cell;
743 pool<RTLIL::IdString> expected_params, expected_ports;
744
745 InternalCellChecker(RTLIL::Module *module, RTLIL::Cell *cell) : module(module), cell(cell) { }
746
747 void error(int linenr)
748 {
749 std::stringstream buf;
750 ILANG_BACKEND::dump_cell(buf, " ", cell);
751
752 log_error("Found error in internal cell %s%s%s (%s) at %s:%d:\n%s",
753 module ? module->name.c_str() : "", module ? "." : "",
754 cell->name.c_str(), cell->type.c_str(), __FILE__, linenr, buf.str().c_str());
755 }
756
757 int param(const char *name)
758 {
759 if (cell->parameters.count(name) == 0)
760 error(__LINE__);
761 expected_params.insert(name);
762 return cell->parameters.at(name).as_int();
763 }
764
765 int param_bool(const char *name)
766 {
767 int v = param(name);
768 if (cell->parameters.at(name).bits.size() > 32)
769 error(__LINE__);
770 if (v != 0 && v != 1)
771 error(__LINE__);
772 return v;
773 }
774
775 void param_bits(const char *name, int width)
776 {
777 param(name);
778 if (int(cell->parameters.at(name).bits.size()) != width)
779 error(__LINE__);
780 }
781
782 void port(const char *name, int width)
783 {
784 if (!cell->hasPort(name))
785 error(__LINE__);
786 if (cell->getPort(name).size() != width)
787 error(__LINE__);
788 expected_ports.insert(name);
789 }
790
791 void check_expected(bool check_matched_sign = true)
792 {
793 for (auto &para : cell->parameters)
794 if (expected_params.count(para.first) == 0)
795 error(__LINE__);
796 for (auto &conn : cell->connections())
797 if (expected_ports.count(conn.first) == 0)
798 error(__LINE__);
799
800 if (expected_params.count("\\A_SIGNED") != 0 && expected_params.count("\\B_SIGNED") && check_matched_sign) {
801 bool a_is_signed = param("\\A_SIGNED") != 0;
802 bool b_is_signed = param("\\B_SIGNED") != 0;
803 if (a_is_signed != b_is_signed)
804 error(__LINE__);
805 }
806 }
807
808 void check_gate(const char *ports)
809 {
810 if (cell->parameters.size() != 0)
811 error(__LINE__);
812
813 for (const char *p = ports; *p; p++) {
814 char portname[3] = { '\\', *p, 0 };
815 if (!cell->hasPort(portname))
816 error(__LINE__);
817 if (cell->getPort(portname).size() != 1)
818 error(__LINE__);
819 }
820
821 for (auto &conn : cell->connections()) {
822 if (conn.first.size() != 2 || conn.first[0] != '\\')
823 error(__LINE__);
824 if (strchr(ports, conn.first[1]) == NULL)
825 error(__LINE__);
826 }
827 }
828
829 void check()
830 {
831 if (cell->type.substr(0, 1) != "$" || cell->type.substr(0, 3) == "$__" || cell->type.substr(0, 8) == "$paramod" || cell->type.substr(0,10) == "$fmcombine" ||
832 cell->type.substr(0, 9) == "$verific$" || cell->type.substr(0, 7) == "$array:" || cell->type.substr(0, 8) == "$extern:")
833 return;
834
835 if (cell->type.in("$not", "$pos", "$neg")) {
836 param_bool("\\A_SIGNED");
837 port("\\A", param("\\A_WIDTH"));
838 port("\\Y", param("\\Y_WIDTH"));
839 check_expected();
840 return;
841 }
842
843 if (cell->type.in("$and", "$or", "$xor", "$xnor")) {
844 param_bool("\\A_SIGNED");
845 param_bool("\\B_SIGNED");
846 port("\\A", param("\\A_WIDTH"));
847 port("\\B", param("\\B_WIDTH"));
848 port("\\Y", param("\\Y_WIDTH"));
849 check_expected();
850 return;
851 }
852
853 if (cell->type.in("$reduce_and", "$reduce_or", "$reduce_xor", "$reduce_xnor", "$reduce_bool")) {
854 param_bool("\\A_SIGNED");
855 port("\\A", param("\\A_WIDTH"));
856 port("\\Y", param("\\Y_WIDTH"));
857 check_expected();
858 return;
859 }
860
861 if (cell->type.in("$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx")) {
862 param_bool("\\A_SIGNED");
863 param_bool("\\B_SIGNED");
864 port("\\A", param("\\A_WIDTH"));
865 port("\\B", param("\\B_WIDTH"));
866 port("\\Y", param("\\Y_WIDTH"));
867 check_expected(false);
868 return;
869 }
870
871 if (cell->type.in("$lt", "$le", "$eq", "$ne", "$eqx", "$nex", "$ge", "$gt")) {
872 param_bool("\\A_SIGNED");
873 param_bool("\\B_SIGNED");
874 port("\\A", param("\\A_WIDTH"));
875 port("\\B", param("\\B_WIDTH"));
876 port("\\Y", param("\\Y_WIDTH"));
877 check_expected();
878 return;
879 }
880
881 if (cell->type.in("$add", "$sub", "$mul", "$div", "$mod", "$pow")) {
882 param_bool("\\A_SIGNED");
883 param_bool("\\B_SIGNED");
884 port("\\A", param("\\A_WIDTH"));
885 port("\\B", param("\\B_WIDTH"));
886 port("\\Y", param("\\Y_WIDTH"));
887 check_expected(cell->type != "$pow");
888 return;
889 }
890
891 if (cell->type == "$fa") {
892 port("\\A", param("\\WIDTH"));
893 port("\\B", param("\\WIDTH"));
894 port("\\C", param("\\WIDTH"));
895 port("\\X", param("\\WIDTH"));
896 port("\\Y", param("\\WIDTH"));
897 check_expected();
898 return;
899 }
900
901 if (cell->type == "$lcu") {
902 port("\\P", param("\\WIDTH"));
903 port("\\G", param("\\WIDTH"));
904 port("\\CI", 1);
905 port("\\CO", param("\\WIDTH"));
906 check_expected();
907 return;
908 }
909
910 if (cell->type == "$alu") {
911 param_bool("\\A_SIGNED");
912 param_bool("\\B_SIGNED");
913 port("\\A", param("\\A_WIDTH"));
914 port("\\B", param("\\B_WIDTH"));
915 port("\\CI", 1);
916 port("\\BI", 1);
917 port("\\X", param("\\Y_WIDTH"));
918 port("\\Y", param("\\Y_WIDTH"));
919 port("\\CO", param("\\Y_WIDTH"));
920 check_expected();
921 return;
922 }
923
924 if (cell->type == "$macc") {
925 param("\\CONFIG");
926 param("\\CONFIG_WIDTH");
927 port("\\A", param("\\A_WIDTH"));
928 port("\\B", param("\\B_WIDTH"));
929 port("\\Y", param("\\Y_WIDTH"));
930 check_expected();
931 Macc().from_cell(cell);
932 return;
933 }
934
935 if (cell->type == "$logic_not") {
936 param_bool("\\A_SIGNED");
937 port("\\A", param("\\A_WIDTH"));
938 port("\\Y", param("\\Y_WIDTH"));
939 check_expected();
940 return;
941 }
942
943 if (cell->type == "$logic_and" || cell->type == "$logic_or") {
944 param_bool("\\A_SIGNED");
945 param_bool("\\B_SIGNED");
946 port("\\A", param("\\A_WIDTH"));
947 port("\\B", param("\\B_WIDTH"));
948 port("\\Y", param("\\Y_WIDTH"));
949 check_expected(false);
950 return;
951 }
952
953 if (cell->type == "$slice") {
954 param("\\OFFSET");
955 port("\\A", param("\\A_WIDTH"));
956 port("\\Y", param("\\Y_WIDTH"));
957 if (param("\\OFFSET") + param("\\Y_WIDTH") > param("\\A_WIDTH"))
958 error(__LINE__);
959 check_expected();
960 return;
961 }
962
963 if (cell->type == "$concat") {
964 port("\\A", param("\\A_WIDTH"));
965 port("\\B", param("\\B_WIDTH"));
966 port("\\Y", param("\\A_WIDTH") + param("\\B_WIDTH"));
967 check_expected();
968 return;
969 }
970
971 if (cell->type == "$mux") {
972 port("\\A", param("\\WIDTH"));
973 port("\\B", param("\\WIDTH"));
974 port("\\S", 1);
975 port("\\Y", param("\\WIDTH"));
976 check_expected();
977 return;
978 }
979
980 if (cell->type == "$pmux") {
981 port("\\A", param("\\WIDTH"));
982 port("\\B", param("\\WIDTH") * param("\\S_WIDTH"));
983 port("\\S", param("\\S_WIDTH"));
984 port("\\Y", param("\\WIDTH"));
985 check_expected();
986 return;
987 }
988
989 if (cell->type == "$lut") {
990 param("\\LUT");
991 port("\\A", param("\\WIDTH"));
992 port("\\Y", 1);
993 check_expected();
994 return;
995 }
996
997 if (cell->type == "$sop") {
998 param("\\DEPTH");
999 param("\\TABLE");
1000 port("\\A", param("\\WIDTH"));
1001 port("\\Y", 1);
1002 check_expected();
1003 return;
1004 }
1005
1006 if (cell->type == "$sr") {
1007 param_bool("\\SET_POLARITY");
1008 param_bool("\\CLR_POLARITY");
1009 port("\\SET", param("\\WIDTH"));
1010 port("\\CLR", param("\\WIDTH"));
1011 port("\\Q", param("\\WIDTH"));
1012 check_expected();
1013 return;
1014 }
1015
1016 if (cell->type == "$ff") {
1017 port("\\D", param("\\WIDTH"));
1018 port("\\Q", param("\\WIDTH"));
1019 check_expected();
1020 return;
1021 }
1022
1023 if (cell->type == "$dff") {
1024 param_bool("\\CLK_POLARITY");
1025 port("\\CLK", 1);
1026 port("\\D", param("\\WIDTH"));
1027 port("\\Q", param("\\WIDTH"));
1028 check_expected();
1029 return;
1030 }
1031
1032 if (cell->type == "$dffe") {
1033 param_bool("\\CLK_POLARITY");
1034 param_bool("\\EN_POLARITY");
1035 port("\\CLK", 1);
1036 port("\\EN", 1);
1037 port("\\D", param("\\WIDTH"));
1038 port("\\Q", param("\\WIDTH"));
1039 check_expected();
1040 return;
1041 }
1042
1043 if (cell->type == "$dffsr") {
1044 param_bool("\\CLK_POLARITY");
1045 param_bool("\\SET_POLARITY");
1046 param_bool("\\CLR_POLARITY");
1047 port("\\CLK", 1);
1048 port("\\SET", param("\\WIDTH"));
1049 port("\\CLR", param("\\WIDTH"));
1050 port("\\D", param("\\WIDTH"));
1051 port("\\Q", param("\\WIDTH"));
1052 check_expected();
1053 return;
1054 }
1055
1056 if (cell->type == "$adff") {
1057 param_bool("\\CLK_POLARITY");
1058 param_bool("\\ARST_POLARITY");
1059 param_bits("\\ARST_VALUE", param("\\WIDTH"));
1060 port("\\CLK", 1);
1061 port("\\ARST", 1);
1062 port("\\D", param("\\WIDTH"));
1063 port("\\Q", param("\\WIDTH"));
1064 check_expected();
1065 return;
1066 }
1067
1068 if (cell->type == "$dlatch") {
1069 param_bool("\\EN_POLARITY");
1070 port("\\EN", 1);
1071 port("\\D", param("\\WIDTH"));
1072 port("\\Q", param("\\WIDTH"));
1073 check_expected();
1074 return;
1075 }
1076
1077 if (cell->type == "$dlatchsr") {
1078 param_bool("\\EN_POLARITY");
1079 param_bool("\\SET_POLARITY");
1080 param_bool("\\CLR_POLARITY");
1081 port("\\EN", 1);
1082 port("\\SET", param("\\WIDTH"));
1083 port("\\CLR", param("\\WIDTH"));
1084 port("\\D", param("\\WIDTH"));
1085 port("\\Q", param("\\WIDTH"));
1086 check_expected();
1087 return;
1088 }
1089
1090 if (cell->type == "$fsm") {
1091 param("\\NAME");
1092 param_bool("\\CLK_POLARITY");
1093 param_bool("\\ARST_POLARITY");
1094 param("\\STATE_BITS");
1095 param("\\STATE_NUM");
1096 param("\\STATE_NUM_LOG2");
1097 param("\\STATE_RST");
1098 param_bits("\\STATE_TABLE", param("\\STATE_BITS") * param("\\STATE_NUM"));
1099 param("\\TRANS_NUM");
1100 param_bits("\\TRANS_TABLE", param("\\TRANS_NUM") * (2*param("\\STATE_NUM_LOG2") + param("\\CTRL_IN_WIDTH") + param("\\CTRL_OUT_WIDTH")));
1101 port("\\CLK", 1);
1102 port("\\ARST", 1);
1103 port("\\CTRL_IN", param("\\CTRL_IN_WIDTH"));
1104 port("\\CTRL_OUT", param("\\CTRL_OUT_WIDTH"));
1105 check_expected();
1106 return;
1107 }
1108
1109 if (cell->type == "$memrd") {
1110 param("\\MEMID");
1111 param_bool("\\CLK_ENABLE");
1112 param_bool("\\CLK_POLARITY");
1113 param_bool("\\TRANSPARENT");
1114 port("\\CLK", 1);
1115 port("\\EN", 1);
1116 port("\\ADDR", param("\\ABITS"));
1117 port("\\DATA", param("\\WIDTH"));
1118 check_expected();
1119 return;
1120 }
1121
1122 if (cell->type == "$memwr") {
1123 param("\\MEMID");
1124 param_bool("\\CLK_ENABLE");
1125 param_bool("\\CLK_POLARITY");
1126 param("\\PRIORITY");
1127 port("\\CLK", 1);
1128 port("\\EN", param("\\WIDTH"));
1129 port("\\ADDR", param("\\ABITS"));
1130 port("\\DATA", param("\\WIDTH"));
1131 check_expected();
1132 return;
1133 }
1134
1135 if (cell->type == "$meminit") {
1136 param("\\MEMID");
1137 param("\\PRIORITY");
1138 port("\\ADDR", param("\\ABITS"));
1139 port("\\DATA", param("\\WIDTH") * param("\\WORDS"));
1140 check_expected();
1141 return;
1142 }
1143
1144 if (cell->type == "$mem") {
1145 param("\\MEMID");
1146 param("\\SIZE");
1147 param("\\OFFSET");
1148 param("\\INIT");
1149 param_bits("\\RD_CLK_ENABLE", max(1, param("\\RD_PORTS")));
1150 param_bits("\\RD_CLK_POLARITY", max(1, param("\\RD_PORTS")));
1151 param_bits("\\RD_TRANSPARENT", max(1, param("\\RD_PORTS")));
1152 param_bits("\\WR_CLK_ENABLE", max(1, param("\\WR_PORTS")));
1153 param_bits("\\WR_CLK_POLARITY", max(1, param("\\WR_PORTS")));
1154 port("\\RD_CLK", param("\\RD_PORTS"));
1155 port("\\RD_EN", param("\\RD_PORTS"));
1156 port("\\RD_ADDR", param("\\RD_PORTS") * param("\\ABITS"));
1157 port("\\RD_DATA", param("\\RD_PORTS") * param("\\WIDTH"));
1158 port("\\WR_CLK", param("\\WR_PORTS"));
1159 port("\\WR_EN", param("\\WR_PORTS") * param("\\WIDTH"));
1160 port("\\WR_ADDR", param("\\WR_PORTS") * param("\\ABITS"));
1161 port("\\WR_DATA", param("\\WR_PORTS") * param("\\WIDTH"));
1162 check_expected();
1163 return;
1164 }
1165
1166 if (cell->type == "$tribuf") {
1167 port("\\A", param("\\WIDTH"));
1168 port("\\Y", param("\\WIDTH"));
1169 port("\\EN", 1);
1170 check_expected();
1171 return;
1172 }
1173
1174 if (cell->type.in("$assert", "$assume", "$live", "$fair", "$cover")) {
1175 port("\\A", 1);
1176 port("\\EN", 1);
1177 check_expected();
1178 return;
1179 }
1180
1181 if (cell->type == "$initstate") {
1182 port("\\Y", 1);
1183 check_expected();
1184 return;
1185 }
1186
1187 if (cell->type.in("$anyconst", "$anyseq", "$allconst", "$allseq")) {
1188 port("\\Y", param("\\WIDTH"));
1189 check_expected();
1190 return;
1191 }
1192
1193 if (cell->type == "$equiv") {
1194 port("\\A", 1);
1195 port("\\B", 1);
1196 port("\\Y", 1);
1197 check_expected();
1198 return;
1199 }
1200
1201 if (cell->type.in("$specify2", "$specify3")) {
1202 param_bool("\\FULL");
1203 param_bool("\\SRC_DST_PEN");
1204 param_bool("\\SRC_DST_POL");
1205 param("\\T_RISE_MIN");
1206 param("\\T_RISE_TYP");
1207 param("\\T_RISE_MAX");
1208 param("\\T_FALL_MIN");
1209 param("\\T_FALL_TYP");
1210 param("\\T_FALL_MAX");
1211 port("\\EN", 1);
1212 port("\\SRC", param("\\SRC_WIDTH"));
1213 port("\\DST", param("\\DST_WIDTH"));
1214 if (cell->type == "$specify3") {
1215 param_bool("\\EDGE_EN");
1216 param_bool("\\EDGE_POL");
1217 param_bool("\\DAT_DST_PEN");
1218 param_bool("\\DAT_DST_POL");
1219 port("\\DAT", param("\\DST_WIDTH"));
1220 }
1221 check_expected();
1222 return;
1223 }
1224
1225 if (cell->type == "$specrule") {
1226 param("\\TYPE");
1227 param_bool("\\SRC_PEN");
1228 param_bool("\\SRC_POL");
1229 param_bool("\\DST_PEN");
1230 param_bool("\\DST_POL");
1231 param("\\T_LIMIT");
1232 param("\\T_LIMIT2");
1233 port("\\SRC_EN", 1);
1234 port("\\DST_EN", 1);
1235 port("\\SRC", param("\\SRC_WIDTH"));
1236 port("\\DST", param("\\DST_WIDTH"));
1237 check_expected();
1238 return;
1239 }
1240
1241 if (cell->type == "$_BUF_") { check_gate("AY"); return; }
1242 if (cell->type == "$_NOT_") { check_gate("AY"); return; }
1243 if (cell->type == "$_AND_") { check_gate("ABY"); return; }
1244 if (cell->type == "$_NAND_") { check_gate("ABY"); return; }
1245 if (cell->type == "$_OR_") { check_gate("ABY"); return; }
1246 if (cell->type == "$_NOR_") { check_gate("ABY"); return; }
1247 if (cell->type == "$_XOR_") { check_gate("ABY"); return; }
1248 if (cell->type == "$_XNOR_") { check_gate("ABY"); return; }
1249 if (cell->type == "$_ANDNOT_") { check_gate("ABY"); return; }
1250 if (cell->type == "$_ORNOT_") { check_gate("ABY"); return; }
1251 if (cell->type == "$_MUX_") { check_gate("ABSY"); return; }
1252 if (cell->type == "$_AOI3_") { check_gate("ABCY"); return; }
1253 if (cell->type == "$_OAI3_") { check_gate("ABCY"); return; }
1254 if (cell->type == "$_AOI4_") { check_gate("ABCDY"); return; }
1255 if (cell->type == "$_OAI4_") { check_gate("ABCDY"); return; }
1256
1257 if (cell->type == "$_TBUF_") { check_gate("AYE"); return; }
1258
1259 if (cell->type == "$_MUX4_") { check_gate("ABCDSTY"); return; }
1260 if (cell->type == "$_MUX8_") { check_gate("ABCDEFGHSTUY"); return; }
1261 if (cell->type == "$_MUX16_") { check_gate("ABCDEFGHIJKLMNOPSTUVY"); return; }
1262
1263 if (cell->type == "$_SR_NN_") { check_gate("SRQ"); return; }
1264 if (cell->type == "$_SR_NP_") { check_gate("SRQ"); return; }
1265 if (cell->type == "$_SR_PN_") { check_gate("SRQ"); return; }
1266 if (cell->type == "$_SR_PP_") { check_gate("SRQ"); return; }
1267
1268 if (cell->type == "$_FF_") { check_gate("DQ"); return; }
1269 if (cell->type == "$_DFF_N_") { check_gate("DQC"); return; }
1270 if (cell->type == "$_DFF_P_") { check_gate("DQC"); return; }
1271
1272 if (cell->type == "$_DFFE_NN_") { check_gate("DQCE"); return; }
1273 if (cell->type == "$_DFFE_NP_") { check_gate("DQCE"); return; }
1274 if (cell->type == "$_DFFE_PN_") { check_gate("DQCE"); return; }
1275 if (cell->type == "$_DFFE_PP_") { check_gate("DQCE"); return; }
1276
1277 if (cell->type == "$_DFF_NN0_") { check_gate("DQCR"); return; }
1278 if (cell->type == "$_DFF_NN1_") { check_gate("DQCR"); return; }
1279 if (cell->type == "$_DFF_NP0_") { check_gate("DQCR"); return; }
1280 if (cell->type == "$_DFF_NP1_") { check_gate("DQCR"); return; }
1281 if (cell->type == "$_DFF_PN0_") { check_gate("DQCR"); return; }
1282 if (cell->type == "$_DFF_PN1_") { check_gate("DQCR"); return; }
1283 if (cell->type == "$_DFF_PP0_") { check_gate("DQCR"); return; }
1284 if (cell->type == "$_DFF_PP1_") { check_gate("DQCR"); return; }
1285
1286 if (cell->type == "$_DFFSR_NNN_") { check_gate("CSRDQ"); return; }
1287 if (cell->type == "$_DFFSR_NNP_") { check_gate("CSRDQ"); return; }
1288 if (cell->type == "$_DFFSR_NPN_") { check_gate("CSRDQ"); return; }
1289 if (cell->type == "$_DFFSR_NPP_") { check_gate("CSRDQ"); return; }
1290 if (cell->type == "$_DFFSR_PNN_") { check_gate("CSRDQ"); return; }
1291 if (cell->type == "$_DFFSR_PNP_") { check_gate("CSRDQ"); return; }
1292 if (cell->type == "$_DFFSR_PPN_") { check_gate("CSRDQ"); return; }
1293 if (cell->type == "$_DFFSR_PPP_") { check_gate("CSRDQ"); return; }
1294
1295 if (cell->type == "$_DLATCH_N_") { check_gate("EDQ"); return; }
1296 if (cell->type == "$_DLATCH_P_") { check_gate("EDQ"); return; }
1297
1298 if (cell->type == "$_DLATCHSR_NNN_") { check_gate("ESRDQ"); return; }
1299 if (cell->type == "$_DLATCHSR_NNP_") { check_gate("ESRDQ"); return; }
1300 if (cell->type == "$_DLATCHSR_NPN_") { check_gate("ESRDQ"); return; }
1301 if (cell->type == "$_DLATCHSR_NPP_") { check_gate("ESRDQ"); return; }
1302 if (cell->type == "$_DLATCHSR_PNN_") { check_gate("ESRDQ"); return; }
1303 if (cell->type == "$_DLATCHSR_PNP_") { check_gate("ESRDQ"); return; }
1304 if (cell->type == "$_DLATCHSR_PPN_") { check_gate("ESRDQ"); return; }
1305 if (cell->type == "$_DLATCHSR_PPP_") { check_gate("ESRDQ"); return; }
1306
1307 error(__LINE__);
1308 }
1309 };
1310 }
1311 #endif
1312
1313 void RTLIL::Module::sort()
1314 {
1315 wires_.sort(sort_by_id_str());
1316 cells_.sort(sort_by_id_str());
1317 avail_parameters.sort(sort_by_id_str());
1318 memories.sort(sort_by_id_str());
1319 processes.sort(sort_by_id_str());
1320 for (auto &it : cells_)
1321 it.second->sort();
1322 for (auto &it : wires_)
1323 it.second->attributes.sort(sort_by_id_str());
1324 for (auto &it : memories)
1325 it.second->attributes.sort(sort_by_id_str());
1326 }
1327
1328 void RTLIL::Module::check()
1329 {
1330 #ifndef NDEBUG
1331 std::vector<bool> ports_declared;
1332 for (auto &it : wires_) {
1333 log_assert(this == it.second->module);
1334 log_assert(it.first == it.second->name);
1335 log_assert(!it.first.empty());
1336 log_assert(it.second->width >= 0);
1337 log_assert(it.second->port_id >= 0);
1338 for (auto &it2 : it.second->attributes)
1339 log_assert(!it2.first.empty());
1340 if (it.second->port_id) {
1341 log_assert(GetSize(ports) >= it.second->port_id);
1342 log_assert(ports.at(it.second->port_id-1) == it.first);
1343 log_assert(it.second->port_input || it.second->port_output);
1344 if (GetSize(ports_declared) < it.second->port_id)
1345 ports_declared.resize(it.second->port_id);
1346 log_assert(ports_declared[it.second->port_id-1] == false);
1347 ports_declared[it.second->port_id-1] = true;
1348 } else
1349 log_assert(!it.second->port_input && !it.second->port_output);
1350 }
1351 for (auto port_declared : ports_declared)
1352 log_assert(port_declared == true);
1353 log_assert(GetSize(ports) == GetSize(ports_declared));
1354
1355 for (auto &it : memories) {
1356 log_assert(it.first == it.second->name);
1357 log_assert(!it.first.empty());
1358 log_assert(it.second->width >= 0);
1359 log_assert(it.second->size >= 0);
1360 for (auto &it2 : it.second->attributes)
1361 log_assert(!it2.first.empty());
1362 }
1363
1364 for (auto &it : cells_) {
1365 log_assert(this == it.second->module);
1366 log_assert(it.first == it.second->name);
1367 log_assert(!it.first.empty());
1368 log_assert(!it.second->type.empty());
1369 for (auto &it2 : it.second->connections()) {
1370 log_assert(!it2.first.empty());
1371 it2.second.check();
1372 }
1373 for (auto &it2 : it.second->attributes)
1374 log_assert(!it2.first.empty());
1375 for (auto &it2 : it.second->parameters)
1376 log_assert(!it2.first.empty());
1377 InternalCellChecker checker(this, it.second);
1378 checker.check();
1379 }
1380
1381 for (auto &it : processes) {
1382 log_assert(it.first == it.second->name);
1383 log_assert(!it.first.empty());
1384 log_assert(it.second->root_case.compare.empty());
1385 std::vector<CaseRule*> all_cases = {&it.second->root_case};
1386 for (size_t i = 0; i < all_cases.size(); i++) {
1387 for (auto &switch_it : all_cases[i]->switches) {
1388 for (auto &case_it : switch_it->cases) {
1389 for (auto &compare_it : case_it->compare) {
1390 log_assert(switch_it->signal.size() == compare_it.size());
1391 }
1392 all_cases.push_back(case_it);
1393 }
1394 }
1395 }
1396 for (auto &sync_it : it.second->syncs) {
1397 switch (sync_it->type) {
1398 case SyncType::ST0:
1399 case SyncType::ST1:
1400 case SyncType::STp:
1401 case SyncType::STn:
1402 case SyncType::STe:
1403 log_assert(!sync_it->signal.empty());
1404 break;
1405 case SyncType::STa:
1406 case SyncType::STg:
1407 case SyncType::STi:
1408 log_assert(sync_it->signal.empty());
1409 break;
1410 }
1411 }
1412 }
1413
1414 for (auto &it : connections_) {
1415 log_assert(it.first.size() == it.second.size());
1416 log_assert(!it.first.has_const());
1417 it.first.check();
1418 it.second.check();
1419 }
1420
1421 for (auto &it : attributes)
1422 log_assert(!it.first.empty());
1423 #endif
1424 }
1425
1426 void RTLIL::Module::optimize()
1427 {
1428 }
1429
1430 void RTLIL::Module::cloneInto(RTLIL::Module *new_mod) const
1431 {
1432 log_assert(new_mod->refcount_wires_ == 0);
1433 log_assert(new_mod->refcount_cells_ == 0);
1434
1435 new_mod->avail_parameters = avail_parameters;
1436
1437 for (auto &conn : connections_)
1438 new_mod->connect(conn);
1439
1440 for (auto &attr : attributes)
1441 new_mod->attributes[attr.first] = attr.second;
1442
1443 for (auto &it : wires_)
1444 new_mod->addWire(it.first, it.second);
1445
1446 for (auto &it : memories)
1447 new_mod->memories[it.first] = new RTLIL::Memory(*it.second);
1448
1449 for (auto &it : cells_)
1450 new_mod->addCell(it.first, it.second);
1451
1452 for (auto &it : processes)
1453 new_mod->processes[it.first] = it.second->clone();
1454
1455 struct RewriteSigSpecWorker
1456 {
1457 RTLIL::Module *mod;
1458 void operator()(RTLIL::SigSpec &sig)
1459 {
1460 std::vector<RTLIL::SigChunk> chunks = sig.chunks();
1461 for (auto &c : chunks)
1462 if (c.wire != NULL)
1463 c.wire = mod->wires_.at(c.wire->name);
1464 sig = chunks;
1465 }
1466 };
1467
1468 RewriteSigSpecWorker rewriteSigSpecWorker;
1469 rewriteSigSpecWorker.mod = new_mod;
1470 new_mod->rewrite_sigspecs(rewriteSigSpecWorker);
1471 new_mod->fixup_ports();
1472 }
1473
1474 RTLIL::Module *RTLIL::Module::clone() const
1475 {
1476 RTLIL::Module *new_mod = new RTLIL::Module;
1477 new_mod->name = name;
1478 cloneInto(new_mod);
1479 return new_mod;
1480 }
1481
1482 bool RTLIL::Module::has_memories() const
1483 {
1484 return !memories.empty();
1485 }
1486
1487 bool RTLIL::Module::has_processes() const
1488 {
1489 return !processes.empty();
1490 }
1491
1492 bool RTLIL::Module::has_memories_warn() const
1493 {
1494 if (!memories.empty())
1495 log_warning("Ignoring module %s because it contains memories (run 'memory' command first).\n", log_id(this));
1496 return !memories.empty();
1497 }
1498
1499 bool RTLIL::Module::has_processes_warn() const
1500 {
1501 if (!processes.empty())
1502 log_warning("Ignoring module %s because it contains processes (run 'proc' command first).\n", log_id(this));
1503 return !processes.empty();
1504 }
1505
1506 std::vector<RTLIL::Wire*> RTLIL::Module::selected_wires() const
1507 {
1508 std::vector<RTLIL::Wire*> result;
1509 result.reserve(wires_.size());
1510 for (auto &it : wires_)
1511 if (design->selected(this, it.second))
1512 result.push_back(it.second);
1513 return result;
1514 }
1515
1516 std::vector<RTLIL::Cell*> RTLIL::Module::selected_cells() const
1517 {
1518 std::vector<RTLIL::Cell*> result;
1519 result.reserve(wires_.size());
1520 for (auto &it : cells_)
1521 if (design->selected(this, it.second))
1522 result.push_back(it.second);
1523 return result;
1524 }
1525
1526 void RTLIL::Module::add(RTLIL::Wire *wire)
1527 {
1528 log_assert(!wire->name.empty());
1529 log_assert(count_id(wire->name) == 0);
1530 log_assert(refcount_wires_ == 0);
1531 wires_[wire->name] = wire;
1532 wire->module = this;
1533 }
1534
1535 void RTLIL::Module::add(RTLIL::Cell *cell)
1536 {
1537 log_assert(!cell->name.empty());
1538 log_assert(count_id(cell->name) == 0);
1539 log_assert(refcount_cells_ == 0);
1540 cells_[cell->name] = cell;
1541 cell->module = this;
1542 }
1543
1544 void RTLIL::Module::remove(const pool<RTLIL::Wire*> &wires)
1545 {
1546 log_assert(refcount_wires_ == 0);
1547
1548 struct DeleteWireWorker
1549 {
1550 RTLIL::Module *module;
1551 const pool<RTLIL::Wire*> *wires_p;
1552
1553 void operator()(RTLIL::SigSpec &sig) {
1554 std::vector<RTLIL::SigChunk> chunks = sig;
1555 for (auto &c : chunks)
1556 if (c.wire != NULL && wires_p->count(c.wire)) {
1557 c.wire = module->addWire(NEW_ID, c.width);
1558 c.offset = 0;
1559 }
1560 sig = chunks;
1561 }
1562
1563 void operator()(RTLIL::SigSpec &lhs, RTLIL::SigSpec &rhs) {
1564 log_assert(GetSize(lhs) == GetSize(rhs));
1565 RTLIL::SigSpec new_lhs, new_rhs;
1566 for (int i = 0; i < GetSize(lhs); i++) {
1567 RTLIL::SigBit lhs_bit = lhs[i];
1568 if (lhs_bit.wire != nullptr && wires_p->count(lhs_bit.wire))
1569 continue;
1570 RTLIL::SigBit rhs_bit = rhs[i];
1571 if (rhs_bit.wire != nullptr && wires_p->count(rhs_bit.wire))
1572 continue;
1573 new_lhs.append(lhs_bit);
1574 new_rhs.append(rhs_bit);
1575 }
1576 lhs = new_lhs;
1577 rhs = new_rhs;
1578 }
1579 };
1580
1581 DeleteWireWorker delete_wire_worker;
1582 delete_wire_worker.module = this;
1583 delete_wire_worker.wires_p = &wires;
1584 rewrite_sigspecs2(delete_wire_worker);
1585
1586 for (auto &it : wires) {
1587 log_assert(wires_.count(it->name) != 0);
1588 wires_.erase(it->name);
1589 delete it;
1590 }
1591 }
1592
1593 void RTLIL::Module::remove(RTLIL::Cell *cell)
1594 {
1595 while (!cell->connections_.empty())
1596 cell->unsetPort(cell->connections_.begin()->first);
1597
1598 auto it = cells_.find(cell->name);
1599 log_assert(it != cells_.end());
1600 log_assert(refcount_cells_ == 0);
1601 cells_.erase(it);
1602 delete cell;
1603 }
1604
1605 void RTLIL::Module::rename(RTLIL::Wire *wire, RTLIL::IdString new_name)
1606 {
1607 log_assert(wires_[wire->name] == wire);
1608 log_assert(refcount_wires_ == 0);
1609 wires_.erase(wire->name);
1610 wire->name = new_name;
1611 add(wire);
1612 }
1613
1614 void RTLIL::Module::rename(RTLIL::Cell *cell, RTLIL::IdString new_name)
1615 {
1616 log_assert(cells_[cell->name] == cell);
1617 log_assert(refcount_wires_ == 0);
1618 cells_.erase(cell->name);
1619 cell->name = new_name;
1620 add(cell);
1621 }
1622
1623 void RTLIL::Module::rename(RTLIL::IdString old_name, RTLIL::IdString new_name)
1624 {
1625 log_assert(count_id(old_name) != 0);
1626 if (wires_.count(old_name))
1627 rename(wires_.at(old_name), new_name);
1628 else if (cells_.count(old_name))
1629 rename(cells_.at(old_name), new_name);
1630 else
1631 log_abort();
1632 }
1633
1634 void RTLIL::Module::swap_names(RTLIL::Wire *w1, RTLIL::Wire *w2)
1635 {
1636 log_assert(wires_[w1->name] == w1);
1637 log_assert(wires_[w2->name] == w2);
1638 log_assert(refcount_wires_ == 0);
1639
1640 wires_.erase(w1->name);
1641 wires_.erase(w2->name);
1642
1643 std::swap(w1->name, w2->name);
1644
1645 wires_[w1->name] = w1;
1646 wires_[w2->name] = w2;
1647 }
1648
1649 void RTLIL::Module::swap_names(RTLIL::Cell *c1, RTLIL::Cell *c2)
1650 {
1651 log_assert(cells_[c1->name] == c1);
1652 log_assert(cells_[c2->name] == c2);
1653 log_assert(refcount_cells_ == 0);
1654
1655 cells_.erase(c1->name);
1656 cells_.erase(c2->name);
1657
1658 std::swap(c1->name, c2->name);
1659
1660 cells_[c1->name] = c1;
1661 cells_[c2->name] = c2;
1662 }
1663
1664 RTLIL::IdString RTLIL::Module::uniquify(RTLIL::IdString name)
1665 {
1666 int index = 0;
1667 return uniquify(name, index);
1668 }
1669
1670 RTLIL::IdString RTLIL::Module::uniquify(RTLIL::IdString name, int &index)
1671 {
1672 if (index == 0) {
1673 if (count_id(name) == 0)
1674 return name;
1675 index++;
1676 }
1677
1678 while (1) {
1679 RTLIL::IdString new_name = stringf("%s_%d", name.c_str(), index);
1680 if (count_id(new_name) == 0)
1681 return new_name;
1682 index++;
1683 }
1684 }
1685
1686 static bool fixup_ports_compare(const RTLIL::Wire *a, const RTLIL::Wire *b)
1687 {
1688 if (a->port_id && !b->port_id)
1689 return true;
1690 if (!a->port_id && b->port_id)
1691 return false;
1692
1693 if (a->port_id == b->port_id)
1694 return a->name < b->name;
1695 return a->port_id < b->port_id;
1696 }
1697
1698 void RTLIL::Module::connect(const RTLIL::SigSig &conn)
1699 {
1700 for (auto mon : monitors)
1701 mon->notify_connect(this, conn);
1702
1703 if (design)
1704 for (auto mon : design->monitors)
1705 mon->notify_connect(this, conn);
1706
1707 // ignore all attempts to assign constants to other constants
1708 if (conn.first.has_const()) {
1709 RTLIL::SigSig new_conn;
1710 for (int i = 0; i < GetSize(conn.first); i++)
1711 if (conn.first[i].wire) {
1712 new_conn.first.append(conn.first[i]);
1713 new_conn.second.append(conn.second[i]);
1714 }
1715 if (GetSize(new_conn.first))
1716 connect(new_conn);
1717 return;
1718 }
1719
1720 if (yosys_xtrace) {
1721 log("#X# Connect (SigSig) in %s: %s = %s (%d bits)\n", log_id(this), log_signal(conn.first), log_signal(conn.second), GetSize(conn.first));
1722 log_backtrace("-X- ", yosys_xtrace-1);
1723 }
1724
1725 log_assert(GetSize(conn.first) == GetSize(conn.second));
1726 connections_.push_back(conn);
1727 }
1728
1729 void RTLIL::Module::connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs)
1730 {
1731 connect(RTLIL::SigSig(lhs, rhs));
1732 }
1733
1734 void RTLIL::Module::new_connections(const std::vector<RTLIL::SigSig> &new_conn)
1735 {
1736 for (auto mon : monitors)
1737 mon->notify_connect(this, new_conn);
1738
1739 if (design)
1740 for (auto mon : design->monitors)
1741 mon->notify_connect(this, new_conn);
1742
1743 if (yosys_xtrace) {
1744 log("#X# New connections vector in %s:\n", log_id(this));
1745 for (auto &conn: new_conn)
1746 log("#X# %s = %s (%d bits)\n", log_signal(conn.first), log_signal(conn.second), GetSize(conn.first));
1747 log_backtrace("-X- ", yosys_xtrace-1);
1748 }
1749
1750 connections_ = new_conn;
1751 }
1752
1753 const std::vector<RTLIL::SigSig> &RTLIL::Module::connections() const
1754 {
1755 return connections_;
1756 }
1757
1758 void RTLIL::Module::fixup_ports()
1759 {
1760 std::vector<RTLIL::Wire*> all_ports;
1761
1762 for (auto &w : wires_)
1763 if (w.second->port_input || w.second->port_output)
1764 all_ports.push_back(w.second);
1765 else
1766 w.second->port_id = 0;
1767
1768 std::sort(all_ports.begin(), all_ports.end(), fixup_ports_compare);
1769
1770 ports.clear();
1771 for (size_t i = 0; i < all_ports.size(); i++) {
1772 ports.push_back(all_ports[i]->name);
1773 all_ports[i]->port_id = i+1;
1774 }
1775 }
1776
1777 RTLIL::Wire *RTLIL::Module::addWire(RTLIL::IdString name, int width)
1778 {
1779 RTLIL::Wire *wire = new RTLIL::Wire;
1780 wire->name = name;
1781 wire->width = width;
1782 add(wire);
1783 return wire;
1784 }
1785
1786 RTLIL::Wire *RTLIL::Module::addWire(RTLIL::IdString name, const RTLIL::Wire *other)
1787 {
1788 RTLIL::Wire *wire = addWire(name);
1789 wire->width = other->width;
1790 wire->start_offset = other->start_offset;
1791 wire->port_id = other->port_id;
1792 wire->port_input = other->port_input;
1793 wire->port_output = other->port_output;
1794 wire->upto = other->upto;
1795 wire->attributes = other->attributes;
1796 return wire;
1797 }
1798
1799 RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, RTLIL::IdString type)
1800 {
1801 RTLIL::Cell *cell = new RTLIL::Cell;
1802 cell->name = name;
1803 cell->type = type;
1804 add(cell);
1805 return cell;
1806 }
1807
1808 RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, const RTLIL::Cell *other)
1809 {
1810 RTLIL::Cell *cell = addCell(name, other->type);
1811 cell->connections_ = other->connections_;
1812 cell->parameters = other->parameters;
1813 cell->attributes = other->attributes;
1814 return cell;
1815 }
1816
1817 #define DEF_METHOD(_func, _y_size, _type) \
1818 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed, const std::string &src) { \
1819 RTLIL::Cell *cell = addCell(name, _type); \
1820 cell->parameters["\\A_SIGNED"] = is_signed; \
1821 cell->parameters["\\A_WIDTH"] = sig_a.size(); \
1822 cell->parameters["\\Y_WIDTH"] = sig_y.size(); \
1823 cell->setPort("\\A", sig_a); \
1824 cell->setPort("\\Y", sig_y); \
1825 cell->set_src_attribute(src); \
1826 return cell; \
1827 } \
1828 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed, const std::string &src) { \
1829 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
1830 add ## _func(name, sig_a, sig_y, is_signed, src); \
1831 return sig_y; \
1832 }
1833 DEF_METHOD(Not, sig_a.size(), "$not")
1834 DEF_METHOD(Pos, sig_a.size(), "$pos")
1835 DEF_METHOD(Neg, sig_a.size(), "$neg")
1836 DEF_METHOD(ReduceAnd, 1, "$reduce_and")
1837 DEF_METHOD(ReduceOr, 1, "$reduce_or")
1838 DEF_METHOD(ReduceXor, 1, "$reduce_xor")
1839 DEF_METHOD(ReduceXnor, 1, "$reduce_xnor")
1840 DEF_METHOD(ReduceBool, 1, "$reduce_bool")
1841 DEF_METHOD(LogicNot, 1, "$logic_not")
1842 #undef DEF_METHOD
1843
1844 #define DEF_METHOD(_func, _y_size, _type) \
1845 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed, const std::string &src) { \
1846 RTLIL::Cell *cell = addCell(name, _type); \
1847 cell->parameters["\\A_SIGNED"] = is_signed; \
1848 cell->parameters["\\B_SIGNED"] = is_signed; \
1849 cell->parameters["\\A_WIDTH"] = sig_a.size(); \
1850 cell->parameters["\\B_WIDTH"] = sig_b.size(); \
1851 cell->parameters["\\Y_WIDTH"] = sig_y.size(); \
1852 cell->setPort("\\A", sig_a); \
1853 cell->setPort("\\B", sig_b); \
1854 cell->setPort("\\Y", sig_y); \
1855 cell->set_src_attribute(src); \
1856 return cell; \
1857 } \
1858 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed, const std::string &src) { \
1859 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
1860 add ## _func(name, sig_a, sig_b, sig_y, is_signed, src); \
1861 return sig_y; \
1862 }
1863 DEF_METHOD(And, max(sig_a.size(), sig_b.size()), "$and")
1864 DEF_METHOD(Or, max(sig_a.size(), sig_b.size()), "$or")
1865 DEF_METHOD(Xor, max(sig_a.size(), sig_b.size()), "$xor")
1866 DEF_METHOD(Xnor, max(sig_a.size(), sig_b.size()), "$xnor")
1867 DEF_METHOD(Shl, sig_a.size(), "$shl")
1868 DEF_METHOD(Shr, sig_a.size(), "$shr")
1869 DEF_METHOD(Sshl, sig_a.size(), "$sshl")
1870 DEF_METHOD(Sshr, sig_a.size(), "$sshr")
1871 DEF_METHOD(Shift, sig_a.size(), "$shift")
1872 DEF_METHOD(Shiftx, sig_a.size(), "$shiftx")
1873 DEF_METHOD(Lt, 1, "$lt")
1874 DEF_METHOD(Le, 1, "$le")
1875 DEF_METHOD(Eq, 1, "$eq")
1876 DEF_METHOD(Ne, 1, "$ne")
1877 DEF_METHOD(Eqx, 1, "$eqx")
1878 DEF_METHOD(Nex, 1, "$nex")
1879 DEF_METHOD(Ge, 1, "$ge")
1880 DEF_METHOD(Gt, 1, "$gt")
1881 DEF_METHOD(Add, max(sig_a.size(), sig_b.size()), "$add")
1882 DEF_METHOD(Sub, max(sig_a.size(), sig_b.size()), "$sub")
1883 DEF_METHOD(Mul, max(sig_a.size(), sig_b.size()), "$mul")
1884 DEF_METHOD(Div, max(sig_a.size(), sig_b.size()), "$div")
1885 DEF_METHOD(Mod, max(sig_a.size(), sig_b.size()), "$mod")
1886 DEF_METHOD(LogicAnd, 1, "$logic_and")
1887 DEF_METHOD(LogicOr, 1, "$logic_or")
1888 #undef DEF_METHOD
1889
1890 #define DEF_METHOD(_func, _type, _pmux) \
1891 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, RTLIL::SigSpec sig_y, const std::string &src) { \
1892 RTLIL::Cell *cell = addCell(name, _type); \
1893 cell->parameters["\\WIDTH"] = sig_a.size(); \
1894 if (_pmux) cell->parameters["\\S_WIDTH"] = sig_s.size(); \
1895 cell->setPort("\\A", sig_a); \
1896 cell->setPort("\\B", sig_b); \
1897 cell->setPort("\\S", sig_s); \
1898 cell->setPort("\\Y", sig_y); \
1899 cell->set_src_attribute(src); \
1900 return cell; \
1901 } \
1902 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, const std::string &src) { \
1903 RTLIL::SigSpec sig_y = addWire(NEW_ID, sig_a.size()); \
1904 add ## _func(name, sig_a, sig_b, sig_s, sig_y, src); \
1905 return sig_y; \
1906 }
1907 DEF_METHOD(Mux, "$mux", 0)
1908 DEF_METHOD(Pmux, "$pmux", 1)
1909 #undef DEF_METHOD
1910
1911 #define DEF_METHOD_2(_func, _type, _P1, _P2) \
1912 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, const std::string &src) { \
1913 RTLIL::Cell *cell = addCell(name, _type); \
1914 cell->setPort("\\" #_P1, sig1); \
1915 cell->setPort("\\" #_P2, sig2); \
1916 cell->set_src_attribute(src); \
1917 return cell; \
1918 } \
1919 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, const std::string &src) { \
1920 RTLIL::SigBit sig2 = addWire(NEW_ID); \
1921 add ## _func(name, sig1, sig2, src); \
1922 return sig2; \
1923 }
1924 #define DEF_METHOD_3(_func, _type, _P1, _P2, _P3) \
1925 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, const std::string &src) { \
1926 RTLIL::Cell *cell = addCell(name, _type); \
1927 cell->setPort("\\" #_P1, sig1); \
1928 cell->setPort("\\" #_P2, sig2); \
1929 cell->setPort("\\" #_P3, sig3); \
1930 cell->set_src_attribute(src); \
1931 return cell; \
1932 } \
1933 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, const std::string &src) { \
1934 RTLIL::SigBit sig3 = addWire(NEW_ID); \
1935 add ## _func(name, sig1, sig2, sig3, src); \
1936 return sig3; \
1937 }
1938 #define DEF_METHOD_4(_func, _type, _P1, _P2, _P3, _P4) \
1939 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, RTLIL::SigBit sig4, const std::string &src) { \
1940 RTLIL::Cell *cell = addCell(name, _type); \
1941 cell->setPort("\\" #_P1, sig1); \
1942 cell->setPort("\\" #_P2, sig2); \
1943 cell->setPort("\\" #_P3, sig3); \
1944 cell->setPort("\\" #_P4, sig4); \
1945 cell->set_src_attribute(src); \
1946 return cell; \
1947 } \
1948 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, const std::string &src) { \
1949 RTLIL::SigBit sig4 = addWire(NEW_ID); \
1950 add ## _func(name, sig1, sig2, sig3, sig4, src); \
1951 return sig4; \
1952 }
1953 #define DEF_METHOD_5(_func, _type, _P1, _P2, _P3, _P4, _P5) \
1954 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, RTLIL::SigBit sig4, RTLIL::SigBit sig5, const std::string &src) { \
1955 RTLIL::Cell *cell = addCell(name, _type); \
1956 cell->setPort("\\" #_P1, sig1); \
1957 cell->setPort("\\" #_P2, sig2); \
1958 cell->setPort("\\" #_P3, sig3); \
1959 cell->setPort("\\" #_P4, sig4); \
1960 cell->setPort("\\" #_P5, sig5); \
1961 cell->set_src_attribute(src); \
1962 return cell; \
1963 } \
1964 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, RTLIL::SigBit sig4, const std::string &src) { \
1965 RTLIL::SigBit sig5 = addWire(NEW_ID); \
1966 add ## _func(name, sig1, sig2, sig3, sig4, sig5, src); \
1967 return sig5; \
1968 }
1969 DEF_METHOD_2(BufGate, "$_BUF_", A, Y)
1970 DEF_METHOD_2(NotGate, "$_NOT_", A, Y)
1971 DEF_METHOD_3(AndGate, "$_AND_", A, B, Y)
1972 DEF_METHOD_3(NandGate, "$_NAND_", A, B, Y)
1973 DEF_METHOD_3(OrGate, "$_OR_", A, B, Y)
1974 DEF_METHOD_3(NorGate, "$_NOR_", A, B, Y)
1975 DEF_METHOD_3(XorGate, "$_XOR_", A, B, Y)
1976 DEF_METHOD_3(XnorGate, "$_XNOR_", A, B, Y)
1977 DEF_METHOD_3(AndnotGate, "$_ANDNOT_", A, B, Y)
1978 DEF_METHOD_3(OrnotGate, "$_ORNOT_", A, B, Y)
1979 DEF_METHOD_4(MuxGate, "$_MUX_", A, B, S, Y)
1980 DEF_METHOD_4(Aoi3Gate, "$_AOI3_", A, B, C, Y)
1981 DEF_METHOD_4(Oai3Gate, "$_OAI3_", A, B, C, Y)
1982 DEF_METHOD_5(Aoi4Gate, "$_AOI4_", A, B, C, D, Y)
1983 DEF_METHOD_5(Oai4Gate, "$_OAI4_", A, B, C, D, Y)
1984 #undef DEF_METHOD_2
1985 #undef DEF_METHOD_3
1986 #undef DEF_METHOD_4
1987 #undef DEF_METHOD_5
1988
1989 RTLIL::Cell* RTLIL::Module::addPow(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool a_signed, bool b_signed, const std::string &src)
1990 {
1991 RTLIL::Cell *cell = addCell(name, "$pow");
1992 cell->parameters["\\A_SIGNED"] = a_signed;
1993 cell->parameters["\\B_SIGNED"] = b_signed;
1994 cell->parameters["\\A_WIDTH"] = sig_a.size();
1995 cell->parameters["\\B_WIDTH"] = sig_b.size();
1996 cell->parameters["\\Y_WIDTH"] = sig_y.size();
1997 cell->setPort("\\A", sig_a);
1998 cell->setPort("\\B", sig_b);
1999 cell->setPort("\\Y", sig_y);
2000 cell->set_src_attribute(src);
2001 return cell;
2002 }
2003
2004 RTLIL::Cell* RTLIL::Module::addSlice(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, RTLIL::Const offset, const std::string &src)
2005 {
2006 RTLIL::Cell *cell = addCell(name, "$slice");
2007 cell->parameters["\\A_WIDTH"] = sig_a.size();
2008 cell->parameters["\\Y_WIDTH"] = sig_y.size();
2009 cell->parameters["\\OFFSET"] = offset;
2010 cell->setPort("\\A", sig_a);
2011 cell->setPort("\\Y", sig_y);
2012 cell->set_src_attribute(src);
2013 return cell;
2014 }
2015
2016 RTLIL::Cell* RTLIL::Module::addConcat(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, const std::string &src)
2017 {
2018 RTLIL::Cell *cell = addCell(name, "$concat");
2019 cell->parameters["\\A_WIDTH"] = sig_a.size();
2020 cell->parameters["\\B_WIDTH"] = sig_b.size();
2021 cell->setPort("\\A", sig_a);
2022 cell->setPort("\\B", sig_b);
2023 cell->setPort("\\Y", sig_y);
2024 cell->set_src_attribute(src);
2025 return cell;
2026 }
2027
2028 RTLIL::Cell* RTLIL::Module::addLut(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, RTLIL::Const lut, const std::string &src)
2029 {
2030 RTLIL::Cell *cell = addCell(name, "$lut");
2031 cell->parameters["\\LUT"] = lut;
2032 cell->parameters["\\WIDTH"] = sig_a.size();
2033 cell->setPort("\\A", sig_a);
2034 cell->setPort("\\Y", sig_y);
2035 cell->set_src_attribute(src);
2036 return cell;
2037 }
2038
2039 RTLIL::Cell* RTLIL::Module::addTribuf(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_y, const std::string &src)
2040 {
2041 RTLIL::Cell *cell = addCell(name, "$tribuf");
2042 cell->parameters["\\WIDTH"] = sig_a.size();
2043 cell->setPort("\\A", sig_a);
2044 cell->setPort("\\EN", sig_en);
2045 cell->setPort("\\Y", sig_y);
2046 cell->set_src_attribute(src);
2047 return cell;
2048 }
2049
2050 RTLIL::Cell* RTLIL::Module::addAssert(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src)
2051 {
2052 RTLIL::Cell *cell = addCell(name, "$assert");
2053 cell->setPort("\\A", sig_a);
2054 cell->setPort("\\EN", sig_en);
2055 cell->set_src_attribute(src);
2056 return cell;
2057 }
2058
2059 RTLIL::Cell* RTLIL::Module::addAssume(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src)
2060 {
2061 RTLIL::Cell *cell = addCell(name, "$assume");
2062 cell->setPort("\\A", sig_a);
2063 cell->setPort("\\EN", sig_en);
2064 cell->set_src_attribute(src);
2065 return cell;
2066 }
2067
2068 RTLIL::Cell* RTLIL::Module::addLive(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src)
2069 {
2070 RTLIL::Cell *cell = addCell(name, "$live");
2071 cell->setPort("\\A", sig_a);
2072 cell->setPort("\\EN", sig_en);
2073 cell->set_src_attribute(src);
2074 return cell;
2075 }
2076
2077 RTLIL::Cell* RTLIL::Module::addFair(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src)
2078 {
2079 RTLIL::Cell *cell = addCell(name, "$fair");
2080 cell->setPort("\\A", sig_a);
2081 cell->setPort("\\EN", sig_en);
2082 cell->set_src_attribute(src);
2083 return cell;
2084 }
2085
2086 RTLIL::Cell* RTLIL::Module::addCover(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src)
2087 {
2088 RTLIL::Cell *cell = addCell(name, "$cover");
2089 cell->setPort("\\A", sig_a);
2090 cell->setPort("\\EN", sig_en);
2091 cell->set_src_attribute(src);
2092 return cell;
2093 }
2094
2095 RTLIL::Cell* RTLIL::Module::addEquiv(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, const std::string &src)
2096 {
2097 RTLIL::Cell *cell = addCell(name, "$equiv");
2098 cell->setPort("\\A", sig_a);
2099 cell->setPort("\\B", sig_b);
2100 cell->setPort("\\Y", sig_y);
2101 cell->set_src_attribute(src);
2102 return cell;
2103 }
2104
2105 RTLIL::Cell* RTLIL::Module::addSr(RTLIL::IdString name, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr, RTLIL::SigSpec sig_q, bool set_polarity, bool clr_polarity, const std::string &src)
2106 {
2107 RTLIL::Cell *cell = addCell(name, "$sr");
2108 cell->parameters["\\SET_POLARITY"] = set_polarity;
2109 cell->parameters["\\CLR_POLARITY"] = clr_polarity;
2110 cell->parameters["\\WIDTH"] = sig_q.size();
2111 cell->setPort("\\SET", sig_set);
2112 cell->setPort("\\CLR", sig_clr);
2113 cell->setPort("\\Q", sig_q);
2114 cell->set_src_attribute(src);
2115 return cell;
2116 }
2117
2118 RTLIL::Cell* RTLIL::Module::addFf(RTLIL::IdString name, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, const std::string &src)
2119 {
2120 RTLIL::Cell *cell = addCell(name, "$ff");
2121 cell->parameters["\\WIDTH"] = sig_q.size();
2122 cell->setPort("\\D", sig_d);
2123 cell->setPort("\\Q", sig_q);
2124 cell->set_src_attribute(src);
2125 return cell;
2126 }
2127
2128 RTLIL::Cell* RTLIL::Module::addDff(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, const std::string &src)
2129 {
2130 RTLIL::Cell *cell = addCell(name, "$dff");
2131 cell->parameters["\\CLK_POLARITY"] = clk_polarity;
2132 cell->parameters["\\WIDTH"] = sig_q.size();
2133 cell->setPort("\\CLK", sig_clk);
2134 cell->setPort("\\D", sig_d);
2135 cell->setPort("\\Q", sig_q);
2136 cell->set_src_attribute(src);
2137 return cell;
2138 }
2139
2140 RTLIL::Cell* RTLIL::Module::addDffe(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, bool en_polarity, const std::string &src)
2141 {
2142 RTLIL::Cell *cell = addCell(name, "$dffe");
2143 cell->parameters["\\CLK_POLARITY"] = clk_polarity;
2144 cell->parameters["\\EN_POLARITY"] = en_polarity;
2145 cell->parameters["\\WIDTH"] = sig_q.size();
2146 cell->setPort("\\CLK", sig_clk);
2147 cell->setPort("\\EN", sig_en);
2148 cell->setPort("\\D", sig_d);
2149 cell->setPort("\\Q", sig_q);
2150 cell->set_src_attribute(src);
2151 return cell;
2152 }
2153
2154 RTLIL::Cell* RTLIL::Module::addDffsr(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
2155 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
2156 {
2157 RTLIL::Cell *cell = addCell(name, "$dffsr");
2158 cell->parameters["\\CLK_POLARITY"] = clk_polarity;
2159 cell->parameters["\\SET_POLARITY"] = set_polarity;
2160 cell->parameters["\\CLR_POLARITY"] = clr_polarity;
2161 cell->parameters["\\WIDTH"] = sig_q.size();
2162 cell->setPort("\\CLK", sig_clk);
2163 cell->setPort("\\SET", sig_set);
2164 cell->setPort("\\CLR", sig_clr);
2165 cell->setPort("\\D", sig_d);
2166 cell->setPort("\\Q", sig_q);
2167 cell->set_src_attribute(src);
2168 return cell;
2169 }
2170
2171 RTLIL::Cell* RTLIL::Module::addAdff(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_arst, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q,
2172 RTLIL::Const arst_value, bool clk_polarity, bool arst_polarity, const std::string &src)
2173 {
2174 RTLIL::Cell *cell = addCell(name, "$adff");
2175 cell->parameters["\\CLK_POLARITY"] = clk_polarity;
2176 cell->parameters["\\ARST_POLARITY"] = arst_polarity;
2177 cell->parameters["\\ARST_VALUE"] = arst_value;
2178 cell->parameters["\\WIDTH"] = sig_q.size();
2179 cell->setPort("\\CLK", sig_clk);
2180 cell->setPort("\\ARST", sig_arst);
2181 cell->setPort("\\D", sig_d);
2182 cell->setPort("\\Q", sig_q);
2183 cell->set_src_attribute(src);
2184 return cell;
2185 }
2186
2187 RTLIL::Cell* RTLIL::Module::addDlatch(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity, const std::string &src)
2188 {
2189 RTLIL::Cell *cell = addCell(name, "$dlatch");
2190 cell->parameters["\\EN_POLARITY"] = en_polarity;
2191 cell->parameters["\\WIDTH"] = sig_q.size();
2192 cell->setPort("\\EN", sig_en);
2193 cell->setPort("\\D", sig_d);
2194 cell->setPort("\\Q", sig_q);
2195 cell->set_src_attribute(src);
2196 return cell;
2197 }
2198
2199 RTLIL::Cell* RTLIL::Module::addDlatchsr(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
2200 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
2201 {
2202 RTLIL::Cell *cell = addCell(name, "$dlatchsr");
2203 cell->parameters["\\EN_POLARITY"] = en_polarity;
2204 cell->parameters["\\SET_POLARITY"] = set_polarity;
2205 cell->parameters["\\CLR_POLARITY"] = clr_polarity;
2206 cell->parameters["\\WIDTH"] = sig_q.size();
2207 cell->setPort("\\EN", sig_en);
2208 cell->setPort("\\SET", sig_set);
2209 cell->setPort("\\CLR", sig_clr);
2210 cell->setPort("\\D", sig_d);
2211 cell->setPort("\\Q", sig_q);
2212 cell->set_src_attribute(src);
2213 return cell;
2214 }
2215
2216 RTLIL::Cell* RTLIL::Module::addFfGate(RTLIL::IdString name, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, const std::string &src)
2217 {
2218 RTLIL::Cell *cell = addCell(name, "$_FF_");
2219 cell->setPort("\\D", sig_d);
2220 cell->setPort("\\Q", sig_q);
2221 cell->set_src_attribute(src);
2222 return cell;
2223 }
2224
2225 RTLIL::Cell* RTLIL::Module::addDffGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, const std::string &src)
2226 {
2227 RTLIL::Cell *cell = addCell(name, stringf("$_DFF_%c_", clk_polarity ? 'P' : 'N'));
2228 cell->setPort("\\C", sig_clk);
2229 cell->setPort("\\D", sig_d);
2230 cell->setPort("\\Q", sig_q);
2231 cell->set_src_attribute(src);
2232 return cell;
2233 }
2234
2235 RTLIL::Cell* RTLIL::Module::addDffeGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, bool en_polarity, const std::string &src)
2236 {
2237 RTLIL::Cell *cell = addCell(name, stringf("$_DFFE_%c%c_", clk_polarity ? 'P' : 'N', en_polarity ? 'P' : 'N'));
2238 cell->setPort("\\C", sig_clk);
2239 cell->setPort("\\E", sig_en);
2240 cell->setPort("\\D", sig_d);
2241 cell->setPort("\\Q", sig_q);
2242 cell->set_src_attribute(src);
2243 return cell;
2244 }
2245
2246 RTLIL::Cell* RTLIL::Module::addDffsrGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
2247 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
2248 {
2249 RTLIL::Cell *cell = addCell(name, stringf("$_DFFSR_%c%c%c_", clk_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N'));
2250 cell->setPort("\\C", sig_clk);
2251 cell->setPort("\\S", sig_set);
2252 cell->setPort("\\R", sig_clr);
2253 cell->setPort("\\D", sig_d);
2254 cell->setPort("\\Q", sig_q);
2255 cell->set_src_attribute(src);
2256 return cell;
2257 }
2258
2259 RTLIL::Cell* RTLIL::Module::addAdffGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_arst, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q,
2260 bool arst_value, bool clk_polarity, bool arst_polarity, const std::string &src)
2261 {
2262 RTLIL::Cell *cell = addCell(name, stringf("$_DFF_%c%c%c_", clk_polarity ? 'P' : 'N', arst_polarity ? 'P' : 'N', arst_value ? '1' : '0'));
2263 cell->setPort("\\C", sig_clk);
2264 cell->setPort("\\R", sig_arst);
2265 cell->setPort("\\D", sig_d);
2266 cell->setPort("\\Q", sig_q);
2267 cell->set_src_attribute(src);
2268 return cell;
2269 }
2270
2271 RTLIL::Cell* RTLIL::Module::addDlatchGate(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity, const std::string &src)
2272 {
2273 RTLIL::Cell *cell = addCell(name, stringf("$_DLATCH_%c_", en_polarity ? 'P' : 'N'));
2274 cell->setPort("\\E", sig_en);
2275 cell->setPort("\\D", sig_d);
2276 cell->setPort("\\Q", sig_q);
2277 cell->set_src_attribute(src);
2278 return cell;
2279 }
2280
2281 RTLIL::Cell* RTLIL::Module::addDlatchsrGate(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
2282 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
2283 {
2284 RTLIL::Cell *cell = addCell(name, stringf("$_DLATCHSR_%c%c%c_", en_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N'));
2285 cell->setPort("\\E", sig_en);
2286 cell->setPort("\\S", sig_set);
2287 cell->setPort("\\R", sig_clr);
2288 cell->setPort("\\D", sig_d);
2289 cell->setPort("\\Q", sig_q);
2290 cell->set_src_attribute(src);
2291 return cell;
2292 }
2293
2294 RTLIL::SigSpec RTLIL::Module::Anyconst(RTLIL::IdString name, int width, const std::string &src)
2295 {
2296 RTLIL::SigSpec sig = addWire(NEW_ID, width);
2297 Cell *cell = addCell(name, "$anyconst");
2298 cell->setParam("\\WIDTH", width);
2299 cell->setPort("\\Y", sig);
2300 cell->set_src_attribute(src);
2301 return sig;
2302 }
2303
2304 RTLIL::SigSpec RTLIL::Module::Anyseq(RTLIL::IdString name, int width, const std::string &src)
2305 {
2306 RTLIL::SigSpec sig = addWire(NEW_ID, width);
2307 Cell *cell = addCell(name, "$anyseq");
2308 cell->setParam("\\WIDTH", width);
2309 cell->setPort("\\Y", sig);
2310 cell->set_src_attribute(src);
2311 return sig;
2312 }
2313
2314 RTLIL::SigSpec RTLIL::Module::Allconst(RTLIL::IdString name, int width, const std::string &src)
2315 {
2316 RTLIL::SigSpec sig = addWire(NEW_ID, width);
2317 Cell *cell = addCell(name, "$allconst");
2318 cell->setParam("\\WIDTH", width);
2319 cell->setPort("\\Y", sig);
2320 cell->set_src_attribute(src);
2321 return sig;
2322 }
2323
2324 RTLIL::SigSpec RTLIL::Module::Allseq(RTLIL::IdString name, int width, const std::string &src)
2325 {
2326 RTLIL::SigSpec sig = addWire(NEW_ID, width);
2327 Cell *cell = addCell(name, "$allseq");
2328 cell->setParam("\\WIDTH", width);
2329 cell->setPort("\\Y", sig);
2330 cell->set_src_attribute(src);
2331 return sig;
2332 }
2333
2334 RTLIL::SigSpec RTLIL::Module::Initstate(RTLIL::IdString name, const std::string &src)
2335 {
2336 RTLIL::SigSpec sig = addWire(NEW_ID);
2337 Cell *cell = addCell(name, "$initstate");
2338 cell->setPort("\\Y", sig);
2339 cell->set_src_attribute(src);
2340 return sig;
2341 }
2342
2343 RTLIL::Wire::Wire()
2344 {
2345 static unsigned int hashidx_count = 123456789;
2346 hashidx_count = mkhash_xorshift(hashidx_count);
2347 hashidx_ = hashidx_count;
2348
2349 module = nullptr;
2350 width = 1;
2351 start_offset = 0;
2352 port_id = 0;
2353 port_input = false;
2354 port_output = false;
2355 upto = false;
2356
2357 #ifdef WITH_PYTHON
2358 RTLIL::Wire::get_all_wires()->insert(std::pair<unsigned int, RTLIL::Wire*>(hashidx_, this));
2359 #endif
2360 }
2361
2362 RTLIL::Wire::~Wire()
2363 {
2364 #ifdef WITH_PYTHON
2365 RTLIL::Wire::get_all_wires()->erase(hashidx_);
2366 #endif
2367 }
2368
2369 #ifdef WITH_PYTHON
2370 static std::map<unsigned int, RTLIL::Wire*> all_wires;
2371 std::map<unsigned int, RTLIL::Wire*> *RTLIL::Wire::get_all_wires(void)
2372 {
2373 return &all_wires;
2374 }
2375 #endif
2376
2377 RTLIL::Memory::Memory()
2378 {
2379 static unsigned int hashidx_count = 123456789;
2380 hashidx_count = mkhash_xorshift(hashidx_count);
2381 hashidx_ = hashidx_count;
2382
2383 width = 1;
2384 start_offset = 0;
2385 size = 0;
2386 #ifdef WITH_PYTHON
2387 RTLIL::Memory::get_all_memorys()->insert(std::pair<unsigned int, RTLIL::Memory*>(hashidx_, this));
2388 #endif
2389 }
2390
2391 RTLIL::Cell::Cell() : module(nullptr)
2392 {
2393 static unsigned int hashidx_count = 123456789;
2394 hashidx_count = mkhash_xorshift(hashidx_count);
2395 hashidx_ = hashidx_count;
2396
2397 // log("#memtrace# %p\n", this);
2398 memhasher();
2399
2400 #ifdef WITH_PYTHON
2401 RTLIL::Cell::get_all_cells()->insert(std::pair<unsigned int, RTLIL::Cell*>(hashidx_, this));
2402 #endif
2403 }
2404
2405 RTLIL::Cell::~Cell()
2406 {
2407 #ifdef WITH_PYTHON
2408 RTLIL::Cell::get_all_cells()->erase(hashidx_);
2409 #endif
2410 }
2411
2412 #ifdef WITH_PYTHON
2413 static std::map<unsigned int, RTLIL::Cell*> all_cells;
2414 std::map<unsigned int, RTLIL::Cell*> *RTLIL::Cell::get_all_cells(void)
2415 {
2416 return &all_cells;
2417 }
2418 #endif
2419
2420 bool RTLIL::Cell::hasPort(RTLIL::IdString portname) const
2421 {
2422 return connections_.count(portname) != 0;
2423 }
2424
2425 void RTLIL::Cell::unsetPort(RTLIL::IdString portname)
2426 {
2427 RTLIL::SigSpec signal;
2428 auto conn_it = connections_.find(portname);
2429
2430 if (conn_it != connections_.end())
2431 {
2432 for (auto mon : module->monitors)
2433 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
2434
2435 if (module->design)
2436 for (auto mon : module->design->monitors)
2437 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
2438
2439 if (yosys_xtrace) {
2440 log("#X# Unconnect %s.%s.%s\n", log_id(this->module), log_id(this), log_id(portname));
2441 log_backtrace("-X- ", yosys_xtrace-1);
2442 }
2443
2444 connections_.erase(conn_it);
2445 }
2446 }
2447
2448 void RTLIL::Cell::setPort(RTLIL::IdString portname, RTLIL::SigSpec signal)
2449 {
2450 auto conn_it = connections_.find(portname);
2451
2452 if (conn_it == connections_.end()) {
2453 connections_[portname] = RTLIL::SigSpec();
2454 conn_it = connections_.find(portname);
2455 log_assert(conn_it != connections_.end());
2456 } else
2457 if (conn_it->second == signal)
2458 return;
2459
2460 for (auto mon : module->monitors)
2461 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
2462
2463 if (module->design)
2464 for (auto mon : module->design->monitors)
2465 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
2466
2467 if (yosys_xtrace) {
2468 log("#X# Connect %s.%s.%s = %s (%d)\n", log_id(this->module), log_id(this), log_id(portname), log_signal(signal), GetSize(signal));
2469 log_backtrace("-X- ", yosys_xtrace-1);
2470 }
2471
2472 conn_it->second = signal;
2473 }
2474
2475 const RTLIL::SigSpec &RTLIL::Cell::getPort(RTLIL::IdString portname) const
2476 {
2477 return connections_.at(portname);
2478 }
2479
2480 const dict<RTLIL::IdString, RTLIL::SigSpec> &RTLIL::Cell::connections() const
2481 {
2482 return connections_;
2483 }
2484
2485 bool RTLIL::Cell::known() const
2486 {
2487 if (yosys_celltypes.cell_known(type))
2488 return true;
2489 if (module && module->design && module->design->module(type))
2490 return true;
2491 return false;
2492 }
2493
2494 bool RTLIL::Cell::input(RTLIL::IdString portname) const
2495 {
2496 if (yosys_celltypes.cell_known(type))
2497 return yosys_celltypes.cell_input(type, portname);
2498 if (module && module->design) {
2499 RTLIL::Module *m = module->design->module(type);
2500 RTLIL::Wire *w = m ? m->wire(portname) : nullptr;
2501 return w && w->port_input;
2502 }
2503 return false;
2504 }
2505
2506 bool RTLIL::Cell::output(RTLIL::IdString portname) const
2507 {
2508 if (yosys_celltypes.cell_known(type))
2509 return yosys_celltypes.cell_output(type, portname);
2510 if (module && module->design) {
2511 RTLIL::Module *m = module->design->module(type);
2512 RTLIL::Wire *w = m ? m->wire(portname) : nullptr;
2513 return w && w->port_output;
2514 }
2515 return false;
2516 }
2517
2518 bool RTLIL::Cell::hasParam(RTLIL::IdString paramname) const
2519 {
2520 return parameters.count(paramname) != 0;
2521 }
2522
2523 void RTLIL::Cell::unsetParam(RTLIL::IdString paramname)
2524 {
2525 parameters.erase(paramname);
2526 }
2527
2528 void RTLIL::Cell::setParam(RTLIL::IdString paramname, RTLIL::Const value)
2529 {
2530 parameters[paramname] = value;
2531 }
2532
2533 const RTLIL::Const &RTLIL::Cell::getParam(RTLIL::IdString paramname) const
2534 {
2535 return parameters.at(paramname);
2536 }
2537
2538 void RTLIL::Cell::sort()
2539 {
2540 connections_.sort(sort_by_id_str());
2541 parameters.sort(sort_by_id_str());
2542 attributes.sort(sort_by_id_str());
2543 }
2544
2545 void RTLIL::Cell::check()
2546 {
2547 #ifndef NDEBUG
2548 InternalCellChecker checker(NULL, this);
2549 checker.check();
2550 #endif
2551 }
2552
2553 void RTLIL::Cell::fixup_parameters(bool set_a_signed, bool set_b_signed)
2554 {
2555 if (type.substr(0, 1) != "$" || type.substr(0, 2) == "$_" || type.substr(0, 8) == "$paramod" || type.substr(0,10) == "$fmcombine" ||
2556 type.substr(0, 9) == "$verific$" || type.substr(0, 7) == "$array:" || type.substr(0, 8) == "$extern:")
2557 return;
2558
2559 if (type == "$mux" || type == "$pmux") {
2560 parameters["\\WIDTH"] = GetSize(connections_["\\Y"]);
2561 if (type == "$pmux")
2562 parameters["\\S_WIDTH"] = GetSize(connections_["\\S"]);
2563 check();
2564 return;
2565 }
2566
2567 if (type == "$lut" || type == "$sop") {
2568 parameters["\\WIDTH"] = GetSize(connections_["\\A"]);
2569 return;
2570 }
2571
2572 if (type == "$fa") {
2573 parameters["\\WIDTH"] = GetSize(connections_["\\Y"]);
2574 return;
2575 }
2576
2577 if (type == "$lcu") {
2578 parameters["\\WIDTH"] = GetSize(connections_["\\CO"]);
2579 return;
2580 }
2581
2582 bool signedness_ab = !type.in("$slice", "$concat", "$macc");
2583
2584 if (connections_.count("\\A")) {
2585 if (signedness_ab) {
2586 if (set_a_signed)
2587 parameters["\\A_SIGNED"] = true;
2588 else if (parameters.count("\\A_SIGNED") == 0)
2589 parameters["\\A_SIGNED"] = false;
2590 }
2591 parameters["\\A_WIDTH"] = GetSize(connections_["\\A"]);
2592 }
2593
2594 if (connections_.count("\\B")) {
2595 if (signedness_ab) {
2596 if (set_b_signed)
2597 parameters["\\B_SIGNED"] = true;
2598 else if (parameters.count("\\B_SIGNED") == 0)
2599 parameters["\\B_SIGNED"] = false;
2600 }
2601 parameters["\\B_WIDTH"] = GetSize(connections_["\\B"]);
2602 }
2603
2604 if (connections_.count("\\Y"))
2605 parameters["\\Y_WIDTH"] = GetSize(connections_["\\Y"]);
2606
2607 if (connections_.count("\\Q"))
2608 parameters["\\WIDTH"] = GetSize(connections_["\\Q"]);
2609
2610 check();
2611 }
2612
2613 RTLIL::SigChunk::SigChunk()
2614 {
2615 wire = NULL;
2616 width = 0;
2617 offset = 0;
2618 }
2619
2620 RTLIL::SigChunk::SigChunk(const RTLIL::Const &value)
2621 {
2622 wire = NULL;
2623 data = value.bits;
2624 width = GetSize(data);
2625 offset = 0;
2626 }
2627
2628 RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire)
2629 {
2630 log_assert(wire != nullptr);
2631 this->wire = wire;
2632 this->width = wire->width;
2633 this->offset = 0;
2634 }
2635
2636 RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire, int offset, int width)
2637 {
2638 log_assert(wire != nullptr);
2639 this->wire = wire;
2640 this->width = width;
2641 this->offset = offset;
2642 }
2643
2644 RTLIL::SigChunk::SigChunk(const std::string &str)
2645 {
2646 wire = NULL;
2647 data = RTLIL::Const(str).bits;
2648 width = GetSize(data);
2649 offset = 0;
2650 }
2651
2652 RTLIL::SigChunk::SigChunk(int val, int width)
2653 {
2654 wire = NULL;
2655 data = RTLIL::Const(val, width).bits;
2656 this->width = GetSize(data);
2657 offset = 0;
2658 }
2659
2660 RTLIL::SigChunk::SigChunk(RTLIL::State bit, int width)
2661 {
2662 wire = NULL;
2663 data = RTLIL::Const(bit, width).bits;
2664 this->width = GetSize(data);
2665 offset = 0;
2666 }
2667
2668 RTLIL::SigChunk::SigChunk(RTLIL::SigBit bit)
2669 {
2670 wire = bit.wire;
2671 offset = 0;
2672 if (wire == NULL)
2673 data = RTLIL::Const(bit.data).bits;
2674 else
2675 offset = bit.offset;
2676 width = 1;
2677 }
2678
2679 RTLIL::SigChunk::SigChunk(const RTLIL::SigChunk &sigchunk) : data(sigchunk.data)
2680 {
2681 wire = sigchunk.wire;
2682 data = sigchunk.data;
2683 width = sigchunk.width;
2684 offset = sigchunk.offset;
2685 }
2686
2687 RTLIL::SigChunk RTLIL::SigChunk::extract(int offset, int length) const
2688 {
2689 RTLIL::SigChunk ret;
2690 if (wire) {
2691 ret.wire = wire;
2692 ret.offset = this->offset + offset;
2693 ret.width = length;
2694 } else {
2695 for (int i = 0; i < length; i++)
2696 ret.data.push_back(data[offset+i]);
2697 ret.width = length;
2698 }
2699 return ret;
2700 }
2701
2702 bool RTLIL::SigChunk::operator <(const RTLIL::SigChunk &other) const
2703 {
2704 if (wire && other.wire)
2705 if (wire->name != other.wire->name)
2706 return wire->name < other.wire->name;
2707
2708 if (wire != other.wire)
2709 return wire < other.wire;
2710
2711 if (offset != other.offset)
2712 return offset < other.offset;
2713
2714 if (width != other.width)
2715 return width < other.width;
2716
2717 return data < other.data;
2718 }
2719
2720 bool RTLIL::SigChunk::operator ==(const RTLIL::SigChunk &other) const
2721 {
2722 return wire == other.wire && width == other.width && offset == other.offset && data == other.data;
2723 }
2724
2725 bool RTLIL::SigChunk::operator !=(const RTLIL::SigChunk &other) const
2726 {
2727 if (*this == other)
2728 return false;
2729 return true;
2730 }
2731
2732 RTLIL::SigSpec::SigSpec()
2733 {
2734 width_ = 0;
2735 hash_ = 0;
2736 }
2737
2738 RTLIL::SigSpec::SigSpec(const RTLIL::SigSpec &other)
2739 {
2740 *this = other;
2741 }
2742
2743 RTLIL::SigSpec::SigSpec(std::initializer_list<RTLIL::SigSpec> parts)
2744 {
2745 cover("kernel.rtlil.sigspec.init.list");
2746
2747 width_ = 0;
2748 hash_ = 0;
2749
2750 std::vector<RTLIL::SigSpec> parts_vec(parts.begin(), parts.end());
2751 for (auto it = parts_vec.rbegin(); it != parts_vec.rend(); it++)
2752 append(*it);
2753 }
2754
2755 const RTLIL::SigSpec &RTLIL::SigSpec::operator=(const RTLIL::SigSpec &other)
2756 {
2757 cover("kernel.rtlil.sigspec.assign");
2758
2759 width_ = other.width_;
2760 hash_ = other.hash_;
2761 chunks_ = other.chunks_;
2762 bits_.clear();
2763
2764 if (!other.bits_.empty())
2765 {
2766 RTLIL::SigChunk *last = NULL;
2767 int last_end_offset = 0;
2768
2769 for (auto &bit : other.bits_) {
2770 if (last && bit.wire == last->wire) {
2771 if (bit.wire == NULL) {
2772 last->data.push_back(bit.data);
2773 last->width++;
2774 continue;
2775 } else if (last_end_offset == bit.offset) {
2776 last_end_offset++;
2777 last->width++;
2778 continue;
2779 }
2780 }
2781 chunks_.push_back(bit);
2782 last = &chunks_.back();
2783 last_end_offset = bit.offset + 1;
2784 }
2785
2786 check();
2787 }
2788
2789 return *this;
2790 }
2791
2792 RTLIL::SigSpec::SigSpec(const RTLIL::Const &value)
2793 {
2794 cover("kernel.rtlil.sigspec.init.const");
2795
2796 chunks_.push_back(RTLIL::SigChunk(value));
2797 width_ = chunks_.back().width;
2798 hash_ = 0;
2799 check();
2800 }
2801
2802 RTLIL::SigSpec::SigSpec(const RTLIL::SigChunk &chunk)
2803 {
2804 cover("kernel.rtlil.sigspec.init.chunk");
2805
2806 chunks_.push_back(chunk);
2807 width_ = chunks_.back().width;
2808 hash_ = 0;
2809 check();
2810 }
2811
2812 RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire)
2813 {
2814 cover("kernel.rtlil.sigspec.init.wire");
2815
2816 chunks_.push_back(RTLIL::SigChunk(wire));
2817 width_ = chunks_.back().width;
2818 hash_ = 0;
2819 check();
2820 }
2821
2822 RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire, int offset, int width)
2823 {
2824 cover("kernel.rtlil.sigspec.init.wire_part");
2825
2826 chunks_.push_back(RTLIL::SigChunk(wire, offset, width));
2827 width_ = chunks_.back().width;
2828 hash_ = 0;
2829 check();
2830 }
2831
2832 RTLIL::SigSpec::SigSpec(const std::string &str)
2833 {
2834 cover("kernel.rtlil.sigspec.init.str");
2835
2836 chunks_.push_back(RTLIL::SigChunk(str));
2837 width_ = chunks_.back().width;
2838 hash_ = 0;
2839 check();
2840 }
2841
2842 RTLIL::SigSpec::SigSpec(int val, int width)
2843 {
2844 cover("kernel.rtlil.sigspec.init.int");
2845
2846 chunks_.push_back(RTLIL::SigChunk(val, width));
2847 width_ = width;
2848 hash_ = 0;
2849 check();
2850 }
2851
2852 RTLIL::SigSpec::SigSpec(RTLIL::State bit, int width)
2853 {
2854 cover("kernel.rtlil.sigspec.init.state");
2855
2856 chunks_.push_back(RTLIL::SigChunk(bit, width));
2857 width_ = width;
2858 hash_ = 0;
2859 check();
2860 }
2861
2862 RTLIL::SigSpec::SigSpec(RTLIL::SigBit bit, int width)
2863 {
2864 cover("kernel.rtlil.sigspec.init.bit");
2865
2866 if (bit.wire == NULL)
2867 chunks_.push_back(RTLIL::SigChunk(bit.data, width));
2868 else
2869 for (int i = 0; i < width; i++)
2870 chunks_.push_back(bit);
2871 width_ = width;
2872 hash_ = 0;
2873 check();
2874 }
2875
2876 RTLIL::SigSpec::SigSpec(std::vector<RTLIL::SigChunk> chunks)
2877 {
2878 cover("kernel.rtlil.sigspec.init.stdvec_chunks");
2879
2880 width_ = 0;
2881 hash_ = 0;
2882 for (auto &c : chunks)
2883 append(c);
2884 check();
2885 }
2886
2887 RTLIL::SigSpec::SigSpec(std::vector<RTLIL::SigBit> bits)
2888 {
2889 cover("kernel.rtlil.sigspec.init.stdvec_bits");
2890
2891 width_ = 0;
2892 hash_ = 0;
2893 for (auto &bit : bits)
2894 append_bit(bit);
2895 check();
2896 }
2897
2898 RTLIL::SigSpec::SigSpec(pool<RTLIL::SigBit> bits)
2899 {
2900 cover("kernel.rtlil.sigspec.init.pool_bits");
2901
2902 width_ = 0;
2903 hash_ = 0;
2904 for (auto &bit : bits)
2905 append_bit(bit);
2906 check();
2907 }
2908
2909 RTLIL::SigSpec::SigSpec(std::set<RTLIL::SigBit> bits)
2910 {
2911 cover("kernel.rtlil.sigspec.init.stdset_bits");
2912
2913 width_ = 0;
2914 hash_ = 0;
2915 for (auto &bit : bits)
2916 append_bit(bit);
2917 check();
2918 }
2919
2920 RTLIL::SigSpec::SigSpec(bool bit)
2921 {
2922 cover("kernel.rtlil.sigspec.init.bool");
2923
2924 width_ = 0;
2925 hash_ = 0;
2926 append_bit(bit);
2927 check();
2928 }
2929
2930 void RTLIL::SigSpec::pack() const
2931 {
2932 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
2933
2934 if (that->bits_.empty())
2935 return;
2936
2937 cover("kernel.rtlil.sigspec.convert.pack");
2938 log_assert(that->chunks_.empty());
2939
2940 std::vector<RTLIL::SigBit> old_bits;
2941 old_bits.swap(that->bits_);
2942
2943 RTLIL::SigChunk *last = NULL;
2944 int last_end_offset = 0;
2945
2946 for (auto &bit : old_bits) {
2947 if (last && bit.wire == last->wire) {
2948 if (bit.wire == NULL) {
2949 last->data.push_back(bit.data);
2950 last->width++;
2951 continue;
2952 } else if (last_end_offset == bit.offset) {
2953 last_end_offset++;
2954 last->width++;
2955 continue;
2956 }
2957 }
2958 that->chunks_.push_back(bit);
2959 last = &that->chunks_.back();
2960 last_end_offset = bit.offset + 1;
2961 }
2962
2963 check();
2964 }
2965
2966 void RTLIL::SigSpec::unpack() const
2967 {
2968 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
2969
2970 if (that->chunks_.empty())
2971 return;
2972
2973 cover("kernel.rtlil.sigspec.convert.unpack");
2974 log_assert(that->bits_.empty());
2975
2976 that->bits_.reserve(that->width_);
2977 for (auto &c : that->chunks_)
2978 for (int i = 0; i < c.width; i++)
2979 that->bits_.push_back(RTLIL::SigBit(c, i));
2980
2981 that->chunks_.clear();
2982 that->hash_ = 0;
2983 }
2984
2985 void RTLIL::SigSpec::updhash() const
2986 {
2987 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
2988
2989 if (that->hash_ != 0)
2990 return;
2991
2992 cover("kernel.rtlil.sigspec.hash");
2993 that->pack();
2994
2995 that->hash_ = mkhash_init;
2996 for (auto &c : that->chunks_)
2997 if (c.wire == NULL) {
2998 for (auto &v : c.data)
2999 that->hash_ = mkhash(that->hash_, v);
3000 } else {
3001 that->hash_ = mkhash(that->hash_, c.wire->name.index_);
3002 that->hash_ = mkhash(that->hash_, c.offset);
3003 that->hash_ = mkhash(that->hash_, c.width);
3004 }
3005
3006 if (that->hash_ == 0)
3007 that->hash_ = 1;
3008 }
3009
3010 void RTLIL::SigSpec::sort()
3011 {
3012 unpack();
3013 cover("kernel.rtlil.sigspec.sort");
3014 std::sort(bits_.begin(), bits_.end());
3015 }
3016
3017 void RTLIL::SigSpec::sort_and_unify()
3018 {
3019 unpack();
3020 cover("kernel.rtlil.sigspec.sort_and_unify");
3021
3022 // A copy of the bits vector is used to prevent duplicating the logic from
3023 // SigSpec::SigSpec(std::vector<SigBit>). This incurrs an extra copy but
3024 // that isn't showing up as significant in profiles.
3025 std::vector<SigBit> unique_bits = bits_;
3026 std::sort(unique_bits.begin(), unique_bits.end());
3027 auto last = std::unique(unique_bits.begin(), unique_bits.end());
3028 unique_bits.erase(last, unique_bits.end());
3029
3030 *this = unique_bits;
3031 }
3032
3033 void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with)
3034 {
3035 replace(pattern, with, this);
3036 }
3037
3038 void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with, RTLIL::SigSpec *other) const
3039 {
3040 log_assert(other != NULL);
3041 log_assert(width_ == other->width_);
3042 log_assert(pattern.width_ == with.width_);
3043
3044 pattern.unpack();
3045 with.unpack();
3046 unpack();
3047 other->unpack();
3048
3049 for (int i = 0; i < GetSize(pattern.bits_); i++) {
3050 if (pattern.bits_[i].wire != NULL) {
3051 for (int j = 0; j < GetSize(bits_); j++) {
3052 if (bits_[j] == pattern.bits_[i]) {
3053 other->bits_[j] = with.bits_[i];
3054 }
3055 }
3056 }
3057 }
3058
3059 other->check();
3060 }
3061
3062 void RTLIL::SigSpec::replace(const dict<RTLIL::SigBit, RTLIL::SigBit> &rules)
3063 {
3064 replace(rules, this);
3065 }
3066
3067 void RTLIL::SigSpec::replace(const dict<RTLIL::SigBit, RTLIL::SigBit> &rules, RTLIL::SigSpec *other) const
3068 {
3069 cover("kernel.rtlil.sigspec.replace_dict");
3070
3071 log_assert(other != NULL);
3072 log_assert(width_ == other->width_);
3073
3074 unpack();
3075 other->unpack();
3076
3077 for (int i = 0; i < GetSize(bits_); i++) {
3078 auto it = rules.find(bits_[i]);
3079 if (it != rules.end())
3080 other->bits_[i] = it->second;
3081 }
3082
3083 other->check();
3084 }
3085
3086 void RTLIL::SigSpec::replace(const std::map<RTLIL::SigBit, RTLIL::SigBit> &rules)
3087 {
3088 replace(rules, this);
3089 }
3090
3091 void RTLIL::SigSpec::replace(const std::map<RTLIL::SigBit, RTLIL::SigBit> &rules, RTLIL::SigSpec *other) const
3092 {
3093 cover("kernel.rtlil.sigspec.replace_map");
3094
3095 log_assert(other != NULL);
3096 log_assert(width_ == other->width_);
3097
3098 unpack();
3099 other->unpack();
3100
3101 for (int i = 0; i < GetSize(bits_); i++) {
3102 auto it = rules.find(bits_[i]);
3103 if (it != rules.end())
3104 other->bits_[i] = it->second;
3105 }
3106
3107 other->check();
3108 }
3109
3110 void RTLIL::SigSpec::remove(const RTLIL::SigSpec &pattern)
3111 {
3112 remove2(pattern, NULL);
3113 }
3114
3115 void RTLIL::SigSpec::remove(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other) const
3116 {
3117 RTLIL::SigSpec tmp = *this;
3118 tmp.remove2(pattern, other);
3119 }
3120
3121 void RTLIL::SigSpec::remove2(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other)
3122 {
3123 if (other)
3124 cover("kernel.rtlil.sigspec.remove_other");
3125 else
3126 cover("kernel.rtlil.sigspec.remove");
3127
3128 unpack();
3129 if (other != NULL) {
3130 log_assert(width_ == other->width_);
3131 other->unpack();
3132 }
3133
3134 for (int i = GetSize(bits_) - 1; i >= 0; i--)
3135 {
3136 if (bits_[i].wire == NULL) continue;
3137
3138 for (auto &pattern_chunk : pattern.chunks())
3139 if (bits_[i].wire == pattern_chunk.wire &&
3140 bits_[i].offset >= pattern_chunk.offset &&
3141 bits_[i].offset < pattern_chunk.offset + pattern_chunk.width) {
3142 bits_.erase(bits_.begin() + i);
3143 width_--;
3144 if (other != NULL) {
3145 other->bits_.erase(other->bits_.begin() + i);
3146 other->width_--;
3147 }
3148 break;
3149 }
3150 }
3151
3152 check();
3153 }
3154
3155 void RTLIL::SigSpec::remove(const pool<RTLIL::SigBit> &pattern)
3156 {
3157 remove2(pattern, NULL);
3158 }
3159
3160 void RTLIL::SigSpec::remove(const pool<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other) const
3161 {
3162 RTLIL::SigSpec tmp = *this;
3163 tmp.remove2(pattern, other);
3164 }
3165
3166 void RTLIL::SigSpec::remove2(const pool<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other)
3167 {
3168 if (other)
3169 cover("kernel.rtlil.sigspec.remove_other");
3170 else
3171 cover("kernel.rtlil.sigspec.remove");
3172
3173 unpack();
3174
3175 if (other != NULL) {
3176 log_assert(width_ == other->width_);
3177 other->unpack();
3178 }
3179
3180 for (int i = GetSize(bits_) - 1; i >= 0; i--) {
3181 if (bits_[i].wire != NULL && pattern.count(bits_[i])) {
3182 bits_.erase(bits_.begin() + i);
3183 width_--;
3184 if (other != NULL) {
3185 other->bits_.erase(other->bits_.begin() + i);
3186 other->width_--;
3187 }
3188 }
3189 }
3190
3191 check();
3192 }
3193
3194 void RTLIL::SigSpec::remove2(const std::set<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other)
3195 {
3196 if (other)
3197 cover("kernel.rtlil.sigspec.remove_other");
3198 else
3199 cover("kernel.rtlil.sigspec.remove");
3200
3201 unpack();
3202
3203 if (other != NULL) {
3204 log_assert(width_ == other->width_);
3205 other->unpack();
3206 }
3207
3208 for (int i = GetSize(bits_) - 1; i >= 0; i--) {
3209 if (bits_[i].wire != NULL && pattern.count(bits_[i])) {
3210 bits_.erase(bits_.begin() + i);
3211 width_--;
3212 if (other != NULL) {
3213 other->bits_.erase(other->bits_.begin() + i);
3214 other->width_--;
3215 }
3216 }
3217 }
3218
3219 check();
3220 }
3221
3222 RTLIL::SigSpec RTLIL::SigSpec::extract(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec *other) const
3223 {
3224 if (other)
3225 cover("kernel.rtlil.sigspec.extract_other");
3226 else
3227 cover("kernel.rtlil.sigspec.extract");
3228
3229 log_assert(other == NULL || width_ == other->width_);
3230
3231 RTLIL::SigSpec ret;
3232 std::vector<RTLIL::SigBit> bits_match = to_sigbit_vector();
3233
3234 for (auto& pattern_chunk : pattern.chunks()) {
3235 if (other) {
3236 std::vector<RTLIL::SigBit> bits_other = other->to_sigbit_vector();
3237 for (int i = 0; i < width_; i++)
3238 if (bits_match[i].wire &&
3239 bits_match[i].wire == pattern_chunk.wire &&
3240 bits_match[i].offset >= pattern_chunk.offset &&
3241 bits_match[i].offset < pattern_chunk.offset + pattern_chunk.width)
3242 ret.append_bit(bits_other[i]);
3243 } else {
3244 for (int i = 0; i < width_; i++)
3245 if (bits_match[i].wire &&
3246 bits_match[i].wire == pattern_chunk.wire &&
3247 bits_match[i].offset >= pattern_chunk.offset &&
3248 bits_match[i].offset < pattern_chunk.offset + pattern_chunk.width)
3249 ret.append_bit(bits_match[i]);
3250 }
3251 }
3252
3253 ret.check();
3254 return ret;
3255 }
3256
3257 RTLIL::SigSpec RTLIL::SigSpec::extract(const pool<RTLIL::SigBit> &pattern, const RTLIL::SigSpec *other) const
3258 {
3259 if (other)
3260 cover("kernel.rtlil.sigspec.extract_other");
3261 else
3262 cover("kernel.rtlil.sigspec.extract");
3263
3264 log_assert(other == NULL || width_ == other->width_);
3265
3266 std::vector<RTLIL::SigBit> bits_match = to_sigbit_vector();
3267 RTLIL::SigSpec ret;
3268
3269 if (other) {
3270 std::vector<RTLIL::SigBit> bits_other = other->to_sigbit_vector();
3271 for (int i = 0; i < width_; i++)
3272 if (bits_match[i].wire && pattern.count(bits_match[i]))
3273 ret.append_bit(bits_other[i]);
3274 } else {
3275 for (int i = 0; i < width_; i++)
3276 if (bits_match[i].wire && pattern.count(bits_match[i]))
3277 ret.append_bit(bits_match[i]);
3278 }
3279
3280 ret.check();
3281 return ret;
3282 }
3283
3284 void RTLIL::SigSpec::replace(int offset, const RTLIL::SigSpec &with)
3285 {
3286 cover("kernel.rtlil.sigspec.replace_pos");
3287
3288 unpack();
3289 with.unpack();
3290
3291 log_assert(offset >= 0);
3292 log_assert(with.width_ >= 0);
3293 log_assert(offset+with.width_ <= width_);
3294
3295 for (int i = 0; i < with.width_; i++)
3296 bits_.at(offset + i) = with.bits_.at(i);
3297
3298 check();
3299 }
3300
3301 void RTLIL::SigSpec::remove_const()
3302 {
3303 if (packed())
3304 {
3305 cover("kernel.rtlil.sigspec.remove_const.packed");
3306
3307 std::vector<RTLIL::SigChunk> new_chunks;
3308 new_chunks.reserve(GetSize(chunks_));
3309
3310 width_ = 0;
3311 for (auto &chunk : chunks_)
3312 if (chunk.wire != NULL) {
3313 new_chunks.push_back(chunk);
3314 width_ += chunk.width;
3315 }
3316
3317 chunks_.swap(new_chunks);
3318 }
3319 else
3320 {
3321 cover("kernel.rtlil.sigspec.remove_const.unpacked");
3322
3323 std::vector<RTLIL::SigBit> new_bits;
3324 new_bits.reserve(width_);
3325
3326 for (auto &bit : bits_)
3327 if (bit.wire != NULL)
3328 new_bits.push_back(bit);
3329
3330 bits_.swap(new_bits);
3331 width_ = bits_.size();
3332 }
3333
3334 check();
3335 }
3336
3337 void RTLIL::SigSpec::remove(int offset, int length)
3338 {
3339 cover("kernel.rtlil.sigspec.remove_pos");
3340
3341 unpack();
3342
3343 log_assert(offset >= 0);
3344 log_assert(length >= 0);
3345 log_assert(offset + length <= width_);
3346
3347 bits_.erase(bits_.begin() + offset, bits_.begin() + offset + length);
3348 width_ = bits_.size();
3349
3350 check();
3351 }
3352
3353 RTLIL::SigSpec RTLIL::SigSpec::extract(int offset, int length) const
3354 {
3355 unpack();
3356 cover("kernel.rtlil.sigspec.extract_pos");
3357 return std::vector<RTLIL::SigBit>(bits_.begin() + offset, bits_.begin() + offset + length);
3358 }
3359
3360 void RTLIL::SigSpec::append(const RTLIL::SigSpec &signal)
3361 {
3362 if (signal.width_ == 0)
3363 return;
3364
3365 if (width_ == 0) {
3366 *this = signal;
3367 return;
3368 }
3369
3370 cover("kernel.rtlil.sigspec.append");
3371
3372 if (packed() != signal.packed()) {
3373 pack();
3374 signal.pack();
3375 }
3376
3377 if (packed())
3378 for (auto &other_c : signal.chunks_)
3379 {
3380 auto &my_last_c = chunks_.back();
3381 if (my_last_c.wire == NULL && other_c.wire == NULL) {
3382 auto &this_data = my_last_c.data;
3383 auto &other_data = other_c.data;
3384 this_data.insert(this_data.end(), other_data.begin(), other_data.end());
3385 my_last_c.width += other_c.width;
3386 } else
3387 if (my_last_c.wire == other_c.wire && my_last_c.offset + my_last_c.width == other_c.offset) {
3388 my_last_c.width += other_c.width;
3389 } else
3390 chunks_.push_back(other_c);
3391 }
3392 else
3393 bits_.insert(bits_.end(), signal.bits_.begin(), signal.bits_.end());
3394
3395 width_ += signal.width_;
3396 check();
3397 }
3398
3399 void RTLIL::SigSpec::append_bit(const RTLIL::SigBit &bit)
3400 {
3401 if (packed())
3402 {
3403 cover("kernel.rtlil.sigspec.append_bit.packed");
3404
3405 if (chunks_.size() == 0)
3406 chunks_.push_back(bit);
3407 else
3408 if (bit.wire == NULL)
3409 if (chunks_.back().wire == NULL) {
3410 chunks_.back().data.push_back(bit.data);
3411 chunks_.back().width++;
3412 } else
3413 chunks_.push_back(bit);
3414 else
3415 if (chunks_.back().wire == bit.wire && chunks_.back().offset + chunks_.back().width == bit.offset)
3416 chunks_.back().width++;
3417 else
3418 chunks_.push_back(bit);
3419 }
3420 else
3421 {
3422 cover("kernel.rtlil.sigspec.append_bit.unpacked");
3423 bits_.push_back(bit);
3424 }
3425
3426 width_++;
3427 check();
3428 }
3429
3430 void RTLIL::SigSpec::extend_u0(int width, bool is_signed)
3431 {
3432 cover("kernel.rtlil.sigspec.extend_u0");
3433
3434 pack();
3435
3436 if (width_ > width)
3437 remove(width, width_ - width);
3438
3439 if (width_ < width) {
3440 RTLIL::SigBit padding = width_ > 0 ? (*this)[width_ - 1] : RTLIL::State::Sx;
3441 if (!is_signed)
3442 padding = RTLIL::State::S0;
3443 while (width_ < width)
3444 append(padding);
3445 }
3446
3447 }
3448
3449 RTLIL::SigSpec RTLIL::SigSpec::repeat(int num) const
3450 {
3451 cover("kernel.rtlil.sigspec.repeat");
3452
3453 RTLIL::SigSpec sig;
3454 for (int i = 0; i < num; i++)
3455 sig.append(*this);
3456 return sig;
3457 }
3458
3459 #ifndef NDEBUG
3460 void RTLIL::SigSpec::check() const
3461 {
3462 if (width_ > 64)
3463 {
3464 cover("kernel.rtlil.sigspec.check.skip");
3465 }
3466 else if (packed())
3467 {
3468 cover("kernel.rtlil.sigspec.check.packed");
3469
3470 int w = 0;
3471 for (size_t i = 0; i < chunks_.size(); i++) {
3472 const RTLIL::SigChunk chunk = chunks_[i];
3473 if (chunk.wire == NULL) {
3474 if (i > 0)
3475 log_assert(chunks_[i-1].wire != NULL);
3476 log_assert(chunk.offset == 0);
3477 log_assert(chunk.data.size() == (size_t)chunk.width);
3478 } else {
3479 if (i > 0 && chunks_[i-1].wire == chunk.wire)
3480 log_assert(chunk.offset != chunks_[i-1].offset + chunks_[i-1].width);
3481 log_assert(chunk.offset >= 0);
3482 log_assert(chunk.width >= 0);
3483 log_assert(chunk.offset + chunk.width <= chunk.wire->width);
3484 log_assert(chunk.data.size() == 0);
3485 }
3486 w += chunk.width;
3487 }
3488 log_assert(w == width_);
3489 log_assert(bits_.empty());
3490 }
3491 else
3492 {
3493 cover("kernel.rtlil.sigspec.check.unpacked");
3494
3495 log_assert(width_ == GetSize(bits_));
3496 log_assert(chunks_.empty());
3497 }
3498 }
3499 #endif
3500
3501 bool RTLIL::SigSpec::operator <(const RTLIL::SigSpec &other) const
3502 {
3503 cover("kernel.rtlil.sigspec.comp_lt");
3504
3505 if (this == &other)
3506 return false;
3507
3508 if (width_ != other.width_)
3509 return width_ < other.width_;
3510
3511 pack();
3512 other.pack();
3513
3514 if (chunks_.size() != other.chunks_.size())
3515 return chunks_.size() < other.chunks_.size();
3516
3517 updhash();
3518 other.updhash();
3519
3520 if (hash_ != other.hash_)
3521 return hash_ < other.hash_;
3522
3523 for (size_t i = 0; i < chunks_.size(); i++)
3524 if (chunks_[i] != other.chunks_[i]) {
3525 cover("kernel.rtlil.sigspec.comp_lt.hash_collision");
3526 return chunks_[i] < other.chunks_[i];
3527 }
3528
3529 cover("kernel.rtlil.sigspec.comp_lt.equal");
3530 return false;
3531 }
3532
3533 bool RTLIL::SigSpec::operator ==(const RTLIL::SigSpec &other) const
3534 {
3535 cover("kernel.rtlil.sigspec.comp_eq");
3536
3537 if (this == &other)
3538 return true;
3539
3540 if (width_ != other.width_)
3541 return false;
3542
3543 pack();
3544 other.pack();
3545
3546 if (chunks_.size() != other.chunks_.size())
3547 return false;
3548
3549 updhash();
3550 other.updhash();
3551
3552 if (hash_ != other.hash_)
3553 return false;
3554
3555 for (size_t i = 0; i < chunks_.size(); i++)
3556 if (chunks_[i] != other.chunks_[i]) {
3557 cover("kernel.rtlil.sigspec.comp_eq.hash_collision");
3558 return false;
3559 }
3560
3561 cover("kernel.rtlil.sigspec.comp_eq.equal");
3562 return true;
3563 }
3564
3565 bool RTLIL::SigSpec::is_wire() const
3566 {
3567 cover("kernel.rtlil.sigspec.is_wire");
3568
3569 pack();
3570 return GetSize(chunks_) == 1 && chunks_[0].wire && chunks_[0].wire->width == width_;
3571 }
3572
3573 bool RTLIL::SigSpec::is_chunk() const
3574 {
3575 cover("kernel.rtlil.sigspec.is_chunk");
3576
3577 pack();
3578 return GetSize(chunks_) == 1;
3579 }
3580
3581 bool RTLIL::SigSpec::is_fully_const() const
3582 {
3583 cover("kernel.rtlil.sigspec.is_fully_const");
3584
3585 pack();
3586 for (auto it = chunks_.begin(); it != chunks_.end(); it++)
3587 if (it->width > 0 && it->wire != NULL)
3588 return false;
3589 return true;
3590 }
3591
3592 bool RTLIL::SigSpec::is_fully_zero() const
3593 {
3594 cover("kernel.rtlil.sigspec.is_fully_zero");
3595
3596 pack();
3597 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
3598 if (it->width > 0 && it->wire != NULL)
3599 return false;
3600 for (size_t i = 0; i < it->data.size(); i++)
3601 if (it->data[i] != RTLIL::State::S0)
3602 return false;
3603 }
3604 return true;
3605 }
3606
3607 bool RTLIL::SigSpec::is_fully_ones() const
3608 {
3609 cover("kernel.rtlil.sigspec.is_fully_ones");
3610
3611 pack();
3612 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
3613 if (it->width > 0 && it->wire != NULL)
3614 return false;
3615 for (size_t i = 0; i < it->data.size(); i++)
3616 if (it->data[i] != RTLIL::State::S1)
3617 return false;
3618 }
3619 return true;
3620 }
3621
3622 bool RTLIL::SigSpec::is_fully_def() const
3623 {
3624 cover("kernel.rtlil.sigspec.is_fully_def");
3625
3626 pack();
3627 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
3628 if (it->width > 0 && it->wire != NULL)
3629 return false;
3630 for (size_t i = 0; i < it->data.size(); i++)
3631 if (it->data[i] != RTLIL::State::S0 && it->data[i] != RTLIL::State::S1)
3632 return false;
3633 }
3634 return true;
3635 }
3636
3637 bool RTLIL::SigSpec::is_fully_undef() const
3638 {
3639 cover("kernel.rtlil.sigspec.is_fully_undef");
3640
3641 pack();
3642 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
3643 if (it->width > 0 && it->wire != NULL)
3644 return false;
3645 for (size_t i = 0; i < it->data.size(); i++)
3646 if (it->data[i] != RTLIL::State::Sx && it->data[i] != RTLIL::State::Sz)
3647 return false;
3648 }
3649 return true;
3650 }
3651
3652 bool RTLIL::SigSpec::has_const() const
3653 {
3654 cover("kernel.rtlil.sigspec.has_const");
3655
3656 pack();
3657 for (auto it = chunks_.begin(); it != chunks_.end(); it++)
3658 if (it->width > 0 && it->wire == NULL)
3659 return true;
3660 return false;
3661 }
3662
3663 bool RTLIL::SigSpec::has_marked_bits() const
3664 {
3665 cover("kernel.rtlil.sigspec.has_marked_bits");
3666
3667 pack();
3668 for (auto it = chunks_.begin(); it != chunks_.end(); it++)
3669 if (it->width > 0 && it->wire == NULL) {
3670 for (size_t i = 0; i < it->data.size(); i++)
3671 if (it->data[i] == RTLIL::State::Sm)
3672 return true;
3673 }
3674 return false;
3675 }
3676
3677 bool RTLIL::SigSpec::as_bool() const
3678 {
3679 cover("kernel.rtlil.sigspec.as_bool");
3680
3681 pack();
3682 log_assert(is_fully_const() && GetSize(chunks_) <= 1);
3683 if (width_)
3684 return RTLIL::Const(chunks_[0].data).as_bool();
3685 return false;
3686 }
3687
3688 int RTLIL::SigSpec::as_int(bool is_signed) const
3689 {
3690 cover("kernel.rtlil.sigspec.as_int");
3691
3692 pack();
3693 log_assert(is_fully_const() && GetSize(chunks_) <= 1);
3694 if (width_)
3695 return RTLIL::Const(chunks_[0].data).as_int(is_signed);
3696 return 0;
3697 }
3698
3699 std::string RTLIL::SigSpec::as_string() const
3700 {
3701 cover("kernel.rtlil.sigspec.as_string");
3702
3703 pack();
3704 std::string str;
3705 for (size_t i = chunks_.size(); i > 0; i--) {
3706 const RTLIL::SigChunk &chunk = chunks_[i-1];
3707 if (chunk.wire != NULL)
3708 for (int j = 0; j < chunk.width; j++)
3709 str += "?";
3710 else
3711 str += RTLIL::Const(chunk.data).as_string();
3712 }
3713 return str;
3714 }
3715
3716 RTLIL::Const RTLIL::SigSpec::as_const() const
3717 {
3718 cover("kernel.rtlil.sigspec.as_const");
3719
3720 pack();
3721 log_assert(is_fully_const() && GetSize(chunks_) <= 1);
3722 if (width_)
3723 return chunks_[0].data;
3724 return RTLIL::Const();
3725 }
3726
3727 RTLIL::Wire *RTLIL::SigSpec::as_wire() const
3728 {
3729 cover("kernel.rtlil.sigspec.as_wire");
3730
3731 pack();
3732 log_assert(is_wire());
3733 return chunks_[0].wire;
3734 }
3735
3736 RTLIL::SigChunk RTLIL::SigSpec::as_chunk() const
3737 {
3738 cover("kernel.rtlil.sigspec.as_chunk");
3739
3740 pack();
3741 log_assert(is_chunk());
3742 return chunks_[0];
3743 }
3744
3745 RTLIL::SigBit RTLIL::SigSpec::as_bit() const
3746 {
3747 cover("kernel.rtlil.sigspec.as_bit");
3748
3749 log_assert(width_ == 1);
3750 if (packed())
3751 return RTLIL::SigBit(*chunks_.begin());
3752 else
3753 return bits_[0];
3754 }
3755
3756 bool RTLIL::SigSpec::match(std::string pattern) const
3757 {
3758 cover("kernel.rtlil.sigspec.match");
3759
3760 pack();
3761 std::string str = as_string();
3762 log_assert(pattern.size() == str.size());
3763
3764 for (size_t i = 0; i < pattern.size(); i++) {
3765 if (pattern[i] == ' ')
3766 continue;
3767 if (pattern[i] == '*') {
3768 if (str[i] != 'z' && str[i] != 'x')
3769 return false;
3770 continue;
3771 }
3772 if (pattern[i] != str[i])
3773 return false;
3774 }
3775
3776 return true;
3777 }
3778
3779 std::set<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_set() const
3780 {
3781 cover("kernel.rtlil.sigspec.to_sigbit_set");
3782
3783 pack();
3784 std::set<RTLIL::SigBit> sigbits;
3785 for (auto &c : chunks_)
3786 for (int i = 0; i < c.width; i++)
3787 sigbits.insert(RTLIL::SigBit(c, i));
3788 return sigbits;
3789 }
3790
3791 pool<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_pool() const
3792 {
3793 cover("kernel.rtlil.sigspec.to_sigbit_pool");
3794
3795 pack();
3796 pool<RTLIL::SigBit> sigbits;
3797 for (auto &c : chunks_)
3798 for (int i = 0; i < c.width; i++)
3799 sigbits.insert(RTLIL::SigBit(c, i));
3800 return sigbits;
3801 }
3802
3803 std::vector<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_vector() const
3804 {
3805 cover("kernel.rtlil.sigspec.to_sigbit_vector");
3806
3807 unpack();
3808 return bits_;
3809 }
3810
3811 std::map<RTLIL::SigBit, RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_map(const RTLIL::SigSpec &other) const
3812 {
3813 cover("kernel.rtlil.sigspec.to_sigbit_map");
3814
3815 unpack();
3816 other.unpack();
3817
3818 log_assert(width_ == other.width_);
3819
3820 std::map<RTLIL::SigBit, RTLIL::SigBit> new_map;
3821 for (int i = 0; i < width_; i++)
3822 new_map[bits_[i]] = other.bits_[i];
3823
3824 return new_map;
3825 }
3826
3827 dict<RTLIL::SigBit, RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_dict(const RTLIL::SigSpec &other) const
3828 {
3829 cover("kernel.rtlil.sigspec.to_sigbit_dict");
3830
3831 unpack();
3832 other.unpack();
3833
3834 log_assert(width_ == other.width_);
3835
3836 dict<RTLIL::SigBit, RTLIL::SigBit> new_map;
3837 for (int i = 0; i < width_; i++)
3838 new_map[bits_[i]] = other.bits_[i];
3839
3840 return new_map;
3841 }
3842
3843 static void sigspec_parse_split(std::vector<std::string> &tokens, const std::string &text, char sep)
3844 {
3845 size_t start = 0, end = 0;
3846 while ((end = text.find(sep, start)) != std::string::npos) {
3847 tokens.push_back(text.substr(start, end - start));
3848 start = end + 1;
3849 }
3850 tokens.push_back(text.substr(start));
3851 }
3852
3853 static int sigspec_parse_get_dummy_line_num()
3854 {
3855 return 0;
3856 }
3857
3858 bool RTLIL::SigSpec::parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str)
3859 {
3860 cover("kernel.rtlil.sigspec.parse");
3861
3862 AST::current_filename = "input";
3863 AST::use_internal_line_num();
3864 AST::set_line_num(0);
3865
3866 std::vector<std::string> tokens;
3867 sigspec_parse_split(tokens, str, ',');
3868
3869 sig = RTLIL::SigSpec();
3870 for (int tokidx = int(tokens.size())-1; tokidx >= 0; tokidx--)
3871 {
3872 std::string netname = tokens[tokidx];
3873 std::string indices;
3874
3875 if (netname.size() == 0)
3876 continue;
3877
3878 if (('0' <= netname[0] && netname[0] <= '9') || netname[0] == '\'') {
3879 cover("kernel.rtlil.sigspec.parse.const");
3880 AST::get_line_num = sigspec_parse_get_dummy_line_num;
3881 AST::AstNode *ast = VERILOG_FRONTEND::const2ast(netname);
3882 if (ast == NULL)
3883 return false;
3884 sig.append(RTLIL::Const(ast->bits));
3885 delete ast;
3886 continue;
3887 }
3888
3889 if (module == NULL)
3890 return false;
3891
3892 cover("kernel.rtlil.sigspec.parse.net");
3893
3894 if (netname[0] != '$' && netname[0] != '\\')
3895 netname = "\\" + netname;
3896
3897 if (module->wires_.count(netname) == 0) {
3898 size_t indices_pos = netname.size()-1;
3899 if (indices_pos > 2 && netname[indices_pos] == ']')
3900 {
3901 indices_pos--;
3902 while (indices_pos > 0 && ('0' <= netname[indices_pos] && netname[indices_pos] <= '9')) indices_pos--;
3903 if (indices_pos > 0 && netname[indices_pos] == ':') {
3904 indices_pos--;
3905 while (indices_pos > 0 && ('0' <= netname[indices_pos] && netname[indices_pos] <= '9')) indices_pos--;
3906 }
3907 if (indices_pos > 0 && netname[indices_pos] == '[') {
3908 indices = netname.substr(indices_pos);
3909 netname = netname.substr(0, indices_pos);
3910 }
3911 }
3912 }
3913
3914 if (module->wires_.count(netname) == 0)
3915 return false;
3916
3917 RTLIL::Wire *wire = module->wires_.at(netname);
3918 if (!indices.empty()) {
3919 std::vector<std::string> index_tokens;
3920 sigspec_parse_split(index_tokens, indices.substr(1, indices.size()-2), ':');
3921 if (index_tokens.size() == 1) {
3922 cover("kernel.rtlil.sigspec.parse.bit_sel");
3923 int a = atoi(index_tokens.at(0).c_str());
3924 if (a < 0 || a >= wire->width)
3925 return false;
3926 sig.append(RTLIL::SigSpec(wire, a));
3927 } else {
3928 cover("kernel.rtlil.sigspec.parse.part_sel");
3929 int a = atoi(index_tokens.at(0).c_str());
3930 int b = atoi(index_tokens.at(1).c_str());
3931 if (a > b) {
3932 int tmp = a;
3933 a = b, b = tmp;
3934 }
3935 if (a < 0 || a >= wire->width)
3936 return false;
3937 if (b < 0 || b >= wire->width)
3938 return false;
3939 sig.append(RTLIL::SigSpec(wire, a, b-a+1));
3940 }
3941 } else
3942 sig.append(wire);
3943 }
3944
3945 return true;
3946 }
3947
3948 bool RTLIL::SigSpec::parse_sel(RTLIL::SigSpec &sig, RTLIL::Design *design, RTLIL::Module *module, std::string str)
3949 {
3950 if (str.empty() || str[0] != '@')
3951 return parse(sig, module, str);
3952
3953 cover("kernel.rtlil.sigspec.parse.sel");
3954
3955 str = RTLIL::escape_id(str.substr(1));
3956 if (design->selection_vars.count(str) == 0)
3957 return false;
3958
3959 sig = RTLIL::SigSpec();
3960 RTLIL::Selection &sel = design->selection_vars.at(str);
3961 for (auto &it : module->wires_)
3962 if (sel.selected_member(module->name, it.first))
3963 sig.append(it.second);
3964
3965 return true;
3966 }
3967
3968 bool RTLIL::SigSpec::parse_rhs(const RTLIL::SigSpec &lhs, RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str)
3969 {
3970 if (str == "0") {
3971 cover("kernel.rtlil.sigspec.parse.rhs_zeros");
3972 sig = RTLIL::SigSpec(RTLIL::State::S0, lhs.width_);
3973 return true;
3974 }
3975
3976 if (str == "~0") {
3977 cover("kernel.rtlil.sigspec.parse.rhs_ones");
3978 sig = RTLIL::SigSpec(RTLIL::State::S1, lhs.width_);
3979 return true;
3980 }
3981
3982 if (lhs.chunks_.size() == 1) {
3983 char *p = (char*)str.c_str(), *endptr;
3984 long int val = strtol(p, &endptr, 10);
3985 if (endptr && endptr != p && *endptr == 0) {
3986 sig = RTLIL::SigSpec(val, lhs.width_);
3987 cover("kernel.rtlil.sigspec.parse.rhs_dec");
3988 return true;
3989 }
3990 }
3991
3992 return parse(sig, module, str);
3993 }
3994
3995 RTLIL::CaseRule::~CaseRule()
3996 {
3997 for (auto it = switches.begin(); it != switches.end(); it++)
3998 delete *it;
3999 }
4000
4001 bool RTLIL::CaseRule::empty() const
4002 {
4003 return actions.empty() && switches.empty();
4004 }
4005
4006 RTLIL::CaseRule *RTLIL::CaseRule::clone() const
4007 {
4008 RTLIL::CaseRule *new_caserule = new RTLIL::CaseRule;
4009 new_caserule->compare = compare;
4010 new_caserule->actions = actions;
4011 for (auto &it : switches)
4012 new_caserule->switches.push_back(it->clone());
4013 return new_caserule;
4014 }
4015
4016 RTLIL::SwitchRule::~SwitchRule()
4017 {
4018 for (auto it = cases.begin(); it != cases.end(); it++)
4019 delete *it;
4020 }
4021
4022 bool RTLIL::SwitchRule::empty() const
4023 {
4024 return cases.empty();
4025 }
4026
4027 RTLIL::SwitchRule *RTLIL::SwitchRule::clone() const
4028 {
4029 RTLIL::SwitchRule *new_switchrule = new RTLIL::SwitchRule;
4030 new_switchrule->signal = signal;
4031 new_switchrule->attributes = attributes;
4032 for (auto &it : cases)
4033 new_switchrule->cases.push_back(it->clone());
4034 return new_switchrule;
4035
4036 }
4037
4038 RTLIL::SyncRule *RTLIL::SyncRule::clone() const
4039 {
4040 RTLIL::SyncRule *new_syncrule = new RTLIL::SyncRule;
4041 new_syncrule->type = type;
4042 new_syncrule->signal = signal;
4043 new_syncrule->actions = actions;
4044 return new_syncrule;
4045 }
4046
4047 RTLIL::Process::~Process()
4048 {
4049 for (auto it = syncs.begin(); it != syncs.end(); it++)
4050 delete *it;
4051 }
4052
4053 RTLIL::Process *RTLIL::Process::clone() const
4054 {
4055 RTLIL::Process *new_proc = new RTLIL::Process;
4056
4057 new_proc->name = name;
4058 new_proc->attributes = attributes;
4059
4060 RTLIL::CaseRule *rc_ptr = root_case.clone();
4061 new_proc->root_case = *rc_ptr;
4062 rc_ptr->switches.clear();
4063 delete rc_ptr;
4064
4065 for (auto &it : syncs)
4066 new_proc->syncs.push_back(it->clone());
4067
4068 return new_proc;
4069 }
4070
4071 #ifdef WITH_PYTHON
4072 RTLIL::Memory::~Memory()
4073 {
4074 RTLIL::Memory::get_all_memorys()->erase(hashidx_);
4075 }
4076 static std::map<unsigned int, RTLIL::Memory*> all_memorys;
4077 std::map<unsigned int, RTLIL::Memory*> *RTLIL::Memory::get_all_memorys(void)
4078 {
4079 return &all_memorys;
4080 }
4081 #endif
4082 YOSYS_NAMESPACE_END