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Merge remote-tracking branch 'origin/master' into xc7dsp
[yosys.git] / kernel / rtlil.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 #include "kernel/yosys.h"
21 #include "kernel/macc.h"
22 #include "kernel/celltypes.h"
23 #include "frontends/verilog/verilog_frontend.h"
24 #include "backends/ilang/ilang_backend.h"
25
26 #include <string.h>
27 #include <algorithm>
28
29 YOSYS_NAMESPACE_BEGIN
30
31 RTLIL::IdString::destruct_guard_t RTLIL::IdString::destruct_guard;
32 std::vector<int> RTLIL::IdString::global_refcount_storage_;
33 std::vector<char*> RTLIL::IdString::global_id_storage_;
34 dict<char*, int, hash_cstr_ops> RTLIL::IdString::global_id_index_;
35 std::vector<int> RTLIL::IdString::global_free_idx_list_;
36 int RTLIL::IdString::last_created_idx_[8];
37 int RTLIL::IdString::last_created_idx_ptr_;
38
39 RTLIL::Const::Const()
40 {
41 flags = RTLIL::CONST_FLAG_NONE;
42 }
43
44 RTLIL::Const::Const(std::string str)
45 {
46 flags = RTLIL::CONST_FLAG_STRING;
47 for (int i = str.size()-1; i >= 0; i--) {
48 unsigned char ch = str[i];
49 for (int j = 0; j < 8; j++) {
50 bits.push_back((ch & 1) != 0 ? RTLIL::S1 : RTLIL::S0);
51 ch = ch >> 1;
52 }
53 }
54 }
55
56 RTLIL::Const::Const(int val, int width)
57 {
58 flags = RTLIL::CONST_FLAG_NONE;
59 for (int i = 0; i < width; i++) {
60 bits.push_back((val & 1) != 0 ? RTLIL::S1 : RTLIL::S0);
61 val = val >> 1;
62 }
63 }
64
65 RTLIL::Const::Const(RTLIL::State bit, int width)
66 {
67 flags = RTLIL::CONST_FLAG_NONE;
68 for (int i = 0; i < width; i++)
69 bits.push_back(bit);
70 }
71
72 RTLIL::Const::Const(const std::vector<bool> &bits)
73 {
74 flags = RTLIL::CONST_FLAG_NONE;
75 for (auto b : bits)
76 this->bits.push_back(b ? RTLIL::S1 : RTLIL::S0);
77 }
78
79 RTLIL::Const::Const(const RTLIL::Const &c)
80 {
81 flags = c.flags;
82 for (auto b : c.bits)
83 this->bits.push_back(b);
84 }
85
86 bool RTLIL::Const::operator <(const RTLIL::Const &other) const
87 {
88 if (bits.size() != other.bits.size())
89 return bits.size() < other.bits.size();
90 for (size_t i = 0; i < bits.size(); i++)
91 if (bits[i] != other.bits[i])
92 return bits[i] < other.bits[i];
93 return false;
94 }
95
96 bool RTLIL::Const::operator ==(const RTLIL::Const &other) const
97 {
98 return bits == other.bits;
99 }
100
101 bool RTLIL::Const::operator !=(const RTLIL::Const &other) const
102 {
103 return bits != other.bits;
104 }
105
106 bool RTLIL::Const::as_bool() const
107 {
108 for (size_t i = 0; i < bits.size(); i++)
109 if (bits[i] == RTLIL::S1)
110 return true;
111 return false;
112 }
113
114 int RTLIL::Const::as_int(bool is_signed) const
115 {
116 int32_t ret = 0;
117 for (size_t i = 0; i < bits.size() && i < 32; i++)
118 if (bits[i] == RTLIL::S1)
119 ret |= 1 << i;
120 if (is_signed && bits.back() == RTLIL::S1)
121 for (size_t i = bits.size(); i < 32; i++)
122 ret |= 1 << i;
123 return ret;
124 }
125
126 std::string RTLIL::Const::as_string() const
127 {
128 std::string ret;
129 for (size_t i = bits.size(); i > 0; i--)
130 switch (bits[i-1]) {
131 case S0: ret += "0"; break;
132 case S1: ret += "1"; break;
133 case Sx: ret += "x"; break;
134 case Sz: ret += "z"; break;
135 case Sa: ret += "-"; break;
136 case Sm: ret += "m"; break;
137 }
138 return ret;
139 }
140
141 RTLIL::Const RTLIL::Const::from_string(std::string str)
142 {
143 Const c;
144 for (auto it = str.rbegin(); it != str.rend(); it++)
145 switch (*it) {
146 case '0': c.bits.push_back(State::S0); break;
147 case '1': c.bits.push_back(State::S1); break;
148 case 'x': c.bits.push_back(State::Sx); break;
149 case 'z': c.bits.push_back(State::Sz); break;
150 case 'm': c.bits.push_back(State::Sm); break;
151 default: c.bits.push_back(State::Sa);
152 }
153 return c;
154 }
155
156 std::string RTLIL::Const::decode_string() const
157 {
158 std::string string;
159 std::vector<char> string_chars;
160 for (int i = 0; i < int (bits.size()); i += 8) {
161 char ch = 0;
162 for (int j = 0; j < 8 && i + j < int (bits.size()); j++)
163 if (bits[i + j] == RTLIL::State::S1)
164 ch |= 1 << j;
165 if (ch != 0)
166 string_chars.push_back(ch);
167 }
168 for (int i = int (string_chars.size()) - 1; i >= 0; i--)
169 string += string_chars[i];
170 return string;
171 }
172
173 bool RTLIL::Const::is_fully_zero() const
174 {
175 cover("kernel.rtlil.const.is_fully_zero");
176
177 for (auto bit : bits)
178 if (bit != RTLIL::State::S0)
179 return false;
180
181 return true;
182 }
183
184 bool RTLIL::Const::is_fully_ones() const
185 {
186 cover("kernel.rtlil.const.is_fully_ones");
187
188 for (auto bit : bits)
189 if (bit != RTLIL::State::S1)
190 return false;
191
192 return true;
193 }
194
195 bool RTLIL::Const::is_fully_def() const
196 {
197 cover("kernel.rtlil.const.is_fully_def");
198
199 for (auto bit : bits)
200 if (bit != RTLIL::State::S0 && bit != RTLIL::State::S1)
201 return false;
202
203 return true;
204 }
205
206 bool RTLIL::Const::is_fully_undef() const
207 {
208 cover("kernel.rtlil.const.is_fully_undef");
209
210 for (auto bit : bits)
211 if (bit != RTLIL::State::Sx && bit != RTLIL::State::Sz)
212 return false;
213
214 return true;
215 }
216
217 void RTLIL::AttrObject::set_bool_attribute(RTLIL::IdString id, bool value)
218 {
219 if (value)
220 attributes[id] = RTLIL::Const(1);
221 else {
222 const auto it = attributes.find(id);
223 if (it != attributes.end())
224 attributes.erase(it);
225 }
226 }
227
228 bool RTLIL::AttrObject::get_bool_attribute(RTLIL::IdString id) const
229 {
230 const auto it = attributes.find(id);
231 if (it == attributes.end())
232 return false;
233 return it->second.as_bool();
234 }
235
236 void RTLIL::AttrObject::set_strpool_attribute(RTLIL::IdString id, const pool<string> &data)
237 {
238 string attrval;
239 for (auto &s : data) {
240 if (!attrval.empty())
241 attrval += "|";
242 attrval += s;
243 }
244 attributes[id] = RTLIL::Const(attrval);
245 }
246
247 void RTLIL::AttrObject::add_strpool_attribute(RTLIL::IdString id, const pool<string> &data)
248 {
249 pool<string> union_data = get_strpool_attribute(id);
250 union_data.insert(data.begin(), data.end());
251 if (!union_data.empty())
252 set_strpool_attribute(id, union_data);
253 }
254
255 pool<string> RTLIL::AttrObject::get_strpool_attribute(RTLIL::IdString id) const
256 {
257 pool<string> data;
258 if (attributes.count(id) != 0)
259 for (auto s : split_tokens(attributes.at(id).decode_string(), "|"))
260 data.insert(s);
261 return data;
262 }
263
264 void RTLIL::AttrObject::set_src_attribute(const std::string &src)
265 {
266 if (src.empty())
267 attributes.erase("\\src");
268 else
269 attributes["\\src"] = src;
270 }
271
272 std::string RTLIL::AttrObject::get_src_attribute() const
273 {
274 std::string src;
275 if (attributes.count("\\src"))
276 src = attributes.at("\\src").decode_string();
277 return src;
278 }
279
280 bool RTLIL::Selection::selected_module(RTLIL::IdString mod_name) const
281 {
282 if (full_selection)
283 return true;
284 if (selected_modules.count(mod_name) > 0)
285 return true;
286 if (selected_members.count(mod_name) > 0)
287 return true;
288 return false;
289 }
290
291 bool RTLIL::Selection::selected_whole_module(RTLIL::IdString mod_name) const
292 {
293 if (full_selection)
294 return true;
295 if (selected_modules.count(mod_name) > 0)
296 return true;
297 return false;
298 }
299
300 bool RTLIL::Selection::selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const
301 {
302 if (full_selection)
303 return true;
304 if (selected_modules.count(mod_name) > 0)
305 return true;
306 if (selected_members.count(mod_name) > 0)
307 if (selected_members.at(mod_name).count(memb_name) > 0)
308 return true;
309 return false;
310 }
311
312 void RTLIL::Selection::optimize(RTLIL::Design *design)
313 {
314 if (full_selection) {
315 selected_modules.clear();
316 selected_members.clear();
317 return;
318 }
319
320 std::vector<RTLIL::IdString> del_list, add_list;
321
322 del_list.clear();
323 for (auto mod_name : selected_modules) {
324 if (design->modules_.count(mod_name) == 0)
325 del_list.push_back(mod_name);
326 selected_members.erase(mod_name);
327 }
328 for (auto mod_name : del_list)
329 selected_modules.erase(mod_name);
330
331 del_list.clear();
332 for (auto &it : selected_members)
333 if (design->modules_.count(it.first) == 0)
334 del_list.push_back(it.first);
335 for (auto mod_name : del_list)
336 selected_members.erase(mod_name);
337
338 for (auto &it : selected_members) {
339 del_list.clear();
340 for (auto memb_name : it.second)
341 if (design->modules_[it.first]->count_id(memb_name) == 0)
342 del_list.push_back(memb_name);
343 for (auto memb_name : del_list)
344 it.second.erase(memb_name);
345 }
346
347 del_list.clear();
348 add_list.clear();
349 for (auto &it : selected_members)
350 if (it.second.size() == 0)
351 del_list.push_back(it.first);
352 else if (it.second.size() == design->modules_[it.first]->wires_.size() + design->modules_[it.first]->memories.size() +
353 design->modules_[it.first]->cells_.size() + design->modules_[it.first]->processes.size())
354 add_list.push_back(it.first);
355 for (auto mod_name : del_list)
356 selected_members.erase(mod_name);
357 for (auto mod_name : add_list) {
358 selected_members.erase(mod_name);
359 selected_modules.insert(mod_name);
360 }
361
362 if (selected_modules.size() == design->modules_.size()) {
363 full_selection = true;
364 selected_modules.clear();
365 selected_members.clear();
366 }
367 }
368
369 RTLIL::Design::Design()
370 {
371 static unsigned int hashidx_count = 123456789;
372 hashidx_count = mkhash_xorshift(hashidx_count);
373 hashidx_ = hashidx_count;
374
375 refcount_modules_ = 0;
376 selection_stack.push_back(RTLIL::Selection());
377
378 #ifdef WITH_PYTHON
379 RTLIL::Design::get_all_designs()->insert(std::pair<unsigned int, RTLIL::Design*>(hashidx_, this));
380 #endif
381 }
382
383 RTLIL::Design::~Design()
384 {
385 for (auto it = modules_.begin(); it != modules_.end(); ++it)
386 delete it->second;
387 for (auto n : verilog_packages)
388 delete n;
389 for (auto n : verilog_globals)
390 delete n;
391 #ifdef WITH_PYTHON
392 RTLIL::Design::get_all_designs()->erase(hashidx_);
393 #endif
394 }
395
396 #ifdef WITH_PYTHON
397 static std::map<unsigned int, RTLIL::Design*> all_designs;
398 std::map<unsigned int, RTLIL::Design*> *RTLIL::Design::get_all_designs(void)
399 {
400 return &all_designs;
401 }
402 #endif
403
404 RTLIL::ObjRange<RTLIL::Module*> RTLIL::Design::modules()
405 {
406 return RTLIL::ObjRange<RTLIL::Module*>(&modules_, &refcount_modules_);
407 }
408
409 RTLIL::Module *RTLIL::Design::module(RTLIL::IdString name)
410 {
411 return modules_.count(name) ? modules_.at(name) : NULL;
412 }
413
414 RTLIL::Module *RTLIL::Design::top_module()
415 {
416 RTLIL::Module *module = nullptr;
417 int module_count = 0;
418
419 for (auto mod : selected_modules()) {
420 if (mod->get_bool_attribute("\\top"))
421 return mod;
422 module_count++;
423 module = mod;
424 }
425
426 return module_count == 1 ? module : nullptr;
427 }
428
429 void RTLIL::Design::add(RTLIL::Module *module)
430 {
431 log_assert(modules_.count(module->name) == 0);
432 log_assert(refcount_modules_ == 0);
433 modules_[module->name] = module;
434 module->design = this;
435
436 for (auto mon : monitors)
437 mon->notify_module_add(module);
438
439 if (yosys_xtrace) {
440 log("#X# New Module: %s\n", log_id(module));
441 log_backtrace("-X- ", yosys_xtrace-1);
442 }
443 }
444
445 RTLIL::Module *RTLIL::Design::addModule(RTLIL::IdString name)
446 {
447 log_assert(modules_.count(name) == 0);
448 log_assert(refcount_modules_ == 0);
449
450 RTLIL::Module *module = new RTLIL::Module;
451 modules_[name] = module;
452 module->design = this;
453 module->name = name;
454
455 for (auto mon : monitors)
456 mon->notify_module_add(module);
457
458 if (yosys_xtrace) {
459 log("#X# New Module: %s\n", log_id(module));
460 log_backtrace("-X- ", yosys_xtrace-1);
461 }
462
463 return module;
464 }
465
466 void RTLIL::Design::scratchpad_unset(std::string varname)
467 {
468 scratchpad.erase(varname);
469 }
470
471 void RTLIL::Design::scratchpad_set_int(std::string varname, int value)
472 {
473 scratchpad[varname] = stringf("%d", value);
474 }
475
476 void RTLIL::Design::scratchpad_set_bool(std::string varname, bool value)
477 {
478 scratchpad[varname] = value ? "true" : "false";
479 }
480
481 void RTLIL::Design::scratchpad_set_string(std::string varname, std::string value)
482 {
483 scratchpad[varname] = value;
484 }
485
486 int RTLIL::Design::scratchpad_get_int(std::string varname, int default_value) const
487 {
488 if (scratchpad.count(varname) == 0)
489 return default_value;
490
491 std::string str = scratchpad.at(varname);
492
493 if (str == "0" || str == "false")
494 return 0;
495
496 if (str == "1" || str == "true")
497 return 1;
498
499 char *endptr = nullptr;
500 long int parsed_value = strtol(str.c_str(), &endptr, 10);
501 return *endptr ? default_value : parsed_value;
502 }
503
504 bool RTLIL::Design::scratchpad_get_bool(std::string varname, bool default_value) const
505 {
506 if (scratchpad.count(varname) == 0)
507 return default_value;
508
509 std::string str = scratchpad.at(varname);
510
511 if (str == "0" || str == "false")
512 return false;
513
514 if (str == "1" || str == "true")
515 return true;
516
517 return default_value;
518 }
519
520 std::string RTLIL::Design::scratchpad_get_string(std::string varname, std::string default_value) const
521 {
522 if (scratchpad.count(varname) == 0)
523 return default_value;
524 return scratchpad.at(varname);
525 }
526
527 void RTLIL::Design::remove(RTLIL::Module *module)
528 {
529 for (auto mon : monitors)
530 mon->notify_module_del(module);
531
532 if (yosys_xtrace) {
533 log("#X# Remove Module: %s\n", log_id(module));
534 log_backtrace("-X- ", yosys_xtrace-1);
535 }
536
537 log_assert(modules_.at(module->name) == module);
538 modules_.erase(module->name);
539 delete module;
540 }
541
542 void RTLIL::Design::rename(RTLIL::Module *module, RTLIL::IdString new_name)
543 {
544 modules_.erase(module->name);
545 module->name = new_name;
546 add(module);
547 }
548
549 void RTLIL::Design::sort()
550 {
551 scratchpad.sort();
552 modules_.sort(sort_by_id_str());
553 for (auto &it : modules_)
554 it.second->sort();
555 }
556
557 void RTLIL::Design::check()
558 {
559 #ifndef NDEBUG
560 for (auto &it : modules_) {
561 log_assert(this == it.second->design);
562 log_assert(it.first == it.second->name);
563 log_assert(!it.first.empty());
564 it.second->check();
565 }
566 #endif
567 }
568
569 void RTLIL::Design::optimize()
570 {
571 for (auto &it : modules_)
572 it.second->optimize();
573 for (auto &it : selection_stack)
574 it.optimize(this);
575 for (auto &it : selection_vars)
576 it.second.optimize(this);
577 }
578
579 bool RTLIL::Design::selected_module(RTLIL::IdString mod_name) const
580 {
581 if (!selected_active_module.empty() && mod_name != selected_active_module)
582 return false;
583 if (selection_stack.size() == 0)
584 return true;
585 return selection_stack.back().selected_module(mod_name);
586 }
587
588 bool RTLIL::Design::selected_whole_module(RTLIL::IdString mod_name) const
589 {
590 if (!selected_active_module.empty() && mod_name != selected_active_module)
591 return false;
592 if (selection_stack.size() == 0)
593 return true;
594 return selection_stack.back().selected_whole_module(mod_name);
595 }
596
597 bool RTLIL::Design::selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const
598 {
599 if (!selected_active_module.empty() && mod_name != selected_active_module)
600 return false;
601 if (selection_stack.size() == 0)
602 return true;
603 return selection_stack.back().selected_member(mod_name, memb_name);
604 }
605
606 bool RTLIL::Design::selected_module(RTLIL::Module *mod) const
607 {
608 return selected_module(mod->name);
609 }
610
611 bool RTLIL::Design::selected_whole_module(RTLIL::Module *mod) const
612 {
613 return selected_whole_module(mod->name);
614 }
615
616 std::vector<RTLIL::Module*> RTLIL::Design::selected_modules() const
617 {
618 std::vector<RTLIL::Module*> result;
619 result.reserve(modules_.size());
620 for (auto &it : modules_)
621 if (selected_module(it.first) && !it.second->get_blackbox_attribute())
622 result.push_back(it.second);
623 return result;
624 }
625
626 std::vector<RTLIL::Module*> RTLIL::Design::selected_whole_modules() const
627 {
628 std::vector<RTLIL::Module*> result;
629 result.reserve(modules_.size());
630 for (auto &it : modules_)
631 if (selected_whole_module(it.first) && !it.second->get_blackbox_attribute())
632 result.push_back(it.second);
633 return result;
634 }
635
636 std::vector<RTLIL::Module*> RTLIL::Design::selected_whole_modules_warn() const
637 {
638 std::vector<RTLIL::Module*> result;
639 result.reserve(modules_.size());
640 for (auto &it : modules_)
641 if (it.second->get_blackbox_attribute())
642 continue;
643 else if (selected_whole_module(it.first))
644 result.push_back(it.second);
645 else if (selected_module(it.first))
646 log_warning("Ignoring partially selected module %s.\n", log_id(it.first));
647 return result;
648 }
649
650 RTLIL::Module::Module()
651 {
652 static unsigned int hashidx_count = 123456789;
653 hashidx_count = mkhash_xorshift(hashidx_count);
654 hashidx_ = hashidx_count;
655
656 design = nullptr;
657 refcount_wires_ = 0;
658 refcount_cells_ = 0;
659
660 #ifdef WITH_PYTHON
661 RTLIL::Module::get_all_modules()->insert(std::pair<unsigned int, RTLIL::Module*>(hashidx_, this));
662 #endif
663 }
664
665 RTLIL::Module::~Module()
666 {
667 for (auto it = wires_.begin(); it != wires_.end(); ++it)
668 delete it->second;
669 for (auto it = memories.begin(); it != memories.end(); ++it)
670 delete it->second;
671 for (auto it = cells_.begin(); it != cells_.end(); ++it)
672 delete it->second;
673 for (auto it = processes.begin(); it != processes.end(); ++it)
674 delete it->second;
675 #ifdef WITH_PYTHON
676 RTLIL::Module::get_all_modules()->erase(hashidx_);
677 #endif
678 }
679
680 #ifdef WITH_PYTHON
681 static std::map<unsigned int, RTLIL::Module*> all_modules;
682 std::map<unsigned int, RTLIL::Module*> *RTLIL::Module::get_all_modules(void)
683 {
684 return &all_modules;
685 }
686 #endif
687
688 void RTLIL::Module::makeblackbox()
689 {
690 pool<RTLIL::Wire*> delwires;
691
692 for (auto it = wires_.begin(); it != wires_.end(); ++it)
693 if (!it->second->port_input && !it->second->port_output)
694 delwires.insert(it->second);
695
696 for (auto it = memories.begin(); it != memories.end(); ++it)
697 delete it->second;
698 memories.clear();
699
700 for (auto it = cells_.begin(); it != cells_.end(); ++it)
701 delete it->second;
702 cells_.clear();
703
704 for (auto it = processes.begin(); it != processes.end(); ++it)
705 delete it->second;
706 processes.clear();
707
708 remove(delwires);
709 set_bool_attribute("\\blackbox");
710 }
711
712 void RTLIL::Module::reprocess_module(RTLIL::Design *, dict<RTLIL::IdString, RTLIL::Module *>)
713 {
714 log_error("Cannot reprocess_module module `%s' !\n", id2cstr(name));
715 }
716
717 RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, dict<RTLIL::IdString, RTLIL::Const>, bool mayfail)
718 {
719 if (mayfail)
720 return RTLIL::IdString();
721 log_error("Module `%s' is used with parameters but is not parametric!\n", id2cstr(name));
722 }
723
724
725 RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, dict<RTLIL::IdString, RTLIL::Const>, dict<RTLIL::IdString, RTLIL::Module*>, dict<RTLIL::IdString, RTLIL::IdString>, bool mayfail)
726 {
727 if (mayfail)
728 return RTLIL::IdString();
729 log_error("Module `%s' is used with parameters but is not parametric!\n", id2cstr(name));
730 }
731
732 size_t RTLIL::Module::count_id(RTLIL::IdString id)
733 {
734 return wires_.count(id) + memories.count(id) + cells_.count(id) + processes.count(id);
735 }
736
737 #ifndef NDEBUG
738 namespace {
739 struct InternalCellChecker
740 {
741 RTLIL::Module *module;
742 RTLIL::Cell *cell;
743 pool<RTLIL::IdString> expected_params, expected_ports;
744
745 InternalCellChecker(RTLIL::Module *module, RTLIL::Cell *cell) : module(module), cell(cell) { }
746
747 void error(int linenr)
748 {
749 std::stringstream buf;
750 ILANG_BACKEND::dump_cell(buf, " ", cell);
751
752 log_error("Found error in internal cell %s%s%s (%s) at %s:%d:\n%s",
753 module ? module->name.c_str() : "", module ? "." : "",
754 cell->name.c_str(), cell->type.c_str(), __FILE__, linenr, buf.str().c_str());
755 }
756
757 int param(const char *name)
758 {
759 if (cell->parameters.count(name) == 0)
760 error(__LINE__);
761 expected_params.insert(name);
762 return cell->parameters.at(name).as_int();
763 }
764
765 int param_bool(const char *name)
766 {
767 int v = param(name);
768 if (cell->parameters.at(name).bits.size() > 32)
769 error(__LINE__);
770 if (v != 0 && v != 1)
771 error(__LINE__);
772 return v;
773 }
774
775 void param_bits(const char *name, int width)
776 {
777 param(name);
778 if (int(cell->parameters.at(name).bits.size()) != width)
779 error(__LINE__);
780 }
781
782 void port(const char *name, int width)
783 {
784 if (!cell->hasPort(name))
785 error(__LINE__);
786 if (cell->getPort(name).size() != width)
787 error(__LINE__);
788 expected_ports.insert(name);
789 }
790
791 void check_expected(bool check_matched_sign = true)
792 {
793 for (auto &para : cell->parameters)
794 if (expected_params.count(para.first) == 0)
795 error(__LINE__);
796 for (auto &conn : cell->connections())
797 if (expected_ports.count(conn.first) == 0)
798 error(__LINE__);
799
800 if (expected_params.count("\\A_SIGNED") != 0 && expected_params.count("\\B_SIGNED") && check_matched_sign) {
801 bool a_is_signed = param("\\A_SIGNED") != 0;
802 bool b_is_signed = param("\\B_SIGNED") != 0;
803 if (a_is_signed != b_is_signed)
804 error(__LINE__);
805 }
806 }
807
808 void check_gate(const char *ports)
809 {
810 if (cell->parameters.size() != 0)
811 error(__LINE__);
812
813 for (const char *p = ports; *p; p++) {
814 char portname[3] = { '\\', *p, 0 };
815 if (!cell->hasPort(portname))
816 error(__LINE__);
817 if (cell->getPort(portname).size() != 1)
818 error(__LINE__);
819 }
820
821 for (auto &conn : cell->connections()) {
822 if (conn.first.size() != 2 || conn.first[0] != '\\')
823 error(__LINE__);
824 if (strchr(ports, conn.first[1]) == NULL)
825 error(__LINE__);
826 }
827 }
828
829 void check()
830 {
831 if (cell->type.substr(0, 1) != "$" || cell->type.substr(0, 3) == "$__" || cell->type.substr(0, 8) == "$paramod" || cell->type.substr(0,10) == "$fmcombine" ||
832 cell->type.substr(0, 9) == "$verific$" || cell->type.substr(0, 7) == "$array:" || cell->type.substr(0, 8) == "$extern:")
833 return;
834
835 if (cell->type.in("$not", "$pos", "$neg")) {
836 param_bool("\\A_SIGNED");
837 port("\\A", param("\\A_WIDTH"));
838 port("\\Y", param("\\Y_WIDTH"));
839 check_expected();
840 return;
841 }
842
843 if (cell->type.in("$and", "$or", "$xor", "$xnor")) {
844 param_bool("\\A_SIGNED");
845 param_bool("\\B_SIGNED");
846 port("\\A", param("\\A_WIDTH"));
847 port("\\B", param("\\B_WIDTH"));
848 port("\\Y", param("\\Y_WIDTH"));
849 check_expected();
850 return;
851 }
852
853 if (cell->type.in("$reduce_and", "$reduce_or", "$reduce_xor", "$reduce_xnor", "$reduce_bool")) {
854 param_bool("\\A_SIGNED");
855 port("\\A", param("\\A_WIDTH"));
856 port("\\Y", param("\\Y_WIDTH"));
857 check_expected();
858 return;
859 }
860
861 if (cell->type.in("$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx")) {
862 param_bool("\\A_SIGNED");
863 param_bool("\\B_SIGNED");
864 port("\\A", param("\\A_WIDTH"));
865 port("\\B", param("\\B_WIDTH"));
866 port("\\Y", param("\\Y_WIDTH"));
867 check_expected(false);
868 return;
869 }
870
871 if (cell->type.in("$lt", "$le", "$eq", "$ne", "$eqx", "$nex", "$ge", "$gt")) {
872 param_bool("\\A_SIGNED");
873 param_bool("\\B_SIGNED");
874 port("\\A", param("\\A_WIDTH"));
875 port("\\B", param("\\B_WIDTH"));
876 port("\\Y", param("\\Y_WIDTH"));
877 check_expected();
878 return;
879 }
880
881 if (cell->type.in("$add", "$sub", "$mul", "$div", "$mod", "$pow")) {
882 param_bool("\\A_SIGNED");
883 param_bool("\\B_SIGNED");
884 port("\\A", param("\\A_WIDTH"));
885 port("\\B", param("\\B_WIDTH"));
886 port("\\Y", param("\\Y_WIDTH"));
887 check_expected(cell->type != "$pow");
888 return;
889 }
890
891 if (cell->type == "$fa") {
892 port("\\A", param("\\WIDTH"));
893 port("\\B", param("\\WIDTH"));
894 port("\\C", param("\\WIDTH"));
895 port("\\X", param("\\WIDTH"));
896 port("\\Y", param("\\WIDTH"));
897 check_expected();
898 return;
899 }
900
901 if (cell->type == "$lcu") {
902 port("\\P", param("\\WIDTH"));
903 port("\\G", param("\\WIDTH"));
904 port("\\CI", 1);
905 port("\\CO", param("\\WIDTH"));
906 check_expected();
907 return;
908 }
909
910 if (cell->type == "$alu") {
911 param_bool("\\A_SIGNED");
912 param_bool("\\B_SIGNED");
913 port("\\A", param("\\A_WIDTH"));
914 port("\\B", param("\\B_WIDTH"));
915 port("\\CI", 1);
916 port("\\BI", 1);
917 port("\\X", param("\\Y_WIDTH"));
918 port("\\Y", param("\\Y_WIDTH"));
919 port("\\CO", param("\\Y_WIDTH"));
920 check_expected();
921 return;
922 }
923
924 if (cell->type == "$macc") {
925 param("\\CONFIG");
926 param("\\CONFIG_WIDTH");
927 port("\\A", param("\\A_WIDTH"));
928 port("\\B", param("\\B_WIDTH"));
929 port("\\Y", param("\\Y_WIDTH"));
930 check_expected();
931 Macc().from_cell(cell);
932 return;
933 }
934
935 if (cell->type == "$logic_not") {
936 param_bool("\\A_SIGNED");
937 port("\\A", param("\\A_WIDTH"));
938 port("\\Y", param("\\Y_WIDTH"));
939 check_expected();
940 return;
941 }
942
943 if (cell->type == "$logic_and" || cell->type == "$logic_or") {
944 param_bool("\\A_SIGNED");
945 param_bool("\\B_SIGNED");
946 port("\\A", param("\\A_WIDTH"));
947 port("\\B", param("\\B_WIDTH"));
948 port("\\Y", param("\\Y_WIDTH"));
949 check_expected(false);
950 return;
951 }
952
953 if (cell->type == "$slice") {
954 param("\\OFFSET");
955 port("\\A", param("\\A_WIDTH"));
956 port("\\Y", param("\\Y_WIDTH"));
957 if (param("\\OFFSET") + param("\\Y_WIDTH") > param("\\A_WIDTH"))
958 error(__LINE__);
959 check_expected();
960 return;
961 }
962
963 if (cell->type == "$concat") {
964 port("\\A", param("\\A_WIDTH"));
965 port("\\B", param("\\B_WIDTH"));
966 port("\\Y", param("\\A_WIDTH") + param("\\B_WIDTH"));
967 check_expected();
968 return;
969 }
970
971 if (cell->type == "$mux") {
972 port("\\A", param("\\WIDTH"));
973 port("\\B", param("\\WIDTH"));
974 port("\\S", 1);
975 port("\\Y", param("\\WIDTH"));
976 check_expected();
977 return;
978 }
979
980 if (cell->type == "$pmux") {
981 port("\\A", param("\\WIDTH"));
982 port("\\B", param("\\WIDTH") * param("\\S_WIDTH"));
983 port("\\S", param("\\S_WIDTH"));
984 port("\\Y", param("\\WIDTH"));
985 check_expected();
986 return;
987 }
988
989 if (cell->type == "$lut") {
990 param("\\LUT");
991 port("\\A", param("\\WIDTH"));
992 port("\\Y", 1);
993 check_expected();
994 return;
995 }
996
997 if (cell->type == "$sop") {
998 param("\\DEPTH");
999 param("\\TABLE");
1000 port("\\A", param("\\WIDTH"));
1001 port("\\Y", 1);
1002 check_expected();
1003 return;
1004 }
1005
1006 if (cell->type == "$sr") {
1007 param_bool("\\SET_POLARITY");
1008 param_bool("\\CLR_POLARITY");
1009 port("\\SET", param("\\WIDTH"));
1010 port("\\CLR", param("\\WIDTH"));
1011 port("\\Q", param("\\WIDTH"));
1012 check_expected();
1013 return;
1014 }
1015
1016 if (cell->type == "$ff") {
1017 port("\\D", param("\\WIDTH"));
1018 port("\\Q", param("\\WIDTH"));
1019 check_expected();
1020 return;
1021 }
1022
1023 if (cell->type == "$dff") {
1024 param_bool("\\CLK_POLARITY");
1025 port("\\CLK", 1);
1026 port("\\D", param("\\WIDTH"));
1027 port("\\Q", param("\\WIDTH"));
1028 check_expected();
1029 return;
1030 }
1031
1032 if (cell->type == "$dffe") {
1033 param_bool("\\CLK_POLARITY");
1034 param_bool("\\EN_POLARITY");
1035 port("\\CLK", 1);
1036 port("\\EN", 1);
1037 port("\\D", param("\\WIDTH"));
1038 port("\\Q", param("\\WIDTH"));
1039 check_expected();
1040 return;
1041 }
1042
1043 if (cell->type == "$dffsr") {
1044 param_bool("\\CLK_POLARITY");
1045 param_bool("\\SET_POLARITY");
1046 param_bool("\\CLR_POLARITY");
1047 port("\\CLK", 1);
1048 port("\\SET", param("\\WIDTH"));
1049 port("\\CLR", param("\\WIDTH"));
1050 port("\\D", param("\\WIDTH"));
1051 port("\\Q", param("\\WIDTH"));
1052 check_expected();
1053 return;
1054 }
1055
1056 if (cell->type == "$adff") {
1057 param_bool("\\CLK_POLARITY");
1058 param_bool("\\ARST_POLARITY");
1059 param_bits("\\ARST_VALUE", param("\\WIDTH"));
1060 port("\\CLK", 1);
1061 port("\\ARST", 1);
1062 port("\\D", param("\\WIDTH"));
1063 port("\\Q", param("\\WIDTH"));
1064 check_expected();
1065 return;
1066 }
1067
1068 if (cell->type == "$dlatch") {
1069 param_bool("\\EN_POLARITY");
1070 port("\\EN", 1);
1071 port("\\D", param("\\WIDTH"));
1072 port("\\Q", param("\\WIDTH"));
1073 check_expected();
1074 return;
1075 }
1076
1077 if (cell->type == "$dlatchsr") {
1078 param_bool("\\EN_POLARITY");
1079 param_bool("\\SET_POLARITY");
1080 param_bool("\\CLR_POLARITY");
1081 port("\\EN", 1);
1082 port("\\SET", param("\\WIDTH"));
1083 port("\\CLR", param("\\WIDTH"));
1084 port("\\D", param("\\WIDTH"));
1085 port("\\Q", param("\\WIDTH"));
1086 check_expected();
1087 return;
1088 }
1089
1090 if (cell->type == "$fsm") {
1091 param("\\NAME");
1092 param_bool("\\CLK_POLARITY");
1093 param_bool("\\ARST_POLARITY");
1094 param("\\STATE_BITS");
1095 param("\\STATE_NUM");
1096 param("\\STATE_NUM_LOG2");
1097 param("\\STATE_RST");
1098 param_bits("\\STATE_TABLE", param("\\STATE_BITS") * param("\\STATE_NUM"));
1099 param("\\TRANS_NUM");
1100 param_bits("\\TRANS_TABLE", param("\\TRANS_NUM") * (2*param("\\STATE_NUM_LOG2") + param("\\CTRL_IN_WIDTH") + param("\\CTRL_OUT_WIDTH")));
1101 port("\\CLK", 1);
1102 port("\\ARST", 1);
1103 port("\\CTRL_IN", param("\\CTRL_IN_WIDTH"));
1104 port("\\CTRL_OUT", param("\\CTRL_OUT_WIDTH"));
1105 check_expected();
1106 return;
1107 }
1108
1109 if (cell->type == "$memrd") {
1110 param("\\MEMID");
1111 param_bool("\\CLK_ENABLE");
1112 param_bool("\\CLK_POLARITY");
1113 param_bool("\\TRANSPARENT");
1114 port("\\CLK", 1);
1115 port("\\EN", 1);
1116 port("\\ADDR", param("\\ABITS"));
1117 port("\\DATA", param("\\WIDTH"));
1118 check_expected();
1119 return;
1120 }
1121
1122 if (cell->type == "$memwr") {
1123 param("\\MEMID");
1124 param_bool("\\CLK_ENABLE");
1125 param_bool("\\CLK_POLARITY");
1126 param("\\PRIORITY");
1127 port("\\CLK", 1);
1128 port("\\EN", param("\\WIDTH"));
1129 port("\\ADDR", param("\\ABITS"));
1130 port("\\DATA", param("\\WIDTH"));
1131 check_expected();
1132 return;
1133 }
1134
1135 if (cell->type == "$meminit") {
1136 param("\\MEMID");
1137 param("\\PRIORITY");
1138 port("\\ADDR", param("\\ABITS"));
1139 port("\\DATA", param("\\WIDTH") * param("\\WORDS"));
1140 check_expected();
1141 return;
1142 }
1143
1144 if (cell->type == "$mem") {
1145 param("\\MEMID");
1146 param("\\SIZE");
1147 param("\\OFFSET");
1148 param("\\INIT");
1149 param_bits("\\RD_CLK_ENABLE", max(1, param("\\RD_PORTS")));
1150 param_bits("\\RD_CLK_POLARITY", max(1, param("\\RD_PORTS")));
1151 param_bits("\\RD_TRANSPARENT", max(1, param("\\RD_PORTS")));
1152 param_bits("\\WR_CLK_ENABLE", max(1, param("\\WR_PORTS")));
1153 param_bits("\\WR_CLK_POLARITY", max(1, param("\\WR_PORTS")));
1154 port("\\RD_CLK", param("\\RD_PORTS"));
1155 port("\\RD_EN", param("\\RD_PORTS"));
1156 port("\\RD_ADDR", param("\\RD_PORTS") * param("\\ABITS"));
1157 port("\\RD_DATA", param("\\RD_PORTS") * param("\\WIDTH"));
1158 port("\\WR_CLK", param("\\WR_PORTS"));
1159 port("\\WR_EN", param("\\WR_PORTS") * param("\\WIDTH"));
1160 port("\\WR_ADDR", param("\\WR_PORTS") * param("\\ABITS"));
1161 port("\\WR_DATA", param("\\WR_PORTS") * param("\\WIDTH"));
1162 check_expected();
1163 return;
1164 }
1165
1166 if (cell->type == "$tribuf") {
1167 port("\\A", param("\\WIDTH"));
1168 port("\\Y", param("\\WIDTH"));
1169 port("\\EN", 1);
1170 check_expected();
1171 return;
1172 }
1173
1174 if (cell->type.in("$assert", "$assume", "$live", "$fair", "$cover")) {
1175 port("\\A", 1);
1176 port("\\EN", 1);
1177 check_expected();
1178 return;
1179 }
1180
1181 if (cell->type == "$initstate") {
1182 port("\\Y", 1);
1183 check_expected();
1184 return;
1185 }
1186
1187 if (cell->type.in("$anyconst", "$anyseq", "$allconst", "$allseq")) {
1188 port("\\Y", param("\\WIDTH"));
1189 check_expected();
1190 return;
1191 }
1192
1193 if (cell->type == "$equiv") {
1194 port("\\A", 1);
1195 port("\\B", 1);
1196 port("\\Y", 1);
1197 check_expected();
1198 return;
1199 }
1200
1201 if (cell->type.in("$specify2", "$specify3")) {
1202 param_bool("\\FULL");
1203 param_bool("\\SRC_DST_PEN");
1204 param_bool("\\SRC_DST_POL");
1205 param("\\T_RISE_MIN");
1206 param("\\T_RISE_TYP");
1207 param("\\T_RISE_MAX");
1208 param("\\T_FALL_MIN");
1209 param("\\T_FALL_TYP");
1210 param("\\T_FALL_MAX");
1211 port("\\EN", 1);
1212 port("\\SRC", param("\\SRC_WIDTH"));
1213 port("\\DST", param("\\DST_WIDTH"));
1214 if (cell->type == "$specify3") {
1215 param_bool("\\EDGE_EN");
1216 param_bool("\\EDGE_POL");
1217 param_bool("\\DAT_DST_PEN");
1218 param_bool("\\DAT_DST_POL");
1219 port("\\DAT", param("\\DST_WIDTH"));
1220 }
1221 check_expected();
1222 return;
1223 }
1224
1225 if (cell->type == "$specrule") {
1226 param("\\TYPE");
1227 param_bool("\\SRC_PEN");
1228 param_bool("\\SRC_POL");
1229 param_bool("\\DST_PEN");
1230 param_bool("\\DST_POL");
1231 param("\\T_LIMIT");
1232 param("\\T_LIMIT2");
1233 port("\\SRC_EN", 1);
1234 port("\\DST_EN", 1);
1235 port("\\SRC", param("\\SRC_WIDTH"));
1236 port("\\DST", param("\\DST_WIDTH"));
1237 check_expected();
1238 return;
1239 }
1240
1241 if (cell->type == "$_BUF_") { check_gate("AY"); return; }
1242 if (cell->type == "$_NOT_") { check_gate("AY"); return; }
1243 if (cell->type == "$_AND_") { check_gate("ABY"); return; }
1244 if (cell->type == "$_NAND_") { check_gate("ABY"); return; }
1245 if (cell->type == "$_OR_") { check_gate("ABY"); return; }
1246 if (cell->type == "$_NOR_") { check_gate("ABY"); return; }
1247 if (cell->type == "$_XOR_") { check_gate("ABY"); return; }
1248 if (cell->type == "$_XNOR_") { check_gate("ABY"); return; }
1249 if (cell->type == "$_ANDNOT_") { check_gate("ABY"); return; }
1250 if (cell->type == "$_ORNOT_") { check_gate("ABY"); return; }
1251 if (cell->type == "$_MUX_") { check_gate("ABSY"); return; }
1252 if (cell->type == "$_NMUX_") { check_gate("ABSY"); return; }
1253 if (cell->type == "$_AOI3_") { check_gate("ABCY"); return; }
1254 if (cell->type == "$_OAI3_") { check_gate("ABCY"); return; }
1255 if (cell->type == "$_AOI4_") { check_gate("ABCDY"); return; }
1256 if (cell->type == "$_OAI4_") { check_gate("ABCDY"); return; }
1257
1258 if (cell->type == "$_TBUF_") { check_gate("AYE"); return; }
1259
1260 if (cell->type == "$_MUX4_") { check_gate("ABCDSTY"); return; }
1261 if (cell->type == "$_MUX8_") { check_gate("ABCDEFGHSTUY"); return; }
1262 if (cell->type == "$_MUX16_") { check_gate("ABCDEFGHIJKLMNOPSTUVY"); return; }
1263
1264 if (cell->type == "$_SR_NN_") { check_gate("SRQ"); return; }
1265 if (cell->type == "$_SR_NP_") { check_gate("SRQ"); return; }
1266 if (cell->type == "$_SR_PN_") { check_gate("SRQ"); return; }
1267 if (cell->type == "$_SR_PP_") { check_gate("SRQ"); return; }
1268
1269 if (cell->type == "$_FF_") { check_gate("DQ"); return; }
1270 if (cell->type == "$_DFF_N_") { check_gate("DQC"); return; }
1271 if (cell->type == "$_DFF_P_") { check_gate("DQC"); return; }
1272
1273 if (cell->type == "$_DFFE_NN_") { check_gate("DQCE"); return; }
1274 if (cell->type == "$_DFFE_NP_") { check_gate("DQCE"); return; }
1275 if (cell->type == "$_DFFE_PN_") { check_gate("DQCE"); return; }
1276 if (cell->type == "$_DFFE_PP_") { check_gate("DQCE"); return; }
1277
1278 if (cell->type == "$_DFF_NN0_") { check_gate("DQCR"); return; }
1279 if (cell->type == "$_DFF_NN1_") { check_gate("DQCR"); return; }
1280 if (cell->type == "$_DFF_NP0_") { check_gate("DQCR"); return; }
1281 if (cell->type == "$_DFF_NP1_") { check_gate("DQCR"); return; }
1282 if (cell->type == "$_DFF_PN0_") { check_gate("DQCR"); return; }
1283 if (cell->type == "$_DFF_PN1_") { check_gate("DQCR"); return; }
1284 if (cell->type == "$_DFF_PP0_") { check_gate("DQCR"); return; }
1285 if (cell->type == "$_DFF_PP1_") { check_gate("DQCR"); return; }
1286
1287 if (cell->type == "$_DFFSR_NNN_") { check_gate("CSRDQ"); return; }
1288 if (cell->type == "$_DFFSR_NNP_") { check_gate("CSRDQ"); return; }
1289 if (cell->type == "$_DFFSR_NPN_") { check_gate("CSRDQ"); return; }
1290 if (cell->type == "$_DFFSR_NPP_") { check_gate("CSRDQ"); return; }
1291 if (cell->type == "$_DFFSR_PNN_") { check_gate("CSRDQ"); return; }
1292 if (cell->type == "$_DFFSR_PNP_") { check_gate("CSRDQ"); return; }
1293 if (cell->type == "$_DFFSR_PPN_") { check_gate("CSRDQ"); return; }
1294 if (cell->type == "$_DFFSR_PPP_") { check_gate("CSRDQ"); return; }
1295
1296 if (cell->type == "$_DLATCH_N_") { check_gate("EDQ"); return; }
1297 if (cell->type == "$_DLATCH_P_") { check_gate("EDQ"); return; }
1298
1299 if (cell->type == "$_DLATCHSR_NNN_") { check_gate("ESRDQ"); return; }
1300 if (cell->type == "$_DLATCHSR_NNP_") { check_gate("ESRDQ"); return; }
1301 if (cell->type == "$_DLATCHSR_NPN_") { check_gate("ESRDQ"); return; }
1302 if (cell->type == "$_DLATCHSR_NPP_") { check_gate("ESRDQ"); return; }
1303 if (cell->type == "$_DLATCHSR_PNN_") { check_gate("ESRDQ"); return; }
1304 if (cell->type == "$_DLATCHSR_PNP_") { check_gate("ESRDQ"); return; }
1305 if (cell->type == "$_DLATCHSR_PPN_") { check_gate("ESRDQ"); return; }
1306 if (cell->type == "$_DLATCHSR_PPP_") { check_gate("ESRDQ"); return; }
1307
1308 error(__LINE__);
1309 }
1310 };
1311 }
1312 #endif
1313
1314 void RTLIL::Module::sort()
1315 {
1316 wires_.sort(sort_by_id_str());
1317 cells_.sort(sort_by_id_str());
1318 avail_parameters.sort(sort_by_id_str());
1319 memories.sort(sort_by_id_str());
1320 processes.sort(sort_by_id_str());
1321 for (auto &it : cells_)
1322 it.second->sort();
1323 for (auto &it : wires_)
1324 it.second->attributes.sort(sort_by_id_str());
1325 for (auto &it : memories)
1326 it.second->attributes.sort(sort_by_id_str());
1327 }
1328
1329 void RTLIL::Module::check()
1330 {
1331 #ifndef NDEBUG
1332 std::vector<bool> ports_declared;
1333 for (auto &it : wires_) {
1334 log_assert(this == it.second->module);
1335 log_assert(it.first == it.second->name);
1336 log_assert(!it.first.empty());
1337 log_assert(it.second->width >= 0);
1338 log_assert(it.second->port_id >= 0);
1339 for (auto &it2 : it.second->attributes)
1340 log_assert(!it2.first.empty());
1341 if (it.second->port_id) {
1342 log_assert(GetSize(ports) >= it.second->port_id);
1343 log_assert(ports.at(it.second->port_id-1) == it.first);
1344 log_assert(it.second->port_input || it.second->port_output);
1345 if (GetSize(ports_declared) < it.second->port_id)
1346 ports_declared.resize(it.second->port_id);
1347 log_assert(ports_declared[it.second->port_id-1] == false);
1348 ports_declared[it.second->port_id-1] = true;
1349 } else
1350 log_assert(!it.second->port_input && !it.second->port_output);
1351 }
1352 for (auto port_declared : ports_declared)
1353 log_assert(port_declared == true);
1354 log_assert(GetSize(ports) == GetSize(ports_declared));
1355
1356 for (auto &it : memories) {
1357 log_assert(it.first == it.second->name);
1358 log_assert(!it.first.empty());
1359 log_assert(it.second->width >= 0);
1360 log_assert(it.second->size >= 0);
1361 for (auto &it2 : it.second->attributes)
1362 log_assert(!it2.first.empty());
1363 }
1364
1365 for (auto &it : cells_) {
1366 log_assert(this == it.second->module);
1367 log_assert(it.first == it.second->name);
1368 log_assert(!it.first.empty());
1369 log_assert(!it.second->type.empty());
1370 for (auto &it2 : it.second->connections()) {
1371 log_assert(!it2.first.empty());
1372 it2.second.check();
1373 }
1374 for (auto &it2 : it.second->attributes)
1375 log_assert(!it2.first.empty());
1376 for (auto &it2 : it.second->parameters)
1377 log_assert(!it2.first.empty());
1378 InternalCellChecker checker(this, it.second);
1379 checker.check();
1380 }
1381
1382 for (auto &it : processes) {
1383 log_assert(it.first == it.second->name);
1384 log_assert(!it.first.empty());
1385 log_assert(it.second->root_case.compare.empty());
1386 std::vector<CaseRule*> all_cases = {&it.second->root_case};
1387 for (size_t i = 0; i < all_cases.size(); i++) {
1388 for (auto &switch_it : all_cases[i]->switches) {
1389 for (auto &case_it : switch_it->cases) {
1390 for (auto &compare_it : case_it->compare) {
1391 log_assert(switch_it->signal.size() == compare_it.size());
1392 }
1393 all_cases.push_back(case_it);
1394 }
1395 }
1396 }
1397 for (auto &sync_it : it.second->syncs) {
1398 switch (sync_it->type) {
1399 case SyncType::ST0:
1400 case SyncType::ST1:
1401 case SyncType::STp:
1402 case SyncType::STn:
1403 case SyncType::STe:
1404 log_assert(!sync_it->signal.empty());
1405 break;
1406 case SyncType::STa:
1407 case SyncType::STg:
1408 case SyncType::STi:
1409 log_assert(sync_it->signal.empty());
1410 break;
1411 }
1412 }
1413 }
1414
1415 for (auto &it : connections_) {
1416 log_assert(it.first.size() == it.second.size());
1417 log_assert(!it.first.has_const());
1418 it.first.check();
1419 it.second.check();
1420 }
1421
1422 for (auto &it : attributes)
1423 log_assert(!it.first.empty());
1424 #endif
1425 }
1426
1427 void RTLIL::Module::optimize()
1428 {
1429 }
1430
1431 void RTLIL::Module::cloneInto(RTLIL::Module *new_mod) const
1432 {
1433 log_assert(new_mod->refcount_wires_ == 0);
1434 log_assert(new_mod->refcount_cells_ == 0);
1435
1436 new_mod->avail_parameters = avail_parameters;
1437
1438 for (auto &conn : connections_)
1439 new_mod->connect(conn);
1440
1441 for (auto &attr : attributes)
1442 new_mod->attributes[attr.first] = attr.second;
1443
1444 for (auto &it : wires_)
1445 new_mod->addWire(it.first, it.second);
1446
1447 for (auto &it : memories)
1448 new_mod->memories[it.first] = new RTLIL::Memory(*it.second);
1449
1450 for (auto &it : cells_)
1451 new_mod->addCell(it.first, it.second);
1452
1453 for (auto &it : processes)
1454 new_mod->processes[it.first] = it.second->clone();
1455
1456 struct RewriteSigSpecWorker
1457 {
1458 RTLIL::Module *mod;
1459 void operator()(RTLIL::SigSpec &sig)
1460 {
1461 std::vector<RTLIL::SigChunk> chunks = sig.chunks();
1462 for (auto &c : chunks)
1463 if (c.wire != NULL)
1464 c.wire = mod->wires_.at(c.wire->name);
1465 sig = chunks;
1466 }
1467 };
1468
1469 RewriteSigSpecWorker rewriteSigSpecWorker;
1470 rewriteSigSpecWorker.mod = new_mod;
1471 new_mod->rewrite_sigspecs(rewriteSigSpecWorker);
1472 new_mod->fixup_ports();
1473 }
1474
1475 RTLIL::Module *RTLIL::Module::clone() const
1476 {
1477 RTLIL::Module *new_mod = new RTLIL::Module;
1478 new_mod->name = name;
1479 cloneInto(new_mod);
1480 return new_mod;
1481 }
1482
1483 bool RTLIL::Module::has_memories() const
1484 {
1485 return !memories.empty();
1486 }
1487
1488 bool RTLIL::Module::has_processes() const
1489 {
1490 return !processes.empty();
1491 }
1492
1493 bool RTLIL::Module::has_memories_warn() const
1494 {
1495 if (!memories.empty())
1496 log_warning("Ignoring module %s because it contains memories (run 'memory' command first).\n", log_id(this));
1497 return !memories.empty();
1498 }
1499
1500 bool RTLIL::Module::has_processes_warn() const
1501 {
1502 if (!processes.empty())
1503 log_warning("Ignoring module %s because it contains processes (run 'proc' command first).\n", log_id(this));
1504 return !processes.empty();
1505 }
1506
1507 std::vector<RTLIL::Wire*> RTLIL::Module::selected_wires() const
1508 {
1509 std::vector<RTLIL::Wire*> result;
1510 result.reserve(wires_.size());
1511 for (auto &it : wires_)
1512 if (design->selected(this, it.second))
1513 result.push_back(it.second);
1514 return result;
1515 }
1516
1517 std::vector<RTLIL::Cell*> RTLIL::Module::selected_cells() const
1518 {
1519 std::vector<RTLIL::Cell*> result;
1520 result.reserve(wires_.size());
1521 for (auto &it : cells_)
1522 if (design->selected(this, it.second))
1523 result.push_back(it.second);
1524 return result;
1525 }
1526
1527 void RTLIL::Module::add(RTLIL::Wire *wire)
1528 {
1529 log_assert(!wire->name.empty());
1530 log_assert(count_id(wire->name) == 0);
1531 log_assert(refcount_wires_ == 0);
1532 wires_[wire->name] = wire;
1533 wire->module = this;
1534 }
1535
1536 void RTLIL::Module::add(RTLIL::Cell *cell)
1537 {
1538 log_assert(!cell->name.empty());
1539 log_assert(count_id(cell->name) == 0);
1540 log_assert(refcount_cells_ == 0);
1541 cells_[cell->name] = cell;
1542 cell->module = this;
1543 }
1544
1545 void RTLIL::Module::remove(const pool<RTLIL::Wire*> &wires)
1546 {
1547 log_assert(refcount_wires_ == 0);
1548
1549 struct DeleteWireWorker
1550 {
1551 RTLIL::Module *module;
1552 const pool<RTLIL::Wire*> *wires_p;
1553
1554 void operator()(RTLIL::SigSpec &sig) {
1555 std::vector<RTLIL::SigChunk> chunks = sig;
1556 for (auto &c : chunks)
1557 if (c.wire != NULL && wires_p->count(c.wire)) {
1558 c.wire = module->addWire(NEW_ID, c.width);
1559 c.offset = 0;
1560 }
1561 sig = chunks;
1562 }
1563
1564 void operator()(RTLIL::SigSpec &lhs, RTLIL::SigSpec &rhs) {
1565 log_assert(GetSize(lhs) == GetSize(rhs));
1566 RTLIL::SigSpec new_lhs, new_rhs;
1567 for (int i = 0; i < GetSize(lhs); i++) {
1568 RTLIL::SigBit lhs_bit = lhs[i];
1569 if (lhs_bit.wire != nullptr && wires_p->count(lhs_bit.wire))
1570 continue;
1571 RTLIL::SigBit rhs_bit = rhs[i];
1572 if (rhs_bit.wire != nullptr && wires_p->count(rhs_bit.wire))
1573 continue;
1574 new_lhs.append(lhs_bit);
1575 new_rhs.append(rhs_bit);
1576 }
1577 lhs = new_lhs;
1578 rhs = new_rhs;
1579 }
1580 };
1581
1582 DeleteWireWorker delete_wire_worker;
1583 delete_wire_worker.module = this;
1584 delete_wire_worker.wires_p = &wires;
1585 rewrite_sigspecs2(delete_wire_worker);
1586
1587 for (auto &it : wires) {
1588 log_assert(wires_.count(it->name) != 0);
1589 wires_.erase(it->name);
1590 delete it;
1591 }
1592 }
1593
1594 void RTLIL::Module::remove(RTLIL::Cell *cell)
1595 {
1596 while (!cell->connections_.empty())
1597 cell->unsetPort(cell->connections_.begin()->first);
1598
1599 log_assert(cells_.count(cell->name) != 0);
1600 log_assert(refcount_cells_ == 0);
1601 cells_.erase(cell->name);
1602 delete cell;
1603 }
1604
1605 void RTLIL::Module::rename(RTLIL::Wire *wire, RTLIL::IdString new_name)
1606 {
1607 log_assert(wires_[wire->name] == wire);
1608 log_assert(refcount_wires_ == 0);
1609 wires_.erase(wire->name);
1610 wire->name = new_name;
1611 add(wire);
1612 }
1613
1614 void RTLIL::Module::rename(RTLIL::Cell *cell, RTLIL::IdString new_name)
1615 {
1616 log_assert(cells_[cell->name] == cell);
1617 log_assert(refcount_wires_ == 0);
1618 cells_.erase(cell->name);
1619 cell->name = new_name;
1620 add(cell);
1621 }
1622
1623 void RTLIL::Module::rename(RTLIL::IdString old_name, RTLIL::IdString new_name)
1624 {
1625 log_assert(count_id(old_name) != 0);
1626 if (wires_.count(old_name))
1627 rename(wires_.at(old_name), new_name);
1628 else if (cells_.count(old_name))
1629 rename(cells_.at(old_name), new_name);
1630 else
1631 log_abort();
1632 }
1633
1634 void RTLIL::Module::swap_names(RTLIL::Wire *w1, RTLIL::Wire *w2)
1635 {
1636 log_assert(wires_[w1->name] == w1);
1637 log_assert(wires_[w2->name] == w2);
1638 log_assert(refcount_wires_ == 0);
1639
1640 wires_.erase(w1->name);
1641 wires_.erase(w2->name);
1642
1643 std::swap(w1->name, w2->name);
1644
1645 wires_[w1->name] = w1;
1646 wires_[w2->name] = w2;
1647 }
1648
1649 void RTLIL::Module::swap_names(RTLIL::Cell *c1, RTLIL::Cell *c2)
1650 {
1651 log_assert(cells_[c1->name] == c1);
1652 log_assert(cells_[c2->name] == c2);
1653 log_assert(refcount_cells_ == 0);
1654
1655 cells_.erase(c1->name);
1656 cells_.erase(c2->name);
1657
1658 std::swap(c1->name, c2->name);
1659
1660 cells_[c1->name] = c1;
1661 cells_[c2->name] = c2;
1662 }
1663
1664 RTLIL::IdString RTLIL::Module::uniquify(RTLIL::IdString name)
1665 {
1666 int index = 0;
1667 return uniquify(name, index);
1668 }
1669
1670 RTLIL::IdString RTLIL::Module::uniquify(RTLIL::IdString name, int &index)
1671 {
1672 if (index == 0) {
1673 if (count_id(name) == 0)
1674 return name;
1675 index++;
1676 }
1677
1678 while (1) {
1679 RTLIL::IdString new_name = stringf("%s_%d", name.c_str(), index);
1680 if (count_id(new_name) == 0)
1681 return new_name;
1682 index++;
1683 }
1684 }
1685
1686 static bool fixup_ports_compare(const RTLIL::Wire *a, const RTLIL::Wire *b)
1687 {
1688 if (a->port_id && !b->port_id)
1689 return true;
1690 if (!a->port_id && b->port_id)
1691 return false;
1692
1693 if (a->port_id == b->port_id)
1694 return a->name < b->name;
1695 return a->port_id < b->port_id;
1696 }
1697
1698 void RTLIL::Module::connect(const RTLIL::SigSig &conn)
1699 {
1700 for (auto mon : monitors)
1701 mon->notify_connect(this, conn);
1702
1703 if (design)
1704 for (auto mon : design->monitors)
1705 mon->notify_connect(this, conn);
1706
1707 // ignore all attempts to assign constants to other constants
1708 if (conn.first.has_const()) {
1709 RTLIL::SigSig new_conn;
1710 for (int i = 0; i < GetSize(conn.first); i++)
1711 if (conn.first[i].wire) {
1712 new_conn.first.append(conn.first[i]);
1713 new_conn.second.append(conn.second[i]);
1714 }
1715 if (GetSize(new_conn.first))
1716 connect(new_conn);
1717 return;
1718 }
1719
1720 if (yosys_xtrace) {
1721 log("#X# Connect (SigSig) in %s: %s = %s (%d bits)\n", log_id(this), log_signal(conn.first), log_signal(conn.second), GetSize(conn.first));
1722 log_backtrace("-X- ", yosys_xtrace-1);
1723 }
1724
1725 log_assert(GetSize(conn.first) == GetSize(conn.second));
1726 connections_.push_back(conn);
1727 }
1728
1729 void RTLIL::Module::connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs)
1730 {
1731 connect(RTLIL::SigSig(lhs, rhs));
1732 }
1733
1734 void RTLIL::Module::new_connections(const std::vector<RTLIL::SigSig> &new_conn)
1735 {
1736 for (auto mon : monitors)
1737 mon->notify_connect(this, new_conn);
1738
1739 if (design)
1740 for (auto mon : design->monitors)
1741 mon->notify_connect(this, new_conn);
1742
1743 if (yosys_xtrace) {
1744 log("#X# New connections vector in %s:\n", log_id(this));
1745 for (auto &conn: new_conn)
1746 log("#X# %s = %s (%d bits)\n", log_signal(conn.first), log_signal(conn.second), GetSize(conn.first));
1747 log_backtrace("-X- ", yosys_xtrace-1);
1748 }
1749
1750 connections_ = new_conn;
1751 }
1752
1753 const std::vector<RTLIL::SigSig> &RTLIL::Module::connections() const
1754 {
1755 return connections_;
1756 }
1757
1758 void RTLIL::Module::fixup_ports()
1759 {
1760 std::vector<RTLIL::Wire*> all_ports;
1761
1762 for (auto &w : wires_)
1763 if (w.second->port_input || w.second->port_output)
1764 all_ports.push_back(w.second);
1765 else
1766 w.second->port_id = 0;
1767
1768 std::sort(all_ports.begin(), all_ports.end(), fixup_ports_compare);
1769
1770 ports.clear();
1771 for (size_t i = 0; i < all_ports.size(); i++) {
1772 ports.push_back(all_ports[i]->name);
1773 all_ports[i]->port_id = i+1;
1774 }
1775 }
1776
1777 RTLIL::Wire *RTLIL::Module::addWire(RTLIL::IdString name, int width)
1778 {
1779 RTLIL::Wire *wire = new RTLIL::Wire;
1780 wire->name = name;
1781 wire->width = width;
1782 add(wire);
1783 return wire;
1784 }
1785
1786 RTLIL::Wire *RTLIL::Module::addWire(RTLIL::IdString name, const RTLIL::Wire *other)
1787 {
1788 RTLIL::Wire *wire = addWire(name);
1789 wire->width = other->width;
1790 wire->start_offset = other->start_offset;
1791 wire->port_id = other->port_id;
1792 wire->port_input = other->port_input;
1793 wire->port_output = other->port_output;
1794 wire->upto = other->upto;
1795 wire->attributes = other->attributes;
1796 return wire;
1797 }
1798
1799 RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, RTLIL::IdString type)
1800 {
1801 RTLIL::Cell *cell = new RTLIL::Cell;
1802 cell->name = name;
1803 cell->type = type;
1804 add(cell);
1805 return cell;
1806 }
1807
1808 RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, const RTLIL::Cell *other)
1809 {
1810 RTLIL::Cell *cell = addCell(name, other->type);
1811 cell->connections_ = other->connections_;
1812 cell->parameters = other->parameters;
1813 cell->attributes = other->attributes;
1814 return cell;
1815 }
1816
1817 #define DEF_METHOD(_func, _y_size, _type) \
1818 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed, const std::string &src) { \
1819 RTLIL::Cell *cell = addCell(name, _type); \
1820 cell->parameters["\\A_SIGNED"] = is_signed; \
1821 cell->parameters["\\A_WIDTH"] = sig_a.size(); \
1822 cell->parameters["\\Y_WIDTH"] = sig_y.size(); \
1823 cell->setPort("\\A", sig_a); \
1824 cell->setPort("\\Y", sig_y); \
1825 cell->set_src_attribute(src); \
1826 return cell; \
1827 } \
1828 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed, const std::string &src) { \
1829 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
1830 add ## _func(name, sig_a, sig_y, is_signed, src); \
1831 return sig_y; \
1832 }
1833 DEF_METHOD(Not, sig_a.size(), "$not")
1834 DEF_METHOD(Pos, sig_a.size(), "$pos")
1835 DEF_METHOD(Neg, sig_a.size(), "$neg")
1836 DEF_METHOD(ReduceAnd, 1, "$reduce_and")
1837 DEF_METHOD(ReduceOr, 1, "$reduce_or")
1838 DEF_METHOD(ReduceXor, 1, "$reduce_xor")
1839 DEF_METHOD(ReduceXnor, 1, "$reduce_xnor")
1840 DEF_METHOD(ReduceBool, 1, "$reduce_bool")
1841 DEF_METHOD(LogicNot, 1, "$logic_not")
1842 #undef DEF_METHOD
1843
1844 #define DEF_METHOD(_func, _y_size, _type) \
1845 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed, const std::string &src) { \
1846 RTLIL::Cell *cell = addCell(name, _type); \
1847 cell->parameters["\\A_SIGNED"] = is_signed; \
1848 cell->parameters["\\B_SIGNED"] = is_signed; \
1849 cell->parameters["\\A_WIDTH"] = sig_a.size(); \
1850 cell->parameters["\\B_WIDTH"] = sig_b.size(); \
1851 cell->parameters["\\Y_WIDTH"] = sig_y.size(); \
1852 cell->setPort("\\A", sig_a); \
1853 cell->setPort("\\B", sig_b); \
1854 cell->setPort("\\Y", sig_y); \
1855 cell->set_src_attribute(src); \
1856 return cell; \
1857 } \
1858 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed, const std::string &src) { \
1859 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
1860 add ## _func(name, sig_a, sig_b, sig_y, is_signed, src); \
1861 return sig_y; \
1862 }
1863 DEF_METHOD(And, max(sig_a.size(), sig_b.size()), "$and")
1864 DEF_METHOD(Or, max(sig_a.size(), sig_b.size()), "$or")
1865 DEF_METHOD(Xor, max(sig_a.size(), sig_b.size()), "$xor")
1866 DEF_METHOD(Xnor, max(sig_a.size(), sig_b.size()), "$xnor")
1867 DEF_METHOD(Shl, sig_a.size(), "$shl")
1868 DEF_METHOD(Shr, sig_a.size(), "$shr")
1869 DEF_METHOD(Sshl, sig_a.size(), "$sshl")
1870 DEF_METHOD(Sshr, sig_a.size(), "$sshr")
1871 DEF_METHOD(Shift, sig_a.size(), "$shift")
1872 DEF_METHOD(Shiftx, sig_a.size(), "$shiftx")
1873 DEF_METHOD(Lt, 1, "$lt")
1874 DEF_METHOD(Le, 1, "$le")
1875 DEF_METHOD(Eq, 1, "$eq")
1876 DEF_METHOD(Ne, 1, "$ne")
1877 DEF_METHOD(Eqx, 1, "$eqx")
1878 DEF_METHOD(Nex, 1, "$nex")
1879 DEF_METHOD(Ge, 1, "$ge")
1880 DEF_METHOD(Gt, 1, "$gt")
1881 DEF_METHOD(Add, max(sig_a.size(), sig_b.size()), "$add")
1882 DEF_METHOD(Sub, max(sig_a.size(), sig_b.size()), "$sub")
1883 DEF_METHOD(Mul, max(sig_a.size(), sig_b.size()), "$mul")
1884 DEF_METHOD(Div, max(sig_a.size(), sig_b.size()), "$div")
1885 DEF_METHOD(Mod, max(sig_a.size(), sig_b.size()), "$mod")
1886 DEF_METHOD(LogicAnd, 1, "$logic_and")
1887 DEF_METHOD(LogicOr, 1, "$logic_or")
1888 #undef DEF_METHOD
1889
1890 #define DEF_METHOD(_func, _type, _pmux) \
1891 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, RTLIL::SigSpec sig_y, const std::string &src) { \
1892 RTLIL::Cell *cell = addCell(name, _type); \
1893 cell->parameters["\\WIDTH"] = sig_a.size(); \
1894 if (_pmux) cell->parameters["\\S_WIDTH"] = sig_s.size(); \
1895 cell->setPort("\\A", sig_a); \
1896 cell->setPort("\\B", sig_b); \
1897 cell->setPort("\\S", sig_s); \
1898 cell->setPort("\\Y", sig_y); \
1899 cell->set_src_attribute(src); \
1900 return cell; \
1901 } \
1902 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, const std::string &src) { \
1903 RTLIL::SigSpec sig_y = addWire(NEW_ID, sig_a.size()); \
1904 add ## _func(name, sig_a, sig_b, sig_s, sig_y, src); \
1905 return sig_y; \
1906 }
1907 DEF_METHOD(Mux, "$mux", 0)
1908 DEF_METHOD(Pmux, "$pmux", 1)
1909 #undef DEF_METHOD
1910
1911 #define DEF_METHOD_2(_func, _type, _P1, _P2) \
1912 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, const std::string &src) { \
1913 RTLIL::Cell *cell = addCell(name, _type); \
1914 cell->setPort("\\" #_P1, sig1); \
1915 cell->setPort("\\" #_P2, sig2); \
1916 cell->set_src_attribute(src); \
1917 return cell; \
1918 } \
1919 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, const std::string &src) { \
1920 RTLIL::SigBit sig2 = addWire(NEW_ID); \
1921 add ## _func(name, sig1, sig2, src); \
1922 return sig2; \
1923 }
1924 #define DEF_METHOD_3(_func, _type, _P1, _P2, _P3) \
1925 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, const std::string &src) { \
1926 RTLIL::Cell *cell = addCell(name, _type); \
1927 cell->setPort("\\" #_P1, sig1); \
1928 cell->setPort("\\" #_P2, sig2); \
1929 cell->setPort("\\" #_P3, sig3); \
1930 cell->set_src_attribute(src); \
1931 return cell; \
1932 } \
1933 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, const std::string &src) { \
1934 RTLIL::SigBit sig3 = addWire(NEW_ID); \
1935 add ## _func(name, sig1, sig2, sig3, src); \
1936 return sig3; \
1937 }
1938 #define DEF_METHOD_4(_func, _type, _P1, _P2, _P3, _P4) \
1939 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, RTLIL::SigBit sig4, const std::string &src) { \
1940 RTLIL::Cell *cell = addCell(name, _type); \
1941 cell->setPort("\\" #_P1, sig1); \
1942 cell->setPort("\\" #_P2, sig2); \
1943 cell->setPort("\\" #_P3, sig3); \
1944 cell->setPort("\\" #_P4, sig4); \
1945 cell->set_src_attribute(src); \
1946 return cell; \
1947 } \
1948 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, const std::string &src) { \
1949 RTLIL::SigBit sig4 = addWire(NEW_ID); \
1950 add ## _func(name, sig1, sig2, sig3, sig4, src); \
1951 return sig4; \
1952 }
1953 #define DEF_METHOD_5(_func, _type, _P1, _P2, _P3, _P4, _P5) \
1954 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, RTLIL::SigBit sig4, RTLIL::SigBit sig5, const std::string &src) { \
1955 RTLIL::Cell *cell = addCell(name, _type); \
1956 cell->setPort("\\" #_P1, sig1); \
1957 cell->setPort("\\" #_P2, sig2); \
1958 cell->setPort("\\" #_P3, sig3); \
1959 cell->setPort("\\" #_P4, sig4); \
1960 cell->setPort("\\" #_P5, sig5); \
1961 cell->set_src_attribute(src); \
1962 return cell; \
1963 } \
1964 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, RTLIL::SigBit sig4, const std::string &src) { \
1965 RTLIL::SigBit sig5 = addWire(NEW_ID); \
1966 add ## _func(name, sig1, sig2, sig3, sig4, sig5, src); \
1967 return sig5; \
1968 }
1969 DEF_METHOD_2(BufGate, "$_BUF_", A, Y)
1970 DEF_METHOD_2(NotGate, "$_NOT_", A, Y)
1971 DEF_METHOD_3(AndGate, "$_AND_", A, B, Y)
1972 DEF_METHOD_3(NandGate, "$_NAND_", A, B, Y)
1973 DEF_METHOD_3(OrGate, "$_OR_", A, B, Y)
1974 DEF_METHOD_3(NorGate, "$_NOR_", A, B, Y)
1975 DEF_METHOD_3(XorGate, "$_XOR_", A, B, Y)
1976 DEF_METHOD_3(XnorGate, "$_XNOR_", A, B, Y)
1977 DEF_METHOD_3(AndnotGate, "$_ANDNOT_", A, B, Y)
1978 DEF_METHOD_3(OrnotGate, "$_ORNOT_", A, B, Y)
1979 DEF_METHOD_4(MuxGate, "$_MUX_", A, B, S, Y)
1980 DEF_METHOD_4(NmuxGate, "$_NMUX_", A, B, S, Y)
1981 DEF_METHOD_4(Aoi3Gate, "$_AOI3_", A, B, C, Y)
1982 DEF_METHOD_4(Oai3Gate, "$_OAI3_", A, B, C, Y)
1983 DEF_METHOD_5(Aoi4Gate, "$_AOI4_", A, B, C, D, Y)
1984 DEF_METHOD_5(Oai4Gate, "$_OAI4_", A, B, C, D, Y)
1985 #undef DEF_METHOD_2
1986 #undef DEF_METHOD_3
1987 #undef DEF_METHOD_4
1988 #undef DEF_METHOD_5
1989
1990 RTLIL::Cell* RTLIL::Module::addPow(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool a_signed, bool b_signed, const std::string &src)
1991 {
1992 RTLIL::Cell *cell = addCell(name, "$pow");
1993 cell->parameters["\\A_SIGNED"] = a_signed;
1994 cell->parameters["\\B_SIGNED"] = b_signed;
1995 cell->parameters["\\A_WIDTH"] = sig_a.size();
1996 cell->parameters["\\B_WIDTH"] = sig_b.size();
1997 cell->parameters["\\Y_WIDTH"] = sig_y.size();
1998 cell->setPort("\\A", sig_a);
1999 cell->setPort("\\B", sig_b);
2000 cell->setPort("\\Y", sig_y);
2001 cell->set_src_attribute(src);
2002 return cell;
2003 }
2004
2005 RTLIL::Cell* RTLIL::Module::addSlice(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, RTLIL::Const offset, const std::string &src)
2006 {
2007 RTLIL::Cell *cell = addCell(name, "$slice");
2008 cell->parameters["\\A_WIDTH"] = sig_a.size();
2009 cell->parameters["\\Y_WIDTH"] = sig_y.size();
2010 cell->parameters["\\OFFSET"] = offset;
2011 cell->setPort("\\A", sig_a);
2012 cell->setPort("\\Y", sig_y);
2013 cell->set_src_attribute(src);
2014 return cell;
2015 }
2016
2017 RTLIL::Cell* RTLIL::Module::addConcat(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, const std::string &src)
2018 {
2019 RTLIL::Cell *cell = addCell(name, "$concat");
2020 cell->parameters["\\A_WIDTH"] = sig_a.size();
2021 cell->parameters["\\B_WIDTH"] = sig_b.size();
2022 cell->setPort("\\A", sig_a);
2023 cell->setPort("\\B", sig_b);
2024 cell->setPort("\\Y", sig_y);
2025 cell->set_src_attribute(src);
2026 return cell;
2027 }
2028
2029 RTLIL::Cell* RTLIL::Module::addLut(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, RTLIL::Const lut, const std::string &src)
2030 {
2031 RTLIL::Cell *cell = addCell(name, "$lut");
2032 cell->parameters["\\LUT"] = lut;
2033 cell->parameters["\\WIDTH"] = sig_a.size();
2034 cell->setPort("\\A", sig_a);
2035 cell->setPort("\\Y", sig_y);
2036 cell->set_src_attribute(src);
2037 return cell;
2038 }
2039
2040 RTLIL::Cell* RTLIL::Module::addTribuf(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_y, const std::string &src)
2041 {
2042 RTLIL::Cell *cell = addCell(name, "$tribuf");
2043 cell->parameters["\\WIDTH"] = sig_a.size();
2044 cell->setPort("\\A", sig_a);
2045 cell->setPort("\\EN", sig_en);
2046 cell->setPort("\\Y", sig_y);
2047 cell->set_src_attribute(src);
2048 return cell;
2049 }
2050
2051 RTLIL::Cell* RTLIL::Module::addAssert(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src)
2052 {
2053 RTLIL::Cell *cell = addCell(name, "$assert");
2054 cell->setPort("\\A", sig_a);
2055 cell->setPort("\\EN", sig_en);
2056 cell->set_src_attribute(src);
2057 return cell;
2058 }
2059
2060 RTLIL::Cell* RTLIL::Module::addAssume(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src)
2061 {
2062 RTLIL::Cell *cell = addCell(name, "$assume");
2063 cell->setPort("\\A", sig_a);
2064 cell->setPort("\\EN", sig_en);
2065 cell->set_src_attribute(src);
2066 return cell;
2067 }
2068
2069 RTLIL::Cell* RTLIL::Module::addLive(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src)
2070 {
2071 RTLIL::Cell *cell = addCell(name, "$live");
2072 cell->setPort("\\A", sig_a);
2073 cell->setPort("\\EN", sig_en);
2074 cell->set_src_attribute(src);
2075 return cell;
2076 }
2077
2078 RTLIL::Cell* RTLIL::Module::addFair(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src)
2079 {
2080 RTLIL::Cell *cell = addCell(name, "$fair");
2081 cell->setPort("\\A", sig_a);
2082 cell->setPort("\\EN", sig_en);
2083 cell->set_src_attribute(src);
2084 return cell;
2085 }
2086
2087 RTLIL::Cell* RTLIL::Module::addCover(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src)
2088 {
2089 RTLIL::Cell *cell = addCell(name, "$cover");
2090 cell->setPort("\\A", sig_a);
2091 cell->setPort("\\EN", sig_en);
2092 cell->set_src_attribute(src);
2093 return cell;
2094 }
2095
2096 RTLIL::Cell* RTLIL::Module::addEquiv(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, const std::string &src)
2097 {
2098 RTLIL::Cell *cell = addCell(name, "$equiv");
2099 cell->setPort("\\A", sig_a);
2100 cell->setPort("\\B", sig_b);
2101 cell->setPort("\\Y", sig_y);
2102 cell->set_src_attribute(src);
2103 return cell;
2104 }
2105
2106 RTLIL::Cell* RTLIL::Module::addSr(RTLIL::IdString name, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr, RTLIL::SigSpec sig_q, bool set_polarity, bool clr_polarity, const std::string &src)
2107 {
2108 RTLIL::Cell *cell = addCell(name, "$sr");
2109 cell->parameters["\\SET_POLARITY"] = set_polarity;
2110 cell->parameters["\\CLR_POLARITY"] = clr_polarity;
2111 cell->parameters["\\WIDTH"] = sig_q.size();
2112 cell->setPort("\\SET", sig_set);
2113 cell->setPort("\\CLR", sig_clr);
2114 cell->setPort("\\Q", sig_q);
2115 cell->set_src_attribute(src);
2116 return cell;
2117 }
2118
2119 RTLIL::Cell* RTLIL::Module::addFf(RTLIL::IdString name, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, const std::string &src)
2120 {
2121 RTLIL::Cell *cell = addCell(name, "$ff");
2122 cell->parameters["\\WIDTH"] = sig_q.size();
2123 cell->setPort("\\D", sig_d);
2124 cell->setPort("\\Q", sig_q);
2125 cell->set_src_attribute(src);
2126 return cell;
2127 }
2128
2129 RTLIL::Cell* RTLIL::Module::addDff(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, const std::string &src)
2130 {
2131 RTLIL::Cell *cell = addCell(name, "$dff");
2132 cell->parameters["\\CLK_POLARITY"] = clk_polarity;
2133 cell->parameters["\\WIDTH"] = sig_q.size();
2134 cell->setPort("\\CLK", sig_clk);
2135 cell->setPort("\\D", sig_d);
2136 cell->setPort("\\Q", sig_q);
2137 cell->set_src_attribute(src);
2138 return cell;
2139 }
2140
2141 RTLIL::Cell* RTLIL::Module::addDffe(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, bool en_polarity, const std::string &src)
2142 {
2143 RTLIL::Cell *cell = addCell(name, "$dffe");
2144 cell->parameters["\\CLK_POLARITY"] = clk_polarity;
2145 cell->parameters["\\EN_POLARITY"] = en_polarity;
2146 cell->parameters["\\WIDTH"] = sig_q.size();
2147 cell->setPort("\\CLK", sig_clk);
2148 cell->setPort("\\EN", sig_en);
2149 cell->setPort("\\D", sig_d);
2150 cell->setPort("\\Q", sig_q);
2151 cell->set_src_attribute(src);
2152 return cell;
2153 }
2154
2155 RTLIL::Cell* RTLIL::Module::addDffsr(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
2156 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
2157 {
2158 RTLIL::Cell *cell = addCell(name, "$dffsr");
2159 cell->parameters["\\CLK_POLARITY"] = clk_polarity;
2160 cell->parameters["\\SET_POLARITY"] = set_polarity;
2161 cell->parameters["\\CLR_POLARITY"] = clr_polarity;
2162 cell->parameters["\\WIDTH"] = sig_q.size();
2163 cell->setPort("\\CLK", sig_clk);
2164 cell->setPort("\\SET", sig_set);
2165 cell->setPort("\\CLR", sig_clr);
2166 cell->setPort("\\D", sig_d);
2167 cell->setPort("\\Q", sig_q);
2168 cell->set_src_attribute(src);
2169 return cell;
2170 }
2171
2172 RTLIL::Cell* RTLIL::Module::addAdff(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_arst, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q,
2173 RTLIL::Const arst_value, bool clk_polarity, bool arst_polarity, const std::string &src)
2174 {
2175 RTLIL::Cell *cell = addCell(name, "$adff");
2176 cell->parameters["\\CLK_POLARITY"] = clk_polarity;
2177 cell->parameters["\\ARST_POLARITY"] = arst_polarity;
2178 cell->parameters["\\ARST_VALUE"] = arst_value;
2179 cell->parameters["\\WIDTH"] = sig_q.size();
2180 cell->setPort("\\CLK", sig_clk);
2181 cell->setPort("\\ARST", sig_arst);
2182 cell->setPort("\\D", sig_d);
2183 cell->setPort("\\Q", sig_q);
2184 cell->set_src_attribute(src);
2185 return cell;
2186 }
2187
2188 RTLIL::Cell* RTLIL::Module::addDlatch(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity, const std::string &src)
2189 {
2190 RTLIL::Cell *cell = addCell(name, "$dlatch");
2191 cell->parameters["\\EN_POLARITY"] = en_polarity;
2192 cell->parameters["\\WIDTH"] = sig_q.size();
2193 cell->setPort("\\EN", sig_en);
2194 cell->setPort("\\D", sig_d);
2195 cell->setPort("\\Q", sig_q);
2196 cell->set_src_attribute(src);
2197 return cell;
2198 }
2199
2200 RTLIL::Cell* RTLIL::Module::addDlatchsr(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
2201 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
2202 {
2203 RTLIL::Cell *cell = addCell(name, "$dlatchsr");
2204 cell->parameters["\\EN_POLARITY"] = en_polarity;
2205 cell->parameters["\\SET_POLARITY"] = set_polarity;
2206 cell->parameters["\\CLR_POLARITY"] = clr_polarity;
2207 cell->parameters["\\WIDTH"] = sig_q.size();
2208 cell->setPort("\\EN", sig_en);
2209 cell->setPort("\\SET", sig_set);
2210 cell->setPort("\\CLR", sig_clr);
2211 cell->setPort("\\D", sig_d);
2212 cell->setPort("\\Q", sig_q);
2213 cell->set_src_attribute(src);
2214 return cell;
2215 }
2216
2217 RTLIL::Cell* RTLIL::Module::addFfGate(RTLIL::IdString name, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, const std::string &src)
2218 {
2219 RTLIL::Cell *cell = addCell(name, "$_FF_");
2220 cell->setPort("\\D", sig_d);
2221 cell->setPort("\\Q", sig_q);
2222 cell->set_src_attribute(src);
2223 return cell;
2224 }
2225
2226 RTLIL::Cell* RTLIL::Module::addDffGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, const std::string &src)
2227 {
2228 RTLIL::Cell *cell = addCell(name, stringf("$_DFF_%c_", clk_polarity ? 'P' : 'N'));
2229 cell->setPort("\\C", sig_clk);
2230 cell->setPort("\\D", sig_d);
2231 cell->setPort("\\Q", sig_q);
2232 cell->set_src_attribute(src);
2233 return cell;
2234 }
2235
2236 RTLIL::Cell* RTLIL::Module::addDffeGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, bool en_polarity, const std::string &src)
2237 {
2238 RTLIL::Cell *cell = addCell(name, stringf("$_DFFE_%c%c_", clk_polarity ? 'P' : 'N', en_polarity ? 'P' : 'N'));
2239 cell->setPort("\\C", sig_clk);
2240 cell->setPort("\\E", sig_en);
2241 cell->setPort("\\D", sig_d);
2242 cell->setPort("\\Q", sig_q);
2243 cell->set_src_attribute(src);
2244 return cell;
2245 }
2246
2247 RTLIL::Cell* RTLIL::Module::addDffsrGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
2248 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
2249 {
2250 RTLIL::Cell *cell = addCell(name, stringf("$_DFFSR_%c%c%c_", clk_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N'));
2251 cell->setPort("\\C", sig_clk);
2252 cell->setPort("\\S", sig_set);
2253 cell->setPort("\\R", sig_clr);
2254 cell->setPort("\\D", sig_d);
2255 cell->setPort("\\Q", sig_q);
2256 cell->set_src_attribute(src);
2257 return cell;
2258 }
2259
2260 RTLIL::Cell* RTLIL::Module::addAdffGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_arst, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q,
2261 bool arst_value, bool clk_polarity, bool arst_polarity, const std::string &src)
2262 {
2263 RTLIL::Cell *cell = addCell(name, stringf("$_DFF_%c%c%c_", clk_polarity ? 'P' : 'N', arst_polarity ? 'P' : 'N', arst_value ? '1' : '0'));
2264 cell->setPort("\\C", sig_clk);
2265 cell->setPort("\\R", sig_arst);
2266 cell->setPort("\\D", sig_d);
2267 cell->setPort("\\Q", sig_q);
2268 cell->set_src_attribute(src);
2269 return cell;
2270 }
2271
2272 RTLIL::Cell* RTLIL::Module::addDlatchGate(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity, const std::string &src)
2273 {
2274 RTLIL::Cell *cell = addCell(name, stringf("$_DLATCH_%c_", en_polarity ? 'P' : 'N'));
2275 cell->setPort("\\E", sig_en);
2276 cell->setPort("\\D", sig_d);
2277 cell->setPort("\\Q", sig_q);
2278 cell->set_src_attribute(src);
2279 return cell;
2280 }
2281
2282 RTLIL::Cell* RTLIL::Module::addDlatchsrGate(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
2283 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
2284 {
2285 RTLIL::Cell *cell = addCell(name, stringf("$_DLATCHSR_%c%c%c_", en_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N'));
2286 cell->setPort("\\E", sig_en);
2287 cell->setPort("\\S", sig_set);
2288 cell->setPort("\\R", sig_clr);
2289 cell->setPort("\\D", sig_d);
2290 cell->setPort("\\Q", sig_q);
2291 cell->set_src_attribute(src);
2292 return cell;
2293 }
2294
2295 RTLIL::SigSpec RTLIL::Module::Anyconst(RTLIL::IdString name, int width, const std::string &src)
2296 {
2297 RTLIL::SigSpec sig = addWire(NEW_ID, width);
2298 Cell *cell = addCell(name, "$anyconst");
2299 cell->setParam("\\WIDTH", width);
2300 cell->setPort("\\Y", sig);
2301 cell->set_src_attribute(src);
2302 return sig;
2303 }
2304
2305 RTLIL::SigSpec RTLIL::Module::Anyseq(RTLIL::IdString name, int width, const std::string &src)
2306 {
2307 RTLIL::SigSpec sig = addWire(NEW_ID, width);
2308 Cell *cell = addCell(name, "$anyseq");
2309 cell->setParam("\\WIDTH", width);
2310 cell->setPort("\\Y", sig);
2311 cell->set_src_attribute(src);
2312 return sig;
2313 }
2314
2315 RTLIL::SigSpec RTLIL::Module::Allconst(RTLIL::IdString name, int width, const std::string &src)
2316 {
2317 RTLIL::SigSpec sig = addWire(NEW_ID, width);
2318 Cell *cell = addCell(name, "$allconst");
2319 cell->setParam("\\WIDTH", width);
2320 cell->setPort("\\Y", sig);
2321 cell->set_src_attribute(src);
2322 return sig;
2323 }
2324
2325 RTLIL::SigSpec RTLIL::Module::Allseq(RTLIL::IdString name, int width, const std::string &src)
2326 {
2327 RTLIL::SigSpec sig = addWire(NEW_ID, width);
2328 Cell *cell = addCell(name, "$allseq");
2329 cell->setParam("\\WIDTH", width);
2330 cell->setPort("\\Y", sig);
2331 cell->set_src_attribute(src);
2332 return sig;
2333 }
2334
2335 RTLIL::SigSpec RTLIL::Module::Initstate(RTLIL::IdString name, const std::string &src)
2336 {
2337 RTLIL::SigSpec sig = addWire(NEW_ID);
2338 Cell *cell = addCell(name, "$initstate");
2339 cell->setPort("\\Y", sig);
2340 cell->set_src_attribute(src);
2341 return sig;
2342 }
2343
2344 RTLIL::Wire::Wire()
2345 {
2346 static unsigned int hashidx_count = 123456789;
2347 hashidx_count = mkhash_xorshift(hashidx_count);
2348 hashidx_ = hashidx_count;
2349
2350 module = nullptr;
2351 width = 1;
2352 start_offset = 0;
2353 port_id = 0;
2354 port_input = false;
2355 port_output = false;
2356 upto = false;
2357
2358 #ifdef WITH_PYTHON
2359 RTLIL::Wire::get_all_wires()->insert(std::pair<unsigned int, RTLIL::Wire*>(hashidx_, this));
2360 #endif
2361 }
2362
2363 RTLIL::Wire::~Wire()
2364 {
2365 #ifdef WITH_PYTHON
2366 RTLIL::Wire::get_all_wires()->erase(hashidx_);
2367 #endif
2368 }
2369
2370 #ifdef WITH_PYTHON
2371 static std::map<unsigned int, RTLIL::Wire*> all_wires;
2372 std::map<unsigned int, RTLIL::Wire*> *RTLIL::Wire::get_all_wires(void)
2373 {
2374 return &all_wires;
2375 }
2376 #endif
2377
2378 RTLIL::Memory::Memory()
2379 {
2380 static unsigned int hashidx_count = 123456789;
2381 hashidx_count = mkhash_xorshift(hashidx_count);
2382 hashidx_ = hashidx_count;
2383
2384 width = 1;
2385 start_offset = 0;
2386 size = 0;
2387 #ifdef WITH_PYTHON
2388 RTLIL::Memory::get_all_memorys()->insert(std::pair<unsigned int, RTLIL::Memory*>(hashidx_, this));
2389 #endif
2390 }
2391
2392 RTLIL::Cell::Cell() : module(nullptr)
2393 {
2394 static unsigned int hashidx_count = 123456789;
2395 hashidx_count = mkhash_xorshift(hashidx_count);
2396 hashidx_ = hashidx_count;
2397
2398 // log("#memtrace# %p\n", this);
2399 memhasher();
2400
2401 #ifdef WITH_PYTHON
2402 RTLIL::Cell::get_all_cells()->insert(std::pair<unsigned int, RTLIL::Cell*>(hashidx_, this));
2403 #endif
2404 }
2405
2406 RTLIL::Cell::~Cell()
2407 {
2408 #ifdef WITH_PYTHON
2409 RTLIL::Cell::get_all_cells()->erase(hashidx_);
2410 #endif
2411 }
2412
2413 #ifdef WITH_PYTHON
2414 static std::map<unsigned int, RTLIL::Cell*> all_cells;
2415 std::map<unsigned int, RTLIL::Cell*> *RTLIL::Cell::get_all_cells(void)
2416 {
2417 return &all_cells;
2418 }
2419 #endif
2420
2421 bool RTLIL::Cell::hasPort(RTLIL::IdString portname) const
2422 {
2423 return connections_.count(portname) != 0;
2424 }
2425
2426 void RTLIL::Cell::unsetPort(RTLIL::IdString portname)
2427 {
2428 RTLIL::SigSpec signal;
2429 auto conn_it = connections_.find(portname);
2430
2431 if (conn_it != connections_.end())
2432 {
2433 for (auto mon : module->monitors)
2434 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
2435
2436 if (module->design)
2437 for (auto mon : module->design->monitors)
2438 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
2439
2440 if (yosys_xtrace) {
2441 log("#X# Unconnect %s.%s.%s\n", log_id(this->module), log_id(this), log_id(portname));
2442 log_backtrace("-X- ", yosys_xtrace-1);
2443 }
2444
2445 connections_.erase(conn_it);
2446 }
2447 }
2448
2449 void RTLIL::Cell::setPort(RTLIL::IdString portname, RTLIL::SigSpec signal)
2450 {
2451 auto conn_it = connections_.find(portname);
2452
2453 if (conn_it == connections_.end()) {
2454 connections_[portname] = RTLIL::SigSpec();
2455 conn_it = connections_.find(portname);
2456 log_assert(conn_it != connections_.end());
2457 } else
2458 if (conn_it->second == signal)
2459 return;
2460
2461 for (auto mon : module->monitors)
2462 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
2463
2464 if (module->design)
2465 for (auto mon : module->design->monitors)
2466 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
2467
2468 if (yosys_xtrace) {
2469 log("#X# Connect %s.%s.%s = %s (%d)\n", log_id(this->module), log_id(this), log_id(portname), log_signal(signal), GetSize(signal));
2470 log_backtrace("-X- ", yosys_xtrace-1);
2471 }
2472
2473 conn_it->second = signal;
2474 }
2475
2476 const RTLIL::SigSpec &RTLIL::Cell::getPort(RTLIL::IdString portname) const
2477 {
2478 return connections_.at(portname);
2479 }
2480
2481 const dict<RTLIL::IdString, RTLIL::SigSpec> &RTLIL::Cell::connections() const
2482 {
2483 return connections_;
2484 }
2485
2486 bool RTLIL::Cell::known() const
2487 {
2488 if (yosys_celltypes.cell_known(type))
2489 return true;
2490 if (module && module->design && module->design->module(type))
2491 return true;
2492 return false;
2493 }
2494
2495 bool RTLIL::Cell::input(RTLIL::IdString portname) const
2496 {
2497 if (yosys_celltypes.cell_known(type))
2498 return yosys_celltypes.cell_input(type, portname);
2499 if (module && module->design) {
2500 RTLIL::Module *m = module->design->module(type);
2501 RTLIL::Wire *w = m ? m->wire(portname) : nullptr;
2502 return w && w->port_input;
2503 }
2504 return false;
2505 }
2506
2507 bool RTLIL::Cell::output(RTLIL::IdString portname) const
2508 {
2509 if (yosys_celltypes.cell_known(type))
2510 return yosys_celltypes.cell_output(type, portname);
2511 if (module && module->design) {
2512 RTLIL::Module *m = module->design->module(type);
2513 RTLIL::Wire *w = m ? m->wire(portname) : nullptr;
2514 return w && w->port_output;
2515 }
2516 return false;
2517 }
2518
2519 bool RTLIL::Cell::hasParam(RTLIL::IdString paramname) const
2520 {
2521 return parameters.count(paramname) != 0;
2522 }
2523
2524 void RTLIL::Cell::unsetParam(RTLIL::IdString paramname)
2525 {
2526 parameters.erase(paramname);
2527 }
2528
2529 void RTLIL::Cell::setParam(RTLIL::IdString paramname, RTLIL::Const value)
2530 {
2531 parameters[paramname] = value;
2532 }
2533
2534 const RTLIL::Const &RTLIL::Cell::getParam(RTLIL::IdString paramname) const
2535 {
2536 return parameters.at(paramname);
2537 }
2538
2539 void RTLIL::Cell::sort()
2540 {
2541 connections_.sort(sort_by_id_str());
2542 parameters.sort(sort_by_id_str());
2543 attributes.sort(sort_by_id_str());
2544 }
2545
2546 void RTLIL::Cell::check()
2547 {
2548 #ifndef NDEBUG
2549 InternalCellChecker checker(NULL, this);
2550 checker.check();
2551 #endif
2552 }
2553
2554 void RTLIL::Cell::fixup_parameters(bool set_a_signed, bool set_b_signed)
2555 {
2556 if (type.substr(0, 1) != "$" || type.substr(0, 2) == "$_" || type.substr(0, 8) == "$paramod" || type.substr(0,10) == "$fmcombine" ||
2557 type.substr(0, 9) == "$verific$" || type.substr(0, 7) == "$array:" || type.substr(0, 8) == "$extern:")
2558 return;
2559
2560 if (type == "$mux" || type == "$pmux") {
2561 parameters["\\WIDTH"] = GetSize(connections_["\\Y"]);
2562 if (type == "$pmux")
2563 parameters["\\S_WIDTH"] = GetSize(connections_["\\S"]);
2564 check();
2565 return;
2566 }
2567
2568 if (type == "$lut" || type == "$sop") {
2569 parameters["\\WIDTH"] = GetSize(connections_["\\A"]);
2570 return;
2571 }
2572
2573 if (type == "$fa") {
2574 parameters["\\WIDTH"] = GetSize(connections_["\\Y"]);
2575 return;
2576 }
2577
2578 if (type == "$lcu") {
2579 parameters["\\WIDTH"] = GetSize(connections_["\\CO"]);
2580 return;
2581 }
2582
2583 bool signedness_ab = !type.in("$slice", "$concat", "$macc");
2584
2585 if (connections_.count("\\A")) {
2586 if (signedness_ab) {
2587 if (set_a_signed)
2588 parameters["\\A_SIGNED"] = true;
2589 else if (parameters.count("\\A_SIGNED") == 0)
2590 parameters["\\A_SIGNED"] = false;
2591 }
2592 parameters["\\A_WIDTH"] = GetSize(connections_["\\A"]);
2593 }
2594
2595 if (connections_.count("\\B")) {
2596 if (signedness_ab) {
2597 if (set_b_signed)
2598 parameters["\\B_SIGNED"] = true;
2599 else if (parameters.count("\\B_SIGNED") == 0)
2600 parameters["\\B_SIGNED"] = false;
2601 }
2602 parameters["\\B_WIDTH"] = GetSize(connections_["\\B"]);
2603 }
2604
2605 if (connections_.count("\\Y"))
2606 parameters["\\Y_WIDTH"] = GetSize(connections_["\\Y"]);
2607
2608 if (connections_.count("\\Q"))
2609 parameters["\\WIDTH"] = GetSize(connections_["\\Q"]);
2610
2611 check();
2612 }
2613
2614 RTLIL::SigChunk::SigChunk()
2615 {
2616 wire = NULL;
2617 width = 0;
2618 offset = 0;
2619 }
2620
2621 RTLIL::SigChunk::SigChunk(const RTLIL::Const &value)
2622 {
2623 wire = NULL;
2624 data = value.bits;
2625 width = GetSize(data);
2626 offset = 0;
2627 }
2628
2629 RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire)
2630 {
2631 log_assert(wire != nullptr);
2632 this->wire = wire;
2633 this->width = wire->width;
2634 this->offset = 0;
2635 }
2636
2637 RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire, int offset, int width)
2638 {
2639 log_assert(wire != nullptr);
2640 this->wire = wire;
2641 this->width = width;
2642 this->offset = offset;
2643 }
2644
2645 RTLIL::SigChunk::SigChunk(const std::string &str)
2646 {
2647 wire = NULL;
2648 data = RTLIL::Const(str).bits;
2649 width = GetSize(data);
2650 offset = 0;
2651 }
2652
2653 RTLIL::SigChunk::SigChunk(int val, int width)
2654 {
2655 wire = NULL;
2656 data = RTLIL::Const(val, width).bits;
2657 this->width = GetSize(data);
2658 offset = 0;
2659 }
2660
2661 RTLIL::SigChunk::SigChunk(RTLIL::State bit, int width)
2662 {
2663 wire = NULL;
2664 data = RTLIL::Const(bit, width).bits;
2665 this->width = GetSize(data);
2666 offset = 0;
2667 }
2668
2669 RTLIL::SigChunk::SigChunk(RTLIL::SigBit bit)
2670 {
2671 wire = bit.wire;
2672 offset = 0;
2673 if (wire == NULL)
2674 data = RTLIL::Const(bit.data).bits;
2675 else
2676 offset = bit.offset;
2677 width = 1;
2678 }
2679
2680 RTLIL::SigChunk::SigChunk(const RTLIL::SigChunk &sigchunk) : data(sigchunk.data)
2681 {
2682 wire = sigchunk.wire;
2683 data = sigchunk.data;
2684 width = sigchunk.width;
2685 offset = sigchunk.offset;
2686 }
2687
2688 RTLIL::SigChunk RTLIL::SigChunk::extract(int offset, int length) const
2689 {
2690 RTLIL::SigChunk ret;
2691 if (wire) {
2692 ret.wire = wire;
2693 ret.offset = this->offset + offset;
2694 ret.width = length;
2695 } else {
2696 for (int i = 0; i < length; i++)
2697 ret.data.push_back(data[offset+i]);
2698 ret.width = length;
2699 }
2700 return ret;
2701 }
2702
2703 bool RTLIL::SigChunk::operator <(const RTLIL::SigChunk &other) const
2704 {
2705 if (wire && other.wire)
2706 if (wire->name != other.wire->name)
2707 return wire->name < other.wire->name;
2708
2709 if (wire != other.wire)
2710 return wire < other.wire;
2711
2712 if (offset != other.offset)
2713 return offset < other.offset;
2714
2715 if (width != other.width)
2716 return width < other.width;
2717
2718 return data < other.data;
2719 }
2720
2721 bool RTLIL::SigChunk::operator ==(const RTLIL::SigChunk &other) const
2722 {
2723 return wire == other.wire && width == other.width && offset == other.offset && data == other.data;
2724 }
2725
2726 bool RTLIL::SigChunk::operator !=(const RTLIL::SigChunk &other) const
2727 {
2728 if (*this == other)
2729 return false;
2730 return true;
2731 }
2732
2733 RTLIL::SigSpec::SigSpec()
2734 {
2735 width_ = 0;
2736 hash_ = 0;
2737 }
2738
2739 RTLIL::SigSpec::SigSpec(const RTLIL::SigSpec &other)
2740 {
2741 *this = other;
2742 }
2743
2744 RTLIL::SigSpec::SigSpec(std::initializer_list<RTLIL::SigSpec> parts)
2745 {
2746 cover("kernel.rtlil.sigspec.init.list");
2747
2748 width_ = 0;
2749 hash_ = 0;
2750
2751 std::vector<RTLIL::SigSpec> parts_vec(parts.begin(), parts.end());
2752 for (auto it = parts_vec.rbegin(); it != parts_vec.rend(); it++)
2753 append(*it);
2754 }
2755
2756 const RTLIL::SigSpec &RTLIL::SigSpec::operator=(const RTLIL::SigSpec &other)
2757 {
2758 cover("kernel.rtlil.sigspec.assign");
2759
2760 width_ = other.width_;
2761 hash_ = other.hash_;
2762 chunks_ = other.chunks_;
2763 bits_.clear();
2764
2765 if (!other.bits_.empty())
2766 {
2767 RTLIL::SigChunk *last = NULL;
2768 int last_end_offset = 0;
2769
2770 for (auto &bit : other.bits_) {
2771 if (last && bit.wire == last->wire) {
2772 if (bit.wire == NULL) {
2773 last->data.push_back(bit.data);
2774 last->width++;
2775 continue;
2776 } else if (last_end_offset == bit.offset) {
2777 last_end_offset++;
2778 last->width++;
2779 continue;
2780 }
2781 }
2782 chunks_.push_back(bit);
2783 last = &chunks_.back();
2784 last_end_offset = bit.offset + 1;
2785 }
2786
2787 check();
2788 }
2789
2790 return *this;
2791 }
2792
2793 RTLIL::SigSpec::SigSpec(const RTLIL::Const &value)
2794 {
2795 cover("kernel.rtlil.sigspec.init.const");
2796
2797 chunks_.push_back(RTLIL::SigChunk(value));
2798 width_ = chunks_.back().width;
2799 hash_ = 0;
2800 check();
2801 }
2802
2803 RTLIL::SigSpec::SigSpec(const RTLIL::SigChunk &chunk)
2804 {
2805 cover("kernel.rtlil.sigspec.init.chunk");
2806
2807 chunks_.push_back(chunk);
2808 width_ = chunks_.back().width;
2809 hash_ = 0;
2810 check();
2811 }
2812
2813 RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire)
2814 {
2815 cover("kernel.rtlil.sigspec.init.wire");
2816
2817 chunks_.push_back(RTLIL::SigChunk(wire));
2818 width_ = chunks_.back().width;
2819 hash_ = 0;
2820 check();
2821 }
2822
2823 RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire, int offset, int width)
2824 {
2825 cover("kernel.rtlil.sigspec.init.wire_part");
2826
2827 chunks_.push_back(RTLIL::SigChunk(wire, offset, width));
2828 width_ = chunks_.back().width;
2829 hash_ = 0;
2830 check();
2831 }
2832
2833 RTLIL::SigSpec::SigSpec(const std::string &str)
2834 {
2835 cover("kernel.rtlil.sigspec.init.str");
2836
2837 chunks_.push_back(RTLIL::SigChunk(str));
2838 width_ = chunks_.back().width;
2839 hash_ = 0;
2840 check();
2841 }
2842
2843 RTLIL::SigSpec::SigSpec(int val, int width)
2844 {
2845 cover("kernel.rtlil.sigspec.init.int");
2846
2847 chunks_.push_back(RTLIL::SigChunk(val, width));
2848 width_ = width;
2849 hash_ = 0;
2850 check();
2851 }
2852
2853 RTLIL::SigSpec::SigSpec(RTLIL::State bit, int width)
2854 {
2855 cover("kernel.rtlil.sigspec.init.state");
2856
2857 chunks_.push_back(RTLIL::SigChunk(bit, width));
2858 width_ = width;
2859 hash_ = 0;
2860 check();
2861 }
2862
2863 RTLIL::SigSpec::SigSpec(RTLIL::SigBit bit, int width)
2864 {
2865 cover("kernel.rtlil.sigspec.init.bit");
2866
2867 if (bit.wire == NULL)
2868 chunks_.push_back(RTLIL::SigChunk(bit.data, width));
2869 else
2870 for (int i = 0; i < width; i++)
2871 chunks_.push_back(bit);
2872 width_ = width;
2873 hash_ = 0;
2874 check();
2875 }
2876
2877 RTLIL::SigSpec::SigSpec(std::vector<RTLIL::SigChunk> chunks)
2878 {
2879 cover("kernel.rtlil.sigspec.init.stdvec_chunks");
2880
2881 width_ = 0;
2882 hash_ = 0;
2883 for (auto &c : chunks)
2884 append(c);
2885 check();
2886 }
2887
2888 RTLIL::SigSpec::SigSpec(std::vector<RTLIL::SigBit> bits)
2889 {
2890 cover("kernel.rtlil.sigspec.init.stdvec_bits");
2891
2892 width_ = 0;
2893 hash_ = 0;
2894 for (auto &bit : bits)
2895 append_bit(bit);
2896 check();
2897 }
2898
2899 RTLIL::SigSpec::SigSpec(pool<RTLIL::SigBit> bits)
2900 {
2901 cover("kernel.rtlil.sigspec.init.pool_bits");
2902
2903 width_ = 0;
2904 hash_ = 0;
2905 for (auto &bit : bits)
2906 append_bit(bit);
2907 check();
2908 }
2909
2910 RTLIL::SigSpec::SigSpec(std::set<RTLIL::SigBit> bits)
2911 {
2912 cover("kernel.rtlil.sigspec.init.stdset_bits");
2913
2914 width_ = 0;
2915 hash_ = 0;
2916 for (auto &bit : bits)
2917 append_bit(bit);
2918 check();
2919 }
2920
2921 RTLIL::SigSpec::SigSpec(bool bit)
2922 {
2923 cover("kernel.rtlil.sigspec.init.bool");
2924
2925 width_ = 0;
2926 hash_ = 0;
2927 append_bit(bit);
2928 check();
2929 }
2930
2931 void RTLIL::SigSpec::pack() const
2932 {
2933 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
2934
2935 if (that->bits_.empty())
2936 return;
2937
2938 cover("kernel.rtlil.sigspec.convert.pack");
2939 log_assert(that->chunks_.empty());
2940
2941 std::vector<RTLIL::SigBit> old_bits;
2942 old_bits.swap(that->bits_);
2943
2944 RTLIL::SigChunk *last = NULL;
2945 int last_end_offset = 0;
2946
2947 for (auto &bit : old_bits) {
2948 if (last && bit.wire == last->wire) {
2949 if (bit.wire == NULL) {
2950 last->data.push_back(bit.data);
2951 last->width++;
2952 continue;
2953 } else if (last_end_offset == bit.offset) {
2954 last_end_offset++;
2955 last->width++;
2956 continue;
2957 }
2958 }
2959 that->chunks_.push_back(bit);
2960 last = &that->chunks_.back();
2961 last_end_offset = bit.offset + 1;
2962 }
2963
2964 check();
2965 }
2966
2967 void RTLIL::SigSpec::unpack() const
2968 {
2969 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
2970
2971 if (that->chunks_.empty())
2972 return;
2973
2974 cover("kernel.rtlil.sigspec.convert.unpack");
2975 log_assert(that->bits_.empty());
2976
2977 that->bits_.reserve(that->width_);
2978 for (auto &c : that->chunks_)
2979 for (int i = 0; i < c.width; i++)
2980 that->bits_.push_back(RTLIL::SigBit(c, i));
2981
2982 that->chunks_.clear();
2983 that->hash_ = 0;
2984 }
2985
2986 void RTLIL::SigSpec::updhash() const
2987 {
2988 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
2989
2990 if (that->hash_ != 0)
2991 return;
2992
2993 cover("kernel.rtlil.sigspec.hash");
2994 that->pack();
2995
2996 that->hash_ = mkhash_init;
2997 for (auto &c : that->chunks_)
2998 if (c.wire == NULL) {
2999 for (auto &v : c.data)
3000 that->hash_ = mkhash(that->hash_, v);
3001 } else {
3002 that->hash_ = mkhash(that->hash_, c.wire->name.index_);
3003 that->hash_ = mkhash(that->hash_, c.offset);
3004 that->hash_ = mkhash(that->hash_, c.width);
3005 }
3006
3007 if (that->hash_ == 0)
3008 that->hash_ = 1;
3009 }
3010
3011 void RTLIL::SigSpec::sort()
3012 {
3013 unpack();
3014 cover("kernel.rtlil.sigspec.sort");
3015 std::sort(bits_.begin(), bits_.end());
3016 }
3017
3018 void RTLIL::SigSpec::sort_and_unify()
3019 {
3020 unpack();
3021 cover("kernel.rtlil.sigspec.sort_and_unify");
3022
3023 // A copy of the bits vector is used to prevent duplicating the logic from
3024 // SigSpec::SigSpec(std::vector<SigBit>). This incurrs an extra copy but
3025 // that isn't showing up as significant in profiles.
3026 std::vector<SigBit> unique_bits = bits_;
3027 std::sort(unique_bits.begin(), unique_bits.end());
3028 auto last = std::unique(unique_bits.begin(), unique_bits.end());
3029 unique_bits.erase(last, unique_bits.end());
3030
3031 *this = unique_bits;
3032 }
3033
3034 void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with)
3035 {
3036 replace(pattern, with, this);
3037 }
3038
3039 void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with, RTLIL::SigSpec *other) const
3040 {
3041 log_assert(other != NULL);
3042 log_assert(width_ == other->width_);
3043 log_assert(pattern.width_ == with.width_);
3044
3045 pattern.unpack();
3046 with.unpack();
3047 unpack();
3048 other->unpack();
3049
3050 for (int i = 0; i < GetSize(pattern.bits_); i++) {
3051 if (pattern.bits_[i].wire != NULL) {
3052 for (int j = 0; j < GetSize(bits_); j++) {
3053 if (bits_[j] == pattern.bits_[i]) {
3054 other->bits_[j] = with.bits_[i];
3055 }
3056 }
3057 }
3058 }
3059
3060 other->check();
3061 }
3062
3063 void RTLIL::SigSpec::replace(const dict<RTLIL::SigBit, RTLIL::SigBit> &rules)
3064 {
3065 replace(rules, this);
3066 }
3067
3068 void RTLIL::SigSpec::replace(const dict<RTLIL::SigBit, RTLIL::SigBit> &rules, RTLIL::SigSpec *other) const
3069 {
3070 cover("kernel.rtlil.sigspec.replace_dict");
3071
3072 log_assert(other != NULL);
3073 log_assert(width_ == other->width_);
3074
3075 unpack();
3076 other->unpack();
3077
3078 for (int i = 0; i < GetSize(bits_); i++) {
3079 auto it = rules.find(bits_[i]);
3080 if (it != rules.end())
3081 other->bits_[i] = it->second;
3082 }
3083
3084 other->check();
3085 }
3086
3087 void RTLIL::SigSpec::replace(const std::map<RTLIL::SigBit, RTLIL::SigBit> &rules)
3088 {
3089 replace(rules, this);
3090 }
3091
3092 void RTLIL::SigSpec::replace(const std::map<RTLIL::SigBit, RTLIL::SigBit> &rules, RTLIL::SigSpec *other) const
3093 {
3094 cover("kernel.rtlil.sigspec.replace_map");
3095
3096 log_assert(other != NULL);
3097 log_assert(width_ == other->width_);
3098
3099 unpack();
3100 other->unpack();
3101
3102 for (int i = 0; i < GetSize(bits_); i++) {
3103 auto it = rules.find(bits_[i]);
3104 if (it != rules.end())
3105 other->bits_[i] = it->second;
3106 }
3107
3108 other->check();
3109 }
3110
3111 void RTLIL::SigSpec::remove(const RTLIL::SigSpec &pattern)
3112 {
3113 remove2(pattern, NULL);
3114 }
3115
3116 void RTLIL::SigSpec::remove(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other) const
3117 {
3118 RTLIL::SigSpec tmp = *this;
3119 tmp.remove2(pattern, other);
3120 }
3121
3122 void RTLIL::SigSpec::remove2(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other)
3123 {
3124 if (other)
3125 cover("kernel.rtlil.sigspec.remove_other");
3126 else
3127 cover("kernel.rtlil.sigspec.remove");
3128
3129 unpack();
3130 if (other != NULL) {
3131 log_assert(width_ == other->width_);
3132 other->unpack();
3133 }
3134
3135 for (int i = GetSize(bits_) - 1; i >= 0; i--)
3136 {
3137 if (bits_[i].wire == NULL) continue;
3138
3139 for (auto &pattern_chunk : pattern.chunks())
3140 if (bits_[i].wire == pattern_chunk.wire &&
3141 bits_[i].offset >= pattern_chunk.offset &&
3142 bits_[i].offset < pattern_chunk.offset + pattern_chunk.width) {
3143 bits_.erase(bits_.begin() + i);
3144 width_--;
3145 if (other != NULL) {
3146 other->bits_.erase(other->bits_.begin() + i);
3147 other->width_--;
3148 }
3149 break;
3150 }
3151 }
3152
3153 check();
3154 }
3155
3156 void RTLIL::SigSpec::remove(const pool<RTLIL::SigBit> &pattern)
3157 {
3158 remove2(pattern, NULL);
3159 }
3160
3161 void RTLIL::SigSpec::remove(const pool<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other) const
3162 {
3163 RTLIL::SigSpec tmp = *this;
3164 tmp.remove2(pattern, other);
3165 }
3166
3167 void RTLIL::SigSpec::remove2(const pool<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other)
3168 {
3169 if (other)
3170 cover("kernel.rtlil.sigspec.remove_other");
3171 else
3172 cover("kernel.rtlil.sigspec.remove");
3173
3174 unpack();
3175
3176 if (other != NULL) {
3177 log_assert(width_ == other->width_);
3178 other->unpack();
3179 }
3180
3181 for (int i = GetSize(bits_) - 1; i >= 0; i--) {
3182 if (bits_[i].wire != NULL && pattern.count(bits_[i])) {
3183 bits_.erase(bits_.begin() + i);
3184 width_--;
3185 if (other != NULL) {
3186 other->bits_.erase(other->bits_.begin() + i);
3187 other->width_--;
3188 }
3189 }
3190 }
3191
3192 check();
3193 }
3194
3195 void RTLIL::SigSpec::remove2(const std::set<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other)
3196 {
3197 if (other)
3198 cover("kernel.rtlil.sigspec.remove_other");
3199 else
3200 cover("kernel.rtlil.sigspec.remove");
3201
3202 unpack();
3203
3204 if (other != NULL) {
3205 log_assert(width_ == other->width_);
3206 other->unpack();
3207 }
3208
3209 for (int i = GetSize(bits_) - 1; i >= 0; i--) {
3210 if (bits_[i].wire != NULL && pattern.count(bits_[i])) {
3211 bits_.erase(bits_.begin() + i);
3212 width_--;
3213 if (other != NULL) {
3214 other->bits_.erase(other->bits_.begin() + i);
3215 other->width_--;
3216 }
3217 }
3218 }
3219
3220 check();
3221 }
3222
3223 RTLIL::SigSpec RTLIL::SigSpec::extract(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec *other) const
3224 {
3225 if (other)
3226 cover("kernel.rtlil.sigspec.extract_other");
3227 else
3228 cover("kernel.rtlil.sigspec.extract");
3229
3230 log_assert(other == NULL || width_ == other->width_);
3231
3232 RTLIL::SigSpec ret;
3233 std::vector<RTLIL::SigBit> bits_match = to_sigbit_vector();
3234
3235 for (auto& pattern_chunk : pattern.chunks()) {
3236 if (other) {
3237 std::vector<RTLIL::SigBit> bits_other = other->to_sigbit_vector();
3238 for (int i = 0; i < width_; i++)
3239 if (bits_match[i].wire &&
3240 bits_match[i].wire == pattern_chunk.wire &&
3241 bits_match[i].offset >= pattern_chunk.offset &&
3242 bits_match[i].offset < pattern_chunk.offset + pattern_chunk.width)
3243 ret.append_bit(bits_other[i]);
3244 } else {
3245 for (int i = 0; i < width_; i++)
3246 if (bits_match[i].wire &&
3247 bits_match[i].wire == pattern_chunk.wire &&
3248 bits_match[i].offset >= pattern_chunk.offset &&
3249 bits_match[i].offset < pattern_chunk.offset + pattern_chunk.width)
3250 ret.append_bit(bits_match[i]);
3251 }
3252 }
3253
3254 ret.check();
3255 return ret;
3256 }
3257
3258 RTLIL::SigSpec RTLIL::SigSpec::extract(const pool<RTLIL::SigBit> &pattern, const RTLIL::SigSpec *other) const
3259 {
3260 if (other)
3261 cover("kernel.rtlil.sigspec.extract_other");
3262 else
3263 cover("kernel.rtlil.sigspec.extract");
3264
3265 log_assert(other == NULL || width_ == other->width_);
3266
3267 std::vector<RTLIL::SigBit> bits_match = to_sigbit_vector();
3268 RTLIL::SigSpec ret;
3269
3270 if (other) {
3271 std::vector<RTLIL::SigBit> bits_other = other->to_sigbit_vector();
3272 for (int i = 0; i < width_; i++)
3273 if (bits_match[i].wire && pattern.count(bits_match[i]))
3274 ret.append_bit(bits_other[i]);
3275 } else {
3276 for (int i = 0; i < width_; i++)
3277 if (bits_match[i].wire && pattern.count(bits_match[i]))
3278 ret.append_bit(bits_match[i]);
3279 }
3280
3281 ret.check();
3282 return ret;
3283 }
3284
3285 void RTLIL::SigSpec::replace(int offset, const RTLIL::SigSpec &with)
3286 {
3287 cover("kernel.rtlil.sigspec.replace_pos");
3288
3289 unpack();
3290 with.unpack();
3291
3292 log_assert(offset >= 0);
3293 log_assert(with.width_ >= 0);
3294 log_assert(offset+with.width_ <= width_);
3295
3296 for (int i = 0; i < with.width_; i++)
3297 bits_.at(offset + i) = with.bits_.at(i);
3298
3299 check();
3300 }
3301
3302 RTLIL::SigSpec& RTLIL::SigSpec::remove_const()
3303 {
3304 if (packed())
3305 {
3306 cover("kernel.rtlil.sigspec.remove_const.packed");
3307
3308 std::vector<RTLIL::SigChunk> new_chunks;
3309 new_chunks.reserve(GetSize(chunks_));
3310
3311 width_ = 0;
3312 for (auto &chunk : chunks_)
3313 if (chunk.wire != NULL) {
3314 new_chunks.push_back(chunk);
3315 width_ += chunk.width;
3316 }
3317
3318 chunks_.swap(new_chunks);
3319 }
3320 else
3321 {
3322 cover("kernel.rtlil.sigspec.remove_const.unpacked");
3323
3324 std::vector<RTLIL::SigBit> new_bits;
3325 new_bits.reserve(width_);
3326
3327 for (auto &bit : bits_)
3328 if (bit.wire != NULL)
3329 new_bits.push_back(bit);
3330
3331 bits_.swap(new_bits);
3332 width_ = bits_.size();
3333 }
3334
3335 check();
3336 return *this;
3337 }
3338
3339 void RTLIL::SigSpec::remove(int offset, int length)
3340 {
3341 cover("kernel.rtlil.sigspec.remove_pos");
3342
3343 unpack();
3344
3345 log_assert(offset >= 0);
3346 log_assert(length >= 0);
3347 log_assert(offset + length <= width_);
3348
3349 bits_.erase(bits_.begin() + offset, bits_.begin() + offset + length);
3350 width_ = bits_.size();
3351
3352 check();
3353 }
3354
3355 RTLIL::SigSpec RTLIL::SigSpec::extract(int offset, int length) const
3356 {
3357 unpack();
3358 cover("kernel.rtlil.sigspec.extract_pos");
3359 return std::vector<RTLIL::SigBit>(bits_.begin() + offset, bits_.begin() + offset + length);
3360 }
3361
3362 void RTLIL::SigSpec::append(const RTLIL::SigSpec &signal)
3363 {
3364 if (signal.width_ == 0)
3365 return;
3366
3367 if (width_ == 0) {
3368 *this = signal;
3369 return;
3370 }
3371
3372 cover("kernel.rtlil.sigspec.append");
3373
3374 if (packed() != signal.packed()) {
3375 pack();
3376 signal.pack();
3377 }
3378
3379 if (packed())
3380 for (auto &other_c : signal.chunks_)
3381 {
3382 auto &my_last_c = chunks_.back();
3383 if (my_last_c.wire == NULL && other_c.wire == NULL) {
3384 auto &this_data = my_last_c.data;
3385 auto &other_data = other_c.data;
3386 this_data.insert(this_data.end(), other_data.begin(), other_data.end());
3387 my_last_c.width += other_c.width;
3388 } else
3389 if (my_last_c.wire == other_c.wire && my_last_c.offset + my_last_c.width == other_c.offset) {
3390 my_last_c.width += other_c.width;
3391 } else
3392 chunks_.push_back(other_c);
3393 }
3394 else
3395 bits_.insert(bits_.end(), signal.bits_.begin(), signal.bits_.end());
3396
3397 width_ += signal.width_;
3398 check();
3399 }
3400
3401 void RTLIL::SigSpec::append_bit(const RTLIL::SigBit &bit)
3402 {
3403 if (packed())
3404 {
3405 cover("kernel.rtlil.sigspec.append_bit.packed");
3406
3407 if (chunks_.size() == 0)
3408 chunks_.push_back(bit);
3409 else
3410 if (bit.wire == NULL)
3411 if (chunks_.back().wire == NULL) {
3412 chunks_.back().data.push_back(bit.data);
3413 chunks_.back().width++;
3414 } else
3415 chunks_.push_back(bit);
3416 else
3417 if (chunks_.back().wire == bit.wire && chunks_.back().offset + chunks_.back().width == bit.offset)
3418 chunks_.back().width++;
3419 else
3420 chunks_.push_back(bit);
3421 }
3422 else
3423 {
3424 cover("kernel.rtlil.sigspec.append_bit.unpacked");
3425 bits_.push_back(bit);
3426 }
3427
3428 width_++;
3429 check();
3430 }
3431
3432 RTLIL::SigSpec& RTLIL::SigSpec::extend_u0(int width, bool is_signed)
3433 {
3434 cover("kernel.rtlil.sigspec.extend_u0");
3435
3436 pack();
3437
3438 if (width_ > width)
3439 remove(width, width_ - width);
3440
3441 if (width_ < width) {
3442 RTLIL::SigBit padding = width_ > 0 ? (*this)[width_ - 1] : RTLIL::State::Sx;
3443 if (!is_signed)
3444 padding = RTLIL::State::S0;
3445 while (width_ < width)
3446 append(padding);
3447 }
3448
3449 return *this;
3450 }
3451
3452 RTLIL::SigSpec RTLIL::SigSpec::repeat(int num) const
3453 {
3454 cover("kernel.rtlil.sigspec.repeat");
3455
3456 RTLIL::SigSpec sig;
3457 for (int i = 0; i < num; i++)
3458 sig.append(*this);
3459 return sig;
3460 }
3461
3462 #ifndef NDEBUG
3463 void RTLIL::SigSpec::check() const
3464 {
3465 if (width_ > 64)
3466 {
3467 cover("kernel.rtlil.sigspec.check.skip");
3468 }
3469 else if (packed())
3470 {
3471 cover("kernel.rtlil.sigspec.check.packed");
3472
3473 int w = 0;
3474 for (size_t i = 0; i < chunks_.size(); i++) {
3475 const RTLIL::SigChunk chunk = chunks_[i];
3476 if (chunk.wire == NULL) {
3477 if (i > 0)
3478 log_assert(chunks_[i-1].wire != NULL);
3479 log_assert(chunk.offset == 0);
3480 log_assert(chunk.data.size() == (size_t)chunk.width);
3481 } else {
3482 if (i > 0 && chunks_[i-1].wire == chunk.wire)
3483 log_assert(chunk.offset != chunks_[i-1].offset + chunks_[i-1].width);
3484 log_assert(chunk.offset >= 0);
3485 log_assert(chunk.width >= 0);
3486 log_assert(chunk.offset + chunk.width <= chunk.wire->width);
3487 log_assert(chunk.data.size() == 0);
3488 }
3489 w += chunk.width;
3490 }
3491 log_assert(w == width_);
3492 log_assert(bits_.empty());
3493 }
3494 else
3495 {
3496 cover("kernel.rtlil.sigspec.check.unpacked");
3497
3498 log_assert(width_ == GetSize(bits_));
3499 log_assert(chunks_.empty());
3500 }
3501 }
3502 #endif
3503
3504 bool RTLIL::SigSpec::operator <(const RTLIL::SigSpec &other) const
3505 {
3506 cover("kernel.rtlil.sigspec.comp_lt");
3507
3508 if (this == &other)
3509 return false;
3510
3511 if (width_ != other.width_)
3512 return width_ < other.width_;
3513
3514 pack();
3515 other.pack();
3516
3517 if (chunks_.size() != other.chunks_.size())
3518 return chunks_.size() < other.chunks_.size();
3519
3520 updhash();
3521 other.updhash();
3522
3523 if (hash_ != other.hash_)
3524 return hash_ < other.hash_;
3525
3526 for (size_t i = 0; i < chunks_.size(); i++)
3527 if (chunks_[i] != other.chunks_[i]) {
3528 cover("kernel.rtlil.sigspec.comp_lt.hash_collision");
3529 return chunks_[i] < other.chunks_[i];
3530 }
3531
3532 cover("kernel.rtlil.sigspec.comp_lt.equal");
3533 return false;
3534 }
3535
3536 bool RTLIL::SigSpec::operator ==(const RTLIL::SigSpec &other) const
3537 {
3538 cover("kernel.rtlil.sigspec.comp_eq");
3539
3540 if (this == &other)
3541 return true;
3542
3543 if (width_ != other.width_)
3544 return false;
3545
3546 pack();
3547 other.pack();
3548
3549 if (chunks_.size() != other.chunks_.size())
3550 return false;
3551
3552 updhash();
3553 other.updhash();
3554
3555 if (hash_ != other.hash_)
3556 return false;
3557
3558 for (size_t i = 0; i < chunks_.size(); i++)
3559 if (chunks_[i] != other.chunks_[i]) {
3560 cover("kernel.rtlil.sigspec.comp_eq.hash_collision");
3561 return false;
3562 }
3563
3564 cover("kernel.rtlil.sigspec.comp_eq.equal");
3565 return true;
3566 }
3567
3568 bool RTLIL::SigSpec::is_wire() const
3569 {
3570 cover("kernel.rtlil.sigspec.is_wire");
3571
3572 pack();
3573 return GetSize(chunks_) == 1 && chunks_[0].wire && chunks_[0].wire->width == width_;
3574 }
3575
3576 bool RTLIL::SigSpec::is_chunk() const
3577 {
3578 cover("kernel.rtlil.sigspec.is_chunk");
3579
3580 pack();
3581 return GetSize(chunks_) == 1;
3582 }
3583
3584 bool RTLIL::SigSpec::is_fully_const() const
3585 {
3586 cover("kernel.rtlil.sigspec.is_fully_const");
3587
3588 pack();
3589 for (auto it = chunks_.begin(); it != chunks_.end(); it++)
3590 if (it->width > 0 && it->wire != NULL)
3591 return false;
3592 return true;
3593 }
3594
3595 bool RTLIL::SigSpec::is_fully_zero() const
3596 {
3597 cover("kernel.rtlil.sigspec.is_fully_zero");
3598
3599 pack();
3600 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
3601 if (it->width > 0 && it->wire != NULL)
3602 return false;
3603 for (size_t i = 0; i < it->data.size(); i++)
3604 if (it->data[i] != RTLIL::State::S0)
3605 return false;
3606 }
3607 return true;
3608 }
3609
3610 bool RTLIL::SigSpec::is_fully_ones() const
3611 {
3612 cover("kernel.rtlil.sigspec.is_fully_ones");
3613
3614 pack();
3615 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
3616 if (it->width > 0 && it->wire != NULL)
3617 return false;
3618 for (size_t i = 0; i < it->data.size(); i++)
3619 if (it->data[i] != RTLIL::State::S1)
3620 return false;
3621 }
3622 return true;
3623 }
3624
3625 bool RTLIL::SigSpec::is_fully_def() const
3626 {
3627 cover("kernel.rtlil.sigspec.is_fully_def");
3628
3629 pack();
3630 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
3631 if (it->width > 0 && it->wire != NULL)
3632 return false;
3633 for (size_t i = 0; i < it->data.size(); i++)
3634 if (it->data[i] != RTLIL::State::S0 && it->data[i] != RTLIL::State::S1)
3635 return false;
3636 }
3637 return true;
3638 }
3639
3640 bool RTLIL::SigSpec::is_fully_undef() const
3641 {
3642 cover("kernel.rtlil.sigspec.is_fully_undef");
3643
3644 pack();
3645 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
3646 if (it->width > 0 && it->wire != NULL)
3647 return false;
3648 for (size_t i = 0; i < it->data.size(); i++)
3649 if (it->data[i] != RTLIL::State::Sx && it->data[i] != RTLIL::State::Sz)
3650 return false;
3651 }
3652 return true;
3653 }
3654
3655 bool RTLIL::SigSpec::has_const() const
3656 {
3657 cover("kernel.rtlil.sigspec.has_const");
3658
3659 pack();
3660 for (auto it = chunks_.begin(); it != chunks_.end(); it++)
3661 if (it->width > 0 && it->wire == NULL)
3662 return true;
3663 return false;
3664 }
3665
3666 bool RTLIL::SigSpec::has_marked_bits() const
3667 {
3668 cover("kernel.rtlil.sigspec.has_marked_bits");
3669
3670 pack();
3671 for (auto it = chunks_.begin(); it != chunks_.end(); it++)
3672 if (it->width > 0 && it->wire == NULL) {
3673 for (size_t i = 0; i < it->data.size(); i++)
3674 if (it->data[i] == RTLIL::State::Sm)
3675 return true;
3676 }
3677 return false;
3678 }
3679
3680 bool RTLIL::SigSpec::as_bool() const
3681 {
3682 cover("kernel.rtlil.sigspec.as_bool");
3683
3684 pack();
3685 log_assert(is_fully_const() && GetSize(chunks_) <= 1);
3686 if (width_)
3687 return RTLIL::Const(chunks_[0].data).as_bool();
3688 return false;
3689 }
3690
3691 int RTLIL::SigSpec::as_int(bool is_signed) const
3692 {
3693 cover("kernel.rtlil.sigspec.as_int");
3694
3695 pack();
3696 log_assert(is_fully_const() && GetSize(chunks_) <= 1);
3697 if (width_)
3698 return RTLIL::Const(chunks_[0].data).as_int(is_signed);
3699 return 0;
3700 }
3701
3702 std::string RTLIL::SigSpec::as_string() const
3703 {
3704 cover("kernel.rtlil.sigspec.as_string");
3705
3706 pack();
3707 std::string str;
3708 for (size_t i = chunks_.size(); i > 0; i--) {
3709 const RTLIL::SigChunk &chunk = chunks_[i-1];
3710 if (chunk.wire != NULL)
3711 for (int j = 0; j < chunk.width; j++)
3712 str += "?";
3713 else
3714 str += RTLIL::Const(chunk.data).as_string();
3715 }
3716 return str;
3717 }
3718
3719 RTLIL::Const RTLIL::SigSpec::as_const() const
3720 {
3721 cover("kernel.rtlil.sigspec.as_const");
3722
3723 pack();
3724 log_assert(is_fully_const() && GetSize(chunks_) <= 1);
3725 if (width_)
3726 return chunks_[0].data;
3727 return RTLIL::Const();
3728 }
3729
3730 RTLIL::Wire *RTLIL::SigSpec::as_wire() const
3731 {
3732 cover("kernel.rtlil.sigspec.as_wire");
3733
3734 pack();
3735 log_assert(is_wire());
3736 return chunks_[0].wire;
3737 }
3738
3739 RTLIL::SigChunk RTLIL::SigSpec::as_chunk() const
3740 {
3741 cover("kernel.rtlil.sigspec.as_chunk");
3742
3743 pack();
3744 log_assert(is_chunk());
3745 return chunks_[0];
3746 }
3747
3748 RTLIL::SigBit RTLIL::SigSpec::as_bit() const
3749 {
3750 cover("kernel.rtlil.sigspec.as_bit");
3751
3752 log_assert(width_ == 1);
3753 if (packed())
3754 return RTLIL::SigBit(*chunks_.begin());
3755 else
3756 return bits_[0];
3757 }
3758
3759 bool RTLIL::SigSpec::match(std::string pattern) const
3760 {
3761 cover("kernel.rtlil.sigspec.match");
3762
3763 pack();
3764 std::string str = as_string();
3765 log_assert(pattern.size() == str.size());
3766
3767 for (size_t i = 0; i < pattern.size(); i++) {
3768 if (pattern[i] == ' ')
3769 continue;
3770 if (pattern[i] == '*') {
3771 if (str[i] != 'z' && str[i] != 'x')
3772 return false;
3773 continue;
3774 }
3775 if (pattern[i] != str[i])
3776 return false;
3777 }
3778
3779 return true;
3780 }
3781
3782 std::set<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_set() const
3783 {
3784 cover("kernel.rtlil.sigspec.to_sigbit_set");
3785
3786 pack();
3787 std::set<RTLIL::SigBit> sigbits;
3788 for (auto &c : chunks_)
3789 for (int i = 0; i < c.width; i++)
3790 sigbits.insert(RTLIL::SigBit(c, i));
3791 return sigbits;
3792 }
3793
3794 pool<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_pool() const
3795 {
3796 cover("kernel.rtlil.sigspec.to_sigbit_pool");
3797
3798 pack();
3799 pool<RTLIL::SigBit> sigbits;
3800 for (auto &c : chunks_)
3801 for (int i = 0; i < c.width; i++)
3802 sigbits.insert(RTLIL::SigBit(c, i));
3803 return sigbits;
3804 }
3805
3806 std::vector<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_vector() const
3807 {
3808 cover("kernel.rtlil.sigspec.to_sigbit_vector");
3809
3810 unpack();
3811 return bits_;
3812 }
3813
3814 std::map<RTLIL::SigBit, RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_map(const RTLIL::SigSpec &other) const
3815 {
3816 cover("kernel.rtlil.sigspec.to_sigbit_map");
3817
3818 unpack();
3819 other.unpack();
3820
3821 log_assert(width_ == other.width_);
3822
3823 std::map<RTLIL::SigBit, RTLIL::SigBit> new_map;
3824 for (int i = 0; i < width_; i++)
3825 new_map[bits_[i]] = other.bits_[i];
3826
3827 return new_map;
3828 }
3829
3830 dict<RTLIL::SigBit, RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_dict(const RTLIL::SigSpec &other) const
3831 {
3832 cover("kernel.rtlil.sigspec.to_sigbit_dict");
3833
3834 unpack();
3835 other.unpack();
3836
3837 log_assert(width_ == other.width_);
3838
3839 dict<RTLIL::SigBit, RTLIL::SigBit> new_map;
3840 for (int i = 0; i < width_; i++)
3841 new_map[bits_[i]] = other.bits_[i];
3842
3843 return new_map;
3844 }
3845
3846 static void sigspec_parse_split(std::vector<std::string> &tokens, const std::string &text, char sep)
3847 {
3848 size_t start = 0, end = 0;
3849 while ((end = text.find(sep, start)) != std::string::npos) {
3850 tokens.push_back(text.substr(start, end - start));
3851 start = end + 1;
3852 }
3853 tokens.push_back(text.substr(start));
3854 }
3855
3856 static int sigspec_parse_get_dummy_line_num()
3857 {
3858 return 0;
3859 }
3860
3861 bool RTLIL::SigSpec::parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str)
3862 {
3863 cover("kernel.rtlil.sigspec.parse");
3864
3865 AST::current_filename = "input";
3866 AST::use_internal_line_num();
3867 AST::set_line_num(0);
3868
3869 std::vector<std::string> tokens;
3870 sigspec_parse_split(tokens, str, ',');
3871
3872 sig = RTLIL::SigSpec();
3873 for (int tokidx = int(tokens.size())-1; tokidx >= 0; tokidx--)
3874 {
3875 std::string netname = tokens[tokidx];
3876 std::string indices;
3877
3878 if (netname.size() == 0)
3879 continue;
3880
3881 if (('0' <= netname[0] && netname[0] <= '9') || netname[0] == '\'') {
3882 cover("kernel.rtlil.sigspec.parse.const");
3883 AST::get_line_num = sigspec_parse_get_dummy_line_num;
3884 AST::AstNode *ast = VERILOG_FRONTEND::const2ast(netname);
3885 if (ast == NULL)
3886 return false;
3887 sig.append(RTLIL::Const(ast->bits));
3888 delete ast;
3889 continue;
3890 }
3891
3892 if (module == NULL)
3893 return false;
3894
3895 cover("kernel.rtlil.sigspec.parse.net");
3896
3897 if (netname[0] != '$' && netname[0] != '\\')
3898 netname = "\\" + netname;
3899
3900 if (module->wires_.count(netname) == 0) {
3901 size_t indices_pos = netname.size()-1;
3902 if (indices_pos > 2 && netname[indices_pos] == ']')
3903 {
3904 indices_pos--;
3905 while (indices_pos > 0 && ('0' <= netname[indices_pos] && netname[indices_pos] <= '9')) indices_pos--;
3906 if (indices_pos > 0 && netname[indices_pos] == ':') {
3907 indices_pos--;
3908 while (indices_pos > 0 && ('0' <= netname[indices_pos] && netname[indices_pos] <= '9')) indices_pos--;
3909 }
3910 if (indices_pos > 0 && netname[indices_pos] == '[') {
3911 indices = netname.substr(indices_pos);
3912 netname = netname.substr(0, indices_pos);
3913 }
3914 }
3915 }
3916
3917 if (module->wires_.count(netname) == 0)
3918 return false;
3919
3920 RTLIL::Wire *wire = module->wires_.at(netname);
3921 if (!indices.empty()) {
3922 std::vector<std::string> index_tokens;
3923 sigspec_parse_split(index_tokens, indices.substr(1, indices.size()-2), ':');
3924 if (index_tokens.size() == 1) {
3925 cover("kernel.rtlil.sigspec.parse.bit_sel");
3926 int a = atoi(index_tokens.at(0).c_str());
3927 if (a < 0 || a >= wire->width)
3928 return false;
3929 sig.append(RTLIL::SigSpec(wire, a));
3930 } else {
3931 cover("kernel.rtlil.sigspec.parse.part_sel");
3932 int a = atoi(index_tokens.at(0).c_str());
3933 int b = atoi(index_tokens.at(1).c_str());
3934 if (a > b) {
3935 int tmp = a;
3936 a = b, b = tmp;
3937 }
3938 if (a < 0 || a >= wire->width)
3939 return false;
3940 if (b < 0 || b >= wire->width)
3941 return false;
3942 sig.append(RTLIL::SigSpec(wire, a, b-a+1));
3943 }
3944 } else
3945 sig.append(wire);
3946 }
3947
3948 return true;
3949 }
3950
3951 bool RTLIL::SigSpec::parse_sel(RTLIL::SigSpec &sig, RTLIL::Design *design, RTLIL::Module *module, std::string str)
3952 {
3953 if (str.empty() || str[0] != '@')
3954 return parse(sig, module, str);
3955
3956 cover("kernel.rtlil.sigspec.parse.sel");
3957
3958 str = RTLIL::escape_id(str.substr(1));
3959 if (design->selection_vars.count(str) == 0)
3960 return false;
3961
3962 sig = RTLIL::SigSpec();
3963 RTLIL::Selection &sel = design->selection_vars.at(str);
3964 for (auto &it : module->wires_)
3965 if (sel.selected_member(module->name, it.first))
3966 sig.append(it.second);
3967
3968 return true;
3969 }
3970
3971 bool RTLIL::SigSpec::parse_rhs(const RTLIL::SigSpec &lhs, RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str)
3972 {
3973 if (str == "0") {
3974 cover("kernel.rtlil.sigspec.parse.rhs_zeros");
3975 sig = RTLIL::SigSpec(RTLIL::State::S0, lhs.width_);
3976 return true;
3977 }
3978
3979 if (str == "~0") {
3980 cover("kernel.rtlil.sigspec.parse.rhs_ones");
3981 sig = RTLIL::SigSpec(RTLIL::State::S1, lhs.width_);
3982 return true;
3983 }
3984
3985 if (lhs.chunks_.size() == 1) {
3986 char *p = (char*)str.c_str(), *endptr;
3987 long int val = strtol(p, &endptr, 10);
3988 if (endptr && endptr != p && *endptr == 0) {
3989 sig = RTLIL::SigSpec(val, lhs.width_);
3990 cover("kernel.rtlil.sigspec.parse.rhs_dec");
3991 return true;
3992 }
3993 }
3994
3995 return parse(sig, module, str);
3996 }
3997
3998 RTLIL::CaseRule::~CaseRule()
3999 {
4000 for (auto it = switches.begin(); it != switches.end(); it++)
4001 delete *it;
4002 }
4003
4004 bool RTLIL::CaseRule::empty() const
4005 {
4006 return actions.empty() && switches.empty();
4007 }
4008
4009 RTLIL::CaseRule *RTLIL::CaseRule::clone() const
4010 {
4011 RTLIL::CaseRule *new_caserule = new RTLIL::CaseRule;
4012 new_caserule->compare = compare;
4013 new_caserule->actions = actions;
4014 for (auto &it : switches)
4015 new_caserule->switches.push_back(it->clone());
4016 return new_caserule;
4017 }
4018
4019 RTLIL::SwitchRule::~SwitchRule()
4020 {
4021 for (auto it = cases.begin(); it != cases.end(); it++)
4022 delete *it;
4023 }
4024
4025 bool RTLIL::SwitchRule::empty() const
4026 {
4027 return cases.empty();
4028 }
4029
4030 RTLIL::SwitchRule *RTLIL::SwitchRule::clone() const
4031 {
4032 RTLIL::SwitchRule *new_switchrule = new RTLIL::SwitchRule;
4033 new_switchrule->signal = signal;
4034 new_switchrule->attributes = attributes;
4035 for (auto &it : cases)
4036 new_switchrule->cases.push_back(it->clone());
4037 return new_switchrule;
4038
4039 }
4040
4041 RTLIL::SyncRule *RTLIL::SyncRule::clone() const
4042 {
4043 RTLIL::SyncRule *new_syncrule = new RTLIL::SyncRule;
4044 new_syncrule->type = type;
4045 new_syncrule->signal = signal;
4046 new_syncrule->actions = actions;
4047 return new_syncrule;
4048 }
4049
4050 RTLIL::Process::~Process()
4051 {
4052 for (auto it = syncs.begin(); it != syncs.end(); it++)
4053 delete *it;
4054 }
4055
4056 RTLIL::Process *RTLIL::Process::clone() const
4057 {
4058 RTLIL::Process *new_proc = new RTLIL::Process;
4059
4060 new_proc->name = name;
4061 new_proc->attributes = attributes;
4062
4063 RTLIL::CaseRule *rc_ptr = root_case.clone();
4064 new_proc->root_case = *rc_ptr;
4065 rc_ptr->switches.clear();
4066 delete rc_ptr;
4067
4068 for (auto &it : syncs)
4069 new_proc->syncs.push_back(it->clone());
4070
4071 return new_proc;
4072 }
4073
4074 #ifdef WITH_PYTHON
4075 RTLIL::Memory::~Memory()
4076 {
4077 RTLIL::Memory::get_all_memorys()->erase(hashidx_);
4078 }
4079 static std::map<unsigned int, RTLIL::Memory*> all_memorys;
4080 std::map<unsigned int, RTLIL::Memory*> *RTLIL::Memory::get_all_memorys(void)
4081 {
4082 return &all_memorys;
4083 }
4084 #endif
4085 YOSYS_NAMESPACE_END