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Merge remote-tracking branch 'origin/master' into xc7mux
[yosys.git] / kernel / rtlil.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 #include "kernel/yosys.h"
21 #include "kernel/macc.h"
22 #include "kernel/celltypes.h"
23 #include "frontends/verilog/verilog_frontend.h"
24 #include "backends/ilang/ilang_backend.h"
25
26 #include <string.h>
27 #include <algorithm>
28
29 YOSYS_NAMESPACE_BEGIN
30
31 RTLIL::IdString::destruct_guard_t RTLIL::IdString::destruct_guard;
32 std::vector<int> RTLIL::IdString::global_refcount_storage_;
33 std::vector<char*> RTLIL::IdString::global_id_storage_;
34 dict<char*, int, hash_cstr_ops> RTLIL::IdString::global_id_index_;
35 std::vector<int> RTLIL::IdString::global_free_idx_list_;
36 int RTLIL::IdString::last_created_idx_[8];
37 int RTLIL::IdString::last_created_idx_ptr_;
38
39 RTLIL::Const::Const()
40 {
41 flags = RTLIL::CONST_FLAG_NONE;
42 }
43
44 RTLIL::Const::Const(std::string str)
45 {
46 flags = RTLIL::CONST_FLAG_STRING;
47 for (int i = str.size()-1; i >= 0; i--) {
48 unsigned char ch = str[i];
49 for (int j = 0; j < 8; j++) {
50 bits.push_back((ch & 1) != 0 ? RTLIL::S1 : RTLIL::S0);
51 ch = ch >> 1;
52 }
53 }
54 }
55
56 RTLIL::Const::Const(int val, int width)
57 {
58 flags = RTLIL::CONST_FLAG_NONE;
59 for (int i = 0; i < width; i++) {
60 bits.push_back((val & 1) != 0 ? RTLIL::S1 : RTLIL::S0);
61 val = val >> 1;
62 }
63 }
64
65 RTLIL::Const::Const(RTLIL::State bit, int width)
66 {
67 flags = RTLIL::CONST_FLAG_NONE;
68 for (int i = 0; i < width; i++)
69 bits.push_back(bit);
70 }
71
72 RTLIL::Const::Const(const std::vector<bool> &bits)
73 {
74 flags = RTLIL::CONST_FLAG_NONE;
75 for (auto b : bits)
76 this->bits.push_back(b ? RTLIL::S1 : RTLIL::S0);
77 }
78
79 RTLIL::Const::Const(const RTLIL::Const &c)
80 {
81 flags = c.flags;
82 for (auto b : c.bits)
83 this->bits.push_back(b);
84 }
85
86 bool RTLIL::Const::operator <(const RTLIL::Const &other) const
87 {
88 if (bits.size() != other.bits.size())
89 return bits.size() < other.bits.size();
90 for (size_t i = 0; i < bits.size(); i++)
91 if (bits[i] != other.bits[i])
92 return bits[i] < other.bits[i];
93 return false;
94 }
95
96 bool RTLIL::Const::operator ==(const RTLIL::Const &other) const
97 {
98 return bits == other.bits;
99 }
100
101 bool RTLIL::Const::operator !=(const RTLIL::Const &other) const
102 {
103 return bits != other.bits;
104 }
105
106 bool RTLIL::Const::as_bool() const
107 {
108 for (size_t i = 0; i < bits.size(); i++)
109 if (bits[i] == RTLIL::S1)
110 return true;
111 return false;
112 }
113
114 int RTLIL::Const::as_int(bool is_signed) const
115 {
116 int32_t ret = 0;
117 for (size_t i = 0; i < bits.size() && i < 32; i++)
118 if (bits[i] == RTLIL::S1)
119 ret |= 1 << i;
120 if (is_signed && bits.back() == RTLIL::S1)
121 for (size_t i = bits.size(); i < 32; i++)
122 ret |= 1 << i;
123 return ret;
124 }
125
126 std::string RTLIL::Const::as_string() const
127 {
128 std::string ret;
129 for (size_t i = bits.size(); i > 0; i--)
130 switch (bits[i-1]) {
131 case S0: ret += "0"; break;
132 case S1: ret += "1"; break;
133 case Sx: ret += "x"; break;
134 case Sz: ret += "z"; break;
135 case Sa: ret += "-"; break;
136 case Sm: ret += "m"; break;
137 }
138 return ret;
139 }
140
141 RTLIL::Const RTLIL::Const::from_string(std::string str)
142 {
143 Const c;
144 for (auto it = str.rbegin(); it != str.rend(); it++)
145 switch (*it) {
146 case '0': c.bits.push_back(State::S0); break;
147 case '1': c.bits.push_back(State::S1); break;
148 case 'x': c.bits.push_back(State::Sx); break;
149 case 'z': c.bits.push_back(State::Sz); break;
150 case 'm': c.bits.push_back(State::Sm); break;
151 default: c.bits.push_back(State::Sa);
152 }
153 return c;
154 }
155
156 std::string RTLIL::Const::decode_string() const
157 {
158 std::string string;
159 std::vector<char> string_chars;
160 for (int i = 0; i < int (bits.size()); i += 8) {
161 char ch = 0;
162 for (int j = 0; j < 8 && i + j < int (bits.size()); j++)
163 if (bits[i + j] == RTLIL::State::S1)
164 ch |= 1 << j;
165 if (ch != 0)
166 string_chars.push_back(ch);
167 }
168 for (int i = int (string_chars.size()) - 1; i >= 0; i--)
169 string += string_chars[i];
170 return string;
171 }
172
173 bool RTLIL::Const::is_fully_zero() const
174 {
175 cover("kernel.rtlil.const.is_fully_zero");
176
177 for (auto bit : bits)
178 if (bit != RTLIL::State::S0)
179 return false;
180
181 return true;
182 }
183
184 bool RTLIL::Const::is_fully_ones() const
185 {
186 cover("kernel.rtlil.const.is_fully_ones");
187
188 for (auto bit : bits)
189 if (bit != RTLIL::State::S1)
190 return false;
191
192 return true;
193 }
194
195 bool RTLIL::Const::is_fully_def() const
196 {
197 cover("kernel.rtlil.const.is_fully_def");
198
199 for (auto bit : bits)
200 if (bit != RTLIL::State::S0 && bit != RTLIL::State::S1)
201 return false;
202
203 return true;
204 }
205
206 bool RTLIL::Const::is_fully_undef() const
207 {
208 cover("kernel.rtlil.const.is_fully_undef");
209
210 for (auto bit : bits)
211 if (bit != RTLIL::State::Sx && bit != RTLIL::State::Sz)
212 return false;
213
214 return true;
215 }
216
217 void RTLIL::AttrObject::set_bool_attribute(RTLIL::IdString id, bool value)
218 {
219 if (value)
220 attributes[id] = RTLIL::Const(1);
221 else {
222 const auto it = attributes.find(id);
223 if (it != attributes.end())
224 attributes.erase(it);
225 }
226 }
227
228 bool RTLIL::AttrObject::get_bool_attribute(RTLIL::IdString id) const
229 {
230 const auto it = attributes.find(id);
231 if (it == attributes.end())
232 return false;
233 return it->second.as_bool();
234 }
235
236 void RTLIL::AttrObject::set_strpool_attribute(RTLIL::IdString id, const pool<string> &data)
237 {
238 string attrval;
239 for (auto &s : data) {
240 if (!attrval.empty())
241 attrval += "|";
242 attrval += s;
243 }
244 attributes[id] = RTLIL::Const(attrval);
245 }
246
247 void RTLIL::AttrObject::add_strpool_attribute(RTLIL::IdString id, const pool<string> &data)
248 {
249 pool<string> union_data = get_strpool_attribute(id);
250 union_data.insert(data.begin(), data.end());
251 if (!union_data.empty())
252 set_strpool_attribute(id, union_data);
253 }
254
255 pool<string> RTLIL::AttrObject::get_strpool_attribute(RTLIL::IdString id) const
256 {
257 pool<string> data;
258 if (attributes.count(id) != 0)
259 for (auto s : split_tokens(attributes.at(id).decode_string(), "|"))
260 data.insert(s);
261 return data;
262 }
263
264 void RTLIL::AttrObject::set_src_attribute(const std::string &src)
265 {
266 if (src.empty())
267 attributes.erase("\\src");
268 else
269 attributes["\\src"] = src;
270 }
271
272 std::string RTLIL::AttrObject::get_src_attribute() const
273 {
274 std::string src;
275 if (attributes.count("\\src"))
276 src = attributes.at("\\src").decode_string();
277 return src;
278 }
279
280 bool RTLIL::Selection::selected_module(RTLIL::IdString mod_name) const
281 {
282 if (full_selection)
283 return true;
284 if (selected_modules.count(mod_name) > 0)
285 return true;
286 if (selected_members.count(mod_name) > 0)
287 return true;
288 return false;
289 }
290
291 bool RTLIL::Selection::selected_whole_module(RTLIL::IdString mod_name) const
292 {
293 if (full_selection)
294 return true;
295 if (selected_modules.count(mod_name) > 0)
296 return true;
297 return false;
298 }
299
300 bool RTLIL::Selection::selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const
301 {
302 if (full_selection)
303 return true;
304 if (selected_modules.count(mod_name) > 0)
305 return true;
306 if (selected_members.count(mod_name) > 0)
307 if (selected_members.at(mod_name).count(memb_name) > 0)
308 return true;
309 return false;
310 }
311
312 void RTLIL::Selection::optimize(RTLIL::Design *design)
313 {
314 if (full_selection) {
315 selected_modules.clear();
316 selected_members.clear();
317 return;
318 }
319
320 std::vector<RTLIL::IdString> del_list, add_list;
321
322 del_list.clear();
323 for (auto mod_name : selected_modules) {
324 if (design->modules_.count(mod_name) == 0)
325 del_list.push_back(mod_name);
326 selected_members.erase(mod_name);
327 }
328 for (auto mod_name : del_list)
329 selected_modules.erase(mod_name);
330
331 del_list.clear();
332 for (auto &it : selected_members)
333 if (design->modules_.count(it.first) == 0)
334 del_list.push_back(it.first);
335 for (auto mod_name : del_list)
336 selected_members.erase(mod_name);
337
338 for (auto &it : selected_members) {
339 del_list.clear();
340 for (auto memb_name : it.second)
341 if (design->modules_[it.first]->count_id(memb_name) == 0)
342 del_list.push_back(memb_name);
343 for (auto memb_name : del_list)
344 it.second.erase(memb_name);
345 }
346
347 del_list.clear();
348 add_list.clear();
349 for (auto &it : selected_members)
350 if (it.second.size() == 0)
351 del_list.push_back(it.first);
352 else if (it.second.size() == design->modules_[it.first]->wires_.size() + design->modules_[it.first]->memories.size() +
353 design->modules_[it.first]->cells_.size() + design->modules_[it.first]->processes.size())
354 add_list.push_back(it.first);
355 for (auto mod_name : del_list)
356 selected_members.erase(mod_name);
357 for (auto mod_name : add_list) {
358 selected_members.erase(mod_name);
359 selected_modules.insert(mod_name);
360 }
361
362 if (selected_modules.size() == design->modules_.size()) {
363 full_selection = true;
364 selected_modules.clear();
365 selected_members.clear();
366 }
367 }
368
369 RTLIL::Design::Design()
370 {
371 static unsigned int hashidx_count = 123456789;
372 hashidx_count = mkhash_xorshift(hashidx_count);
373 hashidx_ = hashidx_count;
374
375 refcount_modules_ = 0;
376 selection_stack.push_back(RTLIL::Selection());
377
378 #ifdef WITH_PYTHON
379 RTLIL::Design::get_all_designs()->insert(std::pair<unsigned int, RTLIL::Design*>(hashidx_, this));
380 #endif
381 }
382
383 RTLIL::Design::~Design()
384 {
385 for (auto it = modules_.begin(); it != modules_.end(); ++it)
386 delete it->second;
387 for (auto n : verilog_packages)
388 delete n;
389 for (auto n : verilog_globals)
390 delete n;
391 #ifdef WITH_PYTHON
392 RTLIL::Design::get_all_designs()->erase(hashidx_);
393 #endif
394 }
395
396 #ifdef WITH_PYTHON
397 static std::map<unsigned int, RTLIL::Design*> all_designs;
398 std::map<unsigned int, RTLIL::Design*> *RTLIL::Design::get_all_designs(void)
399 {
400 return &all_designs;
401 }
402 #endif
403
404 RTLIL::ObjRange<RTLIL::Module*> RTLIL::Design::modules()
405 {
406 return RTLIL::ObjRange<RTLIL::Module*>(&modules_, &refcount_modules_);
407 }
408
409 RTLIL::Module *RTLIL::Design::module(RTLIL::IdString name)
410 {
411 return modules_.count(name) ? modules_.at(name) : NULL;
412 }
413
414 RTLIL::Module *RTLIL::Design::top_module()
415 {
416 RTLIL::Module *module = nullptr;
417 int module_count = 0;
418
419 for (auto mod : selected_modules()) {
420 if (mod->get_bool_attribute("\\top"))
421 return mod;
422 module_count++;
423 module = mod;
424 }
425
426 return module_count == 1 ? module : nullptr;
427 }
428
429 void RTLIL::Design::add(RTLIL::Module *module)
430 {
431 log_assert(modules_.count(module->name) == 0);
432 log_assert(refcount_modules_ == 0);
433 modules_[module->name] = module;
434 module->design = this;
435
436 for (auto mon : monitors)
437 mon->notify_module_add(module);
438
439 if (yosys_xtrace) {
440 log("#X# New Module: %s\n", log_id(module));
441 log_backtrace("-X- ", yosys_xtrace-1);
442 }
443 }
444
445 RTLIL::Module *RTLIL::Design::addModule(RTLIL::IdString name)
446 {
447 log_assert(modules_.count(name) == 0);
448 log_assert(refcount_modules_ == 0);
449
450 RTLIL::Module *module = new RTLIL::Module;
451 modules_[name] = module;
452 module->design = this;
453 module->name = name;
454
455 for (auto mon : monitors)
456 mon->notify_module_add(module);
457
458 if (yosys_xtrace) {
459 log("#X# New Module: %s\n", log_id(module));
460 log_backtrace("-X- ", yosys_xtrace-1);
461 }
462
463 return module;
464 }
465
466 void RTLIL::Design::scratchpad_unset(std::string varname)
467 {
468 scratchpad.erase(varname);
469 }
470
471 void RTLIL::Design::scratchpad_set_int(std::string varname, int value)
472 {
473 scratchpad[varname] = stringf("%d", value);
474 }
475
476 void RTLIL::Design::scratchpad_set_bool(std::string varname, bool value)
477 {
478 scratchpad[varname] = value ? "true" : "false";
479 }
480
481 void RTLIL::Design::scratchpad_set_string(std::string varname, std::string value)
482 {
483 scratchpad[varname] = value;
484 }
485
486 int RTLIL::Design::scratchpad_get_int(std::string varname, int default_value) const
487 {
488 if (scratchpad.count(varname) == 0)
489 return default_value;
490
491 std::string str = scratchpad.at(varname);
492
493 if (str == "0" || str == "false")
494 return 0;
495
496 if (str == "1" || str == "true")
497 return 1;
498
499 char *endptr = nullptr;
500 long int parsed_value = strtol(str.c_str(), &endptr, 10);
501 return *endptr ? default_value : parsed_value;
502 }
503
504 bool RTLIL::Design::scratchpad_get_bool(std::string varname, bool default_value) const
505 {
506 if (scratchpad.count(varname) == 0)
507 return default_value;
508
509 std::string str = scratchpad.at(varname);
510
511 if (str == "0" || str == "false")
512 return false;
513
514 if (str == "1" || str == "true")
515 return true;
516
517 return default_value;
518 }
519
520 std::string RTLIL::Design::scratchpad_get_string(std::string varname, std::string default_value) const
521 {
522 if (scratchpad.count(varname) == 0)
523 return default_value;
524 return scratchpad.at(varname);
525 }
526
527 void RTLIL::Design::remove(RTLIL::Module *module)
528 {
529 for (auto mon : monitors)
530 mon->notify_module_del(module);
531
532 if (yosys_xtrace) {
533 log("#X# Remove Module: %s\n", log_id(module));
534 log_backtrace("-X- ", yosys_xtrace-1);
535 }
536
537 log_assert(modules_.at(module->name) == module);
538 modules_.erase(module->name);
539 delete module;
540 }
541
542 void RTLIL::Design::rename(RTLIL::Module *module, RTLIL::IdString new_name)
543 {
544 modules_.erase(module->name);
545 module->name = new_name;
546 add(module);
547 }
548
549 void RTLIL::Design::sort()
550 {
551 scratchpad.sort();
552 modules_.sort(sort_by_id_str());
553 for (auto &it : modules_)
554 it.second->sort();
555 }
556
557 void RTLIL::Design::check()
558 {
559 #ifndef NDEBUG
560 for (auto &it : modules_) {
561 log_assert(this == it.second->design);
562 log_assert(it.first == it.second->name);
563 log_assert(!it.first.empty());
564 it.second->check();
565 }
566 #endif
567 }
568
569 void RTLIL::Design::optimize()
570 {
571 for (auto &it : modules_)
572 it.second->optimize();
573 for (auto &it : selection_stack)
574 it.optimize(this);
575 for (auto &it : selection_vars)
576 it.second.optimize(this);
577 }
578
579 bool RTLIL::Design::selected_module(RTLIL::IdString mod_name) const
580 {
581 if (!selected_active_module.empty() && mod_name != selected_active_module)
582 return false;
583 if (selection_stack.size() == 0)
584 return true;
585 return selection_stack.back().selected_module(mod_name);
586 }
587
588 bool RTLIL::Design::selected_whole_module(RTLIL::IdString mod_name) const
589 {
590 if (!selected_active_module.empty() && mod_name != selected_active_module)
591 return false;
592 if (selection_stack.size() == 0)
593 return true;
594 return selection_stack.back().selected_whole_module(mod_name);
595 }
596
597 bool RTLIL::Design::selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const
598 {
599 if (!selected_active_module.empty() && mod_name != selected_active_module)
600 return false;
601 if (selection_stack.size() == 0)
602 return true;
603 return selection_stack.back().selected_member(mod_name, memb_name);
604 }
605
606 bool RTLIL::Design::selected_module(RTLIL::Module *mod) const
607 {
608 return selected_module(mod->name);
609 }
610
611 bool RTLIL::Design::selected_whole_module(RTLIL::Module *mod) const
612 {
613 return selected_whole_module(mod->name);
614 }
615
616 std::vector<RTLIL::Module*> RTLIL::Design::selected_modules() const
617 {
618 std::vector<RTLIL::Module*> result;
619 result.reserve(modules_.size());
620 for (auto &it : modules_)
621 if (selected_module(it.first) && !it.second->get_blackbox_attribute())
622 result.push_back(it.second);
623 return result;
624 }
625
626 std::vector<RTLIL::Module*> RTLIL::Design::selected_whole_modules() const
627 {
628 std::vector<RTLIL::Module*> result;
629 result.reserve(modules_.size());
630 for (auto &it : modules_)
631 if (selected_whole_module(it.first) && !it.second->get_blackbox_attribute())
632 result.push_back(it.second);
633 return result;
634 }
635
636 std::vector<RTLIL::Module*> RTLIL::Design::selected_whole_modules_warn() const
637 {
638 std::vector<RTLIL::Module*> result;
639 result.reserve(modules_.size());
640 for (auto &it : modules_)
641 if (it.second->get_blackbox_attribute())
642 continue;
643 else if (selected_whole_module(it.first))
644 result.push_back(it.second);
645 else if (selected_module(it.first))
646 log_warning("Ignoring partially selected module %s.\n", log_id(it.first));
647 return result;
648 }
649
650 RTLIL::Module::Module()
651 {
652 static unsigned int hashidx_count = 123456789;
653 hashidx_count = mkhash_xorshift(hashidx_count);
654 hashidx_ = hashidx_count;
655
656 design = nullptr;
657 refcount_wires_ = 0;
658 refcount_cells_ = 0;
659
660 #ifdef WITH_PYTHON
661 RTLIL::Module::get_all_modules()->insert(std::pair<unsigned int, RTLIL::Module*>(hashidx_, this));
662 #endif
663 }
664
665 RTLIL::Module::~Module()
666 {
667 for (auto it = wires_.begin(); it != wires_.end(); ++it)
668 delete it->second;
669 for (auto it = memories.begin(); it != memories.end(); ++it)
670 delete it->second;
671 for (auto it = cells_.begin(); it != cells_.end(); ++it)
672 delete it->second;
673 for (auto it = processes.begin(); it != processes.end(); ++it)
674 delete it->second;
675 #ifdef WITH_PYTHON
676 RTLIL::Module::get_all_modules()->erase(hashidx_);
677 #endif
678 }
679
680 #ifdef WITH_PYTHON
681 static std::map<unsigned int, RTLIL::Module*> all_modules;
682 std::map<unsigned int, RTLIL::Module*> *RTLIL::Module::get_all_modules(void)
683 {
684 return &all_modules;
685 }
686 #endif
687
688 void RTLIL::Module::makeblackbox()
689 {
690 pool<RTLIL::Wire*> delwires;
691
692 for (auto it = wires_.begin(); it != wires_.end(); ++it)
693 if (!it->second->port_input && !it->second->port_output)
694 delwires.insert(it->second);
695
696 for (auto it = memories.begin(); it != memories.end(); ++it)
697 delete it->second;
698 memories.clear();
699
700 for (auto it = cells_.begin(); it != cells_.end(); ++it)
701 delete it->second;
702 cells_.clear();
703
704 for (auto it = processes.begin(); it != processes.end(); ++it)
705 delete it->second;
706 processes.clear();
707
708 remove(delwires);
709 set_bool_attribute("\\blackbox");
710 }
711
712 void RTLIL::Module::reprocess_module(RTLIL::Design *, dict<RTLIL::IdString, RTLIL::Module *>)
713 {
714 log_error("Cannot reprocess_module module `%s' !\n", id2cstr(name));
715 }
716
717 RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, dict<RTLIL::IdString, RTLIL::Const>, bool mayfail)
718 {
719 if (mayfail)
720 return RTLIL::IdString();
721 log_error("Module `%s' is used with parameters but is not parametric!\n", id2cstr(name));
722 }
723
724
725 RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, dict<RTLIL::IdString, RTLIL::Const>, dict<RTLIL::IdString, RTLIL::Module*>, dict<RTLIL::IdString, RTLIL::IdString>, bool mayfail)
726 {
727 if (mayfail)
728 return RTLIL::IdString();
729 log_error("Module `%s' is used with parameters but is not parametric!\n", id2cstr(name));
730 }
731
732 size_t RTLIL::Module::count_id(RTLIL::IdString id)
733 {
734 return wires_.count(id) + memories.count(id) + cells_.count(id) + processes.count(id);
735 }
736
737 #ifndef NDEBUG
738 namespace {
739 struct InternalCellChecker
740 {
741 RTLIL::Module *module;
742 RTLIL::Cell *cell;
743 pool<RTLIL::IdString> expected_params, expected_ports;
744
745 InternalCellChecker(RTLIL::Module *module, RTLIL::Cell *cell) : module(module), cell(cell) { }
746
747 void error(int linenr)
748 {
749 std::stringstream buf;
750 ILANG_BACKEND::dump_cell(buf, " ", cell);
751
752 log_error("Found error in internal cell %s%s%s (%s) at %s:%d:\n%s",
753 module ? module->name.c_str() : "", module ? "." : "",
754 cell->name.c_str(), cell->type.c_str(), __FILE__, linenr, buf.str().c_str());
755 }
756
757 int param(const char *name)
758 {
759 if (cell->parameters.count(name) == 0)
760 error(__LINE__);
761 expected_params.insert(name);
762 return cell->parameters.at(name).as_int();
763 }
764
765 int param_bool(const char *name)
766 {
767 int v = param(name);
768 if (cell->parameters.at(name).bits.size() > 32)
769 error(__LINE__);
770 if (v != 0 && v != 1)
771 error(__LINE__);
772 return v;
773 }
774
775 void param_bits(const char *name, int width)
776 {
777 param(name);
778 if (int(cell->parameters.at(name).bits.size()) != width)
779 error(__LINE__);
780 }
781
782 void port(const char *name, int width)
783 {
784 if (!cell->hasPort(name))
785 error(__LINE__);
786 if (cell->getPort(name).size() != width)
787 error(__LINE__);
788 expected_ports.insert(name);
789 }
790
791 void check_expected(bool check_matched_sign = true)
792 {
793 for (auto &para : cell->parameters)
794 if (expected_params.count(para.first) == 0)
795 error(__LINE__);
796 for (auto &conn : cell->connections())
797 if (expected_ports.count(conn.first) == 0)
798 error(__LINE__);
799
800 if (expected_params.count("\\A_SIGNED") != 0 && expected_params.count("\\B_SIGNED") && check_matched_sign) {
801 bool a_is_signed = param("\\A_SIGNED") != 0;
802 bool b_is_signed = param("\\B_SIGNED") != 0;
803 if (a_is_signed != b_is_signed)
804 error(__LINE__);
805 }
806 }
807
808 void check_gate(const char *ports)
809 {
810 if (cell->parameters.size() != 0)
811 error(__LINE__);
812
813 for (const char *p = ports; *p; p++) {
814 char portname[3] = { '\\', *p, 0 };
815 if (!cell->hasPort(portname))
816 error(__LINE__);
817 if (cell->getPort(portname).size() != 1)
818 error(__LINE__);
819 }
820
821 for (auto &conn : cell->connections()) {
822 if (conn.first.size() != 2 || conn.first[0] != '\\')
823 error(__LINE__);
824 if (strchr(ports, conn.first[1]) == NULL)
825 error(__LINE__);
826 }
827 }
828
829 void check()
830 {
831 if (cell->type.substr(0, 1) != "$" || cell->type.substr(0, 3) == "$__" || cell->type.substr(0, 8) == "$paramod" || cell->type.substr(0,10) == "$fmcombine" ||
832 cell->type.substr(0, 9) == "$verific$" || cell->type.substr(0, 7) == "$array:" || cell->type.substr(0, 8) == "$extern:")
833 return;
834
835 if (cell->type.in("$not", "$pos", "$neg")) {
836 param_bool("\\A_SIGNED");
837 port("\\A", param("\\A_WIDTH"));
838 port("\\Y", param("\\Y_WIDTH"));
839 check_expected();
840 return;
841 }
842
843 if (cell->type.in("$and", "$or", "$xor", "$xnor")) {
844 param_bool("\\A_SIGNED");
845 param_bool("\\B_SIGNED");
846 port("\\A", param("\\A_WIDTH"));
847 port("\\B", param("\\B_WIDTH"));
848 port("\\Y", param("\\Y_WIDTH"));
849 check_expected();
850 return;
851 }
852
853 if (cell->type.in("$reduce_and", "$reduce_or", "$reduce_xor", "$reduce_xnor", "$reduce_bool")) {
854 param_bool("\\A_SIGNED");
855 port("\\A", param("\\A_WIDTH"));
856 port("\\Y", param("\\Y_WIDTH"));
857 check_expected();
858 return;
859 }
860
861 if (cell->type.in("$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx")) {
862 param_bool("\\A_SIGNED");
863 param_bool("\\B_SIGNED");
864 port("\\A", param("\\A_WIDTH"));
865 port("\\B", param("\\B_WIDTH"));
866 port("\\Y", param("\\Y_WIDTH"));
867 check_expected(false);
868 return;
869 }
870
871 if (cell->type.in("$lt", "$le", "$eq", "$ne", "$eqx", "$nex", "$ge", "$gt")) {
872 param_bool("\\A_SIGNED");
873 param_bool("\\B_SIGNED");
874 port("\\A", param("\\A_WIDTH"));
875 port("\\B", param("\\B_WIDTH"));
876 port("\\Y", param("\\Y_WIDTH"));
877 check_expected();
878 return;
879 }
880
881 if (cell->type.in("$add", "$sub", "$mul", "$div", "$mod", "$pow")) {
882 param_bool("\\A_SIGNED");
883 param_bool("\\B_SIGNED");
884 port("\\A", param("\\A_WIDTH"));
885 port("\\B", param("\\B_WIDTH"));
886 port("\\Y", param("\\Y_WIDTH"));
887 check_expected(cell->type != "$pow");
888 return;
889 }
890
891 if (cell->type == "$fa") {
892 port("\\A", param("\\WIDTH"));
893 port("\\B", param("\\WIDTH"));
894 port("\\C", param("\\WIDTH"));
895 port("\\X", param("\\WIDTH"));
896 port("\\Y", param("\\WIDTH"));
897 check_expected();
898 return;
899 }
900
901 if (cell->type == "$lcu") {
902 port("\\P", param("\\WIDTH"));
903 port("\\G", param("\\WIDTH"));
904 port("\\CI", 1);
905 port("\\CO", param("\\WIDTH"));
906 check_expected();
907 return;
908 }
909
910 if (cell->type == "$alu") {
911 param_bool("\\A_SIGNED");
912 param_bool("\\B_SIGNED");
913 port("\\A", param("\\A_WIDTH"));
914 port("\\B", param("\\B_WIDTH"));
915 port("\\CI", 1);
916 port("\\BI", 1);
917 port("\\X", param("\\Y_WIDTH"));
918 port("\\Y", param("\\Y_WIDTH"));
919 port("\\CO", param("\\Y_WIDTH"));
920 check_expected();
921 return;
922 }
923
924 if (cell->type == "$macc") {
925 param("\\CONFIG");
926 param("\\CONFIG_WIDTH");
927 port("\\A", param("\\A_WIDTH"));
928 port("\\B", param("\\B_WIDTH"));
929 port("\\Y", param("\\Y_WIDTH"));
930 check_expected();
931 Macc().from_cell(cell);
932 return;
933 }
934
935 if (cell->type == "$logic_not") {
936 param_bool("\\A_SIGNED");
937 port("\\A", param("\\A_WIDTH"));
938 port("\\Y", param("\\Y_WIDTH"));
939 check_expected();
940 return;
941 }
942
943 if (cell->type == "$logic_and" || cell->type == "$logic_or") {
944 param_bool("\\A_SIGNED");
945 param_bool("\\B_SIGNED");
946 port("\\A", param("\\A_WIDTH"));
947 port("\\B", param("\\B_WIDTH"));
948 port("\\Y", param("\\Y_WIDTH"));
949 check_expected(false);
950 return;
951 }
952
953 if (cell->type == "$slice") {
954 param("\\OFFSET");
955 port("\\A", param("\\A_WIDTH"));
956 port("\\Y", param("\\Y_WIDTH"));
957 if (param("\\OFFSET") + param("\\Y_WIDTH") > param("\\A_WIDTH"))
958 error(__LINE__);
959 check_expected();
960 return;
961 }
962
963 if (cell->type == "$concat") {
964 port("\\A", param("\\A_WIDTH"));
965 port("\\B", param("\\B_WIDTH"));
966 port("\\Y", param("\\A_WIDTH") + param("\\B_WIDTH"));
967 check_expected();
968 return;
969 }
970
971 if (cell->type == "$mux") {
972 port("\\A", param("\\WIDTH"));
973 port("\\B", param("\\WIDTH"));
974 port("\\S", 1);
975 port("\\Y", param("\\WIDTH"));
976 check_expected();
977 return;
978 }
979
980 if (cell->type == "$pmux") {
981 port("\\A", param("\\WIDTH"));
982 port("\\B", param("\\WIDTH") * param("\\S_WIDTH"));
983 port("\\S", param("\\S_WIDTH"));
984 port("\\Y", param("\\WIDTH"));
985 check_expected();
986 return;
987 }
988
989 if (cell->type == "$lut") {
990 param("\\LUT");
991 port("\\A", param("\\WIDTH"));
992 port("\\Y", 1);
993 check_expected();
994 return;
995 }
996
997 if (cell->type == "$sop") {
998 param("\\DEPTH");
999 param("\\TABLE");
1000 port("\\A", param("\\WIDTH"));
1001 port("\\Y", 1);
1002 check_expected();
1003 return;
1004 }
1005
1006 if (cell->type == "$sr") {
1007 param_bool("\\SET_POLARITY");
1008 param_bool("\\CLR_POLARITY");
1009 port("\\SET", param("\\WIDTH"));
1010 port("\\CLR", param("\\WIDTH"));
1011 port("\\Q", param("\\WIDTH"));
1012 check_expected();
1013 return;
1014 }
1015
1016 if (cell->type == "$ff") {
1017 port("\\D", param("\\WIDTH"));
1018 port("\\Q", param("\\WIDTH"));
1019 check_expected();
1020 return;
1021 }
1022
1023 if (cell->type == "$dff") {
1024 param_bool("\\CLK_POLARITY");
1025 port("\\CLK", 1);
1026 port("\\D", param("\\WIDTH"));
1027 port("\\Q", param("\\WIDTH"));
1028 check_expected();
1029 return;
1030 }
1031
1032 if (cell->type == "$dffe") {
1033 param_bool("\\CLK_POLARITY");
1034 param_bool("\\EN_POLARITY");
1035 port("\\CLK", 1);
1036 port("\\EN", 1);
1037 port("\\D", param("\\WIDTH"));
1038 port("\\Q", param("\\WIDTH"));
1039 check_expected();
1040 return;
1041 }
1042
1043 if (cell->type == "$dffsr") {
1044 param_bool("\\CLK_POLARITY");
1045 param_bool("\\SET_POLARITY");
1046 param_bool("\\CLR_POLARITY");
1047 port("\\CLK", 1);
1048 port("\\SET", param("\\WIDTH"));
1049 port("\\CLR", param("\\WIDTH"));
1050 port("\\D", param("\\WIDTH"));
1051 port("\\Q", param("\\WIDTH"));
1052 check_expected();
1053 return;
1054 }
1055
1056 if (cell->type == "$adff") {
1057 param_bool("\\CLK_POLARITY");
1058 param_bool("\\ARST_POLARITY");
1059 param_bits("\\ARST_VALUE", param("\\WIDTH"));
1060 port("\\CLK", 1);
1061 port("\\ARST", 1);
1062 port("\\D", param("\\WIDTH"));
1063 port("\\Q", param("\\WIDTH"));
1064 check_expected();
1065 return;
1066 }
1067
1068 if (cell->type == "$dlatch") {
1069 param_bool("\\EN_POLARITY");
1070 port("\\EN", 1);
1071 port("\\D", param("\\WIDTH"));
1072 port("\\Q", param("\\WIDTH"));
1073 check_expected();
1074 return;
1075 }
1076
1077 if (cell->type == "$dlatchsr") {
1078 param_bool("\\EN_POLARITY");
1079 param_bool("\\SET_POLARITY");
1080 param_bool("\\CLR_POLARITY");
1081 port("\\EN", 1);
1082 port("\\SET", param("\\WIDTH"));
1083 port("\\CLR", param("\\WIDTH"));
1084 port("\\D", param("\\WIDTH"));
1085 port("\\Q", param("\\WIDTH"));
1086 check_expected();
1087 return;
1088 }
1089
1090 if (cell->type == "$fsm") {
1091 param("\\NAME");
1092 param_bool("\\CLK_POLARITY");
1093 param_bool("\\ARST_POLARITY");
1094 param("\\STATE_BITS");
1095 param("\\STATE_NUM");
1096 param("\\STATE_NUM_LOG2");
1097 param("\\STATE_RST");
1098 param_bits("\\STATE_TABLE", param("\\STATE_BITS") * param("\\STATE_NUM"));
1099 param("\\TRANS_NUM");
1100 param_bits("\\TRANS_TABLE", param("\\TRANS_NUM") * (2*param("\\STATE_NUM_LOG2") + param("\\CTRL_IN_WIDTH") + param("\\CTRL_OUT_WIDTH")));
1101 port("\\CLK", 1);
1102 port("\\ARST", 1);
1103 port("\\CTRL_IN", param("\\CTRL_IN_WIDTH"));
1104 port("\\CTRL_OUT", param("\\CTRL_OUT_WIDTH"));
1105 check_expected();
1106 return;
1107 }
1108
1109 if (cell->type == "$memrd") {
1110 param("\\MEMID");
1111 param_bool("\\CLK_ENABLE");
1112 param_bool("\\CLK_POLARITY");
1113 param_bool("\\TRANSPARENT");
1114 port("\\CLK", 1);
1115 port("\\EN", 1);
1116 port("\\ADDR", param("\\ABITS"));
1117 port("\\DATA", param("\\WIDTH"));
1118 check_expected();
1119 return;
1120 }
1121
1122 if (cell->type == "$memwr") {
1123 param("\\MEMID");
1124 param_bool("\\CLK_ENABLE");
1125 param_bool("\\CLK_POLARITY");
1126 param("\\PRIORITY");
1127 port("\\CLK", 1);
1128 port("\\EN", param("\\WIDTH"));
1129 port("\\ADDR", param("\\ABITS"));
1130 port("\\DATA", param("\\WIDTH"));
1131 check_expected();
1132 return;
1133 }
1134
1135 if (cell->type == "$meminit") {
1136 param("\\MEMID");
1137 param("\\PRIORITY");
1138 port("\\ADDR", param("\\ABITS"));
1139 port("\\DATA", param("\\WIDTH") * param("\\WORDS"));
1140 check_expected();
1141 return;
1142 }
1143
1144 if (cell->type == "$mem") {
1145 param("\\MEMID");
1146 param("\\SIZE");
1147 param("\\OFFSET");
1148 param("\\INIT");
1149 param_bits("\\RD_CLK_ENABLE", max(1, param("\\RD_PORTS")));
1150 param_bits("\\RD_CLK_POLARITY", max(1, param("\\RD_PORTS")));
1151 param_bits("\\RD_TRANSPARENT", max(1, param("\\RD_PORTS")));
1152 param_bits("\\WR_CLK_ENABLE", max(1, param("\\WR_PORTS")));
1153 param_bits("\\WR_CLK_POLARITY", max(1, param("\\WR_PORTS")));
1154 port("\\RD_CLK", param("\\RD_PORTS"));
1155 port("\\RD_EN", param("\\RD_PORTS"));
1156 port("\\RD_ADDR", param("\\RD_PORTS") * param("\\ABITS"));
1157 port("\\RD_DATA", param("\\RD_PORTS") * param("\\WIDTH"));
1158 port("\\WR_CLK", param("\\WR_PORTS"));
1159 port("\\WR_EN", param("\\WR_PORTS") * param("\\WIDTH"));
1160 port("\\WR_ADDR", param("\\WR_PORTS") * param("\\ABITS"));
1161 port("\\WR_DATA", param("\\WR_PORTS") * param("\\WIDTH"));
1162 check_expected();
1163 return;
1164 }
1165
1166 if (cell->type == "$tribuf") {
1167 port("\\A", param("\\WIDTH"));
1168 port("\\Y", param("\\WIDTH"));
1169 port("\\EN", 1);
1170 check_expected();
1171 return;
1172 }
1173
1174 if (cell->type.in("$assert", "$assume", "$live", "$fair", "$cover")) {
1175 port("\\A", 1);
1176 port("\\EN", 1);
1177 check_expected();
1178 return;
1179 }
1180
1181 if (cell->type == "$initstate") {
1182 port("\\Y", 1);
1183 check_expected();
1184 return;
1185 }
1186
1187 if (cell->type.in("$anyconst", "$anyseq", "$allconst", "$allseq")) {
1188 port("\\Y", param("\\WIDTH"));
1189 check_expected();
1190 return;
1191 }
1192
1193 if (cell->type == "$equiv") {
1194 port("\\A", 1);
1195 port("\\B", 1);
1196 port("\\Y", 1);
1197 check_expected();
1198 return;
1199 }
1200
1201 if (cell->type.in("$specify2", "$specify3")) {
1202 param_bool("\\FULL");
1203 param_bool("\\SRC_DST_PEN");
1204 param_bool("\\SRC_DST_POL");
1205 param("\\T_RISE_MIN");
1206 param("\\T_RISE_TYP");
1207 param("\\T_RISE_MAX");
1208 param("\\T_FALL_MIN");
1209 param("\\T_FALL_TYP");
1210 param("\\T_FALL_MAX");
1211 port("\\EN", 1);
1212 port("\\SRC", param("\\SRC_WIDTH"));
1213 port("\\DST", param("\\DST_WIDTH"));
1214 if (cell->type == "$specify3") {
1215 param_bool("\\EDGE_EN");
1216 param_bool("\\EDGE_POL");
1217 param_bool("\\DAT_DST_PEN");
1218 param_bool("\\DAT_DST_POL");
1219 port("\\DAT", param("\\DST_WIDTH"));
1220 }
1221 check_expected();
1222 return;
1223 }
1224
1225 if (cell->type == "$specrule") {
1226 param("\\TYPE");
1227 param_bool("\\SRC_PEN");
1228 param_bool("\\SRC_POL");
1229 param_bool("\\DST_PEN");
1230 param_bool("\\DST_POL");
1231 param("\\T_LIMIT");
1232 param("\\T_LIMIT2");
1233 port("\\SRC_EN", 1);
1234 port("\\DST_EN", 1);
1235 port("\\SRC", param("\\SRC_WIDTH"));
1236 port("\\DST", param("\\DST_WIDTH"));
1237 check_expected();
1238 return;
1239 }
1240
1241 if (cell->type == "$_BUF_") { check_gate("AY"); return; }
1242 if (cell->type == "$_NOT_") { check_gate("AY"); return; }
1243 if (cell->type == "$_AND_") { check_gate("ABY"); return; }
1244 if (cell->type == "$_NAND_") { check_gate("ABY"); return; }
1245 if (cell->type == "$_OR_") { check_gate("ABY"); return; }
1246 if (cell->type == "$_NOR_") { check_gate("ABY"); return; }
1247 if (cell->type == "$_XOR_") { check_gate("ABY"); return; }
1248 if (cell->type == "$_XNOR_") { check_gate("ABY"); return; }
1249 if (cell->type == "$_ANDNOT_") { check_gate("ABY"); return; }
1250 if (cell->type == "$_ORNOT_") { check_gate("ABY"); return; }
1251 if (cell->type == "$_MUX_") { check_gate("ABSY"); return; }
1252 if (cell->type == "$_AOI3_") { check_gate("ABCY"); return; }
1253 if (cell->type == "$_OAI3_") { check_gate("ABCY"); return; }
1254 if (cell->type == "$_AOI4_") { check_gate("ABCDY"); return; }
1255 if (cell->type == "$_OAI4_") { check_gate("ABCDY"); return; }
1256
1257 if (cell->type == "$_TBUF_") { check_gate("AYE"); return; }
1258
1259 if (cell->type == "$_MUX4_") { check_gate("ABCDSTY"); return; }
1260 if (cell->type == "$_MUX8_") { check_gate("ABCDEFGHSTUY"); return; }
1261 if (cell->type == "$_MUX16_") { check_gate("ABCDEFGHIJKLMNOPSTUVY"); return; }
1262
1263 if (cell->type == "$_SR_NN_") { check_gate("SRQ"); return; }
1264 if (cell->type == "$_SR_NP_") { check_gate("SRQ"); return; }
1265 if (cell->type == "$_SR_PN_") { check_gate("SRQ"); return; }
1266 if (cell->type == "$_SR_PP_") { check_gate("SRQ"); return; }
1267
1268 if (cell->type == "$_FF_") { check_gate("DQ"); return; }
1269 if (cell->type == "$_DFF_N_") { check_gate("DQC"); return; }
1270 if (cell->type == "$_DFF_P_") { check_gate("DQC"); return; }
1271
1272 if (cell->type == "$_DFFE_NN_") { check_gate("DQCE"); return; }
1273 if (cell->type == "$_DFFE_NP_") { check_gate("DQCE"); return; }
1274 if (cell->type == "$_DFFE_PN_") { check_gate("DQCE"); return; }
1275 if (cell->type == "$_DFFE_PP_") { check_gate("DQCE"); return; }
1276
1277 if (cell->type == "$_DFF_NN0_") { check_gate("DQCR"); return; }
1278 if (cell->type == "$_DFF_NN1_") { check_gate("DQCR"); return; }
1279 if (cell->type == "$_DFF_NP0_") { check_gate("DQCR"); return; }
1280 if (cell->type == "$_DFF_NP1_") { check_gate("DQCR"); return; }
1281 if (cell->type == "$_DFF_PN0_") { check_gate("DQCR"); return; }
1282 if (cell->type == "$_DFF_PN1_") { check_gate("DQCR"); return; }
1283 if (cell->type == "$_DFF_PP0_") { check_gate("DQCR"); return; }
1284 if (cell->type == "$_DFF_PP1_") { check_gate("DQCR"); return; }
1285
1286 if (cell->type == "$_DFFSR_NNN_") { check_gate("CSRDQ"); return; }
1287 if (cell->type == "$_DFFSR_NNP_") { check_gate("CSRDQ"); return; }
1288 if (cell->type == "$_DFFSR_NPN_") { check_gate("CSRDQ"); return; }
1289 if (cell->type == "$_DFFSR_NPP_") { check_gate("CSRDQ"); return; }
1290 if (cell->type == "$_DFFSR_PNN_") { check_gate("CSRDQ"); return; }
1291 if (cell->type == "$_DFFSR_PNP_") { check_gate("CSRDQ"); return; }
1292 if (cell->type == "$_DFFSR_PPN_") { check_gate("CSRDQ"); return; }
1293 if (cell->type == "$_DFFSR_PPP_") { check_gate("CSRDQ"); return; }
1294
1295 if (cell->type == "$_DLATCH_N_") { check_gate("EDQ"); return; }
1296 if (cell->type == "$_DLATCH_P_") { check_gate("EDQ"); return; }
1297
1298 if (cell->type == "$_DLATCHSR_NNN_") { check_gate("ESRDQ"); return; }
1299 if (cell->type == "$_DLATCHSR_NNP_") { check_gate("ESRDQ"); return; }
1300 if (cell->type == "$_DLATCHSR_NPN_") { check_gate("ESRDQ"); return; }
1301 if (cell->type == "$_DLATCHSR_NPP_") { check_gate("ESRDQ"); return; }
1302 if (cell->type == "$_DLATCHSR_PNN_") { check_gate("ESRDQ"); return; }
1303 if (cell->type == "$_DLATCHSR_PNP_") { check_gate("ESRDQ"); return; }
1304 if (cell->type == "$_DLATCHSR_PPN_") { check_gate("ESRDQ"); return; }
1305 if (cell->type == "$_DLATCHSR_PPP_") { check_gate("ESRDQ"); return; }
1306
1307 error(__LINE__);
1308 }
1309 };
1310 }
1311 #endif
1312
1313 void RTLIL::Module::sort()
1314 {
1315 wires_.sort(sort_by_id_str());
1316 cells_.sort(sort_by_id_str());
1317 avail_parameters.sort(sort_by_id_str());
1318 memories.sort(sort_by_id_str());
1319 processes.sort(sort_by_id_str());
1320 for (auto &it : cells_)
1321 it.second->sort();
1322 for (auto &it : wires_)
1323 it.second->attributes.sort(sort_by_id_str());
1324 for (auto &it : memories)
1325 it.second->attributes.sort(sort_by_id_str());
1326 }
1327
1328 void RTLIL::Module::check()
1329 {
1330 #ifndef NDEBUG
1331 std::vector<bool> ports_declared;
1332 for (auto &it : wires_) {
1333 log_assert(this == it.second->module);
1334 log_assert(it.first == it.second->name);
1335 log_assert(!it.first.empty());
1336 log_assert(it.second->width >= 0);
1337 log_assert(it.second->port_id >= 0);
1338 for (auto &it2 : it.second->attributes)
1339 log_assert(!it2.first.empty());
1340 if (it.second->port_id) {
1341 log_assert(GetSize(ports) >= it.second->port_id);
1342 log_assert(ports.at(it.second->port_id-1) == it.first);
1343 log_assert(it.second->port_input || it.second->port_output);
1344 if (GetSize(ports_declared) < it.second->port_id)
1345 ports_declared.resize(it.second->port_id);
1346 log_assert(ports_declared[it.second->port_id-1] == false);
1347 ports_declared[it.second->port_id-1] = true;
1348 } else
1349 log_assert(!it.second->port_input && !it.second->port_output);
1350 }
1351 for (auto port_declared : ports_declared)
1352 log_assert(port_declared == true);
1353 log_assert(GetSize(ports) == GetSize(ports_declared));
1354
1355 for (auto &it : memories) {
1356 log_assert(it.first == it.second->name);
1357 log_assert(!it.first.empty());
1358 log_assert(it.second->width >= 0);
1359 log_assert(it.second->size >= 0);
1360 for (auto &it2 : it.second->attributes)
1361 log_assert(!it2.first.empty());
1362 }
1363
1364 for (auto &it : cells_) {
1365 log_assert(this == it.second->module);
1366 log_assert(it.first == it.second->name);
1367 log_assert(!it.first.empty());
1368 log_assert(!it.second->type.empty());
1369 for (auto &it2 : it.second->connections()) {
1370 log_assert(!it2.first.empty());
1371 it2.second.check();
1372 }
1373 for (auto &it2 : it.second->attributes)
1374 log_assert(!it2.first.empty());
1375 for (auto &it2 : it.second->parameters)
1376 log_assert(!it2.first.empty());
1377 InternalCellChecker checker(this, it.second);
1378 checker.check();
1379 }
1380
1381 for (auto &it : processes) {
1382 log_assert(it.first == it.second->name);
1383 log_assert(!it.first.empty());
1384 log_assert(it.second->root_case.compare.empty());
1385 std::vector<CaseRule*> all_cases = {&it.second->root_case};
1386 for (size_t i = 0; i < all_cases.size(); i++) {
1387 for (auto &switch_it : all_cases[i]->switches) {
1388 for (auto &case_it : switch_it->cases) {
1389 for (auto &compare_it : case_it->compare) {
1390 log_assert(switch_it->signal.size() == compare_it.size());
1391 }
1392 all_cases.push_back(case_it);
1393 }
1394 }
1395 }
1396 for (auto &sync_it : it.second->syncs) {
1397 switch (sync_it->type) {
1398 case SyncType::ST0:
1399 case SyncType::ST1:
1400 case SyncType::STp:
1401 case SyncType::STn:
1402 case SyncType::STe:
1403 log_assert(!sync_it->signal.empty());
1404 break;
1405 case SyncType::STa:
1406 case SyncType::STg:
1407 case SyncType::STi:
1408 log_assert(sync_it->signal.empty());
1409 break;
1410 }
1411 }
1412 }
1413
1414 for (auto &it : connections_) {
1415 log_assert(it.first.size() == it.second.size());
1416 log_assert(!it.first.has_const());
1417 it.first.check();
1418 it.second.check();
1419 }
1420
1421 for (auto &it : attributes)
1422 log_assert(!it.first.empty());
1423 #endif
1424 }
1425
1426 void RTLIL::Module::optimize()
1427 {
1428 }
1429
1430 void RTLIL::Module::cloneInto(RTLIL::Module *new_mod) const
1431 {
1432 log_assert(new_mod->refcount_wires_ == 0);
1433 log_assert(new_mod->refcount_cells_ == 0);
1434
1435 new_mod->avail_parameters = avail_parameters;
1436
1437 for (auto &conn : connections_)
1438 new_mod->connect(conn);
1439
1440 for (auto &attr : attributes)
1441 new_mod->attributes[attr.first] = attr.second;
1442
1443 for (auto &it : wires_)
1444 new_mod->addWire(it.first, it.second);
1445
1446 for (auto &it : memories)
1447 new_mod->memories[it.first] = new RTLIL::Memory(*it.second);
1448
1449 for (auto &it : cells_)
1450 new_mod->addCell(it.first, it.second);
1451
1452 for (auto &it : processes)
1453 new_mod->processes[it.first] = it.second->clone();
1454
1455 struct RewriteSigSpecWorker
1456 {
1457 RTLIL::Module *mod;
1458 void operator()(RTLIL::SigSpec &sig)
1459 {
1460 std::vector<RTLIL::SigChunk> chunks = sig.chunks();
1461 for (auto &c : chunks)
1462 if (c.wire != NULL)
1463 c.wire = mod->wires_.at(c.wire->name);
1464 sig = chunks;
1465 }
1466 };
1467
1468 RewriteSigSpecWorker rewriteSigSpecWorker;
1469 rewriteSigSpecWorker.mod = new_mod;
1470 new_mod->rewrite_sigspecs(rewriteSigSpecWorker);
1471 new_mod->fixup_ports();
1472 }
1473
1474 RTLIL::Module *RTLIL::Module::clone() const
1475 {
1476 RTLIL::Module *new_mod = new RTLIL::Module;
1477 new_mod->name = name;
1478 cloneInto(new_mod);
1479 return new_mod;
1480 }
1481
1482 bool RTLIL::Module::has_memories() const
1483 {
1484 return !memories.empty();
1485 }
1486
1487 bool RTLIL::Module::has_processes() const
1488 {
1489 return !processes.empty();
1490 }
1491
1492 bool RTLIL::Module::has_memories_warn() const
1493 {
1494 if (!memories.empty())
1495 log_warning("Ignoring module %s because it contains memories (run 'memory' command first).\n", log_id(this));
1496 return !memories.empty();
1497 }
1498
1499 bool RTLIL::Module::has_processes_warn() const
1500 {
1501 if (!processes.empty())
1502 log_warning("Ignoring module %s because it contains processes (run 'proc' command first).\n", log_id(this));
1503 return !processes.empty();
1504 }
1505
1506 std::vector<RTLIL::Wire*> RTLIL::Module::selected_wires() const
1507 {
1508 std::vector<RTLIL::Wire*> result;
1509 result.reserve(wires_.size());
1510 for (auto &it : wires_)
1511 if (design->selected(this, it.second))
1512 result.push_back(it.second);
1513 return result;
1514 }
1515
1516 std::vector<RTLIL::Cell*> RTLIL::Module::selected_cells() const
1517 {
1518 std::vector<RTLIL::Cell*> result;
1519 result.reserve(wires_.size());
1520 for (auto &it : cells_)
1521 if (design->selected(this, it.second))
1522 result.push_back(it.second);
1523 return result;
1524 }
1525
1526 void RTLIL::Module::add(RTLIL::Wire *wire)
1527 {
1528 log_assert(!wire->name.empty());
1529 log_assert(count_id(wire->name) == 0);
1530 log_assert(refcount_wires_ == 0);
1531 wires_[wire->name] = wire;
1532 wire->module = this;
1533 }
1534
1535 void RTLIL::Module::add(RTLIL::Cell *cell)
1536 {
1537 log_assert(!cell->name.empty());
1538 log_assert(count_id(cell->name) == 0);
1539 log_assert(refcount_cells_ == 0);
1540 cells_[cell->name] = cell;
1541 cell->module = this;
1542 }
1543
1544 void RTLIL::Module::remove(const pool<RTLIL::Wire*> &wires)
1545 {
1546 log_assert(refcount_wires_ == 0);
1547
1548 struct DeleteWireWorker
1549 {
1550 RTLIL::Module *module;
1551 const pool<RTLIL::Wire*> *wires_p;
1552
1553 void operator()(RTLIL::SigSpec &sig) {
1554 std::vector<RTLIL::SigChunk> chunks = sig;
1555 for (auto &c : chunks)
1556 if (c.wire != NULL && wires_p->count(c.wire)) {
1557 c.wire = module->addWire(NEW_ID, c.width);
1558 c.offset = 0;
1559 }
1560 sig = chunks;
1561 }
1562
1563 void operator()(RTLIL::SigSpec &lhs, RTLIL::SigSpec &rhs) {
1564 log_assert(GetSize(lhs) == GetSize(rhs));
1565 RTLIL::SigSpec new_lhs, new_rhs;
1566 for (int i = 0; i < GetSize(lhs); i++) {
1567 RTLIL::SigBit lhs_bit = lhs[i];
1568 if (lhs_bit.wire != nullptr && wires_p->count(lhs_bit.wire))
1569 continue;
1570 RTLIL::SigBit rhs_bit = rhs[i];
1571 if (rhs_bit.wire != nullptr && wires_p->count(rhs_bit.wire))
1572 continue;
1573 new_lhs.append(lhs_bit);
1574 new_rhs.append(rhs_bit);
1575 }
1576 lhs = new_lhs;
1577 rhs = new_rhs;
1578 }
1579 };
1580
1581 DeleteWireWorker delete_wire_worker;
1582 delete_wire_worker.module = this;
1583 delete_wire_worker.wires_p = &wires;
1584 rewrite_sigspecs2(delete_wire_worker);
1585
1586 for (auto &it : wires) {
1587 log_assert(wires_.count(it->name) != 0);
1588 wires_.erase(it->name);
1589 delete it;
1590 }
1591 }
1592
1593 void RTLIL::Module::remove(RTLIL::Cell *cell)
1594 {
1595 while (!cell->connections_.empty())
1596 cell->unsetPort(cell->connections_.begin()->first);
1597
1598 log_assert(cells_.count(cell->name) != 0);
1599 log_assert(refcount_cells_ == 0);
1600 cells_.erase(cell->name);
1601 delete cell;
1602 }
1603
1604 void RTLIL::Module::rename(RTLIL::Wire *wire, RTLIL::IdString new_name)
1605 {
1606 log_assert(wires_[wire->name] == wire);
1607 log_assert(refcount_wires_ == 0);
1608 wires_.erase(wire->name);
1609 wire->name = new_name;
1610 add(wire);
1611 }
1612
1613 void RTLIL::Module::rename(RTLIL::Cell *cell, RTLIL::IdString new_name)
1614 {
1615 log_assert(cells_[cell->name] == cell);
1616 log_assert(refcount_wires_ == 0);
1617 cells_.erase(cell->name);
1618 cell->name = new_name;
1619 add(cell);
1620 }
1621
1622 void RTLIL::Module::rename(RTLIL::IdString old_name, RTLIL::IdString new_name)
1623 {
1624 log_assert(count_id(old_name) != 0);
1625 if (wires_.count(old_name))
1626 rename(wires_.at(old_name), new_name);
1627 else if (cells_.count(old_name))
1628 rename(cells_.at(old_name), new_name);
1629 else
1630 log_abort();
1631 }
1632
1633 void RTLIL::Module::swap_names(RTLIL::Wire *w1, RTLIL::Wire *w2)
1634 {
1635 log_assert(wires_[w1->name] == w1);
1636 log_assert(wires_[w2->name] == w2);
1637 log_assert(refcount_wires_ == 0);
1638
1639 wires_.erase(w1->name);
1640 wires_.erase(w2->name);
1641
1642 std::swap(w1->name, w2->name);
1643
1644 wires_[w1->name] = w1;
1645 wires_[w2->name] = w2;
1646 }
1647
1648 void RTLIL::Module::swap_names(RTLIL::Cell *c1, RTLIL::Cell *c2)
1649 {
1650 log_assert(cells_[c1->name] == c1);
1651 log_assert(cells_[c2->name] == c2);
1652 log_assert(refcount_cells_ == 0);
1653
1654 cells_.erase(c1->name);
1655 cells_.erase(c2->name);
1656
1657 std::swap(c1->name, c2->name);
1658
1659 cells_[c1->name] = c1;
1660 cells_[c2->name] = c2;
1661 }
1662
1663 RTLIL::IdString RTLIL::Module::uniquify(RTLIL::IdString name)
1664 {
1665 int index = 0;
1666 return uniquify(name, index);
1667 }
1668
1669 RTLIL::IdString RTLIL::Module::uniquify(RTLIL::IdString name, int &index)
1670 {
1671 if (index == 0) {
1672 if (count_id(name) == 0)
1673 return name;
1674 index++;
1675 }
1676
1677 while (1) {
1678 RTLIL::IdString new_name = stringf("%s_%d", name.c_str(), index);
1679 if (count_id(new_name) == 0)
1680 return new_name;
1681 index++;
1682 }
1683 }
1684
1685 static bool fixup_ports_compare(const RTLIL::Wire *a, const RTLIL::Wire *b)
1686 {
1687 if (a->port_id && !b->port_id)
1688 return true;
1689 if (!a->port_id && b->port_id)
1690 return false;
1691
1692 if (a->port_id == b->port_id)
1693 return a->name < b->name;
1694 return a->port_id < b->port_id;
1695 }
1696
1697 void RTLIL::Module::connect(const RTLIL::SigSig &conn)
1698 {
1699 for (auto mon : monitors)
1700 mon->notify_connect(this, conn);
1701
1702 if (design)
1703 for (auto mon : design->monitors)
1704 mon->notify_connect(this, conn);
1705
1706 // ignore all attempts to assign constants to other constants
1707 if (conn.first.has_const()) {
1708 RTLIL::SigSig new_conn;
1709 for (int i = 0; i < GetSize(conn.first); i++)
1710 if (conn.first[i].wire) {
1711 new_conn.first.append(conn.first[i]);
1712 new_conn.second.append(conn.second[i]);
1713 }
1714 if (GetSize(new_conn.first))
1715 connect(new_conn);
1716 return;
1717 }
1718
1719 if (yosys_xtrace) {
1720 log("#X# Connect (SigSig) in %s: %s = %s (%d bits)\n", log_id(this), log_signal(conn.first), log_signal(conn.second), GetSize(conn.first));
1721 log_backtrace("-X- ", yosys_xtrace-1);
1722 }
1723
1724 log_assert(GetSize(conn.first) == GetSize(conn.second));
1725 connections_.push_back(conn);
1726 }
1727
1728 void RTLIL::Module::connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs)
1729 {
1730 connect(RTLIL::SigSig(lhs, rhs));
1731 }
1732
1733 void RTLIL::Module::new_connections(const std::vector<RTLIL::SigSig> &new_conn)
1734 {
1735 for (auto mon : monitors)
1736 mon->notify_connect(this, new_conn);
1737
1738 if (design)
1739 for (auto mon : design->monitors)
1740 mon->notify_connect(this, new_conn);
1741
1742 if (yosys_xtrace) {
1743 log("#X# New connections vector in %s:\n", log_id(this));
1744 for (auto &conn: new_conn)
1745 log("#X# %s = %s (%d bits)\n", log_signal(conn.first), log_signal(conn.second), GetSize(conn.first));
1746 log_backtrace("-X- ", yosys_xtrace-1);
1747 }
1748
1749 connections_ = new_conn;
1750 }
1751
1752 const std::vector<RTLIL::SigSig> &RTLIL::Module::connections() const
1753 {
1754 return connections_;
1755 }
1756
1757 void RTLIL::Module::fixup_ports()
1758 {
1759 std::vector<RTLIL::Wire*> all_ports;
1760
1761 for (auto &w : wires_)
1762 if (w.second->port_input || w.second->port_output)
1763 all_ports.push_back(w.second);
1764 else
1765 w.second->port_id = 0;
1766
1767 std::sort(all_ports.begin(), all_ports.end(), fixup_ports_compare);
1768
1769 ports.clear();
1770 for (size_t i = 0; i < all_ports.size(); i++) {
1771 ports.push_back(all_ports[i]->name);
1772 all_ports[i]->port_id = i+1;
1773 }
1774 }
1775
1776 RTLIL::Wire *RTLIL::Module::addWire(RTLIL::IdString name, int width)
1777 {
1778 RTLIL::Wire *wire = new RTLIL::Wire;
1779 wire->name = name;
1780 wire->width = width;
1781 add(wire);
1782 return wire;
1783 }
1784
1785 RTLIL::Wire *RTLIL::Module::addWire(RTLIL::IdString name, const RTLIL::Wire *other)
1786 {
1787 RTLIL::Wire *wire = addWire(name);
1788 wire->width = other->width;
1789 wire->start_offset = other->start_offset;
1790 wire->port_id = other->port_id;
1791 wire->port_input = other->port_input;
1792 wire->port_output = other->port_output;
1793 wire->upto = other->upto;
1794 wire->attributes = other->attributes;
1795 return wire;
1796 }
1797
1798 RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, RTLIL::IdString type)
1799 {
1800 RTLIL::Cell *cell = new RTLIL::Cell;
1801 cell->name = name;
1802 cell->type = type;
1803 add(cell);
1804 return cell;
1805 }
1806
1807 RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, const RTLIL::Cell *other)
1808 {
1809 RTLIL::Cell *cell = addCell(name, other->type);
1810 cell->connections_ = other->connections_;
1811 cell->parameters = other->parameters;
1812 cell->attributes = other->attributes;
1813 return cell;
1814 }
1815
1816 #define DEF_METHOD(_func, _y_size, _type) \
1817 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed, const std::string &src) { \
1818 RTLIL::Cell *cell = addCell(name, _type); \
1819 cell->parameters["\\A_SIGNED"] = is_signed; \
1820 cell->parameters["\\A_WIDTH"] = sig_a.size(); \
1821 cell->parameters["\\Y_WIDTH"] = sig_y.size(); \
1822 cell->setPort("\\A", sig_a); \
1823 cell->setPort("\\Y", sig_y); \
1824 cell->set_src_attribute(src); \
1825 return cell; \
1826 } \
1827 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed, const std::string &src) { \
1828 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
1829 add ## _func(name, sig_a, sig_y, is_signed, src); \
1830 return sig_y; \
1831 }
1832 DEF_METHOD(Not, sig_a.size(), "$not")
1833 DEF_METHOD(Pos, sig_a.size(), "$pos")
1834 DEF_METHOD(Neg, sig_a.size(), "$neg")
1835 DEF_METHOD(ReduceAnd, 1, "$reduce_and")
1836 DEF_METHOD(ReduceOr, 1, "$reduce_or")
1837 DEF_METHOD(ReduceXor, 1, "$reduce_xor")
1838 DEF_METHOD(ReduceXnor, 1, "$reduce_xnor")
1839 DEF_METHOD(ReduceBool, 1, "$reduce_bool")
1840 DEF_METHOD(LogicNot, 1, "$logic_not")
1841 #undef DEF_METHOD
1842
1843 #define DEF_METHOD(_func, _y_size, _type) \
1844 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed, const std::string &src) { \
1845 RTLIL::Cell *cell = addCell(name, _type); \
1846 cell->parameters["\\A_SIGNED"] = is_signed; \
1847 cell->parameters["\\B_SIGNED"] = is_signed; \
1848 cell->parameters["\\A_WIDTH"] = sig_a.size(); \
1849 cell->parameters["\\B_WIDTH"] = sig_b.size(); \
1850 cell->parameters["\\Y_WIDTH"] = sig_y.size(); \
1851 cell->setPort("\\A", sig_a); \
1852 cell->setPort("\\B", sig_b); \
1853 cell->setPort("\\Y", sig_y); \
1854 cell->set_src_attribute(src); \
1855 return cell; \
1856 } \
1857 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed, const std::string &src) { \
1858 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
1859 add ## _func(name, sig_a, sig_b, sig_y, is_signed, src); \
1860 return sig_y; \
1861 }
1862 DEF_METHOD(And, max(sig_a.size(), sig_b.size()), "$and")
1863 DEF_METHOD(Or, max(sig_a.size(), sig_b.size()), "$or")
1864 DEF_METHOD(Xor, max(sig_a.size(), sig_b.size()), "$xor")
1865 DEF_METHOD(Xnor, max(sig_a.size(), sig_b.size()), "$xnor")
1866 DEF_METHOD(Shl, sig_a.size(), "$shl")
1867 DEF_METHOD(Shr, sig_a.size(), "$shr")
1868 DEF_METHOD(Sshl, sig_a.size(), "$sshl")
1869 DEF_METHOD(Sshr, sig_a.size(), "$sshr")
1870 DEF_METHOD(Shift, sig_a.size(), "$shift")
1871 DEF_METHOD(Shiftx, sig_a.size(), "$shiftx")
1872 DEF_METHOD(Lt, 1, "$lt")
1873 DEF_METHOD(Le, 1, "$le")
1874 DEF_METHOD(Eq, 1, "$eq")
1875 DEF_METHOD(Ne, 1, "$ne")
1876 DEF_METHOD(Eqx, 1, "$eqx")
1877 DEF_METHOD(Nex, 1, "$nex")
1878 DEF_METHOD(Ge, 1, "$ge")
1879 DEF_METHOD(Gt, 1, "$gt")
1880 DEF_METHOD(Add, max(sig_a.size(), sig_b.size()), "$add")
1881 DEF_METHOD(Sub, max(sig_a.size(), sig_b.size()), "$sub")
1882 DEF_METHOD(Mul, max(sig_a.size(), sig_b.size()), "$mul")
1883 DEF_METHOD(Div, max(sig_a.size(), sig_b.size()), "$div")
1884 DEF_METHOD(Mod, max(sig_a.size(), sig_b.size()), "$mod")
1885 DEF_METHOD(LogicAnd, 1, "$logic_and")
1886 DEF_METHOD(LogicOr, 1, "$logic_or")
1887 #undef DEF_METHOD
1888
1889 #define DEF_METHOD(_func, _type, _pmux) \
1890 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, RTLIL::SigSpec sig_y, const std::string &src) { \
1891 RTLIL::Cell *cell = addCell(name, _type); \
1892 cell->parameters["\\WIDTH"] = sig_a.size(); \
1893 if (_pmux) cell->parameters["\\S_WIDTH"] = sig_s.size(); \
1894 cell->setPort("\\A", sig_a); \
1895 cell->setPort("\\B", sig_b); \
1896 cell->setPort("\\S", sig_s); \
1897 cell->setPort("\\Y", sig_y); \
1898 cell->set_src_attribute(src); \
1899 return cell; \
1900 } \
1901 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, const std::string &src) { \
1902 RTLIL::SigSpec sig_y = addWire(NEW_ID, sig_a.size()); \
1903 add ## _func(name, sig_a, sig_b, sig_s, sig_y, src); \
1904 return sig_y; \
1905 }
1906 DEF_METHOD(Mux, "$mux", 0)
1907 DEF_METHOD(Pmux, "$pmux", 1)
1908 #undef DEF_METHOD
1909
1910 #define DEF_METHOD_2(_func, _type, _P1, _P2) \
1911 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, const std::string &src) { \
1912 RTLIL::Cell *cell = addCell(name, _type); \
1913 cell->setPort("\\" #_P1, sig1); \
1914 cell->setPort("\\" #_P2, sig2); \
1915 cell->set_src_attribute(src); \
1916 return cell; \
1917 } \
1918 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, const std::string &src) { \
1919 RTLIL::SigBit sig2 = addWire(NEW_ID); \
1920 add ## _func(name, sig1, sig2, src); \
1921 return sig2; \
1922 }
1923 #define DEF_METHOD_3(_func, _type, _P1, _P2, _P3) \
1924 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, const std::string &src) { \
1925 RTLIL::Cell *cell = addCell(name, _type); \
1926 cell->setPort("\\" #_P1, sig1); \
1927 cell->setPort("\\" #_P2, sig2); \
1928 cell->setPort("\\" #_P3, sig3); \
1929 cell->set_src_attribute(src); \
1930 return cell; \
1931 } \
1932 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, const std::string &src) { \
1933 RTLIL::SigBit sig3 = addWire(NEW_ID); \
1934 add ## _func(name, sig1, sig2, sig3, src); \
1935 return sig3; \
1936 }
1937 #define DEF_METHOD_4(_func, _type, _P1, _P2, _P3, _P4) \
1938 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, RTLIL::SigBit sig4, const std::string &src) { \
1939 RTLIL::Cell *cell = addCell(name, _type); \
1940 cell->setPort("\\" #_P1, sig1); \
1941 cell->setPort("\\" #_P2, sig2); \
1942 cell->setPort("\\" #_P3, sig3); \
1943 cell->setPort("\\" #_P4, sig4); \
1944 cell->set_src_attribute(src); \
1945 return cell; \
1946 } \
1947 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, const std::string &src) { \
1948 RTLIL::SigBit sig4 = addWire(NEW_ID); \
1949 add ## _func(name, sig1, sig2, sig3, sig4, src); \
1950 return sig4; \
1951 }
1952 #define DEF_METHOD_5(_func, _type, _P1, _P2, _P3, _P4, _P5) \
1953 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, RTLIL::SigBit sig4, RTLIL::SigBit sig5, const std::string &src) { \
1954 RTLIL::Cell *cell = addCell(name, _type); \
1955 cell->setPort("\\" #_P1, sig1); \
1956 cell->setPort("\\" #_P2, sig2); \
1957 cell->setPort("\\" #_P3, sig3); \
1958 cell->setPort("\\" #_P4, sig4); \
1959 cell->setPort("\\" #_P5, sig5); \
1960 cell->set_src_attribute(src); \
1961 return cell; \
1962 } \
1963 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, RTLIL::SigBit sig4, const std::string &src) { \
1964 RTLIL::SigBit sig5 = addWire(NEW_ID); \
1965 add ## _func(name, sig1, sig2, sig3, sig4, sig5, src); \
1966 return sig5; \
1967 }
1968 DEF_METHOD_2(BufGate, "$_BUF_", A, Y)
1969 DEF_METHOD_2(NotGate, "$_NOT_", A, Y)
1970 DEF_METHOD_3(AndGate, "$_AND_", A, B, Y)
1971 DEF_METHOD_3(NandGate, "$_NAND_", A, B, Y)
1972 DEF_METHOD_3(OrGate, "$_OR_", A, B, Y)
1973 DEF_METHOD_3(NorGate, "$_NOR_", A, B, Y)
1974 DEF_METHOD_3(XorGate, "$_XOR_", A, B, Y)
1975 DEF_METHOD_3(XnorGate, "$_XNOR_", A, B, Y)
1976 DEF_METHOD_3(AndnotGate, "$_ANDNOT_", A, B, Y)
1977 DEF_METHOD_3(OrnotGate, "$_ORNOT_", A, B, Y)
1978 DEF_METHOD_4(MuxGate, "$_MUX_", A, B, S, Y)
1979 DEF_METHOD_4(Aoi3Gate, "$_AOI3_", A, B, C, Y)
1980 DEF_METHOD_4(Oai3Gate, "$_OAI3_", A, B, C, Y)
1981 DEF_METHOD_5(Aoi4Gate, "$_AOI4_", A, B, C, D, Y)
1982 DEF_METHOD_5(Oai4Gate, "$_OAI4_", A, B, C, D, Y)
1983 #undef DEF_METHOD_2
1984 #undef DEF_METHOD_3
1985 #undef DEF_METHOD_4
1986 #undef DEF_METHOD_5
1987
1988 RTLIL::Cell* RTLIL::Module::addPow(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool a_signed, bool b_signed, const std::string &src)
1989 {
1990 RTLIL::Cell *cell = addCell(name, "$pow");
1991 cell->parameters["\\A_SIGNED"] = a_signed;
1992 cell->parameters["\\B_SIGNED"] = b_signed;
1993 cell->parameters["\\A_WIDTH"] = sig_a.size();
1994 cell->parameters["\\B_WIDTH"] = sig_b.size();
1995 cell->parameters["\\Y_WIDTH"] = sig_y.size();
1996 cell->setPort("\\A", sig_a);
1997 cell->setPort("\\B", sig_b);
1998 cell->setPort("\\Y", sig_y);
1999 cell->set_src_attribute(src);
2000 return cell;
2001 }
2002
2003 RTLIL::Cell* RTLIL::Module::addSlice(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, RTLIL::Const offset, const std::string &src)
2004 {
2005 RTLIL::Cell *cell = addCell(name, "$slice");
2006 cell->parameters["\\A_WIDTH"] = sig_a.size();
2007 cell->parameters["\\Y_WIDTH"] = sig_y.size();
2008 cell->parameters["\\OFFSET"] = offset;
2009 cell->setPort("\\A", sig_a);
2010 cell->setPort("\\Y", sig_y);
2011 cell->set_src_attribute(src);
2012 return cell;
2013 }
2014
2015 RTLIL::Cell* RTLIL::Module::addConcat(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, const std::string &src)
2016 {
2017 RTLIL::Cell *cell = addCell(name, "$concat");
2018 cell->parameters["\\A_WIDTH"] = sig_a.size();
2019 cell->parameters["\\B_WIDTH"] = sig_b.size();
2020 cell->setPort("\\A", sig_a);
2021 cell->setPort("\\B", sig_b);
2022 cell->setPort("\\Y", sig_y);
2023 cell->set_src_attribute(src);
2024 return cell;
2025 }
2026
2027 RTLIL::Cell* RTLIL::Module::addLut(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, RTLIL::Const lut, const std::string &src)
2028 {
2029 RTLIL::Cell *cell = addCell(name, "$lut");
2030 cell->parameters["\\LUT"] = lut;
2031 cell->parameters["\\WIDTH"] = sig_a.size();
2032 cell->setPort("\\A", sig_a);
2033 cell->setPort("\\Y", sig_y);
2034 cell->set_src_attribute(src);
2035 return cell;
2036 }
2037
2038 RTLIL::Cell* RTLIL::Module::addTribuf(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_y, const std::string &src)
2039 {
2040 RTLIL::Cell *cell = addCell(name, "$tribuf");
2041 cell->parameters["\\WIDTH"] = sig_a.size();
2042 cell->setPort("\\A", sig_a);
2043 cell->setPort("\\EN", sig_en);
2044 cell->setPort("\\Y", sig_y);
2045 cell->set_src_attribute(src);
2046 return cell;
2047 }
2048
2049 RTLIL::Cell* RTLIL::Module::addAssert(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src)
2050 {
2051 RTLIL::Cell *cell = addCell(name, "$assert");
2052 cell->setPort("\\A", sig_a);
2053 cell->setPort("\\EN", sig_en);
2054 cell->set_src_attribute(src);
2055 return cell;
2056 }
2057
2058 RTLIL::Cell* RTLIL::Module::addAssume(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src)
2059 {
2060 RTLIL::Cell *cell = addCell(name, "$assume");
2061 cell->setPort("\\A", sig_a);
2062 cell->setPort("\\EN", sig_en);
2063 cell->set_src_attribute(src);
2064 return cell;
2065 }
2066
2067 RTLIL::Cell* RTLIL::Module::addLive(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src)
2068 {
2069 RTLIL::Cell *cell = addCell(name, "$live");
2070 cell->setPort("\\A", sig_a);
2071 cell->setPort("\\EN", sig_en);
2072 cell->set_src_attribute(src);
2073 return cell;
2074 }
2075
2076 RTLIL::Cell* RTLIL::Module::addFair(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src)
2077 {
2078 RTLIL::Cell *cell = addCell(name, "$fair");
2079 cell->setPort("\\A", sig_a);
2080 cell->setPort("\\EN", sig_en);
2081 cell->set_src_attribute(src);
2082 return cell;
2083 }
2084
2085 RTLIL::Cell* RTLIL::Module::addCover(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src)
2086 {
2087 RTLIL::Cell *cell = addCell(name, "$cover");
2088 cell->setPort("\\A", sig_a);
2089 cell->setPort("\\EN", sig_en);
2090 cell->set_src_attribute(src);
2091 return cell;
2092 }
2093
2094 RTLIL::Cell* RTLIL::Module::addEquiv(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, const std::string &src)
2095 {
2096 RTLIL::Cell *cell = addCell(name, "$equiv");
2097 cell->setPort("\\A", sig_a);
2098 cell->setPort("\\B", sig_b);
2099 cell->setPort("\\Y", sig_y);
2100 cell->set_src_attribute(src);
2101 return cell;
2102 }
2103
2104 RTLIL::Cell* RTLIL::Module::addSr(RTLIL::IdString name, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr, RTLIL::SigSpec sig_q, bool set_polarity, bool clr_polarity, const std::string &src)
2105 {
2106 RTLIL::Cell *cell = addCell(name, "$sr");
2107 cell->parameters["\\SET_POLARITY"] = set_polarity;
2108 cell->parameters["\\CLR_POLARITY"] = clr_polarity;
2109 cell->parameters["\\WIDTH"] = sig_q.size();
2110 cell->setPort("\\SET", sig_set);
2111 cell->setPort("\\CLR", sig_clr);
2112 cell->setPort("\\Q", sig_q);
2113 cell->set_src_attribute(src);
2114 return cell;
2115 }
2116
2117 RTLIL::Cell* RTLIL::Module::addFf(RTLIL::IdString name, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, const std::string &src)
2118 {
2119 RTLIL::Cell *cell = addCell(name, "$ff");
2120 cell->parameters["\\WIDTH"] = sig_q.size();
2121 cell->setPort("\\D", sig_d);
2122 cell->setPort("\\Q", sig_q);
2123 cell->set_src_attribute(src);
2124 return cell;
2125 }
2126
2127 RTLIL::Cell* RTLIL::Module::addDff(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, const std::string &src)
2128 {
2129 RTLIL::Cell *cell = addCell(name, "$dff");
2130 cell->parameters["\\CLK_POLARITY"] = clk_polarity;
2131 cell->parameters["\\WIDTH"] = sig_q.size();
2132 cell->setPort("\\CLK", sig_clk);
2133 cell->setPort("\\D", sig_d);
2134 cell->setPort("\\Q", sig_q);
2135 cell->set_src_attribute(src);
2136 return cell;
2137 }
2138
2139 RTLIL::Cell* RTLIL::Module::addDffe(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, bool en_polarity, const std::string &src)
2140 {
2141 RTLIL::Cell *cell = addCell(name, "$dffe");
2142 cell->parameters["\\CLK_POLARITY"] = clk_polarity;
2143 cell->parameters["\\EN_POLARITY"] = en_polarity;
2144 cell->parameters["\\WIDTH"] = sig_q.size();
2145 cell->setPort("\\CLK", sig_clk);
2146 cell->setPort("\\EN", sig_en);
2147 cell->setPort("\\D", sig_d);
2148 cell->setPort("\\Q", sig_q);
2149 cell->set_src_attribute(src);
2150 return cell;
2151 }
2152
2153 RTLIL::Cell* RTLIL::Module::addDffsr(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
2154 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
2155 {
2156 RTLIL::Cell *cell = addCell(name, "$dffsr");
2157 cell->parameters["\\CLK_POLARITY"] = clk_polarity;
2158 cell->parameters["\\SET_POLARITY"] = set_polarity;
2159 cell->parameters["\\CLR_POLARITY"] = clr_polarity;
2160 cell->parameters["\\WIDTH"] = sig_q.size();
2161 cell->setPort("\\CLK", sig_clk);
2162 cell->setPort("\\SET", sig_set);
2163 cell->setPort("\\CLR", sig_clr);
2164 cell->setPort("\\D", sig_d);
2165 cell->setPort("\\Q", sig_q);
2166 cell->set_src_attribute(src);
2167 return cell;
2168 }
2169
2170 RTLIL::Cell* RTLIL::Module::addAdff(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_arst, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q,
2171 RTLIL::Const arst_value, bool clk_polarity, bool arst_polarity, const std::string &src)
2172 {
2173 RTLIL::Cell *cell = addCell(name, "$adff");
2174 cell->parameters["\\CLK_POLARITY"] = clk_polarity;
2175 cell->parameters["\\ARST_POLARITY"] = arst_polarity;
2176 cell->parameters["\\ARST_VALUE"] = arst_value;
2177 cell->parameters["\\WIDTH"] = sig_q.size();
2178 cell->setPort("\\CLK", sig_clk);
2179 cell->setPort("\\ARST", sig_arst);
2180 cell->setPort("\\D", sig_d);
2181 cell->setPort("\\Q", sig_q);
2182 cell->set_src_attribute(src);
2183 return cell;
2184 }
2185
2186 RTLIL::Cell* RTLIL::Module::addDlatch(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity, const std::string &src)
2187 {
2188 RTLIL::Cell *cell = addCell(name, "$dlatch");
2189 cell->parameters["\\EN_POLARITY"] = en_polarity;
2190 cell->parameters["\\WIDTH"] = sig_q.size();
2191 cell->setPort("\\EN", sig_en);
2192 cell->setPort("\\D", sig_d);
2193 cell->setPort("\\Q", sig_q);
2194 cell->set_src_attribute(src);
2195 return cell;
2196 }
2197
2198 RTLIL::Cell* RTLIL::Module::addDlatchsr(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
2199 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
2200 {
2201 RTLIL::Cell *cell = addCell(name, "$dlatchsr");
2202 cell->parameters["\\EN_POLARITY"] = en_polarity;
2203 cell->parameters["\\SET_POLARITY"] = set_polarity;
2204 cell->parameters["\\CLR_POLARITY"] = clr_polarity;
2205 cell->parameters["\\WIDTH"] = sig_q.size();
2206 cell->setPort("\\EN", sig_en);
2207 cell->setPort("\\SET", sig_set);
2208 cell->setPort("\\CLR", sig_clr);
2209 cell->setPort("\\D", sig_d);
2210 cell->setPort("\\Q", sig_q);
2211 cell->set_src_attribute(src);
2212 return cell;
2213 }
2214
2215 RTLIL::Cell* RTLIL::Module::addFfGate(RTLIL::IdString name, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, const std::string &src)
2216 {
2217 RTLIL::Cell *cell = addCell(name, "$_FF_");
2218 cell->setPort("\\D", sig_d);
2219 cell->setPort("\\Q", sig_q);
2220 cell->set_src_attribute(src);
2221 return cell;
2222 }
2223
2224 RTLIL::Cell* RTLIL::Module::addDffGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, const std::string &src)
2225 {
2226 RTLIL::Cell *cell = addCell(name, stringf("$_DFF_%c_", clk_polarity ? 'P' : 'N'));
2227 cell->setPort("\\C", sig_clk);
2228 cell->setPort("\\D", sig_d);
2229 cell->setPort("\\Q", sig_q);
2230 cell->set_src_attribute(src);
2231 return cell;
2232 }
2233
2234 RTLIL::Cell* RTLIL::Module::addDffeGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, bool en_polarity, const std::string &src)
2235 {
2236 RTLIL::Cell *cell = addCell(name, stringf("$_DFFE_%c%c_", clk_polarity ? 'P' : 'N', en_polarity ? 'P' : 'N'));
2237 cell->setPort("\\C", sig_clk);
2238 cell->setPort("\\E", sig_en);
2239 cell->setPort("\\D", sig_d);
2240 cell->setPort("\\Q", sig_q);
2241 cell->set_src_attribute(src);
2242 return cell;
2243 }
2244
2245 RTLIL::Cell* RTLIL::Module::addDffsrGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
2246 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
2247 {
2248 RTLIL::Cell *cell = addCell(name, stringf("$_DFFSR_%c%c%c_", clk_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N'));
2249 cell->setPort("\\C", sig_clk);
2250 cell->setPort("\\S", sig_set);
2251 cell->setPort("\\R", sig_clr);
2252 cell->setPort("\\D", sig_d);
2253 cell->setPort("\\Q", sig_q);
2254 cell->set_src_attribute(src);
2255 return cell;
2256 }
2257
2258 RTLIL::Cell* RTLIL::Module::addAdffGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_arst, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q,
2259 bool arst_value, bool clk_polarity, bool arst_polarity, const std::string &src)
2260 {
2261 RTLIL::Cell *cell = addCell(name, stringf("$_DFF_%c%c%c_", clk_polarity ? 'P' : 'N', arst_polarity ? 'P' : 'N', arst_value ? '1' : '0'));
2262 cell->setPort("\\C", sig_clk);
2263 cell->setPort("\\R", sig_arst);
2264 cell->setPort("\\D", sig_d);
2265 cell->setPort("\\Q", sig_q);
2266 cell->set_src_attribute(src);
2267 return cell;
2268 }
2269
2270 RTLIL::Cell* RTLIL::Module::addDlatchGate(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity, const std::string &src)
2271 {
2272 RTLIL::Cell *cell = addCell(name, stringf("$_DLATCH_%c_", en_polarity ? 'P' : 'N'));
2273 cell->setPort("\\E", sig_en);
2274 cell->setPort("\\D", sig_d);
2275 cell->setPort("\\Q", sig_q);
2276 cell->set_src_attribute(src);
2277 return cell;
2278 }
2279
2280 RTLIL::Cell* RTLIL::Module::addDlatchsrGate(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
2281 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
2282 {
2283 RTLIL::Cell *cell = addCell(name, stringf("$_DLATCHSR_%c%c%c_", en_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N'));
2284 cell->setPort("\\E", sig_en);
2285 cell->setPort("\\S", sig_set);
2286 cell->setPort("\\R", sig_clr);
2287 cell->setPort("\\D", sig_d);
2288 cell->setPort("\\Q", sig_q);
2289 cell->set_src_attribute(src);
2290 return cell;
2291 }
2292
2293 RTLIL::SigSpec RTLIL::Module::Anyconst(RTLIL::IdString name, int width, const std::string &src)
2294 {
2295 RTLIL::SigSpec sig = addWire(NEW_ID, width);
2296 Cell *cell = addCell(name, "$anyconst");
2297 cell->setParam("\\WIDTH", width);
2298 cell->setPort("\\Y", sig);
2299 cell->set_src_attribute(src);
2300 return sig;
2301 }
2302
2303 RTLIL::SigSpec RTLIL::Module::Anyseq(RTLIL::IdString name, int width, const std::string &src)
2304 {
2305 RTLIL::SigSpec sig = addWire(NEW_ID, width);
2306 Cell *cell = addCell(name, "$anyseq");
2307 cell->setParam("\\WIDTH", width);
2308 cell->setPort("\\Y", sig);
2309 cell->set_src_attribute(src);
2310 return sig;
2311 }
2312
2313 RTLIL::SigSpec RTLIL::Module::Allconst(RTLIL::IdString name, int width, const std::string &src)
2314 {
2315 RTLIL::SigSpec sig = addWire(NEW_ID, width);
2316 Cell *cell = addCell(name, "$allconst");
2317 cell->setParam("\\WIDTH", width);
2318 cell->setPort("\\Y", sig);
2319 cell->set_src_attribute(src);
2320 return sig;
2321 }
2322
2323 RTLIL::SigSpec RTLIL::Module::Allseq(RTLIL::IdString name, int width, const std::string &src)
2324 {
2325 RTLIL::SigSpec sig = addWire(NEW_ID, width);
2326 Cell *cell = addCell(name, "$allseq");
2327 cell->setParam("\\WIDTH", width);
2328 cell->setPort("\\Y", sig);
2329 cell->set_src_attribute(src);
2330 return sig;
2331 }
2332
2333 RTLIL::SigSpec RTLIL::Module::Initstate(RTLIL::IdString name, const std::string &src)
2334 {
2335 RTLIL::SigSpec sig = addWire(NEW_ID);
2336 Cell *cell = addCell(name, "$initstate");
2337 cell->setPort("\\Y", sig);
2338 cell->set_src_attribute(src);
2339 return sig;
2340 }
2341
2342 RTLIL::Wire::Wire()
2343 {
2344 static unsigned int hashidx_count = 123456789;
2345 hashidx_count = mkhash_xorshift(hashidx_count);
2346 hashidx_ = hashidx_count;
2347
2348 module = nullptr;
2349 width = 1;
2350 start_offset = 0;
2351 port_id = 0;
2352 port_input = false;
2353 port_output = false;
2354 upto = false;
2355
2356 #ifdef WITH_PYTHON
2357 RTLIL::Wire::get_all_wires()->insert(std::pair<unsigned int, RTLIL::Wire*>(hashidx_, this));
2358 #endif
2359 }
2360
2361 RTLIL::Wire::~Wire()
2362 {
2363 #ifdef WITH_PYTHON
2364 RTLIL::Wire::get_all_wires()->erase(hashidx_);
2365 #endif
2366 }
2367
2368 #ifdef WITH_PYTHON
2369 static std::map<unsigned int, RTLIL::Wire*> all_wires;
2370 std::map<unsigned int, RTLIL::Wire*> *RTLIL::Wire::get_all_wires(void)
2371 {
2372 return &all_wires;
2373 }
2374 #endif
2375
2376 RTLIL::Memory::Memory()
2377 {
2378 static unsigned int hashidx_count = 123456789;
2379 hashidx_count = mkhash_xorshift(hashidx_count);
2380 hashidx_ = hashidx_count;
2381
2382 width = 1;
2383 start_offset = 0;
2384 size = 0;
2385 #ifdef WITH_PYTHON
2386 RTLIL::Memory::get_all_memorys()->insert(std::pair<unsigned int, RTLIL::Memory*>(hashidx_, this));
2387 #endif
2388 }
2389
2390 RTLIL::Cell::Cell() : module(nullptr)
2391 {
2392 static unsigned int hashidx_count = 123456789;
2393 hashidx_count = mkhash_xorshift(hashidx_count);
2394 hashidx_ = hashidx_count;
2395
2396 // log("#memtrace# %p\n", this);
2397 memhasher();
2398
2399 #ifdef WITH_PYTHON
2400 RTLIL::Cell::get_all_cells()->insert(std::pair<unsigned int, RTLIL::Cell*>(hashidx_, this));
2401 #endif
2402 }
2403
2404 RTLIL::Cell::~Cell()
2405 {
2406 #ifdef WITH_PYTHON
2407 RTLIL::Cell::get_all_cells()->erase(hashidx_);
2408 #endif
2409 }
2410
2411 #ifdef WITH_PYTHON
2412 static std::map<unsigned int, RTLIL::Cell*> all_cells;
2413 std::map<unsigned int, RTLIL::Cell*> *RTLIL::Cell::get_all_cells(void)
2414 {
2415 return &all_cells;
2416 }
2417 #endif
2418
2419 bool RTLIL::Cell::hasPort(RTLIL::IdString portname) const
2420 {
2421 return connections_.count(portname) != 0;
2422 }
2423
2424 void RTLIL::Cell::unsetPort(RTLIL::IdString portname)
2425 {
2426 RTLIL::SigSpec signal;
2427 auto conn_it = connections_.find(portname);
2428
2429 if (conn_it != connections_.end())
2430 {
2431 for (auto mon : module->monitors)
2432 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
2433
2434 if (module->design)
2435 for (auto mon : module->design->monitors)
2436 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
2437
2438 if (yosys_xtrace) {
2439 log("#X# Unconnect %s.%s.%s\n", log_id(this->module), log_id(this), log_id(portname));
2440 log_backtrace("-X- ", yosys_xtrace-1);
2441 }
2442
2443 connections_.erase(conn_it);
2444 }
2445 }
2446
2447 void RTLIL::Cell::setPort(RTLIL::IdString portname, RTLIL::SigSpec signal)
2448 {
2449 auto conn_it = connections_.find(portname);
2450
2451 if (conn_it == connections_.end()) {
2452 connections_[portname] = RTLIL::SigSpec();
2453 conn_it = connections_.find(portname);
2454 log_assert(conn_it != connections_.end());
2455 } else
2456 if (conn_it->second == signal)
2457 return;
2458
2459 for (auto mon : module->monitors)
2460 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
2461
2462 if (module->design)
2463 for (auto mon : module->design->monitors)
2464 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
2465
2466 if (yosys_xtrace) {
2467 log("#X# Connect %s.%s.%s = %s (%d)\n", log_id(this->module), log_id(this), log_id(portname), log_signal(signal), GetSize(signal));
2468 log_backtrace("-X- ", yosys_xtrace-1);
2469 }
2470
2471 conn_it->second = signal;
2472 }
2473
2474 const RTLIL::SigSpec &RTLIL::Cell::getPort(RTLIL::IdString portname) const
2475 {
2476 return connections_.at(portname);
2477 }
2478
2479 const dict<RTLIL::IdString, RTLIL::SigSpec> &RTLIL::Cell::connections() const
2480 {
2481 return connections_;
2482 }
2483
2484 bool RTLIL::Cell::known() const
2485 {
2486 if (yosys_celltypes.cell_known(type))
2487 return true;
2488 if (module && module->design && module->design->module(type))
2489 return true;
2490 return false;
2491 }
2492
2493 bool RTLIL::Cell::input(RTLIL::IdString portname) const
2494 {
2495 if (yosys_celltypes.cell_known(type))
2496 return yosys_celltypes.cell_input(type, portname);
2497 if (module && module->design) {
2498 RTLIL::Module *m = module->design->module(type);
2499 RTLIL::Wire *w = m ? m->wire(portname) : nullptr;
2500 return w && w->port_input;
2501 }
2502 return false;
2503 }
2504
2505 bool RTLIL::Cell::output(RTLIL::IdString portname) const
2506 {
2507 if (yosys_celltypes.cell_known(type))
2508 return yosys_celltypes.cell_output(type, portname);
2509 if (module && module->design) {
2510 RTLIL::Module *m = module->design->module(type);
2511 RTLIL::Wire *w = m ? m->wire(portname) : nullptr;
2512 return w && w->port_output;
2513 }
2514 return false;
2515 }
2516
2517 bool RTLIL::Cell::hasParam(RTLIL::IdString paramname) const
2518 {
2519 return parameters.count(paramname) != 0;
2520 }
2521
2522 void RTLIL::Cell::unsetParam(RTLIL::IdString paramname)
2523 {
2524 parameters.erase(paramname);
2525 }
2526
2527 void RTLIL::Cell::setParam(RTLIL::IdString paramname, RTLIL::Const value)
2528 {
2529 parameters[paramname] = value;
2530 }
2531
2532 const RTLIL::Const &RTLIL::Cell::getParam(RTLIL::IdString paramname) const
2533 {
2534 return parameters.at(paramname);
2535 }
2536
2537 void RTLIL::Cell::sort()
2538 {
2539 connections_.sort(sort_by_id_str());
2540 parameters.sort(sort_by_id_str());
2541 attributes.sort(sort_by_id_str());
2542 }
2543
2544 void RTLIL::Cell::check()
2545 {
2546 #ifndef NDEBUG
2547 InternalCellChecker checker(NULL, this);
2548 checker.check();
2549 #endif
2550 }
2551
2552 void RTLIL::Cell::fixup_parameters(bool set_a_signed, bool set_b_signed)
2553 {
2554 if (type.substr(0, 1) != "$" || type.substr(0, 2) == "$_" || type.substr(0, 8) == "$paramod" || type.substr(0,10) == "$fmcombine" ||
2555 type.substr(0, 9) == "$verific$" || type.substr(0, 7) == "$array:" || type.substr(0, 8) == "$extern:")
2556 return;
2557
2558 if (type == "$mux" || type == "$pmux") {
2559 parameters["\\WIDTH"] = GetSize(connections_["\\Y"]);
2560 if (type == "$pmux")
2561 parameters["\\S_WIDTH"] = GetSize(connections_["\\S"]);
2562 check();
2563 return;
2564 }
2565
2566 if (type == "$lut" || type == "$sop") {
2567 parameters["\\WIDTH"] = GetSize(connections_["\\A"]);
2568 return;
2569 }
2570
2571 if (type == "$fa") {
2572 parameters["\\WIDTH"] = GetSize(connections_["\\Y"]);
2573 return;
2574 }
2575
2576 if (type == "$lcu") {
2577 parameters["\\WIDTH"] = GetSize(connections_["\\CO"]);
2578 return;
2579 }
2580
2581 bool signedness_ab = !type.in("$slice", "$concat", "$macc");
2582
2583 if (connections_.count("\\A")) {
2584 if (signedness_ab) {
2585 if (set_a_signed)
2586 parameters["\\A_SIGNED"] = true;
2587 else if (parameters.count("\\A_SIGNED") == 0)
2588 parameters["\\A_SIGNED"] = false;
2589 }
2590 parameters["\\A_WIDTH"] = GetSize(connections_["\\A"]);
2591 }
2592
2593 if (connections_.count("\\B")) {
2594 if (signedness_ab) {
2595 if (set_b_signed)
2596 parameters["\\B_SIGNED"] = true;
2597 else if (parameters.count("\\B_SIGNED") == 0)
2598 parameters["\\B_SIGNED"] = false;
2599 }
2600 parameters["\\B_WIDTH"] = GetSize(connections_["\\B"]);
2601 }
2602
2603 if (connections_.count("\\Y"))
2604 parameters["\\Y_WIDTH"] = GetSize(connections_["\\Y"]);
2605
2606 if (connections_.count("\\Q"))
2607 parameters["\\WIDTH"] = GetSize(connections_["\\Q"]);
2608
2609 check();
2610 }
2611
2612 RTLIL::SigChunk::SigChunk()
2613 {
2614 wire = NULL;
2615 width = 0;
2616 offset = 0;
2617 }
2618
2619 RTLIL::SigChunk::SigChunk(const RTLIL::Const &value)
2620 {
2621 wire = NULL;
2622 data = value.bits;
2623 width = GetSize(data);
2624 offset = 0;
2625 }
2626
2627 RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire)
2628 {
2629 log_assert(wire != nullptr);
2630 this->wire = wire;
2631 this->width = wire->width;
2632 this->offset = 0;
2633 }
2634
2635 RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire, int offset, int width)
2636 {
2637 log_assert(wire != nullptr);
2638 this->wire = wire;
2639 this->width = width;
2640 this->offset = offset;
2641 }
2642
2643 RTLIL::SigChunk::SigChunk(const std::string &str)
2644 {
2645 wire = NULL;
2646 data = RTLIL::Const(str).bits;
2647 width = GetSize(data);
2648 offset = 0;
2649 }
2650
2651 RTLIL::SigChunk::SigChunk(int val, int width)
2652 {
2653 wire = NULL;
2654 data = RTLIL::Const(val, width).bits;
2655 this->width = GetSize(data);
2656 offset = 0;
2657 }
2658
2659 RTLIL::SigChunk::SigChunk(RTLIL::State bit, int width)
2660 {
2661 wire = NULL;
2662 data = RTLIL::Const(bit, width).bits;
2663 this->width = GetSize(data);
2664 offset = 0;
2665 }
2666
2667 RTLIL::SigChunk::SigChunk(RTLIL::SigBit bit)
2668 {
2669 wire = bit.wire;
2670 offset = 0;
2671 if (wire == NULL)
2672 data = RTLIL::Const(bit.data).bits;
2673 else
2674 offset = bit.offset;
2675 width = 1;
2676 }
2677
2678 RTLIL::SigChunk::SigChunk(const RTLIL::SigChunk &sigchunk) : data(sigchunk.data)
2679 {
2680 wire = sigchunk.wire;
2681 data = sigchunk.data;
2682 width = sigchunk.width;
2683 offset = sigchunk.offset;
2684 }
2685
2686 RTLIL::SigChunk RTLIL::SigChunk::extract(int offset, int length) const
2687 {
2688 RTLIL::SigChunk ret;
2689 if (wire) {
2690 ret.wire = wire;
2691 ret.offset = this->offset + offset;
2692 ret.width = length;
2693 } else {
2694 for (int i = 0; i < length; i++)
2695 ret.data.push_back(data[offset+i]);
2696 ret.width = length;
2697 }
2698 return ret;
2699 }
2700
2701 bool RTLIL::SigChunk::operator <(const RTLIL::SigChunk &other) const
2702 {
2703 if (wire && other.wire)
2704 if (wire->name != other.wire->name)
2705 return wire->name < other.wire->name;
2706
2707 if (wire != other.wire)
2708 return wire < other.wire;
2709
2710 if (offset != other.offset)
2711 return offset < other.offset;
2712
2713 if (width != other.width)
2714 return width < other.width;
2715
2716 return data < other.data;
2717 }
2718
2719 bool RTLIL::SigChunk::operator ==(const RTLIL::SigChunk &other) const
2720 {
2721 return wire == other.wire && width == other.width && offset == other.offset && data == other.data;
2722 }
2723
2724 bool RTLIL::SigChunk::operator !=(const RTLIL::SigChunk &other) const
2725 {
2726 if (*this == other)
2727 return false;
2728 return true;
2729 }
2730
2731 RTLIL::SigSpec::SigSpec()
2732 {
2733 width_ = 0;
2734 hash_ = 0;
2735 }
2736
2737 RTLIL::SigSpec::SigSpec(const RTLIL::SigSpec &other)
2738 {
2739 *this = other;
2740 }
2741
2742 RTLIL::SigSpec::SigSpec(std::initializer_list<RTLIL::SigSpec> parts)
2743 {
2744 cover("kernel.rtlil.sigspec.init.list");
2745
2746 width_ = 0;
2747 hash_ = 0;
2748
2749 std::vector<RTLIL::SigSpec> parts_vec(parts.begin(), parts.end());
2750 for (auto it = parts_vec.rbegin(); it != parts_vec.rend(); it++)
2751 append(*it);
2752 }
2753
2754 const RTLIL::SigSpec &RTLIL::SigSpec::operator=(const RTLIL::SigSpec &other)
2755 {
2756 cover("kernel.rtlil.sigspec.assign");
2757
2758 width_ = other.width_;
2759 hash_ = other.hash_;
2760 chunks_ = other.chunks_;
2761 bits_.clear();
2762
2763 if (!other.bits_.empty())
2764 {
2765 RTLIL::SigChunk *last = NULL;
2766 int last_end_offset = 0;
2767
2768 for (auto &bit : other.bits_) {
2769 if (last && bit.wire == last->wire) {
2770 if (bit.wire == NULL) {
2771 last->data.push_back(bit.data);
2772 last->width++;
2773 continue;
2774 } else if (last_end_offset == bit.offset) {
2775 last_end_offset++;
2776 last->width++;
2777 continue;
2778 }
2779 }
2780 chunks_.push_back(bit);
2781 last = &chunks_.back();
2782 last_end_offset = bit.offset + 1;
2783 }
2784
2785 check();
2786 }
2787
2788 return *this;
2789 }
2790
2791 RTLIL::SigSpec::SigSpec(const RTLIL::Const &value)
2792 {
2793 cover("kernel.rtlil.sigspec.init.const");
2794
2795 chunks_.push_back(RTLIL::SigChunk(value));
2796 width_ = chunks_.back().width;
2797 hash_ = 0;
2798 check();
2799 }
2800
2801 RTLIL::SigSpec::SigSpec(const RTLIL::SigChunk &chunk)
2802 {
2803 cover("kernel.rtlil.sigspec.init.chunk");
2804
2805 chunks_.push_back(chunk);
2806 width_ = chunks_.back().width;
2807 hash_ = 0;
2808 check();
2809 }
2810
2811 RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire)
2812 {
2813 cover("kernel.rtlil.sigspec.init.wire");
2814
2815 chunks_.push_back(RTLIL::SigChunk(wire));
2816 width_ = chunks_.back().width;
2817 hash_ = 0;
2818 check();
2819 }
2820
2821 RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire, int offset, int width)
2822 {
2823 cover("kernel.rtlil.sigspec.init.wire_part");
2824
2825 chunks_.push_back(RTLIL::SigChunk(wire, offset, width));
2826 width_ = chunks_.back().width;
2827 hash_ = 0;
2828 check();
2829 }
2830
2831 RTLIL::SigSpec::SigSpec(const std::string &str)
2832 {
2833 cover("kernel.rtlil.sigspec.init.str");
2834
2835 chunks_.push_back(RTLIL::SigChunk(str));
2836 width_ = chunks_.back().width;
2837 hash_ = 0;
2838 check();
2839 }
2840
2841 RTLIL::SigSpec::SigSpec(int val, int width)
2842 {
2843 cover("kernel.rtlil.sigspec.init.int");
2844
2845 chunks_.push_back(RTLIL::SigChunk(val, width));
2846 width_ = width;
2847 hash_ = 0;
2848 check();
2849 }
2850
2851 RTLIL::SigSpec::SigSpec(RTLIL::State bit, int width)
2852 {
2853 cover("kernel.rtlil.sigspec.init.state");
2854
2855 chunks_.push_back(RTLIL::SigChunk(bit, width));
2856 width_ = width;
2857 hash_ = 0;
2858 check();
2859 }
2860
2861 RTLIL::SigSpec::SigSpec(RTLIL::SigBit bit, int width)
2862 {
2863 cover("kernel.rtlil.sigspec.init.bit");
2864
2865 if (bit.wire == NULL)
2866 chunks_.push_back(RTLIL::SigChunk(bit.data, width));
2867 else
2868 for (int i = 0; i < width; i++)
2869 chunks_.push_back(bit);
2870 width_ = width;
2871 hash_ = 0;
2872 check();
2873 }
2874
2875 RTLIL::SigSpec::SigSpec(std::vector<RTLIL::SigChunk> chunks)
2876 {
2877 cover("kernel.rtlil.sigspec.init.stdvec_chunks");
2878
2879 width_ = 0;
2880 hash_ = 0;
2881 for (auto &c : chunks)
2882 append(c);
2883 check();
2884 }
2885
2886 RTLIL::SigSpec::SigSpec(std::vector<RTLIL::SigBit> bits)
2887 {
2888 cover("kernel.rtlil.sigspec.init.stdvec_bits");
2889
2890 width_ = 0;
2891 hash_ = 0;
2892 for (auto &bit : bits)
2893 append_bit(bit);
2894 check();
2895 }
2896
2897 RTLIL::SigSpec::SigSpec(pool<RTLIL::SigBit> bits)
2898 {
2899 cover("kernel.rtlil.sigspec.init.pool_bits");
2900
2901 width_ = 0;
2902 hash_ = 0;
2903 for (auto &bit : bits)
2904 append_bit(bit);
2905 check();
2906 }
2907
2908 RTLIL::SigSpec::SigSpec(std::set<RTLIL::SigBit> bits)
2909 {
2910 cover("kernel.rtlil.sigspec.init.stdset_bits");
2911
2912 width_ = 0;
2913 hash_ = 0;
2914 for (auto &bit : bits)
2915 append_bit(bit);
2916 check();
2917 }
2918
2919 RTLIL::SigSpec::SigSpec(bool bit)
2920 {
2921 cover("kernel.rtlil.sigspec.init.bool");
2922
2923 width_ = 0;
2924 hash_ = 0;
2925 append_bit(bit);
2926 check();
2927 }
2928
2929 void RTLIL::SigSpec::pack() const
2930 {
2931 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
2932
2933 if (that->bits_.empty())
2934 return;
2935
2936 cover("kernel.rtlil.sigspec.convert.pack");
2937 log_assert(that->chunks_.empty());
2938
2939 std::vector<RTLIL::SigBit> old_bits;
2940 old_bits.swap(that->bits_);
2941
2942 RTLIL::SigChunk *last = NULL;
2943 int last_end_offset = 0;
2944
2945 for (auto &bit : old_bits) {
2946 if (last && bit.wire == last->wire) {
2947 if (bit.wire == NULL) {
2948 last->data.push_back(bit.data);
2949 last->width++;
2950 continue;
2951 } else if (last_end_offset == bit.offset) {
2952 last_end_offset++;
2953 last->width++;
2954 continue;
2955 }
2956 }
2957 that->chunks_.push_back(bit);
2958 last = &that->chunks_.back();
2959 last_end_offset = bit.offset + 1;
2960 }
2961
2962 check();
2963 }
2964
2965 void RTLIL::SigSpec::unpack() const
2966 {
2967 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
2968
2969 if (that->chunks_.empty())
2970 return;
2971
2972 cover("kernel.rtlil.sigspec.convert.unpack");
2973 log_assert(that->bits_.empty());
2974
2975 that->bits_.reserve(that->width_);
2976 for (auto &c : that->chunks_)
2977 for (int i = 0; i < c.width; i++)
2978 that->bits_.push_back(RTLIL::SigBit(c, i));
2979
2980 that->chunks_.clear();
2981 that->hash_ = 0;
2982 }
2983
2984 void RTLIL::SigSpec::updhash() const
2985 {
2986 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
2987
2988 if (that->hash_ != 0)
2989 return;
2990
2991 cover("kernel.rtlil.sigspec.hash");
2992 that->pack();
2993
2994 that->hash_ = mkhash_init;
2995 for (auto &c : that->chunks_)
2996 if (c.wire == NULL) {
2997 for (auto &v : c.data)
2998 that->hash_ = mkhash(that->hash_, v);
2999 } else {
3000 that->hash_ = mkhash(that->hash_, c.wire->name.index_);
3001 that->hash_ = mkhash(that->hash_, c.offset);
3002 that->hash_ = mkhash(that->hash_, c.width);
3003 }
3004
3005 if (that->hash_ == 0)
3006 that->hash_ = 1;
3007 }
3008
3009 void RTLIL::SigSpec::sort()
3010 {
3011 unpack();
3012 cover("kernel.rtlil.sigspec.sort");
3013 std::sort(bits_.begin(), bits_.end());
3014 }
3015
3016 void RTLIL::SigSpec::sort_and_unify()
3017 {
3018 unpack();
3019 cover("kernel.rtlil.sigspec.sort_and_unify");
3020
3021 // A copy of the bits vector is used to prevent duplicating the logic from
3022 // SigSpec::SigSpec(std::vector<SigBit>). This incurrs an extra copy but
3023 // that isn't showing up as significant in profiles.
3024 std::vector<SigBit> unique_bits = bits_;
3025 std::sort(unique_bits.begin(), unique_bits.end());
3026 auto last = std::unique(unique_bits.begin(), unique_bits.end());
3027 unique_bits.erase(last, unique_bits.end());
3028
3029 *this = unique_bits;
3030 }
3031
3032 void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with)
3033 {
3034 replace(pattern, with, this);
3035 }
3036
3037 void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with, RTLIL::SigSpec *other) const
3038 {
3039 log_assert(other != NULL);
3040 log_assert(width_ == other->width_);
3041 log_assert(pattern.width_ == with.width_);
3042
3043 pattern.unpack();
3044 with.unpack();
3045 unpack();
3046 other->unpack();
3047
3048 for (int i = 0; i < GetSize(pattern.bits_); i++) {
3049 if (pattern.bits_[i].wire != NULL) {
3050 for (int j = 0; j < GetSize(bits_); j++) {
3051 if (bits_[j] == pattern.bits_[i]) {
3052 other->bits_[j] = with.bits_[i];
3053 }
3054 }
3055 }
3056 }
3057
3058 other->check();
3059 }
3060
3061 void RTLIL::SigSpec::replace(const dict<RTLIL::SigBit, RTLIL::SigBit> &rules)
3062 {
3063 replace(rules, this);
3064 }
3065
3066 void RTLIL::SigSpec::replace(const dict<RTLIL::SigBit, RTLIL::SigBit> &rules, RTLIL::SigSpec *other) const
3067 {
3068 cover("kernel.rtlil.sigspec.replace_dict");
3069
3070 log_assert(other != NULL);
3071 log_assert(width_ == other->width_);
3072
3073 unpack();
3074 other->unpack();
3075
3076 for (int i = 0; i < GetSize(bits_); i++) {
3077 auto it = rules.find(bits_[i]);
3078 if (it != rules.end())
3079 other->bits_[i] = it->second;
3080 }
3081
3082 other->check();
3083 }
3084
3085 void RTLIL::SigSpec::replace(const std::map<RTLIL::SigBit, RTLIL::SigBit> &rules)
3086 {
3087 replace(rules, this);
3088 }
3089
3090 void RTLIL::SigSpec::replace(const std::map<RTLIL::SigBit, RTLIL::SigBit> &rules, RTLIL::SigSpec *other) const
3091 {
3092 cover("kernel.rtlil.sigspec.replace_map");
3093
3094 log_assert(other != NULL);
3095 log_assert(width_ == other->width_);
3096
3097 unpack();
3098 other->unpack();
3099
3100 for (int i = 0; i < GetSize(bits_); i++) {
3101 auto it = rules.find(bits_[i]);
3102 if (it != rules.end())
3103 other->bits_[i] = it->second;
3104 }
3105
3106 other->check();
3107 }
3108
3109 void RTLIL::SigSpec::remove(const RTLIL::SigSpec &pattern)
3110 {
3111 remove2(pattern, NULL);
3112 }
3113
3114 void RTLIL::SigSpec::remove(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other) const
3115 {
3116 RTLIL::SigSpec tmp = *this;
3117 tmp.remove2(pattern, other);
3118 }
3119
3120 void RTLIL::SigSpec::remove2(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other)
3121 {
3122 if (other)
3123 cover("kernel.rtlil.sigspec.remove_other");
3124 else
3125 cover("kernel.rtlil.sigspec.remove");
3126
3127 unpack();
3128 if (other != NULL) {
3129 log_assert(width_ == other->width_);
3130 other->unpack();
3131 }
3132
3133 for (int i = GetSize(bits_) - 1; i >= 0; i--)
3134 {
3135 if (bits_[i].wire == NULL) continue;
3136
3137 for (auto &pattern_chunk : pattern.chunks())
3138 if (bits_[i].wire == pattern_chunk.wire &&
3139 bits_[i].offset >= pattern_chunk.offset &&
3140 bits_[i].offset < pattern_chunk.offset + pattern_chunk.width) {
3141 bits_.erase(bits_.begin() + i);
3142 width_--;
3143 if (other != NULL) {
3144 other->bits_.erase(other->bits_.begin() + i);
3145 other->width_--;
3146 }
3147 break;
3148 }
3149 }
3150
3151 check();
3152 }
3153
3154 void RTLIL::SigSpec::remove(const pool<RTLIL::SigBit> &pattern)
3155 {
3156 remove2(pattern, NULL);
3157 }
3158
3159 void RTLIL::SigSpec::remove(const pool<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other) const
3160 {
3161 RTLIL::SigSpec tmp = *this;
3162 tmp.remove2(pattern, other);
3163 }
3164
3165 void RTLIL::SigSpec::remove2(const pool<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other)
3166 {
3167 if (other)
3168 cover("kernel.rtlil.sigspec.remove_other");
3169 else
3170 cover("kernel.rtlil.sigspec.remove");
3171
3172 unpack();
3173
3174 if (other != NULL) {
3175 log_assert(width_ == other->width_);
3176 other->unpack();
3177 }
3178
3179 for (int i = GetSize(bits_) - 1; i >= 0; i--) {
3180 if (bits_[i].wire != NULL && pattern.count(bits_[i])) {
3181 bits_.erase(bits_.begin() + i);
3182 width_--;
3183 if (other != NULL) {
3184 other->bits_.erase(other->bits_.begin() + i);
3185 other->width_--;
3186 }
3187 }
3188 }
3189
3190 check();
3191 }
3192
3193 void RTLIL::SigSpec::remove2(const std::set<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other)
3194 {
3195 if (other)
3196 cover("kernel.rtlil.sigspec.remove_other");
3197 else
3198 cover("kernel.rtlil.sigspec.remove");
3199
3200 unpack();
3201
3202 if (other != NULL) {
3203 log_assert(width_ == other->width_);
3204 other->unpack();
3205 }
3206
3207 for (int i = GetSize(bits_) - 1; i >= 0; i--) {
3208 if (bits_[i].wire != NULL && pattern.count(bits_[i])) {
3209 bits_.erase(bits_.begin() + i);
3210 width_--;
3211 if (other != NULL) {
3212 other->bits_.erase(other->bits_.begin() + i);
3213 other->width_--;
3214 }
3215 }
3216 }
3217
3218 check();
3219 }
3220
3221 RTLIL::SigSpec RTLIL::SigSpec::extract(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec *other) const
3222 {
3223 if (other)
3224 cover("kernel.rtlil.sigspec.extract_other");
3225 else
3226 cover("kernel.rtlil.sigspec.extract");
3227
3228 log_assert(other == NULL || width_ == other->width_);
3229
3230 RTLIL::SigSpec ret;
3231 std::vector<RTLIL::SigBit> bits_match = to_sigbit_vector();
3232
3233 for (auto& pattern_chunk : pattern.chunks()) {
3234 if (other) {
3235 std::vector<RTLIL::SigBit> bits_other = other->to_sigbit_vector();
3236 for (int i = 0; i < width_; i++)
3237 if (bits_match[i].wire &&
3238 bits_match[i].wire == pattern_chunk.wire &&
3239 bits_match[i].offset >= pattern_chunk.offset &&
3240 bits_match[i].offset < pattern_chunk.offset + pattern_chunk.width)
3241 ret.append_bit(bits_other[i]);
3242 } else {
3243 for (int i = 0; i < width_; i++)
3244 if (bits_match[i].wire &&
3245 bits_match[i].wire == pattern_chunk.wire &&
3246 bits_match[i].offset >= pattern_chunk.offset &&
3247 bits_match[i].offset < pattern_chunk.offset + pattern_chunk.width)
3248 ret.append_bit(bits_match[i]);
3249 }
3250 }
3251
3252 ret.check();
3253 return ret;
3254 }
3255
3256 RTLIL::SigSpec RTLIL::SigSpec::extract(const pool<RTLIL::SigBit> &pattern, const RTLIL::SigSpec *other) const
3257 {
3258 if (other)
3259 cover("kernel.rtlil.sigspec.extract_other");
3260 else
3261 cover("kernel.rtlil.sigspec.extract");
3262
3263 log_assert(other == NULL || width_ == other->width_);
3264
3265 std::vector<RTLIL::SigBit> bits_match = to_sigbit_vector();
3266 RTLIL::SigSpec ret;
3267
3268 if (other) {
3269 std::vector<RTLIL::SigBit> bits_other = other->to_sigbit_vector();
3270 for (int i = 0; i < width_; i++)
3271 if (bits_match[i].wire && pattern.count(bits_match[i]))
3272 ret.append_bit(bits_other[i]);
3273 } else {
3274 for (int i = 0; i < width_; i++)
3275 if (bits_match[i].wire && pattern.count(bits_match[i]))
3276 ret.append_bit(bits_match[i]);
3277 }
3278
3279 ret.check();
3280 return ret;
3281 }
3282
3283 void RTLIL::SigSpec::replace(int offset, const RTLIL::SigSpec &with)
3284 {
3285 cover("kernel.rtlil.sigspec.replace_pos");
3286
3287 unpack();
3288 with.unpack();
3289
3290 log_assert(offset >= 0);
3291 log_assert(with.width_ >= 0);
3292 log_assert(offset+with.width_ <= width_);
3293
3294 for (int i = 0; i < with.width_; i++)
3295 bits_.at(offset + i) = with.bits_.at(i);
3296
3297 check();
3298 }
3299
3300 void RTLIL::SigSpec::remove_const()
3301 {
3302 if (packed())
3303 {
3304 cover("kernel.rtlil.sigspec.remove_const.packed");
3305
3306 std::vector<RTLIL::SigChunk> new_chunks;
3307 new_chunks.reserve(GetSize(chunks_));
3308
3309 width_ = 0;
3310 for (auto &chunk : chunks_)
3311 if (chunk.wire != NULL) {
3312 new_chunks.push_back(chunk);
3313 width_ += chunk.width;
3314 }
3315
3316 chunks_.swap(new_chunks);
3317 }
3318 else
3319 {
3320 cover("kernel.rtlil.sigspec.remove_const.unpacked");
3321
3322 std::vector<RTLIL::SigBit> new_bits;
3323 new_bits.reserve(width_);
3324
3325 for (auto &bit : bits_)
3326 if (bit.wire != NULL)
3327 new_bits.push_back(bit);
3328
3329 bits_.swap(new_bits);
3330 width_ = bits_.size();
3331 }
3332
3333 check();
3334 }
3335
3336 void RTLIL::SigSpec::remove(int offset, int length)
3337 {
3338 cover("kernel.rtlil.sigspec.remove_pos");
3339
3340 unpack();
3341
3342 log_assert(offset >= 0);
3343 log_assert(length >= 0);
3344 log_assert(offset + length <= width_);
3345
3346 bits_.erase(bits_.begin() + offset, bits_.begin() + offset + length);
3347 width_ = bits_.size();
3348
3349 check();
3350 }
3351
3352 RTLIL::SigSpec RTLIL::SigSpec::extract(int offset, int length) const
3353 {
3354 unpack();
3355 cover("kernel.rtlil.sigspec.extract_pos");
3356 return std::vector<RTLIL::SigBit>(bits_.begin() + offset, bits_.begin() + offset + length);
3357 }
3358
3359 void RTLIL::SigSpec::append(const RTLIL::SigSpec &signal)
3360 {
3361 if (signal.width_ == 0)
3362 return;
3363
3364 if (width_ == 0) {
3365 *this = signal;
3366 return;
3367 }
3368
3369 cover("kernel.rtlil.sigspec.append");
3370
3371 if (packed() != signal.packed()) {
3372 pack();
3373 signal.pack();
3374 }
3375
3376 if (packed())
3377 for (auto &other_c : signal.chunks_)
3378 {
3379 auto &my_last_c = chunks_.back();
3380 if (my_last_c.wire == NULL && other_c.wire == NULL) {
3381 auto &this_data = my_last_c.data;
3382 auto &other_data = other_c.data;
3383 this_data.insert(this_data.end(), other_data.begin(), other_data.end());
3384 my_last_c.width += other_c.width;
3385 } else
3386 if (my_last_c.wire == other_c.wire && my_last_c.offset + my_last_c.width == other_c.offset) {
3387 my_last_c.width += other_c.width;
3388 } else
3389 chunks_.push_back(other_c);
3390 }
3391 else
3392 bits_.insert(bits_.end(), signal.bits_.begin(), signal.bits_.end());
3393
3394 width_ += signal.width_;
3395 check();
3396 }
3397
3398 void RTLIL::SigSpec::append_bit(const RTLIL::SigBit &bit)
3399 {
3400 if (packed())
3401 {
3402 cover("kernel.rtlil.sigspec.append_bit.packed");
3403
3404 if (chunks_.size() == 0)
3405 chunks_.push_back(bit);
3406 else
3407 if (bit.wire == NULL)
3408 if (chunks_.back().wire == NULL) {
3409 chunks_.back().data.push_back(bit.data);
3410 chunks_.back().width++;
3411 } else
3412 chunks_.push_back(bit);
3413 else
3414 if (chunks_.back().wire == bit.wire && chunks_.back().offset + chunks_.back().width == bit.offset)
3415 chunks_.back().width++;
3416 else
3417 chunks_.push_back(bit);
3418 }
3419 else
3420 {
3421 cover("kernel.rtlil.sigspec.append_bit.unpacked");
3422 bits_.push_back(bit);
3423 }
3424
3425 width_++;
3426 check();
3427 }
3428
3429 void RTLIL::SigSpec::extend_u0(int width, bool is_signed)
3430 {
3431 cover("kernel.rtlil.sigspec.extend_u0");
3432
3433 pack();
3434
3435 if (width_ > width)
3436 remove(width, width_ - width);
3437
3438 if (width_ < width) {
3439 RTLIL::SigBit padding = width_ > 0 ? (*this)[width_ - 1] : RTLIL::State::Sx;
3440 if (!is_signed)
3441 padding = RTLIL::State::S0;
3442 while (width_ < width)
3443 append(padding);
3444 }
3445
3446 }
3447
3448 RTLIL::SigSpec RTLIL::SigSpec::repeat(int num) const
3449 {
3450 cover("kernel.rtlil.sigspec.repeat");
3451
3452 RTLIL::SigSpec sig;
3453 for (int i = 0; i < num; i++)
3454 sig.append(*this);
3455 return sig;
3456 }
3457
3458 #ifndef NDEBUG
3459 void RTLIL::SigSpec::check() const
3460 {
3461 if (width_ > 64)
3462 {
3463 cover("kernel.rtlil.sigspec.check.skip");
3464 }
3465 else if (packed())
3466 {
3467 cover("kernel.rtlil.sigspec.check.packed");
3468
3469 int w = 0;
3470 for (size_t i = 0; i < chunks_.size(); i++) {
3471 const RTLIL::SigChunk chunk = chunks_[i];
3472 if (chunk.wire == NULL) {
3473 if (i > 0)
3474 log_assert(chunks_[i-1].wire != NULL);
3475 log_assert(chunk.offset == 0);
3476 log_assert(chunk.data.size() == (size_t)chunk.width);
3477 } else {
3478 if (i > 0 && chunks_[i-1].wire == chunk.wire)
3479 log_assert(chunk.offset != chunks_[i-1].offset + chunks_[i-1].width);
3480 log_assert(chunk.offset >= 0);
3481 log_assert(chunk.width >= 0);
3482 log_assert(chunk.offset + chunk.width <= chunk.wire->width);
3483 log_assert(chunk.data.size() == 0);
3484 }
3485 w += chunk.width;
3486 }
3487 log_assert(w == width_);
3488 log_assert(bits_.empty());
3489 }
3490 else
3491 {
3492 cover("kernel.rtlil.sigspec.check.unpacked");
3493
3494 log_assert(width_ == GetSize(bits_));
3495 log_assert(chunks_.empty());
3496 }
3497 }
3498 #endif
3499
3500 bool RTLIL::SigSpec::operator <(const RTLIL::SigSpec &other) const
3501 {
3502 cover("kernel.rtlil.sigspec.comp_lt");
3503
3504 if (this == &other)
3505 return false;
3506
3507 if (width_ != other.width_)
3508 return width_ < other.width_;
3509
3510 pack();
3511 other.pack();
3512
3513 if (chunks_.size() != other.chunks_.size())
3514 return chunks_.size() < other.chunks_.size();
3515
3516 updhash();
3517 other.updhash();
3518
3519 if (hash_ != other.hash_)
3520 return hash_ < other.hash_;
3521
3522 for (size_t i = 0; i < chunks_.size(); i++)
3523 if (chunks_[i] != other.chunks_[i]) {
3524 cover("kernel.rtlil.sigspec.comp_lt.hash_collision");
3525 return chunks_[i] < other.chunks_[i];
3526 }
3527
3528 cover("kernel.rtlil.sigspec.comp_lt.equal");
3529 return false;
3530 }
3531
3532 bool RTLIL::SigSpec::operator ==(const RTLIL::SigSpec &other) const
3533 {
3534 cover("kernel.rtlil.sigspec.comp_eq");
3535
3536 if (this == &other)
3537 return true;
3538
3539 if (width_ != other.width_)
3540 return false;
3541
3542 pack();
3543 other.pack();
3544
3545 if (chunks_.size() != other.chunks_.size())
3546 return false;
3547
3548 updhash();
3549 other.updhash();
3550
3551 if (hash_ != other.hash_)
3552 return false;
3553
3554 for (size_t i = 0; i < chunks_.size(); i++)
3555 if (chunks_[i] != other.chunks_[i]) {
3556 cover("kernel.rtlil.sigspec.comp_eq.hash_collision");
3557 return false;
3558 }
3559
3560 cover("kernel.rtlil.sigspec.comp_eq.equal");
3561 return true;
3562 }
3563
3564 bool RTLIL::SigSpec::is_wire() const
3565 {
3566 cover("kernel.rtlil.sigspec.is_wire");
3567
3568 pack();
3569 return GetSize(chunks_) == 1 && chunks_[0].wire && chunks_[0].wire->width == width_;
3570 }
3571
3572 bool RTLIL::SigSpec::is_chunk() const
3573 {
3574 cover("kernel.rtlil.sigspec.is_chunk");
3575
3576 pack();
3577 return GetSize(chunks_) == 1;
3578 }
3579
3580 bool RTLIL::SigSpec::is_fully_const() const
3581 {
3582 cover("kernel.rtlil.sigspec.is_fully_const");
3583
3584 pack();
3585 for (auto it = chunks_.begin(); it != chunks_.end(); it++)
3586 if (it->width > 0 && it->wire != NULL)
3587 return false;
3588 return true;
3589 }
3590
3591 bool RTLIL::SigSpec::is_fully_zero() const
3592 {
3593 cover("kernel.rtlil.sigspec.is_fully_zero");
3594
3595 pack();
3596 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
3597 if (it->width > 0 && it->wire != NULL)
3598 return false;
3599 for (size_t i = 0; i < it->data.size(); i++)
3600 if (it->data[i] != RTLIL::State::S0)
3601 return false;
3602 }
3603 return true;
3604 }
3605
3606 bool RTLIL::SigSpec::is_fully_ones() const
3607 {
3608 cover("kernel.rtlil.sigspec.is_fully_ones");
3609
3610 pack();
3611 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
3612 if (it->width > 0 && it->wire != NULL)
3613 return false;
3614 for (size_t i = 0; i < it->data.size(); i++)
3615 if (it->data[i] != RTLIL::State::S1)
3616 return false;
3617 }
3618 return true;
3619 }
3620
3621 bool RTLIL::SigSpec::is_fully_def() const
3622 {
3623 cover("kernel.rtlil.sigspec.is_fully_def");
3624
3625 pack();
3626 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
3627 if (it->width > 0 && it->wire != NULL)
3628 return false;
3629 for (size_t i = 0; i < it->data.size(); i++)
3630 if (it->data[i] != RTLIL::State::S0 && it->data[i] != RTLIL::State::S1)
3631 return false;
3632 }
3633 return true;
3634 }
3635
3636 bool RTLIL::SigSpec::is_fully_undef() const
3637 {
3638 cover("kernel.rtlil.sigspec.is_fully_undef");
3639
3640 pack();
3641 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
3642 if (it->width > 0 && it->wire != NULL)
3643 return false;
3644 for (size_t i = 0; i < it->data.size(); i++)
3645 if (it->data[i] != RTLIL::State::Sx && it->data[i] != RTLIL::State::Sz)
3646 return false;
3647 }
3648 return true;
3649 }
3650
3651 bool RTLIL::SigSpec::has_const() const
3652 {
3653 cover("kernel.rtlil.sigspec.has_const");
3654
3655 pack();
3656 for (auto it = chunks_.begin(); it != chunks_.end(); it++)
3657 if (it->width > 0 && it->wire == NULL)
3658 return true;
3659 return false;
3660 }
3661
3662 bool RTLIL::SigSpec::has_marked_bits() const
3663 {
3664 cover("kernel.rtlil.sigspec.has_marked_bits");
3665
3666 pack();
3667 for (auto it = chunks_.begin(); it != chunks_.end(); it++)
3668 if (it->width > 0 && it->wire == NULL) {
3669 for (size_t i = 0; i < it->data.size(); i++)
3670 if (it->data[i] == RTLIL::State::Sm)
3671 return true;
3672 }
3673 return false;
3674 }
3675
3676 bool RTLIL::SigSpec::as_bool() const
3677 {
3678 cover("kernel.rtlil.sigspec.as_bool");
3679
3680 pack();
3681 log_assert(is_fully_const() && GetSize(chunks_) <= 1);
3682 if (width_)
3683 return RTLIL::Const(chunks_[0].data).as_bool();
3684 return false;
3685 }
3686
3687 int RTLIL::SigSpec::as_int(bool is_signed) const
3688 {
3689 cover("kernel.rtlil.sigspec.as_int");
3690
3691 pack();
3692 log_assert(is_fully_const() && GetSize(chunks_) <= 1);
3693 if (width_)
3694 return RTLIL::Const(chunks_[0].data).as_int(is_signed);
3695 return 0;
3696 }
3697
3698 std::string RTLIL::SigSpec::as_string() const
3699 {
3700 cover("kernel.rtlil.sigspec.as_string");
3701
3702 pack();
3703 std::string str;
3704 for (size_t i = chunks_.size(); i > 0; i--) {
3705 const RTLIL::SigChunk &chunk = chunks_[i-1];
3706 if (chunk.wire != NULL)
3707 for (int j = 0; j < chunk.width; j++)
3708 str += "?";
3709 else
3710 str += RTLIL::Const(chunk.data).as_string();
3711 }
3712 return str;
3713 }
3714
3715 RTLIL::Const RTLIL::SigSpec::as_const() const
3716 {
3717 cover("kernel.rtlil.sigspec.as_const");
3718
3719 pack();
3720 log_assert(is_fully_const() && GetSize(chunks_) <= 1);
3721 if (width_)
3722 return chunks_[0].data;
3723 return RTLIL::Const();
3724 }
3725
3726 RTLIL::Wire *RTLIL::SigSpec::as_wire() const
3727 {
3728 cover("kernel.rtlil.sigspec.as_wire");
3729
3730 pack();
3731 log_assert(is_wire());
3732 return chunks_[0].wire;
3733 }
3734
3735 RTLIL::SigChunk RTLIL::SigSpec::as_chunk() const
3736 {
3737 cover("kernel.rtlil.sigspec.as_chunk");
3738
3739 pack();
3740 log_assert(is_chunk());
3741 return chunks_[0];
3742 }
3743
3744 RTLIL::SigBit RTLIL::SigSpec::as_bit() const
3745 {
3746 cover("kernel.rtlil.sigspec.as_bit");
3747
3748 log_assert(width_ == 1);
3749 if (packed())
3750 return RTLIL::SigBit(*chunks_.begin());
3751 else
3752 return bits_[0];
3753 }
3754
3755 bool RTLIL::SigSpec::match(std::string pattern) const
3756 {
3757 cover("kernel.rtlil.sigspec.match");
3758
3759 pack();
3760 std::string str = as_string();
3761 log_assert(pattern.size() == str.size());
3762
3763 for (size_t i = 0; i < pattern.size(); i++) {
3764 if (pattern[i] == ' ')
3765 continue;
3766 if (pattern[i] == '*') {
3767 if (str[i] != 'z' && str[i] != 'x')
3768 return false;
3769 continue;
3770 }
3771 if (pattern[i] != str[i])
3772 return false;
3773 }
3774
3775 return true;
3776 }
3777
3778 std::set<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_set() const
3779 {
3780 cover("kernel.rtlil.sigspec.to_sigbit_set");
3781
3782 pack();
3783 std::set<RTLIL::SigBit> sigbits;
3784 for (auto &c : chunks_)
3785 for (int i = 0; i < c.width; i++)
3786 sigbits.insert(RTLIL::SigBit(c, i));
3787 return sigbits;
3788 }
3789
3790 pool<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_pool() const
3791 {
3792 cover("kernel.rtlil.sigspec.to_sigbit_pool");
3793
3794 pack();
3795 pool<RTLIL::SigBit> sigbits;
3796 for (auto &c : chunks_)
3797 for (int i = 0; i < c.width; i++)
3798 sigbits.insert(RTLIL::SigBit(c, i));
3799 return sigbits;
3800 }
3801
3802 std::vector<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_vector() const
3803 {
3804 cover("kernel.rtlil.sigspec.to_sigbit_vector");
3805
3806 unpack();
3807 return bits_;
3808 }
3809
3810 std::map<RTLIL::SigBit, RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_map(const RTLIL::SigSpec &other) const
3811 {
3812 cover("kernel.rtlil.sigspec.to_sigbit_map");
3813
3814 unpack();
3815 other.unpack();
3816
3817 log_assert(width_ == other.width_);
3818
3819 std::map<RTLIL::SigBit, RTLIL::SigBit> new_map;
3820 for (int i = 0; i < width_; i++)
3821 new_map[bits_[i]] = other.bits_[i];
3822
3823 return new_map;
3824 }
3825
3826 dict<RTLIL::SigBit, RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_dict(const RTLIL::SigSpec &other) const
3827 {
3828 cover("kernel.rtlil.sigspec.to_sigbit_dict");
3829
3830 unpack();
3831 other.unpack();
3832
3833 log_assert(width_ == other.width_);
3834
3835 dict<RTLIL::SigBit, RTLIL::SigBit> new_map;
3836 for (int i = 0; i < width_; i++)
3837 new_map[bits_[i]] = other.bits_[i];
3838
3839 return new_map;
3840 }
3841
3842 static void sigspec_parse_split(std::vector<std::string> &tokens, const std::string &text, char sep)
3843 {
3844 size_t start = 0, end = 0;
3845 while ((end = text.find(sep, start)) != std::string::npos) {
3846 tokens.push_back(text.substr(start, end - start));
3847 start = end + 1;
3848 }
3849 tokens.push_back(text.substr(start));
3850 }
3851
3852 static int sigspec_parse_get_dummy_line_num()
3853 {
3854 return 0;
3855 }
3856
3857 bool RTLIL::SigSpec::parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str)
3858 {
3859 cover("kernel.rtlil.sigspec.parse");
3860
3861 AST::current_filename = "input";
3862 AST::use_internal_line_num();
3863 AST::set_line_num(0);
3864
3865 std::vector<std::string> tokens;
3866 sigspec_parse_split(tokens, str, ',');
3867
3868 sig = RTLIL::SigSpec();
3869 for (int tokidx = int(tokens.size())-1; tokidx >= 0; tokidx--)
3870 {
3871 std::string netname = tokens[tokidx];
3872 std::string indices;
3873
3874 if (netname.size() == 0)
3875 continue;
3876
3877 if (('0' <= netname[0] && netname[0] <= '9') || netname[0] == '\'') {
3878 cover("kernel.rtlil.sigspec.parse.const");
3879 AST::get_line_num = sigspec_parse_get_dummy_line_num;
3880 AST::AstNode *ast = VERILOG_FRONTEND::const2ast(netname);
3881 if (ast == NULL)
3882 return false;
3883 sig.append(RTLIL::Const(ast->bits));
3884 delete ast;
3885 continue;
3886 }
3887
3888 if (module == NULL)
3889 return false;
3890
3891 cover("kernel.rtlil.sigspec.parse.net");
3892
3893 if (netname[0] != '$' && netname[0] != '\\')
3894 netname = "\\" + netname;
3895
3896 if (module->wires_.count(netname) == 0) {
3897 size_t indices_pos = netname.size()-1;
3898 if (indices_pos > 2 && netname[indices_pos] == ']')
3899 {
3900 indices_pos--;
3901 while (indices_pos > 0 && ('0' <= netname[indices_pos] && netname[indices_pos] <= '9')) indices_pos--;
3902 if (indices_pos > 0 && netname[indices_pos] == ':') {
3903 indices_pos--;
3904 while (indices_pos > 0 && ('0' <= netname[indices_pos] && netname[indices_pos] <= '9')) indices_pos--;
3905 }
3906 if (indices_pos > 0 && netname[indices_pos] == '[') {
3907 indices = netname.substr(indices_pos);
3908 netname = netname.substr(0, indices_pos);
3909 }
3910 }
3911 }
3912
3913 if (module->wires_.count(netname) == 0)
3914 return false;
3915
3916 RTLIL::Wire *wire = module->wires_.at(netname);
3917 if (!indices.empty()) {
3918 std::vector<std::string> index_tokens;
3919 sigspec_parse_split(index_tokens, indices.substr(1, indices.size()-2), ':');
3920 if (index_tokens.size() == 1) {
3921 cover("kernel.rtlil.sigspec.parse.bit_sel");
3922 int a = atoi(index_tokens.at(0).c_str());
3923 if (a < 0 || a >= wire->width)
3924 return false;
3925 sig.append(RTLIL::SigSpec(wire, a));
3926 } else {
3927 cover("kernel.rtlil.sigspec.parse.part_sel");
3928 int a = atoi(index_tokens.at(0).c_str());
3929 int b = atoi(index_tokens.at(1).c_str());
3930 if (a > b) {
3931 int tmp = a;
3932 a = b, b = tmp;
3933 }
3934 if (a < 0 || a >= wire->width)
3935 return false;
3936 if (b < 0 || b >= wire->width)
3937 return false;
3938 sig.append(RTLIL::SigSpec(wire, a, b-a+1));
3939 }
3940 } else
3941 sig.append(wire);
3942 }
3943
3944 return true;
3945 }
3946
3947 bool RTLIL::SigSpec::parse_sel(RTLIL::SigSpec &sig, RTLIL::Design *design, RTLIL::Module *module, std::string str)
3948 {
3949 if (str.empty() || str[0] != '@')
3950 return parse(sig, module, str);
3951
3952 cover("kernel.rtlil.sigspec.parse.sel");
3953
3954 str = RTLIL::escape_id(str.substr(1));
3955 if (design->selection_vars.count(str) == 0)
3956 return false;
3957
3958 sig = RTLIL::SigSpec();
3959 RTLIL::Selection &sel = design->selection_vars.at(str);
3960 for (auto &it : module->wires_)
3961 if (sel.selected_member(module->name, it.first))
3962 sig.append(it.second);
3963
3964 return true;
3965 }
3966
3967 bool RTLIL::SigSpec::parse_rhs(const RTLIL::SigSpec &lhs, RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str)
3968 {
3969 if (str == "0") {
3970 cover("kernel.rtlil.sigspec.parse.rhs_zeros");
3971 sig = RTLIL::SigSpec(RTLIL::State::S0, lhs.width_);
3972 return true;
3973 }
3974
3975 if (str == "~0") {
3976 cover("kernel.rtlil.sigspec.parse.rhs_ones");
3977 sig = RTLIL::SigSpec(RTLIL::State::S1, lhs.width_);
3978 return true;
3979 }
3980
3981 if (lhs.chunks_.size() == 1) {
3982 char *p = (char*)str.c_str(), *endptr;
3983 long int val = strtol(p, &endptr, 10);
3984 if (endptr && endptr != p && *endptr == 0) {
3985 sig = RTLIL::SigSpec(val, lhs.width_);
3986 cover("kernel.rtlil.sigspec.parse.rhs_dec");
3987 return true;
3988 }
3989 }
3990
3991 return parse(sig, module, str);
3992 }
3993
3994 RTLIL::CaseRule::~CaseRule()
3995 {
3996 for (auto it = switches.begin(); it != switches.end(); it++)
3997 delete *it;
3998 }
3999
4000 bool RTLIL::CaseRule::empty() const
4001 {
4002 return actions.empty() && switches.empty();
4003 }
4004
4005 RTLIL::CaseRule *RTLIL::CaseRule::clone() const
4006 {
4007 RTLIL::CaseRule *new_caserule = new RTLIL::CaseRule;
4008 new_caserule->compare = compare;
4009 new_caserule->actions = actions;
4010 for (auto &it : switches)
4011 new_caserule->switches.push_back(it->clone());
4012 return new_caserule;
4013 }
4014
4015 RTLIL::SwitchRule::~SwitchRule()
4016 {
4017 for (auto it = cases.begin(); it != cases.end(); it++)
4018 delete *it;
4019 }
4020
4021 bool RTLIL::SwitchRule::empty() const
4022 {
4023 return cases.empty();
4024 }
4025
4026 RTLIL::SwitchRule *RTLIL::SwitchRule::clone() const
4027 {
4028 RTLIL::SwitchRule *new_switchrule = new RTLIL::SwitchRule;
4029 new_switchrule->signal = signal;
4030 new_switchrule->attributes = attributes;
4031 for (auto &it : cases)
4032 new_switchrule->cases.push_back(it->clone());
4033 return new_switchrule;
4034
4035 }
4036
4037 RTLIL::SyncRule *RTLIL::SyncRule::clone() const
4038 {
4039 RTLIL::SyncRule *new_syncrule = new RTLIL::SyncRule;
4040 new_syncrule->type = type;
4041 new_syncrule->signal = signal;
4042 new_syncrule->actions = actions;
4043 return new_syncrule;
4044 }
4045
4046 RTLIL::Process::~Process()
4047 {
4048 for (auto it = syncs.begin(); it != syncs.end(); it++)
4049 delete *it;
4050 }
4051
4052 RTLIL::Process *RTLIL::Process::clone() const
4053 {
4054 RTLIL::Process *new_proc = new RTLIL::Process;
4055
4056 new_proc->name = name;
4057 new_proc->attributes = attributes;
4058
4059 RTLIL::CaseRule *rc_ptr = root_case.clone();
4060 new_proc->root_case = *rc_ptr;
4061 rc_ptr->switches.clear();
4062 delete rc_ptr;
4063
4064 for (auto &it : syncs)
4065 new_proc->syncs.push_back(it->clone());
4066
4067 return new_proc;
4068 }
4069
4070 #ifdef WITH_PYTHON
4071 RTLIL::Memory::~Memory()
4072 {
4073 RTLIL::Memory::get_all_memorys()->erase(hashidx_);
4074 }
4075 static std::map<unsigned int, RTLIL::Memory*> all_memorys;
4076 std::map<unsigned int, RTLIL::Memory*> *RTLIL::Memory::get_all_memorys(void)
4077 {
4078 return &all_memorys;
4079 }
4080 #endif
4081 YOSYS_NAMESPACE_END