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Merge pull request #576 from cr1901/no-resource
[yosys.git] / kernel / rtlil.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 #include "kernel/yosys.h"
21 #include "kernel/macc.h"
22 #include "kernel/celltypes.h"
23 #include "frontends/verilog/verilog_frontend.h"
24 #include "backends/ilang/ilang_backend.h"
25
26 #include <string.h>
27 #include <algorithm>
28
29 YOSYS_NAMESPACE_BEGIN
30
31 RTLIL::IdString::destruct_guard_t RTLIL::IdString::destruct_guard;
32 std::vector<int> RTLIL::IdString::global_refcount_storage_;
33 std::vector<char*> RTLIL::IdString::global_id_storage_;
34 dict<char*, int, hash_cstr_ops> RTLIL::IdString::global_id_index_;
35 std::vector<int> RTLIL::IdString::global_free_idx_list_;
36
37 RTLIL::Const::Const()
38 {
39 flags = RTLIL::CONST_FLAG_NONE;
40 }
41
42 RTLIL::Const::Const(std::string str)
43 {
44 flags = RTLIL::CONST_FLAG_STRING;
45 for (int i = str.size()-1; i >= 0; i--) {
46 unsigned char ch = str[i];
47 for (int j = 0; j < 8; j++) {
48 bits.push_back((ch & 1) != 0 ? RTLIL::S1 : RTLIL::S0);
49 ch = ch >> 1;
50 }
51 }
52 }
53
54 RTLIL::Const::Const(int val, int width)
55 {
56 flags = RTLIL::CONST_FLAG_NONE;
57 for (int i = 0; i < width; i++) {
58 bits.push_back((val & 1) != 0 ? RTLIL::S1 : RTLIL::S0);
59 val = val >> 1;
60 }
61 }
62
63 RTLIL::Const::Const(RTLIL::State bit, int width)
64 {
65 flags = RTLIL::CONST_FLAG_NONE;
66 for (int i = 0; i < width; i++)
67 bits.push_back(bit);
68 }
69
70 RTLIL::Const::Const(const std::vector<bool> &bits)
71 {
72 flags = RTLIL::CONST_FLAG_NONE;
73 for (auto b : bits)
74 this->bits.push_back(b ? RTLIL::S1 : RTLIL::S0);
75 }
76
77 bool RTLIL::Const::operator <(const RTLIL::Const &other) const
78 {
79 if (bits.size() != other.bits.size())
80 return bits.size() < other.bits.size();
81 for (size_t i = 0; i < bits.size(); i++)
82 if (bits[i] != other.bits[i])
83 return bits[i] < other.bits[i];
84 return false;
85 }
86
87 bool RTLIL::Const::operator ==(const RTLIL::Const &other) const
88 {
89 return bits == other.bits;
90 }
91
92 bool RTLIL::Const::operator !=(const RTLIL::Const &other) const
93 {
94 return bits != other.bits;
95 }
96
97 bool RTLIL::Const::as_bool() const
98 {
99 for (size_t i = 0; i < bits.size(); i++)
100 if (bits[i] == RTLIL::S1)
101 return true;
102 return false;
103 }
104
105 int RTLIL::Const::as_int(bool is_signed) const
106 {
107 int32_t ret = 0;
108 for (size_t i = 0; i < bits.size() && i < 32; i++)
109 if (bits[i] == RTLIL::S1)
110 ret |= 1 << i;
111 if (is_signed && bits.back() == RTLIL::S1)
112 for (size_t i = bits.size(); i < 32; i++)
113 ret |= 1 << i;
114 return ret;
115 }
116
117 std::string RTLIL::Const::as_string() const
118 {
119 std::string ret;
120 for (size_t i = bits.size(); i > 0; i--)
121 switch (bits[i-1]) {
122 case S0: ret += "0"; break;
123 case S1: ret += "1"; break;
124 case Sx: ret += "x"; break;
125 case Sz: ret += "z"; break;
126 case Sa: ret += "-"; break;
127 case Sm: ret += "m"; break;
128 }
129 return ret;
130 }
131
132 RTLIL::Const RTLIL::Const::from_string(std::string str)
133 {
134 Const c;
135 for (auto it = str.rbegin(); it != str.rend(); it++)
136 switch (*it) {
137 case '0': c.bits.push_back(State::S0); break;
138 case '1': c.bits.push_back(State::S1); break;
139 case 'x': c.bits.push_back(State::Sx); break;
140 case 'z': c.bits.push_back(State::Sz); break;
141 case 'm': c.bits.push_back(State::Sm); break;
142 default: c.bits.push_back(State::Sa);
143 }
144 return c;
145 }
146
147 std::string RTLIL::Const::decode_string() const
148 {
149 std::string string;
150 std::vector<char> string_chars;
151 for (int i = 0; i < int (bits.size()); i += 8) {
152 char ch = 0;
153 for (int j = 0; j < 8 && i + j < int (bits.size()); j++)
154 if (bits[i + j] == RTLIL::State::S1)
155 ch |= 1 << j;
156 if (ch != 0)
157 string_chars.push_back(ch);
158 }
159 for (int i = int (string_chars.size()) - 1; i >= 0; i--)
160 string += string_chars[i];
161 return string;
162 }
163
164 bool RTLIL::Const::is_fully_zero() const
165 {
166 cover("kernel.rtlil.const.is_fully_zero");
167
168 for (auto bit : bits)
169 if (bit != RTLIL::State::S0)
170 return false;
171
172 return true;
173 }
174
175 bool RTLIL::Const::is_fully_ones() const
176 {
177 cover("kernel.rtlil.const.is_fully_ones");
178
179 for (auto bit : bits)
180 if (bit != RTLIL::State::S1)
181 return false;
182
183 return true;
184 }
185
186 bool RTLIL::Const::is_fully_def() const
187 {
188 cover("kernel.rtlil.const.is_fully_def");
189
190 for (auto bit : bits)
191 if (bit != RTLIL::State::S0 && bit != RTLIL::State::S1)
192 return false;
193
194 return true;
195 }
196
197 bool RTLIL::Const::is_fully_undef() const
198 {
199 cover("kernel.rtlil.const.is_fully_undef");
200
201 for (auto bit : bits)
202 if (bit != RTLIL::State::Sx && bit != RTLIL::State::Sz)
203 return false;
204
205 return true;
206 }
207
208 void RTLIL::AttrObject::set_bool_attribute(RTLIL::IdString id)
209 {
210 attributes[id] = RTLIL::Const(1);
211 }
212
213 bool RTLIL::AttrObject::get_bool_attribute(RTLIL::IdString id) const
214 {
215 if (attributes.count(id) == 0)
216 return false;
217 return attributes.at(id).as_bool();
218 }
219
220 void RTLIL::AttrObject::set_strpool_attribute(RTLIL::IdString id, const pool<string> &data)
221 {
222 string attrval;
223 for (auto &s : data) {
224 if (!attrval.empty())
225 attrval += "|";
226 attrval += s;
227 }
228 attributes[id] = RTLIL::Const(attrval);
229 }
230
231 void RTLIL::AttrObject::add_strpool_attribute(RTLIL::IdString id, const pool<string> &data)
232 {
233 pool<string> union_data = get_strpool_attribute(id);
234 union_data.insert(data.begin(), data.end());
235 if (!union_data.empty())
236 set_strpool_attribute(id, union_data);
237 }
238
239 pool<string> RTLIL::AttrObject::get_strpool_attribute(RTLIL::IdString id) const
240 {
241 pool<string> data;
242 if (attributes.count(id) != 0)
243 for (auto s : split_tokens(attributes.at(id).decode_string(), "|"))
244 data.insert(s);
245 return data;
246 }
247
248 void RTLIL::AttrObject::set_src_attribute(const std::string &src)
249 {
250 if (src.empty())
251 attributes.erase("\\src");
252 else
253 attributes["\\src"] = src;
254 }
255
256 std::string RTLIL::AttrObject::get_src_attribute() const
257 {
258 std::string src;
259 if (attributes.count("\\src"))
260 src = attributes.at("\\src").decode_string();
261 return src;
262 }
263
264 bool RTLIL::Selection::selected_module(RTLIL::IdString mod_name) const
265 {
266 if (full_selection)
267 return true;
268 if (selected_modules.count(mod_name) > 0)
269 return true;
270 if (selected_members.count(mod_name) > 0)
271 return true;
272 return false;
273 }
274
275 bool RTLIL::Selection::selected_whole_module(RTLIL::IdString mod_name) const
276 {
277 if (full_selection)
278 return true;
279 if (selected_modules.count(mod_name) > 0)
280 return true;
281 return false;
282 }
283
284 bool RTLIL::Selection::selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const
285 {
286 if (full_selection)
287 return true;
288 if (selected_modules.count(mod_name) > 0)
289 return true;
290 if (selected_members.count(mod_name) > 0)
291 if (selected_members.at(mod_name).count(memb_name) > 0)
292 return true;
293 return false;
294 }
295
296 void RTLIL::Selection::optimize(RTLIL::Design *design)
297 {
298 if (full_selection) {
299 selected_modules.clear();
300 selected_members.clear();
301 return;
302 }
303
304 std::vector<RTLIL::IdString> del_list, add_list;
305
306 del_list.clear();
307 for (auto mod_name : selected_modules) {
308 if (design->modules_.count(mod_name) == 0)
309 del_list.push_back(mod_name);
310 selected_members.erase(mod_name);
311 }
312 for (auto mod_name : del_list)
313 selected_modules.erase(mod_name);
314
315 del_list.clear();
316 for (auto &it : selected_members)
317 if (design->modules_.count(it.first) == 0)
318 del_list.push_back(it.first);
319 for (auto mod_name : del_list)
320 selected_members.erase(mod_name);
321
322 for (auto &it : selected_members) {
323 del_list.clear();
324 for (auto memb_name : it.second)
325 if (design->modules_[it.first]->count_id(memb_name) == 0)
326 del_list.push_back(memb_name);
327 for (auto memb_name : del_list)
328 it.second.erase(memb_name);
329 }
330
331 del_list.clear();
332 add_list.clear();
333 for (auto &it : selected_members)
334 if (it.second.size() == 0)
335 del_list.push_back(it.first);
336 else if (it.second.size() == design->modules_[it.first]->wires_.size() + design->modules_[it.first]->memories.size() +
337 design->modules_[it.first]->cells_.size() + design->modules_[it.first]->processes.size())
338 add_list.push_back(it.first);
339 for (auto mod_name : del_list)
340 selected_members.erase(mod_name);
341 for (auto mod_name : add_list) {
342 selected_members.erase(mod_name);
343 selected_modules.insert(mod_name);
344 }
345
346 if (selected_modules.size() == design->modules_.size()) {
347 full_selection = true;
348 selected_modules.clear();
349 selected_members.clear();
350 }
351 }
352
353 RTLIL::Design::Design()
354 {
355 static unsigned int hashidx_count = 123456789;
356 hashidx_count = mkhash_xorshift(hashidx_count);
357 hashidx_ = hashidx_count;
358
359 refcount_modules_ = 0;
360 selection_stack.push_back(RTLIL::Selection());
361 }
362
363 RTLIL::Design::~Design()
364 {
365 for (auto it = modules_.begin(); it != modules_.end(); ++it)
366 delete it->second;
367 for (auto n : verilog_packages)
368 delete n;
369 for (auto n : verilog_globals)
370 delete n;
371 }
372
373 RTLIL::ObjRange<RTLIL::Module*> RTLIL::Design::modules()
374 {
375 return RTLIL::ObjRange<RTLIL::Module*>(&modules_, &refcount_modules_);
376 }
377
378 RTLIL::Module *RTLIL::Design::module(RTLIL::IdString name)
379 {
380 return modules_.count(name) ? modules_.at(name) : NULL;
381 }
382
383 RTLIL::Module *RTLIL::Design::top_module()
384 {
385 RTLIL::Module *module = nullptr;
386 int module_count = 0;
387
388 for (auto mod : selected_modules()) {
389 if (mod->get_bool_attribute("\\top"))
390 return mod;
391 module_count++;
392 module = mod;
393 }
394
395 return module_count == 1 ? module : nullptr;
396 }
397
398 void RTLIL::Design::add(RTLIL::Module *module)
399 {
400 log_assert(modules_.count(module->name) == 0);
401 log_assert(refcount_modules_ == 0);
402 modules_[module->name] = module;
403 module->design = this;
404
405 for (auto mon : monitors)
406 mon->notify_module_add(module);
407
408 if (yosys_xtrace) {
409 log("#X# New Module: %s\n", log_id(module));
410 log_backtrace("-X- ", yosys_xtrace-1);
411 }
412 }
413
414 RTLIL::Module *RTLIL::Design::addModule(RTLIL::IdString name)
415 {
416 log_assert(modules_.count(name) == 0);
417 log_assert(refcount_modules_ == 0);
418
419 RTLIL::Module *module = new RTLIL::Module;
420 modules_[name] = module;
421 module->design = this;
422 module->name = name;
423
424 for (auto mon : monitors)
425 mon->notify_module_add(module);
426
427 if (yosys_xtrace) {
428 log("#X# New Module: %s\n", log_id(module));
429 log_backtrace("-X- ", yosys_xtrace-1);
430 }
431
432 return module;
433 }
434
435 void RTLIL::Design::scratchpad_unset(std::string varname)
436 {
437 scratchpad.erase(varname);
438 }
439
440 void RTLIL::Design::scratchpad_set_int(std::string varname, int value)
441 {
442 scratchpad[varname] = stringf("%d", value);
443 }
444
445 void RTLIL::Design::scratchpad_set_bool(std::string varname, bool value)
446 {
447 scratchpad[varname] = value ? "true" : "false";
448 }
449
450 void RTLIL::Design::scratchpad_set_string(std::string varname, std::string value)
451 {
452 scratchpad[varname] = value;
453 }
454
455 int RTLIL::Design::scratchpad_get_int(std::string varname, int default_value) const
456 {
457 if (scratchpad.count(varname) == 0)
458 return default_value;
459
460 std::string str = scratchpad.at(varname);
461
462 if (str == "0" || str == "false")
463 return 0;
464
465 if (str == "1" || str == "true")
466 return 1;
467
468 char *endptr = nullptr;
469 long int parsed_value = strtol(str.c_str(), &endptr, 10);
470 return *endptr ? default_value : parsed_value;
471 }
472
473 bool RTLIL::Design::scratchpad_get_bool(std::string varname, bool default_value) const
474 {
475 if (scratchpad.count(varname) == 0)
476 return default_value;
477
478 std::string str = scratchpad.at(varname);
479
480 if (str == "0" || str == "false")
481 return false;
482
483 if (str == "1" || str == "true")
484 return true;
485
486 return default_value;
487 }
488
489 std::string RTLIL::Design::scratchpad_get_string(std::string varname, std::string default_value) const
490 {
491 if (scratchpad.count(varname) == 0)
492 return default_value;
493 return scratchpad.at(varname);
494 }
495
496 void RTLIL::Design::remove(RTLIL::Module *module)
497 {
498 for (auto mon : monitors)
499 mon->notify_module_del(module);
500
501 if (yosys_xtrace) {
502 log("#X# Remove Module: %s\n", log_id(module));
503 log_backtrace("-X- ", yosys_xtrace-1);
504 }
505
506 log_assert(modules_.at(module->name) == module);
507 modules_.erase(module->name);
508 delete module;
509 }
510
511 void RTLIL::Design::rename(RTLIL::Module *module, RTLIL::IdString new_name)
512 {
513 modules_.erase(module->name);
514 module->name = new_name;
515 add(module);
516 }
517
518 void RTLIL::Design::sort()
519 {
520 scratchpad.sort();
521 modules_.sort(sort_by_id_str());
522 for (auto &it : modules_)
523 it.second->sort();
524 }
525
526 void RTLIL::Design::check()
527 {
528 #ifndef NDEBUG
529 for (auto &it : modules_) {
530 log_assert(this == it.second->design);
531 log_assert(it.first == it.second->name);
532 log_assert(!it.first.empty());
533 it.second->check();
534 }
535 #endif
536 }
537
538 void RTLIL::Design::optimize()
539 {
540 for (auto &it : modules_)
541 it.second->optimize();
542 for (auto &it : selection_stack)
543 it.optimize(this);
544 for (auto &it : selection_vars)
545 it.second.optimize(this);
546 }
547
548 bool RTLIL::Design::selected_module(RTLIL::IdString mod_name) const
549 {
550 if (!selected_active_module.empty() && mod_name != selected_active_module)
551 return false;
552 if (selection_stack.size() == 0)
553 return true;
554 return selection_stack.back().selected_module(mod_name);
555 }
556
557 bool RTLIL::Design::selected_whole_module(RTLIL::IdString mod_name) const
558 {
559 if (!selected_active_module.empty() && mod_name != selected_active_module)
560 return false;
561 if (selection_stack.size() == 0)
562 return true;
563 return selection_stack.back().selected_whole_module(mod_name);
564 }
565
566 bool RTLIL::Design::selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const
567 {
568 if (!selected_active_module.empty() && mod_name != selected_active_module)
569 return false;
570 if (selection_stack.size() == 0)
571 return true;
572 return selection_stack.back().selected_member(mod_name, memb_name);
573 }
574
575 bool RTLIL::Design::selected_module(RTLIL::Module *mod) const
576 {
577 return selected_module(mod->name);
578 }
579
580 bool RTLIL::Design::selected_whole_module(RTLIL::Module *mod) const
581 {
582 return selected_whole_module(mod->name);
583 }
584
585 std::vector<RTLIL::Module*> RTLIL::Design::selected_modules() const
586 {
587 std::vector<RTLIL::Module*> result;
588 result.reserve(modules_.size());
589 for (auto &it : modules_)
590 if (selected_module(it.first) && !it.second->get_bool_attribute("\\blackbox"))
591 result.push_back(it.second);
592 return result;
593 }
594
595 std::vector<RTLIL::Module*> RTLIL::Design::selected_whole_modules() const
596 {
597 std::vector<RTLIL::Module*> result;
598 result.reserve(modules_.size());
599 for (auto &it : modules_)
600 if (selected_whole_module(it.first) && !it.second->get_bool_attribute("\\blackbox"))
601 result.push_back(it.second);
602 return result;
603 }
604
605 std::vector<RTLIL::Module*> RTLIL::Design::selected_whole_modules_warn() const
606 {
607 std::vector<RTLIL::Module*> result;
608 result.reserve(modules_.size());
609 for (auto &it : modules_)
610 if (it.second->get_bool_attribute("\\blackbox"))
611 continue;
612 else if (selected_whole_module(it.first))
613 result.push_back(it.second);
614 else if (selected_module(it.first))
615 log_warning("Ignoring partially selected module %s.\n", log_id(it.first));
616 return result;
617 }
618
619 RTLIL::Module::Module()
620 {
621 static unsigned int hashidx_count = 123456789;
622 hashidx_count = mkhash_xorshift(hashidx_count);
623 hashidx_ = hashidx_count;
624
625 design = nullptr;
626 refcount_wires_ = 0;
627 refcount_cells_ = 0;
628 }
629
630 RTLIL::Module::~Module()
631 {
632 for (auto it = wires_.begin(); it != wires_.end(); ++it)
633 delete it->second;
634 for (auto it = memories.begin(); it != memories.end(); ++it)
635 delete it->second;
636 for (auto it = cells_.begin(); it != cells_.end(); ++it)
637 delete it->second;
638 for (auto it = processes.begin(); it != processes.end(); ++it)
639 delete it->second;
640 }
641
642 RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, dict<RTLIL::IdString, RTLIL::Const>, bool mayfail)
643 {
644 if (mayfail)
645 return RTLIL::IdString();
646 log_error("Module `%s' is used with parameters but is not parametric!\n", id2cstr(name));
647 }
648
649 size_t RTLIL::Module::count_id(RTLIL::IdString id)
650 {
651 return wires_.count(id) + memories.count(id) + cells_.count(id) + processes.count(id);
652 }
653
654 #ifndef NDEBUG
655 namespace {
656 struct InternalCellChecker
657 {
658 RTLIL::Module *module;
659 RTLIL::Cell *cell;
660 pool<RTLIL::IdString> expected_params, expected_ports;
661
662 InternalCellChecker(RTLIL::Module *module, RTLIL::Cell *cell) : module(module), cell(cell) { }
663
664 void error(int linenr)
665 {
666 std::stringstream buf;
667 ILANG_BACKEND::dump_cell(buf, " ", cell);
668
669 log_error("Found error in internal cell %s%s%s (%s) at %s:%d:\n%s",
670 module ? module->name.c_str() : "", module ? "." : "",
671 cell->name.c_str(), cell->type.c_str(), __FILE__, linenr, buf.str().c_str());
672 }
673
674 int param(const char *name)
675 {
676 if (cell->parameters.count(name) == 0)
677 error(__LINE__);
678 expected_params.insert(name);
679 return cell->parameters.at(name).as_int();
680 }
681
682 int param_bool(const char *name)
683 {
684 int v = param(name);
685 if (cell->parameters.at(name).bits.size() > 32)
686 error(__LINE__);
687 if (v != 0 && v != 1)
688 error(__LINE__);
689 return v;
690 }
691
692 void param_bits(const char *name, int width)
693 {
694 param(name);
695 if (int(cell->parameters.at(name).bits.size()) != width)
696 error(__LINE__);
697 }
698
699 void port(const char *name, int width)
700 {
701 if (!cell->hasPort(name))
702 error(__LINE__);
703 if (cell->getPort(name).size() != width)
704 error(__LINE__);
705 expected_ports.insert(name);
706 }
707
708 void check_expected(bool check_matched_sign = true)
709 {
710 for (auto &para : cell->parameters)
711 if (expected_params.count(para.first) == 0)
712 error(__LINE__);
713 for (auto &conn : cell->connections())
714 if (expected_ports.count(conn.first) == 0)
715 error(__LINE__);
716
717 if (expected_params.count("\\A_SIGNED") != 0 && expected_params.count("\\B_SIGNED") && check_matched_sign) {
718 bool a_is_signed = param("\\A_SIGNED") != 0;
719 bool b_is_signed = param("\\B_SIGNED") != 0;
720 if (a_is_signed != b_is_signed)
721 error(__LINE__);
722 }
723 }
724
725 void check_gate(const char *ports)
726 {
727 if (cell->parameters.size() != 0)
728 error(__LINE__);
729
730 for (const char *p = ports; *p; p++) {
731 char portname[3] = { '\\', *p, 0 };
732 if (!cell->hasPort(portname))
733 error(__LINE__);
734 if (cell->getPort(portname).size() != 1)
735 error(__LINE__);
736 }
737
738 for (auto &conn : cell->connections()) {
739 if (conn.first.size() != 2 || conn.first[0] != '\\')
740 error(__LINE__);
741 if (strchr(ports, conn.first[1]) == NULL)
742 error(__LINE__);
743 }
744 }
745
746 void check()
747 {
748 if (cell->type.substr(0, 1) != "$" || cell->type.substr(0, 3) == "$__" || cell->type.substr(0, 8) == "$paramod" ||
749 cell->type.substr(0, 9) == "$verific$" || cell->type.substr(0, 7) == "$array:" || cell->type.substr(0, 8) == "$extern:")
750 return;
751
752 if (cell->type.in("$not", "$pos", "$neg")) {
753 param_bool("\\A_SIGNED");
754 port("\\A", param("\\A_WIDTH"));
755 port("\\Y", param("\\Y_WIDTH"));
756 check_expected();
757 return;
758 }
759
760 if (cell->type.in("$and", "$or", "$xor", "$xnor")) {
761 param_bool("\\A_SIGNED");
762 param_bool("\\B_SIGNED");
763 port("\\A", param("\\A_WIDTH"));
764 port("\\B", param("\\B_WIDTH"));
765 port("\\Y", param("\\Y_WIDTH"));
766 check_expected();
767 return;
768 }
769
770 if (cell->type.in("$reduce_and", "$reduce_or", "$reduce_xor", "$reduce_xnor", "$reduce_bool")) {
771 param_bool("\\A_SIGNED");
772 port("\\A", param("\\A_WIDTH"));
773 port("\\Y", param("\\Y_WIDTH"));
774 check_expected();
775 return;
776 }
777
778 if (cell->type.in("$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx")) {
779 param_bool("\\A_SIGNED");
780 param_bool("\\B_SIGNED");
781 port("\\A", param("\\A_WIDTH"));
782 port("\\B", param("\\B_WIDTH"));
783 port("\\Y", param("\\Y_WIDTH"));
784 check_expected(false);
785 return;
786 }
787
788 if (cell->type.in("$lt", "$le", "$eq", "$ne", "$eqx", "$nex", "$ge", "$gt")) {
789 param_bool("\\A_SIGNED");
790 param_bool("\\B_SIGNED");
791 port("\\A", param("\\A_WIDTH"));
792 port("\\B", param("\\B_WIDTH"));
793 port("\\Y", param("\\Y_WIDTH"));
794 check_expected();
795 return;
796 }
797
798 if (cell->type.in("$add", "$sub", "$mul", "$div", "$mod", "$pow")) {
799 param_bool("\\A_SIGNED");
800 param_bool("\\B_SIGNED");
801 port("\\A", param("\\A_WIDTH"));
802 port("\\B", param("\\B_WIDTH"));
803 port("\\Y", param("\\Y_WIDTH"));
804 check_expected(cell->type != "$pow");
805 return;
806 }
807
808 if (cell->type == "$fa") {
809 port("\\A", param("\\WIDTH"));
810 port("\\B", param("\\WIDTH"));
811 port("\\C", param("\\WIDTH"));
812 port("\\X", param("\\WIDTH"));
813 port("\\Y", param("\\WIDTH"));
814 check_expected();
815 return;
816 }
817
818 if (cell->type == "$lcu") {
819 port("\\P", param("\\WIDTH"));
820 port("\\G", param("\\WIDTH"));
821 port("\\CI", 1);
822 port("\\CO", param("\\WIDTH"));
823 check_expected();
824 return;
825 }
826
827 if (cell->type == "$alu") {
828 param_bool("\\A_SIGNED");
829 param_bool("\\B_SIGNED");
830 port("\\A", param("\\A_WIDTH"));
831 port("\\B", param("\\B_WIDTH"));
832 port("\\CI", 1);
833 port("\\BI", 1);
834 port("\\X", param("\\Y_WIDTH"));
835 port("\\Y", param("\\Y_WIDTH"));
836 port("\\CO", param("\\Y_WIDTH"));
837 check_expected();
838 return;
839 }
840
841 if (cell->type == "$macc") {
842 param("\\CONFIG");
843 param("\\CONFIG_WIDTH");
844 port("\\A", param("\\A_WIDTH"));
845 port("\\B", param("\\B_WIDTH"));
846 port("\\Y", param("\\Y_WIDTH"));
847 check_expected();
848 Macc().from_cell(cell);
849 return;
850 }
851
852 if (cell->type == "$logic_not") {
853 param_bool("\\A_SIGNED");
854 port("\\A", param("\\A_WIDTH"));
855 port("\\Y", param("\\Y_WIDTH"));
856 check_expected();
857 return;
858 }
859
860 if (cell->type == "$logic_and" || cell->type == "$logic_or") {
861 param_bool("\\A_SIGNED");
862 param_bool("\\B_SIGNED");
863 port("\\A", param("\\A_WIDTH"));
864 port("\\B", param("\\B_WIDTH"));
865 port("\\Y", param("\\Y_WIDTH"));
866 check_expected(false);
867 return;
868 }
869
870 if (cell->type == "$slice") {
871 param("\\OFFSET");
872 port("\\A", param("\\A_WIDTH"));
873 port("\\Y", param("\\Y_WIDTH"));
874 if (param("\\OFFSET") + param("\\Y_WIDTH") > param("\\A_WIDTH"))
875 error(__LINE__);
876 check_expected();
877 return;
878 }
879
880 if (cell->type == "$concat") {
881 port("\\A", param("\\A_WIDTH"));
882 port("\\B", param("\\B_WIDTH"));
883 port("\\Y", param("\\A_WIDTH") + param("\\B_WIDTH"));
884 check_expected();
885 return;
886 }
887
888 if (cell->type == "$mux") {
889 port("\\A", param("\\WIDTH"));
890 port("\\B", param("\\WIDTH"));
891 port("\\S", 1);
892 port("\\Y", param("\\WIDTH"));
893 check_expected();
894 return;
895 }
896
897 if (cell->type == "$pmux") {
898 port("\\A", param("\\WIDTH"));
899 port("\\B", param("\\WIDTH") * param("\\S_WIDTH"));
900 port("\\S", param("\\S_WIDTH"));
901 port("\\Y", param("\\WIDTH"));
902 check_expected();
903 return;
904 }
905
906 if (cell->type == "$lut") {
907 param("\\LUT");
908 port("\\A", param("\\WIDTH"));
909 port("\\Y", 1);
910 check_expected();
911 return;
912 }
913
914 if (cell->type == "$sop") {
915 param("\\DEPTH");
916 param("\\TABLE");
917 port("\\A", param("\\WIDTH"));
918 port("\\Y", 1);
919 check_expected();
920 return;
921 }
922
923 if (cell->type == "$sr") {
924 param_bool("\\SET_POLARITY");
925 param_bool("\\CLR_POLARITY");
926 port("\\SET", param("\\WIDTH"));
927 port("\\CLR", param("\\WIDTH"));
928 port("\\Q", param("\\WIDTH"));
929 check_expected();
930 return;
931 }
932
933 if (cell->type == "$ff") {
934 port("\\D", param("\\WIDTH"));
935 port("\\Q", param("\\WIDTH"));
936 check_expected();
937 return;
938 }
939
940 if (cell->type == "$dff") {
941 param_bool("\\CLK_POLARITY");
942 port("\\CLK", 1);
943 port("\\D", param("\\WIDTH"));
944 port("\\Q", param("\\WIDTH"));
945 check_expected();
946 return;
947 }
948
949 if (cell->type == "$dffe") {
950 param_bool("\\CLK_POLARITY");
951 param_bool("\\EN_POLARITY");
952 port("\\CLK", 1);
953 port("\\EN", 1);
954 port("\\D", param("\\WIDTH"));
955 port("\\Q", param("\\WIDTH"));
956 check_expected();
957 return;
958 }
959
960 if (cell->type == "$dffsr") {
961 param_bool("\\CLK_POLARITY");
962 param_bool("\\SET_POLARITY");
963 param_bool("\\CLR_POLARITY");
964 port("\\CLK", 1);
965 port("\\SET", param("\\WIDTH"));
966 port("\\CLR", param("\\WIDTH"));
967 port("\\D", param("\\WIDTH"));
968 port("\\Q", param("\\WIDTH"));
969 check_expected();
970 return;
971 }
972
973 if (cell->type == "$adff") {
974 param_bool("\\CLK_POLARITY");
975 param_bool("\\ARST_POLARITY");
976 param_bits("\\ARST_VALUE", param("\\WIDTH"));
977 port("\\CLK", 1);
978 port("\\ARST", 1);
979 port("\\D", param("\\WIDTH"));
980 port("\\Q", param("\\WIDTH"));
981 check_expected();
982 return;
983 }
984
985 if (cell->type == "$dlatch") {
986 param_bool("\\EN_POLARITY");
987 port("\\EN", 1);
988 port("\\D", param("\\WIDTH"));
989 port("\\Q", param("\\WIDTH"));
990 check_expected();
991 return;
992 }
993
994 if (cell->type == "$dlatchsr") {
995 param_bool("\\EN_POLARITY");
996 param_bool("\\SET_POLARITY");
997 param_bool("\\CLR_POLARITY");
998 port("\\EN", 1);
999 port("\\SET", param("\\WIDTH"));
1000 port("\\CLR", param("\\WIDTH"));
1001 port("\\D", param("\\WIDTH"));
1002 port("\\Q", param("\\WIDTH"));
1003 check_expected();
1004 return;
1005 }
1006
1007 if (cell->type == "$fsm") {
1008 param("\\NAME");
1009 param_bool("\\CLK_POLARITY");
1010 param_bool("\\ARST_POLARITY");
1011 param("\\STATE_BITS");
1012 param("\\STATE_NUM");
1013 param("\\STATE_NUM_LOG2");
1014 param("\\STATE_RST");
1015 param_bits("\\STATE_TABLE", param("\\STATE_BITS") * param("\\STATE_NUM"));
1016 param("\\TRANS_NUM");
1017 param_bits("\\TRANS_TABLE", param("\\TRANS_NUM") * (2*param("\\STATE_NUM_LOG2") + param("\\CTRL_IN_WIDTH") + param("\\CTRL_OUT_WIDTH")));
1018 port("\\CLK", 1);
1019 port("\\ARST", 1);
1020 port("\\CTRL_IN", param("\\CTRL_IN_WIDTH"));
1021 port("\\CTRL_OUT", param("\\CTRL_OUT_WIDTH"));
1022 check_expected();
1023 return;
1024 }
1025
1026 if (cell->type == "$memrd") {
1027 param("\\MEMID");
1028 param_bool("\\CLK_ENABLE");
1029 param_bool("\\CLK_POLARITY");
1030 param_bool("\\TRANSPARENT");
1031 port("\\CLK", 1);
1032 port("\\EN", 1);
1033 port("\\ADDR", param("\\ABITS"));
1034 port("\\DATA", param("\\WIDTH"));
1035 check_expected();
1036 return;
1037 }
1038
1039 if (cell->type == "$memwr") {
1040 param("\\MEMID");
1041 param_bool("\\CLK_ENABLE");
1042 param_bool("\\CLK_POLARITY");
1043 param("\\PRIORITY");
1044 port("\\CLK", 1);
1045 port("\\EN", param("\\WIDTH"));
1046 port("\\ADDR", param("\\ABITS"));
1047 port("\\DATA", param("\\WIDTH"));
1048 check_expected();
1049 return;
1050 }
1051
1052 if (cell->type == "$meminit") {
1053 param("\\MEMID");
1054 param("\\PRIORITY");
1055 port("\\ADDR", param("\\ABITS"));
1056 port("\\DATA", param("\\WIDTH") * param("\\WORDS"));
1057 check_expected();
1058 return;
1059 }
1060
1061 if (cell->type == "$mem") {
1062 param("\\MEMID");
1063 param("\\SIZE");
1064 param("\\OFFSET");
1065 param("\\INIT");
1066 param_bits("\\RD_CLK_ENABLE", max(1, param("\\RD_PORTS")));
1067 param_bits("\\RD_CLK_POLARITY", max(1, param("\\RD_PORTS")));
1068 param_bits("\\RD_TRANSPARENT", max(1, param("\\RD_PORTS")));
1069 param_bits("\\WR_CLK_ENABLE", max(1, param("\\WR_PORTS")));
1070 param_bits("\\WR_CLK_POLARITY", max(1, param("\\WR_PORTS")));
1071 port("\\RD_CLK", param("\\RD_PORTS"));
1072 port("\\RD_EN", param("\\RD_PORTS"));
1073 port("\\RD_ADDR", param("\\RD_PORTS") * param("\\ABITS"));
1074 port("\\RD_DATA", param("\\RD_PORTS") * param("\\WIDTH"));
1075 port("\\WR_CLK", param("\\WR_PORTS"));
1076 port("\\WR_EN", param("\\WR_PORTS") * param("\\WIDTH"));
1077 port("\\WR_ADDR", param("\\WR_PORTS") * param("\\ABITS"));
1078 port("\\WR_DATA", param("\\WR_PORTS") * param("\\WIDTH"));
1079 check_expected();
1080 return;
1081 }
1082
1083 if (cell->type == "$tribuf") {
1084 port("\\A", param("\\WIDTH"));
1085 port("\\Y", param("\\WIDTH"));
1086 port("\\EN", 1);
1087 check_expected();
1088 return;
1089 }
1090
1091 if (cell->type.in("$assert", "$assume", "$live", "$fair", "$cover")) {
1092 port("\\A", 1);
1093 port("\\EN", 1);
1094 check_expected();
1095 return;
1096 }
1097
1098 if (cell->type == "$initstate") {
1099 port("\\Y", 1);
1100 check_expected();
1101 return;
1102 }
1103
1104 if (cell->type.in("$anyconst", "$anyseq", "$allconst", "$allseq")) {
1105 port("\\Y", param("\\WIDTH"));
1106 check_expected();
1107 return;
1108 }
1109
1110 if (cell->type == "$equiv") {
1111 port("\\A", 1);
1112 port("\\B", 1);
1113 port("\\Y", 1);
1114 check_expected();
1115 return;
1116 }
1117
1118 if (cell->type == "$_BUF_") { check_gate("AY"); return; }
1119 if (cell->type == "$_NOT_") { check_gate("AY"); return; }
1120 if (cell->type == "$_AND_") { check_gate("ABY"); return; }
1121 if (cell->type == "$_NAND_") { check_gate("ABY"); return; }
1122 if (cell->type == "$_OR_") { check_gate("ABY"); return; }
1123 if (cell->type == "$_NOR_") { check_gate("ABY"); return; }
1124 if (cell->type == "$_XOR_") { check_gate("ABY"); return; }
1125 if (cell->type == "$_XNOR_") { check_gate("ABY"); return; }
1126 if (cell->type == "$_ANDNOT_") { check_gate("ABY"); return; }
1127 if (cell->type == "$_ORNOT_") { check_gate("ABY"); return; }
1128 if (cell->type == "$_MUX_") { check_gate("ABSY"); return; }
1129 if (cell->type == "$_AOI3_") { check_gate("ABCY"); return; }
1130 if (cell->type == "$_OAI3_") { check_gate("ABCY"); return; }
1131 if (cell->type == "$_AOI4_") { check_gate("ABCDY"); return; }
1132 if (cell->type == "$_OAI4_") { check_gate("ABCDY"); return; }
1133
1134 if (cell->type == "$_TBUF_") { check_gate("AYE"); return; }
1135
1136 if (cell->type == "$_MUX4_") { check_gate("ABCDSTY"); return; }
1137 if (cell->type == "$_MUX8_") { check_gate("ABCDEFGHSTUY"); return; }
1138 if (cell->type == "$_MUX16_") { check_gate("ABCDEFGHIJKLMNOPSTUVY"); return; }
1139
1140 if (cell->type == "$_SR_NN_") { check_gate("SRQ"); return; }
1141 if (cell->type == "$_SR_NP_") { check_gate("SRQ"); return; }
1142 if (cell->type == "$_SR_PN_") { check_gate("SRQ"); return; }
1143 if (cell->type == "$_SR_PP_") { check_gate("SRQ"); return; }
1144
1145 if (cell->type == "$_FF_") { check_gate("DQ"); return; }
1146 if (cell->type == "$_DFF_N_") { check_gate("DQC"); return; }
1147 if (cell->type == "$_DFF_P_") { check_gate("DQC"); return; }
1148
1149 if (cell->type == "$_DFFE_NN_") { check_gate("DQCE"); return; }
1150 if (cell->type == "$_DFFE_NP_") { check_gate("DQCE"); return; }
1151 if (cell->type == "$_DFFE_PN_") { check_gate("DQCE"); return; }
1152 if (cell->type == "$_DFFE_PP_") { check_gate("DQCE"); return; }
1153
1154 if (cell->type == "$_DFF_NN0_") { check_gate("DQCR"); return; }
1155 if (cell->type == "$_DFF_NN1_") { check_gate("DQCR"); return; }
1156 if (cell->type == "$_DFF_NP0_") { check_gate("DQCR"); return; }
1157 if (cell->type == "$_DFF_NP1_") { check_gate("DQCR"); return; }
1158 if (cell->type == "$_DFF_PN0_") { check_gate("DQCR"); return; }
1159 if (cell->type == "$_DFF_PN1_") { check_gate("DQCR"); return; }
1160 if (cell->type == "$_DFF_PP0_") { check_gate("DQCR"); return; }
1161 if (cell->type == "$_DFF_PP1_") { check_gate("DQCR"); return; }
1162
1163 if (cell->type == "$_DFFSR_NNN_") { check_gate("CSRDQ"); return; }
1164 if (cell->type == "$_DFFSR_NNP_") { check_gate("CSRDQ"); return; }
1165 if (cell->type == "$_DFFSR_NPN_") { check_gate("CSRDQ"); return; }
1166 if (cell->type == "$_DFFSR_NPP_") { check_gate("CSRDQ"); return; }
1167 if (cell->type == "$_DFFSR_PNN_") { check_gate("CSRDQ"); return; }
1168 if (cell->type == "$_DFFSR_PNP_") { check_gate("CSRDQ"); return; }
1169 if (cell->type == "$_DFFSR_PPN_") { check_gate("CSRDQ"); return; }
1170 if (cell->type == "$_DFFSR_PPP_") { check_gate("CSRDQ"); return; }
1171
1172 if (cell->type == "$_DLATCH_N_") { check_gate("EDQ"); return; }
1173 if (cell->type == "$_DLATCH_P_") { check_gate("EDQ"); return; }
1174
1175 if (cell->type == "$_DLATCHSR_NNN_") { check_gate("ESRDQ"); return; }
1176 if (cell->type == "$_DLATCHSR_NNP_") { check_gate("ESRDQ"); return; }
1177 if (cell->type == "$_DLATCHSR_NPN_") { check_gate("ESRDQ"); return; }
1178 if (cell->type == "$_DLATCHSR_NPP_") { check_gate("ESRDQ"); return; }
1179 if (cell->type == "$_DLATCHSR_PNN_") { check_gate("ESRDQ"); return; }
1180 if (cell->type == "$_DLATCHSR_PNP_") { check_gate("ESRDQ"); return; }
1181 if (cell->type == "$_DLATCHSR_PPN_") { check_gate("ESRDQ"); return; }
1182 if (cell->type == "$_DLATCHSR_PPP_") { check_gate("ESRDQ"); return; }
1183
1184 error(__LINE__);
1185 }
1186 };
1187 }
1188 #endif
1189
1190 void RTLIL::Module::sort()
1191 {
1192 wires_.sort(sort_by_id_str());
1193 cells_.sort(sort_by_id_str());
1194 avail_parameters.sort(sort_by_id_str());
1195 memories.sort(sort_by_id_str());
1196 processes.sort(sort_by_id_str());
1197 for (auto &it : cells_)
1198 it.second->sort();
1199 for (auto &it : wires_)
1200 it.second->attributes.sort(sort_by_id_str());
1201 for (auto &it : memories)
1202 it.second->attributes.sort(sort_by_id_str());
1203 }
1204
1205 void RTLIL::Module::check()
1206 {
1207 #ifndef NDEBUG
1208 std::vector<bool> ports_declared;
1209 for (auto &it : wires_) {
1210 log_assert(this == it.second->module);
1211 log_assert(it.first == it.second->name);
1212 log_assert(!it.first.empty());
1213 log_assert(it.second->width >= 0);
1214 log_assert(it.second->port_id >= 0);
1215 for (auto &it2 : it.second->attributes)
1216 log_assert(!it2.first.empty());
1217 if (it.second->port_id) {
1218 log_assert(GetSize(ports) >= it.second->port_id);
1219 log_assert(ports.at(it.second->port_id-1) == it.first);
1220 log_assert(it.second->port_input || it.second->port_output);
1221 if (GetSize(ports_declared) < it.second->port_id)
1222 ports_declared.resize(it.second->port_id);
1223 log_assert(ports_declared[it.second->port_id-1] == false);
1224 ports_declared[it.second->port_id-1] = true;
1225 } else
1226 log_assert(!it.second->port_input && !it.second->port_output);
1227 }
1228 for (auto port_declared : ports_declared)
1229 log_assert(port_declared == true);
1230 log_assert(GetSize(ports) == GetSize(ports_declared));
1231
1232 for (auto &it : memories) {
1233 log_assert(it.first == it.second->name);
1234 log_assert(!it.first.empty());
1235 log_assert(it.second->width >= 0);
1236 log_assert(it.second->size >= 0);
1237 for (auto &it2 : it.second->attributes)
1238 log_assert(!it2.first.empty());
1239 }
1240
1241 for (auto &it : cells_) {
1242 log_assert(this == it.second->module);
1243 log_assert(it.first == it.second->name);
1244 log_assert(!it.first.empty());
1245 log_assert(!it.second->type.empty());
1246 for (auto &it2 : it.second->connections()) {
1247 log_assert(!it2.first.empty());
1248 it2.second.check();
1249 }
1250 for (auto &it2 : it.second->attributes)
1251 log_assert(!it2.first.empty());
1252 for (auto &it2 : it.second->parameters)
1253 log_assert(!it2.first.empty());
1254 InternalCellChecker checker(this, it.second);
1255 checker.check();
1256 }
1257
1258 for (auto &it : processes) {
1259 log_assert(it.first == it.second->name);
1260 log_assert(!it.first.empty());
1261 // FIXME: More checks here..
1262 }
1263
1264 for (auto &it : connections_) {
1265 log_assert(it.first.size() == it.second.size());
1266 log_assert(!it.first.has_const());
1267 it.first.check();
1268 it.second.check();
1269 }
1270
1271 for (auto &it : attributes)
1272 log_assert(!it.first.empty());
1273 #endif
1274 }
1275
1276 void RTLIL::Module::optimize()
1277 {
1278 }
1279
1280 void RTLIL::Module::cloneInto(RTLIL::Module *new_mod) const
1281 {
1282 log_assert(new_mod->refcount_wires_ == 0);
1283 log_assert(new_mod->refcount_cells_ == 0);
1284
1285 new_mod->avail_parameters = avail_parameters;
1286
1287 for (auto &conn : connections_)
1288 new_mod->connect(conn);
1289
1290 for (auto &attr : attributes)
1291 new_mod->attributes[attr.first] = attr.second;
1292
1293 for (auto &it : wires_)
1294 new_mod->addWire(it.first, it.second);
1295
1296 for (auto &it : memories)
1297 new_mod->memories[it.first] = new RTLIL::Memory(*it.second);
1298
1299 for (auto &it : cells_)
1300 new_mod->addCell(it.first, it.second);
1301
1302 for (auto &it : processes)
1303 new_mod->processes[it.first] = it.second->clone();
1304
1305 struct RewriteSigSpecWorker
1306 {
1307 RTLIL::Module *mod;
1308 void operator()(RTLIL::SigSpec &sig)
1309 {
1310 std::vector<RTLIL::SigChunk> chunks = sig.chunks();
1311 for (auto &c : chunks)
1312 if (c.wire != NULL)
1313 c.wire = mod->wires_.at(c.wire->name);
1314 sig = chunks;
1315 }
1316 };
1317
1318 RewriteSigSpecWorker rewriteSigSpecWorker;
1319 rewriteSigSpecWorker.mod = new_mod;
1320 new_mod->rewrite_sigspecs(rewriteSigSpecWorker);
1321 new_mod->fixup_ports();
1322 }
1323
1324 RTLIL::Module *RTLIL::Module::clone() const
1325 {
1326 RTLIL::Module *new_mod = new RTLIL::Module;
1327 new_mod->name = name;
1328 cloneInto(new_mod);
1329 return new_mod;
1330 }
1331
1332 bool RTLIL::Module::has_memories() const
1333 {
1334 return !memories.empty();
1335 }
1336
1337 bool RTLIL::Module::has_processes() const
1338 {
1339 return !processes.empty();
1340 }
1341
1342 bool RTLIL::Module::has_memories_warn() const
1343 {
1344 if (!memories.empty())
1345 log_warning("Ignoring module %s because it contains memories (run 'memory' command first).\n", log_id(this));
1346 return !memories.empty();
1347 }
1348
1349 bool RTLIL::Module::has_processes_warn() const
1350 {
1351 if (!processes.empty())
1352 log_warning("Ignoring module %s because it contains processes (run 'proc' command first).\n", log_id(this));
1353 return !processes.empty();
1354 }
1355
1356 std::vector<RTLIL::Wire*> RTLIL::Module::selected_wires() const
1357 {
1358 std::vector<RTLIL::Wire*> result;
1359 result.reserve(wires_.size());
1360 for (auto &it : wires_)
1361 if (design->selected(this, it.second))
1362 result.push_back(it.second);
1363 return result;
1364 }
1365
1366 std::vector<RTLIL::Cell*> RTLIL::Module::selected_cells() const
1367 {
1368 std::vector<RTLIL::Cell*> result;
1369 result.reserve(wires_.size());
1370 for (auto &it : cells_)
1371 if (design->selected(this, it.second))
1372 result.push_back(it.second);
1373 return result;
1374 }
1375
1376 void RTLIL::Module::add(RTLIL::Wire *wire)
1377 {
1378 log_assert(!wire->name.empty());
1379 log_assert(count_id(wire->name) == 0);
1380 log_assert(refcount_wires_ == 0);
1381 wires_[wire->name] = wire;
1382 wire->module = this;
1383 }
1384
1385 void RTLIL::Module::add(RTLIL::Cell *cell)
1386 {
1387 log_assert(!cell->name.empty());
1388 log_assert(count_id(cell->name) == 0);
1389 log_assert(refcount_cells_ == 0);
1390 cells_[cell->name] = cell;
1391 cell->module = this;
1392 }
1393
1394 namespace {
1395 struct DeleteWireWorker
1396 {
1397 RTLIL::Module *module;
1398 const pool<RTLIL::Wire*> *wires_p;
1399
1400 void operator()(RTLIL::SigSpec &sig) {
1401 std::vector<RTLIL::SigChunk> chunks = sig;
1402 for (auto &c : chunks)
1403 if (c.wire != NULL && wires_p->count(c.wire)) {
1404 c.wire = module->addWire(NEW_ID, c.width);
1405 c.offset = 0;
1406 }
1407 sig = chunks;
1408 }
1409 };
1410 }
1411
1412 void RTLIL::Module::remove(const pool<RTLIL::Wire*> &wires)
1413 {
1414 log_assert(refcount_wires_ == 0);
1415
1416 DeleteWireWorker delete_wire_worker;
1417 delete_wire_worker.module = this;
1418 delete_wire_worker.wires_p = &wires;
1419 rewrite_sigspecs(delete_wire_worker);
1420
1421 for (auto &it : wires) {
1422 log_assert(wires_.count(it->name) != 0);
1423 wires_.erase(it->name);
1424 delete it;
1425 }
1426 }
1427
1428 void RTLIL::Module::remove(RTLIL::Cell *cell)
1429 {
1430 while (!cell->connections_.empty())
1431 cell->unsetPort(cell->connections_.begin()->first);
1432
1433 log_assert(cells_.count(cell->name) != 0);
1434 log_assert(refcount_cells_ == 0);
1435 cells_.erase(cell->name);
1436 delete cell;
1437 }
1438
1439 void RTLIL::Module::rename(RTLIL::Wire *wire, RTLIL::IdString new_name)
1440 {
1441 log_assert(wires_[wire->name] == wire);
1442 log_assert(refcount_wires_ == 0);
1443 wires_.erase(wire->name);
1444 wire->name = new_name;
1445 add(wire);
1446 }
1447
1448 void RTLIL::Module::rename(RTLIL::Cell *cell, RTLIL::IdString new_name)
1449 {
1450 log_assert(cells_[cell->name] == cell);
1451 log_assert(refcount_wires_ == 0);
1452 cells_.erase(cell->name);
1453 cell->name = new_name;
1454 add(cell);
1455 }
1456
1457 void RTLIL::Module::rename(RTLIL::IdString old_name, RTLIL::IdString new_name)
1458 {
1459 log_assert(count_id(old_name) != 0);
1460 if (wires_.count(old_name))
1461 rename(wires_.at(old_name), new_name);
1462 else if (cells_.count(old_name))
1463 rename(cells_.at(old_name), new_name);
1464 else
1465 log_abort();
1466 }
1467
1468 void RTLIL::Module::swap_names(RTLIL::Wire *w1, RTLIL::Wire *w2)
1469 {
1470 log_assert(wires_[w1->name] == w1);
1471 log_assert(wires_[w2->name] == w2);
1472 log_assert(refcount_wires_ == 0);
1473
1474 wires_.erase(w1->name);
1475 wires_.erase(w2->name);
1476
1477 std::swap(w1->name, w2->name);
1478
1479 wires_[w1->name] = w1;
1480 wires_[w2->name] = w2;
1481 }
1482
1483 void RTLIL::Module::swap_names(RTLIL::Cell *c1, RTLIL::Cell *c2)
1484 {
1485 log_assert(cells_[c1->name] == c1);
1486 log_assert(cells_[c2->name] == c2);
1487 log_assert(refcount_cells_ == 0);
1488
1489 cells_.erase(c1->name);
1490 cells_.erase(c2->name);
1491
1492 std::swap(c1->name, c2->name);
1493
1494 cells_[c1->name] = c1;
1495 cells_[c2->name] = c2;
1496 }
1497
1498 RTLIL::IdString RTLIL::Module::uniquify(RTLIL::IdString name)
1499 {
1500 int index = 0;
1501 return uniquify(name, index);
1502 }
1503
1504 RTLIL::IdString RTLIL::Module::uniquify(RTLIL::IdString name, int &index)
1505 {
1506 if (index == 0) {
1507 if (count_id(name) == 0)
1508 return name;
1509 index++;
1510 }
1511
1512 while (1) {
1513 RTLIL::IdString new_name = stringf("%s_%d", name.c_str(), index);
1514 if (count_id(new_name) == 0)
1515 return new_name;
1516 index++;
1517 }
1518 }
1519
1520 static bool fixup_ports_compare(const RTLIL::Wire *a, const RTLIL::Wire *b)
1521 {
1522 if (a->port_id && !b->port_id)
1523 return true;
1524 if (!a->port_id && b->port_id)
1525 return false;
1526
1527 if (a->port_id == b->port_id)
1528 return a->name < b->name;
1529 return a->port_id < b->port_id;
1530 }
1531
1532 void RTLIL::Module::connect(const RTLIL::SigSig &conn)
1533 {
1534 for (auto mon : monitors)
1535 mon->notify_connect(this, conn);
1536
1537 if (design)
1538 for (auto mon : design->monitors)
1539 mon->notify_connect(this, conn);
1540
1541 // ignore all attempts to assign constants to other constants
1542 if (conn.first.has_const()) {
1543 RTLIL::SigSig new_conn;
1544 for (int i = 0; i < GetSize(conn.first); i++)
1545 if (conn.first[i].wire) {
1546 new_conn.first.append(conn.first[i]);
1547 new_conn.second.append(conn.second[i]);
1548 }
1549 if (GetSize(new_conn.first))
1550 connect(new_conn);
1551 return;
1552 }
1553
1554 if (yosys_xtrace) {
1555 log("#X# Connect (SigSig) in %s: %s = %s (%d bits)\n", log_id(this), log_signal(conn.first), log_signal(conn.second), GetSize(conn.first));
1556 log_backtrace("-X- ", yosys_xtrace-1);
1557 }
1558
1559 log_assert(GetSize(conn.first) == GetSize(conn.second));
1560 connections_.push_back(conn);
1561 }
1562
1563 void RTLIL::Module::connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs)
1564 {
1565 connect(RTLIL::SigSig(lhs, rhs));
1566 }
1567
1568 void RTLIL::Module::new_connections(const std::vector<RTLIL::SigSig> &new_conn)
1569 {
1570 for (auto mon : monitors)
1571 mon->notify_connect(this, new_conn);
1572
1573 if (design)
1574 for (auto mon : design->monitors)
1575 mon->notify_connect(this, new_conn);
1576
1577 if (yosys_xtrace) {
1578 log("#X# New connections vector in %s:\n", log_id(this));
1579 for (auto &conn: new_conn)
1580 log("#X# %s = %s (%d bits)\n", log_signal(conn.first), log_signal(conn.second), GetSize(conn.first));
1581 log_backtrace("-X- ", yosys_xtrace-1);
1582 }
1583
1584 connections_ = new_conn;
1585 }
1586
1587 const std::vector<RTLIL::SigSig> &RTLIL::Module::connections() const
1588 {
1589 return connections_;
1590 }
1591
1592 void RTLIL::Module::fixup_ports()
1593 {
1594 std::vector<RTLIL::Wire*> all_ports;
1595
1596 for (auto &w : wires_)
1597 if (w.second->port_input || w.second->port_output)
1598 all_ports.push_back(w.second);
1599 else
1600 w.second->port_id = 0;
1601
1602 std::sort(all_ports.begin(), all_ports.end(), fixup_ports_compare);
1603
1604 ports.clear();
1605 for (size_t i = 0; i < all_ports.size(); i++) {
1606 ports.push_back(all_ports[i]->name);
1607 all_ports[i]->port_id = i+1;
1608 }
1609 }
1610
1611 RTLIL::Wire *RTLIL::Module::addWire(RTLIL::IdString name, int width)
1612 {
1613 RTLIL::Wire *wire = new RTLIL::Wire;
1614 wire->name = name;
1615 wire->width = width;
1616 add(wire);
1617 return wire;
1618 }
1619
1620 RTLIL::Wire *RTLIL::Module::addWire(RTLIL::IdString name, const RTLIL::Wire *other)
1621 {
1622 RTLIL::Wire *wire = addWire(name);
1623 wire->width = other->width;
1624 wire->start_offset = other->start_offset;
1625 wire->port_id = other->port_id;
1626 wire->port_input = other->port_input;
1627 wire->port_output = other->port_output;
1628 wire->upto = other->upto;
1629 wire->attributes = other->attributes;
1630 return wire;
1631 }
1632
1633 RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, RTLIL::IdString type)
1634 {
1635 RTLIL::Cell *cell = new RTLIL::Cell;
1636 cell->name = name;
1637 cell->type = type;
1638 add(cell);
1639 return cell;
1640 }
1641
1642 RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, const RTLIL::Cell *other)
1643 {
1644 RTLIL::Cell *cell = addCell(name, other->type);
1645 cell->connections_ = other->connections_;
1646 cell->parameters = other->parameters;
1647 cell->attributes = other->attributes;
1648 return cell;
1649 }
1650
1651 #define DEF_METHOD(_func, _y_size, _type) \
1652 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed, const std::string &src) { \
1653 RTLIL::Cell *cell = addCell(name, _type); \
1654 cell->parameters["\\A_SIGNED"] = is_signed; \
1655 cell->parameters["\\A_WIDTH"] = sig_a.size(); \
1656 cell->parameters["\\Y_WIDTH"] = sig_y.size(); \
1657 cell->setPort("\\A", sig_a); \
1658 cell->setPort("\\Y", sig_y); \
1659 cell->set_src_attribute(src); \
1660 return cell; \
1661 } \
1662 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed, const std::string &src) { \
1663 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
1664 add ## _func(name, sig_a, sig_y, is_signed, src); \
1665 return sig_y; \
1666 }
1667 DEF_METHOD(Not, sig_a.size(), "$not")
1668 DEF_METHOD(Pos, sig_a.size(), "$pos")
1669 DEF_METHOD(Neg, sig_a.size(), "$neg")
1670 DEF_METHOD(ReduceAnd, 1, "$reduce_and")
1671 DEF_METHOD(ReduceOr, 1, "$reduce_or")
1672 DEF_METHOD(ReduceXor, 1, "$reduce_xor")
1673 DEF_METHOD(ReduceXnor, 1, "$reduce_xnor")
1674 DEF_METHOD(ReduceBool, 1, "$reduce_bool")
1675 DEF_METHOD(LogicNot, 1, "$logic_not")
1676 #undef DEF_METHOD
1677
1678 #define DEF_METHOD(_func, _y_size, _type) \
1679 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed, const std::string &src) { \
1680 RTLIL::Cell *cell = addCell(name, _type); \
1681 cell->parameters["\\A_SIGNED"] = is_signed; \
1682 cell->parameters["\\B_SIGNED"] = is_signed; \
1683 cell->parameters["\\A_WIDTH"] = sig_a.size(); \
1684 cell->parameters["\\B_WIDTH"] = sig_b.size(); \
1685 cell->parameters["\\Y_WIDTH"] = sig_y.size(); \
1686 cell->setPort("\\A", sig_a); \
1687 cell->setPort("\\B", sig_b); \
1688 cell->setPort("\\Y", sig_y); \
1689 cell->set_src_attribute(src); \
1690 return cell; \
1691 } \
1692 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed, const std::string &src) { \
1693 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
1694 add ## _func(name, sig_a, sig_b, sig_y, is_signed, src); \
1695 return sig_y; \
1696 }
1697 DEF_METHOD(And, max(sig_a.size(), sig_b.size()), "$and")
1698 DEF_METHOD(Or, max(sig_a.size(), sig_b.size()), "$or")
1699 DEF_METHOD(Xor, max(sig_a.size(), sig_b.size()), "$xor")
1700 DEF_METHOD(Xnor, max(sig_a.size(), sig_b.size()), "$xnor")
1701 DEF_METHOD(Shl, sig_a.size(), "$shl")
1702 DEF_METHOD(Shr, sig_a.size(), "$shr")
1703 DEF_METHOD(Sshl, sig_a.size(), "$sshl")
1704 DEF_METHOD(Sshr, sig_a.size(), "$sshr")
1705 DEF_METHOD(Shift, sig_a.size(), "$shift")
1706 DEF_METHOD(Shiftx, sig_a.size(), "$shiftx")
1707 DEF_METHOD(Lt, 1, "$lt")
1708 DEF_METHOD(Le, 1, "$le")
1709 DEF_METHOD(Eq, 1, "$eq")
1710 DEF_METHOD(Ne, 1, "$ne")
1711 DEF_METHOD(Eqx, 1, "$eqx")
1712 DEF_METHOD(Nex, 1, "$nex")
1713 DEF_METHOD(Ge, 1, "$ge")
1714 DEF_METHOD(Gt, 1, "$gt")
1715 DEF_METHOD(Add, max(sig_a.size(), sig_b.size()), "$add")
1716 DEF_METHOD(Sub, max(sig_a.size(), sig_b.size()), "$sub")
1717 DEF_METHOD(Mul, max(sig_a.size(), sig_b.size()), "$mul")
1718 DEF_METHOD(Div, max(sig_a.size(), sig_b.size()), "$div")
1719 DEF_METHOD(Mod, max(sig_a.size(), sig_b.size()), "$mod")
1720 DEF_METHOD(LogicAnd, 1, "$logic_and")
1721 DEF_METHOD(LogicOr, 1, "$logic_or")
1722 #undef DEF_METHOD
1723
1724 #define DEF_METHOD(_func, _type, _pmux) \
1725 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, RTLIL::SigSpec sig_y, const std::string &src) { \
1726 RTLIL::Cell *cell = addCell(name, _type); \
1727 cell->parameters["\\WIDTH"] = sig_a.size(); \
1728 if (_pmux) cell->parameters["\\S_WIDTH"] = sig_s.size(); \
1729 cell->setPort("\\A", sig_a); \
1730 cell->setPort("\\B", sig_b); \
1731 cell->setPort("\\S", sig_s); \
1732 cell->setPort("\\Y", sig_y); \
1733 cell->set_src_attribute(src); \
1734 return cell; \
1735 } \
1736 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, const std::string &src) { \
1737 RTLIL::SigSpec sig_y = addWire(NEW_ID, sig_a.size()); \
1738 add ## _func(name, sig_a, sig_b, sig_s, sig_y, src); \
1739 return sig_y; \
1740 }
1741 DEF_METHOD(Mux, "$mux", 0)
1742 DEF_METHOD(Pmux, "$pmux", 1)
1743 #undef DEF_METHOD
1744
1745 #define DEF_METHOD_2(_func, _type, _P1, _P2) \
1746 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, const std::string &src) { \
1747 RTLIL::Cell *cell = addCell(name, _type); \
1748 cell->setPort("\\" #_P1, sig1); \
1749 cell->setPort("\\" #_P2, sig2); \
1750 cell->set_src_attribute(src); \
1751 return cell; \
1752 } \
1753 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, const std::string &src) { \
1754 RTLIL::SigBit sig2 = addWire(NEW_ID); \
1755 add ## _func(name, sig1, sig2, src); \
1756 return sig2; \
1757 }
1758 #define DEF_METHOD_3(_func, _type, _P1, _P2, _P3) \
1759 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, const std::string &src) { \
1760 RTLIL::Cell *cell = addCell(name, _type); \
1761 cell->setPort("\\" #_P1, sig1); \
1762 cell->setPort("\\" #_P2, sig2); \
1763 cell->setPort("\\" #_P3, sig3); \
1764 cell->set_src_attribute(src); \
1765 return cell; \
1766 } \
1767 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, const std::string &src) { \
1768 RTLIL::SigBit sig3 = addWire(NEW_ID); \
1769 add ## _func(name, sig1, sig2, sig3, src); \
1770 return sig3; \
1771 }
1772 #define DEF_METHOD_4(_func, _type, _P1, _P2, _P3, _P4) \
1773 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, RTLIL::SigBit sig4, const std::string &src) { \
1774 RTLIL::Cell *cell = addCell(name, _type); \
1775 cell->setPort("\\" #_P1, sig1); \
1776 cell->setPort("\\" #_P2, sig2); \
1777 cell->setPort("\\" #_P3, sig3); \
1778 cell->setPort("\\" #_P4, sig4); \
1779 cell->set_src_attribute(src); \
1780 return cell; \
1781 } \
1782 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, const std::string &src) { \
1783 RTLIL::SigBit sig4 = addWire(NEW_ID); \
1784 add ## _func(name, sig1, sig2, sig3, sig4, src); \
1785 return sig4; \
1786 }
1787 #define DEF_METHOD_5(_func, _type, _P1, _P2, _P3, _P4, _P5) \
1788 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, RTLIL::SigBit sig4, RTLIL::SigBit sig5, const std::string &src) { \
1789 RTLIL::Cell *cell = addCell(name, _type); \
1790 cell->setPort("\\" #_P1, sig1); \
1791 cell->setPort("\\" #_P2, sig2); \
1792 cell->setPort("\\" #_P3, sig3); \
1793 cell->setPort("\\" #_P4, sig4); \
1794 cell->setPort("\\" #_P5, sig5); \
1795 cell->set_src_attribute(src); \
1796 return cell; \
1797 } \
1798 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, RTLIL::SigBit sig4, const std::string &src) { \
1799 RTLIL::SigBit sig5 = addWire(NEW_ID); \
1800 add ## _func(name, sig1, sig2, sig3, sig4, sig5, src); \
1801 return sig5; \
1802 }
1803 DEF_METHOD_2(BufGate, "$_BUF_", A, Y)
1804 DEF_METHOD_2(NotGate, "$_NOT_", A, Y)
1805 DEF_METHOD_3(AndGate, "$_AND_", A, B, Y)
1806 DEF_METHOD_3(NandGate, "$_NAND_", A, B, Y)
1807 DEF_METHOD_3(OrGate, "$_OR_", A, B, Y)
1808 DEF_METHOD_3(NorGate, "$_NOR_", A, B, Y)
1809 DEF_METHOD_3(XorGate, "$_XOR_", A, B, Y)
1810 DEF_METHOD_3(XnorGate, "$_XNOR_", A, B, Y)
1811 DEF_METHOD_3(AndnotGate, "$_ANDNOT_", A, B, Y)
1812 DEF_METHOD_3(OrnotGate, "$_ORNOT_", A, B, Y)
1813 DEF_METHOD_4(MuxGate, "$_MUX_", A, B, S, Y)
1814 DEF_METHOD_4(Aoi3Gate, "$_AOI3_", A, B, C, Y)
1815 DEF_METHOD_4(Oai3Gate, "$_OAI3_", A, B, C, Y)
1816 DEF_METHOD_5(Aoi4Gate, "$_AOI4_", A, B, C, D, Y)
1817 DEF_METHOD_5(Oai4Gate, "$_OAI4_", A, B, C, D, Y)
1818 #undef DEF_METHOD_2
1819 #undef DEF_METHOD_3
1820 #undef DEF_METHOD_4
1821 #undef DEF_METHOD_5
1822
1823 RTLIL::Cell* RTLIL::Module::addPow(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool a_signed, bool b_signed, const std::string &src)
1824 {
1825 RTLIL::Cell *cell = addCell(name, "$pow");
1826 cell->parameters["\\A_SIGNED"] = a_signed;
1827 cell->parameters["\\B_SIGNED"] = b_signed;
1828 cell->parameters["\\A_WIDTH"] = sig_a.size();
1829 cell->parameters["\\B_WIDTH"] = sig_b.size();
1830 cell->parameters["\\Y_WIDTH"] = sig_y.size();
1831 cell->setPort("\\A", sig_a);
1832 cell->setPort("\\B", sig_b);
1833 cell->setPort("\\Y", sig_y);
1834 cell->set_src_attribute(src);
1835 return cell;
1836 }
1837
1838 RTLIL::Cell* RTLIL::Module::addSlice(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, RTLIL::Const offset, const std::string &src)
1839 {
1840 RTLIL::Cell *cell = addCell(name, "$slice");
1841 cell->parameters["\\A_WIDTH"] = sig_a.size();
1842 cell->parameters["\\Y_WIDTH"] = sig_y.size();
1843 cell->parameters["\\OFFSET"] = offset;
1844 cell->setPort("\\A", sig_a);
1845 cell->setPort("\\Y", sig_y);
1846 cell->set_src_attribute(src);
1847 return cell;
1848 }
1849
1850 RTLIL::Cell* RTLIL::Module::addConcat(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, const std::string &src)
1851 {
1852 RTLIL::Cell *cell = addCell(name, "$concat");
1853 cell->parameters["\\A_WIDTH"] = sig_a.size();
1854 cell->parameters["\\B_WIDTH"] = sig_b.size();
1855 cell->setPort("\\A", sig_a);
1856 cell->setPort("\\B", sig_b);
1857 cell->setPort("\\Y", sig_y);
1858 cell->set_src_attribute(src);
1859 return cell;
1860 }
1861
1862 RTLIL::Cell* RTLIL::Module::addLut(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, RTLIL::Const lut, const std::string &src)
1863 {
1864 RTLIL::Cell *cell = addCell(name, "$lut");
1865 cell->parameters["\\LUT"] = lut;
1866 cell->parameters["\\WIDTH"] = sig_a.size();
1867 cell->setPort("\\A", sig_a);
1868 cell->setPort("\\Y", sig_y);
1869 cell->set_src_attribute(src);
1870 return cell;
1871 }
1872
1873 RTLIL::Cell* RTLIL::Module::addTribuf(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_y, const std::string &src)
1874 {
1875 RTLIL::Cell *cell = addCell(name, "$tribuf");
1876 cell->parameters["\\WIDTH"] = sig_a.size();
1877 cell->setPort("\\A", sig_a);
1878 cell->setPort("\\EN", sig_en);
1879 cell->setPort("\\Y", sig_y);
1880 cell->set_src_attribute(src);
1881 return cell;
1882 }
1883
1884 RTLIL::Cell* RTLIL::Module::addAssert(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src)
1885 {
1886 RTLIL::Cell *cell = addCell(name, "$assert");
1887 cell->setPort("\\A", sig_a);
1888 cell->setPort("\\EN", sig_en);
1889 cell->set_src_attribute(src);
1890 return cell;
1891 }
1892
1893 RTLIL::Cell* RTLIL::Module::addAssume(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src)
1894 {
1895 RTLIL::Cell *cell = addCell(name, "$assume");
1896 cell->setPort("\\A", sig_a);
1897 cell->setPort("\\EN", sig_en);
1898 cell->set_src_attribute(src);
1899 return cell;
1900 }
1901
1902 RTLIL::Cell* RTLIL::Module::addLive(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src)
1903 {
1904 RTLIL::Cell *cell = addCell(name, "$live");
1905 cell->setPort("\\A", sig_a);
1906 cell->setPort("\\EN", sig_en);
1907 cell->set_src_attribute(src);
1908 return cell;
1909 }
1910
1911 RTLIL::Cell* RTLIL::Module::addFair(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src)
1912 {
1913 RTLIL::Cell *cell = addCell(name, "$fair");
1914 cell->setPort("\\A", sig_a);
1915 cell->setPort("\\EN", sig_en);
1916 cell->set_src_attribute(src);
1917 return cell;
1918 }
1919
1920 RTLIL::Cell* RTLIL::Module::addCover(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src)
1921 {
1922 RTLIL::Cell *cell = addCell(name, "$cover");
1923 cell->setPort("\\A", sig_a);
1924 cell->setPort("\\EN", sig_en);
1925 cell->set_src_attribute(src);
1926 return cell;
1927 }
1928
1929 RTLIL::Cell* RTLIL::Module::addEquiv(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, const std::string &src)
1930 {
1931 RTLIL::Cell *cell = addCell(name, "$equiv");
1932 cell->setPort("\\A", sig_a);
1933 cell->setPort("\\B", sig_b);
1934 cell->setPort("\\Y", sig_y);
1935 cell->set_src_attribute(src);
1936 return cell;
1937 }
1938
1939 RTLIL::Cell* RTLIL::Module::addSr(RTLIL::IdString name, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr, RTLIL::SigSpec sig_q, bool set_polarity, bool clr_polarity, const std::string &src)
1940 {
1941 RTLIL::Cell *cell = addCell(name, "$sr");
1942 cell->parameters["\\SET_POLARITY"] = set_polarity;
1943 cell->parameters["\\CLR_POLARITY"] = clr_polarity;
1944 cell->parameters["\\WIDTH"] = sig_q.size();
1945 cell->setPort("\\SET", sig_set);
1946 cell->setPort("\\CLR", sig_clr);
1947 cell->setPort("\\Q", sig_q);
1948 cell->set_src_attribute(src);
1949 return cell;
1950 }
1951
1952 RTLIL::Cell* RTLIL::Module::addFf(RTLIL::IdString name, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, const std::string &src)
1953 {
1954 RTLIL::Cell *cell = addCell(name, "$ff");
1955 cell->parameters["\\WIDTH"] = sig_q.size();
1956 cell->setPort("\\D", sig_d);
1957 cell->setPort("\\Q", sig_q);
1958 cell->set_src_attribute(src);
1959 return cell;
1960 }
1961
1962 RTLIL::Cell* RTLIL::Module::addDff(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, const std::string &src)
1963 {
1964 RTLIL::Cell *cell = addCell(name, "$dff");
1965 cell->parameters["\\CLK_POLARITY"] = clk_polarity;
1966 cell->parameters["\\WIDTH"] = sig_q.size();
1967 cell->setPort("\\CLK", sig_clk);
1968 cell->setPort("\\D", sig_d);
1969 cell->setPort("\\Q", sig_q);
1970 cell->set_src_attribute(src);
1971 return cell;
1972 }
1973
1974 RTLIL::Cell* RTLIL::Module::addDffe(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, bool en_polarity, const std::string &src)
1975 {
1976 RTLIL::Cell *cell = addCell(name, "$dffe");
1977 cell->parameters["\\CLK_POLARITY"] = clk_polarity;
1978 cell->parameters["\\EN_POLARITY"] = en_polarity;
1979 cell->parameters["\\WIDTH"] = sig_q.size();
1980 cell->setPort("\\CLK", sig_clk);
1981 cell->setPort("\\EN", sig_en);
1982 cell->setPort("\\D", sig_d);
1983 cell->setPort("\\Q", sig_q);
1984 cell->set_src_attribute(src);
1985 return cell;
1986 }
1987
1988 RTLIL::Cell* RTLIL::Module::addDffsr(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
1989 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
1990 {
1991 RTLIL::Cell *cell = addCell(name, "$dffsr");
1992 cell->parameters["\\CLK_POLARITY"] = clk_polarity;
1993 cell->parameters["\\SET_POLARITY"] = set_polarity;
1994 cell->parameters["\\CLR_POLARITY"] = clr_polarity;
1995 cell->parameters["\\WIDTH"] = sig_q.size();
1996 cell->setPort("\\CLK", sig_clk);
1997 cell->setPort("\\SET", sig_set);
1998 cell->setPort("\\CLR", sig_clr);
1999 cell->setPort("\\D", sig_d);
2000 cell->setPort("\\Q", sig_q);
2001 cell->set_src_attribute(src);
2002 return cell;
2003 }
2004
2005 RTLIL::Cell* RTLIL::Module::addAdff(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_arst, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q,
2006 RTLIL::Const arst_value, bool clk_polarity, bool arst_polarity, const std::string &src)
2007 {
2008 RTLIL::Cell *cell = addCell(name, "$adff");
2009 cell->parameters["\\CLK_POLARITY"] = clk_polarity;
2010 cell->parameters["\\ARST_POLARITY"] = arst_polarity;
2011 cell->parameters["\\ARST_VALUE"] = arst_value;
2012 cell->parameters["\\WIDTH"] = sig_q.size();
2013 cell->setPort("\\CLK", sig_clk);
2014 cell->setPort("\\ARST", sig_arst);
2015 cell->setPort("\\D", sig_d);
2016 cell->setPort("\\Q", sig_q);
2017 cell->set_src_attribute(src);
2018 return cell;
2019 }
2020
2021 RTLIL::Cell* RTLIL::Module::addDlatch(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity, const std::string &src)
2022 {
2023 RTLIL::Cell *cell = addCell(name, "$dlatch");
2024 cell->parameters["\\EN_POLARITY"] = en_polarity;
2025 cell->parameters["\\WIDTH"] = sig_q.size();
2026 cell->setPort("\\EN", sig_en);
2027 cell->setPort("\\D", sig_d);
2028 cell->setPort("\\Q", sig_q);
2029 cell->set_src_attribute(src);
2030 return cell;
2031 }
2032
2033 RTLIL::Cell* RTLIL::Module::addDlatchsr(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
2034 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
2035 {
2036 RTLIL::Cell *cell = addCell(name, "$dlatchsr");
2037 cell->parameters["\\EN_POLARITY"] = en_polarity;
2038 cell->parameters["\\SET_POLARITY"] = set_polarity;
2039 cell->parameters["\\CLR_POLARITY"] = clr_polarity;
2040 cell->parameters["\\WIDTH"] = sig_q.size();
2041 cell->setPort("\\EN", sig_en);
2042 cell->setPort("\\SET", sig_set);
2043 cell->setPort("\\CLR", sig_clr);
2044 cell->setPort("\\D", sig_d);
2045 cell->setPort("\\Q", sig_q);
2046 cell->set_src_attribute(src);
2047 return cell;
2048 }
2049
2050 RTLIL::Cell* RTLIL::Module::addFfGate(RTLIL::IdString name, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, const std::string &src)
2051 {
2052 RTLIL::Cell *cell = addCell(name, "$_FF_");
2053 cell->setPort("\\D", sig_d);
2054 cell->setPort("\\Q", sig_q);
2055 cell->set_src_attribute(src);
2056 return cell;
2057 }
2058
2059 RTLIL::Cell* RTLIL::Module::addDffGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, const std::string &src)
2060 {
2061 RTLIL::Cell *cell = addCell(name, stringf("$_DFF_%c_", clk_polarity ? 'P' : 'N'));
2062 cell->setPort("\\C", sig_clk);
2063 cell->setPort("\\D", sig_d);
2064 cell->setPort("\\Q", sig_q);
2065 cell->set_src_attribute(src);
2066 return cell;
2067 }
2068
2069 RTLIL::Cell* RTLIL::Module::addDffeGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, bool en_polarity, const std::string &src)
2070 {
2071 RTLIL::Cell *cell = addCell(name, stringf("$_DFFE_%c%c_", clk_polarity ? 'P' : 'N', en_polarity ? 'P' : 'N'));
2072 cell->setPort("\\C", sig_clk);
2073 cell->setPort("\\E", sig_en);
2074 cell->setPort("\\D", sig_d);
2075 cell->setPort("\\Q", sig_q);
2076 cell->set_src_attribute(src);
2077 return cell;
2078 }
2079
2080 RTLIL::Cell* RTLIL::Module::addDffsrGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
2081 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
2082 {
2083 RTLIL::Cell *cell = addCell(name, stringf("$_DFFSR_%c%c%c_", clk_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N'));
2084 cell->setPort("\\C", sig_clk);
2085 cell->setPort("\\S", sig_set);
2086 cell->setPort("\\R", sig_clr);
2087 cell->setPort("\\D", sig_d);
2088 cell->setPort("\\Q", sig_q);
2089 cell->set_src_attribute(src);
2090 return cell;
2091 }
2092
2093 RTLIL::Cell* RTLIL::Module::addAdffGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_arst, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q,
2094 bool arst_value, bool clk_polarity, bool arst_polarity, const std::string &src)
2095 {
2096 RTLIL::Cell *cell = addCell(name, stringf("$_DFF_%c%c%c_", clk_polarity ? 'P' : 'N', arst_polarity ? 'P' : 'N', arst_value ? '1' : '0'));
2097 cell->setPort("\\C", sig_clk);
2098 cell->setPort("\\R", sig_arst);
2099 cell->setPort("\\D", sig_d);
2100 cell->setPort("\\Q", sig_q);
2101 cell->set_src_attribute(src);
2102 return cell;
2103 }
2104
2105 RTLIL::Cell* RTLIL::Module::addDlatchGate(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity, const std::string &src)
2106 {
2107 RTLIL::Cell *cell = addCell(name, stringf("$_DLATCH_%c_", en_polarity ? 'P' : 'N'));
2108 cell->setPort("\\E", sig_en);
2109 cell->setPort("\\D", sig_d);
2110 cell->setPort("\\Q", sig_q);
2111 cell->set_src_attribute(src);
2112 return cell;
2113 }
2114
2115 RTLIL::Cell* RTLIL::Module::addDlatchsrGate(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
2116 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
2117 {
2118 RTLIL::Cell *cell = addCell(name, stringf("$_DLATCHSR_%c%c%c_", en_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N'));
2119 cell->setPort("\\E", sig_en);
2120 cell->setPort("\\S", sig_set);
2121 cell->setPort("\\R", sig_clr);
2122 cell->setPort("\\D", sig_d);
2123 cell->setPort("\\Q", sig_q);
2124 cell->set_src_attribute(src);
2125 return cell;
2126 }
2127
2128 RTLIL::SigSpec RTLIL::Module::Anyconst(RTLIL::IdString name, int width, const std::string &src)
2129 {
2130 RTLIL::SigSpec sig = addWire(NEW_ID, width);
2131 Cell *cell = addCell(name, "$anyconst");
2132 cell->setParam("\\WIDTH", width);
2133 cell->setPort("\\Y", sig);
2134 cell->set_src_attribute(src);
2135 return sig;
2136 }
2137
2138 RTLIL::SigSpec RTLIL::Module::Anyseq(RTLIL::IdString name, int width, const std::string &src)
2139 {
2140 RTLIL::SigSpec sig = addWire(NEW_ID, width);
2141 Cell *cell = addCell(name, "$anyseq");
2142 cell->setParam("\\WIDTH", width);
2143 cell->setPort("\\Y", sig);
2144 cell->set_src_attribute(src);
2145 return sig;
2146 }
2147
2148 RTLIL::SigSpec RTLIL::Module::Allconst(RTLIL::IdString name, int width, const std::string &src)
2149 {
2150 RTLIL::SigSpec sig = addWire(NEW_ID, width);
2151 Cell *cell = addCell(name, "$allconst");
2152 cell->setParam("\\WIDTH", width);
2153 cell->setPort("\\Y", sig);
2154 cell->set_src_attribute(src);
2155 return sig;
2156 }
2157
2158 RTLIL::SigSpec RTLIL::Module::Allseq(RTLIL::IdString name, int width, const std::string &src)
2159 {
2160 RTLIL::SigSpec sig = addWire(NEW_ID, width);
2161 Cell *cell = addCell(name, "$allseq");
2162 cell->setParam("\\WIDTH", width);
2163 cell->setPort("\\Y", sig);
2164 cell->set_src_attribute(src);
2165 return sig;
2166 }
2167
2168 RTLIL::SigSpec RTLIL::Module::Initstate(RTLIL::IdString name, const std::string &src)
2169 {
2170 RTLIL::SigSpec sig = addWire(NEW_ID);
2171 Cell *cell = addCell(name, "$initstate");
2172 cell->setPort("\\Y", sig);
2173 cell->set_src_attribute(src);
2174 return sig;
2175 }
2176
2177 RTLIL::Wire::Wire()
2178 {
2179 static unsigned int hashidx_count = 123456789;
2180 hashidx_count = mkhash_xorshift(hashidx_count);
2181 hashidx_ = hashidx_count;
2182
2183 module = nullptr;
2184 width = 1;
2185 start_offset = 0;
2186 port_id = 0;
2187 port_input = false;
2188 port_output = false;
2189 upto = false;
2190 }
2191
2192 RTLIL::Memory::Memory()
2193 {
2194 static unsigned int hashidx_count = 123456789;
2195 hashidx_count = mkhash_xorshift(hashidx_count);
2196 hashidx_ = hashidx_count;
2197
2198 width = 1;
2199 start_offset = 0;
2200 size = 0;
2201 }
2202
2203 RTLIL::Cell::Cell() : module(nullptr)
2204 {
2205 static unsigned int hashidx_count = 123456789;
2206 hashidx_count = mkhash_xorshift(hashidx_count);
2207 hashidx_ = hashidx_count;
2208
2209 // log("#memtrace# %p\n", this);
2210 memhasher();
2211 }
2212
2213 bool RTLIL::Cell::hasPort(RTLIL::IdString portname) const
2214 {
2215 return connections_.count(portname) != 0;
2216 }
2217
2218 void RTLIL::Cell::unsetPort(RTLIL::IdString portname)
2219 {
2220 RTLIL::SigSpec signal;
2221 auto conn_it = connections_.find(portname);
2222
2223 if (conn_it != connections_.end())
2224 {
2225 for (auto mon : module->monitors)
2226 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
2227
2228 if (module->design)
2229 for (auto mon : module->design->monitors)
2230 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
2231
2232 if (yosys_xtrace) {
2233 log("#X# Unconnect %s.%s.%s\n", log_id(this->module), log_id(this), log_id(portname));
2234 log_backtrace("-X- ", yosys_xtrace-1);
2235 }
2236
2237 connections_.erase(conn_it);
2238 }
2239 }
2240
2241 void RTLIL::Cell::setPort(RTLIL::IdString portname, RTLIL::SigSpec signal)
2242 {
2243 auto conn_it = connections_.find(portname);
2244
2245 if (conn_it == connections_.end()) {
2246 connections_[portname] = RTLIL::SigSpec();
2247 conn_it = connections_.find(portname);
2248 log_assert(conn_it != connections_.end());
2249 } else
2250 if (conn_it->second == signal)
2251 return;
2252
2253 for (auto mon : module->monitors)
2254 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
2255
2256 if (module->design)
2257 for (auto mon : module->design->monitors)
2258 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
2259
2260 if (yosys_xtrace) {
2261 log("#X# Connect %s.%s.%s = %s (%d)\n", log_id(this->module), log_id(this), log_id(portname), log_signal(signal), GetSize(signal));
2262 log_backtrace("-X- ", yosys_xtrace-1);
2263 }
2264
2265 conn_it->second = signal;
2266 }
2267
2268 const RTLIL::SigSpec &RTLIL::Cell::getPort(RTLIL::IdString portname) const
2269 {
2270 return connections_.at(portname);
2271 }
2272
2273 const dict<RTLIL::IdString, RTLIL::SigSpec> &RTLIL::Cell::connections() const
2274 {
2275 return connections_;
2276 }
2277
2278 bool RTLIL::Cell::known() const
2279 {
2280 if (yosys_celltypes.cell_known(type))
2281 return true;
2282 if (module && module->design && module->design->module(type))
2283 return true;
2284 return false;
2285 }
2286
2287 bool RTLIL::Cell::input(RTLIL::IdString portname) const
2288 {
2289 if (yosys_celltypes.cell_known(type))
2290 return yosys_celltypes.cell_input(type, portname);
2291 if (module && module->design) {
2292 RTLIL::Module *m = module->design->module(type);
2293 RTLIL::Wire *w = m ? m->wire(portname) : nullptr;
2294 return w && w->port_input;
2295 }
2296 return false;
2297 }
2298
2299 bool RTLIL::Cell::output(RTLIL::IdString portname) const
2300 {
2301 if (yosys_celltypes.cell_known(type))
2302 return yosys_celltypes.cell_output(type, portname);
2303 if (module && module->design) {
2304 RTLIL::Module *m = module->design->module(type);
2305 RTLIL::Wire *w = m ? m->wire(portname) : nullptr;
2306 return w && w->port_output;
2307 }
2308 return false;
2309 }
2310
2311 bool RTLIL::Cell::hasParam(RTLIL::IdString paramname) const
2312 {
2313 return parameters.count(paramname) != 0;
2314 }
2315
2316 void RTLIL::Cell::unsetParam(RTLIL::IdString paramname)
2317 {
2318 parameters.erase(paramname);
2319 }
2320
2321 void RTLIL::Cell::setParam(RTLIL::IdString paramname, RTLIL::Const value)
2322 {
2323 parameters[paramname] = value;
2324 }
2325
2326 const RTLIL::Const &RTLIL::Cell::getParam(RTLIL::IdString paramname) const
2327 {
2328 return parameters.at(paramname);
2329 }
2330
2331 void RTLIL::Cell::sort()
2332 {
2333 connections_.sort(sort_by_id_str());
2334 parameters.sort(sort_by_id_str());
2335 attributes.sort(sort_by_id_str());
2336 }
2337
2338 void RTLIL::Cell::check()
2339 {
2340 #ifndef NDEBUG
2341 InternalCellChecker checker(NULL, this);
2342 checker.check();
2343 #endif
2344 }
2345
2346 void RTLIL::Cell::fixup_parameters(bool set_a_signed, bool set_b_signed)
2347 {
2348 if (type.substr(0, 1) != "$" || type.substr(0, 2) == "$_" || type.substr(0, 8) == "$paramod" ||
2349 type.substr(0, 9) == "$verific$" || type.substr(0, 7) == "$array:" || type.substr(0, 8) == "$extern:")
2350 return;
2351
2352 if (type == "$mux" || type == "$pmux") {
2353 parameters["\\WIDTH"] = GetSize(connections_["\\Y"]);
2354 if (type == "$pmux")
2355 parameters["\\S_WIDTH"] = GetSize(connections_["\\S"]);
2356 check();
2357 return;
2358 }
2359
2360 if (type == "$lut" || type == "$sop") {
2361 parameters["\\WIDTH"] = GetSize(connections_["\\A"]);
2362 return;
2363 }
2364
2365 if (type == "$fa") {
2366 parameters["\\WIDTH"] = GetSize(connections_["\\Y"]);
2367 return;
2368 }
2369
2370 if (type == "$lcu") {
2371 parameters["\\WIDTH"] = GetSize(connections_["\\CO"]);
2372 return;
2373 }
2374
2375 bool signedness_ab = !type.in("$slice", "$concat", "$macc");
2376
2377 if (connections_.count("\\A")) {
2378 if (signedness_ab) {
2379 if (set_a_signed)
2380 parameters["\\A_SIGNED"] = true;
2381 else if (parameters.count("\\A_SIGNED") == 0)
2382 parameters["\\A_SIGNED"] = false;
2383 }
2384 parameters["\\A_WIDTH"] = GetSize(connections_["\\A"]);
2385 }
2386
2387 if (connections_.count("\\B")) {
2388 if (signedness_ab) {
2389 if (set_b_signed)
2390 parameters["\\B_SIGNED"] = true;
2391 else if (parameters.count("\\B_SIGNED") == 0)
2392 parameters["\\B_SIGNED"] = false;
2393 }
2394 parameters["\\B_WIDTH"] = GetSize(connections_["\\B"]);
2395 }
2396
2397 if (connections_.count("\\Y"))
2398 parameters["\\Y_WIDTH"] = GetSize(connections_["\\Y"]);
2399
2400 check();
2401 }
2402
2403 RTLIL::SigChunk::SigChunk()
2404 {
2405 wire = NULL;
2406 width = 0;
2407 offset = 0;
2408 }
2409
2410 RTLIL::SigChunk::SigChunk(const RTLIL::Const &value)
2411 {
2412 wire = NULL;
2413 data = value.bits;
2414 width = GetSize(data);
2415 offset = 0;
2416 }
2417
2418 RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire)
2419 {
2420 log_assert(wire != nullptr);
2421 this->wire = wire;
2422 this->width = wire->width;
2423 this->offset = 0;
2424 }
2425
2426 RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire, int offset, int width)
2427 {
2428 log_assert(wire != nullptr);
2429 this->wire = wire;
2430 this->width = width;
2431 this->offset = offset;
2432 }
2433
2434 RTLIL::SigChunk::SigChunk(const std::string &str)
2435 {
2436 wire = NULL;
2437 data = RTLIL::Const(str).bits;
2438 width = GetSize(data);
2439 offset = 0;
2440 }
2441
2442 RTLIL::SigChunk::SigChunk(int val, int width)
2443 {
2444 wire = NULL;
2445 data = RTLIL::Const(val, width).bits;
2446 this->width = GetSize(data);
2447 offset = 0;
2448 }
2449
2450 RTLIL::SigChunk::SigChunk(RTLIL::State bit, int width)
2451 {
2452 wire = NULL;
2453 data = RTLIL::Const(bit, width).bits;
2454 this->width = GetSize(data);
2455 offset = 0;
2456 }
2457
2458 RTLIL::SigChunk::SigChunk(RTLIL::SigBit bit)
2459 {
2460 wire = bit.wire;
2461 offset = 0;
2462 if (wire == NULL)
2463 data = RTLIL::Const(bit.data).bits;
2464 else
2465 offset = bit.offset;
2466 width = 1;
2467 }
2468
2469 RTLIL::SigChunk RTLIL::SigChunk::extract(int offset, int length) const
2470 {
2471 RTLIL::SigChunk ret;
2472 if (wire) {
2473 ret.wire = wire;
2474 ret.offset = this->offset + offset;
2475 ret.width = length;
2476 } else {
2477 for (int i = 0; i < length; i++)
2478 ret.data.push_back(data[offset+i]);
2479 ret.width = length;
2480 }
2481 return ret;
2482 }
2483
2484 bool RTLIL::SigChunk::operator <(const RTLIL::SigChunk &other) const
2485 {
2486 if (wire && other.wire)
2487 if (wire->name != other.wire->name)
2488 return wire->name < other.wire->name;
2489
2490 if (wire != other.wire)
2491 return wire < other.wire;
2492
2493 if (offset != other.offset)
2494 return offset < other.offset;
2495
2496 if (width != other.width)
2497 return width < other.width;
2498
2499 return data < other.data;
2500 }
2501
2502 bool RTLIL::SigChunk::operator ==(const RTLIL::SigChunk &other) const
2503 {
2504 return wire == other.wire && width == other.width && offset == other.offset && data == other.data;
2505 }
2506
2507 bool RTLIL::SigChunk::operator !=(const RTLIL::SigChunk &other) const
2508 {
2509 if (*this == other)
2510 return false;
2511 return true;
2512 }
2513
2514 RTLIL::SigSpec::SigSpec()
2515 {
2516 width_ = 0;
2517 hash_ = 0;
2518 }
2519
2520 RTLIL::SigSpec::SigSpec(const RTLIL::SigSpec &other)
2521 {
2522 *this = other;
2523 }
2524
2525 RTLIL::SigSpec::SigSpec(std::initializer_list<RTLIL::SigSpec> parts)
2526 {
2527 cover("kernel.rtlil.sigspec.init.list");
2528
2529 width_ = 0;
2530 hash_ = 0;
2531
2532 std::vector<RTLIL::SigSpec> parts_vec(parts.begin(), parts.end());
2533 for (auto it = parts_vec.rbegin(); it != parts_vec.rend(); it++)
2534 append(*it);
2535 }
2536
2537 const RTLIL::SigSpec &RTLIL::SigSpec::operator=(const RTLIL::SigSpec &other)
2538 {
2539 cover("kernel.rtlil.sigspec.assign");
2540
2541 width_ = other.width_;
2542 hash_ = other.hash_;
2543 chunks_ = other.chunks_;
2544 bits_.clear();
2545
2546 if (!other.bits_.empty())
2547 {
2548 RTLIL::SigChunk *last = NULL;
2549 int last_end_offset = 0;
2550
2551 for (auto &bit : other.bits_) {
2552 if (last && bit.wire == last->wire) {
2553 if (bit.wire == NULL) {
2554 last->data.push_back(bit.data);
2555 last->width++;
2556 continue;
2557 } else if (last_end_offset == bit.offset) {
2558 last_end_offset++;
2559 last->width++;
2560 continue;
2561 }
2562 }
2563 chunks_.push_back(bit);
2564 last = &chunks_.back();
2565 last_end_offset = bit.offset + 1;
2566 }
2567
2568 check();
2569 }
2570
2571 return *this;
2572 }
2573
2574 RTLIL::SigSpec::SigSpec(const RTLIL::Const &value)
2575 {
2576 cover("kernel.rtlil.sigspec.init.const");
2577
2578 chunks_.push_back(RTLIL::SigChunk(value));
2579 width_ = chunks_.back().width;
2580 hash_ = 0;
2581 check();
2582 }
2583
2584 RTLIL::SigSpec::SigSpec(const RTLIL::SigChunk &chunk)
2585 {
2586 cover("kernel.rtlil.sigspec.init.chunk");
2587
2588 chunks_.push_back(chunk);
2589 width_ = chunks_.back().width;
2590 hash_ = 0;
2591 check();
2592 }
2593
2594 RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire)
2595 {
2596 cover("kernel.rtlil.sigspec.init.wire");
2597
2598 chunks_.push_back(RTLIL::SigChunk(wire));
2599 width_ = chunks_.back().width;
2600 hash_ = 0;
2601 check();
2602 }
2603
2604 RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire, int offset, int width)
2605 {
2606 cover("kernel.rtlil.sigspec.init.wire_part");
2607
2608 chunks_.push_back(RTLIL::SigChunk(wire, offset, width));
2609 width_ = chunks_.back().width;
2610 hash_ = 0;
2611 check();
2612 }
2613
2614 RTLIL::SigSpec::SigSpec(const std::string &str)
2615 {
2616 cover("kernel.rtlil.sigspec.init.str");
2617
2618 chunks_.push_back(RTLIL::SigChunk(str));
2619 width_ = chunks_.back().width;
2620 hash_ = 0;
2621 check();
2622 }
2623
2624 RTLIL::SigSpec::SigSpec(int val, int width)
2625 {
2626 cover("kernel.rtlil.sigspec.init.int");
2627
2628 chunks_.push_back(RTLIL::SigChunk(val, width));
2629 width_ = width;
2630 hash_ = 0;
2631 check();
2632 }
2633
2634 RTLIL::SigSpec::SigSpec(RTLIL::State bit, int width)
2635 {
2636 cover("kernel.rtlil.sigspec.init.state");
2637
2638 chunks_.push_back(RTLIL::SigChunk(bit, width));
2639 width_ = width;
2640 hash_ = 0;
2641 check();
2642 }
2643
2644 RTLIL::SigSpec::SigSpec(RTLIL::SigBit bit, int width)
2645 {
2646 cover("kernel.rtlil.sigspec.init.bit");
2647
2648 if (bit.wire == NULL)
2649 chunks_.push_back(RTLIL::SigChunk(bit.data, width));
2650 else
2651 for (int i = 0; i < width; i++)
2652 chunks_.push_back(bit);
2653 width_ = width;
2654 hash_ = 0;
2655 check();
2656 }
2657
2658 RTLIL::SigSpec::SigSpec(std::vector<RTLIL::SigChunk> chunks)
2659 {
2660 cover("kernel.rtlil.sigspec.init.stdvec_chunks");
2661
2662 width_ = 0;
2663 hash_ = 0;
2664 for (auto &c : chunks)
2665 append(c);
2666 check();
2667 }
2668
2669 RTLIL::SigSpec::SigSpec(std::vector<RTLIL::SigBit> bits)
2670 {
2671 cover("kernel.rtlil.sigspec.init.stdvec_bits");
2672
2673 width_ = 0;
2674 hash_ = 0;
2675 for (auto &bit : bits)
2676 append_bit(bit);
2677 check();
2678 }
2679
2680 RTLIL::SigSpec::SigSpec(pool<RTLIL::SigBit> bits)
2681 {
2682 cover("kernel.rtlil.sigspec.init.pool_bits");
2683
2684 width_ = 0;
2685 hash_ = 0;
2686 for (auto &bit : bits)
2687 append_bit(bit);
2688 check();
2689 }
2690
2691 RTLIL::SigSpec::SigSpec(std::set<RTLIL::SigBit> bits)
2692 {
2693 cover("kernel.rtlil.sigspec.init.stdset_bits");
2694
2695 width_ = 0;
2696 hash_ = 0;
2697 for (auto &bit : bits)
2698 append_bit(bit);
2699 check();
2700 }
2701
2702 RTLIL::SigSpec::SigSpec(bool bit)
2703 {
2704 cover("kernel.rtlil.sigspec.init.bool");
2705
2706 width_ = 0;
2707 hash_ = 0;
2708 append_bit(bit);
2709 check();
2710 }
2711
2712 void RTLIL::SigSpec::pack() const
2713 {
2714 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
2715
2716 if (that->bits_.empty())
2717 return;
2718
2719 cover("kernel.rtlil.sigspec.convert.pack");
2720 log_assert(that->chunks_.empty());
2721
2722 std::vector<RTLIL::SigBit> old_bits;
2723 old_bits.swap(that->bits_);
2724
2725 RTLIL::SigChunk *last = NULL;
2726 int last_end_offset = 0;
2727
2728 for (auto &bit : old_bits) {
2729 if (last && bit.wire == last->wire) {
2730 if (bit.wire == NULL) {
2731 last->data.push_back(bit.data);
2732 last->width++;
2733 continue;
2734 } else if (last_end_offset == bit.offset) {
2735 last_end_offset++;
2736 last->width++;
2737 continue;
2738 }
2739 }
2740 that->chunks_.push_back(bit);
2741 last = &that->chunks_.back();
2742 last_end_offset = bit.offset + 1;
2743 }
2744
2745 check();
2746 }
2747
2748 void RTLIL::SigSpec::unpack() const
2749 {
2750 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
2751
2752 if (that->chunks_.empty())
2753 return;
2754
2755 cover("kernel.rtlil.sigspec.convert.unpack");
2756 log_assert(that->bits_.empty());
2757
2758 that->bits_.reserve(that->width_);
2759 for (auto &c : that->chunks_)
2760 for (int i = 0; i < c.width; i++)
2761 that->bits_.push_back(RTLIL::SigBit(c, i));
2762
2763 that->chunks_.clear();
2764 that->hash_ = 0;
2765 }
2766
2767 void RTLIL::SigSpec::updhash() const
2768 {
2769 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
2770
2771 if (that->hash_ != 0)
2772 return;
2773
2774 cover("kernel.rtlil.sigspec.hash");
2775 that->pack();
2776
2777 that->hash_ = mkhash_init;
2778 for (auto &c : that->chunks_)
2779 if (c.wire == NULL) {
2780 for (auto &v : c.data)
2781 that->hash_ = mkhash(that->hash_, v);
2782 } else {
2783 that->hash_ = mkhash(that->hash_, c.wire->name.index_);
2784 that->hash_ = mkhash(that->hash_, c.offset);
2785 that->hash_ = mkhash(that->hash_, c.width);
2786 }
2787
2788 if (that->hash_ == 0)
2789 that->hash_ = 1;
2790 }
2791
2792 void RTLIL::SigSpec::sort()
2793 {
2794 unpack();
2795 cover("kernel.rtlil.sigspec.sort");
2796 std::sort(bits_.begin(), bits_.end());
2797 }
2798
2799 void RTLIL::SigSpec::sort_and_unify()
2800 {
2801 unpack();
2802 cover("kernel.rtlil.sigspec.sort_and_unify");
2803
2804 // A copy of the bits vector is used to prevent duplicating the logic from
2805 // SigSpec::SigSpec(std::vector<SigBit>). This incurrs an extra copy but
2806 // that isn't showing up as significant in profiles.
2807 std::vector<SigBit> unique_bits = bits_;
2808 std::sort(unique_bits.begin(), unique_bits.end());
2809 auto last = std::unique(unique_bits.begin(), unique_bits.end());
2810 unique_bits.erase(last, unique_bits.end());
2811
2812 *this = unique_bits;
2813 }
2814
2815 void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with)
2816 {
2817 replace(pattern, with, this);
2818 }
2819
2820 void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with, RTLIL::SigSpec *other) const
2821 {
2822 log_assert(other != NULL);
2823 log_assert(width_ == other->width_);
2824 log_assert(pattern.width_ == with.width_);
2825
2826 pattern.unpack();
2827 with.unpack();
2828 unpack();
2829 other->unpack();
2830
2831 for (int i = 0; i < GetSize(pattern.bits_); i++) {
2832 if (pattern.bits_[i].wire != NULL) {
2833 for (int j = 0; j < GetSize(bits_); j++) {
2834 if (bits_[j] == pattern.bits_[i]) {
2835 other->bits_[j] = with.bits_[i];
2836 }
2837 }
2838 }
2839 }
2840
2841 other->check();
2842 }
2843
2844 void RTLIL::SigSpec::replace(const dict<RTLIL::SigBit, RTLIL::SigBit> &rules)
2845 {
2846 replace(rules, this);
2847 }
2848
2849 void RTLIL::SigSpec::replace(const dict<RTLIL::SigBit, RTLIL::SigBit> &rules, RTLIL::SigSpec *other) const
2850 {
2851 cover("kernel.rtlil.sigspec.replace_dict");
2852
2853 log_assert(other != NULL);
2854 log_assert(width_ == other->width_);
2855
2856 unpack();
2857 other->unpack();
2858
2859 for (int i = 0; i < GetSize(bits_); i++) {
2860 auto it = rules.find(bits_[i]);
2861 if (it != rules.end())
2862 other->bits_[i] = it->second;
2863 }
2864
2865 other->check();
2866 }
2867
2868 void RTLIL::SigSpec::replace(const std::map<RTLIL::SigBit, RTLIL::SigBit> &rules)
2869 {
2870 replace(rules, this);
2871 }
2872
2873 void RTLIL::SigSpec::replace(const std::map<RTLIL::SigBit, RTLIL::SigBit> &rules, RTLIL::SigSpec *other) const
2874 {
2875 cover("kernel.rtlil.sigspec.replace_map");
2876
2877 log_assert(other != NULL);
2878 log_assert(width_ == other->width_);
2879
2880 unpack();
2881 other->unpack();
2882
2883 for (int i = 0; i < GetSize(bits_); i++) {
2884 auto it = rules.find(bits_[i]);
2885 if (it != rules.end())
2886 other->bits_[i] = it->second;
2887 }
2888
2889 other->check();
2890 }
2891
2892 void RTLIL::SigSpec::remove(const RTLIL::SigSpec &pattern)
2893 {
2894 remove2(pattern, NULL);
2895 }
2896
2897 void RTLIL::SigSpec::remove(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other) const
2898 {
2899 RTLIL::SigSpec tmp = *this;
2900 tmp.remove2(pattern, other);
2901 }
2902
2903 void RTLIL::SigSpec::remove2(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other)
2904 {
2905 if (other)
2906 cover("kernel.rtlil.sigspec.remove_other");
2907 else
2908 cover("kernel.rtlil.sigspec.remove");
2909
2910 unpack();
2911 if (other != NULL) {
2912 log_assert(width_ == other->width_);
2913 other->unpack();
2914 }
2915
2916 for (int i = GetSize(bits_) - 1; i >= 0; i--)
2917 {
2918 if (bits_[i].wire == NULL) continue;
2919
2920 for (auto &pattern_chunk : pattern.chunks())
2921 if (bits_[i].wire == pattern_chunk.wire &&
2922 bits_[i].offset >= pattern_chunk.offset &&
2923 bits_[i].offset < pattern_chunk.offset + pattern_chunk.width) {
2924 bits_.erase(bits_.begin() + i);
2925 width_--;
2926 if (other != NULL) {
2927 other->bits_.erase(other->bits_.begin() + i);
2928 other->width_--;
2929 }
2930 break;
2931 }
2932 }
2933
2934 check();
2935 }
2936
2937 void RTLIL::SigSpec::remove(const pool<RTLIL::SigBit> &pattern)
2938 {
2939 remove2(pattern, NULL);
2940 }
2941
2942 void RTLIL::SigSpec::remove(const pool<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other) const
2943 {
2944 RTLIL::SigSpec tmp = *this;
2945 tmp.remove2(pattern, other);
2946 }
2947
2948 void RTLIL::SigSpec::remove2(const pool<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other)
2949 {
2950 if (other)
2951 cover("kernel.rtlil.sigspec.remove_other");
2952 else
2953 cover("kernel.rtlil.sigspec.remove");
2954
2955 unpack();
2956
2957 if (other != NULL) {
2958 log_assert(width_ == other->width_);
2959 other->unpack();
2960 }
2961
2962 for (int i = GetSize(bits_) - 1; i >= 0; i--) {
2963 if (bits_[i].wire != NULL && pattern.count(bits_[i])) {
2964 bits_.erase(bits_.begin() + i);
2965 width_--;
2966 if (other != NULL) {
2967 other->bits_.erase(other->bits_.begin() + i);
2968 other->width_--;
2969 }
2970 }
2971 }
2972
2973 check();
2974 }
2975
2976 void RTLIL::SigSpec::remove2(const std::set<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other)
2977 {
2978 if (other)
2979 cover("kernel.rtlil.sigspec.remove_other");
2980 else
2981 cover("kernel.rtlil.sigspec.remove");
2982
2983 unpack();
2984
2985 if (other != NULL) {
2986 log_assert(width_ == other->width_);
2987 other->unpack();
2988 }
2989
2990 for (int i = GetSize(bits_) - 1; i >= 0; i--) {
2991 if (bits_[i].wire != NULL && pattern.count(bits_[i])) {
2992 bits_.erase(bits_.begin() + i);
2993 width_--;
2994 if (other != NULL) {
2995 other->bits_.erase(other->bits_.begin() + i);
2996 other->width_--;
2997 }
2998 }
2999 }
3000
3001 check();
3002 }
3003
3004 RTLIL::SigSpec RTLIL::SigSpec::extract(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec *other) const
3005 {
3006 if (other)
3007 cover("kernel.rtlil.sigspec.extract_other");
3008 else
3009 cover("kernel.rtlil.sigspec.extract");
3010
3011 log_assert(other == NULL || width_ == other->width_);
3012
3013 RTLIL::SigSpec ret;
3014 std::vector<RTLIL::SigBit> bits_match = to_sigbit_vector();
3015
3016 for (auto& pattern_chunk : pattern.chunks()) {
3017 if (other) {
3018 std::vector<RTLIL::SigBit> bits_other = other->to_sigbit_vector();
3019 for (int i = 0; i < width_; i++)
3020 if (bits_match[i].wire &&
3021 bits_match[i].wire == pattern_chunk.wire &&
3022 bits_match[i].offset >= pattern_chunk.offset &&
3023 bits_match[i].offset < pattern_chunk.offset + pattern_chunk.width)
3024 ret.append_bit(bits_other[i]);
3025 } else {
3026 for (int i = 0; i < width_; i++)
3027 if (bits_match[i].wire &&
3028 bits_match[i].wire == pattern_chunk.wire &&
3029 bits_match[i].offset >= pattern_chunk.offset &&
3030 bits_match[i].offset < pattern_chunk.offset + pattern_chunk.width)
3031 ret.append_bit(bits_match[i]);
3032 }
3033 }
3034
3035 ret.check();
3036 return ret;
3037 }
3038
3039 RTLIL::SigSpec RTLIL::SigSpec::extract(const pool<RTLIL::SigBit> &pattern, const RTLIL::SigSpec *other) const
3040 {
3041 if (other)
3042 cover("kernel.rtlil.sigspec.extract_other");
3043 else
3044 cover("kernel.rtlil.sigspec.extract");
3045
3046 log_assert(other == NULL || width_ == other->width_);
3047
3048 std::vector<RTLIL::SigBit> bits_match = to_sigbit_vector();
3049 RTLIL::SigSpec ret;
3050
3051 if (other) {
3052 std::vector<RTLIL::SigBit> bits_other = other->to_sigbit_vector();
3053 for (int i = 0; i < width_; i++)
3054 if (bits_match[i].wire && pattern.count(bits_match[i]))
3055 ret.append_bit(bits_other[i]);
3056 } else {
3057 for (int i = 0; i < width_; i++)
3058 if (bits_match[i].wire && pattern.count(bits_match[i]))
3059 ret.append_bit(bits_match[i]);
3060 }
3061
3062 ret.check();
3063 return ret;
3064 }
3065
3066 void RTLIL::SigSpec::replace(int offset, const RTLIL::SigSpec &with)
3067 {
3068 cover("kernel.rtlil.sigspec.replace_pos");
3069
3070 unpack();
3071 with.unpack();
3072
3073 log_assert(offset >= 0);
3074 log_assert(with.width_ >= 0);
3075 log_assert(offset+with.width_ <= width_);
3076
3077 for (int i = 0; i < with.width_; i++)
3078 bits_.at(offset + i) = with.bits_.at(i);
3079
3080 check();
3081 }
3082
3083 void RTLIL::SigSpec::remove_const()
3084 {
3085 if (packed())
3086 {
3087 cover("kernel.rtlil.sigspec.remove_const.packed");
3088
3089 std::vector<RTLIL::SigChunk> new_chunks;
3090 new_chunks.reserve(GetSize(chunks_));
3091
3092 width_ = 0;
3093 for (auto &chunk : chunks_)
3094 if (chunk.wire != NULL) {
3095 new_chunks.push_back(chunk);
3096 width_ += chunk.width;
3097 }
3098
3099 chunks_.swap(new_chunks);
3100 }
3101 else
3102 {
3103 cover("kernel.rtlil.sigspec.remove_const.unpacked");
3104
3105 std::vector<RTLIL::SigBit> new_bits;
3106 new_bits.reserve(width_);
3107
3108 for (auto &bit : bits_)
3109 if (bit.wire != NULL)
3110 new_bits.push_back(bit);
3111
3112 bits_.swap(new_bits);
3113 width_ = bits_.size();
3114 }
3115
3116 check();
3117 }
3118
3119 void RTLIL::SigSpec::remove(int offset, int length)
3120 {
3121 cover("kernel.rtlil.sigspec.remove_pos");
3122
3123 unpack();
3124
3125 log_assert(offset >= 0);
3126 log_assert(length >= 0);
3127 log_assert(offset + length <= width_);
3128
3129 bits_.erase(bits_.begin() + offset, bits_.begin() + offset + length);
3130 width_ = bits_.size();
3131
3132 check();
3133 }
3134
3135 RTLIL::SigSpec RTLIL::SigSpec::extract(int offset, int length) const
3136 {
3137 unpack();
3138 cover("kernel.rtlil.sigspec.extract_pos");
3139 return std::vector<RTLIL::SigBit>(bits_.begin() + offset, bits_.begin() + offset + length);
3140 }
3141
3142 void RTLIL::SigSpec::append(const RTLIL::SigSpec &signal)
3143 {
3144 if (signal.width_ == 0)
3145 return;
3146
3147 if (width_ == 0) {
3148 *this = signal;
3149 return;
3150 }
3151
3152 cover("kernel.rtlil.sigspec.append");
3153
3154 if (packed() != signal.packed()) {
3155 pack();
3156 signal.pack();
3157 }
3158
3159 if (packed())
3160 for (auto &other_c : signal.chunks_)
3161 {
3162 auto &my_last_c = chunks_.back();
3163 if (my_last_c.wire == NULL && other_c.wire == NULL) {
3164 auto &this_data = my_last_c.data;
3165 auto &other_data = other_c.data;
3166 this_data.insert(this_data.end(), other_data.begin(), other_data.end());
3167 my_last_c.width += other_c.width;
3168 } else
3169 if (my_last_c.wire == other_c.wire && my_last_c.offset + my_last_c.width == other_c.offset) {
3170 my_last_c.width += other_c.width;
3171 } else
3172 chunks_.push_back(other_c);
3173 }
3174 else
3175 bits_.insert(bits_.end(), signal.bits_.begin(), signal.bits_.end());
3176
3177 width_ += signal.width_;
3178 check();
3179 }
3180
3181 void RTLIL::SigSpec::append_bit(const RTLIL::SigBit &bit)
3182 {
3183 if (packed())
3184 {
3185 cover("kernel.rtlil.sigspec.append_bit.packed");
3186
3187 if (chunks_.size() == 0)
3188 chunks_.push_back(bit);
3189 else
3190 if (bit.wire == NULL)
3191 if (chunks_.back().wire == NULL) {
3192 chunks_.back().data.push_back(bit.data);
3193 chunks_.back().width++;
3194 } else
3195 chunks_.push_back(bit);
3196 else
3197 if (chunks_.back().wire == bit.wire && chunks_.back().offset + chunks_.back().width == bit.offset)
3198 chunks_.back().width++;
3199 else
3200 chunks_.push_back(bit);
3201 }
3202 else
3203 {
3204 cover("kernel.rtlil.sigspec.append_bit.unpacked");
3205 bits_.push_back(bit);
3206 }
3207
3208 width_++;
3209 check();
3210 }
3211
3212 void RTLIL::SigSpec::extend_u0(int width, bool is_signed)
3213 {
3214 cover("kernel.rtlil.sigspec.extend_u0");
3215
3216 pack();
3217
3218 if (width_ > width)
3219 remove(width, width_ - width);
3220
3221 if (width_ < width) {
3222 RTLIL::SigBit padding = width_ > 0 ? (*this)[width_ - 1] : RTLIL::State::S0;
3223 if (!is_signed)
3224 padding = RTLIL::State::S0;
3225 while (width_ < width)
3226 append(padding);
3227 }
3228
3229 }
3230
3231 RTLIL::SigSpec RTLIL::SigSpec::repeat(int num) const
3232 {
3233 cover("kernel.rtlil.sigspec.repeat");
3234
3235 RTLIL::SigSpec sig;
3236 for (int i = 0; i < num; i++)
3237 sig.append(*this);
3238 return sig;
3239 }
3240
3241 #ifndef NDEBUG
3242 void RTLIL::SigSpec::check() const
3243 {
3244 if (width_ > 64)
3245 {
3246 cover("kernel.rtlil.sigspec.check.skip");
3247 }
3248 else if (packed())
3249 {
3250 cover("kernel.rtlil.sigspec.check.packed");
3251
3252 int w = 0;
3253 for (size_t i = 0; i < chunks_.size(); i++) {
3254 const RTLIL::SigChunk chunk = chunks_[i];
3255 if (chunk.wire == NULL) {
3256 if (i > 0)
3257 log_assert(chunks_[i-1].wire != NULL);
3258 log_assert(chunk.offset == 0);
3259 log_assert(chunk.data.size() == (size_t)chunk.width);
3260 } else {
3261 if (i > 0 && chunks_[i-1].wire == chunk.wire)
3262 log_assert(chunk.offset != chunks_[i-1].offset + chunks_[i-1].width);
3263 log_assert(chunk.offset >= 0);
3264 log_assert(chunk.width >= 0);
3265 log_assert(chunk.offset + chunk.width <= chunk.wire->width);
3266 log_assert(chunk.data.size() == 0);
3267 }
3268 w += chunk.width;
3269 }
3270 log_assert(w == width_);
3271 log_assert(bits_.empty());
3272 }
3273 else
3274 {
3275 cover("kernel.rtlil.sigspec.check.unpacked");
3276
3277 log_assert(width_ == GetSize(bits_));
3278 log_assert(chunks_.empty());
3279 }
3280 }
3281 #endif
3282
3283 bool RTLIL::SigSpec::operator <(const RTLIL::SigSpec &other) const
3284 {
3285 cover("kernel.rtlil.sigspec.comp_lt");
3286
3287 if (this == &other)
3288 return false;
3289
3290 if (width_ != other.width_)
3291 return width_ < other.width_;
3292
3293 pack();
3294 other.pack();
3295
3296 if (chunks_.size() != other.chunks_.size())
3297 return chunks_.size() < other.chunks_.size();
3298
3299 updhash();
3300 other.updhash();
3301
3302 if (hash_ != other.hash_)
3303 return hash_ < other.hash_;
3304
3305 for (size_t i = 0; i < chunks_.size(); i++)
3306 if (chunks_[i] != other.chunks_[i]) {
3307 cover("kernel.rtlil.sigspec.comp_lt.hash_collision");
3308 return chunks_[i] < other.chunks_[i];
3309 }
3310
3311 cover("kernel.rtlil.sigspec.comp_lt.equal");
3312 return false;
3313 }
3314
3315 bool RTLIL::SigSpec::operator ==(const RTLIL::SigSpec &other) const
3316 {
3317 cover("kernel.rtlil.sigspec.comp_eq");
3318
3319 if (this == &other)
3320 return true;
3321
3322 if (width_ != other.width_)
3323 return false;
3324
3325 pack();
3326 other.pack();
3327
3328 if (chunks_.size() != chunks_.size())
3329 return false;
3330
3331 updhash();
3332 other.updhash();
3333
3334 if (hash_ != other.hash_)
3335 return false;
3336
3337 for (size_t i = 0; i < chunks_.size(); i++)
3338 if (chunks_[i] != other.chunks_[i]) {
3339 cover("kernel.rtlil.sigspec.comp_eq.hash_collision");
3340 return false;
3341 }
3342
3343 cover("kernel.rtlil.sigspec.comp_eq.equal");
3344 return true;
3345 }
3346
3347 bool RTLIL::SigSpec::is_wire() const
3348 {
3349 cover("kernel.rtlil.sigspec.is_wire");
3350
3351 pack();
3352 return GetSize(chunks_) == 1 && chunks_[0].wire && chunks_[0].wire->width == width_;
3353 }
3354
3355 bool RTLIL::SigSpec::is_chunk() const
3356 {
3357 cover("kernel.rtlil.sigspec.is_chunk");
3358
3359 pack();
3360 return GetSize(chunks_) == 1;
3361 }
3362
3363 bool RTLIL::SigSpec::is_fully_const() const
3364 {
3365 cover("kernel.rtlil.sigspec.is_fully_const");
3366
3367 pack();
3368 for (auto it = chunks_.begin(); it != chunks_.end(); it++)
3369 if (it->width > 0 && it->wire != NULL)
3370 return false;
3371 return true;
3372 }
3373
3374 bool RTLIL::SigSpec::is_fully_zero() const
3375 {
3376 cover("kernel.rtlil.sigspec.is_fully_zero");
3377
3378 pack();
3379 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
3380 if (it->width > 0 && it->wire != NULL)
3381 return false;
3382 for (size_t i = 0; i < it->data.size(); i++)
3383 if (it->data[i] != RTLIL::State::S0)
3384 return false;
3385 }
3386 return true;
3387 }
3388
3389 bool RTLIL::SigSpec::is_fully_ones() const
3390 {
3391 cover("kernel.rtlil.sigspec.is_fully_ones");
3392
3393 pack();
3394 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
3395 if (it->width > 0 && it->wire != NULL)
3396 return false;
3397 for (size_t i = 0; i < it->data.size(); i++)
3398 if (it->data[i] != RTLIL::State::S1)
3399 return false;
3400 }
3401 return true;
3402 }
3403
3404 bool RTLIL::SigSpec::is_fully_def() const
3405 {
3406 cover("kernel.rtlil.sigspec.is_fully_def");
3407
3408 pack();
3409 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
3410 if (it->width > 0 && it->wire != NULL)
3411 return false;
3412 for (size_t i = 0; i < it->data.size(); i++)
3413 if (it->data[i] != RTLIL::State::S0 && it->data[i] != RTLIL::State::S1)
3414 return false;
3415 }
3416 return true;
3417 }
3418
3419 bool RTLIL::SigSpec::is_fully_undef() const
3420 {
3421 cover("kernel.rtlil.sigspec.is_fully_undef");
3422
3423 pack();
3424 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
3425 if (it->width > 0 && it->wire != NULL)
3426 return false;
3427 for (size_t i = 0; i < it->data.size(); i++)
3428 if (it->data[i] != RTLIL::State::Sx && it->data[i] != RTLIL::State::Sz)
3429 return false;
3430 }
3431 return true;
3432 }
3433
3434 bool RTLIL::SigSpec::has_const() const
3435 {
3436 cover("kernel.rtlil.sigspec.has_const");
3437
3438 pack();
3439 for (auto it = chunks_.begin(); it != chunks_.end(); it++)
3440 if (it->width > 0 && it->wire == NULL)
3441 return true;
3442 return false;
3443 }
3444
3445 bool RTLIL::SigSpec::has_marked_bits() const
3446 {
3447 cover("kernel.rtlil.sigspec.has_marked_bits");
3448
3449 pack();
3450 for (auto it = chunks_.begin(); it != chunks_.end(); it++)
3451 if (it->width > 0 && it->wire == NULL) {
3452 for (size_t i = 0; i < it->data.size(); i++)
3453 if (it->data[i] == RTLIL::State::Sm)
3454 return true;
3455 }
3456 return false;
3457 }
3458
3459 bool RTLIL::SigSpec::as_bool() const
3460 {
3461 cover("kernel.rtlil.sigspec.as_bool");
3462
3463 pack();
3464 log_assert(is_fully_const() && GetSize(chunks_) <= 1);
3465 if (width_)
3466 return RTLIL::Const(chunks_[0].data).as_bool();
3467 return false;
3468 }
3469
3470 int RTLIL::SigSpec::as_int(bool is_signed) const
3471 {
3472 cover("kernel.rtlil.sigspec.as_int");
3473
3474 pack();
3475 log_assert(is_fully_const() && GetSize(chunks_) <= 1);
3476 if (width_)
3477 return RTLIL::Const(chunks_[0].data).as_int(is_signed);
3478 return 0;
3479 }
3480
3481 std::string RTLIL::SigSpec::as_string() const
3482 {
3483 cover("kernel.rtlil.sigspec.as_string");
3484
3485 pack();
3486 std::string str;
3487 for (size_t i = chunks_.size(); i > 0; i--) {
3488 const RTLIL::SigChunk &chunk = chunks_[i-1];
3489 if (chunk.wire != NULL)
3490 for (int j = 0; j < chunk.width; j++)
3491 str += "?";
3492 else
3493 str += RTLIL::Const(chunk.data).as_string();
3494 }
3495 return str;
3496 }
3497
3498 RTLIL::Const RTLIL::SigSpec::as_const() const
3499 {
3500 cover("kernel.rtlil.sigspec.as_const");
3501
3502 pack();
3503 log_assert(is_fully_const() && GetSize(chunks_) <= 1);
3504 if (width_)
3505 return chunks_[0].data;
3506 return RTLIL::Const();
3507 }
3508
3509 RTLIL::Wire *RTLIL::SigSpec::as_wire() const
3510 {
3511 cover("kernel.rtlil.sigspec.as_wire");
3512
3513 pack();
3514 log_assert(is_wire());
3515 return chunks_[0].wire;
3516 }
3517
3518 RTLIL::SigChunk RTLIL::SigSpec::as_chunk() const
3519 {
3520 cover("kernel.rtlil.sigspec.as_chunk");
3521
3522 pack();
3523 log_assert(is_chunk());
3524 return chunks_[0];
3525 }
3526
3527 RTLIL::SigBit RTLIL::SigSpec::as_bit() const
3528 {
3529 cover("kernel.rtlil.sigspec.as_bit");
3530
3531 log_assert(width_ == 1);
3532 if (packed())
3533 return RTLIL::SigBit(*chunks_.begin());
3534 else
3535 return bits_[0];
3536 }
3537
3538 bool RTLIL::SigSpec::match(std::string pattern) const
3539 {
3540 cover("kernel.rtlil.sigspec.match");
3541
3542 pack();
3543 std::string str = as_string();
3544 log_assert(pattern.size() == str.size());
3545
3546 for (size_t i = 0; i < pattern.size(); i++) {
3547 if (pattern[i] == ' ')
3548 continue;
3549 if (pattern[i] == '*') {
3550 if (str[i] != 'z' && str[i] != 'x')
3551 return false;
3552 continue;
3553 }
3554 if (pattern[i] != str[i])
3555 return false;
3556 }
3557
3558 return true;
3559 }
3560
3561 std::set<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_set() const
3562 {
3563 cover("kernel.rtlil.sigspec.to_sigbit_set");
3564
3565 pack();
3566 std::set<RTLIL::SigBit> sigbits;
3567 for (auto &c : chunks_)
3568 for (int i = 0; i < c.width; i++)
3569 sigbits.insert(RTLIL::SigBit(c, i));
3570 return sigbits;
3571 }
3572
3573 pool<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_pool() const
3574 {
3575 cover("kernel.rtlil.sigspec.to_sigbit_pool");
3576
3577 pack();
3578 pool<RTLIL::SigBit> sigbits;
3579 for (auto &c : chunks_)
3580 for (int i = 0; i < c.width; i++)
3581 sigbits.insert(RTLIL::SigBit(c, i));
3582 return sigbits;
3583 }
3584
3585 std::vector<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_vector() const
3586 {
3587 cover("kernel.rtlil.sigspec.to_sigbit_vector");
3588
3589 unpack();
3590 return bits_;
3591 }
3592
3593 std::map<RTLIL::SigBit, RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_map(const RTLIL::SigSpec &other) const
3594 {
3595 cover("kernel.rtlil.sigspec.to_sigbit_map");
3596
3597 unpack();
3598 other.unpack();
3599
3600 log_assert(width_ == other.width_);
3601
3602 std::map<RTLIL::SigBit, RTLIL::SigBit> new_map;
3603 for (int i = 0; i < width_; i++)
3604 new_map[bits_[i]] = other.bits_[i];
3605
3606 return new_map;
3607 }
3608
3609 dict<RTLIL::SigBit, RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_dict(const RTLIL::SigSpec &other) const
3610 {
3611 cover("kernel.rtlil.sigspec.to_sigbit_dict");
3612
3613 unpack();
3614 other.unpack();
3615
3616 log_assert(width_ == other.width_);
3617
3618 dict<RTLIL::SigBit, RTLIL::SigBit> new_map;
3619 for (int i = 0; i < width_; i++)
3620 new_map[bits_[i]] = other.bits_[i];
3621
3622 return new_map;
3623 }
3624
3625 static void sigspec_parse_split(std::vector<std::string> &tokens, const std::string &text, char sep)
3626 {
3627 size_t start = 0, end = 0;
3628 while ((end = text.find(sep, start)) != std::string::npos) {
3629 tokens.push_back(text.substr(start, end - start));
3630 start = end + 1;
3631 }
3632 tokens.push_back(text.substr(start));
3633 }
3634
3635 static int sigspec_parse_get_dummy_line_num()
3636 {
3637 return 0;
3638 }
3639
3640 bool RTLIL::SigSpec::parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str)
3641 {
3642 cover("kernel.rtlil.sigspec.parse");
3643
3644 AST::current_filename = "input";
3645 AST::use_internal_line_num();
3646 AST::set_line_num(0);
3647
3648 std::vector<std::string> tokens;
3649 sigspec_parse_split(tokens, str, ',');
3650
3651 sig = RTLIL::SigSpec();
3652 for (int tokidx = int(tokens.size())-1; tokidx >= 0; tokidx--)
3653 {
3654 std::string netname = tokens[tokidx];
3655 std::string indices;
3656
3657 if (netname.size() == 0)
3658 continue;
3659
3660 if (('0' <= netname[0] && netname[0] <= '9') || netname[0] == '\'') {
3661 cover("kernel.rtlil.sigspec.parse.const");
3662 AST::get_line_num = sigspec_parse_get_dummy_line_num;
3663 AST::AstNode *ast = VERILOG_FRONTEND::const2ast(netname);
3664 if (ast == NULL)
3665 return false;
3666 sig.append(RTLIL::Const(ast->bits));
3667 delete ast;
3668 continue;
3669 }
3670
3671 if (module == NULL)
3672 return false;
3673
3674 cover("kernel.rtlil.sigspec.parse.net");
3675
3676 if (netname[0] != '$' && netname[0] != '\\')
3677 netname = "\\" + netname;
3678
3679 if (module->wires_.count(netname) == 0) {
3680 size_t indices_pos = netname.size()-1;
3681 if (indices_pos > 2 && netname[indices_pos] == ']')
3682 {
3683 indices_pos--;
3684 while (indices_pos > 0 && ('0' <= netname[indices_pos] && netname[indices_pos] <= '9')) indices_pos--;
3685 if (indices_pos > 0 && netname[indices_pos] == ':') {
3686 indices_pos--;
3687 while (indices_pos > 0 && ('0' <= netname[indices_pos] && netname[indices_pos] <= '9')) indices_pos--;
3688 }
3689 if (indices_pos > 0 && netname[indices_pos] == '[') {
3690 indices = netname.substr(indices_pos);
3691 netname = netname.substr(0, indices_pos);
3692 }
3693 }
3694 }
3695
3696 if (module->wires_.count(netname) == 0)
3697 return false;
3698
3699 RTLIL::Wire *wire = module->wires_.at(netname);
3700 if (!indices.empty()) {
3701 std::vector<std::string> index_tokens;
3702 sigspec_parse_split(index_tokens, indices.substr(1, indices.size()-2), ':');
3703 if (index_tokens.size() == 1) {
3704 cover("kernel.rtlil.sigspec.parse.bit_sel");
3705 int a = atoi(index_tokens.at(0).c_str());
3706 if (a < 0 || a >= wire->width)
3707 return false;
3708 sig.append(RTLIL::SigSpec(wire, a));
3709 } else {
3710 cover("kernel.rtlil.sigspec.parse.part_sel");
3711 int a = atoi(index_tokens.at(0).c_str());
3712 int b = atoi(index_tokens.at(1).c_str());
3713 if (a > b) {
3714 int tmp = a;
3715 a = b, b = tmp;
3716 }
3717 if (a < 0 || a >= wire->width)
3718 return false;
3719 if (b < 0 || b >= wire->width)
3720 return false;
3721 sig.append(RTLIL::SigSpec(wire, a, b-a+1));
3722 }
3723 } else
3724 sig.append(wire);
3725 }
3726
3727 return true;
3728 }
3729
3730 bool RTLIL::SigSpec::parse_sel(RTLIL::SigSpec &sig, RTLIL::Design *design, RTLIL::Module *module, std::string str)
3731 {
3732 if (str.empty() || str[0] != '@')
3733 return parse(sig, module, str);
3734
3735 cover("kernel.rtlil.sigspec.parse.sel");
3736
3737 str = RTLIL::escape_id(str.substr(1));
3738 if (design->selection_vars.count(str) == 0)
3739 return false;
3740
3741 sig = RTLIL::SigSpec();
3742 RTLIL::Selection &sel = design->selection_vars.at(str);
3743 for (auto &it : module->wires_)
3744 if (sel.selected_member(module->name, it.first))
3745 sig.append(it.second);
3746
3747 return true;
3748 }
3749
3750 bool RTLIL::SigSpec::parse_rhs(const RTLIL::SigSpec &lhs, RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str)
3751 {
3752 if (str == "0") {
3753 cover("kernel.rtlil.sigspec.parse.rhs_zeros");
3754 sig = RTLIL::SigSpec(RTLIL::State::S0, lhs.width_);
3755 return true;
3756 }
3757
3758 if (str == "~0") {
3759 cover("kernel.rtlil.sigspec.parse.rhs_ones");
3760 sig = RTLIL::SigSpec(RTLIL::State::S1, lhs.width_);
3761 return true;
3762 }
3763
3764 if (lhs.chunks_.size() == 1) {
3765 char *p = (char*)str.c_str(), *endptr;
3766 long int val = strtol(p, &endptr, 10);
3767 if (endptr && endptr != p && *endptr == 0) {
3768 sig = RTLIL::SigSpec(val, lhs.width_);
3769 cover("kernel.rtlil.sigspec.parse.rhs_dec");
3770 return true;
3771 }
3772 }
3773
3774 return parse(sig, module, str);
3775 }
3776
3777 RTLIL::CaseRule::~CaseRule()
3778 {
3779 for (auto it = switches.begin(); it != switches.end(); it++)
3780 delete *it;
3781 }
3782
3783 RTLIL::CaseRule *RTLIL::CaseRule::clone() const
3784 {
3785 RTLIL::CaseRule *new_caserule = new RTLIL::CaseRule;
3786 new_caserule->compare = compare;
3787 new_caserule->actions = actions;
3788 for (auto &it : switches)
3789 new_caserule->switches.push_back(it->clone());
3790 return new_caserule;
3791 }
3792
3793 RTLIL::SwitchRule::~SwitchRule()
3794 {
3795 for (auto it = cases.begin(); it != cases.end(); it++)
3796 delete *it;
3797 }
3798
3799 RTLIL::SwitchRule *RTLIL::SwitchRule::clone() const
3800 {
3801 RTLIL::SwitchRule *new_switchrule = new RTLIL::SwitchRule;
3802 new_switchrule->signal = signal;
3803 new_switchrule->attributes = attributes;
3804 for (auto &it : cases)
3805 new_switchrule->cases.push_back(it->clone());
3806 return new_switchrule;
3807
3808 }
3809
3810 RTLIL::SyncRule *RTLIL::SyncRule::clone() const
3811 {
3812 RTLIL::SyncRule *new_syncrule = new RTLIL::SyncRule;
3813 new_syncrule->type = type;
3814 new_syncrule->signal = signal;
3815 new_syncrule->actions = actions;
3816 return new_syncrule;
3817 }
3818
3819 RTLIL::Process::~Process()
3820 {
3821 for (auto it = syncs.begin(); it != syncs.end(); it++)
3822 delete *it;
3823 }
3824
3825 RTLIL::Process *RTLIL::Process::clone() const
3826 {
3827 RTLIL::Process *new_proc = new RTLIL::Process;
3828
3829 new_proc->name = name;
3830 new_proc->attributes = attributes;
3831
3832 RTLIL::CaseRule *rc_ptr = root_case.clone();
3833 new_proc->root_case = *rc_ptr;
3834 rc_ptr->switches.clear();
3835 delete rc_ptr;
3836
3837 for (auto &it : syncs)
3838 new_proc->syncs.push_back(it->clone());
3839
3840 return new_proc;
3841 }
3842
3843 YOSYS_NAMESPACE_END
3844