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Merge remote-tracking branch 'origin/master' into eddie/abc9_dsp_refactor
[yosys.git] / kernel / rtlil.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 #include "kernel/yosys.h"
21 #include "kernel/macc.h"
22 #include "kernel/celltypes.h"
23 #include "frontends/verilog/verilog_frontend.h"
24 #include "backends/ilang/ilang_backend.h"
25
26 #include <string.h>
27 #include <algorithm>
28
29 YOSYS_NAMESPACE_BEGIN
30
31 RTLIL::IdString::destruct_guard_t RTLIL::IdString::destruct_guard;
32 std::vector<char*> RTLIL::IdString::global_id_storage_;
33 dict<char*, int, hash_cstr_ops> RTLIL::IdString::global_id_index_;
34 #ifndef YOSYS_NO_IDS_REFCNT
35 std::vector<int> RTLIL::IdString::global_refcount_storage_;
36 std::vector<int> RTLIL::IdString::global_free_idx_list_;
37 #endif
38 #ifdef YOSYS_USE_STICKY_IDS
39 int RTLIL::IdString::last_created_idx_[8];
40 int RTLIL::IdString::last_created_idx_ptr_;
41 #endif
42
43 IdString RTLIL::ID::A;
44 IdString RTLIL::ID::B;
45 IdString RTLIL::ID::Y;
46 IdString RTLIL::ID::keep;
47 IdString RTLIL::ID::whitebox;
48 IdString RTLIL::ID::blackbox;
49
50 RTLIL::Const::Const()
51 {
52 flags = RTLIL::CONST_FLAG_NONE;
53 }
54
55 RTLIL::Const::Const(std::string str)
56 {
57 flags = RTLIL::CONST_FLAG_STRING;
58 for (int i = str.size()-1; i >= 0; i--) {
59 unsigned char ch = str[i];
60 for (int j = 0; j < 8; j++) {
61 bits.push_back((ch & 1) != 0 ? State::S1 : State::S0);
62 ch = ch >> 1;
63 }
64 }
65 }
66
67 RTLIL::Const::Const(int val, int width)
68 {
69 flags = RTLIL::CONST_FLAG_NONE;
70 for (int i = 0; i < width; i++) {
71 bits.push_back((val & 1) != 0 ? State::S1 : State::S0);
72 val = val >> 1;
73 }
74 }
75
76 RTLIL::Const::Const(RTLIL::State bit, int width)
77 {
78 flags = RTLIL::CONST_FLAG_NONE;
79 for (int i = 0; i < width; i++)
80 bits.push_back(bit);
81 }
82
83 RTLIL::Const::Const(const std::vector<bool> &bits)
84 {
85 flags = RTLIL::CONST_FLAG_NONE;
86 for (auto b : bits)
87 this->bits.push_back(b ? State::S1 : State::S0);
88 }
89
90 RTLIL::Const::Const(const RTLIL::Const &c)
91 {
92 flags = c.flags;
93 for (auto b : c.bits)
94 this->bits.push_back(b);
95 }
96
97 bool RTLIL::Const::operator <(const RTLIL::Const &other) const
98 {
99 if (bits.size() != other.bits.size())
100 return bits.size() < other.bits.size();
101 for (size_t i = 0; i < bits.size(); i++)
102 if (bits[i] != other.bits[i])
103 return bits[i] < other.bits[i];
104 return false;
105 }
106
107 bool RTLIL::Const::operator ==(const RTLIL::Const &other) const
108 {
109 return bits == other.bits;
110 }
111
112 bool RTLIL::Const::operator !=(const RTLIL::Const &other) const
113 {
114 return bits != other.bits;
115 }
116
117 bool RTLIL::Const::as_bool() const
118 {
119 for (size_t i = 0; i < bits.size(); i++)
120 if (bits[i] == State::S1)
121 return true;
122 return false;
123 }
124
125 int RTLIL::Const::as_int(bool is_signed) const
126 {
127 int32_t ret = 0;
128 for (size_t i = 0; i < bits.size() && i < 32; i++)
129 if (bits[i] == State::S1)
130 ret |= 1 << i;
131 if (is_signed && bits.back() == State::S1)
132 for (size_t i = bits.size(); i < 32; i++)
133 ret |= 1 << i;
134 return ret;
135 }
136
137 std::string RTLIL::Const::as_string() const
138 {
139 std::string ret;
140 for (size_t i = bits.size(); i > 0; i--)
141 switch (bits[i-1]) {
142 case S0: ret += "0"; break;
143 case S1: ret += "1"; break;
144 case Sx: ret += "x"; break;
145 case Sz: ret += "z"; break;
146 case Sa: ret += "-"; break;
147 case Sm: ret += "m"; break;
148 }
149 return ret;
150 }
151
152 RTLIL::Const RTLIL::Const::from_string(std::string str)
153 {
154 Const c;
155 for (auto it = str.rbegin(); it != str.rend(); it++)
156 switch (*it) {
157 case '0': c.bits.push_back(State::S0); break;
158 case '1': c.bits.push_back(State::S1); break;
159 case 'x': c.bits.push_back(State::Sx); break;
160 case 'z': c.bits.push_back(State::Sz); break;
161 case 'm': c.bits.push_back(State::Sm); break;
162 default: c.bits.push_back(State::Sa);
163 }
164 return c;
165 }
166
167 std::string RTLIL::Const::decode_string() const
168 {
169 std::string string;
170 std::vector<char> string_chars;
171 for (int i = 0; i < int (bits.size()); i += 8) {
172 char ch = 0;
173 for (int j = 0; j < 8 && i + j < int (bits.size()); j++)
174 if (bits[i + j] == RTLIL::State::S1)
175 ch |= 1 << j;
176 if (ch != 0)
177 string_chars.push_back(ch);
178 }
179 for (int i = int (string_chars.size()) - 1; i >= 0; i--)
180 string += string_chars[i];
181 return string;
182 }
183
184 bool RTLIL::Const::is_fully_zero() const
185 {
186 cover("kernel.rtlil.const.is_fully_zero");
187
188 for (auto bit : bits)
189 if (bit != RTLIL::State::S0)
190 return false;
191
192 return true;
193 }
194
195 bool RTLIL::Const::is_fully_ones() const
196 {
197 cover("kernel.rtlil.const.is_fully_ones");
198
199 for (auto bit : bits)
200 if (bit != RTLIL::State::S1)
201 return false;
202
203 return true;
204 }
205
206 bool RTLIL::Const::is_fully_def() const
207 {
208 cover("kernel.rtlil.const.is_fully_def");
209
210 for (auto bit : bits)
211 if (bit != RTLIL::State::S0 && bit != RTLIL::State::S1)
212 return false;
213
214 return true;
215 }
216
217 bool RTLIL::Const::is_fully_undef() const
218 {
219 cover("kernel.rtlil.const.is_fully_undef");
220
221 for (auto bit : bits)
222 if (bit != RTLIL::State::Sx && bit != RTLIL::State::Sz)
223 return false;
224
225 return true;
226 }
227
228 void RTLIL::AttrObject::set_bool_attribute(RTLIL::IdString id, bool value)
229 {
230 if (value)
231 attributes[id] = RTLIL::Const(1);
232 else {
233 const auto it = attributes.find(id);
234 if (it != attributes.end())
235 attributes.erase(it);
236 }
237 }
238
239 bool RTLIL::AttrObject::get_bool_attribute(RTLIL::IdString id) const
240 {
241 const auto it = attributes.find(id);
242 if (it == attributes.end())
243 return false;
244 return it->second.as_bool();
245 }
246
247 void RTLIL::AttrObject::set_strpool_attribute(RTLIL::IdString id, const pool<string> &data)
248 {
249 string attrval;
250 for (auto &s : data) {
251 if (!attrval.empty())
252 attrval += "|";
253 attrval += s;
254 }
255 attributes[id] = RTLIL::Const(attrval);
256 }
257
258 void RTLIL::AttrObject::add_strpool_attribute(RTLIL::IdString id, const pool<string> &data)
259 {
260 pool<string> union_data = get_strpool_attribute(id);
261 union_data.insert(data.begin(), data.end());
262 if (!union_data.empty())
263 set_strpool_attribute(id, union_data);
264 }
265
266 pool<string> RTLIL::AttrObject::get_strpool_attribute(RTLIL::IdString id) const
267 {
268 pool<string> data;
269 if (attributes.count(id) != 0)
270 for (auto s : split_tokens(attributes.at(id).decode_string(), "|"))
271 data.insert(s);
272 return data;
273 }
274
275 void RTLIL::AttrObject::set_src_attribute(const std::string &src)
276 {
277 if (src.empty())
278 attributes.erase(ID(src));
279 else
280 attributes[ID(src)] = src;
281 }
282
283 std::string RTLIL::AttrObject::get_src_attribute() const
284 {
285 std::string src;
286 if (attributes.count(ID(src)))
287 src = attributes.at(ID(src)).decode_string();
288 return src;
289 }
290
291 bool RTLIL::Selection::selected_module(RTLIL::IdString mod_name) const
292 {
293 if (full_selection)
294 return true;
295 if (selected_modules.count(mod_name) > 0)
296 return true;
297 if (selected_members.count(mod_name) > 0)
298 return true;
299 return false;
300 }
301
302 bool RTLIL::Selection::selected_whole_module(RTLIL::IdString mod_name) const
303 {
304 if (full_selection)
305 return true;
306 if (selected_modules.count(mod_name) > 0)
307 return true;
308 return false;
309 }
310
311 bool RTLIL::Selection::selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const
312 {
313 if (full_selection)
314 return true;
315 if (selected_modules.count(mod_name) > 0)
316 return true;
317 if (selected_members.count(mod_name) > 0)
318 if (selected_members.at(mod_name).count(memb_name) > 0)
319 return true;
320 return false;
321 }
322
323 void RTLIL::Selection::optimize(RTLIL::Design *design)
324 {
325 if (full_selection) {
326 selected_modules.clear();
327 selected_members.clear();
328 return;
329 }
330
331 std::vector<RTLIL::IdString> del_list, add_list;
332
333 del_list.clear();
334 for (auto mod_name : selected_modules) {
335 if (design->modules_.count(mod_name) == 0)
336 del_list.push_back(mod_name);
337 selected_members.erase(mod_name);
338 }
339 for (auto mod_name : del_list)
340 selected_modules.erase(mod_name);
341
342 del_list.clear();
343 for (auto &it : selected_members)
344 if (design->modules_.count(it.first) == 0)
345 del_list.push_back(it.first);
346 for (auto mod_name : del_list)
347 selected_members.erase(mod_name);
348
349 for (auto &it : selected_members) {
350 del_list.clear();
351 for (auto memb_name : it.second)
352 if (design->modules_[it.first]->count_id(memb_name) == 0)
353 del_list.push_back(memb_name);
354 for (auto memb_name : del_list)
355 it.second.erase(memb_name);
356 }
357
358 del_list.clear();
359 add_list.clear();
360 for (auto &it : selected_members)
361 if (it.second.size() == 0)
362 del_list.push_back(it.first);
363 else if (it.second.size() == design->modules_[it.first]->wires_.size() + design->modules_[it.first]->memories.size() +
364 design->modules_[it.first]->cells_.size() + design->modules_[it.first]->processes.size())
365 add_list.push_back(it.first);
366 for (auto mod_name : del_list)
367 selected_members.erase(mod_name);
368 for (auto mod_name : add_list) {
369 selected_members.erase(mod_name);
370 selected_modules.insert(mod_name);
371 }
372
373 if (selected_modules.size() == design->modules_.size()) {
374 full_selection = true;
375 selected_modules.clear();
376 selected_members.clear();
377 }
378 }
379
380 RTLIL::Design::Design()
381 {
382 static unsigned int hashidx_count = 123456789;
383 hashidx_count = mkhash_xorshift(hashidx_count);
384 hashidx_ = hashidx_count;
385
386 refcount_modules_ = 0;
387 selection_stack.push_back(RTLIL::Selection());
388
389 #ifdef WITH_PYTHON
390 RTLIL::Design::get_all_designs()->insert(std::pair<unsigned int, RTLIL::Design*>(hashidx_, this));
391 #endif
392 }
393
394 RTLIL::Design::~Design()
395 {
396 for (auto it = modules_.begin(); it != modules_.end(); ++it)
397 delete it->second;
398 for (auto n : verilog_packages)
399 delete n;
400 for (auto n : verilog_globals)
401 delete n;
402 #ifdef WITH_PYTHON
403 RTLIL::Design::get_all_designs()->erase(hashidx_);
404 #endif
405 }
406
407 #ifdef WITH_PYTHON
408 static std::map<unsigned int, RTLIL::Design*> all_designs;
409 std::map<unsigned int, RTLIL::Design*> *RTLIL::Design::get_all_designs(void)
410 {
411 return &all_designs;
412 }
413 #endif
414
415 RTLIL::ObjRange<RTLIL::Module*> RTLIL::Design::modules()
416 {
417 return RTLIL::ObjRange<RTLIL::Module*>(&modules_, &refcount_modules_);
418 }
419
420 RTLIL::Module *RTLIL::Design::module(RTLIL::IdString name)
421 {
422 return modules_.count(name) ? modules_.at(name) : NULL;
423 }
424
425 RTLIL::Module *RTLIL::Design::top_module()
426 {
427 RTLIL::Module *module = nullptr;
428 int module_count = 0;
429
430 for (auto mod : selected_modules()) {
431 if (mod->get_bool_attribute(ID(top)))
432 return mod;
433 module_count++;
434 module = mod;
435 }
436
437 return module_count == 1 ? module : nullptr;
438 }
439
440 void RTLIL::Design::add(RTLIL::Module *module)
441 {
442 log_assert(modules_.count(module->name) == 0);
443 log_assert(refcount_modules_ == 0);
444 modules_[module->name] = module;
445 module->design = this;
446
447 for (auto mon : monitors)
448 mon->notify_module_add(module);
449
450 if (yosys_xtrace) {
451 log("#X# New Module: %s\n", log_id(module));
452 log_backtrace("-X- ", yosys_xtrace-1);
453 }
454 }
455
456 RTLIL::Module *RTLIL::Design::addModule(RTLIL::IdString name)
457 {
458 log_assert(modules_.count(name) == 0);
459 log_assert(refcount_modules_ == 0);
460
461 RTLIL::Module *module = new RTLIL::Module;
462 modules_[name] = module;
463 module->design = this;
464 module->name = name;
465
466 for (auto mon : monitors)
467 mon->notify_module_add(module);
468
469 if (yosys_xtrace) {
470 log("#X# New Module: %s\n", log_id(module));
471 log_backtrace("-X- ", yosys_xtrace-1);
472 }
473
474 return module;
475 }
476
477 void RTLIL::Design::scratchpad_unset(std::string varname)
478 {
479 scratchpad.erase(varname);
480 }
481
482 void RTLIL::Design::scratchpad_set_int(std::string varname, int value)
483 {
484 scratchpad[varname] = stringf("%d", value);
485 }
486
487 void RTLIL::Design::scratchpad_set_bool(std::string varname, bool value)
488 {
489 scratchpad[varname] = value ? "true" : "false";
490 }
491
492 void RTLIL::Design::scratchpad_set_string(std::string varname, std::string value)
493 {
494 scratchpad[varname] = value;
495 }
496
497 int RTLIL::Design::scratchpad_get_int(std::string varname, int default_value) const
498 {
499 if (scratchpad.count(varname) == 0)
500 return default_value;
501
502 std::string str = scratchpad.at(varname);
503
504 if (str == "0" || str == "false")
505 return 0;
506
507 if (str == "1" || str == "true")
508 return 1;
509
510 char *endptr = nullptr;
511 long int parsed_value = strtol(str.c_str(), &endptr, 10);
512 return *endptr ? default_value : parsed_value;
513 }
514
515 bool RTLIL::Design::scratchpad_get_bool(std::string varname, bool default_value) const
516 {
517 if (scratchpad.count(varname) == 0)
518 return default_value;
519
520 std::string str = scratchpad.at(varname);
521
522 if (str == "0" || str == "false")
523 return false;
524
525 if (str == "1" || str == "true")
526 return true;
527
528 return default_value;
529 }
530
531 std::string RTLIL::Design::scratchpad_get_string(std::string varname, std::string default_value) const
532 {
533 if (scratchpad.count(varname) == 0)
534 return default_value;
535 return scratchpad.at(varname);
536 }
537
538 void RTLIL::Design::remove(RTLIL::Module *module)
539 {
540 for (auto mon : monitors)
541 mon->notify_module_del(module);
542
543 if (yosys_xtrace) {
544 log("#X# Remove Module: %s\n", log_id(module));
545 log_backtrace("-X- ", yosys_xtrace-1);
546 }
547
548 log_assert(modules_.at(module->name) == module);
549 modules_.erase(module->name);
550 delete module;
551 }
552
553 void RTLIL::Design::rename(RTLIL::Module *module, RTLIL::IdString new_name)
554 {
555 modules_.erase(module->name);
556 module->name = new_name;
557 add(module);
558 }
559
560 void RTLIL::Design::sort()
561 {
562 scratchpad.sort();
563 modules_.sort(sort_by_id_str());
564 for (auto &it : modules_)
565 it.second->sort();
566 }
567
568 void RTLIL::Design::check()
569 {
570 #ifndef NDEBUG
571 for (auto &it : modules_) {
572 log_assert(this == it.second->design);
573 log_assert(it.first == it.second->name);
574 log_assert(!it.first.empty());
575 it.second->check();
576 }
577 #endif
578 }
579
580 void RTLIL::Design::optimize()
581 {
582 for (auto &it : modules_)
583 it.second->optimize();
584 for (auto &it : selection_stack)
585 it.optimize(this);
586 for (auto &it : selection_vars)
587 it.second.optimize(this);
588 }
589
590 bool RTLIL::Design::selected_module(RTLIL::IdString mod_name) const
591 {
592 if (!selected_active_module.empty() && mod_name != selected_active_module)
593 return false;
594 if (selection_stack.size() == 0)
595 return true;
596 return selection_stack.back().selected_module(mod_name);
597 }
598
599 bool RTLIL::Design::selected_whole_module(RTLIL::IdString mod_name) const
600 {
601 if (!selected_active_module.empty() && mod_name != selected_active_module)
602 return false;
603 if (selection_stack.size() == 0)
604 return true;
605 return selection_stack.back().selected_whole_module(mod_name);
606 }
607
608 bool RTLIL::Design::selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const
609 {
610 if (!selected_active_module.empty() && mod_name != selected_active_module)
611 return false;
612 if (selection_stack.size() == 0)
613 return true;
614 return selection_stack.back().selected_member(mod_name, memb_name);
615 }
616
617 bool RTLIL::Design::selected_module(RTLIL::Module *mod) const
618 {
619 return selected_module(mod->name);
620 }
621
622 bool RTLIL::Design::selected_whole_module(RTLIL::Module *mod) const
623 {
624 return selected_whole_module(mod->name);
625 }
626
627 std::vector<RTLIL::Module*> RTLIL::Design::selected_modules() const
628 {
629 std::vector<RTLIL::Module*> result;
630 result.reserve(modules_.size());
631 for (auto &it : modules_)
632 if (selected_module(it.first) && !it.second->get_blackbox_attribute())
633 result.push_back(it.second);
634 return result;
635 }
636
637 std::vector<RTLIL::Module*> RTLIL::Design::selected_whole_modules() const
638 {
639 std::vector<RTLIL::Module*> result;
640 result.reserve(modules_.size());
641 for (auto &it : modules_)
642 if (selected_whole_module(it.first) && !it.second->get_blackbox_attribute())
643 result.push_back(it.second);
644 return result;
645 }
646
647 std::vector<RTLIL::Module*> RTLIL::Design::selected_whole_modules_warn() const
648 {
649 std::vector<RTLIL::Module*> result;
650 result.reserve(modules_.size());
651 for (auto &it : modules_)
652 if (it.second->get_blackbox_attribute())
653 continue;
654 else if (selected_whole_module(it.first))
655 result.push_back(it.second);
656 else if (selected_module(it.first))
657 log_warning("Ignoring partially selected module %s.\n", log_id(it.first));
658 return result;
659 }
660
661 RTLIL::Module::Module()
662 {
663 static unsigned int hashidx_count = 123456789;
664 hashidx_count = mkhash_xorshift(hashidx_count);
665 hashidx_ = hashidx_count;
666
667 design = nullptr;
668 refcount_wires_ = 0;
669 refcount_cells_ = 0;
670
671 #ifdef WITH_PYTHON
672 RTLIL::Module::get_all_modules()->insert(std::pair<unsigned int, RTLIL::Module*>(hashidx_, this));
673 #endif
674 }
675
676 RTLIL::Module::~Module()
677 {
678 for (auto it = wires_.begin(); it != wires_.end(); ++it)
679 delete it->second;
680 for (auto it = memories.begin(); it != memories.end(); ++it)
681 delete it->second;
682 for (auto it = cells_.begin(); it != cells_.end(); ++it)
683 delete it->second;
684 for (auto it = processes.begin(); it != processes.end(); ++it)
685 delete it->second;
686 #ifdef WITH_PYTHON
687 RTLIL::Module::get_all_modules()->erase(hashidx_);
688 #endif
689 }
690
691 #ifdef WITH_PYTHON
692 static std::map<unsigned int, RTLIL::Module*> all_modules;
693 std::map<unsigned int, RTLIL::Module*> *RTLIL::Module::get_all_modules(void)
694 {
695 return &all_modules;
696 }
697 #endif
698
699 void RTLIL::Module::makeblackbox()
700 {
701 pool<RTLIL::Wire*> delwires;
702
703 for (auto it = wires_.begin(); it != wires_.end(); ++it)
704 if (!it->second->port_input && !it->second->port_output)
705 delwires.insert(it->second);
706
707 for (auto it = memories.begin(); it != memories.end(); ++it)
708 delete it->second;
709 memories.clear();
710
711 for (auto it = cells_.begin(); it != cells_.end(); ++it)
712 delete it->second;
713 cells_.clear();
714
715 for (auto it = processes.begin(); it != processes.end(); ++it)
716 delete it->second;
717 processes.clear();
718
719 remove(delwires);
720 set_bool_attribute(ID::blackbox);
721 }
722
723 void RTLIL::Module::reprocess_module(RTLIL::Design *, dict<RTLIL::IdString, RTLIL::Module *>)
724 {
725 log_error("Cannot reprocess_module module `%s' !\n", id2cstr(name));
726 }
727
728 RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, dict<RTLIL::IdString, RTLIL::Const>, bool mayfail)
729 {
730 if (mayfail)
731 return RTLIL::IdString();
732 log_error("Module `%s' is used with parameters but is not parametric!\n", id2cstr(name));
733 }
734
735
736 RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, dict<RTLIL::IdString, RTLIL::Const>, dict<RTLIL::IdString, RTLIL::Module*>, dict<RTLIL::IdString, RTLIL::IdString>, bool mayfail)
737 {
738 if (mayfail)
739 return RTLIL::IdString();
740 log_error("Module `%s' is used with parameters but is not parametric!\n", id2cstr(name));
741 }
742
743 size_t RTLIL::Module::count_id(RTLIL::IdString id)
744 {
745 return wires_.count(id) + memories.count(id) + cells_.count(id) + processes.count(id);
746 }
747
748 #ifndef NDEBUG
749 namespace {
750 struct InternalCellChecker
751 {
752 RTLIL::Module *module;
753 RTLIL::Cell *cell;
754 pool<RTLIL::IdString> expected_params, expected_ports;
755
756 InternalCellChecker(RTLIL::Module *module, RTLIL::Cell *cell) : module(module), cell(cell) { }
757
758 void error(int linenr)
759 {
760 std::stringstream buf;
761 ILANG_BACKEND::dump_cell(buf, " ", cell);
762
763 log_error("Found error in internal cell %s%s%s (%s) at %s:%d:\n%s",
764 module ? module->name.c_str() : "", module ? "." : "",
765 cell->name.c_str(), cell->type.c_str(), __FILE__, linenr, buf.str().c_str());
766 }
767
768 int param(RTLIL::IdString name)
769 {
770 if (cell->parameters.count(name) == 0)
771 error(__LINE__);
772 expected_params.insert(name);
773 return cell->parameters.at(name).as_int();
774 }
775
776 int param_bool(RTLIL::IdString name)
777 {
778 int v = param(name);
779 if (cell->parameters.at(name).bits.size() > 32)
780 error(__LINE__);
781 if (v != 0 && v != 1)
782 error(__LINE__);
783 return v;
784 }
785
786 int param_bool(RTLIL::IdString name, bool expected)
787 {
788 int v = param_bool(name);
789 if (v != expected)
790 error(__LINE__);
791 return v;
792 }
793
794 void param_bits(RTLIL::IdString name, int width)
795 {
796 param(name);
797 if (int(cell->parameters.at(name).bits.size()) != width)
798 error(__LINE__);
799 }
800
801 void port(RTLIL::IdString name, int width)
802 {
803 if (!cell->hasPort(name))
804 error(__LINE__);
805 if (cell->getPort(name).size() != width)
806 error(__LINE__);
807 expected_ports.insert(name);
808 }
809
810 void check_expected(bool check_matched_sign = true)
811 {
812 for (auto &para : cell->parameters)
813 if (expected_params.count(para.first) == 0)
814 error(__LINE__);
815 for (auto &conn : cell->connections())
816 if (expected_ports.count(conn.first) == 0)
817 error(__LINE__);
818
819 if (expected_params.count(ID(A_SIGNED)) != 0 && expected_params.count(ID(B_SIGNED)) && check_matched_sign) {
820 bool a_is_signed = param(ID(A_SIGNED)) != 0;
821 bool b_is_signed = param(ID(B_SIGNED)) != 0;
822 if (a_is_signed != b_is_signed)
823 error(__LINE__);
824 }
825 }
826
827 void check_gate(const char *ports)
828 {
829 if (cell->parameters.size() != 0)
830 error(__LINE__);
831
832 for (const char *p = ports; *p; p++) {
833 char portname[3] = { '\\', *p, 0 };
834 if (!cell->hasPort(portname))
835 error(__LINE__);
836 if (cell->getPort(portname).size() != 1)
837 error(__LINE__);
838 }
839
840 for (auto &conn : cell->connections()) {
841 if (conn.first.size() != 2 || conn.first[0] != '\\')
842 error(__LINE__);
843 if (strchr(ports, conn.first[1]) == NULL)
844 error(__LINE__);
845 }
846 }
847
848 void check()
849 {
850 if (!cell->type.begins_with("$") || cell->type.begins_with("$__") || cell->type.begins_with("$paramod") || cell->type.begins_with("$fmcombine") ||
851 cell->type.begins_with("$verific$") || cell->type.begins_with("$array:") || cell->type.begins_with("$extern:"))
852 return;
853
854 if (cell->type.in(ID($not), ID($pos), ID($neg))) {
855 param_bool(ID(A_SIGNED));
856 port(ID::A, param(ID(A_WIDTH)));
857 port(ID::Y, param(ID(Y_WIDTH)));
858 check_expected();
859 return;
860 }
861
862 if (cell->type.in(ID($and), ID($or), ID($xor), ID($xnor))) {
863 param_bool(ID(A_SIGNED));
864 param_bool(ID(B_SIGNED));
865 port(ID::A, param(ID(A_WIDTH)));
866 port(ID::B, param(ID(B_WIDTH)));
867 port(ID::Y, param(ID(Y_WIDTH)));
868 check_expected();
869 return;
870 }
871
872 if (cell->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor), ID($reduce_bool))) {
873 param_bool(ID(A_SIGNED));
874 port(ID::A, param(ID(A_WIDTH)));
875 port(ID::Y, param(ID(Y_WIDTH)));
876 check_expected();
877 return;
878 }
879
880 if (cell->type.in(ID($shl), ID($shr), ID($sshl), ID($sshr))) {
881 param_bool(ID(A_SIGNED));
882 param_bool(ID(B_SIGNED), /*expected=*/false);
883 port(ID::A, param(ID(A_WIDTH)));
884 port(ID::B, param(ID(B_WIDTH)));
885 port(ID::Y, param(ID(Y_WIDTH)));
886 check_expected(/*check_matched_sign=*/false);
887 return;
888 }
889
890 if (cell->type.in(ID($shift), ID($shiftx))) {
891 param_bool(ID(A_SIGNED));
892 param_bool(ID(B_SIGNED));
893 port(ID::A, param(ID(A_WIDTH)));
894 port(ID::B, param(ID(B_WIDTH)));
895 port(ID::Y, param(ID(Y_WIDTH)));
896 check_expected(/*check_matched_sign=*/false);
897 return;
898 }
899
900 if (cell->type.in(ID($lt), ID($le), ID($eq), ID($ne), ID($eqx), ID($nex), ID($ge), ID($gt))) {
901 param_bool(ID(A_SIGNED));
902 param_bool(ID(B_SIGNED));
903 port(ID::A, param(ID(A_WIDTH)));
904 port(ID::B, param(ID(B_WIDTH)));
905 port(ID::Y, param(ID(Y_WIDTH)));
906 check_expected();
907 return;
908 }
909
910 if (cell->type.in(ID($add), ID($sub), ID($mul), ID($div), ID($mod), ID($pow))) {
911 param_bool(ID(A_SIGNED));
912 param_bool(ID(B_SIGNED));
913 port(ID::A, param(ID(A_WIDTH)));
914 port(ID::B, param(ID(B_WIDTH)));
915 port(ID::Y, param(ID(Y_WIDTH)));
916 check_expected(cell->type != ID($pow));
917 return;
918 }
919
920 if (cell->type == ID($fa)) {
921 port(ID::A, param(ID(WIDTH)));
922 port(ID::B, param(ID(WIDTH)));
923 port(ID(C), param(ID(WIDTH)));
924 port(ID(X), param(ID(WIDTH)));
925 port(ID::Y, param(ID(WIDTH)));
926 check_expected();
927 return;
928 }
929
930 if (cell->type == ID($lcu)) {
931 port(ID(P), param(ID(WIDTH)));
932 port(ID(G), param(ID(WIDTH)));
933 port(ID(CI), 1);
934 port(ID(CO), param(ID(WIDTH)));
935 check_expected();
936 return;
937 }
938
939 if (cell->type == ID($alu)) {
940 param_bool(ID(A_SIGNED));
941 param_bool(ID(B_SIGNED));
942 port(ID::A, param(ID(A_WIDTH)));
943 port(ID::B, param(ID(B_WIDTH)));
944 port(ID(CI), 1);
945 port(ID(BI), 1);
946 port(ID(X), param(ID(Y_WIDTH)));
947 port(ID::Y, param(ID(Y_WIDTH)));
948 port(ID(CO), param(ID(Y_WIDTH)));
949 check_expected();
950 return;
951 }
952
953 if (cell->type == ID($macc)) {
954 param(ID(CONFIG));
955 param(ID(CONFIG_WIDTH));
956 port(ID::A, param(ID(A_WIDTH)));
957 port(ID::B, param(ID(B_WIDTH)));
958 port(ID::Y, param(ID(Y_WIDTH)));
959 check_expected();
960 Macc().from_cell(cell);
961 return;
962 }
963
964 if (cell->type == ID($logic_not)) {
965 param_bool(ID(A_SIGNED));
966 port(ID::A, param(ID(A_WIDTH)));
967 port(ID::Y, param(ID(Y_WIDTH)));
968 check_expected();
969 return;
970 }
971
972 if (cell->type.in(ID($logic_and), ID($logic_or))) {
973 param_bool(ID(A_SIGNED));
974 param_bool(ID(B_SIGNED));
975 port(ID::A, param(ID(A_WIDTH)));
976 port(ID::B, param(ID(B_WIDTH)));
977 port(ID::Y, param(ID(Y_WIDTH)));
978 check_expected(/*check_matched_sign=*/false);
979 return;
980 }
981
982 if (cell->type == ID($slice)) {
983 param(ID(OFFSET));
984 port(ID::A, param(ID(A_WIDTH)));
985 port(ID::Y, param(ID(Y_WIDTH)));
986 if (param(ID(OFFSET)) + param(ID(Y_WIDTH)) > param(ID(A_WIDTH)))
987 error(__LINE__);
988 check_expected();
989 return;
990 }
991
992 if (cell->type == ID($concat)) {
993 port(ID::A, param(ID(A_WIDTH)));
994 port(ID::B, param(ID(B_WIDTH)));
995 port(ID::Y, param(ID(A_WIDTH)) + param(ID(B_WIDTH)));
996 check_expected();
997 return;
998 }
999
1000 if (cell->type == ID($mux)) {
1001 port(ID::A, param(ID(WIDTH)));
1002 port(ID::B, param(ID(WIDTH)));
1003 port(ID(S), 1);
1004 port(ID::Y, param(ID(WIDTH)));
1005 check_expected();
1006 return;
1007 }
1008
1009 if (cell->type == ID($pmux)) {
1010 port(ID::A, param(ID(WIDTH)));
1011 port(ID::B, param(ID(WIDTH)) * param(ID(S_WIDTH)));
1012 port(ID(S), param(ID(S_WIDTH)));
1013 port(ID::Y, param(ID(WIDTH)));
1014 check_expected();
1015 return;
1016 }
1017
1018 if (cell->type == ID($lut)) {
1019 param(ID(LUT));
1020 port(ID::A, param(ID(WIDTH)));
1021 port(ID::Y, 1);
1022 check_expected();
1023 return;
1024 }
1025
1026 if (cell->type == ID($sop)) {
1027 param(ID(DEPTH));
1028 param(ID(TABLE));
1029 port(ID::A, param(ID(WIDTH)));
1030 port(ID::Y, 1);
1031 check_expected();
1032 return;
1033 }
1034
1035 if (cell->type == ID($sr)) {
1036 param_bool(ID(SET_POLARITY));
1037 param_bool(ID(CLR_POLARITY));
1038 port(ID(SET), param(ID(WIDTH)));
1039 port(ID(CLR), param(ID(WIDTH)));
1040 port(ID(Q), param(ID(WIDTH)));
1041 check_expected();
1042 return;
1043 }
1044
1045 if (cell->type == ID($ff)) {
1046 port(ID(D), param(ID(WIDTH)));
1047 port(ID(Q), param(ID(WIDTH)));
1048 check_expected();
1049 return;
1050 }
1051
1052 if (cell->type == ID($dff)) {
1053 param_bool(ID(CLK_POLARITY));
1054 port(ID(CLK), 1);
1055 port(ID(D), param(ID(WIDTH)));
1056 port(ID(Q), param(ID(WIDTH)));
1057 check_expected();
1058 return;
1059 }
1060
1061 if (cell->type == ID($dffe)) {
1062 param_bool(ID(CLK_POLARITY));
1063 param_bool(ID(EN_POLARITY));
1064 port(ID(CLK), 1);
1065 port(ID(EN), 1);
1066 port(ID(D), param(ID(WIDTH)));
1067 port(ID(Q), param(ID(WIDTH)));
1068 check_expected();
1069 return;
1070 }
1071
1072 if (cell->type == ID($dffsr)) {
1073 param_bool(ID(CLK_POLARITY));
1074 param_bool(ID(SET_POLARITY));
1075 param_bool(ID(CLR_POLARITY));
1076 port(ID(CLK), 1);
1077 port(ID(SET), param(ID(WIDTH)));
1078 port(ID(CLR), param(ID(WIDTH)));
1079 port(ID(D), param(ID(WIDTH)));
1080 port(ID(Q), param(ID(WIDTH)));
1081 check_expected();
1082 return;
1083 }
1084
1085 if (cell->type == ID($adff)) {
1086 param_bool(ID(CLK_POLARITY));
1087 param_bool(ID(ARST_POLARITY));
1088 param_bits(ID(ARST_VALUE), param(ID(WIDTH)));
1089 port(ID(CLK), 1);
1090 port(ID(ARST), 1);
1091 port(ID(D), param(ID(WIDTH)));
1092 port(ID(Q), param(ID(WIDTH)));
1093 check_expected();
1094 return;
1095 }
1096
1097 if (cell->type == ID($dlatch)) {
1098 param_bool(ID(EN_POLARITY));
1099 port(ID(EN), 1);
1100 port(ID(D), param(ID(WIDTH)));
1101 port(ID(Q), param(ID(WIDTH)));
1102 check_expected();
1103 return;
1104 }
1105
1106 if (cell->type == ID($dlatchsr)) {
1107 param_bool(ID(EN_POLARITY));
1108 param_bool(ID(SET_POLARITY));
1109 param_bool(ID(CLR_POLARITY));
1110 port(ID(EN), 1);
1111 port(ID(SET), param(ID(WIDTH)));
1112 port(ID(CLR), param(ID(WIDTH)));
1113 port(ID(D), param(ID(WIDTH)));
1114 port(ID(Q), param(ID(WIDTH)));
1115 check_expected();
1116 return;
1117 }
1118
1119 if (cell->type == ID($fsm)) {
1120 param(ID(NAME));
1121 param_bool(ID(CLK_POLARITY));
1122 param_bool(ID(ARST_POLARITY));
1123 param(ID(STATE_BITS));
1124 param(ID(STATE_NUM));
1125 param(ID(STATE_NUM_LOG2));
1126 param(ID(STATE_RST));
1127 param_bits(ID(STATE_TABLE), param(ID(STATE_BITS)) * param(ID(STATE_NUM)));
1128 param(ID(TRANS_NUM));
1129 param_bits(ID(TRANS_TABLE), param(ID(TRANS_NUM)) * (2*param(ID(STATE_NUM_LOG2)) + param(ID(CTRL_IN_WIDTH)) + param(ID(CTRL_OUT_WIDTH))));
1130 port(ID(CLK), 1);
1131 port(ID(ARST), 1);
1132 port(ID(CTRL_IN), param(ID(CTRL_IN_WIDTH)));
1133 port(ID(CTRL_OUT), param(ID(CTRL_OUT_WIDTH)));
1134 check_expected();
1135 return;
1136 }
1137
1138 if (cell->type == ID($memrd)) {
1139 param(ID(MEMID));
1140 param_bool(ID(CLK_ENABLE));
1141 param_bool(ID(CLK_POLARITY));
1142 param_bool(ID(TRANSPARENT));
1143 port(ID(CLK), 1);
1144 port(ID(EN), 1);
1145 port(ID(ADDR), param(ID(ABITS)));
1146 port(ID(DATA), param(ID(WIDTH)));
1147 check_expected();
1148 return;
1149 }
1150
1151 if (cell->type == ID($memwr)) {
1152 param(ID(MEMID));
1153 param_bool(ID(CLK_ENABLE));
1154 param_bool(ID(CLK_POLARITY));
1155 param(ID(PRIORITY));
1156 port(ID(CLK), 1);
1157 port(ID(EN), param(ID(WIDTH)));
1158 port(ID(ADDR), param(ID(ABITS)));
1159 port(ID(DATA), param(ID(WIDTH)));
1160 check_expected();
1161 return;
1162 }
1163
1164 if (cell->type == ID($meminit)) {
1165 param(ID(MEMID));
1166 param(ID(PRIORITY));
1167 port(ID(ADDR), param(ID(ABITS)));
1168 port(ID(DATA), param(ID(WIDTH)) * param(ID(WORDS)));
1169 check_expected();
1170 return;
1171 }
1172
1173 if (cell->type == ID($mem)) {
1174 param(ID(MEMID));
1175 param(ID(SIZE));
1176 param(ID(OFFSET));
1177 param(ID(INIT));
1178 param_bits(ID(RD_CLK_ENABLE), max(1, param(ID(RD_PORTS))));
1179 param_bits(ID(RD_CLK_POLARITY), max(1, param(ID(RD_PORTS))));
1180 param_bits(ID(RD_TRANSPARENT), max(1, param(ID(RD_PORTS))));
1181 param_bits(ID(WR_CLK_ENABLE), max(1, param(ID(WR_PORTS))));
1182 param_bits(ID(WR_CLK_POLARITY), max(1, param(ID(WR_PORTS))));
1183 port(ID(RD_CLK), param(ID(RD_PORTS)));
1184 port(ID(RD_EN), param(ID(RD_PORTS)));
1185 port(ID(RD_ADDR), param(ID(RD_PORTS)) * param(ID(ABITS)));
1186 port(ID(RD_DATA), param(ID(RD_PORTS)) * param(ID(WIDTH)));
1187 port(ID(WR_CLK), param(ID(WR_PORTS)));
1188 port(ID(WR_EN), param(ID(WR_PORTS)) * param(ID(WIDTH)));
1189 port(ID(WR_ADDR), param(ID(WR_PORTS)) * param(ID(ABITS)));
1190 port(ID(WR_DATA), param(ID(WR_PORTS)) * param(ID(WIDTH)));
1191 check_expected();
1192 return;
1193 }
1194
1195 if (cell->type == ID($tribuf)) {
1196 port(ID::A, param(ID(WIDTH)));
1197 port(ID::Y, param(ID(WIDTH)));
1198 port(ID(EN), 1);
1199 check_expected();
1200 return;
1201 }
1202
1203 if (cell->type.in(ID($assert), ID($assume), ID($live), ID($fair), ID($cover))) {
1204 port(ID::A, 1);
1205 port(ID(EN), 1);
1206 check_expected();
1207 return;
1208 }
1209
1210 if (cell->type == ID($initstate)) {
1211 port(ID::Y, 1);
1212 check_expected();
1213 return;
1214 }
1215
1216 if (cell->type.in(ID($anyconst), ID($anyseq), ID($allconst), ID($allseq))) {
1217 port(ID::Y, param(ID(WIDTH)));
1218 check_expected();
1219 return;
1220 }
1221
1222 if (cell->type == ID($equiv)) {
1223 port(ID::A, 1);
1224 port(ID::B, 1);
1225 port(ID::Y, 1);
1226 check_expected();
1227 return;
1228 }
1229
1230 if (cell->type.in(ID($specify2), ID($specify3))) {
1231 param_bool(ID(FULL));
1232 param_bool(ID(SRC_DST_PEN));
1233 param_bool(ID(SRC_DST_POL));
1234 param(ID(T_RISE_MIN));
1235 param(ID(T_RISE_TYP));
1236 param(ID(T_RISE_MAX));
1237 param(ID(T_FALL_MIN));
1238 param(ID(T_FALL_TYP));
1239 param(ID(T_FALL_MAX));
1240 port(ID(EN), 1);
1241 port(ID(SRC), param(ID(SRC_WIDTH)));
1242 port(ID(DST), param(ID(DST_WIDTH)));
1243 if (cell->type == ID($specify3)) {
1244 param_bool(ID(EDGE_EN));
1245 param_bool(ID(EDGE_POL));
1246 param_bool(ID(DAT_DST_PEN));
1247 param_bool(ID(DAT_DST_POL));
1248 port(ID(DAT), param(ID(DST_WIDTH)));
1249 }
1250 check_expected();
1251 return;
1252 }
1253
1254 if (cell->type == ID($specrule)) {
1255 param(ID(TYPE));
1256 param_bool(ID(SRC_PEN));
1257 param_bool(ID(SRC_POL));
1258 param_bool(ID(DST_PEN));
1259 param_bool(ID(DST_POL));
1260 param(ID(T_LIMIT));
1261 param(ID(T_LIMIT2));
1262 port(ID(SRC_EN), 1);
1263 port(ID(DST_EN), 1);
1264 port(ID(SRC), param(ID(SRC_WIDTH)));
1265 port(ID(DST), param(ID(DST_WIDTH)));
1266 check_expected();
1267 return;
1268 }
1269
1270 if (cell->type == ID($_BUF_)) { check_gate("AY"); return; }
1271 if (cell->type == ID($_NOT_)) { check_gate("AY"); return; }
1272 if (cell->type == ID($_AND_)) { check_gate("ABY"); return; }
1273 if (cell->type == ID($_NAND_)) { check_gate("ABY"); return; }
1274 if (cell->type == ID($_OR_)) { check_gate("ABY"); return; }
1275 if (cell->type == ID($_NOR_)) { check_gate("ABY"); return; }
1276 if (cell->type == ID($_XOR_)) { check_gate("ABY"); return; }
1277 if (cell->type == ID($_XNOR_)) { check_gate("ABY"); return; }
1278 if (cell->type == ID($_ANDNOT_)) { check_gate("ABY"); return; }
1279 if (cell->type == ID($_ORNOT_)) { check_gate("ABY"); return; }
1280 if (cell->type == ID($_MUX_)) { check_gate("ABSY"); return; }
1281 if (cell->type == ID($_NMUX_)) { check_gate("ABSY"); return; }
1282 if (cell->type == ID($_AOI3_)) { check_gate("ABCY"); return; }
1283 if (cell->type == ID($_OAI3_)) { check_gate("ABCY"); return; }
1284 if (cell->type == ID($_AOI4_)) { check_gate("ABCDY"); return; }
1285 if (cell->type == ID($_OAI4_)) { check_gate("ABCDY"); return; }
1286
1287 if (cell->type == ID($_TBUF_)) { check_gate("AYE"); return; }
1288
1289 if (cell->type == ID($_MUX4_)) { check_gate("ABCDSTY"); return; }
1290 if (cell->type == ID($_MUX8_)) { check_gate("ABCDEFGHSTUY"); return; }
1291 if (cell->type == ID($_MUX16_)) { check_gate("ABCDEFGHIJKLMNOPSTUVY"); return; }
1292
1293 if (cell->type == ID($_SR_NN_)) { check_gate("SRQ"); return; }
1294 if (cell->type == ID($_SR_NP_)) { check_gate("SRQ"); return; }
1295 if (cell->type == ID($_SR_PN_)) { check_gate("SRQ"); return; }
1296 if (cell->type == ID($_SR_PP_)) { check_gate("SRQ"); return; }
1297
1298 if (cell->type == ID($_FF_)) { check_gate("DQ"); return; }
1299 if (cell->type == ID($_DFF_N_)) { check_gate("DQC"); return; }
1300 if (cell->type == ID($_DFF_P_)) { check_gate("DQC"); return; }
1301
1302 if (cell->type == ID($_DFFE_NN_)) { check_gate("DQCE"); return; }
1303 if (cell->type == ID($_DFFE_NP_)) { check_gate("DQCE"); return; }
1304 if (cell->type == ID($_DFFE_PN_)) { check_gate("DQCE"); return; }
1305 if (cell->type == ID($_DFFE_PP_)) { check_gate("DQCE"); return; }
1306
1307 if (cell->type == ID($_DFF_NN0_)) { check_gate("DQCR"); return; }
1308 if (cell->type == ID($_DFF_NN1_)) { check_gate("DQCR"); return; }
1309 if (cell->type == ID($_DFF_NP0_)) { check_gate("DQCR"); return; }
1310 if (cell->type == ID($_DFF_NP1_)) { check_gate("DQCR"); return; }
1311 if (cell->type == ID($_DFF_PN0_)) { check_gate("DQCR"); return; }
1312 if (cell->type == ID($_DFF_PN1_)) { check_gate("DQCR"); return; }
1313 if (cell->type == ID($_DFF_PP0_)) { check_gate("DQCR"); return; }
1314 if (cell->type == ID($_DFF_PP1_)) { check_gate("DQCR"); return; }
1315
1316 if (cell->type == ID($_DFFSR_NNN_)) { check_gate("CSRDQ"); return; }
1317 if (cell->type == ID($_DFFSR_NNP_)) { check_gate("CSRDQ"); return; }
1318 if (cell->type == ID($_DFFSR_NPN_)) { check_gate("CSRDQ"); return; }
1319 if (cell->type == ID($_DFFSR_NPP_)) { check_gate("CSRDQ"); return; }
1320 if (cell->type == ID($_DFFSR_PNN_)) { check_gate("CSRDQ"); return; }
1321 if (cell->type == ID($_DFFSR_PNP_)) { check_gate("CSRDQ"); return; }
1322 if (cell->type == ID($_DFFSR_PPN_)) { check_gate("CSRDQ"); return; }
1323 if (cell->type == ID($_DFFSR_PPP_)) { check_gate("CSRDQ"); return; }
1324
1325 if (cell->type == ID($_DLATCH_N_)) { check_gate("EDQ"); return; }
1326 if (cell->type == ID($_DLATCH_P_)) { check_gate("EDQ"); return; }
1327
1328 if (cell->type == ID($_DLATCHSR_NNN_)) { check_gate("ESRDQ"); return; }
1329 if (cell->type == ID($_DLATCHSR_NNP_)) { check_gate("ESRDQ"); return; }
1330 if (cell->type == ID($_DLATCHSR_NPN_)) { check_gate("ESRDQ"); return; }
1331 if (cell->type == ID($_DLATCHSR_NPP_)) { check_gate("ESRDQ"); return; }
1332 if (cell->type == ID($_DLATCHSR_PNN_)) { check_gate("ESRDQ"); return; }
1333 if (cell->type == ID($_DLATCHSR_PNP_)) { check_gate("ESRDQ"); return; }
1334 if (cell->type == ID($_DLATCHSR_PPN_)) { check_gate("ESRDQ"); return; }
1335 if (cell->type == ID($_DLATCHSR_PPP_)) { check_gate("ESRDQ"); return; }
1336
1337 error(__LINE__);
1338 }
1339 };
1340 }
1341 #endif
1342
1343 void RTLIL::Module::sort()
1344 {
1345 wires_.sort(sort_by_id_str());
1346 cells_.sort(sort_by_id_str());
1347 avail_parameters.sort(sort_by_id_str());
1348 memories.sort(sort_by_id_str());
1349 processes.sort(sort_by_id_str());
1350 for (auto &it : cells_)
1351 it.second->sort();
1352 for (auto &it : wires_)
1353 it.second->attributes.sort(sort_by_id_str());
1354 for (auto &it : memories)
1355 it.second->attributes.sort(sort_by_id_str());
1356 }
1357
1358 void RTLIL::Module::check()
1359 {
1360 #ifndef NDEBUG
1361 std::vector<bool> ports_declared;
1362 for (auto &it : wires_) {
1363 log_assert(this == it.second->module);
1364 log_assert(it.first == it.second->name);
1365 log_assert(!it.first.empty());
1366 log_assert(it.second->width >= 0);
1367 log_assert(it.second->port_id >= 0);
1368 for (auto &it2 : it.second->attributes)
1369 log_assert(!it2.first.empty());
1370 if (it.second->port_id) {
1371 log_assert(GetSize(ports) >= it.second->port_id);
1372 log_assert(ports.at(it.second->port_id-1) == it.first);
1373 log_assert(it.second->port_input || it.second->port_output);
1374 if (GetSize(ports_declared) < it.second->port_id)
1375 ports_declared.resize(it.second->port_id);
1376 log_assert(ports_declared[it.second->port_id-1] == false);
1377 ports_declared[it.second->port_id-1] = true;
1378 } else
1379 log_assert(!it.second->port_input && !it.second->port_output);
1380 }
1381 for (auto port_declared : ports_declared)
1382 log_assert(port_declared == true);
1383 log_assert(GetSize(ports) == GetSize(ports_declared));
1384
1385 for (auto &it : memories) {
1386 log_assert(it.first == it.second->name);
1387 log_assert(!it.first.empty());
1388 log_assert(it.second->width >= 0);
1389 log_assert(it.second->size >= 0);
1390 for (auto &it2 : it.second->attributes)
1391 log_assert(!it2.first.empty());
1392 }
1393
1394 for (auto &it : cells_) {
1395 log_assert(this == it.second->module);
1396 log_assert(it.first == it.second->name);
1397 log_assert(!it.first.empty());
1398 log_assert(!it.second->type.empty());
1399 for (auto &it2 : it.second->connections()) {
1400 log_assert(!it2.first.empty());
1401 it2.second.check();
1402 }
1403 for (auto &it2 : it.second->attributes)
1404 log_assert(!it2.first.empty());
1405 for (auto &it2 : it.second->parameters)
1406 log_assert(!it2.first.empty());
1407 InternalCellChecker checker(this, it.second);
1408 checker.check();
1409 }
1410
1411 for (auto &it : processes) {
1412 log_assert(it.first == it.second->name);
1413 log_assert(!it.first.empty());
1414 log_assert(it.second->root_case.compare.empty());
1415 std::vector<CaseRule*> all_cases = {&it.second->root_case};
1416 for (size_t i = 0; i < all_cases.size(); i++) {
1417 for (auto &switch_it : all_cases[i]->switches) {
1418 for (auto &case_it : switch_it->cases) {
1419 for (auto &compare_it : case_it->compare) {
1420 log_assert(switch_it->signal.size() == compare_it.size());
1421 }
1422 all_cases.push_back(case_it);
1423 }
1424 }
1425 }
1426 for (auto &sync_it : it.second->syncs) {
1427 switch (sync_it->type) {
1428 case SyncType::ST0:
1429 case SyncType::ST1:
1430 case SyncType::STp:
1431 case SyncType::STn:
1432 case SyncType::STe:
1433 log_assert(!sync_it->signal.empty());
1434 break;
1435 case SyncType::STa:
1436 case SyncType::STg:
1437 case SyncType::STi:
1438 log_assert(sync_it->signal.empty());
1439 break;
1440 }
1441 }
1442 }
1443
1444 for (auto &it : connections_) {
1445 log_assert(it.first.size() == it.second.size());
1446 log_assert(!it.first.has_const());
1447 it.first.check();
1448 it.second.check();
1449 }
1450
1451 for (auto &it : attributes)
1452 log_assert(!it.first.empty());
1453 #endif
1454 }
1455
1456 void RTLIL::Module::optimize()
1457 {
1458 }
1459
1460 void RTLIL::Module::cloneInto(RTLIL::Module *new_mod) const
1461 {
1462 log_assert(new_mod->refcount_wires_ == 0);
1463 log_assert(new_mod->refcount_cells_ == 0);
1464
1465 new_mod->avail_parameters = avail_parameters;
1466
1467 for (auto &conn : connections_)
1468 new_mod->connect(conn);
1469
1470 for (auto &attr : attributes)
1471 new_mod->attributes[attr.first] = attr.second;
1472
1473 for (auto &it : wires_)
1474 new_mod->addWire(it.first, it.second);
1475
1476 for (auto &it : memories)
1477 new_mod->memories[it.first] = new RTLIL::Memory(*it.second);
1478
1479 for (auto &it : cells_)
1480 new_mod->addCell(it.first, it.second);
1481
1482 for (auto &it : processes)
1483 new_mod->processes[it.first] = it.second->clone();
1484
1485 struct RewriteSigSpecWorker
1486 {
1487 RTLIL::Module *mod;
1488 void operator()(RTLIL::SigSpec &sig)
1489 {
1490 std::vector<RTLIL::SigChunk> chunks = sig.chunks();
1491 for (auto &c : chunks)
1492 if (c.wire != NULL)
1493 c.wire = mod->wires_.at(c.wire->name);
1494 sig = chunks;
1495 }
1496 };
1497
1498 RewriteSigSpecWorker rewriteSigSpecWorker;
1499 rewriteSigSpecWorker.mod = new_mod;
1500 new_mod->rewrite_sigspecs(rewriteSigSpecWorker);
1501 new_mod->fixup_ports();
1502 }
1503
1504 RTLIL::Module *RTLIL::Module::clone() const
1505 {
1506 RTLIL::Module *new_mod = new RTLIL::Module;
1507 new_mod->name = name;
1508 cloneInto(new_mod);
1509 return new_mod;
1510 }
1511
1512 bool RTLIL::Module::has_memories() const
1513 {
1514 return !memories.empty();
1515 }
1516
1517 bool RTLIL::Module::has_processes() const
1518 {
1519 return !processes.empty();
1520 }
1521
1522 bool RTLIL::Module::has_memories_warn() const
1523 {
1524 if (!memories.empty())
1525 log_warning("Ignoring module %s because it contains memories (run 'memory' command first).\n", log_id(this));
1526 return !memories.empty();
1527 }
1528
1529 bool RTLIL::Module::has_processes_warn() const
1530 {
1531 if (!processes.empty())
1532 log_warning("Ignoring module %s because it contains processes (run 'proc' command first).\n", log_id(this));
1533 return !processes.empty();
1534 }
1535
1536 std::vector<RTLIL::Wire*> RTLIL::Module::selected_wires() const
1537 {
1538 std::vector<RTLIL::Wire*> result;
1539 result.reserve(wires_.size());
1540 for (auto &it : wires_)
1541 if (design->selected(this, it.second))
1542 result.push_back(it.second);
1543 return result;
1544 }
1545
1546 std::vector<RTLIL::Cell*> RTLIL::Module::selected_cells() const
1547 {
1548 std::vector<RTLIL::Cell*> result;
1549 result.reserve(cells_.size());
1550 for (auto &it : cells_)
1551 if (design->selected(this, it.second))
1552 result.push_back(it.second);
1553 return result;
1554 }
1555
1556 void RTLIL::Module::add(RTLIL::Wire *wire)
1557 {
1558 log_assert(!wire->name.empty());
1559 log_assert(count_id(wire->name) == 0);
1560 log_assert(refcount_wires_ == 0);
1561 wires_[wire->name] = wire;
1562 wire->module = this;
1563 }
1564
1565 void RTLIL::Module::add(RTLIL::Cell *cell)
1566 {
1567 log_assert(!cell->name.empty());
1568 log_assert(count_id(cell->name) == 0);
1569 log_assert(refcount_cells_ == 0);
1570 cells_[cell->name] = cell;
1571 cell->module = this;
1572 }
1573
1574 void RTLIL::Module::remove(const pool<RTLIL::Wire*> &wires)
1575 {
1576 log_assert(refcount_wires_ == 0);
1577
1578 struct DeleteWireWorker
1579 {
1580 RTLIL::Module *module;
1581 const pool<RTLIL::Wire*> *wires_p;
1582
1583 void operator()(RTLIL::SigSpec &sig) {
1584 std::vector<RTLIL::SigChunk> chunks = sig;
1585 for (auto &c : chunks)
1586 if (c.wire != NULL && wires_p->count(c.wire)) {
1587 c.wire = module->addWire(NEW_ID, c.width);
1588 c.offset = 0;
1589 }
1590 sig = chunks;
1591 }
1592
1593 void operator()(RTLIL::SigSpec &lhs, RTLIL::SigSpec &rhs) {
1594 log_assert(GetSize(lhs) == GetSize(rhs));
1595 RTLIL::SigSpec new_lhs, new_rhs;
1596 for (int i = 0; i < GetSize(lhs); i++) {
1597 RTLIL::SigBit lhs_bit = lhs[i];
1598 if (lhs_bit.wire != nullptr && wires_p->count(lhs_bit.wire))
1599 continue;
1600 RTLIL::SigBit rhs_bit = rhs[i];
1601 if (rhs_bit.wire != nullptr && wires_p->count(rhs_bit.wire))
1602 continue;
1603 new_lhs.append(lhs_bit);
1604 new_rhs.append(rhs_bit);
1605 }
1606 lhs = new_lhs;
1607 rhs = new_rhs;
1608 }
1609 };
1610
1611 DeleteWireWorker delete_wire_worker;
1612 delete_wire_worker.module = this;
1613 delete_wire_worker.wires_p = &wires;
1614 rewrite_sigspecs2(delete_wire_worker);
1615
1616 for (auto &it : wires) {
1617 log_assert(wires_.count(it->name) != 0);
1618 wires_.erase(it->name);
1619 delete it;
1620 }
1621 }
1622
1623 void RTLIL::Module::remove(RTLIL::Cell *cell)
1624 {
1625 while (!cell->connections_.empty())
1626 cell->unsetPort(cell->connections_.begin()->first);
1627
1628 log_assert(cells_.count(cell->name) != 0);
1629 log_assert(refcount_cells_ == 0);
1630 cells_.erase(cell->name);
1631 delete cell;
1632 }
1633
1634 void RTLIL::Module::rename(RTLIL::Wire *wire, RTLIL::IdString new_name)
1635 {
1636 log_assert(wires_[wire->name] == wire);
1637 log_assert(refcount_wires_ == 0);
1638 wires_.erase(wire->name);
1639 wire->name = new_name;
1640 add(wire);
1641 }
1642
1643 void RTLIL::Module::rename(RTLIL::Cell *cell, RTLIL::IdString new_name)
1644 {
1645 log_assert(cells_[cell->name] == cell);
1646 log_assert(refcount_wires_ == 0);
1647 cells_.erase(cell->name);
1648 cell->name = new_name;
1649 add(cell);
1650 }
1651
1652 void RTLIL::Module::rename(RTLIL::IdString old_name, RTLIL::IdString new_name)
1653 {
1654 log_assert(count_id(old_name) != 0);
1655 if (wires_.count(old_name))
1656 rename(wires_.at(old_name), new_name);
1657 else if (cells_.count(old_name))
1658 rename(cells_.at(old_name), new_name);
1659 else
1660 log_abort();
1661 }
1662
1663 void RTLIL::Module::swap_names(RTLIL::Wire *w1, RTLIL::Wire *w2)
1664 {
1665 log_assert(wires_[w1->name] == w1);
1666 log_assert(wires_[w2->name] == w2);
1667 log_assert(refcount_wires_ == 0);
1668
1669 wires_.erase(w1->name);
1670 wires_.erase(w2->name);
1671
1672 std::swap(w1->name, w2->name);
1673
1674 wires_[w1->name] = w1;
1675 wires_[w2->name] = w2;
1676 }
1677
1678 void RTLIL::Module::swap_names(RTLIL::Cell *c1, RTLIL::Cell *c2)
1679 {
1680 log_assert(cells_[c1->name] == c1);
1681 log_assert(cells_[c2->name] == c2);
1682 log_assert(refcount_cells_ == 0);
1683
1684 cells_.erase(c1->name);
1685 cells_.erase(c2->name);
1686
1687 std::swap(c1->name, c2->name);
1688
1689 cells_[c1->name] = c1;
1690 cells_[c2->name] = c2;
1691 }
1692
1693 RTLIL::IdString RTLIL::Module::uniquify(RTLIL::IdString name)
1694 {
1695 int index = 0;
1696 return uniquify(name, index);
1697 }
1698
1699 RTLIL::IdString RTLIL::Module::uniquify(RTLIL::IdString name, int &index)
1700 {
1701 if (index == 0) {
1702 if (count_id(name) == 0)
1703 return name;
1704 index++;
1705 }
1706
1707 while (1) {
1708 RTLIL::IdString new_name = stringf("%s_%d", name.c_str(), index);
1709 if (count_id(new_name) == 0)
1710 return new_name;
1711 index++;
1712 }
1713 }
1714
1715 static bool fixup_ports_compare(const RTLIL::Wire *a, const RTLIL::Wire *b)
1716 {
1717 if (a->port_id && !b->port_id)
1718 return true;
1719 if (!a->port_id && b->port_id)
1720 return false;
1721
1722 if (a->port_id == b->port_id)
1723 return a->name < b->name;
1724 return a->port_id < b->port_id;
1725 }
1726
1727 void RTLIL::Module::connect(const RTLIL::SigSig &conn)
1728 {
1729 for (auto mon : monitors)
1730 mon->notify_connect(this, conn);
1731
1732 if (design)
1733 for (auto mon : design->monitors)
1734 mon->notify_connect(this, conn);
1735
1736 // ignore all attempts to assign constants to other constants
1737 if (conn.first.has_const()) {
1738 RTLIL::SigSig new_conn;
1739 for (int i = 0; i < GetSize(conn.first); i++)
1740 if (conn.first[i].wire) {
1741 new_conn.first.append(conn.first[i]);
1742 new_conn.second.append(conn.second[i]);
1743 }
1744 if (GetSize(new_conn.first))
1745 connect(new_conn);
1746 return;
1747 }
1748
1749 if (yosys_xtrace) {
1750 log("#X# Connect (SigSig) in %s: %s = %s (%d bits)\n", log_id(this), log_signal(conn.first), log_signal(conn.second), GetSize(conn.first));
1751 log_backtrace("-X- ", yosys_xtrace-1);
1752 }
1753
1754 log_assert(GetSize(conn.first) == GetSize(conn.second));
1755 connections_.push_back(conn);
1756 }
1757
1758 void RTLIL::Module::connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs)
1759 {
1760 connect(RTLIL::SigSig(lhs, rhs));
1761 }
1762
1763 void RTLIL::Module::new_connections(const std::vector<RTLIL::SigSig> &new_conn)
1764 {
1765 for (auto mon : monitors)
1766 mon->notify_connect(this, new_conn);
1767
1768 if (design)
1769 for (auto mon : design->monitors)
1770 mon->notify_connect(this, new_conn);
1771
1772 if (yosys_xtrace) {
1773 log("#X# New connections vector in %s:\n", log_id(this));
1774 for (auto &conn: new_conn)
1775 log("#X# %s = %s (%d bits)\n", log_signal(conn.first), log_signal(conn.second), GetSize(conn.first));
1776 log_backtrace("-X- ", yosys_xtrace-1);
1777 }
1778
1779 connections_ = new_conn;
1780 }
1781
1782 const std::vector<RTLIL::SigSig> &RTLIL::Module::connections() const
1783 {
1784 return connections_;
1785 }
1786
1787 void RTLIL::Module::fixup_ports()
1788 {
1789 std::vector<RTLIL::Wire*> all_ports;
1790
1791 for (auto &w : wires_)
1792 if (w.second->port_input || w.second->port_output)
1793 all_ports.push_back(w.second);
1794 else
1795 w.second->port_id = 0;
1796
1797 std::sort(all_ports.begin(), all_ports.end(), fixup_ports_compare);
1798
1799 ports.clear();
1800 for (size_t i = 0; i < all_ports.size(); i++) {
1801 ports.push_back(all_ports[i]->name);
1802 all_ports[i]->port_id = i+1;
1803 }
1804 }
1805
1806 RTLIL::Wire *RTLIL::Module::addWire(RTLIL::IdString name, int width)
1807 {
1808 RTLIL::Wire *wire = new RTLIL::Wire;
1809 wire->name = name;
1810 wire->width = width;
1811 add(wire);
1812 return wire;
1813 }
1814
1815 RTLIL::Wire *RTLIL::Module::addWire(RTLIL::IdString name, const RTLIL::Wire *other)
1816 {
1817 RTLIL::Wire *wire = addWire(name);
1818 wire->width = other->width;
1819 wire->start_offset = other->start_offset;
1820 wire->port_id = other->port_id;
1821 wire->port_input = other->port_input;
1822 wire->port_output = other->port_output;
1823 wire->upto = other->upto;
1824 wire->attributes = other->attributes;
1825 return wire;
1826 }
1827
1828 RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, RTLIL::IdString type)
1829 {
1830 RTLIL::Cell *cell = new RTLIL::Cell;
1831 cell->name = name;
1832 cell->type = type;
1833 add(cell);
1834 return cell;
1835 }
1836
1837 RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, const RTLIL::Cell *other)
1838 {
1839 RTLIL::Cell *cell = addCell(name, other->type);
1840 cell->connections_ = other->connections_;
1841 cell->parameters = other->parameters;
1842 cell->attributes = other->attributes;
1843 return cell;
1844 }
1845
1846 #define DEF_METHOD(_func, _y_size, _type) \
1847 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed, const std::string &src) { \
1848 RTLIL::Cell *cell = addCell(name, _type); \
1849 cell->parameters[ID(A_SIGNED)] = is_signed; \
1850 cell->parameters[ID(A_WIDTH)] = sig_a.size(); \
1851 cell->parameters[ID(Y_WIDTH)] = sig_y.size(); \
1852 cell->setPort(ID::A, sig_a); \
1853 cell->setPort(ID::Y, sig_y); \
1854 cell->set_src_attribute(src); \
1855 return cell; \
1856 } \
1857 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed, const std::string &src) { \
1858 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
1859 add ## _func(name, sig_a, sig_y, is_signed, src); \
1860 return sig_y; \
1861 }
1862 DEF_METHOD(Not, sig_a.size(), ID($not))
1863 DEF_METHOD(Pos, sig_a.size(), ID($pos))
1864 DEF_METHOD(Neg, sig_a.size(), ID($neg))
1865 DEF_METHOD(ReduceAnd, 1, ID($reduce_and))
1866 DEF_METHOD(ReduceOr, 1, ID($reduce_or))
1867 DEF_METHOD(ReduceXor, 1, ID($reduce_xor))
1868 DEF_METHOD(ReduceXnor, 1, ID($reduce_xnor))
1869 DEF_METHOD(ReduceBool, 1, ID($reduce_bool))
1870 DEF_METHOD(LogicNot, 1, ID($logic_not))
1871 #undef DEF_METHOD
1872
1873 #define DEF_METHOD(_func, _y_size, _type) \
1874 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed, const std::string &src) { \
1875 RTLIL::Cell *cell = addCell(name, _type); \
1876 cell->parameters[ID(A_SIGNED)] = is_signed; \
1877 cell->parameters[ID(B_SIGNED)] = is_signed; \
1878 cell->parameters[ID(A_WIDTH)] = sig_a.size(); \
1879 cell->parameters[ID(B_WIDTH)] = sig_b.size(); \
1880 cell->parameters[ID(Y_WIDTH)] = sig_y.size(); \
1881 cell->setPort(ID::A, sig_a); \
1882 cell->setPort(ID::B, sig_b); \
1883 cell->setPort(ID::Y, sig_y); \
1884 cell->set_src_attribute(src); \
1885 return cell; \
1886 } \
1887 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed, const std::string &src) { \
1888 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
1889 add ## _func(name, sig_a, sig_b, sig_y, is_signed, src); \
1890 return sig_y; \
1891 }
1892 DEF_METHOD(And, max(sig_a.size(), sig_b.size()), ID($and))
1893 DEF_METHOD(Or, max(sig_a.size(), sig_b.size()), ID($or))
1894 DEF_METHOD(Xor, max(sig_a.size(), sig_b.size()), ID($xor))
1895 DEF_METHOD(Xnor, max(sig_a.size(), sig_b.size()), ID($xnor))
1896 DEF_METHOD(Shift, sig_a.size(), ID($shift))
1897 DEF_METHOD(Shiftx, sig_a.size(), ID($shiftx))
1898 DEF_METHOD(Lt, 1, ID($lt))
1899 DEF_METHOD(Le, 1, ID($le))
1900 DEF_METHOD(Eq, 1, ID($eq))
1901 DEF_METHOD(Ne, 1, ID($ne))
1902 DEF_METHOD(Eqx, 1, ID($eqx))
1903 DEF_METHOD(Nex, 1, ID($nex))
1904 DEF_METHOD(Ge, 1, ID($ge))
1905 DEF_METHOD(Gt, 1, ID($gt))
1906 DEF_METHOD(Add, max(sig_a.size(), sig_b.size()), ID($add))
1907 DEF_METHOD(Sub, max(sig_a.size(), sig_b.size()), ID($sub))
1908 DEF_METHOD(Mul, max(sig_a.size(), sig_b.size()), ID($mul))
1909 DEF_METHOD(Div, max(sig_a.size(), sig_b.size()), ID($div))
1910 DEF_METHOD(Mod, max(sig_a.size(), sig_b.size()), ID($mod))
1911 DEF_METHOD(LogicAnd, 1, ID($logic_and))
1912 DEF_METHOD(LogicOr, 1, ID($logic_or))
1913 #undef DEF_METHOD
1914
1915 #define DEF_METHOD(_func, _y_size, _type) \
1916 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed, const std::string &src) { \
1917 RTLIL::Cell *cell = addCell(name, _type); \
1918 cell->parameters[ID(A_SIGNED)] = is_signed; \
1919 cell->parameters[ID(B_SIGNED)] = false; \
1920 cell->parameters[ID(A_WIDTH)] = sig_a.size(); \
1921 cell->parameters[ID(B_WIDTH)] = sig_b.size(); \
1922 cell->parameters[ID(Y_WIDTH)] = sig_y.size(); \
1923 cell->setPort(ID::A, sig_a); \
1924 cell->setPort(ID::B, sig_b); \
1925 cell->setPort(ID::Y, sig_y); \
1926 cell->set_src_attribute(src); \
1927 return cell; \
1928 } \
1929 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed, const std::string &src) { \
1930 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
1931 add ## _func(name, sig_a, sig_b, sig_y, is_signed, src); \
1932 return sig_y; \
1933 }
1934 DEF_METHOD(Shl, sig_a.size(), ID($shl))
1935 DEF_METHOD(Shr, sig_a.size(), ID($shr))
1936 DEF_METHOD(Sshl, sig_a.size(), ID($sshl))
1937 DEF_METHOD(Sshr, sig_a.size(), ID($sshr))
1938 #undef DEF_METHOD
1939
1940 #define DEF_METHOD(_func, _type, _pmux) \
1941 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, RTLIL::SigSpec sig_y, const std::string &src) { \
1942 RTLIL::Cell *cell = addCell(name, _type); \
1943 cell->parameters[ID(WIDTH)] = sig_a.size(); \
1944 if (_pmux) cell->parameters[ID(S_WIDTH)] = sig_s.size(); \
1945 cell->setPort(ID::A, sig_a); \
1946 cell->setPort(ID::B, sig_b); \
1947 cell->setPort(ID(S), sig_s); \
1948 cell->setPort(ID::Y, sig_y); \
1949 cell->set_src_attribute(src); \
1950 return cell; \
1951 } \
1952 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, const std::string &src) { \
1953 RTLIL::SigSpec sig_y = addWire(NEW_ID, sig_a.size()); \
1954 add ## _func(name, sig_a, sig_b, sig_s, sig_y, src); \
1955 return sig_y; \
1956 }
1957 DEF_METHOD(Mux, ID($mux), 0)
1958 DEF_METHOD(Pmux, ID($pmux), 1)
1959 #undef DEF_METHOD
1960
1961 #define DEF_METHOD_2(_func, _type, _P1, _P2) \
1962 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, const std::string &src) { \
1963 RTLIL::Cell *cell = addCell(name, _type); \
1964 cell->setPort("\\" #_P1, sig1); \
1965 cell->setPort("\\" #_P2, sig2); \
1966 cell->set_src_attribute(src); \
1967 return cell; \
1968 } \
1969 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, const std::string &src) { \
1970 RTLIL::SigBit sig2 = addWire(NEW_ID); \
1971 add ## _func(name, sig1, sig2, src); \
1972 return sig2; \
1973 }
1974 #define DEF_METHOD_3(_func, _type, _P1, _P2, _P3) \
1975 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, const std::string &src) { \
1976 RTLIL::Cell *cell = addCell(name, _type); \
1977 cell->setPort("\\" #_P1, sig1); \
1978 cell->setPort("\\" #_P2, sig2); \
1979 cell->setPort("\\" #_P3, sig3); \
1980 cell->set_src_attribute(src); \
1981 return cell; \
1982 } \
1983 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, const std::string &src) { \
1984 RTLIL::SigBit sig3 = addWire(NEW_ID); \
1985 add ## _func(name, sig1, sig2, sig3, src); \
1986 return sig3; \
1987 }
1988 #define DEF_METHOD_4(_func, _type, _P1, _P2, _P3, _P4) \
1989 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, RTLIL::SigBit sig4, const std::string &src) { \
1990 RTLIL::Cell *cell = addCell(name, _type); \
1991 cell->setPort("\\" #_P1, sig1); \
1992 cell->setPort("\\" #_P2, sig2); \
1993 cell->setPort("\\" #_P3, sig3); \
1994 cell->setPort("\\" #_P4, sig4); \
1995 cell->set_src_attribute(src); \
1996 return cell; \
1997 } \
1998 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, const std::string &src) { \
1999 RTLIL::SigBit sig4 = addWire(NEW_ID); \
2000 add ## _func(name, sig1, sig2, sig3, sig4, src); \
2001 return sig4; \
2002 }
2003 #define DEF_METHOD_5(_func, _type, _P1, _P2, _P3, _P4, _P5) \
2004 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, RTLIL::SigBit sig4, RTLIL::SigBit sig5, const std::string &src) { \
2005 RTLIL::Cell *cell = addCell(name, _type); \
2006 cell->setPort("\\" #_P1, sig1); \
2007 cell->setPort("\\" #_P2, sig2); \
2008 cell->setPort("\\" #_P3, sig3); \
2009 cell->setPort("\\" #_P4, sig4); \
2010 cell->setPort("\\" #_P5, sig5); \
2011 cell->set_src_attribute(src); \
2012 return cell; \
2013 } \
2014 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, RTLIL::SigBit sig4, const std::string &src) { \
2015 RTLIL::SigBit sig5 = addWire(NEW_ID); \
2016 add ## _func(name, sig1, sig2, sig3, sig4, sig5, src); \
2017 return sig5; \
2018 }
2019 DEF_METHOD_2(BufGate, ID($_BUF_), A, Y)
2020 DEF_METHOD_2(NotGate, ID($_NOT_), A, Y)
2021 DEF_METHOD_3(AndGate, ID($_AND_), A, B, Y)
2022 DEF_METHOD_3(NandGate, ID($_NAND_), A, B, Y)
2023 DEF_METHOD_3(OrGate, ID($_OR_), A, B, Y)
2024 DEF_METHOD_3(NorGate, ID($_NOR_), A, B, Y)
2025 DEF_METHOD_3(XorGate, ID($_XOR_), A, B, Y)
2026 DEF_METHOD_3(XnorGate, ID($_XNOR_), A, B, Y)
2027 DEF_METHOD_3(AndnotGate, ID($_ANDNOT_), A, B, Y)
2028 DEF_METHOD_3(OrnotGate, ID($_ORNOT_), A, B, Y)
2029 DEF_METHOD_4(MuxGate, ID($_MUX_), A, B, S, Y)
2030 DEF_METHOD_4(NmuxGate, ID($_NMUX_), A, B, S, Y)
2031 DEF_METHOD_4(Aoi3Gate, ID($_AOI3_), A, B, C, Y)
2032 DEF_METHOD_4(Oai3Gate, ID($_OAI3_), A, B, C, Y)
2033 DEF_METHOD_5(Aoi4Gate, ID($_AOI4_), A, B, C, D, Y)
2034 DEF_METHOD_5(Oai4Gate, ID($_OAI4_), A, B, C, D, Y)
2035 #undef DEF_METHOD_2
2036 #undef DEF_METHOD_3
2037 #undef DEF_METHOD_4
2038 #undef DEF_METHOD_5
2039
2040 RTLIL::Cell* RTLIL::Module::addPow(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool a_signed, bool b_signed, const std::string &src)
2041 {
2042 RTLIL::Cell *cell = addCell(name, ID($pow));
2043 cell->parameters[ID(A_SIGNED)] = a_signed;
2044 cell->parameters[ID(B_SIGNED)] = b_signed;
2045 cell->parameters[ID(A_WIDTH)] = sig_a.size();
2046 cell->parameters[ID(B_WIDTH)] = sig_b.size();
2047 cell->parameters[ID(Y_WIDTH)] = sig_y.size();
2048 cell->setPort(ID::A, sig_a);
2049 cell->setPort(ID::B, sig_b);
2050 cell->setPort(ID::Y, sig_y);
2051 cell->set_src_attribute(src);
2052 return cell;
2053 }
2054
2055 RTLIL::Cell* RTLIL::Module::addSlice(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, RTLIL::Const offset, const std::string &src)
2056 {
2057 RTLIL::Cell *cell = addCell(name, ID($slice));
2058 cell->parameters[ID(A_WIDTH)] = sig_a.size();
2059 cell->parameters[ID(Y_WIDTH)] = sig_y.size();
2060 cell->parameters[ID(OFFSET)] = offset;
2061 cell->setPort(ID::A, sig_a);
2062 cell->setPort(ID::Y, sig_y);
2063 cell->set_src_attribute(src);
2064 return cell;
2065 }
2066
2067 RTLIL::Cell* RTLIL::Module::addConcat(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, const std::string &src)
2068 {
2069 RTLIL::Cell *cell = addCell(name, ID($concat));
2070 cell->parameters[ID(A_WIDTH)] = sig_a.size();
2071 cell->parameters[ID(B_WIDTH)] = sig_b.size();
2072 cell->setPort(ID::A, sig_a);
2073 cell->setPort(ID::B, sig_b);
2074 cell->setPort(ID::Y, sig_y);
2075 cell->set_src_attribute(src);
2076 return cell;
2077 }
2078
2079 RTLIL::Cell* RTLIL::Module::addLut(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, RTLIL::Const lut, const std::string &src)
2080 {
2081 RTLIL::Cell *cell = addCell(name, ID($lut));
2082 cell->parameters[ID(LUT)] = lut;
2083 cell->parameters[ID(WIDTH)] = sig_a.size();
2084 cell->setPort(ID::A, sig_a);
2085 cell->setPort(ID::Y, sig_y);
2086 cell->set_src_attribute(src);
2087 return cell;
2088 }
2089
2090 RTLIL::Cell* RTLIL::Module::addTribuf(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_y, const std::string &src)
2091 {
2092 RTLIL::Cell *cell = addCell(name, ID($tribuf));
2093 cell->parameters[ID(WIDTH)] = sig_a.size();
2094 cell->setPort(ID::A, sig_a);
2095 cell->setPort(ID(EN), sig_en);
2096 cell->setPort(ID::Y, sig_y);
2097 cell->set_src_attribute(src);
2098 return cell;
2099 }
2100
2101 RTLIL::Cell* RTLIL::Module::addAssert(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src)
2102 {
2103 RTLIL::Cell *cell = addCell(name, ID($assert));
2104 cell->setPort(ID::A, sig_a);
2105 cell->setPort(ID(EN), sig_en);
2106 cell->set_src_attribute(src);
2107 return cell;
2108 }
2109
2110 RTLIL::Cell* RTLIL::Module::addAssume(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src)
2111 {
2112 RTLIL::Cell *cell = addCell(name, ID($assume));
2113 cell->setPort(ID::A, sig_a);
2114 cell->setPort(ID(EN), sig_en);
2115 cell->set_src_attribute(src);
2116 return cell;
2117 }
2118
2119 RTLIL::Cell* RTLIL::Module::addLive(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src)
2120 {
2121 RTLIL::Cell *cell = addCell(name, ID($live));
2122 cell->setPort(ID::A, sig_a);
2123 cell->setPort(ID(EN), sig_en);
2124 cell->set_src_attribute(src);
2125 return cell;
2126 }
2127
2128 RTLIL::Cell* RTLIL::Module::addFair(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src)
2129 {
2130 RTLIL::Cell *cell = addCell(name, ID($fair));
2131 cell->setPort(ID::A, sig_a);
2132 cell->setPort(ID(EN), sig_en);
2133 cell->set_src_attribute(src);
2134 return cell;
2135 }
2136
2137 RTLIL::Cell* RTLIL::Module::addCover(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src)
2138 {
2139 RTLIL::Cell *cell = addCell(name, ID($cover));
2140 cell->setPort(ID::A, sig_a);
2141 cell->setPort(ID(EN), sig_en);
2142 cell->set_src_attribute(src);
2143 return cell;
2144 }
2145
2146 RTLIL::Cell* RTLIL::Module::addEquiv(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, const std::string &src)
2147 {
2148 RTLIL::Cell *cell = addCell(name, ID($equiv));
2149 cell->setPort(ID::A, sig_a);
2150 cell->setPort(ID::B, sig_b);
2151 cell->setPort(ID::Y, sig_y);
2152 cell->set_src_attribute(src);
2153 return cell;
2154 }
2155
2156 RTLIL::Cell* RTLIL::Module::addSr(RTLIL::IdString name, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr, RTLIL::SigSpec sig_q, bool set_polarity, bool clr_polarity, const std::string &src)
2157 {
2158 RTLIL::Cell *cell = addCell(name, ID($sr));
2159 cell->parameters[ID(SET_POLARITY)] = set_polarity;
2160 cell->parameters[ID(CLR_POLARITY)] = clr_polarity;
2161 cell->parameters[ID(WIDTH)] = sig_q.size();
2162 cell->setPort(ID(SET), sig_set);
2163 cell->setPort(ID(CLR), sig_clr);
2164 cell->setPort(ID(Q), sig_q);
2165 cell->set_src_attribute(src);
2166 return cell;
2167 }
2168
2169 RTLIL::Cell* RTLIL::Module::addFf(RTLIL::IdString name, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, const std::string &src)
2170 {
2171 RTLIL::Cell *cell = addCell(name, ID($ff));
2172 cell->parameters[ID(WIDTH)] = sig_q.size();
2173 cell->setPort(ID(D), sig_d);
2174 cell->setPort(ID(Q), sig_q);
2175 cell->set_src_attribute(src);
2176 return cell;
2177 }
2178
2179 RTLIL::Cell* RTLIL::Module::addDff(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, const std::string &src)
2180 {
2181 RTLIL::Cell *cell = addCell(name, ID($dff));
2182 cell->parameters[ID(CLK_POLARITY)] = clk_polarity;
2183 cell->parameters[ID(WIDTH)] = sig_q.size();
2184 cell->setPort(ID(CLK), sig_clk);
2185 cell->setPort(ID(D), sig_d);
2186 cell->setPort(ID(Q), sig_q);
2187 cell->set_src_attribute(src);
2188 return cell;
2189 }
2190
2191 RTLIL::Cell* RTLIL::Module::addDffe(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, bool en_polarity, const std::string &src)
2192 {
2193 RTLIL::Cell *cell = addCell(name, ID($dffe));
2194 cell->parameters[ID(CLK_POLARITY)] = clk_polarity;
2195 cell->parameters[ID(EN_POLARITY)] = en_polarity;
2196 cell->parameters[ID(WIDTH)] = sig_q.size();
2197 cell->setPort(ID(CLK), sig_clk);
2198 cell->setPort(ID(EN), sig_en);
2199 cell->setPort(ID(D), sig_d);
2200 cell->setPort(ID(Q), sig_q);
2201 cell->set_src_attribute(src);
2202 return cell;
2203 }
2204
2205 RTLIL::Cell* RTLIL::Module::addDffsr(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
2206 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
2207 {
2208 RTLIL::Cell *cell = addCell(name, ID($dffsr));
2209 cell->parameters[ID(CLK_POLARITY)] = clk_polarity;
2210 cell->parameters[ID(SET_POLARITY)] = set_polarity;
2211 cell->parameters[ID(CLR_POLARITY)] = clr_polarity;
2212 cell->parameters[ID(WIDTH)] = sig_q.size();
2213 cell->setPort(ID(CLK), sig_clk);
2214 cell->setPort(ID(SET), sig_set);
2215 cell->setPort(ID(CLR), sig_clr);
2216 cell->setPort(ID(D), sig_d);
2217 cell->setPort(ID(Q), sig_q);
2218 cell->set_src_attribute(src);
2219 return cell;
2220 }
2221
2222 RTLIL::Cell* RTLIL::Module::addAdff(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_arst, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q,
2223 RTLIL::Const arst_value, bool clk_polarity, bool arst_polarity, const std::string &src)
2224 {
2225 RTLIL::Cell *cell = addCell(name, ID($adff));
2226 cell->parameters[ID(CLK_POLARITY)] = clk_polarity;
2227 cell->parameters[ID(ARST_POLARITY)] = arst_polarity;
2228 cell->parameters[ID(ARST_VALUE)] = arst_value;
2229 cell->parameters[ID(WIDTH)] = sig_q.size();
2230 cell->setPort(ID(CLK), sig_clk);
2231 cell->setPort(ID(ARST), sig_arst);
2232 cell->setPort(ID(D), sig_d);
2233 cell->setPort(ID(Q), sig_q);
2234 cell->set_src_attribute(src);
2235 return cell;
2236 }
2237
2238 RTLIL::Cell* RTLIL::Module::addDlatch(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity, const std::string &src)
2239 {
2240 RTLIL::Cell *cell = addCell(name, ID($dlatch));
2241 cell->parameters[ID(EN_POLARITY)] = en_polarity;
2242 cell->parameters[ID(WIDTH)] = sig_q.size();
2243 cell->setPort(ID(EN), sig_en);
2244 cell->setPort(ID(D), sig_d);
2245 cell->setPort(ID(Q), sig_q);
2246 cell->set_src_attribute(src);
2247 return cell;
2248 }
2249
2250 RTLIL::Cell* RTLIL::Module::addDlatchsr(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
2251 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
2252 {
2253 RTLIL::Cell *cell = addCell(name, ID($dlatchsr));
2254 cell->parameters[ID(EN_POLARITY)] = en_polarity;
2255 cell->parameters[ID(SET_POLARITY)] = set_polarity;
2256 cell->parameters[ID(CLR_POLARITY)] = clr_polarity;
2257 cell->parameters[ID(WIDTH)] = sig_q.size();
2258 cell->setPort(ID(EN), sig_en);
2259 cell->setPort(ID(SET), sig_set);
2260 cell->setPort(ID(CLR), sig_clr);
2261 cell->setPort(ID(D), sig_d);
2262 cell->setPort(ID(Q), sig_q);
2263 cell->set_src_attribute(src);
2264 return cell;
2265 }
2266
2267 RTLIL::Cell* RTLIL::Module::addFfGate(RTLIL::IdString name, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, const std::string &src)
2268 {
2269 RTLIL::Cell *cell = addCell(name, ID($_FF_));
2270 cell->setPort(ID(D), sig_d);
2271 cell->setPort(ID(Q), sig_q);
2272 cell->set_src_attribute(src);
2273 return cell;
2274 }
2275
2276 RTLIL::Cell* RTLIL::Module::addDffGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, const std::string &src)
2277 {
2278 RTLIL::Cell *cell = addCell(name, stringf("$_DFF_%c_", clk_polarity ? 'P' : 'N'));
2279 cell->setPort(ID(C), sig_clk);
2280 cell->setPort(ID(D), sig_d);
2281 cell->setPort(ID(Q), sig_q);
2282 cell->set_src_attribute(src);
2283 return cell;
2284 }
2285
2286 RTLIL::Cell* RTLIL::Module::addDffeGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, bool en_polarity, const std::string &src)
2287 {
2288 RTLIL::Cell *cell = addCell(name, stringf("$_DFFE_%c%c_", clk_polarity ? 'P' : 'N', en_polarity ? 'P' : 'N'));
2289 cell->setPort(ID(C), sig_clk);
2290 cell->setPort(ID(E), sig_en);
2291 cell->setPort(ID(D), sig_d);
2292 cell->setPort(ID(Q), sig_q);
2293 cell->set_src_attribute(src);
2294 return cell;
2295 }
2296
2297 RTLIL::Cell* RTLIL::Module::addDffsrGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
2298 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
2299 {
2300 RTLIL::Cell *cell = addCell(name, stringf("$_DFFSR_%c%c%c_", clk_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N'));
2301 cell->setPort(ID(C), sig_clk);
2302 cell->setPort(ID(S), sig_set);
2303 cell->setPort(ID(R), sig_clr);
2304 cell->setPort(ID(D), sig_d);
2305 cell->setPort(ID(Q), sig_q);
2306 cell->set_src_attribute(src);
2307 return cell;
2308 }
2309
2310 RTLIL::Cell* RTLIL::Module::addAdffGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_arst, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q,
2311 bool arst_value, bool clk_polarity, bool arst_polarity, const std::string &src)
2312 {
2313 RTLIL::Cell *cell = addCell(name, stringf("$_DFF_%c%c%c_", clk_polarity ? 'P' : 'N', arst_polarity ? 'P' : 'N', arst_value ? '1' : '0'));
2314 cell->setPort(ID(C), sig_clk);
2315 cell->setPort(ID(R), sig_arst);
2316 cell->setPort(ID(D), sig_d);
2317 cell->setPort(ID(Q), sig_q);
2318 cell->set_src_attribute(src);
2319 return cell;
2320 }
2321
2322 RTLIL::Cell* RTLIL::Module::addDlatchGate(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity, const std::string &src)
2323 {
2324 RTLIL::Cell *cell = addCell(name, stringf("$_DLATCH_%c_", en_polarity ? 'P' : 'N'));
2325 cell->setPort(ID(E), sig_en);
2326 cell->setPort(ID(D), sig_d);
2327 cell->setPort(ID(Q), sig_q);
2328 cell->set_src_attribute(src);
2329 return cell;
2330 }
2331
2332 RTLIL::Cell* RTLIL::Module::addDlatchsrGate(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
2333 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
2334 {
2335 RTLIL::Cell *cell = addCell(name, stringf("$_DLATCHSR_%c%c%c_", en_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N'));
2336 cell->setPort(ID(E), sig_en);
2337 cell->setPort(ID(S), sig_set);
2338 cell->setPort(ID(R), sig_clr);
2339 cell->setPort(ID(D), sig_d);
2340 cell->setPort(ID(Q), sig_q);
2341 cell->set_src_attribute(src);
2342 return cell;
2343 }
2344
2345 RTLIL::SigSpec RTLIL::Module::Anyconst(RTLIL::IdString name, int width, const std::string &src)
2346 {
2347 RTLIL::SigSpec sig = addWire(NEW_ID, width);
2348 Cell *cell = addCell(name, ID($anyconst));
2349 cell->setParam(ID(WIDTH), width);
2350 cell->setPort(ID::Y, sig);
2351 cell->set_src_attribute(src);
2352 return sig;
2353 }
2354
2355 RTLIL::SigSpec RTLIL::Module::Anyseq(RTLIL::IdString name, int width, const std::string &src)
2356 {
2357 RTLIL::SigSpec sig = addWire(NEW_ID, width);
2358 Cell *cell = addCell(name, ID($anyseq));
2359 cell->setParam(ID(WIDTH), width);
2360 cell->setPort(ID::Y, sig);
2361 cell->set_src_attribute(src);
2362 return sig;
2363 }
2364
2365 RTLIL::SigSpec RTLIL::Module::Allconst(RTLIL::IdString name, int width, const std::string &src)
2366 {
2367 RTLIL::SigSpec sig = addWire(NEW_ID, width);
2368 Cell *cell = addCell(name, ID($allconst));
2369 cell->setParam(ID(WIDTH), width);
2370 cell->setPort(ID::Y, sig);
2371 cell->set_src_attribute(src);
2372 return sig;
2373 }
2374
2375 RTLIL::SigSpec RTLIL::Module::Allseq(RTLIL::IdString name, int width, const std::string &src)
2376 {
2377 RTLIL::SigSpec sig = addWire(NEW_ID, width);
2378 Cell *cell = addCell(name, ID($allseq));
2379 cell->setParam(ID(WIDTH), width);
2380 cell->setPort(ID::Y, sig);
2381 cell->set_src_attribute(src);
2382 return sig;
2383 }
2384
2385 RTLIL::SigSpec RTLIL::Module::Initstate(RTLIL::IdString name, const std::string &src)
2386 {
2387 RTLIL::SigSpec sig = addWire(NEW_ID);
2388 Cell *cell = addCell(name, ID($initstate));
2389 cell->setPort(ID::Y, sig);
2390 cell->set_src_attribute(src);
2391 return sig;
2392 }
2393
2394 RTLIL::Wire::Wire()
2395 {
2396 static unsigned int hashidx_count = 123456789;
2397 hashidx_count = mkhash_xorshift(hashidx_count);
2398 hashidx_ = hashidx_count;
2399
2400 module = nullptr;
2401 width = 1;
2402 start_offset = 0;
2403 port_id = 0;
2404 port_input = false;
2405 port_output = false;
2406 upto = false;
2407
2408 #ifdef WITH_PYTHON
2409 RTLIL::Wire::get_all_wires()->insert(std::pair<unsigned int, RTLIL::Wire*>(hashidx_, this));
2410 #endif
2411 }
2412
2413 RTLIL::Wire::~Wire()
2414 {
2415 #ifdef WITH_PYTHON
2416 RTLIL::Wire::get_all_wires()->erase(hashidx_);
2417 #endif
2418 }
2419
2420 #ifdef WITH_PYTHON
2421 static std::map<unsigned int, RTLIL::Wire*> all_wires;
2422 std::map<unsigned int, RTLIL::Wire*> *RTLIL::Wire::get_all_wires(void)
2423 {
2424 return &all_wires;
2425 }
2426 #endif
2427
2428 RTLIL::Memory::Memory()
2429 {
2430 static unsigned int hashidx_count = 123456789;
2431 hashidx_count = mkhash_xorshift(hashidx_count);
2432 hashidx_ = hashidx_count;
2433
2434 width = 1;
2435 start_offset = 0;
2436 size = 0;
2437 #ifdef WITH_PYTHON
2438 RTLIL::Memory::get_all_memorys()->insert(std::pair<unsigned int, RTLIL::Memory*>(hashidx_, this));
2439 #endif
2440 }
2441
2442 RTLIL::Cell::Cell() : module(nullptr)
2443 {
2444 static unsigned int hashidx_count = 123456789;
2445 hashidx_count = mkhash_xorshift(hashidx_count);
2446 hashidx_ = hashidx_count;
2447
2448 // log("#memtrace# %p\n", this);
2449 memhasher();
2450
2451 #ifdef WITH_PYTHON
2452 RTLIL::Cell::get_all_cells()->insert(std::pair<unsigned int, RTLIL::Cell*>(hashidx_, this));
2453 #endif
2454 }
2455
2456 RTLIL::Cell::~Cell()
2457 {
2458 #ifdef WITH_PYTHON
2459 RTLIL::Cell::get_all_cells()->erase(hashidx_);
2460 #endif
2461 }
2462
2463 #ifdef WITH_PYTHON
2464 static std::map<unsigned int, RTLIL::Cell*> all_cells;
2465 std::map<unsigned int, RTLIL::Cell*> *RTLIL::Cell::get_all_cells(void)
2466 {
2467 return &all_cells;
2468 }
2469 #endif
2470
2471 bool RTLIL::Cell::hasPort(RTLIL::IdString portname) const
2472 {
2473 return connections_.count(portname) != 0;
2474 }
2475
2476 void RTLIL::Cell::unsetPort(RTLIL::IdString portname)
2477 {
2478 RTLIL::SigSpec signal;
2479 auto conn_it = connections_.find(portname);
2480
2481 if (conn_it != connections_.end())
2482 {
2483 for (auto mon : module->monitors)
2484 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
2485
2486 if (module->design)
2487 for (auto mon : module->design->monitors)
2488 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
2489
2490 if (yosys_xtrace) {
2491 log("#X# Unconnect %s.%s.%s\n", log_id(this->module), log_id(this), log_id(portname));
2492 log_backtrace("-X- ", yosys_xtrace-1);
2493 }
2494
2495 connections_.erase(conn_it);
2496 }
2497 }
2498
2499 void RTLIL::Cell::setPort(RTLIL::IdString portname, RTLIL::SigSpec signal)
2500 {
2501 auto conn_it = connections_.find(portname);
2502
2503 if (conn_it == connections_.end()) {
2504 connections_[portname] = RTLIL::SigSpec();
2505 conn_it = connections_.find(portname);
2506 log_assert(conn_it != connections_.end());
2507 } else
2508 if (conn_it->second == signal)
2509 return;
2510
2511 for (auto mon : module->monitors)
2512 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
2513
2514 if (module->design)
2515 for (auto mon : module->design->monitors)
2516 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
2517
2518 if (yosys_xtrace) {
2519 log("#X# Connect %s.%s.%s = %s (%d)\n", log_id(this->module), log_id(this), log_id(portname), log_signal(signal), GetSize(signal));
2520 log_backtrace("-X- ", yosys_xtrace-1);
2521 }
2522
2523 conn_it->second = signal;
2524 }
2525
2526 const RTLIL::SigSpec &RTLIL::Cell::getPort(RTLIL::IdString portname) const
2527 {
2528 return connections_.at(portname);
2529 }
2530
2531 const dict<RTLIL::IdString, RTLIL::SigSpec> &RTLIL::Cell::connections() const
2532 {
2533 return connections_;
2534 }
2535
2536 bool RTLIL::Cell::known() const
2537 {
2538 if (yosys_celltypes.cell_known(type))
2539 return true;
2540 if (module && module->design && module->design->module(type))
2541 return true;
2542 return false;
2543 }
2544
2545 bool RTLIL::Cell::input(RTLIL::IdString portname) const
2546 {
2547 if (yosys_celltypes.cell_known(type))
2548 return yosys_celltypes.cell_input(type, portname);
2549 if (module && module->design) {
2550 RTLIL::Module *m = module->design->module(type);
2551 RTLIL::Wire *w = m ? m->wire(portname) : nullptr;
2552 return w && w->port_input;
2553 }
2554 return false;
2555 }
2556
2557 bool RTLIL::Cell::output(RTLIL::IdString portname) const
2558 {
2559 if (yosys_celltypes.cell_known(type))
2560 return yosys_celltypes.cell_output(type, portname);
2561 if (module && module->design) {
2562 RTLIL::Module *m = module->design->module(type);
2563 RTLIL::Wire *w = m ? m->wire(portname) : nullptr;
2564 return w && w->port_output;
2565 }
2566 return false;
2567 }
2568
2569 bool RTLIL::Cell::hasParam(RTLIL::IdString paramname) const
2570 {
2571 return parameters.count(paramname) != 0;
2572 }
2573
2574 void RTLIL::Cell::unsetParam(RTLIL::IdString paramname)
2575 {
2576 parameters.erase(paramname);
2577 }
2578
2579 void RTLIL::Cell::setParam(RTLIL::IdString paramname, RTLIL::Const value)
2580 {
2581 parameters[paramname] = value;
2582 }
2583
2584 const RTLIL::Const &RTLIL::Cell::getParam(RTLIL::IdString paramname) const
2585 {
2586 return parameters.at(paramname);
2587 }
2588
2589 void RTLIL::Cell::sort()
2590 {
2591 connections_.sort(sort_by_id_str());
2592 parameters.sort(sort_by_id_str());
2593 attributes.sort(sort_by_id_str());
2594 }
2595
2596 void RTLIL::Cell::check()
2597 {
2598 #ifndef NDEBUG
2599 InternalCellChecker checker(NULL, this);
2600 checker.check();
2601 #endif
2602 }
2603
2604 void RTLIL::Cell::fixup_parameters(bool set_a_signed, bool set_b_signed)
2605 {
2606 if (!type.begins_with("$") || type.begins_with("$_") || type.begins_with("$paramod") || type.begins_with("$fmcombine") ||
2607 type.begins_with("$verific$") || type.begins_with("$array:") || type.begins_with("$extern:"))
2608 return;
2609
2610 if (type == ID($mux) || type == ID($pmux)) {
2611 parameters[ID(WIDTH)] = GetSize(connections_[ID::Y]);
2612 if (type == ID($pmux))
2613 parameters[ID(S_WIDTH)] = GetSize(connections_[ID(S)]);
2614 check();
2615 return;
2616 }
2617
2618 if (type == ID($lut) || type == ID($sop)) {
2619 parameters[ID(WIDTH)] = GetSize(connections_[ID::A]);
2620 return;
2621 }
2622
2623 if (type == ID($fa)) {
2624 parameters[ID(WIDTH)] = GetSize(connections_[ID::Y]);
2625 return;
2626 }
2627
2628 if (type == ID($lcu)) {
2629 parameters[ID(WIDTH)] = GetSize(connections_[ID(CO)]);
2630 return;
2631 }
2632
2633 bool signedness_ab = !type.in(ID($slice), ID($concat), ID($macc));
2634
2635 if (connections_.count(ID::A)) {
2636 if (signedness_ab) {
2637 if (set_a_signed)
2638 parameters[ID(A_SIGNED)] = true;
2639 else if (parameters.count(ID(A_SIGNED)) == 0)
2640 parameters[ID(A_SIGNED)] = false;
2641 }
2642 parameters[ID(A_WIDTH)] = GetSize(connections_[ID::A]);
2643 }
2644
2645 if (connections_.count(ID::B)) {
2646 if (signedness_ab) {
2647 if (set_b_signed)
2648 parameters[ID(B_SIGNED)] = true;
2649 else if (parameters.count(ID(B_SIGNED)) == 0)
2650 parameters[ID(B_SIGNED)] = false;
2651 }
2652 parameters[ID(B_WIDTH)] = GetSize(connections_[ID::B]);
2653 }
2654
2655 if (connections_.count(ID::Y))
2656 parameters[ID(Y_WIDTH)] = GetSize(connections_[ID::Y]);
2657
2658 if (connections_.count(ID(Q)))
2659 parameters[ID(WIDTH)] = GetSize(connections_[ID(Q)]);
2660
2661 check();
2662 }
2663
2664 RTLIL::SigChunk::SigChunk()
2665 {
2666 wire = NULL;
2667 width = 0;
2668 offset = 0;
2669 }
2670
2671 RTLIL::SigChunk::SigChunk(const RTLIL::Const &value)
2672 {
2673 wire = NULL;
2674 data = value.bits;
2675 width = GetSize(data);
2676 offset = 0;
2677 }
2678
2679 RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire)
2680 {
2681 log_assert(wire != nullptr);
2682 this->wire = wire;
2683 this->width = wire->width;
2684 this->offset = 0;
2685 }
2686
2687 RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire, int offset, int width)
2688 {
2689 log_assert(wire != nullptr);
2690 this->wire = wire;
2691 this->width = width;
2692 this->offset = offset;
2693 }
2694
2695 RTLIL::SigChunk::SigChunk(const std::string &str)
2696 {
2697 wire = NULL;
2698 data = RTLIL::Const(str).bits;
2699 width = GetSize(data);
2700 offset = 0;
2701 }
2702
2703 RTLIL::SigChunk::SigChunk(int val, int width)
2704 {
2705 wire = NULL;
2706 data = RTLIL::Const(val, width).bits;
2707 this->width = GetSize(data);
2708 offset = 0;
2709 }
2710
2711 RTLIL::SigChunk::SigChunk(RTLIL::State bit, int width)
2712 {
2713 wire = NULL;
2714 data = RTLIL::Const(bit, width).bits;
2715 this->width = GetSize(data);
2716 offset = 0;
2717 }
2718
2719 RTLIL::SigChunk::SigChunk(RTLIL::SigBit bit)
2720 {
2721 wire = bit.wire;
2722 offset = 0;
2723 if (wire == NULL)
2724 data = RTLIL::Const(bit.data).bits;
2725 else
2726 offset = bit.offset;
2727 width = 1;
2728 }
2729
2730 RTLIL::SigChunk::SigChunk(const RTLIL::SigChunk &sigchunk) : data(sigchunk.data)
2731 {
2732 wire = sigchunk.wire;
2733 data = sigchunk.data;
2734 width = sigchunk.width;
2735 offset = sigchunk.offset;
2736 }
2737
2738 RTLIL::SigChunk RTLIL::SigChunk::extract(int offset, int length) const
2739 {
2740 RTLIL::SigChunk ret;
2741 if (wire) {
2742 ret.wire = wire;
2743 ret.offset = this->offset + offset;
2744 ret.width = length;
2745 } else {
2746 for (int i = 0; i < length; i++)
2747 ret.data.push_back(data[offset+i]);
2748 ret.width = length;
2749 }
2750 return ret;
2751 }
2752
2753 bool RTLIL::SigChunk::operator <(const RTLIL::SigChunk &other) const
2754 {
2755 if (wire && other.wire)
2756 if (wire->name != other.wire->name)
2757 return wire->name < other.wire->name;
2758
2759 if (wire != other.wire)
2760 return wire < other.wire;
2761
2762 if (offset != other.offset)
2763 return offset < other.offset;
2764
2765 if (width != other.width)
2766 return width < other.width;
2767
2768 return data < other.data;
2769 }
2770
2771 bool RTLIL::SigChunk::operator ==(const RTLIL::SigChunk &other) const
2772 {
2773 return wire == other.wire && width == other.width && offset == other.offset && data == other.data;
2774 }
2775
2776 bool RTLIL::SigChunk::operator !=(const RTLIL::SigChunk &other) const
2777 {
2778 if (*this == other)
2779 return false;
2780 return true;
2781 }
2782
2783 RTLIL::SigSpec::SigSpec()
2784 {
2785 width_ = 0;
2786 hash_ = 0;
2787 }
2788
2789 RTLIL::SigSpec::SigSpec(const RTLIL::SigSpec &other)
2790 {
2791 *this = other;
2792 }
2793
2794 RTLIL::SigSpec::SigSpec(std::initializer_list<RTLIL::SigSpec> parts)
2795 {
2796 cover("kernel.rtlil.sigspec.init.list");
2797
2798 width_ = 0;
2799 hash_ = 0;
2800
2801 std::vector<RTLIL::SigSpec> parts_vec(parts.begin(), parts.end());
2802 for (auto it = parts_vec.rbegin(); it != parts_vec.rend(); it++)
2803 append(*it);
2804 }
2805
2806 const RTLIL::SigSpec &RTLIL::SigSpec::operator=(const RTLIL::SigSpec &other)
2807 {
2808 cover("kernel.rtlil.sigspec.assign");
2809
2810 width_ = other.width_;
2811 hash_ = other.hash_;
2812 chunks_ = other.chunks_;
2813 bits_.clear();
2814
2815 if (!other.bits_.empty())
2816 {
2817 RTLIL::SigChunk *last = NULL;
2818 int last_end_offset = 0;
2819
2820 for (auto &bit : other.bits_) {
2821 if (last && bit.wire == last->wire) {
2822 if (bit.wire == NULL) {
2823 last->data.push_back(bit.data);
2824 last->width++;
2825 continue;
2826 } else if (last_end_offset == bit.offset) {
2827 last_end_offset++;
2828 last->width++;
2829 continue;
2830 }
2831 }
2832 chunks_.push_back(bit);
2833 last = &chunks_.back();
2834 last_end_offset = bit.offset + 1;
2835 }
2836
2837 check();
2838 }
2839
2840 return *this;
2841 }
2842
2843 RTLIL::SigSpec::SigSpec(const RTLIL::Const &value)
2844 {
2845 cover("kernel.rtlil.sigspec.init.const");
2846
2847 chunks_.push_back(RTLIL::SigChunk(value));
2848 width_ = chunks_.back().width;
2849 hash_ = 0;
2850 check();
2851 }
2852
2853 RTLIL::SigSpec::SigSpec(const RTLIL::SigChunk &chunk)
2854 {
2855 cover("kernel.rtlil.sigspec.init.chunk");
2856
2857 chunks_.push_back(chunk);
2858 width_ = chunks_.back().width;
2859 hash_ = 0;
2860 check();
2861 }
2862
2863 RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire)
2864 {
2865 cover("kernel.rtlil.sigspec.init.wire");
2866
2867 chunks_.push_back(RTLIL::SigChunk(wire));
2868 width_ = chunks_.back().width;
2869 hash_ = 0;
2870 check();
2871 }
2872
2873 RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire, int offset, int width)
2874 {
2875 cover("kernel.rtlil.sigspec.init.wire_part");
2876
2877 chunks_.push_back(RTLIL::SigChunk(wire, offset, width));
2878 width_ = chunks_.back().width;
2879 hash_ = 0;
2880 check();
2881 }
2882
2883 RTLIL::SigSpec::SigSpec(const std::string &str)
2884 {
2885 cover("kernel.rtlil.sigspec.init.str");
2886
2887 chunks_.push_back(RTLIL::SigChunk(str));
2888 width_ = chunks_.back().width;
2889 hash_ = 0;
2890 check();
2891 }
2892
2893 RTLIL::SigSpec::SigSpec(int val, int width)
2894 {
2895 cover("kernel.rtlil.sigspec.init.int");
2896
2897 chunks_.push_back(RTLIL::SigChunk(val, width));
2898 width_ = width;
2899 hash_ = 0;
2900 check();
2901 }
2902
2903 RTLIL::SigSpec::SigSpec(RTLIL::State bit, int width)
2904 {
2905 cover("kernel.rtlil.sigspec.init.state");
2906
2907 chunks_.push_back(RTLIL::SigChunk(bit, width));
2908 width_ = width;
2909 hash_ = 0;
2910 check();
2911 }
2912
2913 RTLIL::SigSpec::SigSpec(RTLIL::SigBit bit, int width)
2914 {
2915 cover("kernel.rtlil.sigspec.init.bit");
2916
2917 if (bit.wire == NULL)
2918 chunks_.push_back(RTLIL::SigChunk(bit.data, width));
2919 else
2920 for (int i = 0; i < width; i++)
2921 chunks_.push_back(bit);
2922 width_ = width;
2923 hash_ = 0;
2924 check();
2925 }
2926
2927 RTLIL::SigSpec::SigSpec(std::vector<RTLIL::SigChunk> chunks)
2928 {
2929 cover("kernel.rtlil.sigspec.init.stdvec_chunks");
2930
2931 width_ = 0;
2932 hash_ = 0;
2933 for (auto &c : chunks)
2934 append(c);
2935 check();
2936 }
2937
2938 RTLIL::SigSpec::SigSpec(std::vector<RTLIL::SigBit> bits)
2939 {
2940 cover("kernel.rtlil.sigspec.init.stdvec_bits");
2941
2942 width_ = 0;
2943 hash_ = 0;
2944 for (auto &bit : bits)
2945 append_bit(bit);
2946 check();
2947 }
2948
2949 RTLIL::SigSpec::SigSpec(pool<RTLIL::SigBit> bits)
2950 {
2951 cover("kernel.rtlil.sigspec.init.pool_bits");
2952
2953 width_ = 0;
2954 hash_ = 0;
2955 for (auto &bit : bits)
2956 append_bit(bit);
2957 check();
2958 }
2959
2960 RTLIL::SigSpec::SigSpec(std::set<RTLIL::SigBit> bits)
2961 {
2962 cover("kernel.rtlil.sigspec.init.stdset_bits");
2963
2964 width_ = 0;
2965 hash_ = 0;
2966 for (auto &bit : bits)
2967 append_bit(bit);
2968 check();
2969 }
2970
2971 RTLIL::SigSpec::SigSpec(bool bit)
2972 {
2973 cover("kernel.rtlil.sigspec.init.bool");
2974
2975 width_ = 0;
2976 hash_ = 0;
2977 append_bit(bit);
2978 check();
2979 }
2980
2981 void RTLIL::SigSpec::pack() const
2982 {
2983 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
2984
2985 if (that->bits_.empty())
2986 return;
2987
2988 cover("kernel.rtlil.sigspec.convert.pack");
2989 log_assert(that->chunks_.empty());
2990
2991 std::vector<RTLIL::SigBit> old_bits;
2992 old_bits.swap(that->bits_);
2993
2994 RTLIL::SigChunk *last = NULL;
2995 int last_end_offset = 0;
2996
2997 for (auto &bit : old_bits) {
2998 if (last && bit.wire == last->wire) {
2999 if (bit.wire == NULL) {
3000 last->data.push_back(bit.data);
3001 last->width++;
3002 continue;
3003 } else if (last_end_offset == bit.offset) {
3004 last_end_offset++;
3005 last->width++;
3006 continue;
3007 }
3008 }
3009 that->chunks_.push_back(bit);
3010 last = &that->chunks_.back();
3011 last_end_offset = bit.offset + 1;
3012 }
3013
3014 check();
3015 }
3016
3017 void RTLIL::SigSpec::unpack() const
3018 {
3019 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
3020
3021 if (that->chunks_.empty())
3022 return;
3023
3024 cover("kernel.rtlil.sigspec.convert.unpack");
3025 log_assert(that->bits_.empty());
3026
3027 that->bits_.reserve(that->width_);
3028 for (auto &c : that->chunks_)
3029 for (int i = 0; i < c.width; i++)
3030 that->bits_.push_back(RTLIL::SigBit(c, i));
3031
3032 that->chunks_.clear();
3033 that->hash_ = 0;
3034 }
3035
3036 void RTLIL::SigSpec::updhash() const
3037 {
3038 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
3039
3040 if (that->hash_ != 0)
3041 return;
3042
3043 cover("kernel.rtlil.sigspec.hash");
3044 that->pack();
3045
3046 that->hash_ = mkhash_init;
3047 for (auto &c : that->chunks_)
3048 if (c.wire == NULL) {
3049 for (auto &v : c.data)
3050 that->hash_ = mkhash(that->hash_, v);
3051 } else {
3052 that->hash_ = mkhash(that->hash_, c.wire->name.index_);
3053 that->hash_ = mkhash(that->hash_, c.offset);
3054 that->hash_ = mkhash(that->hash_, c.width);
3055 }
3056
3057 if (that->hash_ == 0)
3058 that->hash_ = 1;
3059 }
3060
3061 void RTLIL::SigSpec::sort()
3062 {
3063 unpack();
3064 cover("kernel.rtlil.sigspec.sort");
3065 std::sort(bits_.begin(), bits_.end());
3066 }
3067
3068 void RTLIL::SigSpec::sort_and_unify()
3069 {
3070 unpack();
3071 cover("kernel.rtlil.sigspec.sort_and_unify");
3072
3073 // A copy of the bits vector is used to prevent duplicating the logic from
3074 // SigSpec::SigSpec(std::vector<SigBit>). This incurrs an extra copy but
3075 // that isn't showing up as significant in profiles.
3076 std::vector<SigBit> unique_bits = bits_;
3077 std::sort(unique_bits.begin(), unique_bits.end());
3078 auto last = std::unique(unique_bits.begin(), unique_bits.end());
3079 unique_bits.erase(last, unique_bits.end());
3080
3081 *this = unique_bits;
3082 }
3083
3084 void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with)
3085 {
3086 replace(pattern, with, this);
3087 }
3088
3089 void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with, RTLIL::SigSpec *other) const
3090 {
3091 log_assert(other != NULL);
3092 log_assert(width_ == other->width_);
3093 log_assert(pattern.width_ == with.width_);
3094
3095 pattern.unpack();
3096 with.unpack();
3097 unpack();
3098 other->unpack();
3099
3100 for (int i = 0; i < GetSize(pattern.bits_); i++) {
3101 if (pattern.bits_[i].wire != NULL) {
3102 for (int j = 0; j < GetSize(bits_); j++) {
3103 if (bits_[j] == pattern.bits_[i]) {
3104 other->bits_[j] = with.bits_[i];
3105 }
3106 }
3107 }
3108 }
3109
3110 other->check();
3111 }
3112
3113 void RTLIL::SigSpec::replace(const dict<RTLIL::SigBit, RTLIL::SigBit> &rules)
3114 {
3115 replace(rules, this);
3116 }
3117
3118 void RTLIL::SigSpec::replace(const dict<RTLIL::SigBit, RTLIL::SigBit> &rules, RTLIL::SigSpec *other) const
3119 {
3120 cover("kernel.rtlil.sigspec.replace_dict");
3121
3122 log_assert(other != NULL);
3123 log_assert(width_ == other->width_);
3124
3125 if (rules.empty()) return;
3126 unpack();
3127 other->unpack();
3128
3129 for (int i = 0; i < GetSize(bits_); i++) {
3130 auto it = rules.find(bits_[i]);
3131 if (it != rules.end())
3132 other->bits_[i] = it->second;
3133 }
3134
3135 other->check();
3136 }
3137
3138 void RTLIL::SigSpec::replace(const std::map<RTLIL::SigBit, RTLIL::SigBit> &rules)
3139 {
3140 replace(rules, this);
3141 }
3142
3143 void RTLIL::SigSpec::replace(const std::map<RTLIL::SigBit, RTLIL::SigBit> &rules, RTLIL::SigSpec *other) const
3144 {
3145 cover("kernel.rtlil.sigspec.replace_map");
3146
3147 log_assert(other != NULL);
3148 log_assert(width_ == other->width_);
3149
3150 if (rules.empty()) return;
3151 unpack();
3152 other->unpack();
3153
3154 for (int i = 0; i < GetSize(bits_); i++) {
3155 auto it = rules.find(bits_[i]);
3156 if (it != rules.end())
3157 other->bits_[i] = it->second;
3158 }
3159
3160 other->check();
3161 }
3162
3163 void RTLIL::SigSpec::remove(const RTLIL::SigSpec &pattern)
3164 {
3165 remove2(pattern, NULL);
3166 }
3167
3168 void RTLIL::SigSpec::remove(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other) const
3169 {
3170 RTLIL::SigSpec tmp = *this;
3171 tmp.remove2(pattern, other);
3172 }
3173
3174 void RTLIL::SigSpec::remove2(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other)
3175 {
3176 if (other)
3177 cover("kernel.rtlil.sigspec.remove_other");
3178 else
3179 cover("kernel.rtlil.sigspec.remove");
3180
3181 unpack();
3182 if (other != NULL) {
3183 log_assert(width_ == other->width_);
3184 other->unpack();
3185 }
3186
3187 for (int i = GetSize(bits_) - 1; i >= 0; i--)
3188 {
3189 if (bits_[i].wire == NULL) continue;
3190
3191 for (auto &pattern_chunk : pattern.chunks())
3192 if (bits_[i].wire == pattern_chunk.wire &&
3193 bits_[i].offset >= pattern_chunk.offset &&
3194 bits_[i].offset < pattern_chunk.offset + pattern_chunk.width) {
3195 bits_.erase(bits_.begin() + i);
3196 width_--;
3197 if (other != NULL) {
3198 other->bits_.erase(other->bits_.begin() + i);
3199 other->width_--;
3200 }
3201 break;
3202 }
3203 }
3204
3205 check();
3206 }
3207
3208 void RTLIL::SigSpec::remove(const pool<RTLIL::SigBit> &pattern)
3209 {
3210 remove2(pattern, NULL);
3211 }
3212
3213 void RTLIL::SigSpec::remove(const pool<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other) const
3214 {
3215 RTLIL::SigSpec tmp = *this;
3216 tmp.remove2(pattern, other);
3217 }
3218
3219 void RTLIL::SigSpec::remove2(const pool<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other)
3220 {
3221 if (other)
3222 cover("kernel.rtlil.sigspec.remove_other");
3223 else
3224 cover("kernel.rtlil.sigspec.remove");
3225
3226 unpack();
3227
3228 if (other != NULL) {
3229 log_assert(width_ == other->width_);
3230 other->unpack();
3231 }
3232
3233 for (int i = GetSize(bits_) - 1; i >= 0; i--) {
3234 if (bits_[i].wire != NULL && pattern.count(bits_[i])) {
3235 bits_.erase(bits_.begin() + i);
3236 width_--;
3237 if (other != NULL) {
3238 other->bits_.erase(other->bits_.begin() + i);
3239 other->width_--;
3240 }
3241 }
3242 }
3243
3244 check();
3245 }
3246
3247 void RTLIL::SigSpec::remove2(const std::set<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other)
3248 {
3249 if (other)
3250 cover("kernel.rtlil.sigspec.remove_other");
3251 else
3252 cover("kernel.rtlil.sigspec.remove");
3253
3254 unpack();
3255
3256 if (other != NULL) {
3257 log_assert(width_ == other->width_);
3258 other->unpack();
3259 }
3260
3261 for (int i = GetSize(bits_) - 1; i >= 0; i--) {
3262 if (bits_[i].wire != NULL && pattern.count(bits_[i])) {
3263 bits_.erase(bits_.begin() + i);
3264 width_--;
3265 if (other != NULL) {
3266 other->bits_.erase(other->bits_.begin() + i);
3267 other->width_--;
3268 }
3269 }
3270 }
3271
3272 check();
3273 }
3274
3275 RTLIL::SigSpec RTLIL::SigSpec::extract(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec *other) const
3276 {
3277 if (other)
3278 cover("kernel.rtlil.sigspec.extract_other");
3279 else
3280 cover("kernel.rtlil.sigspec.extract");
3281
3282 log_assert(other == NULL || width_ == other->width_);
3283
3284 RTLIL::SigSpec ret;
3285 std::vector<RTLIL::SigBit> bits_match = to_sigbit_vector();
3286
3287 for (auto& pattern_chunk : pattern.chunks()) {
3288 if (other) {
3289 std::vector<RTLIL::SigBit> bits_other = other->to_sigbit_vector();
3290 for (int i = 0; i < width_; i++)
3291 if (bits_match[i].wire &&
3292 bits_match[i].wire == pattern_chunk.wire &&
3293 bits_match[i].offset >= pattern_chunk.offset &&
3294 bits_match[i].offset < pattern_chunk.offset + pattern_chunk.width)
3295 ret.append_bit(bits_other[i]);
3296 } else {
3297 for (int i = 0; i < width_; i++)
3298 if (bits_match[i].wire &&
3299 bits_match[i].wire == pattern_chunk.wire &&
3300 bits_match[i].offset >= pattern_chunk.offset &&
3301 bits_match[i].offset < pattern_chunk.offset + pattern_chunk.width)
3302 ret.append_bit(bits_match[i]);
3303 }
3304 }
3305
3306 ret.check();
3307 return ret;
3308 }
3309
3310 RTLIL::SigSpec RTLIL::SigSpec::extract(const pool<RTLIL::SigBit> &pattern, const RTLIL::SigSpec *other) const
3311 {
3312 if (other)
3313 cover("kernel.rtlil.sigspec.extract_other");
3314 else
3315 cover("kernel.rtlil.sigspec.extract");
3316
3317 log_assert(other == NULL || width_ == other->width_);
3318
3319 std::vector<RTLIL::SigBit> bits_match = to_sigbit_vector();
3320 RTLIL::SigSpec ret;
3321
3322 if (other) {
3323 std::vector<RTLIL::SigBit> bits_other = other->to_sigbit_vector();
3324 for (int i = 0; i < width_; i++)
3325 if (bits_match[i].wire && pattern.count(bits_match[i]))
3326 ret.append_bit(bits_other[i]);
3327 } else {
3328 for (int i = 0; i < width_; i++)
3329 if (bits_match[i].wire && pattern.count(bits_match[i]))
3330 ret.append_bit(bits_match[i]);
3331 }
3332
3333 ret.check();
3334 return ret;
3335 }
3336
3337 void RTLIL::SigSpec::replace(int offset, const RTLIL::SigSpec &with)
3338 {
3339 cover("kernel.rtlil.sigspec.replace_pos");
3340
3341 unpack();
3342 with.unpack();
3343
3344 log_assert(offset >= 0);
3345 log_assert(with.width_ >= 0);
3346 log_assert(offset+with.width_ <= width_);
3347
3348 for (int i = 0; i < with.width_; i++)
3349 bits_.at(offset + i) = with.bits_.at(i);
3350
3351 check();
3352 }
3353
3354 void RTLIL::SigSpec::remove_const()
3355 {
3356 if (packed())
3357 {
3358 cover("kernel.rtlil.sigspec.remove_const.packed");
3359
3360 std::vector<RTLIL::SigChunk> new_chunks;
3361 new_chunks.reserve(GetSize(chunks_));
3362
3363 width_ = 0;
3364 for (auto &chunk : chunks_)
3365 if (chunk.wire != NULL) {
3366 new_chunks.push_back(chunk);
3367 width_ += chunk.width;
3368 }
3369
3370 chunks_.swap(new_chunks);
3371 }
3372 else
3373 {
3374 cover("kernel.rtlil.sigspec.remove_const.unpacked");
3375
3376 std::vector<RTLIL::SigBit> new_bits;
3377 new_bits.reserve(width_);
3378
3379 for (auto &bit : bits_)
3380 if (bit.wire != NULL)
3381 new_bits.push_back(bit);
3382
3383 bits_.swap(new_bits);
3384 width_ = bits_.size();
3385 }
3386
3387 check();
3388 }
3389
3390 void RTLIL::SigSpec::remove(int offset, int length)
3391 {
3392 cover("kernel.rtlil.sigspec.remove_pos");
3393
3394 unpack();
3395
3396 log_assert(offset >= 0);
3397 log_assert(length >= 0);
3398 log_assert(offset + length <= width_);
3399
3400 bits_.erase(bits_.begin() + offset, bits_.begin() + offset + length);
3401 width_ = bits_.size();
3402
3403 check();
3404 }
3405
3406 RTLIL::SigSpec RTLIL::SigSpec::extract(int offset, int length) const
3407 {
3408 unpack();
3409 cover("kernel.rtlil.sigspec.extract_pos");
3410 return std::vector<RTLIL::SigBit>(bits_.begin() + offset, bits_.begin() + offset + length);
3411 }
3412
3413 void RTLIL::SigSpec::append(const RTLIL::SigSpec &signal)
3414 {
3415 if (signal.width_ == 0)
3416 return;
3417
3418 if (width_ == 0) {
3419 *this = signal;
3420 return;
3421 }
3422
3423 cover("kernel.rtlil.sigspec.append");
3424
3425 if (packed() != signal.packed()) {
3426 pack();
3427 signal.pack();
3428 }
3429
3430 if (packed())
3431 for (auto &other_c : signal.chunks_)
3432 {
3433 auto &my_last_c = chunks_.back();
3434 if (my_last_c.wire == NULL && other_c.wire == NULL) {
3435 auto &this_data = my_last_c.data;
3436 auto &other_data = other_c.data;
3437 this_data.insert(this_data.end(), other_data.begin(), other_data.end());
3438 my_last_c.width += other_c.width;
3439 } else
3440 if (my_last_c.wire == other_c.wire && my_last_c.offset + my_last_c.width == other_c.offset) {
3441 my_last_c.width += other_c.width;
3442 } else
3443 chunks_.push_back(other_c);
3444 }
3445 else
3446 bits_.insert(bits_.end(), signal.bits_.begin(), signal.bits_.end());
3447
3448 width_ += signal.width_;
3449 check();
3450 }
3451
3452 void RTLIL::SigSpec::append_bit(const RTLIL::SigBit &bit)
3453 {
3454 if (packed())
3455 {
3456 cover("kernel.rtlil.sigspec.append_bit.packed");
3457
3458 if (chunks_.size() == 0)
3459 chunks_.push_back(bit);
3460 else
3461 if (bit.wire == NULL)
3462 if (chunks_.back().wire == NULL) {
3463 chunks_.back().data.push_back(bit.data);
3464 chunks_.back().width++;
3465 } else
3466 chunks_.push_back(bit);
3467 else
3468 if (chunks_.back().wire == bit.wire && chunks_.back().offset + chunks_.back().width == bit.offset)
3469 chunks_.back().width++;
3470 else
3471 chunks_.push_back(bit);
3472 }
3473 else
3474 {
3475 cover("kernel.rtlil.sigspec.append_bit.unpacked");
3476 bits_.push_back(bit);
3477 }
3478
3479 width_++;
3480 check();
3481 }
3482
3483 void RTLIL::SigSpec::extend_u0(int width, bool is_signed)
3484 {
3485 cover("kernel.rtlil.sigspec.extend_u0");
3486
3487 pack();
3488
3489 if (width_ > width)
3490 remove(width, width_ - width);
3491
3492 if (width_ < width) {
3493 RTLIL::SigBit padding = width_ > 0 ? (*this)[width_ - 1] : RTLIL::State::Sx;
3494 if (!is_signed)
3495 padding = RTLIL::State::S0;
3496 while (width_ < width)
3497 append(padding);
3498 }
3499
3500 }
3501
3502 RTLIL::SigSpec RTLIL::SigSpec::repeat(int num) const
3503 {
3504 cover("kernel.rtlil.sigspec.repeat");
3505
3506 RTLIL::SigSpec sig;
3507 for (int i = 0; i < num; i++)
3508 sig.append(*this);
3509 return sig;
3510 }
3511
3512 #ifndef NDEBUG
3513 void RTLIL::SigSpec::check() const
3514 {
3515 if (width_ > 64)
3516 {
3517 cover("kernel.rtlil.sigspec.check.skip");
3518 }
3519 else if (packed())
3520 {
3521 cover("kernel.rtlil.sigspec.check.packed");
3522
3523 int w = 0;
3524 for (size_t i = 0; i < chunks_.size(); i++) {
3525 const RTLIL::SigChunk chunk = chunks_[i];
3526 if (chunk.wire == NULL) {
3527 if (i > 0)
3528 log_assert(chunks_[i-1].wire != NULL);
3529 log_assert(chunk.offset == 0);
3530 log_assert(chunk.data.size() == (size_t)chunk.width);
3531 } else {
3532 if (i > 0 && chunks_[i-1].wire == chunk.wire)
3533 log_assert(chunk.offset != chunks_[i-1].offset + chunks_[i-1].width);
3534 log_assert(chunk.offset >= 0);
3535 log_assert(chunk.width >= 0);
3536 log_assert(chunk.offset + chunk.width <= chunk.wire->width);
3537 log_assert(chunk.data.size() == 0);
3538 }
3539 w += chunk.width;
3540 }
3541 log_assert(w == width_);
3542 log_assert(bits_.empty());
3543 }
3544 else
3545 {
3546 cover("kernel.rtlil.sigspec.check.unpacked");
3547
3548 log_assert(width_ == GetSize(bits_));
3549 log_assert(chunks_.empty());
3550 }
3551 }
3552 #endif
3553
3554 bool RTLIL::SigSpec::operator <(const RTLIL::SigSpec &other) const
3555 {
3556 cover("kernel.rtlil.sigspec.comp_lt");
3557
3558 if (this == &other)
3559 return false;
3560
3561 if (width_ != other.width_)
3562 return width_ < other.width_;
3563
3564 pack();
3565 other.pack();
3566
3567 if (chunks_.size() != other.chunks_.size())
3568 return chunks_.size() < other.chunks_.size();
3569
3570 updhash();
3571 other.updhash();
3572
3573 if (hash_ != other.hash_)
3574 return hash_ < other.hash_;
3575
3576 for (size_t i = 0; i < chunks_.size(); i++)
3577 if (chunks_[i] != other.chunks_[i]) {
3578 cover("kernel.rtlil.sigspec.comp_lt.hash_collision");
3579 return chunks_[i] < other.chunks_[i];
3580 }
3581
3582 cover("kernel.rtlil.sigspec.comp_lt.equal");
3583 return false;
3584 }
3585
3586 bool RTLIL::SigSpec::operator ==(const RTLIL::SigSpec &other) const
3587 {
3588 cover("kernel.rtlil.sigspec.comp_eq");
3589
3590 if (this == &other)
3591 return true;
3592
3593 if (width_ != other.width_)
3594 return false;
3595
3596 // Without this, SigSpec() == SigSpec(State::S0, 0) will fail
3597 // since the RHS will contain one SigChunk of width 0 causing
3598 // the size check below to fail
3599 if (width_ == 0)
3600 return true;
3601
3602 pack();
3603 other.pack();
3604
3605 if (chunks_.size() != other.chunks_.size())
3606 return false;
3607
3608 updhash();
3609 other.updhash();
3610
3611 if (hash_ != other.hash_)
3612 return false;
3613
3614 for (size_t i = 0; i < chunks_.size(); i++)
3615 if (chunks_[i] != other.chunks_[i]) {
3616 cover("kernel.rtlil.sigspec.comp_eq.hash_collision");
3617 return false;
3618 }
3619
3620 cover("kernel.rtlil.sigspec.comp_eq.equal");
3621 return true;
3622 }
3623
3624 bool RTLIL::SigSpec::is_wire() const
3625 {
3626 cover("kernel.rtlil.sigspec.is_wire");
3627
3628 pack();
3629 return GetSize(chunks_) == 1 && chunks_[0].wire && chunks_[0].wire->width == width_;
3630 }
3631
3632 bool RTLIL::SigSpec::is_chunk() const
3633 {
3634 cover("kernel.rtlil.sigspec.is_chunk");
3635
3636 pack();
3637 return GetSize(chunks_) == 1;
3638 }
3639
3640 bool RTLIL::SigSpec::is_fully_const() const
3641 {
3642 cover("kernel.rtlil.sigspec.is_fully_const");
3643
3644 pack();
3645 for (auto it = chunks_.begin(); it != chunks_.end(); it++)
3646 if (it->width > 0 && it->wire != NULL)
3647 return false;
3648 return true;
3649 }
3650
3651 bool RTLIL::SigSpec::is_fully_zero() const
3652 {
3653 cover("kernel.rtlil.sigspec.is_fully_zero");
3654
3655 pack();
3656 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
3657 if (it->width > 0 && it->wire != NULL)
3658 return false;
3659 for (size_t i = 0; i < it->data.size(); i++)
3660 if (it->data[i] != RTLIL::State::S0)
3661 return false;
3662 }
3663 return true;
3664 }
3665
3666 bool RTLIL::SigSpec::is_fully_ones() const
3667 {
3668 cover("kernel.rtlil.sigspec.is_fully_ones");
3669
3670 pack();
3671 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
3672 if (it->width > 0 && it->wire != NULL)
3673 return false;
3674 for (size_t i = 0; i < it->data.size(); i++)
3675 if (it->data[i] != RTLIL::State::S1)
3676 return false;
3677 }
3678 return true;
3679 }
3680
3681 bool RTLIL::SigSpec::is_fully_def() const
3682 {
3683 cover("kernel.rtlil.sigspec.is_fully_def");
3684
3685 pack();
3686 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
3687 if (it->width > 0 && it->wire != NULL)
3688 return false;
3689 for (size_t i = 0; i < it->data.size(); i++)
3690 if (it->data[i] != RTLIL::State::S0 && it->data[i] != RTLIL::State::S1)
3691 return false;
3692 }
3693 return true;
3694 }
3695
3696 bool RTLIL::SigSpec::is_fully_undef() const
3697 {
3698 cover("kernel.rtlil.sigspec.is_fully_undef");
3699
3700 pack();
3701 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
3702 if (it->width > 0 && it->wire != NULL)
3703 return false;
3704 for (size_t i = 0; i < it->data.size(); i++)
3705 if (it->data[i] != RTLIL::State::Sx && it->data[i] != RTLIL::State::Sz)
3706 return false;
3707 }
3708 return true;
3709 }
3710
3711 bool RTLIL::SigSpec::has_const() const
3712 {
3713 cover("kernel.rtlil.sigspec.has_const");
3714
3715 pack();
3716 for (auto it = chunks_.begin(); it != chunks_.end(); it++)
3717 if (it->width > 0 && it->wire == NULL)
3718 return true;
3719 return false;
3720 }
3721
3722 bool RTLIL::SigSpec::has_marked_bits() const
3723 {
3724 cover("kernel.rtlil.sigspec.has_marked_bits");
3725
3726 pack();
3727 for (auto it = chunks_.begin(); it != chunks_.end(); it++)
3728 if (it->width > 0 && it->wire == NULL) {
3729 for (size_t i = 0; i < it->data.size(); i++)
3730 if (it->data[i] == RTLIL::State::Sm)
3731 return true;
3732 }
3733 return false;
3734 }
3735
3736 bool RTLIL::SigSpec::as_bool() const
3737 {
3738 cover("kernel.rtlil.sigspec.as_bool");
3739
3740 pack();
3741 log_assert(is_fully_const() && GetSize(chunks_) <= 1);
3742 if (width_)
3743 return RTLIL::Const(chunks_[0].data).as_bool();
3744 return false;
3745 }
3746
3747 int RTLIL::SigSpec::as_int(bool is_signed) const
3748 {
3749 cover("kernel.rtlil.sigspec.as_int");
3750
3751 pack();
3752 log_assert(is_fully_const() && GetSize(chunks_) <= 1);
3753 if (width_)
3754 return RTLIL::Const(chunks_[0].data).as_int(is_signed);
3755 return 0;
3756 }
3757
3758 std::string RTLIL::SigSpec::as_string() const
3759 {
3760 cover("kernel.rtlil.sigspec.as_string");
3761
3762 pack();
3763 std::string str;
3764 for (size_t i = chunks_.size(); i > 0; i--) {
3765 const RTLIL::SigChunk &chunk = chunks_[i-1];
3766 if (chunk.wire != NULL)
3767 for (int j = 0; j < chunk.width; j++)
3768 str += "?";
3769 else
3770 str += RTLIL::Const(chunk.data).as_string();
3771 }
3772 return str;
3773 }
3774
3775 RTLIL::Const RTLIL::SigSpec::as_const() const
3776 {
3777 cover("kernel.rtlil.sigspec.as_const");
3778
3779 pack();
3780 log_assert(is_fully_const() && GetSize(chunks_) <= 1);
3781 if (width_)
3782 return chunks_[0].data;
3783 return RTLIL::Const();
3784 }
3785
3786 RTLIL::Wire *RTLIL::SigSpec::as_wire() const
3787 {
3788 cover("kernel.rtlil.sigspec.as_wire");
3789
3790 pack();
3791 log_assert(is_wire());
3792 return chunks_[0].wire;
3793 }
3794
3795 RTLIL::SigChunk RTLIL::SigSpec::as_chunk() const
3796 {
3797 cover("kernel.rtlil.sigspec.as_chunk");
3798
3799 pack();
3800 log_assert(is_chunk());
3801 return chunks_[0];
3802 }
3803
3804 RTLIL::SigBit RTLIL::SigSpec::as_bit() const
3805 {
3806 cover("kernel.rtlil.sigspec.as_bit");
3807
3808 log_assert(width_ == 1);
3809 if (packed())
3810 return RTLIL::SigBit(*chunks_.begin());
3811 else
3812 return bits_[0];
3813 }
3814
3815 bool RTLIL::SigSpec::match(std::string pattern) const
3816 {
3817 cover("kernel.rtlil.sigspec.match");
3818
3819 pack();
3820 std::string str = as_string();
3821 log_assert(pattern.size() == str.size());
3822
3823 for (size_t i = 0; i < pattern.size(); i++) {
3824 if (pattern[i] == ' ')
3825 continue;
3826 if (pattern[i] == '*') {
3827 if (str[i] != 'z' && str[i] != 'x')
3828 return false;
3829 continue;
3830 }
3831 if (pattern[i] != str[i])
3832 return false;
3833 }
3834
3835 return true;
3836 }
3837
3838 std::set<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_set() const
3839 {
3840 cover("kernel.rtlil.sigspec.to_sigbit_set");
3841
3842 pack();
3843 std::set<RTLIL::SigBit> sigbits;
3844 for (auto &c : chunks_)
3845 for (int i = 0; i < c.width; i++)
3846 sigbits.insert(RTLIL::SigBit(c, i));
3847 return sigbits;
3848 }
3849
3850 pool<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_pool() const
3851 {
3852 cover("kernel.rtlil.sigspec.to_sigbit_pool");
3853
3854 pack();
3855 pool<RTLIL::SigBit> sigbits;
3856 for (auto &c : chunks_)
3857 for (int i = 0; i < c.width; i++)
3858 sigbits.insert(RTLIL::SigBit(c, i));
3859 return sigbits;
3860 }
3861
3862 std::vector<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_vector() const
3863 {
3864 cover("kernel.rtlil.sigspec.to_sigbit_vector");
3865
3866 unpack();
3867 return bits_;
3868 }
3869
3870 std::map<RTLIL::SigBit, RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_map(const RTLIL::SigSpec &other) const
3871 {
3872 cover("kernel.rtlil.sigspec.to_sigbit_map");
3873
3874 unpack();
3875 other.unpack();
3876
3877 log_assert(width_ == other.width_);
3878
3879 std::map<RTLIL::SigBit, RTLIL::SigBit> new_map;
3880 for (int i = 0; i < width_; i++)
3881 new_map[bits_[i]] = other.bits_[i];
3882
3883 return new_map;
3884 }
3885
3886 dict<RTLIL::SigBit, RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_dict(const RTLIL::SigSpec &other) const
3887 {
3888 cover("kernel.rtlil.sigspec.to_sigbit_dict");
3889
3890 unpack();
3891 other.unpack();
3892
3893 log_assert(width_ == other.width_);
3894
3895 dict<RTLIL::SigBit, RTLIL::SigBit> new_map;
3896 for (int i = 0; i < width_; i++)
3897 new_map[bits_[i]] = other.bits_[i];
3898
3899 return new_map;
3900 }
3901
3902 static void sigspec_parse_split(std::vector<std::string> &tokens, const std::string &text, char sep)
3903 {
3904 size_t start = 0, end = 0;
3905 while ((end = text.find(sep, start)) != std::string::npos) {
3906 tokens.push_back(text.substr(start, end - start));
3907 start = end + 1;
3908 }
3909 tokens.push_back(text.substr(start));
3910 }
3911
3912 static int sigspec_parse_get_dummy_line_num()
3913 {
3914 return 0;
3915 }
3916
3917 bool RTLIL::SigSpec::parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str)
3918 {
3919 cover("kernel.rtlil.sigspec.parse");
3920
3921 AST::current_filename = "input";
3922 AST::use_internal_line_num();
3923 AST::set_line_num(0);
3924
3925 std::vector<std::string> tokens;
3926 sigspec_parse_split(tokens, str, ',');
3927
3928 sig = RTLIL::SigSpec();
3929 for (int tokidx = int(tokens.size())-1; tokidx >= 0; tokidx--)
3930 {
3931 std::string netname = tokens[tokidx];
3932 std::string indices;
3933
3934 if (netname.size() == 0)
3935 continue;
3936
3937 if (('0' <= netname[0] && netname[0] <= '9') || netname[0] == '\'') {
3938 cover("kernel.rtlil.sigspec.parse.const");
3939 AST::get_line_num = sigspec_parse_get_dummy_line_num;
3940 AST::AstNode *ast = VERILOG_FRONTEND::const2ast(netname);
3941 if (ast == NULL)
3942 return false;
3943 sig.append(RTLIL::Const(ast->bits));
3944 delete ast;
3945 continue;
3946 }
3947
3948 if (module == NULL)
3949 return false;
3950
3951 cover("kernel.rtlil.sigspec.parse.net");
3952
3953 if (netname[0] != '$' && netname[0] != '\\')
3954 netname = "\\" + netname;
3955
3956 if (module->wires_.count(netname) == 0) {
3957 size_t indices_pos = netname.size()-1;
3958 if (indices_pos > 2 && netname[indices_pos] == ']')
3959 {
3960 indices_pos--;
3961 while (indices_pos > 0 && ('0' <= netname[indices_pos] && netname[indices_pos] <= '9')) indices_pos--;
3962 if (indices_pos > 0 && netname[indices_pos] == ':') {
3963 indices_pos--;
3964 while (indices_pos > 0 && ('0' <= netname[indices_pos] && netname[indices_pos] <= '9')) indices_pos--;
3965 }
3966 if (indices_pos > 0 && netname[indices_pos] == '[') {
3967 indices = netname.substr(indices_pos);
3968 netname = netname.substr(0, indices_pos);
3969 }
3970 }
3971 }
3972
3973 if (module->wires_.count(netname) == 0)
3974 return false;
3975
3976 RTLIL::Wire *wire = module->wires_.at(netname);
3977 if (!indices.empty()) {
3978 std::vector<std::string> index_tokens;
3979 sigspec_parse_split(index_tokens, indices.substr(1, indices.size()-2), ':');
3980 if (index_tokens.size() == 1) {
3981 cover("kernel.rtlil.sigspec.parse.bit_sel");
3982 int a = atoi(index_tokens.at(0).c_str());
3983 if (a < 0 || a >= wire->width)
3984 return false;
3985 sig.append(RTLIL::SigSpec(wire, a));
3986 } else {
3987 cover("kernel.rtlil.sigspec.parse.part_sel");
3988 int a = atoi(index_tokens.at(0).c_str());
3989 int b = atoi(index_tokens.at(1).c_str());
3990 if (a > b) {
3991 int tmp = a;
3992 a = b, b = tmp;
3993 }
3994 if (a < 0 || a >= wire->width)
3995 return false;
3996 if (b < 0 || b >= wire->width)
3997 return false;
3998 sig.append(RTLIL::SigSpec(wire, a, b-a+1));
3999 }
4000 } else
4001 sig.append(wire);
4002 }
4003
4004 return true;
4005 }
4006
4007 bool RTLIL::SigSpec::parse_sel(RTLIL::SigSpec &sig, RTLIL::Design *design, RTLIL::Module *module, std::string str)
4008 {
4009 if (str.empty() || str[0] != '@')
4010 return parse(sig, module, str);
4011
4012 cover("kernel.rtlil.sigspec.parse.sel");
4013
4014 str = RTLIL::escape_id(str.substr(1));
4015 if (design->selection_vars.count(str) == 0)
4016 return false;
4017
4018 sig = RTLIL::SigSpec();
4019 RTLIL::Selection &sel = design->selection_vars.at(str);
4020 for (auto &it : module->wires_)
4021 if (sel.selected_member(module->name, it.first))
4022 sig.append(it.second);
4023
4024 return true;
4025 }
4026
4027 bool RTLIL::SigSpec::parse_rhs(const RTLIL::SigSpec &lhs, RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str)
4028 {
4029 if (str == "0") {
4030 cover("kernel.rtlil.sigspec.parse.rhs_zeros");
4031 sig = RTLIL::SigSpec(RTLIL::State::S0, lhs.width_);
4032 return true;
4033 }
4034
4035 if (str == "~0") {
4036 cover("kernel.rtlil.sigspec.parse.rhs_ones");
4037 sig = RTLIL::SigSpec(RTLIL::State::S1, lhs.width_);
4038 return true;
4039 }
4040
4041 if (lhs.chunks_.size() == 1) {
4042 char *p = (char*)str.c_str(), *endptr;
4043 long int val = strtol(p, &endptr, 10);
4044 if (endptr && endptr != p && *endptr == 0) {
4045 sig = RTLIL::SigSpec(val, lhs.width_);
4046 cover("kernel.rtlil.sigspec.parse.rhs_dec");
4047 return true;
4048 }
4049 }
4050
4051 return parse(sig, module, str);
4052 }
4053
4054 RTLIL::CaseRule::~CaseRule()
4055 {
4056 for (auto it = switches.begin(); it != switches.end(); it++)
4057 delete *it;
4058 }
4059
4060 bool RTLIL::CaseRule::empty() const
4061 {
4062 return actions.empty() && switches.empty();
4063 }
4064
4065 RTLIL::CaseRule *RTLIL::CaseRule::clone() const
4066 {
4067 RTLIL::CaseRule *new_caserule = new RTLIL::CaseRule;
4068 new_caserule->compare = compare;
4069 new_caserule->actions = actions;
4070 for (auto &it : switches)
4071 new_caserule->switches.push_back(it->clone());
4072 return new_caserule;
4073 }
4074
4075 RTLIL::SwitchRule::~SwitchRule()
4076 {
4077 for (auto it = cases.begin(); it != cases.end(); it++)
4078 delete *it;
4079 }
4080
4081 bool RTLIL::SwitchRule::empty() const
4082 {
4083 return cases.empty();
4084 }
4085
4086 RTLIL::SwitchRule *RTLIL::SwitchRule::clone() const
4087 {
4088 RTLIL::SwitchRule *new_switchrule = new RTLIL::SwitchRule;
4089 new_switchrule->signal = signal;
4090 new_switchrule->attributes = attributes;
4091 for (auto &it : cases)
4092 new_switchrule->cases.push_back(it->clone());
4093 return new_switchrule;
4094
4095 }
4096
4097 RTLIL::SyncRule *RTLIL::SyncRule::clone() const
4098 {
4099 RTLIL::SyncRule *new_syncrule = new RTLIL::SyncRule;
4100 new_syncrule->type = type;
4101 new_syncrule->signal = signal;
4102 new_syncrule->actions = actions;
4103 return new_syncrule;
4104 }
4105
4106 RTLIL::Process::~Process()
4107 {
4108 for (auto it = syncs.begin(); it != syncs.end(); it++)
4109 delete *it;
4110 }
4111
4112 RTLIL::Process *RTLIL::Process::clone() const
4113 {
4114 RTLIL::Process *new_proc = new RTLIL::Process;
4115
4116 new_proc->name = name;
4117 new_proc->attributes = attributes;
4118
4119 RTLIL::CaseRule *rc_ptr = root_case.clone();
4120 new_proc->root_case = *rc_ptr;
4121 rc_ptr->switches.clear();
4122 delete rc_ptr;
4123
4124 for (auto &it : syncs)
4125 new_proc->syncs.push_back(it->clone());
4126
4127 return new_proc;
4128 }
4129
4130 #ifdef WITH_PYTHON
4131 RTLIL::Memory::~Memory()
4132 {
4133 RTLIL::Memory::get_all_memorys()->erase(hashidx_);
4134 }
4135 static std::map<unsigned int, RTLIL::Memory*> all_memorys;
4136 std::map<unsigned int, RTLIL::Memory*> *RTLIL::Memory::get_all_memorys(void)
4137 {
4138 return &all_memorys;
4139 }
4140 #endif
4141 YOSYS_NAMESPACE_END