2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include "kernel/yosys.h"
21 #include "kernel/macc.h"
22 #include "kernel/celltypes.h"
23 #include "frontends/verilog/verilog_frontend.h"
24 #include "backends/ilang/ilang_backend.h"
31 RTLIL::IdString::destruct_guard_t
RTLIL::IdString::destruct_guard
;
32 std::vector
<char*> RTLIL::IdString::global_id_storage_
;
33 dict
<char*, int, hash_cstr_ops
> RTLIL::IdString::global_id_index_
;
34 #ifndef YOSYS_NO_IDS_REFCNT
35 std::vector
<int> RTLIL::IdString::global_refcount_storage_
;
36 std::vector
<int> RTLIL::IdString::global_free_idx_list_
;
38 #ifdef YOSYS_USE_STICKY_IDS
39 int RTLIL::IdString::last_created_idx_
[8];
40 int RTLIL::IdString::last_created_idx_ptr_
;
43 IdString
RTLIL::ID::A
;
44 IdString
RTLIL::ID::B
;
45 IdString
RTLIL::ID::Y
;
46 IdString
RTLIL::ID::keep
;
47 IdString
RTLIL::ID::whitebox
;
48 IdString
RTLIL::ID::blackbox
;
52 flags
= RTLIL::CONST_FLAG_NONE
;
55 RTLIL::Const::Const(std::string str
)
57 flags
= RTLIL::CONST_FLAG_STRING
;
58 for (int i
= str
.size()-1; i
>= 0; i
--) {
59 unsigned char ch
= str
[i
];
60 for (int j
= 0; j
< 8; j
++) {
61 bits
.push_back((ch
& 1) != 0 ? State::S1
: State::S0
);
67 RTLIL::Const::Const(int val
, int width
)
69 flags
= RTLIL::CONST_FLAG_NONE
;
70 for (int i
= 0; i
< width
; i
++) {
71 bits
.push_back((val
& 1) != 0 ? State::S1
: State::S0
);
76 RTLIL::Const::Const(RTLIL::State bit
, int width
)
78 flags
= RTLIL::CONST_FLAG_NONE
;
79 for (int i
= 0; i
< width
; i
++)
83 RTLIL::Const::Const(const std::vector
<bool> &bits
)
85 flags
= RTLIL::CONST_FLAG_NONE
;
87 this->bits
.push_back(b
? State::S1
: State::S0
);
90 RTLIL::Const::Const(const RTLIL::Const
&c
)
94 this->bits
.push_back(b
);
97 bool RTLIL::Const::operator <(const RTLIL::Const
&other
) const
99 if (bits
.size() != other
.bits
.size())
100 return bits
.size() < other
.bits
.size();
101 for (size_t i
= 0; i
< bits
.size(); i
++)
102 if (bits
[i
] != other
.bits
[i
])
103 return bits
[i
] < other
.bits
[i
];
107 bool RTLIL::Const::operator ==(const RTLIL::Const
&other
) const
109 return bits
== other
.bits
;
112 bool RTLIL::Const::operator !=(const RTLIL::Const
&other
) const
114 return bits
!= other
.bits
;
117 bool RTLIL::Const::as_bool() const
119 for (size_t i
= 0; i
< bits
.size(); i
++)
120 if (bits
[i
] == State::S1
)
125 int RTLIL::Const::as_int(bool is_signed
) const
128 for (size_t i
= 0; i
< bits
.size() && i
< 32; i
++)
129 if (bits
[i
] == State::S1
)
131 if (is_signed
&& bits
.back() == State::S1
)
132 for (size_t i
= bits
.size(); i
< 32; i
++)
137 std::string
RTLIL::Const::as_string() const
140 for (size_t i
= bits
.size(); i
> 0; i
--)
142 case S0
: ret
+= "0"; break;
143 case S1
: ret
+= "1"; break;
144 case Sx
: ret
+= "x"; break;
145 case Sz
: ret
+= "z"; break;
146 case Sa
: ret
+= "-"; break;
147 case Sm
: ret
+= "m"; break;
152 RTLIL::Const
RTLIL::Const::from_string(std::string str
)
155 for (auto it
= str
.rbegin(); it
!= str
.rend(); it
++)
157 case '0': c
.bits
.push_back(State::S0
); break;
158 case '1': c
.bits
.push_back(State::S1
); break;
159 case 'x': c
.bits
.push_back(State::Sx
); break;
160 case 'z': c
.bits
.push_back(State::Sz
); break;
161 case 'm': c
.bits
.push_back(State::Sm
); break;
162 default: c
.bits
.push_back(State::Sa
);
167 std::string
RTLIL::Const::decode_string() const
170 std::vector
<char> string_chars
;
171 for (int i
= 0; i
< int (bits
.size()); i
+= 8) {
173 for (int j
= 0; j
< 8 && i
+ j
< int (bits
.size()); j
++)
174 if (bits
[i
+ j
] == RTLIL::State::S1
)
177 string_chars
.push_back(ch
);
179 for (int i
= int (string_chars
.size()) - 1; i
>= 0; i
--)
180 string
+= string_chars
[i
];
184 bool RTLIL::Const::is_fully_zero() const
186 cover("kernel.rtlil.const.is_fully_zero");
188 for (auto bit
: bits
)
189 if (bit
!= RTLIL::State::S0
)
195 bool RTLIL::Const::is_fully_ones() const
197 cover("kernel.rtlil.const.is_fully_ones");
199 for (auto bit
: bits
)
200 if (bit
!= RTLIL::State::S1
)
206 bool RTLIL::Const::is_fully_def() const
208 cover("kernel.rtlil.const.is_fully_def");
210 for (auto bit
: bits
)
211 if (bit
!= RTLIL::State::S0
&& bit
!= RTLIL::State::S1
)
217 bool RTLIL::Const::is_fully_undef() const
219 cover("kernel.rtlil.const.is_fully_undef");
221 for (auto bit
: bits
)
222 if (bit
!= RTLIL::State::Sx
&& bit
!= RTLIL::State::Sz
)
228 void RTLIL::AttrObject::set_bool_attribute(RTLIL::IdString id
, bool value
)
231 attributes
[id
] = RTLIL::Const(1);
233 const auto it
= attributes
.find(id
);
234 if (it
!= attributes
.end())
235 attributes
.erase(it
);
239 bool RTLIL::AttrObject::get_bool_attribute(RTLIL::IdString id
) const
241 const auto it
= attributes
.find(id
);
242 if (it
== attributes
.end())
244 return it
->second
.as_bool();
247 void RTLIL::AttrObject::set_strpool_attribute(RTLIL::IdString id
, const pool
<string
> &data
)
250 for (auto &s
: data
) {
251 if (!attrval
.empty())
255 attributes
[id
] = RTLIL::Const(attrval
);
258 void RTLIL::AttrObject::add_strpool_attribute(RTLIL::IdString id
, const pool
<string
> &data
)
260 pool
<string
> union_data
= get_strpool_attribute(id
);
261 union_data
.insert(data
.begin(), data
.end());
262 if (!union_data
.empty())
263 set_strpool_attribute(id
, union_data
);
266 pool
<string
> RTLIL::AttrObject::get_strpool_attribute(RTLIL::IdString id
) const
269 if (attributes
.count(id
) != 0)
270 for (auto s
: split_tokens(attributes
.at(id
).decode_string(), "|"))
275 void RTLIL::AttrObject::set_src_attribute(const std::string
&src
)
278 attributes
.erase(ID(src
));
280 attributes
[ID(src
)] = src
;
283 std::string
RTLIL::AttrObject::get_src_attribute() const
286 if (attributes
.count(ID(src
)))
287 src
= attributes
.at(ID(src
)).decode_string();
291 bool RTLIL::Selection::selected_module(RTLIL::IdString mod_name
) const
295 if (selected_modules
.count(mod_name
) > 0)
297 if (selected_members
.count(mod_name
) > 0)
302 bool RTLIL::Selection::selected_whole_module(RTLIL::IdString mod_name
) const
306 if (selected_modules
.count(mod_name
) > 0)
311 bool RTLIL::Selection::selected_member(RTLIL::IdString mod_name
, RTLIL::IdString memb_name
) const
315 if (selected_modules
.count(mod_name
) > 0)
317 if (selected_members
.count(mod_name
) > 0)
318 if (selected_members
.at(mod_name
).count(memb_name
) > 0)
323 void RTLIL::Selection::optimize(RTLIL::Design
*design
)
325 if (full_selection
) {
326 selected_modules
.clear();
327 selected_members
.clear();
331 std::vector
<RTLIL::IdString
> del_list
, add_list
;
334 for (auto mod_name
: selected_modules
) {
335 if (design
->modules_
.count(mod_name
) == 0)
336 del_list
.push_back(mod_name
);
337 selected_members
.erase(mod_name
);
339 for (auto mod_name
: del_list
)
340 selected_modules
.erase(mod_name
);
343 for (auto &it
: selected_members
)
344 if (design
->modules_
.count(it
.first
) == 0)
345 del_list
.push_back(it
.first
);
346 for (auto mod_name
: del_list
)
347 selected_members
.erase(mod_name
);
349 for (auto &it
: selected_members
) {
351 for (auto memb_name
: it
.second
)
352 if (design
->modules_
[it
.first
]->count_id(memb_name
) == 0)
353 del_list
.push_back(memb_name
);
354 for (auto memb_name
: del_list
)
355 it
.second
.erase(memb_name
);
360 for (auto &it
: selected_members
)
361 if (it
.second
.size() == 0)
362 del_list
.push_back(it
.first
);
363 else if (it
.second
.size() == design
->modules_
[it
.first
]->wires_
.size() + design
->modules_
[it
.first
]->memories
.size() +
364 design
->modules_
[it
.first
]->cells_
.size() + design
->modules_
[it
.first
]->processes
.size())
365 add_list
.push_back(it
.first
);
366 for (auto mod_name
: del_list
)
367 selected_members
.erase(mod_name
);
368 for (auto mod_name
: add_list
) {
369 selected_members
.erase(mod_name
);
370 selected_modules
.insert(mod_name
);
373 if (selected_modules
.size() == design
->modules_
.size()) {
374 full_selection
= true;
375 selected_modules
.clear();
376 selected_members
.clear();
380 RTLIL::Design::Design()
382 static unsigned int hashidx_count
= 123456789;
383 hashidx_count
= mkhash_xorshift(hashidx_count
);
384 hashidx_
= hashidx_count
;
386 refcount_modules_
= 0;
387 selection_stack
.push_back(RTLIL::Selection());
390 RTLIL::Design::get_all_designs()->insert(std::pair
<unsigned int, RTLIL::Design
*>(hashidx_
, this));
394 RTLIL::Design::~Design()
396 for (auto it
= modules_
.begin(); it
!= modules_
.end(); ++it
)
398 for (auto n
: verilog_packages
)
400 for (auto n
: verilog_globals
)
403 RTLIL::Design::get_all_designs()->erase(hashidx_
);
408 static std::map
<unsigned int, RTLIL::Design
*> all_designs
;
409 std::map
<unsigned int, RTLIL::Design
*> *RTLIL::Design::get_all_designs(void)
415 RTLIL::ObjRange
<RTLIL::Module
*> RTLIL::Design::modules()
417 return RTLIL::ObjRange
<RTLIL::Module
*>(&modules_
, &refcount_modules_
);
420 RTLIL::Module
*RTLIL::Design::module(RTLIL::IdString name
)
422 return modules_
.count(name
) ? modules_
.at(name
) : NULL
;
425 RTLIL::Module
*RTLIL::Design::top_module()
427 RTLIL::Module
*module
= nullptr;
428 int module_count
= 0;
430 for (auto mod
: selected_modules()) {
431 if (mod
->get_bool_attribute(ID(top
)))
437 return module_count
== 1 ? module
: nullptr;
440 void RTLIL::Design::add(RTLIL::Module
*module
)
442 log_assert(modules_
.count(module
->name
) == 0);
443 log_assert(refcount_modules_
== 0);
444 modules_
[module
->name
] = module
;
445 module
->design
= this;
447 for (auto mon
: monitors
)
448 mon
->notify_module_add(module
);
451 log("#X# New Module: %s\n", log_id(module
));
452 log_backtrace("-X- ", yosys_xtrace
-1);
456 RTLIL::Module
*RTLIL::Design::addModule(RTLIL::IdString name
)
458 log_assert(modules_
.count(name
) == 0);
459 log_assert(refcount_modules_
== 0);
461 RTLIL::Module
*module
= new RTLIL::Module
;
462 modules_
[name
] = module
;
463 module
->design
= this;
466 for (auto mon
: monitors
)
467 mon
->notify_module_add(module
);
470 log("#X# New Module: %s\n", log_id(module
));
471 log_backtrace("-X- ", yosys_xtrace
-1);
477 void RTLIL::Design::scratchpad_unset(std::string varname
)
479 scratchpad
.erase(varname
);
482 void RTLIL::Design::scratchpad_set_int(std::string varname
, int value
)
484 scratchpad
[varname
] = stringf("%d", value
);
487 void RTLIL::Design::scratchpad_set_bool(std::string varname
, bool value
)
489 scratchpad
[varname
] = value
? "true" : "false";
492 void RTLIL::Design::scratchpad_set_string(std::string varname
, std::string value
)
494 scratchpad
[varname
] = value
;
497 int RTLIL::Design::scratchpad_get_int(std::string varname
, int default_value
) const
499 if (scratchpad
.count(varname
) == 0)
500 return default_value
;
502 std::string str
= scratchpad
.at(varname
);
504 if (str
== "0" || str
== "false")
507 if (str
== "1" || str
== "true")
510 char *endptr
= nullptr;
511 long int parsed_value
= strtol(str
.c_str(), &endptr
, 10);
512 return *endptr
? default_value
: parsed_value
;
515 bool RTLIL::Design::scratchpad_get_bool(std::string varname
, bool default_value
) const
517 if (scratchpad
.count(varname
) == 0)
518 return default_value
;
520 std::string str
= scratchpad
.at(varname
);
522 if (str
== "0" || str
== "false")
525 if (str
== "1" || str
== "true")
528 return default_value
;
531 std::string
RTLIL::Design::scratchpad_get_string(std::string varname
, std::string default_value
) const
533 if (scratchpad
.count(varname
) == 0)
534 return default_value
;
535 return scratchpad
.at(varname
);
538 void RTLIL::Design::remove(RTLIL::Module
*module
)
540 for (auto mon
: monitors
)
541 mon
->notify_module_del(module
);
544 log("#X# Remove Module: %s\n", log_id(module
));
545 log_backtrace("-X- ", yosys_xtrace
-1);
548 log_assert(modules_
.at(module
->name
) == module
);
549 modules_
.erase(module
->name
);
553 void RTLIL::Design::rename(RTLIL::Module
*module
, RTLIL::IdString new_name
)
555 modules_
.erase(module
->name
);
556 module
->name
= new_name
;
560 void RTLIL::Design::sort()
563 modules_
.sort(sort_by_id_str());
564 for (auto &it
: modules_
)
568 void RTLIL::Design::check()
571 for (auto &it
: modules_
) {
572 log_assert(this == it
.second
->design
);
573 log_assert(it
.first
== it
.second
->name
);
574 log_assert(!it
.first
.empty());
580 void RTLIL::Design::optimize()
582 for (auto &it
: modules_
)
583 it
.second
->optimize();
584 for (auto &it
: selection_stack
)
586 for (auto &it
: selection_vars
)
587 it
.second
.optimize(this);
590 bool RTLIL::Design::selected_module(RTLIL::IdString mod_name
) const
592 if (!selected_active_module
.empty() && mod_name
!= selected_active_module
)
594 if (selection_stack
.size() == 0)
596 return selection_stack
.back().selected_module(mod_name
);
599 bool RTLIL::Design::selected_whole_module(RTLIL::IdString mod_name
) const
601 if (!selected_active_module
.empty() && mod_name
!= selected_active_module
)
603 if (selection_stack
.size() == 0)
605 return selection_stack
.back().selected_whole_module(mod_name
);
608 bool RTLIL::Design::selected_member(RTLIL::IdString mod_name
, RTLIL::IdString memb_name
) const
610 if (!selected_active_module
.empty() && mod_name
!= selected_active_module
)
612 if (selection_stack
.size() == 0)
614 return selection_stack
.back().selected_member(mod_name
, memb_name
);
617 bool RTLIL::Design::selected_module(RTLIL::Module
*mod
) const
619 return selected_module(mod
->name
);
622 bool RTLIL::Design::selected_whole_module(RTLIL::Module
*mod
) const
624 return selected_whole_module(mod
->name
);
627 std::vector
<RTLIL::Module
*> RTLIL::Design::selected_modules() const
629 std::vector
<RTLIL::Module
*> result
;
630 result
.reserve(modules_
.size());
631 for (auto &it
: modules_
)
632 if (selected_module(it
.first
) && !it
.second
->get_blackbox_attribute())
633 result
.push_back(it
.second
);
637 std::vector
<RTLIL::Module
*> RTLIL::Design::selected_whole_modules() const
639 std::vector
<RTLIL::Module
*> result
;
640 result
.reserve(modules_
.size());
641 for (auto &it
: modules_
)
642 if (selected_whole_module(it
.first
) && !it
.second
->get_blackbox_attribute())
643 result
.push_back(it
.second
);
647 std::vector
<RTLIL::Module
*> RTLIL::Design::selected_whole_modules_warn() const
649 std::vector
<RTLIL::Module
*> result
;
650 result
.reserve(modules_
.size());
651 for (auto &it
: modules_
)
652 if (it
.second
->get_blackbox_attribute())
654 else if (selected_whole_module(it
.first
))
655 result
.push_back(it
.second
);
656 else if (selected_module(it
.first
))
657 log_warning("Ignoring partially selected module %s.\n", log_id(it
.first
));
661 RTLIL::Module::Module()
663 static unsigned int hashidx_count
= 123456789;
664 hashidx_count
= mkhash_xorshift(hashidx_count
);
665 hashidx_
= hashidx_count
;
672 RTLIL::Module::get_all_modules()->insert(std::pair
<unsigned int, RTLIL::Module
*>(hashidx_
, this));
676 RTLIL::Module::~Module()
678 for (auto it
= wires_
.begin(); it
!= wires_
.end(); ++it
)
680 for (auto it
= memories
.begin(); it
!= memories
.end(); ++it
)
682 for (auto it
= cells_
.begin(); it
!= cells_
.end(); ++it
)
684 for (auto it
= processes
.begin(); it
!= processes
.end(); ++it
)
687 RTLIL::Module::get_all_modules()->erase(hashidx_
);
692 static std::map
<unsigned int, RTLIL::Module
*> all_modules
;
693 std::map
<unsigned int, RTLIL::Module
*> *RTLIL::Module::get_all_modules(void)
699 void RTLIL::Module::makeblackbox()
701 pool
<RTLIL::Wire
*> delwires
;
703 for (auto it
= wires_
.begin(); it
!= wires_
.end(); ++it
)
704 if (!it
->second
->port_input
&& !it
->second
->port_output
)
705 delwires
.insert(it
->second
);
707 for (auto it
= memories
.begin(); it
!= memories
.end(); ++it
)
711 for (auto it
= cells_
.begin(); it
!= cells_
.end(); ++it
)
715 for (auto it
= processes
.begin(); it
!= processes
.end(); ++it
)
720 set_bool_attribute(ID::blackbox
);
723 void RTLIL::Module::reprocess_module(RTLIL::Design
*, dict
<RTLIL::IdString
, RTLIL::Module
*>)
725 log_error("Cannot reprocess_module module `%s' !\n", id2cstr(name
));
728 RTLIL::IdString
RTLIL::Module::derive(RTLIL::Design
*, dict
<RTLIL::IdString
, RTLIL::Const
>, bool mayfail
)
731 return RTLIL::IdString();
732 log_error("Module `%s' is used with parameters but is not parametric!\n", id2cstr(name
));
736 RTLIL::IdString
RTLIL::Module::derive(RTLIL::Design
*, dict
<RTLIL::IdString
, RTLIL::Const
>, dict
<RTLIL::IdString
, RTLIL::Module
*>, dict
<RTLIL::IdString
, RTLIL::IdString
>, bool mayfail
)
739 return RTLIL::IdString();
740 log_error("Module `%s' is used with parameters but is not parametric!\n", id2cstr(name
));
743 size_t RTLIL::Module::count_id(RTLIL::IdString id
)
745 return wires_
.count(id
) + memories
.count(id
) + cells_
.count(id
) + processes
.count(id
);
750 struct InternalCellChecker
752 RTLIL::Module
*module
;
754 pool
<RTLIL::IdString
> expected_params
, expected_ports
;
756 InternalCellChecker(RTLIL::Module
*module
, RTLIL::Cell
*cell
) : module(module
), cell(cell
) { }
758 void error(int linenr
)
760 std::stringstream buf
;
761 ILANG_BACKEND::dump_cell(buf
, " ", cell
);
763 log_error("Found error in internal cell %s%s%s (%s) at %s:%d:\n%s",
764 module
? module
->name
.c_str() : "", module
? "." : "",
765 cell
->name
.c_str(), cell
->type
.c_str(), __FILE__
, linenr
, buf
.str().c_str());
768 int param(RTLIL::IdString name
)
770 if (cell
->parameters
.count(name
) == 0)
772 expected_params
.insert(name
);
773 return cell
->parameters
.at(name
).as_int();
776 int param_bool(RTLIL::IdString name
)
779 if (cell
->parameters
.at(name
).bits
.size() > 32)
781 if (v
!= 0 && v
!= 1)
786 void param_bits(RTLIL::IdString name
, int width
)
789 if (int(cell
->parameters
.at(name
).bits
.size()) != width
)
793 void port(RTLIL::IdString name
, int width
)
795 if (!cell
->hasPort(name
))
797 if (cell
->getPort(name
).size() != width
)
799 expected_ports
.insert(name
);
802 void check_expected(bool check_matched_sign
= true)
804 for (auto ¶
: cell
->parameters
)
805 if (expected_params
.count(para
.first
) == 0)
807 for (auto &conn
: cell
->connections())
808 if (expected_ports
.count(conn
.first
) == 0)
811 if (expected_params
.count(ID(A_SIGNED
)) != 0 && expected_params
.count(ID(B_SIGNED
)) && check_matched_sign
) {
812 bool a_is_signed
= param(ID(A_SIGNED
)) != 0;
813 bool b_is_signed
= param(ID(B_SIGNED
)) != 0;
814 if (a_is_signed
!= b_is_signed
)
819 void check_gate(const char *ports
)
821 if (cell
->parameters
.size() != 0)
824 for (const char *p
= ports
; *p
; p
++) {
825 char portname
[3] = { '\\', *p
, 0 };
826 if (!cell
->hasPort(portname
))
828 if (cell
->getPort(portname
).size() != 1)
832 for (auto &conn
: cell
->connections()) {
833 if (conn
.first
.size() != 2 || conn
.first
[0] != '\\')
835 if (strchr(ports
, conn
.first
[1]) == NULL
)
842 if (!cell
->type
.begins_with("$") || cell
->type
.begins_with("$__") || cell
->type
.begins_with("$paramod") || cell
->type
.begins_with("$fmcombine") ||
843 cell
->type
.begins_with("$verific$") || cell
->type
.begins_with("$array:") || cell
->type
.begins_with("$extern:"))
846 if (cell
->type
.in(ID($
not), ID($pos
), ID($neg
))) {
847 param_bool(ID(A_SIGNED
));
848 port(ID::A
, param(ID(A_WIDTH
)));
849 port(ID::Y
, param(ID(Y_WIDTH
)));
854 if (cell
->type
.in(ID($
and), ID($
or), ID($
xor), ID($xnor
))) {
855 param_bool(ID(A_SIGNED
));
856 param_bool(ID(B_SIGNED
));
857 port(ID::A
, param(ID(A_WIDTH
)));
858 port(ID::B
, param(ID(B_WIDTH
)));
859 port(ID::Y
, param(ID(Y_WIDTH
)));
864 if (cell
->type
.in(ID($reduce_and
), ID($reduce_or
), ID($reduce_xor
), ID($reduce_xnor
), ID($reduce_bool
))) {
865 param_bool(ID(A_SIGNED
));
866 port(ID::A
, param(ID(A_WIDTH
)));
867 port(ID::Y
, param(ID(Y_WIDTH
)));
872 if (cell
->type
.in(ID($shl
), ID($shr
), ID($sshl
), ID($sshr
), ID($shift
), ID($shiftx
))) {
873 param_bool(ID(A_SIGNED
));
874 param_bool(ID(B_SIGNED
));
875 port(ID::A
, param(ID(A_WIDTH
)));
876 port(ID::B
, param(ID(B_WIDTH
)));
877 port(ID::Y
, param(ID(Y_WIDTH
)));
878 check_expected(false);
882 if (cell
->type
.in(ID($lt
), ID($le
), ID($eq
), ID($ne
), ID($eqx
), ID($nex
), ID($ge
), ID($gt
))) {
883 param_bool(ID(A_SIGNED
));
884 param_bool(ID(B_SIGNED
));
885 port(ID::A
, param(ID(A_WIDTH
)));
886 port(ID::B
, param(ID(B_WIDTH
)));
887 port(ID::Y
, param(ID(Y_WIDTH
)));
892 if (cell
->type
.in(ID($add
), ID($sub
), ID($mul
), ID($div
), ID($mod
), ID($pow
))) {
893 param_bool(ID(A_SIGNED
));
894 param_bool(ID(B_SIGNED
));
895 port(ID::A
, param(ID(A_WIDTH
)));
896 port(ID::B
, param(ID(B_WIDTH
)));
897 port(ID::Y
, param(ID(Y_WIDTH
)));
898 check_expected(cell
->type
!= ID($pow
));
902 if (cell
->type
== ID($fa
)) {
903 port(ID::A
, param(ID(WIDTH
)));
904 port(ID::B
, param(ID(WIDTH
)));
905 port(ID(C
), param(ID(WIDTH
)));
906 port(ID(X
), param(ID(WIDTH
)));
907 port(ID::Y
, param(ID(WIDTH
)));
912 if (cell
->type
== ID($lcu
)) {
913 port(ID(P
), param(ID(WIDTH
)));
914 port(ID(G
), param(ID(WIDTH
)));
916 port(ID(CO
), param(ID(WIDTH
)));
921 if (cell
->type
== ID($alu
)) {
922 param_bool(ID(A_SIGNED
));
923 param_bool(ID(B_SIGNED
));
924 port(ID::A
, param(ID(A_WIDTH
)));
925 port(ID::B
, param(ID(B_WIDTH
)));
928 port(ID(X
), param(ID(Y_WIDTH
)));
929 port(ID::Y
, param(ID(Y_WIDTH
)));
930 port(ID(CO
), param(ID(Y_WIDTH
)));
935 if (cell
->type
== ID($macc
)) {
937 param(ID(CONFIG_WIDTH
));
938 port(ID::A
, param(ID(A_WIDTH
)));
939 port(ID::B
, param(ID(B_WIDTH
)));
940 port(ID::Y
, param(ID(Y_WIDTH
)));
942 Macc().from_cell(cell
);
946 if (cell
->type
== ID($logic_not
)) {
947 param_bool(ID(A_SIGNED
));
948 port(ID::A
, param(ID(A_WIDTH
)));
949 port(ID::Y
, param(ID(Y_WIDTH
)));
954 if (cell
->type
.in(ID($logic_and
), ID($logic_or
))) {
955 param_bool(ID(A_SIGNED
));
956 param_bool(ID(B_SIGNED
));
957 port(ID::A
, param(ID(A_WIDTH
)));
958 port(ID::B
, param(ID(B_WIDTH
)));
959 port(ID::Y
, param(ID(Y_WIDTH
)));
960 check_expected(false);
964 if (cell
->type
== ID($slice
)) {
966 port(ID::A
, param(ID(A_WIDTH
)));
967 port(ID::Y
, param(ID(Y_WIDTH
)));
968 if (param(ID(OFFSET
)) + param(ID(Y_WIDTH
)) > param(ID(A_WIDTH
)))
974 if (cell
->type
== ID($concat
)) {
975 port(ID::A
, param(ID(A_WIDTH
)));
976 port(ID::B
, param(ID(B_WIDTH
)));
977 port(ID::Y
, param(ID(A_WIDTH
)) + param(ID(B_WIDTH
)));
982 if (cell
->type
== ID($mux
)) {
983 port(ID::A
, param(ID(WIDTH
)));
984 port(ID::B
, param(ID(WIDTH
)));
986 port(ID::Y
, param(ID(WIDTH
)));
991 if (cell
->type
== ID($pmux
)) {
992 port(ID::A
, param(ID(WIDTH
)));
993 port(ID::B
, param(ID(WIDTH
)) * param(ID(S_WIDTH
)));
994 port(ID(S
), param(ID(S_WIDTH
)));
995 port(ID::Y
, param(ID(WIDTH
)));
1000 if (cell
->type
== ID($lut
)) {
1002 port(ID::A
, param(ID(WIDTH
)));
1008 if (cell
->type
== ID($sop
)) {
1011 port(ID::A
, param(ID(WIDTH
)));
1017 if (cell
->type
== ID($sr
)) {
1018 param_bool(ID(SET_POLARITY
));
1019 param_bool(ID(CLR_POLARITY
));
1020 port(ID(SET
), param(ID(WIDTH
)));
1021 port(ID(CLR
), param(ID(WIDTH
)));
1022 port(ID(Q
), param(ID(WIDTH
)));
1027 if (cell
->type
== ID($ff
)) {
1028 port(ID(D
), param(ID(WIDTH
)));
1029 port(ID(Q
), param(ID(WIDTH
)));
1034 if (cell
->type
== ID($dff
)) {
1035 param_bool(ID(CLK_POLARITY
));
1037 port(ID(D
), param(ID(WIDTH
)));
1038 port(ID(Q
), param(ID(WIDTH
)));
1043 if (cell
->type
== ID($dffe
)) {
1044 param_bool(ID(CLK_POLARITY
));
1045 param_bool(ID(EN_POLARITY
));
1048 port(ID(D
), param(ID(WIDTH
)));
1049 port(ID(Q
), param(ID(WIDTH
)));
1054 if (cell
->type
== ID($dffsr
)) {
1055 param_bool(ID(CLK_POLARITY
));
1056 param_bool(ID(SET_POLARITY
));
1057 param_bool(ID(CLR_POLARITY
));
1059 port(ID(SET
), param(ID(WIDTH
)));
1060 port(ID(CLR
), param(ID(WIDTH
)));
1061 port(ID(D
), param(ID(WIDTH
)));
1062 port(ID(Q
), param(ID(WIDTH
)));
1067 if (cell
->type
== ID($adff
)) {
1068 param_bool(ID(CLK_POLARITY
));
1069 param_bool(ID(ARST_POLARITY
));
1070 param_bits(ID(ARST_VALUE
), param(ID(WIDTH
)));
1073 port(ID(D
), param(ID(WIDTH
)));
1074 port(ID(Q
), param(ID(WIDTH
)));
1079 if (cell
->type
== ID($dlatch
)) {
1080 param_bool(ID(EN_POLARITY
));
1082 port(ID(D
), param(ID(WIDTH
)));
1083 port(ID(Q
), param(ID(WIDTH
)));
1088 if (cell
->type
== ID($dlatchsr
)) {
1089 param_bool(ID(EN_POLARITY
));
1090 param_bool(ID(SET_POLARITY
));
1091 param_bool(ID(CLR_POLARITY
));
1093 port(ID(SET
), param(ID(WIDTH
)));
1094 port(ID(CLR
), param(ID(WIDTH
)));
1095 port(ID(D
), param(ID(WIDTH
)));
1096 port(ID(Q
), param(ID(WIDTH
)));
1101 if (cell
->type
== ID($fsm
)) {
1103 param_bool(ID(CLK_POLARITY
));
1104 param_bool(ID(ARST_POLARITY
));
1105 param(ID(STATE_BITS
));
1106 param(ID(STATE_NUM
));
1107 param(ID(STATE_NUM_LOG2
));
1108 param(ID(STATE_RST
));
1109 param_bits(ID(STATE_TABLE
), param(ID(STATE_BITS
)) * param(ID(STATE_NUM
)));
1110 param(ID(TRANS_NUM
));
1111 param_bits(ID(TRANS_TABLE
), param(ID(TRANS_NUM
)) * (2*param(ID(STATE_NUM_LOG2
)) + param(ID(CTRL_IN_WIDTH
)) + param(ID(CTRL_OUT_WIDTH
))));
1114 port(ID(CTRL_IN
), param(ID(CTRL_IN_WIDTH
)));
1115 port(ID(CTRL_OUT
), param(ID(CTRL_OUT_WIDTH
)));
1120 if (cell
->type
== ID($memrd
)) {
1122 param_bool(ID(CLK_ENABLE
));
1123 param_bool(ID(CLK_POLARITY
));
1124 param_bool(ID(TRANSPARENT
));
1127 port(ID(ADDR
), param(ID(ABITS
)));
1128 port(ID(DATA
), param(ID(WIDTH
)));
1133 if (cell
->type
== ID($memwr
)) {
1135 param_bool(ID(CLK_ENABLE
));
1136 param_bool(ID(CLK_POLARITY
));
1137 param(ID(PRIORITY
));
1139 port(ID(EN
), param(ID(WIDTH
)));
1140 port(ID(ADDR
), param(ID(ABITS
)));
1141 port(ID(DATA
), param(ID(WIDTH
)));
1146 if (cell
->type
== ID($meminit
)) {
1148 param(ID(PRIORITY
));
1149 port(ID(ADDR
), param(ID(ABITS
)));
1150 port(ID(DATA
), param(ID(WIDTH
)) * param(ID(WORDS
)));
1155 if (cell
->type
== ID($mem
)) {
1160 param_bits(ID(RD_CLK_ENABLE
), max(1, param(ID(RD_PORTS
))));
1161 param_bits(ID(RD_CLK_POLARITY
), max(1, param(ID(RD_PORTS
))));
1162 param_bits(ID(RD_TRANSPARENT
), max(1, param(ID(RD_PORTS
))));
1163 param_bits(ID(WR_CLK_ENABLE
), max(1, param(ID(WR_PORTS
))));
1164 param_bits(ID(WR_CLK_POLARITY
), max(1, param(ID(WR_PORTS
))));
1165 port(ID(RD_CLK
), param(ID(RD_PORTS
)));
1166 port(ID(RD_EN
), param(ID(RD_PORTS
)));
1167 port(ID(RD_ADDR
), param(ID(RD_PORTS
)) * param(ID(ABITS
)));
1168 port(ID(RD_DATA
), param(ID(RD_PORTS
)) * param(ID(WIDTH
)));
1169 port(ID(WR_CLK
), param(ID(WR_PORTS
)));
1170 port(ID(WR_EN
), param(ID(WR_PORTS
)) * param(ID(WIDTH
)));
1171 port(ID(WR_ADDR
), param(ID(WR_PORTS
)) * param(ID(ABITS
)));
1172 port(ID(WR_DATA
), param(ID(WR_PORTS
)) * param(ID(WIDTH
)));
1177 if (cell
->type
== ID($tribuf
)) {
1178 port(ID::A
, param(ID(WIDTH
)));
1179 port(ID::Y
, param(ID(WIDTH
)));
1185 if (cell
->type
.in(ID($
assert), ID($assume
), ID($live
), ID($fair
), ID($cover
))) {
1192 if (cell
->type
== ID($initstate
)) {
1198 if (cell
->type
.in(ID($anyconst
), ID($anyseq
), ID($allconst
), ID($allseq
))) {
1199 port(ID::Y
, param(ID(WIDTH
)));
1204 if (cell
->type
== ID($equiv
)) {
1212 if (cell
->type
.in(ID($specify2
), ID($specify3
))) {
1213 param_bool(ID(FULL
));
1214 param_bool(ID(SRC_DST_PEN
));
1215 param_bool(ID(SRC_DST_POL
));
1216 param(ID(T_RISE_MIN
));
1217 param(ID(T_RISE_TYP
));
1218 param(ID(T_RISE_MAX
));
1219 param(ID(T_FALL_MIN
));
1220 param(ID(T_FALL_TYP
));
1221 param(ID(T_FALL_MAX
));
1223 port(ID(SRC
), param(ID(SRC_WIDTH
)));
1224 port(ID(DST
), param(ID(DST_WIDTH
)));
1225 if (cell
->type
== ID($specify3
)) {
1226 param_bool(ID(EDGE_EN
));
1227 param_bool(ID(EDGE_POL
));
1228 param_bool(ID(DAT_DST_PEN
));
1229 param_bool(ID(DAT_DST_POL
));
1230 port(ID(DAT
), param(ID(DST_WIDTH
)));
1236 if (cell
->type
== ID($specrule
)) {
1238 param_bool(ID(SRC_PEN
));
1239 param_bool(ID(SRC_POL
));
1240 param_bool(ID(DST_PEN
));
1241 param_bool(ID(DST_POL
));
1243 param(ID(T_LIMIT2
));
1244 port(ID(SRC_EN
), 1);
1245 port(ID(DST_EN
), 1);
1246 port(ID(SRC
), param(ID(SRC_WIDTH
)));
1247 port(ID(DST
), param(ID(DST_WIDTH
)));
1252 if (cell
->type
== ID($_BUF_
)) { check_gate("AY"); return; }
1253 if (cell
->type
== ID($_NOT_
)) { check_gate("AY"); return; }
1254 if (cell
->type
== ID($_AND_
)) { check_gate("ABY"); return; }
1255 if (cell
->type
== ID($_NAND_
)) { check_gate("ABY"); return; }
1256 if (cell
->type
== ID($_OR_
)) { check_gate("ABY"); return; }
1257 if (cell
->type
== ID($_NOR_
)) { check_gate("ABY"); return; }
1258 if (cell
->type
== ID($_XOR_
)) { check_gate("ABY"); return; }
1259 if (cell
->type
== ID($_XNOR_
)) { check_gate("ABY"); return; }
1260 if (cell
->type
== ID($_ANDNOT_
)) { check_gate("ABY"); return; }
1261 if (cell
->type
== ID($_ORNOT_
)) { check_gate("ABY"); return; }
1262 if (cell
->type
== ID($_MUX_
)) { check_gate("ABSY"); return; }
1263 if (cell
->type
== ID($_NMUX_
)) { check_gate("ABSY"); return; }
1264 if (cell
->type
== ID($_AOI3_
)) { check_gate("ABCY"); return; }
1265 if (cell
->type
== ID($_OAI3_
)) { check_gate("ABCY"); return; }
1266 if (cell
->type
== ID($_AOI4_
)) { check_gate("ABCDY"); return; }
1267 if (cell
->type
== ID($_OAI4_
)) { check_gate("ABCDY"); return; }
1269 if (cell
->type
== ID($_TBUF_
)) { check_gate("AYE"); return; }
1271 if (cell
->type
== ID($_MUX4_
)) { check_gate("ABCDSTY"); return; }
1272 if (cell
->type
== ID($_MUX8_
)) { check_gate("ABCDEFGHSTUY"); return; }
1273 if (cell
->type
== ID($_MUX16_
)) { check_gate("ABCDEFGHIJKLMNOPSTUVY"); return; }
1275 if (cell
->type
== ID($_SR_NN_
)) { check_gate("SRQ"); return; }
1276 if (cell
->type
== ID($_SR_NP_
)) { check_gate("SRQ"); return; }
1277 if (cell
->type
== ID($_SR_PN_
)) { check_gate("SRQ"); return; }
1278 if (cell
->type
== ID($_SR_PP_
)) { check_gate("SRQ"); return; }
1280 if (cell
->type
== ID($_FF_
)) { check_gate("DQ"); return; }
1281 if (cell
->type
== ID($_DFF_N_
)) { check_gate("DQC"); return; }
1282 if (cell
->type
== ID($_DFF_P_
)) { check_gate("DQC"); return; }
1284 if (cell
->type
== ID($_DFFE_NN_
)) { check_gate("DQCE"); return; }
1285 if (cell
->type
== ID($_DFFE_NP_
)) { check_gate("DQCE"); return; }
1286 if (cell
->type
== ID($_DFFE_PN_
)) { check_gate("DQCE"); return; }
1287 if (cell
->type
== ID($_DFFE_PP_
)) { check_gate("DQCE"); return; }
1289 if (cell
->type
== ID($_DFF_NN0_
)) { check_gate("DQCR"); return; }
1290 if (cell
->type
== ID($_DFF_NN1_
)) { check_gate("DQCR"); return; }
1291 if (cell
->type
== ID($_DFF_NP0_
)) { check_gate("DQCR"); return; }
1292 if (cell
->type
== ID($_DFF_NP1_
)) { check_gate("DQCR"); return; }
1293 if (cell
->type
== ID($_DFF_PN0_
)) { check_gate("DQCR"); return; }
1294 if (cell
->type
== ID($_DFF_PN1_
)) { check_gate("DQCR"); return; }
1295 if (cell
->type
== ID($_DFF_PP0_
)) { check_gate("DQCR"); return; }
1296 if (cell
->type
== ID($_DFF_PP1_
)) { check_gate("DQCR"); return; }
1298 if (cell
->type
== ID($_DFFSR_NNN_
)) { check_gate("CSRDQ"); return; }
1299 if (cell
->type
== ID($_DFFSR_NNP_
)) { check_gate("CSRDQ"); return; }
1300 if (cell
->type
== ID($_DFFSR_NPN_
)) { check_gate("CSRDQ"); return; }
1301 if (cell
->type
== ID($_DFFSR_NPP_
)) { check_gate("CSRDQ"); return; }
1302 if (cell
->type
== ID($_DFFSR_PNN_
)) { check_gate("CSRDQ"); return; }
1303 if (cell
->type
== ID($_DFFSR_PNP_
)) { check_gate("CSRDQ"); return; }
1304 if (cell
->type
== ID($_DFFSR_PPN_
)) { check_gate("CSRDQ"); return; }
1305 if (cell
->type
== ID($_DFFSR_PPP_
)) { check_gate("CSRDQ"); return; }
1307 if (cell
->type
== ID($_DLATCH_N_
)) { check_gate("EDQ"); return; }
1308 if (cell
->type
== ID($_DLATCH_P_
)) { check_gate("EDQ"); return; }
1310 if (cell
->type
== ID($_DLATCHSR_NNN_
)) { check_gate("ESRDQ"); return; }
1311 if (cell
->type
== ID($_DLATCHSR_NNP_
)) { check_gate("ESRDQ"); return; }
1312 if (cell
->type
== ID($_DLATCHSR_NPN_
)) { check_gate("ESRDQ"); return; }
1313 if (cell
->type
== ID($_DLATCHSR_NPP_
)) { check_gate("ESRDQ"); return; }
1314 if (cell
->type
== ID($_DLATCHSR_PNN_
)) { check_gate("ESRDQ"); return; }
1315 if (cell
->type
== ID($_DLATCHSR_PNP_
)) { check_gate("ESRDQ"); return; }
1316 if (cell
->type
== ID($_DLATCHSR_PPN_
)) { check_gate("ESRDQ"); return; }
1317 if (cell
->type
== ID($_DLATCHSR_PPP_
)) { check_gate("ESRDQ"); return; }
1325 void RTLIL::Module::sort()
1327 wires_
.sort(sort_by_id_str());
1328 cells_
.sort(sort_by_id_str());
1329 avail_parameters
.sort(sort_by_id_str());
1330 memories
.sort(sort_by_id_str());
1331 processes
.sort(sort_by_id_str());
1332 for (auto &it
: cells_
)
1334 for (auto &it
: wires_
)
1335 it
.second
->attributes
.sort(sort_by_id_str());
1336 for (auto &it
: memories
)
1337 it
.second
->attributes
.sort(sort_by_id_str());
1340 void RTLIL::Module::check()
1343 std::vector
<bool> ports_declared
;
1344 for (auto &it
: wires_
) {
1345 log_assert(this == it
.second
->module
);
1346 log_assert(it
.first
== it
.second
->name
);
1347 log_assert(!it
.first
.empty());
1348 log_assert(it
.second
->width
>= 0);
1349 log_assert(it
.second
->port_id
>= 0);
1350 for (auto &it2
: it
.second
->attributes
)
1351 log_assert(!it2
.first
.empty());
1352 if (it
.second
->port_id
) {
1353 log_assert(GetSize(ports
) >= it
.second
->port_id
);
1354 log_assert(ports
.at(it
.second
->port_id
-1) == it
.first
);
1355 log_assert(it
.second
->port_input
|| it
.second
->port_output
);
1356 if (GetSize(ports_declared
) < it
.second
->port_id
)
1357 ports_declared
.resize(it
.second
->port_id
);
1358 log_assert(ports_declared
[it
.second
->port_id
-1] == false);
1359 ports_declared
[it
.second
->port_id
-1] = true;
1361 log_assert(!it
.second
->port_input
&& !it
.second
->port_output
);
1363 for (auto port_declared
: ports_declared
)
1364 log_assert(port_declared
== true);
1365 log_assert(GetSize(ports
) == GetSize(ports_declared
));
1367 for (auto &it
: memories
) {
1368 log_assert(it
.first
== it
.second
->name
);
1369 log_assert(!it
.first
.empty());
1370 log_assert(it
.second
->width
>= 0);
1371 log_assert(it
.second
->size
>= 0);
1372 for (auto &it2
: it
.second
->attributes
)
1373 log_assert(!it2
.first
.empty());
1376 for (auto &it
: cells_
) {
1377 log_assert(this == it
.second
->module
);
1378 log_assert(it
.first
== it
.second
->name
);
1379 log_assert(!it
.first
.empty());
1380 log_assert(!it
.second
->type
.empty());
1381 for (auto &it2
: it
.second
->connections()) {
1382 log_assert(!it2
.first
.empty());
1385 for (auto &it2
: it
.second
->attributes
)
1386 log_assert(!it2
.first
.empty());
1387 for (auto &it2
: it
.second
->parameters
)
1388 log_assert(!it2
.first
.empty());
1389 InternalCellChecker
checker(this, it
.second
);
1393 for (auto &it
: processes
) {
1394 log_assert(it
.first
== it
.second
->name
);
1395 log_assert(!it
.first
.empty());
1396 log_assert(it
.second
->root_case
.compare
.empty());
1397 std::vector
<CaseRule
*> all_cases
= {&it
.second
->root_case
};
1398 for (size_t i
= 0; i
< all_cases
.size(); i
++) {
1399 for (auto &switch_it
: all_cases
[i
]->switches
) {
1400 for (auto &case_it
: switch_it
->cases
) {
1401 for (auto &compare_it
: case_it
->compare
) {
1402 log_assert(switch_it
->signal
.size() == compare_it
.size());
1404 all_cases
.push_back(case_it
);
1408 for (auto &sync_it
: it
.second
->syncs
) {
1409 switch (sync_it
->type
) {
1415 log_assert(!sync_it
->signal
.empty());
1420 log_assert(sync_it
->signal
.empty());
1426 for (auto &it
: connections_
) {
1427 log_assert(it
.first
.size() == it
.second
.size());
1428 log_assert(!it
.first
.has_const());
1433 for (auto &it
: attributes
)
1434 log_assert(!it
.first
.empty());
1438 void RTLIL::Module::optimize()
1442 void RTLIL::Module::cloneInto(RTLIL::Module
*new_mod
) const
1444 log_assert(new_mod
->refcount_wires_
== 0);
1445 log_assert(new_mod
->refcount_cells_
== 0);
1447 new_mod
->avail_parameters
= avail_parameters
;
1449 for (auto &conn
: connections_
)
1450 new_mod
->connect(conn
);
1452 for (auto &attr
: attributes
)
1453 new_mod
->attributes
[attr
.first
] = attr
.second
;
1455 for (auto &it
: wires_
)
1456 new_mod
->addWire(it
.first
, it
.second
);
1458 for (auto &it
: memories
)
1459 new_mod
->memories
[it
.first
] = new RTLIL::Memory(*it
.second
);
1461 for (auto &it
: cells_
)
1462 new_mod
->addCell(it
.first
, it
.second
);
1464 for (auto &it
: processes
)
1465 new_mod
->processes
[it
.first
] = it
.second
->clone();
1467 struct RewriteSigSpecWorker
1470 void operator()(RTLIL::SigSpec
&sig
)
1472 std::vector
<RTLIL::SigChunk
> chunks
= sig
.chunks();
1473 for (auto &c
: chunks
)
1475 c
.wire
= mod
->wires_
.at(c
.wire
->name
);
1480 RewriteSigSpecWorker rewriteSigSpecWorker
;
1481 rewriteSigSpecWorker
.mod
= new_mod
;
1482 new_mod
->rewrite_sigspecs(rewriteSigSpecWorker
);
1483 new_mod
->fixup_ports();
1486 RTLIL::Module
*RTLIL::Module::clone() const
1488 RTLIL::Module
*new_mod
= new RTLIL::Module
;
1489 new_mod
->name
= name
;
1494 bool RTLIL::Module::has_memories() const
1496 return !memories
.empty();
1499 bool RTLIL::Module::has_processes() const
1501 return !processes
.empty();
1504 bool RTLIL::Module::has_memories_warn() const
1506 if (!memories
.empty())
1507 log_warning("Ignoring module %s because it contains memories (run 'memory' command first).\n", log_id(this));
1508 return !memories
.empty();
1511 bool RTLIL::Module::has_processes_warn() const
1513 if (!processes
.empty())
1514 log_warning("Ignoring module %s because it contains processes (run 'proc' command first).\n", log_id(this));
1515 return !processes
.empty();
1518 std::vector
<RTLIL::Wire
*> RTLIL::Module::selected_wires() const
1520 std::vector
<RTLIL::Wire
*> result
;
1521 result
.reserve(wires_
.size());
1522 for (auto &it
: wires_
)
1523 if (design
->selected(this, it
.second
))
1524 result
.push_back(it
.second
);
1528 std::vector
<RTLIL::Cell
*> RTLIL::Module::selected_cells() const
1530 std::vector
<RTLIL::Cell
*> result
;
1531 result
.reserve(cells_
.size());
1532 for (auto &it
: cells_
)
1533 if (design
->selected(this, it
.second
))
1534 result
.push_back(it
.second
);
1538 void RTLIL::Module::add(RTLIL::Wire
*wire
)
1540 log_assert(!wire
->name
.empty());
1541 log_assert(count_id(wire
->name
) == 0);
1542 log_assert(refcount_wires_
== 0);
1543 wires_
[wire
->name
] = wire
;
1544 wire
->module
= this;
1547 void RTLIL::Module::add(RTLIL::Cell
*cell
)
1549 log_assert(!cell
->name
.empty());
1550 log_assert(count_id(cell
->name
) == 0);
1551 log_assert(refcount_cells_
== 0);
1552 cells_
[cell
->name
] = cell
;
1553 cell
->module
= this;
1556 void RTLIL::Module::remove(const pool
<RTLIL::Wire
*> &wires
)
1558 log_assert(refcount_wires_
== 0);
1560 struct DeleteWireWorker
1562 RTLIL::Module
*module
;
1563 const pool
<RTLIL::Wire
*> *wires_p
;
1565 void operator()(RTLIL::SigSpec
&sig
) {
1566 std::vector
<RTLIL::SigChunk
> chunks
= sig
;
1567 for (auto &c
: chunks
)
1568 if (c
.wire
!= NULL
&& wires_p
->count(c
.wire
)) {
1569 c
.wire
= module
->addWire(NEW_ID
, c
.width
);
1575 void operator()(RTLIL::SigSpec
&lhs
, RTLIL::SigSpec
&rhs
) {
1576 log_assert(GetSize(lhs
) == GetSize(rhs
));
1577 RTLIL::SigSpec new_lhs
, new_rhs
;
1578 for (int i
= 0; i
< GetSize(lhs
); i
++) {
1579 RTLIL::SigBit lhs_bit
= lhs
[i
];
1580 if (lhs_bit
.wire
!= nullptr && wires_p
->count(lhs_bit
.wire
))
1582 RTLIL::SigBit rhs_bit
= rhs
[i
];
1583 if (rhs_bit
.wire
!= nullptr && wires_p
->count(rhs_bit
.wire
))
1585 new_lhs
.append(lhs_bit
);
1586 new_rhs
.append(rhs_bit
);
1593 DeleteWireWorker delete_wire_worker
;
1594 delete_wire_worker
.module
= this;
1595 delete_wire_worker
.wires_p
= &wires
;
1596 rewrite_sigspecs2(delete_wire_worker
);
1598 for (auto &it
: wires
) {
1599 log_assert(wires_
.count(it
->name
) != 0);
1600 wires_
.erase(it
->name
);
1605 void RTLIL::Module::remove(RTLIL::Cell
*cell
)
1607 while (!cell
->connections_
.empty())
1608 cell
->unsetPort(cell
->connections_
.begin()->first
);
1610 log_assert(cells_
.count(cell
->name
) != 0);
1611 log_assert(refcount_cells_
== 0);
1612 cells_
.erase(cell
->name
);
1616 void RTLIL::Module::rename(RTLIL::Wire
*wire
, RTLIL::IdString new_name
)
1618 log_assert(wires_
[wire
->name
] == wire
);
1619 log_assert(refcount_wires_
== 0);
1620 wires_
.erase(wire
->name
);
1621 wire
->name
= new_name
;
1625 void RTLIL::Module::rename(RTLIL::Cell
*cell
, RTLIL::IdString new_name
)
1627 log_assert(cells_
[cell
->name
] == cell
);
1628 log_assert(refcount_wires_
== 0);
1629 cells_
.erase(cell
->name
);
1630 cell
->name
= new_name
;
1634 void RTLIL::Module::rename(RTLIL::IdString old_name
, RTLIL::IdString new_name
)
1636 log_assert(count_id(old_name
) != 0);
1637 if (wires_
.count(old_name
))
1638 rename(wires_
.at(old_name
), new_name
);
1639 else if (cells_
.count(old_name
))
1640 rename(cells_
.at(old_name
), new_name
);
1645 void RTLIL::Module::swap_names(RTLIL::Wire
*w1
, RTLIL::Wire
*w2
)
1647 log_assert(wires_
[w1
->name
] == w1
);
1648 log_assert(wires_
[w2
->name
] == w2
);
1649 log_assert(refcount_wires_
== 0);
1651 wires_
.erase(w1
->name
);
1652 wires_
.erase(w2
->name
);
1654 std::swap(w1
->name
, w2
->name
);
1656 wires_
[w1
->name
] = w1
;
1657 wires_
[w2
->name
] = w2
;
1660 void RTLIL::Module::swap_names(RTLIL::Cell
*c1
, RTLIL::Cell
*c2
)
1662 log_assert(cells_
[c1
->name
] == c1
);
1663 log_assert(cells_
[c2
->name
] == c2
);
1664 log_assert(refcount_cells_
== 0);
1666 cells_
.erase(c1
->name
);
1667 cells_
.erase(c2
->name
);
1669 std::swap(c1
->name
, c2
->name
);
1671 cells_
[c1
->name
] = c1
;
1672 cells_
[c2
->name
] = c2
;
1675 RTLIL::IdString
RTLIL::Module::uniquify(RTLIL::IdString name
)
1678 return uniquify(name
, index
);
1681 RTLIL::IdString
RTLIL::Module::uniquify(RTLIL::IdString name
, int &index
)
1684 if (count_id(name
) == 0)
1690 RTLIL::IdString new_name
= stringf("%s_%d", name
.c_str(), index
);
1691 if (count_id(new_name
) == 0)
1697 static bool fixup_ports_compare(const RTLIL::Wire
*a
, const RTLIL::Wire
*b
)
1699 if (a
->port_id
&& !b
->port_id
)
1701 if (!a
->port_id
&& b
->port_id
)
1704 if (a
->port_id
== b
->port_id
)
1705 return a
->name
< b
->name
;
1706 return a
->port_id
< b
->port_id
;
1709 void RTLIL::Module::connect(const RTLIL::SigSig
&conn
)
1711 for (auto mon
: monitors
)
1712 mon
->notify_connect(this, conn
);
1715 for (auto mon
: design
->monitors
)
1716 mon
->notify_connect(this, conn
);
1718 // ignore all attempts to assign constants to other constants
1719 if (conn
.first
.has_const()) {
1720 RTLIL::SigSig new_conn
;
1721 for (int i
= 0; i
< GetSize(conn
.first
); i
++)
1722 if (conn
.first
[i
].wire
) {
1723 new_conn
.first
.append(conn
.first
[i
]);
1724 new_conn
.second
.append(conn
.second
[i
]);
1726 if (GetSize(new_conn
.first
))
1732 log("#X# Connect (SigSig) in %s: %s = %s (%d bits)\n", log_id(this), log_signal(conn
.first
), log_signal(conn
.second
), GetSize(conn
.first
));
1733 log_backtrace("-X- ", yosys_xtrace
-1);
1736 log_assert(GetSize(conn
.first
) == GetSize(conn
.second
));
1737 connections_
.push_back(conn
);
1740 void RTLIL::Module::connect(const RTLIL::SigSpec
&lhs
, const RTLIL::SigSpec
&rhs
)
1742 connect(RTLIL::SigSig(lhs
, rhs
));
1745 void RTLIL::Module::new_connections(const std::vector
<RTLIL::SigSig
> &new_conn
)
1747 for (auto mon
: monitors
)
1748 mon
->notify_connect(this, new_conn
);
1751 for (auto mon
: design
->monitors
)
1752 mon
->notify_connect(this, new_conn
);
1755 log("#X# New connections vector in %s:\n", log_id(this));
1756 for (auto &conn
: new_conn
)
1757 log("#X# %s = %s (%d bits)\n", log_signal(conn
.first
), log_signal(conn
.second
), GetSize(conn
.first
));
1758 log_backtrace("-X- ", yosys_xtrace
-1);
1761 connections_
= new_conn
;
1764 const std::vector
<RTLIL::SigSig
> &RTLIL::Module::connections() const
1766 return connections_
;
1769 void RTLIL::Module::fixup_ports()
1771 std::vector
<RTLIL::Wire
*> all_ports
;
1773 for (auto &w
: wires_
)
1774 if (w
.second
->port_input
|| w
.second
->port_output
)
1775 all_ports
.push_back(w
.second
);
1777 w
.second
->port_id
= 0;
1779 std::sort(all_ports
.begin(), all_ports
.end(), fixup_ports_compare
);
1782 for (size_t i
= 0; i
< all_ports
.size(); i
++) {
1783 ports
.push_back(all_ports
[i
]->name
);
1784 all_ports
[i
]->port_id
= i
+1;
1788 RTLIL::Wire
*RTLIL::Module::addWire(RTLIL::IdString name
, int width
)
1790 RTLIL::Wire
*wire
= new RTLIL::Wire
;
1792 wire
->width
= width
;
1797 RTLIL::Wire
*RTLIL::Module::addWire(RTLIL::IdString name
, const RTLIL::Wire
*other
)
1799 RTLIL::Wire
*wire
= addWire(name
);
1800 wire
->width
= other
->width
;
1801 wire
->start_offset
= other
->start_offset
;
1802 wire
->port_id
= other
->port_id
;
1803 wire
->port_input
= other
->port_input
;
1804 wire
->port_output
= other
->port_output
;
1805 wire
->upto
= other
->upto
;
1806 wire
->attributes
= other
->attributes
;
1810 RTLIL::Cell
*RTLIL::Module::addCell(RTLIL::IdString name
, RTLIL::IdString type
)
1812 RTLIL::Cell
*cell
= new RTLIL::Cell
;
1819 RTLIL::Cell
*RTLIL::Module::addCell(RTLIL::IdString name
, const RTLIL::Cell
*other
)
1821 RTLIL::Cell
*cell
= addCell(name
, other
->type
);
1822 cell
->connections_
= other
->connections_
;
1823 cell
->parameters
= other
->parameters
;
1824 cell
->attributes
= other
->attributes
;
1828 #define DEF_METHOD(_func, _y_size, _type) \
1829 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed, const std::string &src) { \
1830 RTLIL::Cell *cell = addCell(name, _type); \
1831 cell->parameters[ID(A_SIGNED)] = is_signed; \
1832 cell->parameters[ID(A_WIDTH)] = sig_a.size(); \
1833 cell->parameters[ID(Y_WIDTH)] = sig_y.size(); \
1834 cell->setPort(ID::A, sig_a); \
1835 cell->setPort(ID::Y, sig_y); \
1836 cell->set_src_attribute(src); \
1839 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed, const std::string &src) { \
1840 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
1841 add ## _func(name, sig_a, sig_y, is_signed, src); \
1844 DEF_METHOD(Not
, sig_a
.size(), ID($
not))
1845 DEF_METHOD(Pos
, sig_a
.size(), ID($pos
))
1846 DEF_METHOD(Neg
, sig_a
.size(), ID($neg
))
1847 DEF_METHOD(ReduceAnd
, 1, ID($reduce_and
))
1848 DEF_METHOD(ReduceOr
, 1, ID($reduce_or
))
1849 DEF_METHOD(ReduceXor
, 1, ID($reduce_xor
))
1850 DEF_METHOD(ReduceXnor
, 1, ID($reduce_xnor
))
1851 DEF_METHOD(ReduceBool
, 1, ID($reduce_bool
))
1852 DEF_METHOD(LogicNot
, 1, ID($logic_not
))
1855 #define DEF_METHOD(_func, _y_size, _type) \
1856 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed, const std::string &src) { \
1857 RTLIL::Cell *cell = addCell(name, _type); \
1858 cell->parameters[ID(A_SIGNED)] = is_signed; \
1859 cell->parameters[ID(B_SIGNED)] = is_signed; \
1860 cell->parameters[ID(A_WIDTH)] = sig_a.size(); \
1861 cell->parameters[ID(B_WIDTH)] = sig_b.size(); \
1862 cell->parameters[ID(Y_WIDTH)] = sig_y.size(); \
1863 cell->setPort(ID::A, sig_a); \
1864 cell->setPort(ID::B, sig_b); \
1865 cell->setPort(ID::Y, sig_y); \
1866 cell->set_src_attribute(src); \
1869 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed, const std::string &src) { \
1870 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
1871 add ## _func(name, sig_a, sig_b, sig_y, is_signed, src); \
1874 DEF_METHOD(And
, max(sig_a
.size(), sig_b
.size()), ID($
and))
1875 DEF_METHOD(Or
, max(sig_a
.size(), sig_b
.size()), ID($
or))
1876 DEF_METHOD(Xor
, max(sig_a
.size(), sig_b
.size()), ID($
xor))
1877 DEF_METHOD(Xnor
, max(sig_a
.size(), sig_b
.size()), ID($xnor
))
1878 DEF_METHOD(Shl
, sig_a
.size(), ID($shl
))
1879 DEF_METHOD(Shr
, sig_a
.size(), ID($shr
))
1880 DEF_METHOD(Sshl
, sig_a
.size(), ID($sshl
))
1881 DEF_METHOD(Sshr
, sig_a
.size(), ID($sshr
))
1882 DEF_METHOD(Shift
, sig_a
.size(), ID($shift
))
1883 DEF_METHOD(Shiftx
, sig_a
.size(), ID($shiftx
))
1884 DEF_METHOD(Lt
, 1, ID($lt
))
1885 DEF_METHOD(Le
, 1, ID($le
))
1886 DEF_METHOD(Eq
, 1, ID($eq
))
1887 DEF_METHOD(Ne
, 1, ID($ne
))
1888 DEF_METHOD(Eqx
, 1, ID($eqx
))
1889 DEF_METHOD(Nex
, 1, ID($nex
))
1890 DEF_METHOD(Ge
, 1, ID($ge
))
1891 DEF_METHOD(Gt
, 1, ID($gt
))
1892 DEF_METHOD(Add
, max(sig_a
.size(), sig_b
.size()), ID($add
))
1893 DEF_METHOD(Sub
, max(sig_a
.size(), sig_b
.size()), ID($sub
))
1894 DEF_METHOD(Mul
, max(sig_a
.size(), sig_b
.size()), ID($mul
))
1895 DEF_METHOD(Div
, max(sig_a
.size(), sig_b
.size()), ID($div
))
1896 DEF_METHOD(Mod
, max(sig_a
.size(), sig_b
.size()), ID($mod
))
1897 DEF_METHOD(LogicAnd
, 1, ID($logic_and
))
1898 DEF_METHOD(LogicOr
, 1, ID($logic_or
))
1901 #define DEF_METHOD(_func, _type, _pmux) \
1902 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, RTLIL::SigSpec sig_y, const std::string &src) { \
1903 RTLIL::Cell *cell = addCell(name, _type); \
1904 cell->parameters[ID(WIDTH)] = sig_a.size(); \
1905 if (_pmux) cell->parameters[ID(S_WIDTH)] = sig_s.size(); \
1906 cell->setPort(ID::A, sig_a); \
1907 cell->setPort(ID::B, sig_b); \
1908 cell->setPort(ID(S), sig_s); \
1909 cell->setPort(ID::Y, sig_y); \
1910 cell->set_src_attribute(src); \
1913 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, const std::string &src) { \
1914 RTLIL::SigSpec sig_y = addWire(NEW_ID, sig_a.size()); \
1915 add ## _func(name, sig_a, sig_b, sig_s, sig_y, src); \
1918 DEF_METHOD(Mux
, ID($mux
), 0)
1919 DEF_METHOD(Pmux
, ID($pmux
), 1)
1922 #define DEF_METHOD_2(_func, _type, _P1, _P2) \
1923 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, const std::string &src) { \
1924 RTLIL::Cell *cell = addCell(name, _type); \
1925 cell->setPort("\\" #_P1, sig1); \
1926 cell->setPort("\\" #_P2, sig2); \
1927 cell->set_src_attribute(src); \
1930 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, const std::string &src) { \
1931 RTLIL::SigBit sig2 = addWire(NEW_ID); \
1932 add ## _func(name, sig1, sig2, src); \
1935 #define DEF_METHOD_3(_func, _type, _P1, _P2, _P3) \
1936 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, const std::string &src) { \
1937 RTLIL::Cell *cell = addCell(name, _type); \
1938 cell->setPort("\\" #_P1, sig1); \
1939 cell->setPort("\\" #_P2, sig2); \
1940 cell->setPort("\\" #_P3, sig3); \
1941 cell->set_src_attribute(src); \
1944 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, const std::string &src) { \
1945 RTLIL::SigBit sig3 = addWire(NEW_ID); \
1946 add ## _func(name, sig1, sig2, sig3, src); \
1949 #define DEF_METHOD_4(_func, _type, _P1, _P2, _P3, _P4) \
1950 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, RTLIL::SigBit sig4, const std::string &src) { \
1951 RTLIL::Cell *cell = addCell(name, _type); \
1952 cell->setPort("\\" #_P1, sig1); \
1953 cell->setPort("\\" #_P2, sig2); \
1954 cell->setPort("\\" #_P3, sig3); \
1955 cell->setPort("\\" #_P4, sig4); \
1956 cell->set_src_attribute(src); \
1959 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, const std::string &src) { \
1960 RTLIL::SigBit sig4 = addWire(NEW_ID); \
1961 add ## _func(name, sig1, sig2, sig3, sig4, src); \
1964 #define DEF_METHOD_5(_func, _type, _P1, _P2, _P3, _P4, _P5) \
1965 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, RTLIL::SigBit sig4, RTLIL::SigBit sig5, const std::string &src) { \
1966 RTLIL::Cell *cell = addCell(name, _type); \
1967 cell->setPort("\\" #_P1, sig1); \
1968 cell->setPort("\\" #_P2, sig2); \
1969 cell->setPort("\\" #_P3, sig3); \
1970 cell->setPort("\\" #_P4, sig4); \
1971 cell->setPort("\\" #_P5, sig5); \
1972 cell->set_src_attribute(src); \
1975 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, RTLIL::SigBit sig4, const std::string &src) { \
1976 RTLIL::SigBit sig5 = addWire(NEW_ID); \
1977 add ## _func(name, sig1, sig2, sig3, sig4, sig5, src); \
1980 DEF_METHOD_2(BufGate
, ID($_BUF_
), A
, Y
)
1981 DEF_METHOD_2(NotGate
, ID($_NOT_
), A
, Y
)
1982 DEF_METHOD_3(AndGate
, ID($_AND_
), A
, B
, Y
)
1983 DEF_METHOD_3(NandGate
, ID($_NAND_
), A
, B
, Y
)
1984 DEF_METHOD_3(OrGate
, ID($_OR_
), A
, B
, Y
)
1985 DEF_METHOD_3(NorGate
, ID($_NOR_
), A
, B
, Y
)
1986 DEF_METHOD_3(XorGate
, ID($_XOR_
), A
, B
, Y
)
1987 DEF_METHOD_3(XnorGate
, ID($_XNOR_
), A
, B
, Y
)
1988 DEF_METHOD_3(AndnotGate
, ID($_ANDNOT_
), A
, B
, Y
)
1989 DEF_METHOD_3(OrnotGate
, ID($_ORNOT_
), A
, B
, Y
)
1990 DEF_METHOD_4(MuxGate
, ID($_MUX_
), A
, B
, S
, Y
)
1991 DEF_METHOD_4(NmuxGate
, ID($_NMUX_
), A
, B
, S
, Y
)
1992 DEF_METHOD_4(Aoi3Gate
, ID($_AOI3_
), A
, B
, C
, Y
)
1993 DEF_METHOD_4(Oai3Gate
, ID($_OAI3_
), A
, B
, C
, Y
)
1994 DEF_METHOD_5(Aoi4Gate
, ID($_AOI4_
), A
, B
, C
, D
, Y
)
1995 DEF_METHOD_5(Oai4Gate
, ID($_OAI4_
), A
, B
, C
, D
, Y
)
2001 RTLIL::Cell
* RTLIL::Module::addPow(RTLIL::IdString name
, RTLIL::SigSpec sig_a
, RTLIL::SigSpec sig_b
, RTLIL::SigSpec sig_y
, bool a_signed
, bool b_signed
, const std::string
&src
)
2003 RTLIL::Cell
*cell
= addCell(name
, ID($pow
));
2004 cell
->parameters
[ID(A_SIGNED
)] = a_signed
;
2005 cell
->parameters
[ID(B_SIGNED
)] = b_signed
;
2006 cell
->parameters
[ID(A_WIDTH
)] = sig_a
.size();
2007 cell
->parameters
[ID(B_WIDTH
)] = sig_b
.size();
2008 cell
->parameters
[ID(Y_WIDTH
)] = sig_y
.size();
2009 cell
->setPort(ID::A
, sig_a
);
2010 cell
->setPort(ID::B
, sig_b
);
2011 cell
->setPort(ID::Y
, sig_y
);
2012 cell
->set_src_attribute(src
);
2016 RTLIL::Cell
* RTLIL::Module::addSlice(RTLIL::IdString name
, RTLIL::SigSpec sig_a
, RTLIL::SigSpec sig_y
, RTLIL::Const offset
, const std::string
&src
)
2018 RTLIL::Cell
*cell
= addCell(name
, ID($slice
));
2019 cell
->parameters
[ID(A_WIDTH
)] = sig_a
.size();
2020 cell
->parameters
[ID(Y_WIDTH
)] = sig_y
.size();
2021 cell
->parameters
[ID(OFFSET
)] = offset
;
2022 cell
->setPort(ID::A
, sig_a
);
2023 cell
->setPort(ID::Y
, sig_y
);
2024 cell
->set_src_attribute(src
);
2028 RTLIL::Cell
* RTLIL::Module::addConcat(RTLIL::IdString name
, RTLIL::SigSpec sig_a
, RTLIL::SigSpec sig_b
, RTLIL::SigSpec sig_y
, const std::string
&src
)
2030 RTLIL::Cell
*cell
= addCell(name
, ID($concat
));
2031 cell
->parameters
[ID(A_WIDTH
)] = sig_a
.size();
2032 cell
->parameters
[ID(B_WIDTH
)] = sig_b
.size();
2033 cell
->setPort(ID::A
, sig_a
);
2034 cell
->setPort(ID::B
, sig_b
);
2035 cell
->setPort(ID::Y
, sig_y
);
2036 cell
->set_src_attribute(src
);
2040 RTLIL::Cell
* RTLIL::Module::addLut(RTLIL::IdString name
, RTLIL::SigSpec sig_a
, RTLIL::SigSpec sig_y
, RTLIL::Const lut
, const std::string
&src
)
2042 RTLIL::Cell
*cell
= addCell(name
, ID($lut
));
2043 cell
->parameters
[ID(LUT
)] = lut
;
2044 cell
->parameters
[ID(WIDTH
)] = sig_a
.size();
2045 cell
->setPort(ID::A
, sig_a
);
2046 cell
->setPort(ID::Y
, sig_y
);
2047 cell
->set_src_attribute(src
);
2051 RTLIL::Cell
* RTLIL::Module::addTribuf(RTLIL::IdString name
, RTLIL::SigSpec sig_a
, RTLIL::SigSpec sig_en
, RTLIL::SigSpec sig_y
, const std::string
&src
)
2053 RTLIL::Cell
*cell
= addCell(name
, ID($tribuf
));
2054 cell
->parameters
[ID(WIDTH
)] = sig_a
.size();
2055 cell
->setPort(ID::A
, sig_a
);
2056 cell
->setPort(ID(EN
), sig_en
);
2057 cell
->setPort(ID::Y
, sig_y
);
2058 cell
->set_src_attribute(src
);
2062 RTLIL::Cell
* RTLIL::Module::addAssert(RTLIL::IdString name
, RTLIL::SigSpec sig_a
, RTLIL::SigSpec sig_en
, const std::string
&src
)
2064 RTLIL::Cell
*cell
= addCell(name
, ID($
assert));
2065 cell
->setPort(ID::A
, sig_a
);
2066 cell
->setPort(ID(EN
), sig_en
);
2067 cell
->set_src_attribute(src
);
2071 RTLIL::Cell
* RTLIL::Module::addAssume(RTLIL::IdString name
, RTLIL::SigSpec sig_a
, RTLIL::SigSpec sig_en
, const std::string
&src
)
2073 RTLIL::Cell
*cell
= addCell(name
, ID($assume
));
2074 cell
->setPort(ID::A
, sig_a
);
2075 cell
->setPort(ID(EN
), sig_en
);
2076 cell
->set_src_attribute(src
);
2080 RTLIL::Cell
* RTLIL::Module::addLive(RTLIL::IdString name
, RTLIL::SigSpec sig_a
, RTLIL::SigSpec sig_en
, const std::string
&src
)
2082 RTLIL::Cell
*cell
= addCell(name
, ID($live
));
2083 cell
->setPort(ID::A
, sig_a
);
2084 cell
->setPort(ID(EN
), sig_en
);
2085 cell
->set_src_attribute(src
);
2089 RTLIL::Cell
* RTLIL::Module::addFair(RTLIL::IdString name
, RTLIL::SigSpec sig_a
, RTLIL::SigSpec sig_en
, const std::string
&src
)
2091 RTLIL::Cell
*cell
= addCell(name
, ID($fair
));
2092 cell
->setPort(ID::A
, sig_a
);
2093 cell
->setPort(ID(EN
), sig_en
);
2094 cell
->set_src_attribute(src
);
2098 RTLIL::Cell
* RTLIL::Module::addCover(RTLIL::IdString name
, RTLIL::SigSpec sig_a
, RTLIL::SigSpec sig_en
, const std::string
&src
)
2100 RTLIL::Cell
*cell
= addCell(name
, ID($cover
));
2101 cell
->setPort(ID::A
, sig_a
);
2102 cell
->setPort(ID(EN
), sig_en
);
2103 cell
->set_src_attribute(src
);
2107 RTLIL::Cell
* RTLIL::Module::addEquiv(RTLIL::IdString name
, RTLIL::SigSpec sig_a
, RTLIL::SigSpec sig_b
, RTLIL::SigSpec sig_y
, const std::string
&src
)
2109 RTLIL::Cell
*cell
= addCell(name
, ID($equiv
));
2110 cell
->setPort(ID::A
, sig_a
);
2111 cell
->setPort(ID::B
, sig_b
);
2112 cell
->setPort(ID::Y
, sig_y
);
2113 cell
->set_src_attribute(src
);
2117 RTLIL::Cell
* RTLIL::Module::addSr(RTLIL::IdString name
, RTLIL::SigSpec sig_set
, RTLIL::SigSpec sig_clr
, RTLIL::SigSpec sig_q
, bool set_polarity
, bool clr_polarity
, const std::string
&src
)
2119 RTLIL::Cell
*cell
= addCell(name
, ID($sr
));
2120 cell
->parameters
[ID(SET_POLARITY
)] = set_polarity
;
2121 cell
->parameters
[ID(CLR_POLARITY
)] = clr_polarity
;
2122 cell
->parameters
[ID(WIDTH
)] = sig_q
.size();
2123 cell
->setPort(ID(SET
), sig_set
);
2124 cell
->setPort(ID(CLR
), sig_clr
);
2125 cell
->setPort(ID(Q
), sig_q
);
2126 cell
->set_src_attribute(src
);
2130 RTLIL::Cell
* RTLIL::Module::addFf(RTLIL::IdString name
, RTLIL::SigSpec sig_d
, RTLIL::SigSpec sig_q
, const std::string
&src
)
2132 RTLIL::Cell
*cell
= addCell(name
, ID($ff
));
2133 cell
->parameters
[ID(WIDTH
)] = sig_q
.size();
2134 cell
->setPort(ID(D
), sig_d
);
2135 cell
->setPort(ID(Q
), sig_q
);
2136 cell
->set_src_attribute(src
);
2140 RTLIL::Cell
* RTLIL::Module::addDff(RTLIL::IdString name
, RTLIL::SigSpec sig_clk
, RTLIL::SigSpec sig_d
, RTLIL::SigSpec sig_q
, bool clk_polarity
, const std::string
&src
)
2142 RTLIL::Cell
*cell
= addCell(name
, ID($dff
));
2143 cell
->parameters
[ID(CLK_POLARITY
)] = clk_polarity
;
2144 cell
->parameters
[ID(WIDTH
)] = sig_q
.size();
2145 cell
->setPort(ID(CLK
), sig_clk
);
2146 cell
->setPort(ID(D
), sig_d
);
2147 cell
->setPort(ID(Q
), sig_q
);
2148 cell
->set_src_attribute(src
);
2152 RTLIL::Cell
* RTLIL::Module::addDffe(RTLIL::IdString name
, RTLIL::SigSpec sig_clk
, RTLIL::SigSpec sig_en
, RTLIL::SigSpec sig_d
, RTLIL::SigSpec sig_q
, bool clk_polarity
, bool en_polarity
, const std::string
&src
)
2154 RTLIL::Cell
*cell
= addCell(name
, ID($dffe
));
2155 cell
->parameters
[ID(CLK_POLARITY
)] = clk_polarity
;
2156 cell
->parameters
[ID(EN_POLARITY
)] = en_polarity
;
2157 cell
->parameters
[ID(WIDTH
)] = sig_q
.size();
2158 cell
->setPort(ID(CLK
), sig_clk
);
2159 cell
->setPort(ID(EN
), sig_en
);
2160 cell
->setPort(ID(D
), sig_d
);
2161 cell
->setPort(ID(Q
), sig_q
);
2162 cell
->set_src_attribute(src
);
2166 RTLIL::Cell
* RTLIL::Module::addDffsr(RTLIL::IdString name
, RTLIL::SigSpec sig_clk
, RTLIL::SigSpec sig_set
, RTLIL::SigSpec sig_clr
,
2167 RTLIL::SigSpec sig_d
, RTLIL::SigSpec sig_q
, bool clk_polarity
, bool set_polarity
, bool clr_polarity
, const std::string
&src
)
2169 RTLIL::Cell
*cell
= addCell(name
, ID($dffsr
));
2170 cell
->parameters
[ID(CLK_POLARITY
)] = clk_polarity
;
2171 cell
->parameters
[ID(SET_POLARITY
)] = set_polarity
;
2172 cell
->parameters
[ID(CLR_POLARITY
)] = clr_polarity
;
2173 cell
->parameters
[ID(WIDTH
)] = sig_q
.size();
2174 cell
->setPort(ID(CLK
), sig_clk
);
2175 cell
->setPort(ID(SET
), sig_set
);
2176 cell
->setPort(ID(CLR
), sig_clr
);
2177 cell
->setPort(ID(D
), sig_d
);
2178 cell
->setPort(ID(Q
), sig_q
);
2179 cell
->set_src_attribute(src
);
2183 RTLIL::Cell
* RTLIL::Module::addAdff(RTLIL::IdString name
, RTLIL::SigSpec sig_clk
, RTLIL::SigSpec sig_arst
, RTLIL::SigSpec sig_d
, RTLIL::SigSpec sig_q
,
2184 RTLIL::Const arst_value
, bool clk_polarity
, bool arst_polarity
, const std::string
&src
)
2186 RTLIL::Cell
*cell
= addCell(name
, ID($adff
));
2187 cell
->parameters
[ID(CLK_POLARITY
)] = clk_polarity
;
2188 cell
->parameters
[ID(ARST_POLARITY
)] = arst_polarity
;
2189 cell
->parameters
[ID(ARST_VALUE
)] = arst_value
;
2190 cell
->parameters
[ID(WIDTH
)] = sig_q
.size();
2191 cell
->setPort(ID(CLK
), sig_clk
);
2192 cell
->setPort(ID(ARST
), sig_arst
);
2193 cell
->setPort(ID(D
), sig_d
);
2194 cell
->setPort(ID(Q
), sig_q
);
2195 cell
->set_src_attribute(src
);
2199 RTLIL::Cell
* RTLIL::Module::addDlatch(RTLIL::IdString name
, RTLIL::SigSpec sig_en
, RTLIL::SigSpec sig_d
, RTLIL::SigSpec sig_q
, bool en_polarity
, const std::string
&src
)
2201 RTLIL::Cell
*cell
= addCell(name
, ID($dlatch
));
2202 cell
->parameters
[ID(EN_POLARITY
)] = en_polarity
;
2203 cell
->parameters
[ID(WIDTH
)] = sig_q
.size();
2204 cell
->setPort(ID(EN
), sig_en
);
2205 cell
->setPort(ID(D
), sig_d
);
2206 cell
->setPort(ID(Q
), sig_q
);
2207 cell
->set_src_attribute(src
);
2211 RTLIL::Cell
* RTLIL::Module::addDlatchsr(RTLIL::IdString name
, RTLIL::SigSpec sig_en
, RTLIL::SigSpec sig_set
, RTLIL::SigSpec sig_clr
,
2212 RTLIL::SigSpec sig_d
, RTLIL::SigSpec sig_q
, bool en_polarity
, bool set_polarity
, bool clr_polarity
, const std::string
&src
)
2214 RTLIL::Cell
*cell
= addCell(name
, ID($dlatchsr
));
2215 cell
->parameters
[ID(EN_POLARITY
)] = en_polarity
;
2216 cell
->parameters
[ID(SET_POLARITY
)] = set_polarity
;
2217 cell
->parameters
[ID(CLR_POLARITY
)] = clr_polarity
;
2218 cell
->parameters
[ID(WIDTH
)] = sig_q
.size();
2219 cell
->setPort(ID(EN
), sig_en
);
2220 cell
->setPort(ID(SET
), sig_set
);
2221 cell
->setPort(ID(CLR
), sig_clr
);
2222 cell
->setPort(ID(D
), sig_d
);
2223 cell
->setPort(ID(Q
), sig_q
);
2224 cell
->set_src_attribute(src
);
2228 RTLIL::Cell
* RTLIL::Module::addFfGate(RTLIL::IdString name
, RTLIL::SigSpec sig_d
, RTLIL::SigSpec sig_q
, const std::string
&src
)
2230 RTLIL::Cell
*cell
= addCell(name
, ID($_FF_
));
2231 cell
->setPort(ID(D
), sig_d
);
2232 cell
->setPort(ID(Q
), sig_q
);
2233 cell
->set_src_attribute(src
);
2237 RTLIL::Cell
* RTLIL::Module::addDffGate(RTLIL::IdString name
, RTLIL::SigSpec sig_clk
, RTLIL::SigSpec sig_d
, RTLIL::SigSpec sig_q
, bool clk_polarity
, const std::string
&src
)
2239 RTLIL::Cell
*cell
= addCell(name
, stringf("$_DFF_%c_", clk_polarity
? 'P' : 'N'));
2240 cell
->setPort(ID(C
), sig_clk
);
2241 cell
->setPort(ID(D
), sig_d
);
2242 cell
->setPort(ID(Q
), sig_q
);
2243 cell
->set_src_attribute(src
);
2247 RTLIL::Cell
* RTLIL::Module::addDffeGate(RTLIL::IdString name
, RTLIL::SigSpec sig_clk
, RTLIL::SigSpec sig_en
, RTLIL::SigSpec sig_d
, RTLIL::SigSpec sig_q
, bool clk_polarity
, bool en_polarity
, const std::string
&src
)
2249 RTLIL::Cell
*cell
= addCell(name
, stringf("$_DFFE_%c%c_", clk_polarity
? 'P' : 'N', en_polarity
? 'P' : 'N'));
2250 cell
->setPort(ID(C
), sig_clk
);
2251 cell
->setPort(ID(E
), sig_en
);
2252 cell
->setPort(ID(D
), sig_d
);
2253 cell
->setPort(ID(Q
), sig_q
);
2254 cell
->set_src_attribute(src
);
2258 RTLIL::Cell
* RTLIL::Module::addDffsrGate(RTLIL::IdString name
, RTLIL::SigSpec sig_clk
, RTLIL::SigSpec sig_set
, RTLIL::SigSpec sig_clr
,
2259 RTLIL::SigSpec sig_d
, RTLIL::SigSpec sig_q
, bool clk_polarity
, bool set_polarity
, bool clr_polarity
, const std::string
&src
)
2261 RTLIL::Cell
*cell
= addCell(name
, stringf("$_DFFSR_%c%c%c_", clk_polarity
? 'P' : 'N', set_polarity
? 'P' : 'N', clr_polarity
? 'P' : 'N'));
2262 cell
->setPort(ID(C
), sig_clk
);
2263 cell
->setPort(ID(S
), sig_set
);
2264 cell
->setPort(ID(R
), sig_clr
);
2265 cell
->setPort(ID(D
), sig_d
);
2266 cell
->setPort(ID(Q
), sig_q
);
2267 cell
->set_src_attribute(src
);
2271 RTLIL::Cell
* RTLIL::Module::addAdffGate(RTLIL::IdString name
, RTLIL::SigSpec sig_clk
, RTLIL::SigSpec sig_arst
, RTLIL::SigSpec sig_d
, RTLIL::SigSpec sig_q
,
2272 bool arst_value
, bool clk_polarity
, bool arst_polarity
, const std::string
&src
)
2274 RTLIL::Cell
*cell
= addCell(name
, stringf("$_DFF_%c%c%c_", clk_polarity
? 'P' : 'N', arst_polarity
? 'P' : 'N', arst_value
? '1' : '0'));
2275 cell
->setPort(ID(C
), sig_clk
);
2276 cell
->setPort(ID(R
), sig_arst
);
2277 cell
->setPort(ID(D
), sig_d
);
2278 cell
->setPort(ID(Q
), sig_q
);
2279 cell
->set_src_attribute(src
);
2283 RTLIL::Cell
* RTLIL::Module::addDlatchGate(RTLIL::IdString name
, RTLIL::SigSpec sig_en
, RTLIL::SigSpec sig_d
, RTLIL::SigSpec sig_q
, bool en_polarity
, const std::string
&src
)
2285 RTLIL::Cell
*cell
= addCell(name
, stringf("$_DLATCH_%c_", en_polarity
? 'P' : 'N'));
2286 cell
->setPort(ID(E
), sig_en
);
2287 cell
->setPort(ID(D
), sig_d
);
2288 cell
->setPort(ID(Q
), sig_q
);
2289 cell
->set_src_attribute(src
);
2293 RTLIL::Cell
* RTLIL::Module::addDlatchsrGate(RTLIL::IdString name
, RTLIL::SigSpec sig_en
, RTLIL::SigSpec sig_set
, RTLIL::SigSpec sig_clr
,
2294 RTLIL::SigSpec sig_d
, RTLIL::SigSpec sig_q
, bool en_polarity
, bool set_polarity
, bool clr_polarity
, const std::string
&src
)
2296 RTLIL::Cell
*cell
= addCell(name
, stringf("$_DLATCHSR_%c%c%c_", en_polarity
? 'P' : 'N', set_polarity
? 'P' : 'N', clr_polarity
? 'P' : 'N'));
2297 cell
->setPort(ID(E
), sig_en
);
2298 cell
->setPort(ID(S
), sig_set
);
2299 cell
->setPort(ID(R
), sig_clr
);
2300 cell
->setPort(ID(D
), sig_d
);
2301 cell
->setPort(ID(Q
), sig_q
);
2302 cell
->set_src_attribute(src
);
2306 RTLIL::SigSpec
RTLIL::Module::Anyconst(RTLIL::IdString name
, int width
, const std::string
&src
)
2308 RTLIL::SigSpec sig
= addWire(NEW_ID
, width
);
2309 Cell
*cell
= addCell(name
, ID($anyconst
));
2310 cell
->setParam(ID(WIDTH
), width
);
2311 cell
->setPort(ID::Y
, sig
);
2312 cell
->set_src_attribute(src
);
2316 RTLIL::SigSpec
RTLIL::Module::Anyseq(RTLIL::IdString name
, int width
, const std::string
&src
)
2318 RTLIL::SigSpec sig
= addWire(NEW_ID
, width
);
2319 Cell
*cell
= addCell(name
, ID($anyseq
));
2320 cell
->setParam(ID(WIDTH
), width
);
2321 cell
->setPort(ID::Y
, sig
);
2322 cell
->set_src_attribute(src
);
2326 RTLIL::SigSpec
RTLIL::Module::Allconst(RTLIL::IdString name
, int width
, const std::string
&src
)
2328 RTLIL::SigSpec sig
= addWire(NEW_ID
, width
);
2329 Cell
*cell
= addCell(name
, ID($allconst
));
2330 cell
->setParam(ID(WIDTH
), width
);
2331 cell
->setPort(ID::Y
, sig
);
2332 cell
->set_src_attribute(src
);
2336 RTLIL::SigSpec
RTLIL::Module::Allseq(RTLIL::IdString name
, int width
, const std::string
&src
)
2338 RTLIL::SigSpec sig
= addWire(NEW_ID
, width
);
2339 Cell
*cell
= addCell(name
, ID($allseq
));
2340 cell
->setParam(ID(WIDTH
), width
);
2341 cell
->setPort(ID::Y
, sig
);
2342 cell
->set_src_attribute(src
);
2346 RTLIL::SigSpec
RTLIL::Module::Initstate(RTLIL::IdString name
, const std::string
&src
)
2348 RTLIL::SigSpec sig
= addWire(NEW_ID
);
2349 Cell
*cell
= addCell(name
, ID($initstate
));
2350 cell
->setPort(ID::Y
, sig
);
2351 cell
->set_src_attribute(src
);
2357 static unsigned int hashidx_count
= 123456789;
2358 hashidx_count
= mkhash_xorshift(hashidx_count
);
2359 hashidx_
= hashidx_count
;
2366 port_output
= false;
2370 RTLIL::Wire::get_all_wires()->insert(std::pair
<unsigned int, RTLIL::Wire
*>(hashidx_
, this));
2374 RTLIL::Wire::~Wire()
2377 RTLIL::Wire::get_all_wires()->erase(hashidx_
);
2382 static std::map
<unsigned int, RTLIL::Wire
*> all_wires
;
2383 std::map
<unsigned int, RTLIL::Wire
*> *RTLIL::Wire::get_all_wires(void)
2389 RTLIL::Memory::Memory()
2391 static unsigned int hashidx_count
= 123456789;
2392 hashidx_count
= mkhash_xorshift(hashidx_count
);
2393 hashidx_
= hashidx_count
;
2399 RTLIL::Memory::get_all_memorys()->insert(std::pair
<unsigned int, RTLIL::Memory
*>(hashidx_
, this));
2403 RTLIL::Cell::Cell() : module(nullptr)
2405 static unsigned int hashidx_count
= 123456789;
2406 hashidx_count
= mkhash_xorshift(hashidx_count
);
2407 hashidx_
= hashidx_count
;
2409 // log("#memtrace# %p\n", this);
2413 RTLIL::Cell::get_all_cells()->insert(std::pair
<unsigned int, RTLIL::Cell
*>(hashidx_
, this));
2417 RTLIL::Cell::~Cell()
2420 RTLIL::Cell::get_all_cells()->erase(hashidx_
);
2425 static std::map
<unsigned int, RTLIL::Cell
*> all_cells
;
2426 std::map
<unsigned int, RTLIL::Cell
*> *RTLIL::Cell::get_all_cells(void)
2432 bool RTLIL::Cell::hasPort(RTLIL::IdString portname
) const
2434 return connections_
.count(portname
) != 0;
2437 void RTLIL::Cell::unsetPort(RTLIL::IdString portname
)
2439 RTLIL::SigSpec signal
;
2440 auto conn_it
= connections_
.find(portname
);
2442 if (conn_it
!= connections_
.end())
2444 for (auto mon
: module
->monitors
)
2445 mon
->notify_connect(this, conn_it
->first
, conn_it
->second
, signal
);
2448 for (auto mon
: module
->design
->monitors
)
2449 mon
->notify_connect(this, conn_it
->first
, conn_it
->second
, signal
);
2452 log("#X# Unconnect %s.%s.%s\n", log_id(this->module
), log_id(this), log_id(portname
));
2453 log_backtrace("-X- ", yosys_xtrace
-1);
2456 connections_
.erase(conn_it
);
2460 void RTLIL::Cell::setPort(RTLIL::IdString portname
, RTLIL::SigSpec signal
)
2462 auto conn_it
= connections_
.find(portname
);
2464 if (conn_it
== connections_
.end()) {
2465 connections_
[portname
] = RTLIL::SigSpec();
2466 conn_it
= connections_
.find(portname
);
2467 log_assert(conn_it
!= connections_
.end());
2469 if (conn_it
->second
== signal
)
2472 for (auto mon
: module
->monitors
)
2473 mon
->notify_connect(this, conn_it
->first
, conn_it
->second
, signal
);
2476 for (auto mon
: module
->design
->monitors
)
2477 mon
->notify_connect(this, conn_it
->first
, conn_it
->second
, signal
);
2480 log("#X# Connect %s.%s.%s = %s (%d)\n", log_id(this->module
), log_id(this), log_id(portname
), log_signal(signal
), GetSize(signal
));
2481 log_backtrace("-X- ", yosys_xtrace
-1);
2484 conn_it
->second
= signal
;
2487 const RTLIL::SigSpec
&RTLIL::Cell::getPort(RTLIL::IdString portname
) const
2489 return connections_
.at(portname
);
2492 const dict
<RTLIL::IdString
, RTLIL::SigSpec
> &RTLIL::Cell::connections() const
2494 return connections_
;
2497 bool RTLIL::Cell::known() const
2499 if (yosys_celltypes
.cell_known(type
))
2501 if (module
&& module
->design
&& module
->design
->module(type
))
2506 bool RTLIL::Cell::input(RTLIL::IdString portname
) const
2508 if (yosys_celltypes
.cell_known(type
))
2509 return yosys_celltypes
.cell_input(type
, portname
);
2510 if (module
&& module
->design
) {
2511 RTLIL::Module
*m
= module
->design
->module(type
);
2512 RTLIL::Wire
*w
= m
? m
->wire(portname
) : nullptr;
2513 return w
&& w
->port_input
;
2518 bool RTLIL::Cell::output(RTLIL::IdString portname
) const
2520 if (yosys_celltypes
.cell_known(type
))
2521 return yosys_celltypes
.cell_output(type
, portname
);
2522 if (module
&& module
->design
) {
2523 RTLIL::Module
*m
= module
->design
->module(type
);
2524 RTLIL::Wire
*w
= m
? m
->wire(portname
) : nullptr;
2525 return w
&& w
->port_output
;
2530 bool RTLIL::Cell::hasParam(RTLIL::IdString paramname
) const
2532 return parameters
.count(paramname
) != 0;
2535 void RTLIL::Cell::unsetParam(RTLIL::IdString paramname
)
2537 parameters
.erase(paramname
);
2540 void RTLIL::Cell::setParam(RTLIL::IdString paramname
, RTLIL::Const value
)
2542 parameters
[paramname
] = value
;
2545 const RTLIL::Const
&RTLIL::Cell::getParam(RTLIL::IdString paramname
) const
2547 return parameters
.at(paramname
);
2550 void RTLIL::Cell::sort()
2552 connections_
.sort(sort_by_id_str());
2553 parameters
.sort(sort_by_id_str());
2554 attributes
.sort(sort_by_id_str());
2557 void RTLIL::Cell::check()
2560 InternalCellChecker
checker(NULL
, this);
2565 void RTLIL::Cell::fixup_parameters(bool set_a_signed
, bool set_b_signed
)
2567 if (!type
.begins_with("$") || type
.begins_with("$_") || type
.begins_with("$paramod") || type
.begins_with("$fmcombine") ||
2568 type
.begins_with("$verific$") || type
.begins_with("$array:") || type
.begins_with("$extern:"))
2571 if (type
== ID($mux
) || type
== ID($pmux
)) {
2572 parameters
[ID(WIDTH
)] = GetSize(connections_
[ID::Y
]);
2573 if (type
== ID($pmux
))
2574 parameters
[ID(S_WIDTH
)] = GetSize(connections_
[ID(S
)]);
2579 if (type
== ID($lut
) || type
== ID($sop
)) {
2580 parameters
[ID(WIDTH
)] = GetSize(connections_
[ID::A
]);
2584 if (type
== ID($fa
)) {
2585 parameters
[ID(WIDTH
)] = GetSize(connections_
[ID::Y
]);
2589 if (type
== ID($lcu
)) {
2590 parameters
[ID(WIDTH
)] = GetSize(connections_
[ID(CO
)]);
2594 bool signedness_ab
= !type
.in(ID($slice
), ID($concat
), ID($macc
));
2596 if (connections_
.count(ID::A
)) {
2597 if (signedness_ab
) {
2599 parameters
[ID(A_SIGNED
)] = true;
2600 else if (parameters
.count(ID(A_SIGNED
)) == 0)
2601 parameters
[ID(A_SIGNED
)] = false;
2603 parameters
[ID(A_WIDTH
)] = GetSize(connections_
[ID::A
]);
2606 if (connections_
.count(ID::B
)) {
2607 if (signedness_ab
) {
2609 parameters
[ID(B_SIGNED
)] = true;
2610 else if (parameters
.count(ID(B_SIGNED
)) == 0)
2611 parameters
[ID(B_SIGNED
)] = false;
2613 parameters
[ID(B_WIDTH
)] = GetSize(connections_
[ID::B
]);
2616 if (connections_
.count(ID::Y
))
2617 parameters
[ID(Y_WIDTH
)] = GetSize(connections_
[ID::Y
]);
2619 if (connections_
.count(ID(Q
)))
2620 parameters
[ID(WIDTH
)] = GetSize(connections_
[ID(Q
)]);
2625 RTLIL::SigChunk::SigChunk()
2632 RTLIL::SigChunk::SigChunk(const RTLIL::Const
&value
)
2636 width
= GetSize(data
);
2640 RTLIL::SigChunk::SigChunk(RTLIL::Wire
*wire
)
2642 log_assert(wire
!= nullptr);
2644 this->width
= wire
->width
;
2648 RTLIL::SigChunk::SigChunk(RTLIL::Wire
*wire
, int offset
, int width
)
2650 log_assert(wire
!= nullptr);
2652 this->width
= width
;
2653 this->offset
= offset
;
2656 RTLIL::SigChunk::SigChunk(const std::string
&str
)
2659 data
= RTLIL::Const(str
).bits
;
2660 width
= GetSize(data
);
2664 RTLIL::SigChunk::SigChunk(int val
, int width
)
2667 data
= RTLIL::Const(val
, width
).bits
;
2668 this->width
= GetSize(data
);
2672 RTLIL::SigChunk::SigChunk(RTLIL::State bit
, int width
)
2675 data
= RTLIL::Const(bit
, width
).bits
;
2676 this->width
= GetSize(data
);
2680 RTLIL::SigChunk::SigChunk(RTLIL::SigBit bit
)
2685 data
= RTLIL::Const(bit
.data
).bits
;
2687 offset
= bit
.offset
;
2691 RTLIL::SigChunk::SigChunk(const RTLIL::SigChunk
&sigchunk
) : data(sigchunk
.data
)
2693 wire
= sigchunk
.wire
;
2694 data
= sigchunk
.data
;
2695 width
= sigchunk
.width
;
2696 offset
= sigchunk
.offset
;
2699 RTLIL::SigChunk
RTLIL::SigChunk::extract(int offset
, int length
) const
2701 RTLIL::SigChunk ret
;
2704 ret
.offset
= this->offset
+ offset
;
2707 for (int i
= 0; i
< length
; i
++)
2708 ret
.data
.push_back(data
[offset
+i
]);
2714 bool RTLIL::SigChunk::operator <(const RTLIL::SigChunk
&other
) const
2716 if (wire
&& other
.wire
)
2717 if (wire
->name
!= other
.wire
->name
)
2718 return wire
->name
< other
.wire
->name
;
2720 if (wire
!= other
.wire
)
2721 return wire
< other
.wire
;
2723 if (offset
!= other
.offset
)
2724 return offset
< other
.offset
;
2726 if (width
!= other
.width
)
2727 return width
< other
.width
;
2729 return data
< other
.data
;
2732 bool RTLIL::SigChunk::operator ==(const RTLIL::SigChunk
&other
) const
2734 return wire
== other
.wire
&& width
== other
.width
&& offset
== other
.offset
&& data
== other
.data
;
2737 bool RTLIL::SigChunk::operator !=(const RTLIL::SigChunk
&other
) const
2744 RTLIL::SigSpec::SigSpec()
2750 RTLIL::SigSpec::SigSpec(const RTLIL::SigSpec
&other
)
2755 RTLIL::SigSpec::SigSpec(std::initializer_list
<RTLIL::SigSpec
> parts
)
2757 cover("kernel.rtlil.sigspec.init.list");
2762 std::vector
<RTLIL::SigSpec
> parts_vec(parts
.begin(), parts
.end());
2763 for (auto it
= parts_vec
.rbegin(); it
!= parts_vec
.rend(); it
++)
2767 const RTLIL::SigSpec
&RTLIL::SigSpec::operator=(const RTLIL::SigSpec
&other
)
2769 cover("kernel.rtlil.sigspec.assign");
2771 width_
= other
.width_
;
2772 hash_
= other
.hash_
;
2773 chunks_
= other
.chunks_
;
2776 if (!other
.bits_
.empty())
2778 RTLIL::SigChunk
*last
= NULL
;
2779 int last_end_offset
= 0;
2781 for (auto &bit
: other
.bits_
) {
2782 if (last
&& bit
.wire
== last
->wire
) {
2783 if (bit
.wire
== NULL
) {
2784 last
->data
.push_back(bit
.data
);
2787 } else if (last_end_offset
== bit
.offset
) {
2793 chunks_
.push_back(bit
);
2794 last
= &chunks_
.back();
2795 last_end_offset
= bit
.offset
+ 1;
2804 RTLIL::SigSpec::SigSpec(const RTLIL::Const
&value
)
2806 cover("kernel.rtlil.sigspec.init.const");
2808 chunks_
.push_back(RTLIL::SigChunk(value
));
2809 width_
= chunks_
.back().width
;
2814 RTLIL::SigSpec::SigSpec(const RTLIL::SigChunk
&chunk
)
2816 cover("kernel.rtlil.sigspec.init.chunk");
2818 chunks_
.push_back(chunk
);
2819 width_
= chunks_
.back().width
;
2824 RTLIL::SigSpec::SigSpec(RTLIL::Wire
*wire
)
2826 cover("kernel.rtlil.sigspec.init.wire");
2828 chunks_
.push_back(RTLIL::SigChunk(wire
));
2829 width_
= chunks_
.back().width
;
2834 RTLIL::SigSpec::SigSpec(RTLIL::Wire
*wire
, int offset
, int width
)
2836 cover("kernel.rtlil.sigspec.init.wire_part");
2838 chunks_
.push_back(RTLIL::SigChunk(wire
, offset
, width
));
2839 width_
= chunks_
.back().width
;
2844 RTLIL::SigSpec::SigSpec(const std::string
&str
)
2846 cover("kernel.rtlil.sigspec.init.str");
2848 chunks_
.push_back(RTLIL::SigChunk(str
));
2849 width_
= chunks_
.back().width
;
2854 RTLIL::SigSpec::SigSpec(int val
, int width
)
2856 cover("kernel.rtlil.sigspec.init.int");
2858 chunks_
.push_back(RTLIL::SigChunk(val
, width
));
2864 RTLIL::SigSpec::SigSpec(RTLIL::State bit
, int width
)
2866 cover("kernel.rtlil.sigspec.init.state");
2868 chunks_
.push_back(RTLIL::SigChunk(bit
, width
));
2874 RTLIL::SigSpec::SigSpec(RTLIL::SigBit bit
, int width
)
2876 cover("kernel.rtlil.sigspec.init.bit");
2878 if (bit
.wire
== NULL
)
2879 chunks_
.push_back(RTLIL::SigChunk(bit
.data
, width
));
2881 for (int i
= 0; i
< width
; i
++)
2882 chunks_
.push_back(bit
);
2888 RTLIL::SigSpec::SigSpec(std::vector
<RTLIL::SigChunk
> chunks
)
2890 cover("kernel.rtlil.sigspec.init.stdvec_chunks");
2894 for (auto &c
: chunks
)
2899 RTLIL::SigSpec::SigSpec(std::vector
<RTLIL::SigBit
> bits
)
2901 cover("kernel.rtlil.sigspec.init.stdvec_bits");
2905 for (auto &bit
: bits
)
2910 RTLIL::SigSpec::SigSpec(pool
<RTLIL::SigBit
> bits
)
2912 cover("kernel.rtlil.sigspec.init.pool_bits");
2916 for (auto &bit
: bits
)
2921 RTLIL::SigSpec::SigSpec(std::set
<RTLIL::SigBit
> bits
)
2923 cover("kernel.rtlil.sigspec.init.stdset_bits");
2927 for (auto &bit
: bits
)
2932 RTLIL::SigSpec::SigSpec(bool bit
)
2934 cover("kernel.rtlil.sigspec.init.bool");
2942 void RTLIL::SigSpec::pack() const
2944 RTLIL::SigSpec
*that
= (RTLIL::SigSpec
*)this;
2946 if (that
->bits_
.empty())
2949 cover("kernel.rtlil.sigspec.convert.pack");
2950 log_assert(that
->chunks_
.empty());
2952 std::vector
<RTLIL::SigBit
> old_bits
;
2953 old_bits
.swap(that
->bits_
);
2955 RTLIL::SigChunk
*last
= NULL
;
2956 int last_end_offset
= 0;
2958 for (auto &bit
: old_bits
) {
2959 if (last
&& bit
.wire
== last
->wire
) {
2960 if (bit
.wire
== NULL
) {
2961 last
->data
.push_back(bit
.data
);
2964 } else if (last_end_offset
== bit
.offset
) {
2970 that
->chunks_
.push_back(bit
);
2971 last
= &that
->chunks_
.back();
2972 last_end_offset
= bit
.offset
+ 1;
2978 void RTLIL::SigSpec::unpack() const
2980 RTLIL::SigSpec
*that
= (RTLIL::SigSpec
*)this;
2982 if (that
->chunks_
.empty())
2985 cover("kernel.rtlil.sigspec.convert.unpack");
2986 log_assert(that
->bits_
.empty());
2988 that
->bits_
.reserve(that
->width_
);
2989 for (auto &c
: that
->chunks_
)
2990 for (int i
= 0; i
< c
.width
; i
++)
2991 that
->bits_
.push_back(RTLIL::SigBit(c
, i
));
2993 that
->chunks_
.clear();
2997 void RTLIL::SigSpec::updhash() const
2999 RTLIL::SigSpec
*that
= (RTLIL::SigSpec
*)this;
3001 if (that
->hash_
!= 0)
3004 cover("kernel.rtlil.sigspec.hash");
3007 that
->hash_
= mkhash_init
;
3008 for (auto &c
: that
->chunks_
)
3009 if (c
.wire
== NULL
) {
3010 for (auto &v
: c
.data
)
3011 that
->hash_
= mkhash(that
->hash_
, v
);
3013 that
->hash_
= mkhash(that
->hash_
, c
.wire
->name
.index_
);
3014 that
->hash_
= mkhash(that
->hash_
, c
.offset
);
3015 that
->hash_
= mkhash(that
->hash_
, c
.width
);
3018 if (that
->hash_
== 0)
3022 void RTLIL::SigSpec::sort()
3025 cover("kernel.rtlil.sigspec.sort");
3026 std::sort(bits_
.begin(), bits_
.end());
3029 void RTLIL::SigSpec::sort_and_unify()
3032 cover("kernel.rtlil.sigspec.sort_and_unify");
3034 // A copy of the bits vector is used to prevent duplicating the logic from
3035 // SigSpec::SigSpec(std::vector<SigBit>). This incurrs an extra copy but
3036 // that isn't showing up as significant in profiles.
3037 std::vector
<SigBit
> unique_bits
= bits_
;
3038 std::sort(unique_bits
.begin(), unique_bits
.end());
3039 auto last
= std::unique(unique_bits
.begin(), unique_bits
.end());
3040 unique_bits
.erase(last
, unique_bits
.end());
3042 *this = unique_bits
;
3045 void RTLIL::SigSpec::replace(const RTLIL::SigSpec
&pattern
, const RTLIL::SigSpec
&with
)
3047 replace(pattern
, with
, this);
3050 void RTLIL::SigSpec::replace(const RTLIL::SigSpec
&pattern
, const RTLIL::SigSpec
&with
, RTLIL::SigSpec
*other
) const
3052 log_assert(other
!= NULL
);
3053 log_assert(width_
== other
->width_
);
3054 log_assert(pattern
.width_
== with
.width_
);
3061 for (int i
= 0; i
< GetSize(pattern
.bits_
); i
++) {
3062 if (pattern
.bits_
[i
].wire
!= NULL
) {
3063 for (int j
= 0; j
< GetSize(bits_
); j
++) {
3064 if (bits_
[j
] == pattern
.bits_
[i
]) {
3065 other
->bits_
[j
] = with
.bits_
[i
];
3074 void RTLIL::SigSpec::replace(const dict
<RTLIL::SigBit
, RTLIL::SigBit
> &rules
)
3076 replace(rules
, this);
3079 void RTLIL::SigSpec::replace(const dict
<RTLIL::SigBit
, RTLIL::SigBit
> &rules
, RTLIL::SigSpec
*other
) const
3081 cover("kernel.rtlil.sigspec.replace_dict");
3083 log_assert(other
!= NULL
);
3084 log_assert(width_
== other
->width_
);
3086 if (rules
.empty()) return;
3090 for (int i
= 0; i
< GetSize(bits_
); i
++) {
3091 auto it
= rules
.find(bits_
[i
]);
3092 if (it
!= rules
.end())
3093 other
->bits_
[i
] = it
->second
;
3099 void RTLIL::SigSpec::replace(const std::map
<RTLIL::SigBit
, RTLIL::SigBit
> &rules
)
3101 replace(rules
, this);
3104 void RTLIL::SigSpec::replace(const std::map
<RTLIL::SigBit
, RTLIL::SigBit
> &rules
, RTLIL::SigSpec
*other
) const
3106 cover("kernel.rtlil.sigspec.replace_map");
3108 log_assert(other
!= NULL
);
3109 log_assert(width_
== other
->width_
);
3111 if (rules
.empty()) return;
3115 for (int i
= 0; i
< GetSize(bits_
); i
++) {
3116 auto it
= rules
.find(bits_
[i
]);
3117 if (it
!= rules
.end())
3118 other
->bits_
[i
] = it
->second
;
3124 void RTLIL::SigSpec::remove(const RTLIL::SigSpec
&pattern
)
3126 remove2(pattern
, NULL
);
3129 void RTLIL::SigSpec::remove(const RTLIL::SigSpec
&pattern
, RTLIL::SigSpec
*other
) const
3131 RTLIL::SigSpec tmp
= *this;
3132 tmp
.remove2(pattern
, other
);
3135 void RTLIL::SigSpec::remove2(const RTLIL::SigSpec
&pattern
, RTLIL::SigSpec
*other
)
3138 cover("kernel.rtlil.sigspec.remove_other");
3140 cover("kernel.rtlil.sigspec.remove");
3143 if (other
!= NULL
) {
3144 log_assert(width_
== other
->width_
);
3148 for (int i
= GetSize(bits_
) - 1; i
>= 0; i
--)
3150 if (bits_
[i
].wire
== NULL
) continue;
3152 for (auto &pattern_chunk
: pattern
.chunks())
3153 if (bits_
[i
].wire
== pattern_chunk
.wire
&&
3154 bits_
[i
].offset
>= pattern_chunk
.offset
&&
3155 bits_
[i
].offset
< pattern_chunk
.offset
+ pattern_chunk
.width
) {
3156 bits_
.erase(bits_
.begin() + i
);
3158 if (other
!= NULL
) {
3159 other
->bits_
.erase(other
->bits_
.begin() + i
);
3169 void RTLIL::SigSpec::remove(const pool
<RTLIL::SigBit
> &pattern
)
3171 remove2(pattern
, NULL
);
3174 void RTLIL::SigSpec::remove(const pool
<RTLIL::SigBit
> &pattern
, RTLIL::SigSpec
*other
) const
3176 RTLIL::SigSpec tmp
= *this;
3177 tmp
.remove2(pattern
, other
);
3180 void RTLIL::SigSpec::remove2(const pool
<RTLIL::SigBit
> &pattern
, RTLIL::SigSpec
*other
)
3183 cover("kernel.rtlil.sigspec.remove_other");
3185 cover("kernel.rtlil.sigspec.remove");
3189 if (other
!= NULL
) {
3190 log_assert(width_
== other
->width_
);
3194 for (int i
= GetSize(bits_
) - 1; i
>= 0; i
--) {
3195 if (bits_
[i
].wire
!= NULL
&& pattern
.count(bits_
[i
])) {
3196 bits_
.erase(bits_
.begin() + i
);
3198 if (other
!= NULL
) {
3199 other
->bits_
.erase(other
->bits_
.begin() + i
);
3208 void RTLIL::SigSpec::remove2(const std::set
<RTLIL::SigBit
> &pattern
, RTLIL::SigSpec
*other
)
3211 cover("kernel.rtlil.sigspec.remove_other");
3213 cover("kernel.rtlil.sigspec.remove");
3217 if (other
!= NULL
) {
3218 log_assert(width_
== other
->width_
);
3222 for (int i
= GetSize(bits_
) - 1; i
>= 0; i
--) {
3223 if (bits_
[i
].wire
!= NULL
&& pattern
.count(bits_
[i
])) {
3224 bits_
.erase(bits_
.begin() + i
);
3226 if (other
!= NULL
) {
3227 other
->bits_
.erase(other
->bits_
.begin() + i
);
3236 RTLIL::SigSpec
RTLIL::SigSpec::extract(const RTLIL::SigSpec
&pattern
, const RTLIL::SigSpec
*other
) const
3239 cover("kernel.rtlil.sigspec.extract_other");
3241 cover("kernel.rtlil.sigspec.extract");
3243 log_assert(other
== NULL
|| width_
== other
->width_
);
3246 std::vector
<RTLIL::SigBit
> bits_match
= to_sigbit_vector();
3248 for (auto& pattern_chunk
: pattern
.chunks()) {
3250 std::vector
<RTLIL::SigBit
> bits_other
= other
->to_sigbit_vector();
3251 for (int i
= 0; i
< width_
; i
++)
3252 if (bits_match
[i
].wire
&&
3253 bits_match
[i
].wire
== pattern_chunk
.wire
&&
3254 bits_match
[i
].offset
>= pattern_chunk
.offset
&&
3255 bits_match
[i
].offset
< pattern_chunk
.offset
+ pattern_chunk
.width
)
3256 ret
.append_bit(bits_other
[i
]);
3258 for (int i
= 0; i
< width_
; i
++)
3259 if (bits_match
[i
].wire
&&
3260 bits_match
[i
].wire
== pattern_chunk
.wire
&&
3261 bits_match
[i
].offset
>= pattern_chunk
.offset
&&
3262 bits_match
[i
].offset
< pattern_chunk
.offset
+ pattern_chunk
.width
)
3263 ret
.append_bit(bits_match
[i
]);
3271 RTLIL::SigSpec
RTLIL::SigSpec::extract(const pool
<RTLIL::SigBit
> &pattern
, const RTLIL::SigSpec
*other
) const
3274 cover("kernel.rtlil.sigspec.extract_other");
3276 cover("kernel.rtlil.sigspec.extract");
3278 log_assert(other
== NULL
|| width_
== other
->width_
);
3280 std::vector
<RTLIL::SigBit
> bits_match
= to_sigbit_vector();
3284 std::vector
<RTLIL::SigBit
> bits_other
= other
->to_sigbit_vector();
3285 for (int i
= 0; i
< width_
; i
++)
3286 if (bits_match
[i
].wire
&& pattern
.count(bits_match
[i
]))
3287 ret
.append_bit(bits_other
[i
]);
3289 for (int i
= 0; i
< width_
; i
++)
3290 if (bits_match
[i
].wire
&& pattern
.count(bits_match
[i
]))
3291 ret
.append_bit(bits_match
[i
]);
3298 void RTLIL::SigSpec::replace(int offset
, const RTLIL::SigSpec
&with
)
3300 cover("kernel.rtlil.sigspec.replace_pos");
3305 log_assert(offset
>= 0);
3306 log_assert(with
.width_
>= 0);
3307 log_assert(offset
+with
.width_
<= width_
);
3309 for (int i
= 0; i
< with
.width_
; i
++)
3310 bits_
.at(offset
+ i
) = with
.bits_
.at(i
);
3315 void RTLIL::SigSpec::remove_const()
3319 cover("kernel.rtlil.sigspec.remove_const.packed");
3321 std::vector
<RTLIL::SigChunk
> new_chunks
;
3322 new_chunks
.reserve(GetSize(chunks_
));
3325 for (auto &chunk
: chunks_
)
3326 if (chunk
.wire
!= NULL
) {
3327 new_chunks
.push_back(chunk
);
3328 width_
+= chunk
.width
;
3331 chunks_
.swap(new_chunks
);
3335 cover("kernel.rtlil.sigspec.remove_const.unpacked");
3337 std::vector
<RTLIL::SigBit
> new_bits
;
3338 new_bits
.reserve(width_
);
3340 for (auto &bit
: bits_
)
3341 if (bit
.wire
!= NULL
)
3342 new_bits
.push_back(bit
);
3344 bits_
.swap(new_bits
);
3345 width_
= bits_
.size();
3351 void RTLIL::SigSpec::remove(int offset
, int length
)
3353 cover("kernel.rtlil.sigspec.remove_pos");
3357 log_assert(offset
>= 0);
3358 log_assert(length
>= 0);
3359 log_assert(offset
+ length
<= width_
);
3361 bits_
.erase(bits_
.begin() + offset
, bits_
.begin() + offset
+ length
);
3362 width_
= bits_
.size();
3367 RTLIL::SigSpec
RTLIL::SigSpec::extract(int offset
, int length
) const
3370 cover("kernel.rtlil.sigspec.extract_pos");
3371 return std::vector
<RTLIL::SigBit
>(bits_
.begin() + offset
, bits_
.begin() + offset
+ length
);
3374 void RTLIL::SigSpec::append(const RTLIL::SigSpec
&signal
)
3376 if (signal
.width_
== 0)
3384 cover("kernel.rtlil.sigspec.append");
3386 if (packed() != signal
.packed()) {
3392 for (auto &other_c
: signal
.chunks_
)
3394 auto &my_last_c
= chunks_
.back();
3395 if (my_last_c
.wire
== NULL
&& other_c
.wire
== NULL
) {
3396 auto &this_data
= my_last_c
.data
;
3397 auto &other_data
= other_c
.data
;
3398 this_data
.insert(this_data
.end(), other_data
.begin(), other_data
.end());
3399 my_last_c
.width
+= other_c
.width
;
3401 if (my_last_c
.wire
== other_c
.wire
&& my_last_c
.offset
+ my_last_c
.width
== other_c
.offset
) {
3402 my_last_c
.width
+= other_c
.width
;
3404 chunks_
.push_back(other_c
);
3407 bits_
.insert(bits_
.end(), signal
.bits_
.begin(), signal
.bits_
.end());
3409 width_
+= signal
.width_
;
3413 void RTLIL::SigSpec::append_bit(const RTLIL::SigBit
&bit
)
3417 cover("kernel.rtlil.sigspec.append_bit.packed");
3419 if (chunks_
.size() == 0)
3420 chunks_
.push_back(bit
);
3422 if (bit
.wire
== NULL
)
3423 if (chunks_
.back().wire
== NULL
) {
3424 chunks_
.back().data
.push_back(bit
.data
);
3425 chunks_
.back().width
++;
3427 chunks_
.push_back(bit
);
3429 if (chunks_
.back().wire
== bit
.wire
&& chunks_
.back().offset
+ chunks_
.back().width
== bit
.offset
)
3430 chunks_
.back().width
++;
3432 chunks_
.push_back(bit
);
3436 cover("kernel.rtlil.sigspec.append_bit.unpacked");
3437 bits_
.push_back(bit
);
3444 void RTLIL::SigSpec::extend_u0(int width
, bool is_signed
)
3446 cover("kernel.rtlil.sigspec.extend_u0");
3451 remove(width
, width_
- width
);
3453 if (width_
< width
) {
3454 RTLIL::SigBit padding
= width_
> 0 ? (*this)[width_
- 1] : RTLIL::State::Sx
;
3456 padding
= RTLIL::State::S0
;
3457 while (width_
< width
)
3463 RTLIL::SigSpec
RTLIL::SigSpec::repeat(int num
) const
3465 cover("kernel.rtlil.sigspec.repeat");
3468 for (int i
= 0; i
< num
; i
++)
3474 void RTLIL::SigSpec::check() const
3478 cover("kernel.rtlil.sigspec.check.skip");
3482 cover("kernel.rtlil.sigspec.check.packed");
3485 for (size_t i
= 0; i
< chunks_
.size(); i
++) {
3486 const RTLIL::SigChunk chunk
= chunks_
[i
];
3487 if (chunk
.wire
== NULL
) {
3489 log_assert(chunks_
[i
-1].wire
!= NULL
);
3490 log_assert(chunk
.offset
== 0);
3491 log_assert(chunk
.data
.size() == (size_t)chunk
.width
);
3493 if (i
> 0 && chunks_
[i
-1].wire
== chunk
.wire
)
3494 log_assert(chunk
.offset
!= chunks_
[i
-1].offset
+ chunks_
[i
-1].width
);
3495 log_assert(chunk
.offset
>= 0);
3496 log_assert(chunk
.width
>= 0);
3497 log_assert(chunk
.offset
+ chunk
.width
<= chunk
.wire
->width
);
3498 log_assert(chunk
.data
.size() == 0);
3502 log_assert(w
== width_
);
3503 log_assert(bits_
.empty());
3507 cover("kernel.rtlil.sigspec.check.unpacked");
3509 log_assert(width_
== GetSize(bits_
));
3510 log_assert(chunks_
.empty());
3515 bool RTLIL::SigSpec::operator <(const RTLIL::SigSpec
&other
) const
3517 cover("kernel.rtlil.sigspec.comp_lt");
3522 if (width_
!= other
.width_
)
3523 return width_
< other
.width_
;
3528 if (chunks_
.size() != other
.chunks_
.size())
3529 return chunks_
.size() < other
.chunks_
.size();
3534 if (hash_
!= other
.hash_
)
3535 return hash_
< other
.hash_
;
3537 for (size_t i
= 0; i
< chunks_
.size(); i
++)
3538 if (chunks_
[i
] != other
.chunks_
[i
]) {
3539 cover("kernel.rtlil.sigspec.comp_lt.hash_collision");
3540 return chunks_
[i
] < other
.chunks_
[i
];
3543 cover("kernel.rtlil.sigspec.comp_lt.equal");
3547 bool RTLIL::SigSpec::operator ==(const RTLIL::SigSpec
&other
) const
3549 cover("kernel.rtlil.sigspec.comp_eq");
3554 if (width_
!= other
.width_
)
3557 // Without this, SigSpec() == SigSpec(State::S0, 0) will fail
3558 // since the RHS will contain one SigChunk of width 0 causing
3559 // the size check below to fail
3566 if (chunks_
.size() != other
.chunks_
.size())
3572 if (hash_
!= other
.hash_
)
3575 for (size_t i
= 0; i
< chunks_
.size(); i
++)
3576 if (chunks_
[i
] != other
.chunks_
[i
]) {
3577 cover("kernel.rtlil.sigspec.comp_eq.hash_collision");
3581 cover("kernel.rtlil.sigspec.comp_eq.equal");
3585 bool RTLIL::SigSpec::is_wire() const
3587 cover("kernel.rtlil.sigspec.is_wire");
3590 return GetSize(chunks_
) == 1 && chunks_
[0].wire
&& chunks_
[0].wire
->width
== width_
;
3593 bool RTLIL::SigSpec::is_chunk() const
3595 cover("kernel.rtlil.sigspec.is_chunk");
3598 return GetSize(chunks_
) == 1;
3601 bool RTLIL::SigSpec::is_fully_const() const
3603 cover("kernel.rtlil.sigspec.is_fully_const");
3606 for (auto it
= chunks_
.begin(); it
!= chunks_
.end(); it
++)
3607 if (it
->width
> 0 && it
->wire
!= NULL
)
3612 bool RTLIL::SigSpec::is_fully_zero() const
3614 cover("kernel.rtlil.sigspec.is_fully_zero");
3617 for (auto it
= chunks_
.begin(); it
!= chunks_
.end(); it
++) {
3618 if (it
->width
> 0 && it
->wire
!= NULL
)
3620 for (size_t i
= 0; i
< it
->data
.size(); i
++)
3621 if (it
->data
[i
] != RTLIL::State::S0
)
3627 bool RTLIL::SigSpec::is_fully_ones() const
3629 cover("kernel.rtlil.sigspec.is_fully_ones");
3632 for (auto it
= chunks_
.begin(); it
!= chunks_
.end(); it
++) {
3633 if (it
->width
> 0 && it
->wire
!= NULL
)
3635 for (size_t i
= 0; i
< it
->data
.size(); i
++)
3636 if (it
->data
[i
] != RTLIL::State::S1
)
3642 bool RTLIL::SigSpec::is_fully_def() const
3644 cover("kernel.rtlil.sigspec.is_fully_def");
3647 for (auto it
= chunks_
.begin(); it
!= chunks_
.end(); it
++) {
3648 if (it
->width
> 0 && it
->wire
!= NULL
)
3650 for (size_t i
= 0; i
< it
->data
.size(); i
++)
3651 if (it
->data
[i
] != RTLIL::State::S0
&& it
->data
[i
] != RTLIL::State::S1
)
3657 bool RTLIL::SigSpec::is_fully_undef() const
3659 cover("kernel.rtlil.sigspec.is_fully_undef");
3662 for (auto it
= chunks_
.begin(); it
!= chunks_
.end(); it
++) {
3663 if (it
->width
> 0 && it
->wire
!= NULL
)
3665 for (size_t i
= 0; i
< it
->data
.size(); i
++)
3666 if (it
->data
[i
] != RTLIL::State::Sx
&& it
->data
[i
] != RTLIL::State::Sz
)
3672 bool RTLIL::SigSpec::has_const() const
3674 cover("kernel.rtlil.sigspec.has_const");
3677 for (auto it
= chunks_
.begin(); it
!= chunks_
.end(); it
++)
3678 if (it
->width
> 0 && it
->wire
== NULL
)
3683 bool RTLIL::SigSpec::has_marked_bits() const
3685 cover("kernel.rtlil.sigspec.has_marked_bits");
3688 for (auto it
= chunks_
.begin(); it
!= chunks_
.end(); it
++)
3689 if (it
->width
> 0 && it
->wire
== NULL
) {
3690 for (size_t i
= 0; i
< it
->data
.size(); i
++)
3691 if (it
->data
[i
] == RTLIL::State::Sm
)
3697 bool RTLIL::SigSpec::as_bool() const
3699 cover("kernel.rtlil.sigspec.as_bool");
3702 log_assert(is_fully_const() && GetSize(chunks_
) <= 1);
3704 return RTLIL::Const(chunks_
[0].data
).as_bool();
3708 int RTLIL::SigSpec::as_int(bool is_signed
) const
3710 cover("kernel.rtlil.sigspec.as_int");
3713 log_assert(is_fully_const() && GetSize(chunks_
) <= 1);
3715 return RTLIL::Const(chunks_
[0].data
).as_int(is_signed
);
3719 std::string
RTLIL::SigSpec::as_string() const
3721 cover("kernel.rtlil.sigspec.as_string");
3725 for (size_t i
= chunks_
.size(); i
> 0; i
--) {
3726 const RTLIL::SigChunk
&chunk
= chunks_
[i
-1];
3727 if (chunk
.wire
!= NULL
)
3728 for (int j
= 0; j
< chunk
.width
; j
++)
3731 str
+= RTLIL::Const(chunk
.data
).as_string();
3736 RTLIL::Const
RTLIL::SigSpec::as_const() const
3738 cover("kernel.rtlil.sigspec.as_const");
3741 log_assert(is_fully_const() && GetSize(chunks_
) <= 1);
3743 return chunks_
[0].data
;
3744 return RTLIL::Const();
3747 RTLIL::Wire
*RTLIL::SigSpec::as_wire() const
3749 cover("kernel.rtlil.sigspec.as_wire");
3752 log_assert(is_wire());
3753 return chunks_
[0].wire
;
3756 RTLIL::SigChunk
RTLIL::SigSpec::as_chunk() const
3758 cover("kernel.rtlil.sigspec.as_chunk");
3761 log_assert(is_chunk());
3765 RTLIL::SigBit
RTLIL::SigSpec::as_bit() const
3767 cover("kernel.rtlil.sigspec.as_bit");
3769 log_assert(width_
== 1);
3771 return RTLIL::SigBit(*chunks_
.begin());
3776 bool RTLIL::SigSpec::match(std::string pattern
) const
3778 cover("kernel.rtlil.sigspec.match");
3781 std::string str
= as_string();
3782 log_assert(pattern
.size() == str
.size());
3784 for (size_t i
= 0; i
< pattern
.size(); i
++) {
3785 if (pattern
[i
] == ' ')
3787 if (pattern
[i
] == '*') {
3788 if (str
[i
] != 'z' && str
[i
] != 'x')
3792 if (pattern
[i
] != str
[i
])
3799 std::set
<RTLIL::SigBit
> RTLIL::SigSpec::to_sigbit_set() const
3801 cover("kernel.rtlil.sigspec.to_sigbit_set");
3804 std::set
<RTLIL::SigBit
> sigbits
;
3805 for (auto &c
: chunks_
)
3806 for (int i
= 0; i
< c
.width
; i
++)
3807 sigbits
.insert(RTLIL::SigBit(c
, i
));
3811 pool
<RTLIL::SigBit
> RTLIL::SigSpec::to_sigbit_pool() const
3813 cover("kernel.rtlil.sigspec.to_sigbit_pool");
3816 pool
<RTLIL::SigBit
> sigbits
;
3817 for (auto &c
: chunks_
)
3818 for (int i
= 0; i
< c
.width
; i
++)
3819 sigbits
.insert(RTLIL::SigBit(c
, i
));
3823 std::vector
<RTLIL::SigBit
> RTLIL::SigSpec::to_sigbit_vector() const
3825 cover("kernel.rtlil.sigspec.to_sigbit_vector");
3831 std::map
<RTLIL::SigBit
, RTLIL::SigBit
> RTLIL::SigSpec::to_sigbit_map(const RTLIL::SigSpec
&other
) const
3833 cover("kernel.rtlil.sigspec.to_sigbit_map");
3838 log_assert(width_
== other
.width_
);
3840 std::map
<RTLIL::SigBit
, RTLIL::SigBit
> new_map
;
3841 for (int i
= 0; i
< width_
; i
++)
3842 new_map
[bits_
[i
]] = other
.bits_
[i
];
3847 dict
<RTLIL::SigBit
, RTLIL::SigBit
> RTLIL::SigSpec::to_sigbit_dict(const RTLIL::SigSpec
&other
) const
3849 cover("kernel.rtlil.sigspec.to_sigbit_dict");
3854 log_assert(width_
== other
.width_
);
3856 dict
<RTLIL::SigBit
, RTLIL::SigBit
> new_map
;
3857 for (int i
= 0; i
< width_
; i
++)
3858 new_map
[bits_
[i
]] = other
.bits_
[i
];
3863 static void sigspec_parse_split(std::vector
<std::string
> &tokens
, const std::string
&text
, char sep
)
3865 size_t start
= 0, end
= 0;
3866 while ((end
= text
.find(sep
, start
)) != std::string::npos
) {
3867 tokens
.push_back(text
.substr(start
, end
- start
));
3870 tokens
.push_back(text
.substr(start
));
3873 static int sigspec_parse_get_dummy_line_num()
3878 bool RTLIL::SigSpec::parse(RTLIL::SigSpec
&sig
, RTLIL::Module
*module
, std::string str
)
3880 cover("kernel.rtlil.sigspec.parse");
3882 AST::current_filename
= "input";
3883 AST::use_internal_line_num();
3884 AST::set_line_num(0);
3886 std::vector
<std::string
> tokens
;
3887 sigspec_parse_split(tokens
, str
, ',');
3889 sig
= RTLIL::SigSpec();
3890 for (int tokidx
= int(tokens
.size())-1; tokidx
>= 0; tokidx
--)
3892 std::string netname
= tokens
[tokidx
];
3893 std::string indices
;
3895 if (netname
.size() == 0)
3898 if (('0' <= netname
[0] && netname
[0] <= '9') || netname
[0] == '\'') {
3899 cover("kernel.rtlil.sigspec.parse.const");
3900 AST::get_line_num
= sigspec_parse_get_dummy_line_num
;
3901 AST::AstNode
*ast
= VERILOG_FRONTEND::const2ast(netname
);
3904 sig
.append(RTLIL::Const(ast
->bits
));
3912 cover("kernel.rtlil.sigspec.parse.net");
3914 if (netname
[0] != '$' && netname
[0] != '\\')
3915 netname
= "\\" + netname
;
3917 if (module
->wires_
.count(netname
) == 0) {
3918 size_t indices_pos
= netname
.size()-1;
3919 if (indices_pos
> 2 && netname
[indices_pos
] == ']')
3922 while (indices_pos
> 0 && ('0' <= netname
[indices_pos
] && netname
[indices_pos
] <= '9')) indices_pos
--;
3923 if (indices_pos
> 0 && netname
[indices_pos
] == ':') {
3925 while (indices_pos
> 0 && ('0' <= netname
[indices_pos
] && netname
[indices_pos
] <= '9')) indices_pos
--;
3927 if (indices_pos
> 0 && netname
[indices_pos
] == '[') {
3928 indices
= netname
.substr(indices_pos
);
3929 netname
= netname
.substr(0, indices_pos
);
3934 if (module
->wires_
.count(netname
) == 0)
3937 RTLIL::Wire
*wire
= module
->wires_
.at(netname
);
3938 if (!indices
.empty()) {
3939 std::vector
<std::string
> index_tokens
;
3940 sigspec_parse_split(index_tokens
, indices
.substr(1, indices
.size()-2), ':');
3941 if (index_tokens
.size() == 1) {
3942 cover("kernel.rtlil.sigspec.parse.bit_sel");
3943 int a
= atoi(index_tokens
.at(0).c_str());
3944 if (a
< 0 || a
>= wire
->width
)
3946 sig
.append(RTLIL::SigSpec(wire
, a
));
3948 cover("kernel.rtlil.sigspec.parse.part_sel");
3949 int a
= atoi(index_tokens
.at(0).c_str());
3950 int b
= atoi(index_tokens
.at(1).c_str());
3955 if (a
< 0 || a
>= wire
->width
)
3957 if (b
< 0 || b
>= wire
->width
)
3959 sig
.append(RTLIL::SigSpec(wire
, a
, b
-a
+1));
3968 bool RTLIL::SigSpec::parse_sel(RTLIL::SigSpec
&sig
, RTLIL::Design
*design
, RTLIL::Module
*module
, std::string str
)
3970 if (str
.empty() || str
[0] != '@')
3971 return parse(sig
, module
, str
);
3973 cover("kernel.rtlil.sigspec.parse.sel");
3975 str
= RTLIL::escape_id(str
.substr(1));
3976 if (design
->selection_vars
.count(str
) == 0)
3979 sig
= RTLIL::SigSpec();
3980 RTLIL::Selection
&sel
= design
->selection_vars
.at(str
);
3981 for (auto &it
: module
->wires_
)
3982 if (sel
.selected_member(module
->name
, it
.first
))
3983 sig
.append(it
.second
);
3988 bool RTLIL::SigSpec::parse_rhs(const RTLIL::SigSpec
&lhs
, RTLIL::SigSpec
&sig
, RTLIL::Module
*module
, std::string str
)
3991 cover("kernel.rtlil.sigspec.parse.rhs_zeros");
3992 sig
= RTLIL::SigSpec(RTLIL::State::S0
, lhs
.width_
);
3997 cover("kernel.rtlil.sigspec.parse.rhs_ones");
3998 sig
= RTLIL::SigSpec(RTLIL::State::S1
, lhs
.width_
);
4002 if (lhs
.chunks_
.size() == 1) {
4003 char *p
= (char*)str
.c_str(), *endptr
;
4004 long int val
= strtol(p
, &endptr
, 10);
4005 if (endptr
&& endptr
!= p
&& *endptr
== 0) {
4006 sig
= RTLIL::SigSpec(val
, lhs
.width_
);
4007 cover("kernel.rtlil.sigspec.parse.rhs_dec");
4012 return parse(sig
, module
, str
);
4015 RTLIL::CaseRule::~CaseRule()
4017 for (auto it
= switches
.begin(); it
!= switches
.end(); it
++)
4021 bool RTLIL::CaseRule::empty() const
4023 return actions
.empty() && switches
.empty();
4026 RTLIL::CaseRule
*RTLIL::CaseRule::clone() const
4028 RTLIL::CaseRule
*new_caserule
= new RTLIL::CaseRule
;
4029 new_caserule
->compare
= compare
;
4030 new_caserule
->actions
= actions
;
4031 for (auto &it
: switches
)
4032 new_caserule
->switches
.push_back(it
->clone());
4033 return new_caserule
;
4036 RTLIL::SwitchRule::~SwitchRule()
4038 for (auto it
= cases
.begin(); it
!= cases
.end(); it
++)
4042 bool RTLIL::SwitchRule::empty() const
4044 return cases
.empty();
4047 RTLIL::SwitchRule
*RTLIL::SwitchRule::clone() const
4049 RTLIL::SwitchRule
*new_switchrule
= new RTLIL::SwitchRule
;
4050 new_switchrule
->signal
= signal
;
4051 new_switchrule
->attributes
= attributes
;
4052 for (auto &it
: cases
)
4053 new_switchrule
->cases
.push_back(it
->clone());
4054 return new_switchrule
;
4058 RTLIL::SyncRule
*RTLIL::SyncRule::clone() const
4060 RTLIL::SyncRule
*new_syncrule
= new RTLIL::SyncRule
;
4061 new_syncrule
->type
= type
;
4062 new_syncrule
->signal
= signal
;
4063 new_syncrule
->actions
= actions
;
4064 return new_syncrule
;
4067 RTLIL::Process::~Process()
4069 for (auto it
= syncs
.begin(); it
!= syncs
.end(); it
++)
4073 RTLIL::Process
*RTLIL::Process::clone() const
4075 RTLIL::Process
*new_proc
= new RTLIL::Process
;
4077 new_proc
->name
= name
;
4078 new_proc
->attributes
= attributes
;
4080 RTLIL::CaseRule
*rc_ptr
= root_case
.clone();
4081 new_proc
->root_case
= *rc_ptr
;
4082 rc_ptr
->switches
.clear();
4085 for (auto &it
: syncs
)
4086 new_proc
->syncs
.push_back(it
->clone());
4092 RTLIL::Memory::~Memory()
4094 RTLIL::Memory::get_all_memorys()->erase(hashidx_
);
4096 static std::map
<unsigned int, RTLIL::Memory
*> all_memorys
;
4097 std::map
<unsigned int, RTLIL::Memory
*> *RTLIL::Memory::get_all_memorys(void)
4099 return &all_memorys
;