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c497ee102fa526ea1ad575ad21bb94bea26f201a
[yosys.git] / kernel / rtlil.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 #include "kernel/yosys.h"
21 #include "kernel/macc.h"
22 #include "kernel/celltypes.h"
23 #include "frontends/verilog/verilog_frontend.h"
24 #include "backends/ilang/ilang_backend.h"
25
26 #include <string.h>
27 #include <algorithm>
28
29 YOSYS_NAMESPACE_BEGIN
30
31 RTLIL::IdString::destruct_guard_t RTLIL::IdString::destruct_guard;
32 std::vector<int> RTLIL::IdString::global_refcount_storage_;
33 std::vector<char*> RTLIL::IdString::global_id_storage_;
34 dict<char*, int, hash_cstr_ops> RTLIL::IdString::global_id_index_;
35 std::vector<int> RTLIL::IdString::global_free_idx_list_;
36
37 RTLIL::Const::Const()
38 {
39 flags = RTLIL::CONST_FLAG_NONE;
40 }
41
42 RTLIL::Const::Const(std::string str)
43 {
44 flags = RTLIL::CONST_FLAG_STRING;
45 for (int i = str.size()-1; i >= 0; i--) {
46 unsigned char ch = str[i];
47 for (int j = 0; j < 8; j++) {
48 bits.push_back((ch & 1) != 0 ? RTLIL::S1 : RTLIL::S0);
49 ch = ch >> 1;
50 }
51 }
52 }
53
54 RTLIL::Const::Const(int val, int width)
55 {
56 flags = RTLIL::CONST_FLAG_NONE;
57 for (int i = 0; i < width; i++) {
58 bits.push_back((val & 1) != 0 ? RTLIL::S1 : RTLIL::S0);
59 val = val >> 1;
60 }
61 }
62
63 RTLIL::Const::Const(RTLIL::State bit, int width)
64 {
65 flags = RTLIL::CONST_FLAG_NONE;
66 for (int i = 0; i < width; i++)
67 bits.push_back(bit);
68 }
69
70 RTLIL::Const::Const(const std::vector<bool> &bits)
71 {
72 flags = RTLIL::CONST_FLAG_NONE;
73 for (auto b : bits)
74 this->bits.push_back(b ? RTLIL::S1 : RTLIL::S0);
75 }
76
77 bool RTLIL::Const::operator <(const RTLIL::Const &other) const
78 {
79 if (bits.size() != other.bits.size())
80 return bits.size() < other.bits.size();
81 for (size_t i = 0; i < bits.size(); i++)
82 if (bits[i] != other.bits[i])
83 return bits[i] < other.bits[i];
84 return false;
85 }
86
87 bool RTLIL::Const::operator ==(const RTLIL::Const &other) const
88 {
89 return bits == other.bits;
90 }
91
92 bool RTLIL::Const::operator !=(const RTLIL::Const &other) const
93 {
94 return bits != other.bits;
95 }
96
97 bool RTLIL::Const::as_bool() const
98 {
99 for (size_t i = 0; i < bits.size(); i++)
100 if (bits[i] == RTLIL::S1)
101 return true;
102 return false;
103 }
104
105 int RTLIL::Const::as_int(bool is_signed) const
106 {
107 int32_t ret = 0;
108 for (size_t i = 0; i < bits.size() && i < 32; i++)
109 if (bits[i] == RTLIL::S1)
110 ret |= 1 << i;
111 if (is_signed && bits.back() == RTLIL::S1)
112 for (size_t i = bits.size(); i < 32; i++)
113 ret |= 1 << i;
114 return ret;
115 }
116
117 std::string RTLIL::Const::as_string() const
118 {
119 std::string ret;
120 for (size_t i = bits.size(); i > 0; i--)
121 switch (bits[i-1]) {
122 case S0: ret += "0"; break;
123 case S1: ret += "1"; break;
124 case Sx: ret += "x"; break;
125 case Sz: ret += "z"; break;
126 case Sa: ret += "-"; break;
127 case Sm: ret += "m"; break;
128 }
129 return ret;
130 }
131
132 RTLIL::Const RTLIL::Const::from_string(std::string str)
133 {
134 Const c;
135 for (auto it = str.rbegin(); it != str.rend(); it++)
136 switch (*it) {
137 case '0': c.bits.push_back(State::S0); break;
138 case '1': c.bits.push_back(State::S1); break;
139 case 'x': c.bits.push_back(State::Sx); break;
140 case 'z': c.bits.push_back(State::Sz); break;
141 case 'm': c.bits.push_back(State::Sm); break;
142 default: c.bits.push_back(State::Sa);
143 }
144 return c;
145 }
146
147 std::string RTLIL::Const::decode_string() const
148 {
149 std::string string;
150 std::vector<char> string_chars;
151 for (int i = 0; i < int (bits.size()); i += 8) {
152 char ch = 0;
153 for (int j = 0; j < 8 && i + j < int (bits.size()); j++)
154 if (bits[i + j] == RTLIL::State::S1)
155 ch |= 1 << j;
156 if (ch != 0)
157 string_chars.push_back(ch);
158 }
159 for (int i = int (string_chars.size()) - 1; i >= 0; i--)
160 string += string_chars[i];
161 return string;
162 }
163
164 void RTLIL::AttrObject::set_bool_attribute(RTLIL::IdString id)
165 {
166 attributes[id] = RTLIL::Const(1);
167 }
168
169 bool RTLIL::AttrObject::get_bool_attribute(RTLIL::IdString id) const
170 {
171 if (attributes.count(id) == 0)
172 return false;
173 return attributes.at(id).as_bool();
174 }
175
176 void RTLIL::AttrObject::set_strpool_attribute(RTLIL::IdString id, const pool<string> &data)
177 {
178 string attrval;
179 for (auto &s : data) {
180 if (!attrval.empty())
181 attrval += "|";
182 attrval += s;
183 }
184 attributes[id] = RTLIL::Const(attrval);
185 }
186
187 void RTLIL::AttrObject::add_strpool_attribute(RTLIL::IdString id, const pool<string> &data)
188 {
189 pool<string> union_data = get_strpool_attribute(id);
190 union_data.insert(data.begin(), data.end());
191 if (!union_data.empty())
192 set_strpool_attribute(id, union_data);
193 }
194
195 pool<string> RTLIL::AttrObject::get_strpool_attribute(RTLIL::IdString id) const
196 {
197 pool<string> data;
198 if (attributes.count(id) != 0)
199 for (auto s : split_tokens(attributes.at(id).decode_string(), "|"))
200 data.insert(s);
201 return data;
202 }
203
204 bool RTLIL::Selection::selected_module(RTLIL::IdString mod_name) const
205 {
206 if (full_selection)
207 return true;
208 if (selected_modules.count(mod_name) > 0)
209 return true;
210 if (selected_members.count(mod_name) > 0)
211 return true;
212 return false;
213 }
214
215 bool RTLIL::Selection::selected_whole_module(RTLIL::IdString mod_name) const
216 {
217 if (full_selection)
218 return true;
219 if (selected_modules.count(mod_name) > 0)
220 return true;
221 return false;
222 }
223
224 bool RTLIL::Selection::selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const
225 {
226 if (full_selection)
227 return true;
228 if (selected_modules.count(mod_name) > 0)
229 return true;
230 if (selected_members.count(mod_name) > 0)
231 if (selected_members.at(mod_name).count(memb_name) > 0)
232 return true;
233 return false;
234 }
235
236 void RTLIL::Selection::optimize(RTLIL::Design *design)
237 {
238 if (full_selection) {
239 selected_modules.clear();
240 selected_members.clear();
241 return;
242 }
243
244 std::vector<RTLIL::IdString> del_list, add_list;
245
246 del_list.clear();
247 for (auto mod_name : selected_modules) {
248 if (design->modules_.count(mod_name) == 0)
249 del_list.push_back(mod_name);
250 selected_members.erase(mod_name);
251 }
252 for (auto mod_name : del_list)
253 selected_modules.erase(mod_name);
254
255 del_list.clear();
256 for (auto &it : selected_members)
257 if (design->modules_.count(it.first) == 0)
258 del_list.push_back(it.first);
259 for (auto mod_name : del_list)
260 selected_members.erase(mod_name);
261
262 for (auto &it : selected_members) {
263 del_list.clear();
264 for (auto memb_name : it.second)
265 if (design->modules_[it.first]->count_id(memb_name) == 0)
266 del_list.push_back(memb_name);
267 for (auto memb_name : del_list)
268 it.second.erase(memb_name);
269 }
270
271 del_list.clear();
272 add_list.clear();
273 for (auto &it : selected_members)
274 if (it.second.size() == 0)
275 del_list.push_back(it.first);
276 else if (it.second.size() == design->modules_[it.first]->wires_.size() + design->modules_[it.first]->memories.size() +
277 design->modules_[it.first]->cells_.size() + design->modules_[it.first]->processes.size())
278 add_list.push_back(it.first);
279 for (auto mod_name : del_list)
280 selected_members.erase(mod_name);
281 for (auto mod_name : add_list) {
282 selected_members.erase(mod_name);
283 selected_modules.insert(mod_name);
284 }
285
286 if (selected_modules.size() == design->modules_.size()) {
287 full_selection = true;
288 selected_modules.clear();
289 selected_members.clear();
290 }
291 }
292
293 RTLIL::Design::Design()
294 {
295 static unsigned int hashidx_count = 123456789;
296 hashidx_count = mkhash_xorshift(hashidx_count);
297 hashidx_ = hashidx_count;
298
299 refcount_modules_ = 0;
300 selection_stack.push_back(RTLIL::Selection());
301 }
302
303 RTLIL::Design::~Design()
304 {
305 for (auto it = modules_.begin(); it != modules_.end(); ++it)
306 delete it->second;
307 }
308
309 RTLIL::ObjRange<RTLIL::Module*> RTLIL::Design::modules()
310 {
311 return RTLIL::ObjRange<RTLIL::Module*>(&modules_, &refcount_modules_);
312 }
313
314 RTLIL::Module *RTLIL::Design::module(RTLIL::IdString name)
315 {
316 return modules_.count(name) ? modules_.at(name) : NULL;
317 }
318
319 RTLIL::Module *RTLIL::Design::top_module()
320 {
321 RTLIL::Module *module = nullptr;
322 int module_count = 0;
323
324 for (auto mod : selected_modules()) {
325 if (mod->get_bool_attribute("\\top"))
326 return mod;
327 module_count++;
328 module = mod;
329 }
330
331 return module_count == 1 ? module : nullptr;
332 }
333
334 void RTLIL::Design::add(RTLIL::Module *module)
335 {
336 log_assert(modules_.count(module->name) == 0);
337 log_assert(refcount_modules_ == 0);
338 modules_[module->name] = module;
339 module->design = this;
340
341 for (auto mon : monitors)
342 mon->notify_module_add(module);
343
344 if (yosys_xtrace) {
345 log("#X# New Module: %s\n", log_id(module));
346 log_backtrace("-X- ", yosys_xtrace-1);
347 }
348 }
349
350 RTLIL::Module *RTLIL::Design::addModule(RTLIL::IdString name)
351 {
352 log_assert(modules_.count(name) == 0);
353 log_assert(refcount_modules_ == 0);
354
355 RTLIL::Module *module = new RTLIL::Module;
356 modules_[name] = module;
357 module->design = this;
358 module->name = name;
359
360 for (auto mon : monitors)
361 mon->notify_module_add(module);
362
363 if (yosys_xtrace) {
364 log("#X# New Module: %s\n", log_id(module));
365 log_backtrace("-X- ", yosys_xtrace-1);
366 }
367
368 return module;
369 }
370
371 void RTLIL::Design::scratchpad_unset(std::string varname)
372 {
373 scratchpad.erase(varname);
374 }
375
376 void RTLIL::Design::scratchpad_set_int(std::string varname, int value)
377 {
378 scratchpad[varname] = stringf("%d", value);
379 }
380
381 void RTLIL::Design::scratchpad_set_bool(std::string varname, bool value)
382 {
383 scratchpad[varname] = value ? "true" : "false";
384 }
385
386 void RTLIL::Design::scratchpad_set_string(std::string varname, std::string value)
387 {
388 scratchpad[varname] = value;
389 }
390
391 int RTLIL::Design::scratchpad_get_int(std::string varname, int default_value) const
392 {
393 if (scratchpad.count(varname) == 0)
394 return default_value;
395
396 std::string str = scratchpad.at(varname);
397
398 if (str == "0" || str == "false")
399 return 0;
400
401 if (str == "1" || str == "true")
402 return 1;
403
404 char *endptr = nullptr;
405 long int parsed_value = strtol(str.c_str(), &endptr, 10);
406 return *endptr ? default_value : parsed_value;
407 }
408
409 bool RTLIL::Design::scratchpad_get_bool(std::string varname, bool default_value) const
410 {
411 if (scratchpad.count(varname) == 0)
412 return default_value;
413
414 std::string str = scratchpad.at(varname);
415
416 if (str == "0" || str == "false")
417 return false;
418
419 if (str == "1" || str == "true")
420 return true;
421
422 return default_value;
423 }
424
425 std::string RTLIL::Design::scratchpad_get_string(std::string varname, std::string default_value) const
426 {
427 if (scratchpad.count(varname) == 0)
428 return default_value;
429 return scratchpad.at(varname);
430 }
431
432 void RTLIL::Design::remove(RTLIL::Module *module)
433 {
434 for (auto mon : monitors)
435 mon->notify_module_del(module);
436
437 if (yosys_xtrace) {
438 log("#X# Remove Module: %s\n", log_id(module));
439 log_backtrace("-X- ", yosys_xtrace-1);
440 }
441
442 log_assert(modules_.at(module->name) == module);
443 modules_.erase(module->name);
444 delete module;
445 }
446
447 void RTLIL::Design::rename(RTLIL::Module *module, RTLIL::IdString new_name)
448 {
449 modules_.erase(module->name);
450 module->name = new_name;
451 add(module);
452 }
453
454 void RTLIL::Design::sort()
455 {
456 scratchpad.sort();
457 modules_.sort(sort_by_id_str());
458 for (auto &it : modules_)
459 it.second->sort();
460 }
461
462 void RTLIL::Design::check()
463 {
464 #ifndef NDEBUG
465 for (auto &it : modules_) {
466 log_assert(this == it.second->design);
467 log_assert(it.first == it.second->name);
468 log_assert(!it.first.empty());
469 it.second->check();
470 }
471 #endif
472 }
473
474 void RTLIL::Design::optimize()
475 {
476 for (auto &it : modules_)
477 it.second->optimize();
478 for (auto &it : selection_stack)
479 it.optimize(this);
480 for (auto &it : selection_vars)
481 it.second.optimize(this);
482 }
483
484 bool RTLIL::Design::selected_module(RTLIL::IdString mod_name) const
485 {
486 if (!selected_active_module.empty() && mod_name != selected_active_module)
487 return false;
488 if (selection_stack.size() == 0)
489 return true;
490 return selection_stack.back().selected_module(mod_name);
491 }
492
493 bool RTLIL::Design::selected_whole_module(RTLIL::IdString mod_name) const
494 {
495 if (!selected_active_module.empty() && mod_name != selected_active_module)
496 return false;
497 if (selection_stack.size() == 0)
498 return true;
499 return selection_stack.back().selected_whole_module(mod_name);
500 }
501
502 bool RTLIL::Design::selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const
503 {
504 if (!selected_active_module.empty() && mod_name != selected_active_module)
505 return false;
506 if (selection_stack.size() == 0)
507 return true;
508 return selection_stack.back().selected_member(mod_name, memb_name);
509 }
510
511 bool RTLIL::Design::selected_module(RTLIL::Module *mod) const
512 {
513 return selected_module(mod->name);
514 }
515
516 bool RTLIL::Design::selected_whole_module(RTLIL::Module *mod) const
517 {
518 return selected_whole_module(mod->name);
519 }
520
521 std::vector<RTLIL::Module*> RTLIL::Design::selected_modules() const
522 {
523 std::vector<RTLIL::Module*> result;
524 result.reserve(modules_.size());
525 for (auto &it : modules_)
526 if (selected_module(it.first) && !it.second->get_bool_attribute("\\blackbox"))
527 result.push_back(it.second);
528 return result;
529 }
530
531 std::vector<RTLIL::Module*> RTLIL::Design::selected_whole_modules() const
532 {
533 std::vector<RTLIL::Module*> result;
534 result.reserve(modules_.size());
535 for (auto &it : modules_)
536 if (selected_whole_module(it.first) && !it.second->get_bool_attribute("\\blackbox"))
537 result.push_back(it.second);
538 return result;
539 }
540
541 std::vector<RTLIL::Module*> RTLIL::Design::selected_whole_modules_warn() const
542 {
543 std::vector<RTLIL::Module*> result;
544 result.reserve(modules_.size());
545 for (auto &it : modules_)
546 if (it.second->get_bool_attribute("\\blackbox"))
547 continue;
548 else if (selected_whole_module(it.first))
549 result.push_back(it.second);
550 else if (selected_module(it.first))
551 log_warning("Ignoring partially selected module %s.\n", log_id(it.first));
552 return result;
553 }
554
555 RTLIL::Module::Module()
556 {
557 static unsigned int hashidx_count = 123456789;
558 hashidx_count = mkhash_xorshift(hashidx_count);
559 hashidx_ = hashidx_count;
560
561 design = nullptr;
562 refcount_wires_ = 0;
563 refcount_cells_ = 0;
564 }
565
566 RTLIL::Module::~Module()
567 {
568 for (auto it = wires_.begin(); it != wires_.end(); ++it)
569 delete it->second;
570 for (auto it = memories.begin(); it != memories.end(); ++it)
571 delete it->second;
572 for (auto it = cells_.begin(); it != cells_.end(); ++it)
573 delete it->second;
574 for (auto it = processes.begin(); it != processes.end(); ++it)
575 delete it->second;
576 }
577
578 RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, dict<RTLIL::IdString, RTLIL::Const>)
579 {
580 log_error("Module `%s' is used with parameters but is not parametric!\n", id2cstr(name));
581 }
582
583 size_t RTLIL::Module::count_id(RTLIL::IdString id)
584 {
585 return wires_.count(id) + memories.count(id) + cells_.count(id) + processes.count(id);
586 }
587
588 #ifndef NDEBUG
589 namespace {
590 struct InternalCellChecker
591 {
592 RTLIL::Module *module;
593 RTLIL::Cell *cell;
594 pool<RTLIL::IdString> expected_params, expected_ports;
595
596 InternalCellChecker(RTLIL::Module *module, RTLIL::Cell *cell) : module(module), cell(cell) { }
597
598 void error(int linenr)
599 {
600 std::stringstream buf;
601 ILANG_BACKEND::dump_cell(buf, " ", cell);
602
603 log_error("Found error in internal cell %s%s%s (%s) at %s:%d:\n%s",
604 module ? module->name.c_str() : "", module ? "." : "",
605 cell->name.c_str(), cell->type.c_str(), __FILE__, linenr, buf.str().c_str());
606 }
607
608 int param(const char *name)
609 {
610 if (cell->parameters.count(name) == 0)
611 error(__LINE__);
612 expected_params.insert(name);
613 return cell->parameters.at(name).as_int();
614 }
615
616 int param_bool(const char *name)
617 {
618 int v = param(name);
619 if (cell->parameters.at(name).bits.size() > 32)
620 error(__LINE__);
621 if (v != 0 && v != 1)
622 error(__LINE__);
623 return v;
624 }
625
626 void param_bits(const char *name, int width)
627 {
628 param(name);
629 if (int(cell->parameters.at(name).bits.size()) != width)
630 error(__LINE__);
631 }
632
633 void port(const char *name, int width)
634 {
635 if (!cell->hasPort(name))
636 error(__LINE__);
637 if (cell->getPort(name).size() != width)
638 error(__LINE__);
639 expected_ports.insert(name);
640 }
641
642 void check_expected(bool check_matched_sign = true)
643 {
644 for (auto &para : cell->parameters)
645 if (expected_params.count(para.first) == 0)
646 error(__LINE__);
647 for (auto &conn : cell->connections())
648 if (expected_ports.count(conn.first) == 0)
649 error(__LINE__);
650
651 if (expected_params.count("\\A_SIGNED") != 0 && expected_params.count("\\B_SIGNED") && check_matched_sign) {
652 bool a_is_signed = param("\\A_SIGNED") != 0;
653 bool b_is_signed = param("\\B_SIGNED") != 0;
654 if (a_is_signed != b_is_signed)
655 error(__LINE__);
656 }
657 }
658
659 void check_gate(const char *ports)
660 {
661 if (cell->parameters.size() != 0)
662 error(__LINE__);
663
664 for (const char *p = ports; *p; p++) {
665 char portname[3] = { '\\', *p, 0 };
666 if (!cell->hasPort(portname))
667 error(__LINE__);
668 if (cell->getPort(portname).size() != 1)
669 error(__LINE__);
670 }
671
672 for (auto &conn : cell->connections()) {
673 if (conn.first.size() != 2 || conn.first[0] != '\\')
674 error(__LINE__);
675 if (strchr(ports, conn.first[1]) == NULL)
676 error(__LINE__);
677 }
678 }
679
680 void check()
681 {
682 if (cell->type.substr(0, 1) != "$" || cell->type.substr(0, 3) == "$__" || cell->type.substr(0, 8) == "$paramod" ||
683 cell->type.substr(0, 9) == "$verific$" || cell->type.substr(0, 7) == "$array:" || cell->type.substr(0, 8) == "$extern:")
684 return;
685
686 if (cell->type.in("$not", "$pos", "$neg")) {
687 param_bool("\\A_SIGNED");
688 port("\\A", param("\\A_WIDTH"));
689 port("\\Y", param("\\Y_WIDTH"));
690 check_expected();
691 return;
692 }
693
694 if (cell->type.in("$and", "$or", "$xor", "$xnor")) {
695 param_bool("\\A_SIGNED");
696 param_bool("\\B_SIGNED");
697 port("\\A", param("\\A_WIDTH"));
698 port("\\B", param("\\B_WIDTH"));
699 port("\\Y", param("\\Y_WIDTH"));
700 check_expected();
701 return;
702 }
703
704 if (cell->type.in("$reduce_and", "$reduce_or", "$reduce_xor", "$reduce_xnor", "$reduce_bool")) {
705 param_bool("\\A_SIGNED");
706 port("\\A", param("\\A_WIDTH"));
707 port("\\Y", param("\\Y_WIDTH"));
708 check_expected();
709 return;
710 }
711
712 if (cell->type.in("$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx")) {
713 param_bool("\\A_SIGNED");
714 param_bool("\\B_SIGNED");
715 port("\\A", param("\\A_WIDTH"));
716 port("\\B", param("\\B_WIDTH"));
717 port("\\Y", param("\\Y_WIDTH"));
718 check_expected(false);
719 return;
720 }
721
722 if (cell->type.in("$lt", "$le", "$eq", "$ne", "$eqx", "$nex", "$ge", "$gt")) {
723 param_bool("\\A_SIGNED");
724 param_bool("\\B_SIGNED");
725 port("\\A", param("\\A_WIDTH"));
726 port("\\B", param("\\B_WIDTH"));
727 port("\\Y", param("\\Y_WIDTH"));
728 check_expected();
729 return;
730 }
731
732 if (cell->type.in("$add", "$sub", "$mul", "$div", "$mod", "$pow")) {
733 param_bool("\\A_SIGNED");
734 param_bool("\\B_SIGNED");
735 port("\\A", param("\\A_WIDTH"));
736 port("\\B", param("\\B_WIDTH"));
737 port("\\Y", param("\\Y_WIDTH"));
738 check_expected(cell->type != "$pow");
739 return;
740 }
741
742 if (cell->type == "$fa") {
743 port("\\A", param("\\WIDTH"));
744 port("\\B", param("\\WIDTH"));
745 port("\\C", param("\\WIDTH"));
746 port("\\X", param("\\WIDTH"));
747 port("\\Y", param("\\WIDTH"));
748 check_expected();
749 return;
750 }
751
752 if (cell->type == "$lcu") {
753 port("\\P", param("\\WIDTH"));
754 port("\\G", param("\\WIDTH"));
755 port("\\CI", 1);
756 port("\\CO", param("\\WIDTH"));
757 check_expected();
758 return;
759 }
760
761 if (cell->type == "$alu") {
762 param_bool("\\A_SIGNED");
763 param_bool("\\B_SIGNED");
764 port("\\A", param("\\A_WIDTH"));
765 port("\\B", param("\\B_WIDTH"));
766 port("\\CI", 1);
767 port("\\BI", 1);
768 port("\\X", param("\\Y_WIDTH"));
769 port("\\Y", param("\\Y_WIDTH"));
770 port("\\CO", param("\\Y_WIDTH"));
771 check_expected();
772 return;
773 }
774
775 if (cell->type == "$macc") {
776 param("\\CONFIG");
777 param("\\CONFIG_WIDTH");
778 port("\\A", param("\\A_WIDTH"));
779 port("\\B", param("\\B_WIDTH"));
780 port("\\Y", param("\\Y_WIDTH"));
781 check_expected();
782 Macc().from_cell(cell);
783 return;
784 }
785
786 if (cell->type == "$logic_not") {
787 param_bool("\\A_SIGNED");
788 port("\\A", param("\\A_WIDTH"));
789 port("\\Y", param("\\Y_WIDTH"));
790 check_expected();
791 return;
792 }
793
794 if (cell->type == "$logic_and" || cell->type == "$logic_or") {
795 param_bool("\\A_SIGNED");
796 param_bool("\\B_SIGNED");
797 port("\\A", param("\\A_WIDTH"));
798 port("\\B", param("\\B_WIDTH"));
799 port("\\Y", param("\\Y_WIDTH"));
800 check_expected(false);
801 return;
802 }
803
804 if (cell->type == "$slice") {
805 param("\\OFFSET");
806 port("\\A", param("\\A_WIDTH"));
807 port("\\Y", param("\\Y_WIDTH"));
808 if (param("\\OFFSET") + param("\\Y_WIDTH") > param("\\A_WIDTH"))
809 error(__LINE__);
810 check_expected();
811 return;
812 }
813
814 if (cell->type == "$concat") {
815 port("\\A", param("\\A_WIDTH"));
816 port("\\B", param("\\B_WIDTH"));
817 port("\\Y", param("\\A_WIDTH") + param("\\B_WIDTH"));
818 check_expected();
819 return;
820 }
821
822 if (cell->type == "$mux") {
823 port("\\A", param("\\WIDTH"));
824 port("\\B", param("\\WIDTH"));
825 port("\\S", 1);
826 port("\\Y", param("\\WIDTH"));
827 check_expected();
828 return;
829 }
830
831 if (cell->type == "$pmux") {
832 port("\\A", param("\\WIDTH"));
833 port("\\B", param("\\WIDTH") * param("\\S_WIDTH"));
834 port("\\S", param("\\S_WIDTH"));
835 port("\\Y", param("\\WIDTH"));
836 check_expected();
837 return;
838 }
839
840 if (cell->type == "$lut") {
841 param("\\LUT");
842 port("\\A", param("\\WIDTH"));
843 port("\\Y", 1);
844 check_expected();
845 return;
846 }
847
848 if (cell->type == "$sr") {
849 param_bool("\\SET_POLARITY");
850 param_bool("\\CLR_POLARITY");
851 port("\\SET", param("\\WIDTH"));
852 port("\\CLR", param("\\WIDTH"));
853 port("\\Q", param("\\WIDTH"));
854 check_expected();
855 return;
856 }
857
858 if (cell->type == "$dff") {
859 param_bool("\\CLK_POLARITY");
860 port("\\CLK", 1);
861 port("\\D", param("\\WIDTH"));
862 port("\\Q", param("\\WIDTH"));
863 check_expected();
864 return;
865 }
866
867 if (cell->type == "$dffe") {
868 param_bool("\\CLK_POLARITY");
869 param_bool("\\EN_POLARITY");
870 port("\\CLK", 1);
871 port("\\EN", 1);
872 port("\\D", param("\\WIDTH"));
873 port("\\Q", param("\\WIDTH"));
874 check_expected();
875 return;
876 }
877
878 if (cell->type == "$dffsr") {
879 param_bool("\\CLK_POLARITY");
880 param_bool("\\SET_POLARITY");
881 param_bool("\\CLR_POLARITY");
882 port("\\CLK", 1);
883 port("\\SET", param("\\WIDTH"));
884 port("\\CLR", param("\\WIDTH"));
885 port("\\D", param("\\WIDTH"));
886 port("\\Q", param("\\WIDTH"));
887 check_expected();
888 return;
889 }
890
891 if (cell->type == "$adff") {
892 param_bool("\\CLK_POLARITY");
893 param_bool("\\ARST_POLARITY");
894 param_bits("\\ARST_VALUE", param("\\WIDTH"));
895 port("\\CLK", 1);
896 port("\\ARST", 1);
897 port("\\D", param("\\WIDTH"));
898 port("\\Q", param("\\WIDTH"));
899 check_expected();
900 return;
901 }
902
903 if (cell->type == "$dlatch") {
904 param_bool("\\EN_POLARITY");
905 port("\\EN", 1);
906 port("\\D", param("\\WIDTH"));
907 port("\\Q", param("\\WIDTH"));
908 check_expected();
909 return;
910 }
911
912 if (cell->type == "$dlatchsr") {
913 param_bool("\\EN_POLARITY");
914 param_bool("\\SET_POLARITY");
915 param_bool("\\CLR_POLARITY");
916 port("\\EN", 1);
917 port("\\SET", param("\\WIDTH"));
918 port("\\CLR", param("\\WIDTH"));
919 port("\\D", param("\\WIDTH"));
920 port("\\Q", param("\\WIDTH"));
921 check_expected();
922 return;
923 }
924
925 if (cell->type == "$fsm") {
926 param("\\NAME");
927 param_bool("\\CLK_POLARITY");
928 param_bool("\\ARST_POLARITY");
929 param("\\STATE_BITS");
930 param("\\STATE_NUM");
931 param("\\STATE_NUM_LOG2");
932 param("\\STATE_RST");
933 param_bits("\\STATE_TABLE", param("\\STATE_BITS") * param("\\STATE_NUM"));
934 param("\\TRANS_NUM");
935 param_bits("\\TRANS_TABLE", param("\\TRANS_NUM") * (2*param("\\STATE_NUM_LOG2") + param("\\CTRL_IN_WIDTH") + param("\\CTRL_OUT_WIDTH")));
936 port("\\CLK", 1);
937 port("\\ARST", 1);
938 port("\\CTRL_IN", param("\\CTRL_IN_WIDTH"));
939 port("\\CTRL_OUT", param("\\CTRL_OUT_WIDTH"));
940 check_expected();
941 return;
942 }
943
944 if (cell->type == "$memrd") {
945 param("\\MEMID");
946 param_bool("\\CLK_ENABLE");
947 param_bool("\\CLK_POLARITY");
948 param_bool("\\TRANSPARENT");
949 port("\\CLK", 1);
950 port("\\ADDR", param("\\ABITS"));
951 port("\\DATA", param("\\WIDTH"));
952 check_expected();
953 return;
954 }
955
956 if (cell->type == "$memwr") {
957 param("\\MEMID");
958 param_bool("\\CLK_ENABLE");
959 param_bool("\\CLK_POLARITY");
960 param("\\PRIORITY");
961 port("\\CLK", 1);
962 port("\\EN", param("\\WIDTH"));
963 port("\\ADDR", param("\\ABITS"));
964 port("\\DATA", param("\\WIDTH"));
965 check_expected();
966 return;
967 }
968
969 if (cell->type == "$meminit") {
970 param("\\MEMID");
971 param("\\PRIORITY");
972 port("\\ADDR", param("\\ABITS"));
973 port("\\DATA", param("\\WIDTH"));
974 check_expected();
975 return;
976 }
977
978 if (cell->type == "$mem") {
979 param("\\MEMID");
980 param("\\SIZE");
981 param("\\OFFSET");
982 param("\\INIT");
983 param_bits("\\RD_CLK_ENABLE", std::max(1, param("\\RD_PORTS")));
984 param_bits("\\RD_CLK_POLARITY", std::max(1, param("\\RD_PORTS")));
985 param_bits("\\RD_TRANSPARENT", std::max(1, param("\\RD_PORTS")));
986 param_bits("\\WR_CLK_ENABLE", std::max(1, param("\\WR_PORTS")));
987 param_bits("\\WR_CLK_POLARITY", std::max(1, param("\\WR_PORTS")));
988 port("\\RD_CLK", param("\\RD_PORTS"));
989 port("\\RD_ADDR", param("\\RD_PORTS") * param("\\ABITS"));
990 port("\\RD_DATA", param("\\RD_PORTS") * param("\\WIDTH"));
991 port("\\WR_CLK", param("\\WR_PORTS"));
992 port("\\WR_EN", param("\\WR_PORTS") * param("\\WIDTH"));
993 port("\\WR_ADDR", param("\\WR_PORTS") * param("\\ABITS"));
994 port("\\WR_DATA", param("\\WR_PORTS") * param("\\WIDTH"));
995 check_expected();
996 return;
997 }
998
999 if (cell->type == "$assert") {
1000 port("\\A", 1);
1001 port("\\EN", 1);
1002 check_expected();
1003 return;
1004 }
1005
1006 if (cell->type == "$assume") {
1007 port("\\A", 1);
1008 port("\\EN", 1);
1009 check_expected();
1010 return;
1011 }
1012
1013 if (cell->type == "$equiv") {
1014 port("\\A", 1);
1015 port("\\B", 1);
1016 port("\\Y", 1);
1017 check_expected();
1018 return;
1019 }
1020
1021 if (cell->type == "$_BUF_") { check_gate("AY"); return; }
1022 if (cell->type == "$_NOT_") { check_gate("AY"); return; }
1023 if (cell->type == "$_AND_") { check_gate("ABY"); return; }
1024 if (cell->type == "$_NAND_") { check_gate("ABY"); return; }
1025 if (cell->type == "$_OR_") { check_gate("ABY"); return; }
1026 if (cell->type == "$_NOR_") { check_gate("ABY"); return; }
1027 if (cell->type == "$_XOR_") { check_gate("ABY"); return; }
1028 if (cell->type == "$_XNOR_") { check_gate("ABY"); return; }
1029 if (cell->type == "$_MUX_") { check_gate("ABSY"); return; }
1030 if (cell->type == "$_AOI3_") { check_gate("ABCY"); return; }
1031 if (cell->type == "$_OAI3_") { check_gate("ABCY"); return; }
1032 if (cell->type == "$_AOI4_") { check_gate("ABCDY"); return; }
1033 if (cell->type == "$_OAI4_") { check_gate("ABCDY"); return; }
1034
1035 if (cell->type == "$_MUX4_") { check_gate("ABCDSTY"); return; }
1036 if (cell->type == "$_MUX8_") { check_gate("ABCDEFGHSTUY"); return; }
1037 if (cell->type == "$_MUX16_") { check_gate("ABCDEFGHIJKLMNOPSTUVY"); return; }
1038
1039 if (cell->type == "$_SR_NN_") { check_gate("SRQ"); return; }
1040 if (cell->type == "$_SR_NP_") { check_gate("SRQ"); return; }
1041 if (cell->type == "$_SR_PN_") { check_gate("SRQ"); return; }
1042 if (cell->type == "$_SR_PP_") { check_gate("SRQ"); return; }
1043
1044 if (cell->type == "$_DFF_N_") { check_gate("DQC"); return; }
1045 if (cell->type == "$_DFF_P_") { check_gate("DQC"); return; }
1046
1047 if (cell->type == "$_DFFE_NN_") { check_gate("DQCE"); return; }
1048 if (cell->type == "$_DFFE_NP_") { check_gate("DQCE"); return; }
1049 if (cell->type == "$_DFFE_PN_") { check_gate("DQCE"); return; }
1050 if (cell->type == "$_DFFE_PP_") { check_gate("DQCE"); return; }
1051
1052 if (cell->type == "$_DFF_NN0_") { check_gate("DQCR"); return; }
1053 if (cell->type == "$_DFF_NN1_") { check_gate("DQCR"); return; }
1054 if (cell->type == "$_DFF_NP0_") { check_gate("DQCR"); return; }
1055 if (cell->type == "$_DFF_NP1_") { check_gate("DQCR"); return; }
1056 if (cell->type == "$_DFF_PN0_") { check_gate("DQCR"); return; }
1057 if (cell->type == "$_DFF_PN1_") { check_gate("DQCR"); return; }
1058 if (cell->type == "$_DFF_PP0_") { check_gate("DQCR"); return; }
1059 if (cell->type == "$_DFF_PP1_") { check_gate("DQCR"); return; }
1060
1061 if (cell->type == "$_DFFSR_NNN_") { check_gate("CSRDQ"); return; }
1062 if (cell->type == "$_DFFSR_NNP_") { check_gate("CSRDQ"); return; }
1063 if (cell->type == "$_DFFSR_NPN_") { check_gate("CSRDQ"); return; }
1064 if (cell->type == "$_DFFSR_NPP_") { check_gate("CSRDQ"); return; }
1065 if (cell->type == "$_DFFSR_PNN_") { check_gate("CSRDQ"); return; }
1066 if (cell->type == "$_DFFSR_PNP_") { check_gate("CSRDQ"); return; }
1067 if (cell->type == "$_DFFSR_PPN_") { check_gate("CSRDQ"); return; }
1068 if (cell->type == "$_DFFSR_PPP_") { check_gate("CSRDQ"); return; }
1069
1070 if (cell->type == "$_DLATCH_N_") { check_gate("EDQ"); return; }
1071 if (cell->type == "$_DLATCH_P_") { check_gate("EDQ"); return; }
1072
1073 if (cell->type == "$_DLATCHSR_NNN_") { check_gate("ESRDQ"); return; }
1074 if (cell->type == "$_DLATCHSR_NNP_") { check_gate("ESRDQ"); return; }
1075 if (cell->type == "$_DLATCHSR_NPN_") { check_gate("ESRDQ"); return; }
1076 if (cell->type == "$_DLATCHSR_NPP_") { check_gate("ESRDQ"); return; }
1077 if (cell->type == "$_DLATCHSR_PNN_") { check_gate("ESRDQ"); return; }
1078 if (cell->type == "$_DLATCHSR_PNP_") { check_gate("ESRDQ"); return; }
1079 if (cell->type == "$_DLATCHSR_PPN_") { check_gate("ESRDQ"); return; }
1080 if (cell->type == "$_DLATCHSR_PPP_") { check_gate("ESRDQ"); return; }
1081
1082 error(__LINE__);
1083 }
1084 };
1085 }
1086 #endif
1087
1088 void RTLIL::Module::sort()
1089 {
1090 wires_.sort(sort_by_id_str());
1091 cells_.sort(sort_by_id_str());
1092 avail_parameters.sort(sort_by_id_str());
1093 memories.sort(sort_by_id_str());
1094 processes.sort(sort_by_id_str());
1095 for (auto &it : cells_)
1096 it.second->sort();
1097 for (auto &it : wires_)
1098 it.second->attributes.sort(sort_by_id_str());
1099 for (auto &it : memories)
1100 it.second->attributes.sort(sort_by_id_str());
1101 }
1102
1103 void RTLIL::Module::check()
1104 {
1105 #ifndef NDEBUG
1106 std::vector<bool> ports_declared;
1107 for (auto &it : wires_) {
1108 log_assert(this == it.second->module);
1109 log_assert(it.first == it.second->name);
1110 log_assert(!it.first.empty());
1111 log_assert(it.second->width >= 0);
1112 log_assert(it.second->port_id >= 0);
1113 for (auto &it2 : it.second->attributes)
1114 log_assert(!it2.first.empty());
1115 if (it.second->port_id) {
1116 log_assert(GetSize(ports) >= it.second->port_id);
1117 log_assert(ports.at(it.second->port_id-1) == it.first);
1118 log_assert(it.second->port_input || it.second->port_output);
1119 if (GetSize(ports_declared) < it.second->port_id)
1120 ports_declared.resize(it.second->port_id);
1121 log_assert(ports_declared[it.second->port_id-1] == false);
1122 ports_declared[it.second->port_id-1] = true;
1123 } else
1124 log_assert(!it.second->port_input && !it.second->port_output);
1125 }
1126 for (auto port_declared : ports_declared)
1127 log_assert(port_declared == true);
1128 log_assert(GetSize(ports) == GetSize(ports_declared));
1129
1130 for (auto &it : memories) {
1131 log_assert(it.first == it.second->name);
1132 log_assert(!it.first.empty());
1133 log_assert(it.second->width >= 0);
1134 log_assert(it.second->size >= 0);
1135 for (auto &it2 : it.second->attributes)
1136 log_assert(!it2.first.empty());
1137 }
1138
1139 for (auto &it : cells_) {
1140 log_assert(this == it.second->module);
1141 log_assert(it.first == it.second->name);
1142 log_assert(!it.first.empty());
1143 log_assert(!it.second->type.empty());
1144 for (auto &it2 : it.second->connections()) {
1145 log_assert(!it2.first.empty());
1146 it2.second.check();
1147 }
1148 for (auto &it2 : it.second->attributes)
1149 log_assert(!it2.first.empty());
1150 for (auto &it2 : it.second->parameters)
1151 log_assert(!it2.first.empty());
1152 InternalCellChecker checker(this, it.second);
1153 checker.check();
1154 }
1155
1156 for (auto &it : processes) {
1157 log_assert(it.first == it.second->name);
1158 log_assert(!it.first.empty());
1159 // FIXME: More checks here..
1160 }
1161
1162 for (auto &it : connections_) {
1163 log_assert(it.first.size() == it.second.size());
1164 log_assert(!it.first.has_const());
1165 it.first.check();
1166 it.second.check();
1167 }
1168
1169 for (auto &it : attributes)
1170 log_assert(!it.first.empty());
1171 #endif
1172 }
1173
1174 void RTLIL::Module::optimize()
1175 {
1176 }
1177
1178 void RTLIL::Module::cloneInto(RTLIL::Module *new_mod) const
1179 {
1180 log_assert(new_mod->refcount_wires_ == 0);
1181 log_assert(new_mod->refcount_cells_ == 0);
1182
1183 new_mod->avail_parameters = avail_parameters;
1184
1185 for (auto &conn : connections_)
1186 new_mod->connect(conn);
1187
1188 for (auto &attr : attributes)
1189 new_mod->attributes[attr.first] = attr.second;
1190
1191 for (auto &it : wires_)
1192 new_mod->addWire(it.first, it.second);
1193
1194 for (auto &it : memories)
1195 new_mod->memories[it.first] = new RTLIL::Memory(*it.second);
1196
1197 for (auto &it : cells_)
1198 new_mod->addCell(it.first, it.second);
1199
1200 for (auto &it : processes)
1201 new_mod->processes[it.first] = it.second->clone();
1202
1203 struct RewriteSigSpecWorker
1204 {
1205 RTLIL::Module *mod;
1206 void operator()(RTLIL::SigSpec &sig)
1207 {
1208 std::vector<RTLIL::SigChunk> chunks = sig.chunks();
1209 for (auto &c : chunks)
1210 if (c.wire != NULL)
1211 c.wire = mod->wires_.at(c.wire->name);
1212 sig = chunks;
1213 }
1214 };
1215
1216 RewriteSigSpecWorker rewriteSigSpecWorker;
1217 rewriteSigSpecWorker.mod = new_mod;
1218 new_mod->rewrite_sigspecs(rewriteSigSpecWorker);
1219 new_mod->fixup_ports();
1220 }
1221
1222 RTLIL::Module *RTLIL::Module::clone() const
1223 {
1224 RTLIL::Module *new_mod = new RTLIL::Module;
1225 new_mod->name = name;
1226 cloneInto(new_mod);
1227 return new_mod;
1228 }
1229
1230 bool RTLIL::Module::has_memories() const
1231 {
1232 return !memories.empty();
1233 }
1234
1235 bool RTLIL::Module::has_processes() const
1236 {
1237 return !processes.empty();
1238 }
1239
1240 bool RTLIL::Module::has_memories_warn() const
1241 {
1242 if (!memories.empty())
1243 log_warning("Ignoring module %s because it contains memories (run 'memory' command first).\n", log_id(this));
1244 return !memories.empty();
1245 }
1246
1247 bool RTLIL::Module::has_processes_warn() const
1248 {
1249 if (!processes.empty())
1250 log_warning("Ignoring module %s because it contains processes (run 'proc' command first).\n", log_id(this));
1251 return !processes.empty();
1252 }
1253
1254 std::vector<RTLIL::Wire*> RTLIL::Module::selected_wires() const
1255 {
1256 std::vector<RTLIL::Wire*> result;
1257 result.reserve(wires_.size());
1258 for (auto &it : wires_)
1259 if (design->selected(this, it.second))
1260 result.push_back(it.second);
1261 return result;
1262 }
1263
1264 std::vector<RTLIL::Cell*> RTLIL::Module::selected_cells() const
1265 {
1266 std::vector<RTLIL::Cell*> result;
1267 result.reserve(wires_.size());
1268 for (auto &it : cells_)
1269 if (design->selected(this, it.second))
1270 result.push_back(it.second);
1271 return result;
1272 }
1273
1274 void RTLIL::Module::add(RTLIL::Wire *wire)
1275 {
1276 log_assert(!wire->name.empty());
1277 log_assert(count_id(wire->name) == 0);
1278 log_assert(refcount_wires_ == 0);
1279 wires_[wire->name] = wire;
1280 wire->module = this;
1281 }
1282
1283 void RTLIL::Module::add(RTLIL::Cell *cell)
1284 {
1285 log_assert(!cell->name.empty());
1286 log_assert(count_id(cell->name) == 0);
1287 log_assert(refcount_cells_ == 0);
1288 cells_[cell->name] = cell;
1289 cell->module = this;
1290 }
1291
1292 namespace {
1293 struct DeleteWireWorker
1294 {
1295 RTLIL::Module *module;
1296 const pool<RTLIL::Wire*> *wires_p;
1297
1298 void operator()(RTLIL::SigSpec &sig) {
1299 std::vector<RTLIL::SigChunk> chunks = sig;
1300 for (auto &c : chunks)
1301 if (c.wire != NULL && wires_p->count(c.wire)) {
1302 c.wire = module->addWire(NEW_ID, c.width);
1303 c.offset = 0;
1304 }
1305 sig = chunks;
1306 }
1307 };
1308 }
1309
1310 void RTLIL::Module::remove(const pool<RTLIL::Wire*> &wires)
1311 {
1312 log_assert(refcount_wires_ == 0);
1313
1314 DeleteWireWorker delete_wire_worker;
1315 delete_wire_worker.module = this;
1316 delete_wire_worker.wires_p = &wires;
1317 rewrite_sigspecs(delete_wire_worker);
1318
1319 for (auto &it : wires) {
1320 log_assert(wires_.count(it->name) != 0);
1321 wires_.erase(it->name);
1322 delete it;
1323 }
1324 }
1325
1326 void RTLIL::Module::remove(RTLIL::Cell *cell)
1327 {
1328 while (!cell->connections_.empty())
1329 cell->unsetPort(cell->connections_.begin()->first);
1330
1331 log_assert(cells_.count(cell->name) != 0);
1332 log_assert(refcount_cells_ == 0);
1333 cells_.erase(cell->name);
1334 delete cell;
1335 }
1336
1337 void RTLIL::Module::rename(RTLIL::Wire *wire, RTLIL::IdString new_name)
1338 {
1339 log_assert(wires_[wire->name] == wire);
1340 log_assert(refcount_wires_ == 0);
1341 wires_.erase(wire->name);
1342 wire->name = new_name;
1343 add(wire);
1344 }
1345
1346 void RTLIL::Module::rename(RTLIL::Cell *cell, RTLIL::IdString new_name)
1347 {
1348 log_assert(cells_[cell->name] == cell);
1349 log_assert(refcount_wires_ == 0);
1350 cells_.erase(cell->name);
1351 cell->name = new_name;
1352 add(cell);
1353 }
1354
1355 void RTLIL::Module::rename(RTLIL::IdString old_name, RTLIL::IdString new_name)
1356 {
1357 log_assert(count_id(old_name) != 0);
1358 if (wires_.count(old_name))
1359 rename(wires_.at(old_name), new_name);
1360 else if (cells_.count(old_name))
1361 rename(cells_.at(old_name), new_name);
1362 else
1363 log_abort();
1364 }
1365
1366 void RTLIL::Module::swap_names(RTLIL::Wire *w1, RTLIL::Wire *w2)
1367 {
1368 log_assert(wires_[w1->name] == w1);
1369 log_assert(wires_[w2->name] == w2);
1370 log_assert(refcount_wires_ == 0);
1371
1372 wires_.erase(w1->name);
1373 wires_.erase(w2->name);
1374
1375 std::swap(w1->name, w2->name);
1376
1377 wires_[w1->name] = w1;
1378 wires_[w2->name] = w2;
1379 }
1380
1381 void RTLIL::Module::swap_names(RTLIL::Cell *c1, RTLIL::Cell *c2)
1382 {
1383 log_assert(cells_[c1->name] == c1);
1384 log_assert(cells_[c2->name] == c2);
1385 log_assert(refcount_cells_ == 0);
1386
1387 cells_.erase(c1->name);
1388 cells_.erase(c2->name);
1389
1390 std::swap(c1->name, c2->name);
1391
1392 cells_[c1->name] = c1;
1393 cells_[c2->name] = c2;
1394 }
1395
1396 RTLIL::IdString RTLIL::Module::uniquify(RTLIL::IdString name)
1397 {
1398 int index = 0;
1399 return uniquify(name, index);
1400 }
1401
1402 RTLIL::IdString RTLIL::Module::uniquify(RTLIL::IdString name, int &index)
1403 {
1404 if (index == 0) {
1405 if (count_id(name) == 0)
1406 return name;
1407 index++;
1408 }
1409
1410 while (1) {
1411 RTLIL::IdString new_name = stringf("%s_%d", name.c_str(), index);
1412 if (count_id(new_name) == 0)
1413 return new_name;
1414 index++;
1415 }
1416 }
1417
1418 static bool fixup_ports_compare(const RTLIL::Wire *a, const RTLIL::Wire *b)
1419 {
1420 if (a->port_id && !b->port_id)
1421 return true;
1422 if (!a->port_id && b->port_id)
1423 return false;
1424
1425 if (a->port_id == b->port_id)
1426 return a->name < b->name;
1427 return a->port_id < b->port_id;
1428 }
1429
1430 void RTLIL::Module::connect(const RTLIL::SigSig &conn)
1431 {
1432 for (auto mon : monitors)
1433 mon->notify_connect(this, conn);
1434
1435 if (design)
1436 for (auto mon : design->monitors)
1437 mon->notify_connect(this, conn);
1438
1439 if (yosys_xtrace) {
1440 log("#X# Connect (SigSig) in %s: %s = %s (%d bits)\n", log_id(this), log_signal(conn.first), log_signal(conn.second), GetSize(conn.first));
1441 log_backtrace("-X- ", yosys_xtrace-1);
1442 }
1443
1444 connections_.push_back(conn);
1445 }
1446
1447 void RTLIL::Module::connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs)
1448 {
1449 connect(RTLIL::SigSig(lhs, rhs));
1450 }
1451
1452 void RTLIL::Module::new_connections(const std::vector<RTLIL::SigSig> &new_conn)
1453 {
1454 for (auto mon : monitors)
1455 mon->notify_connect(this, new_conn);
1456
1457 if (design)
1458 for (auto mon : design->monitors)
1459 mon->notify_connect(this, new_conn);
1460
1461 if (yosys_xtrace) {
1462 log("#X# New connections vector in %s:\n", log_id(this));
1463 for (auto &conn: new_conn)
1464 log("#X# %s = %s (%d bits)\n", log_signal(conn.first), log_signal(conn.second), GetSize(conn.first));
1465 log_backtrace("-X- ", yosys_xtrace-1);
1466 }
1467
1468 connections_ = new_conn;
1469 }
1470
1471 const std::vector<RTLIL::SigSig> &RTLIL::Module::connections() const
1472 {
1473 return connections_;
1474 }
1475
1476 void RTLIL::Module::fixup_ports()
1477 {
1478 std::vector<RTLIL::Wire*> all_ports;
1479
1480 for (auto &w : wires_)
1481 if (w.second->port_input || w.second->port_output)
1482 all_ports.push_back(w.second);
1483 else
1484 w.second->port_id = 0;
1485
1486 std::sort(all_ports.begin(), all_ports.end(), fixup_ports_compare);
1487
1488 ports.clear();
1489 for (size_t i = 0; i < all_ports.size(); i++) {
1490 ports.push_back(all_ports[i]->name);
1491 all_ports[i]->port_id = i+1;
1492 }
1493 }
1494
1495 RTLIL::Wire *RTLIL::Module::addWire(RTLIL::IdString name, int width)
1496 {
1497 RTLIL::Wire *wire = new RTLIL::Wire;
1498 wire->name = name;
1499 wire->width = width;
1500 add(wire);
1501 return wire;
1502 }
1503
1504 RTLIL::Wire *RTLIL::Module::addWire(RTLIL::IdString name, const RTLIL::Wire *other)
1505 {
1506 RTLIL::Wire *wire = addWire(name);
1507 wire->width = other->width;
1508 wire->start_offset = other->start_offset;
1509 wire->port_id = other->port_id;
1510 wire->port_input = other->port_input;
1511 wire->port_output = other->port_output;
1512 wire->upto = other->upto;
1513 wire->attributes = other->attributes;
1514 return wire;
1515 }
1516
1517 RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, RTLIL::IdString type)
1518 {
1519 RTLIL::Cell *cell = new RTLIL::Cell;
1520 cell->name = name;
1521 cell->type = type;
1522 add(cell);
1523 return cell;
1524 }
1525
1526 RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, const RTLIL::Cell *other)
1527 {
1528 RTLIL::Cell *cell = addCell(name, other->type);
1529 cell->connections_ = other->connections_;
1530 cell->parameters = other->parameters;
1531 cell->attributes = other->attributes;
1532 return cell;
1533 }
1534
1535 #define DEF_METHOD(_func, _y_size, _type) \
1536 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed) { \
1537 RTLIL::Cell *cell = addCell(name, _type); \
1538 cell->parameters["\\A_SIGNED"] = is_signed; \
1539 cell->parameters["\\A_WIDTH"] = sig_a.size(); \
1540 cell->parameters["\\Y_WIDTH"] = sig_y.size(); \
1541 cell->setPort("\\A", sig_a); \
1542 cell->setPort("\\Y", sig_y); \
1543 return cell; \
1544 } \
1545 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed) { \
1546 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
1547 add ## _func(name, sig_a, sig_y, is_signed); \
1548 return sig_y; \
1549 }
1550 DEF_METHOD(Not, sig_a.size(), "$not")
1551 DEF_METHOD(Pos, sig_a.size(), "$pos")
1552 DEF_METHOD(Neg, sig_a.size(), "$neg")
1553 DEF_METHOD(ReduceAnd, 1, "$reduce_and")
1554 DEF_METHOD(ReduceOr, 1, "$reduce_or")
1555 DEF_METHOD(ReduceXor, 1, "$reduce_xor")
1556 DEF_METHOD(ReduceXnor, 1, "$reduce_xnor")
1557 DEF_METHOD(ReduceBool, 1, "$reduce_bool")
1558 DEF_METHOD(LogicNot, 1, "$logic_not")
1559 #undef DEF_METHOD
1560
1561 #define DEF_METHOD(_func, _y_size, _type) \
1562 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed) { \
1563 RTLIL::Cell *cell = addCell(name, _type); \
1564 cell->parameters["\\A_SIGNED"] = is_signed; \
1565 cell->parameters["\\B_SIGNED"] = is_signed; \
1566 cell->parameters["\\A_WIDTH"] = sig_a.size(); \
1567 cell->parameters["\\B_WIDTH"] = sig_b.size(); \
1568 cell->parameters["\\Y_WIDTH"] = sig_y.size(); \
1569 cell->setPort("\\A", sig_a); \
1570 cell->setPort("\\B", sig_b); \
1571 cell->setPort("\\Y", sig_y); \
1572 return cell; \
1573 } \
1574 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed) { \
1575 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
1576 add ## _func(name, sig_a, sig_b, sig_y, is_signed); \
1577 return sig_y; \
1578 }
1579 DEF_METHOD(And, std::max(sig_a.size(), sig_b.size()), "$and")
1580 DEF_METHOD(Or, std::max(sig_a.size(), sig_b.size()), "$or")
1581 DEF_METHOD(Xor, std::max(sig_a.size(), sig_b.size()), "$xor")
1582 DEF_METHOD(Xnor, std::max(sig_a.size(), sig_b.size()), "$xnor")
1583 DEF_METHOD(Shl, sig_a.size(), "$shl")
1584 DEF_METHOD(Shr, sig_a.size(), "$shr")
1585 DEF_METHOD(Sshl, sig_a.size(), "$sshl")
1586 DEF_METHOD(Sshr, sig_a.size(), "$sshr")
1587 DEF_METHOD(Shift, sig_a.size(), "$shift")
1588 DEF_METHOD(Shiftx, sig_a.size(), "$shiftx")
1589 DEF_METHOD(Lt, 1, "$lt")
1590 DEF_METHOD(Le, 1, "$le")
1591 DEF_METHOD(Eq, 1, "$eq")
1592 DEF_METHOD(Ne, 1, "$ne")
1593 DEF_METHOD(Eqx, 1, "$eqx")
1594 DEF_METHOD(Nex, 1, "$nex")
1595 DEF_METHOD(Ge, 1, "$ge")
1596 DEF_METHOD(Gt, 1, "$gt")
1597 DEF_METHOD(Add, std::max(sig_a.size(), sig_b.size()), "$add")
1598 DEF_METHOD(Sub, std::max(sig_a.size(), sig_b.size()), "$sub")
1599 DEF_METHOD(Mul, std::max(sig_a.size(), sig_b.size()), "$mul")
1600 DEF_METHOD(Div, std::max(sig_a.size(), sig_b.size()), "$div")
1601 DEF_METHOD(Mod, std::max(sig_a.size(), sig_b.size()), "$mod")
1602 DEF_METHOD(LogicAnd, 1, "$logic_and")
1603 DEF_METHOD(LogicOr, 1, "$logic_or")
1604 #undef DEF_METHOD
1605
1606 #define DEF_METHOD(_func, _type, _pmux) \
1607 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, RTLIL::SigSpec sig_y) { \
1608 RTLIL::Cell *cell = addCell(name, _type); \
1609 cell->parameters["\\WIDTH"] = sig_a.size(); \
1610 if (_pmux) cell->parameters["\\S_WIDTH"] = sig_s.size(); \
1611 cell->setPort("\\A", sig_a); \
1612 cell->setPort("\\B", sig_b); \
1613 cell->setPort("\\S", sig_s); \
1614 cell->setPort("\\Y", sig_y); \
1615 return cell; \
1616 } \
1617 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s) { \
1618 RTLIL::SigSpec sig_y = addWire(NEW_ID, sig_a.size()); \
1619 add ## _func(name, sig_a, sig_b, sig_s, sig_y); \
1620 return sig_y; \
1621 }
1622 DEF_METHOD(Mux, "$mux", 0)
1623 DEF_METHOD(Pmux, "$pmux", 1)
1624 #undef DEF_METHOD
1625
1626 #define DEF_METHOD_2(_func, _type, _P1, _P2) \
1627 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2) { \
1628 RTLIL::Cell *cell = addCell(name, _type); \
1629 cell->setPort("\\" #_P1, sig1); \
1630 cell->setPort("\\" #_P2, sig2); \
1631 return cell; \
1632 } \
1633 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1) { \
1634 RTLIL::SigBit sig2 = addWire(NEW_ID); \
1635 add ## _func(name, sig1, sig2); \
1636 return sig2; \
1637 }
1638 #define DEF_METHOD_3(_func, _type, _P1, _P2, _P3) \
1639 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3) { \
1640 RTLIL::Cell *cell = addCell(name, _type); \
1641 cell->setPort("\\" #_P1, sig1); \
1642 cell->setPort("\\" #_P2, sig2); \
1643 cell->setPort("\\" #_P3, sig3); \
1644 return cell; \
1645 } \
1646 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2) { \
1647 RTLIL::SigBit sig3 = addWire(NEW_ID); \
1648 add ## _func(name, sig1, sig2, sig3); \
1649 return sig3; \
1650 }
1651 #define DEF_METHOD_4(_func, _type, _P1, _P2, _P3, _P4) \
1652 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, RTLIL::SigBit sig4) { \
1653 RTLIL::Cell *cell = addCell(name, _type); \
1654 cell->setPort("\\" #_P1, sig1); \
1655 cell->setPort("\\" #_P2, sig2); \
1656 cell->setPort("\\" #_P3, sig3); \
1657 cell->setPort("\\" #_P4, sig4); \
1658 return cell; \
1659 } \
1660 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3) { \
1661 RTLIL::SigBit sig4 = addWire(NEW_ID); \
1662 add ## _func(name, sig1, sig2, sig3, sig4); \
1663 return sig4; \
1664 }
1665 #define DEF_METHOD_5(_func, _type, _P1, _P2, _P3, _P4, _P5) \
1666 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, RTLIL::SigBit sig4, RTLIL::SigBit sig5) { \
1667 RTLIL::Cell *cell = addCell(name, _type); \
1668 cell->setPort("\\" #_P1, sig1); \
1669 cell->setPort("\\" #_P2, sig2); \
1670 cell->setPort("\\" #_P3, sig3); \
1671 cell->setPort("\\" #_P4, sig4); \
1672 cell->setPort("\\" #_P5, sig5); \
1673 return cell; \
1674 } \
1675 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, RTLIL::SigBit sig4) { \
1676 RTLIL::SigBit sig5 = addWire(NEW_ID); \
1677 add ## _func(name, sig1, sig2, sig3, sig4, sig5); \
1678 return sig5; \
1679 }
1680 DEF_METHOD_2(NotGate, "$_NOT_", A, Y)
1681 DEF_METHOD_3(AndGate, "$_AND_", A, B, Y)
1682 DEF_METHOD_3(NandGate, "$_NAND_", A, B, Y)
1683 DEF_METHOD_3(OrGate, "$_OR_", A, B, Y)
1684 DEF_METHOD_3(NorGate, "$_NOR_", A, B, Y)
1685 DEF_METHOD_3(XorGate, "$_XOR_", A, B, Y)
1686 DEF_METHOD_3(XnorGate, "$_XNOR_", A, B, Y)
1687 DEF_METHOD_4(MuxGate, "$_MUX_", A, B, S, Y)
1688 DEF_METHOD_4(Aoi3Gate, "$_AOI3_", A, B, C, Y)
1689 DEF_METHOD_4(Oai3Gate, "$_OAI3_", A, B, C, Y)
1690 DEF_METHOD_5(Aoi4Gate, "$_AOI4_", A, B, C, D, Y)
1691 DEF_METHOD_5(Oai4Gate, "$_OAI4_", A, B, C, D, Y)
1692 #undef DEF_METHOD_2
1693 #undef DEF_METHOD_3
1694 #undef DEF_METHOD_4
1695 #undef DEF_METHOD_5
1696
1697 RTLIL::Cell* RTLIL::Module::addPow(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool a_signed, bool b_signed)
1698 {
1699 RTLIL::Cell *cell = addCell(name, "$pow");
1700 cell->parameters["\\A_SIGNED"] = a_signed;
1701 cell->parameters["\\B_SIGNED"] = b_signed;
1702 cell->parameters["\\A_WIDTH"] = sig_a.size();
1703 cell->parameters["\\B_WIDTH"] = sig_b.size();
1704 cell->parameters["\\Y_WIDTH"] = sig_y.size();
1705 cell->setPort("\\A", sig_a);
1706 cell->setPort("\\B", sig_b);
1707 cell->setPort("\\Y", sig_y);
1708 return cell;
1709 }
1710
1711 RTLIL::Cell* RTLIL::Module::addSlice(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, RTLIL::Const offset)
1712 {
1713 RTLIL::Cell *cell = addCell(name, "$slice");
1714 cell->parameters["\\A_WIDTH"] = sig_a.size();
1715 cell->parameters["\\Y_WIDTH"] = sig_y.size();
1716 cell->parameters["\\OFFSET"] = offset;
1717 cell->setPort("\\A", sig_a);
1718 cell->setPort("\\Y", sig_y);
1719 return cell;
1720 }
1721
1722 RTLIL::Cell* RTLIL::Module::addConcat(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y)
1723 {
1724 RTLIL::Cell *cell = addCell(name, "$concat");
1725 cell->parameters["\\A_WIDTH"] = sig_a.size();
1726 cell->parameters["\\B_WIDTH"] = sig_b.size();
1727 cell->setPort("\\A", sig_a);
1728 cell->setPort("\\B", sig_b);
1729 cell->setPort("\\Y", sig_y);
1730 return cell;
1731 }
1732
1733 RTLIL::Cell* RTLIL::Module::addLut(RTLIL::IdString name, RTLIL::SigSpec sig_i, RTLIL::SigSpec sig_o, RTLIL::Const lut)
1734 {
1735 RTLIL::Cell *cell = addCell(name, "$lut");
1736 cell->parameters["\\LUT"] = lut;
1737 cell->parameters["\\WIDTH"] = sig_i.size();
1738 cell->setPort("\\A", sig_i);
1739 cell->setPort("\\Y", sig_o);
1740 return cell;
1741 }
1742
1743 RTLIL::Cell* RTLIL::Module::addAssert(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en)
1744 {
1745 RTLIL::Cell *cell = addCell(name, "$assert");
1746 cell->setPort("\\A", sig_a);
1747 cell->setPort("\\EN", sig_en);
1748 return cell;
1749 }
1750
1751 RTLIL::Cell* RTLIL::Module::addEquiv(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y)
1752 {
1753 RTLIL::Cell *cell = addCell(name, "$equiv");
1754 cell->setPort("\\A", sig_a);
1755 cell->setPort("\\B", sig_b);
1756 cell->setPort("\\Y", sig_y);
1757 return cell;
1758 }
1759
1760 RTLIL::Cell* RTLIL::Module::addSr(RTLIL::IdString name, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr, RTLIL::SigSpec sig_q, bool set_polarity, bool clr_polarity)
1761 {
1762 RTLIL::Cell *cell = addCell(name, "$sr");
1763 cell->parameters["\\SET_POLARITY"] = set_polarity;
1764 cell->parameters["\\CLR_POLARITY"] = clr_polarity;
1765 cell->parameters["\\WIDTH"] = sig_q.size();
1766 cell->setPort("\\SET", sig_set);
1767 cell->setPort("\\CLR", sig_clr);
1768 cell->setPort("\\Q", sig_q);
1769 return cell;
1770 }
1771
1772 RTLIL::Cell* RTLIL::Module::addDff(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity)
1773 {
1774 RTLIL::Cell *cell = addCell(name, "$dff");
1775 cell->parameters["\\CLK_POLARITY"] = clk_polarity;
1776 cell->parameters["\\WIDTH"] = sig_q.size();
1777 cell->setPort("\\CLK", sig_clk);
1778 cell->setPort("\\D", sig_d);
1779 cell->setPort("\\Q", sig_q);
1780 return cell;
1781 }
1782
1783 RTLIL::Cell* RTLIL::Module::addDffe(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, bool en_polarity)
1784 {
1785 RTLIL::Cell *cell = addCell(name, "$dffe");
1786 cell->parameters["\\CLK_POLARITY"] = clk_polarity;
1787 cell->parameters["\\EN_POLARITY"] = en_polarity;
1788 cell->parameters["\\WIDTH"] = sig_q.size();
1789 cell->setPort("\\CLK", sig_clk);
1790 cell->setPort("\\EN", sig_en);
1791 cell->setPort("\\D", sig_d);
1792 cell->setPort("\\Q", sig_q);
1793 return cell;
1794 }
1795
1796 RTLIL::Cell* RTLIL::Module::addDffsr(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
1797 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity)
1798 {
1799 RTLIL::Cell *cell = addCell(name, "$dffsr");
1800 cell->parameters["\\CLK_POLARITY"] = clk_polarity;
1801 cell->parameters["\\SET_POLARITY"] = set_polarity;
1802 cell->parameters["\\CLR_POLARITY"] = clr_polarity;
1803 cell->parameters["\\WIDTH"] = sig_q.size();
1804 cell->setPort("\\CLK", sig_clk);
1805 cell->setPort("\\SET", sig_set);
1806 cell->setPort("\\CLR", sig_clr);
1807 cell->setPort("\\D", sig_d);
1808 cell->setPort("\\Q", sig_q);
1809 return cell;
1810 }
1811
1812 RTLIL::Cell* RTLIL::Module::addAdff(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_arst, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q,
1813 RTLIL::Const arst_value, bool clk_polarity, bool arst_polarity)
1814 {
1815 RTLIL::Cell *cell = addCell(name, "$adff");
1816 cell->parameters["\\CLK_POLARITY"] = clk_polarity;
1817 cell->parameters["\\ARST_POLARITY"] = arst_polarity;
1818 cell->parameters["\\ARST_VALUE"] = arst_value;
1819 cell->parameters["\\WIDTH"] = sig_q.size();
1820 cell->setPort("\\CLK", sig_clk);
1821 cell->setPort("\\ARST", sig_arst);
1822 cell->setPort("\\D", sig_d);
1823 cell->setPort("\\Q", sig_q);
1824 return cell;
1825 }
1826
1827 RTLIL::Cell* RTLIL::Module::addDlatch(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity)
1828 {
1829 RTLIL::Cell *cell = addCell(name, "$dlatch");
1830 cell->parameters["\\EN_POLARITY"] = en_polarity;
1831 cell->parameters["\\WIDTH"] = sig_q.size();
1832 cell->setPort("\\EN", sig_en);
1833 cell->setPort("\\D", sig_d);
1834 cell->setPort("\\Q", sig_q);
1835 return cell;
1836 }
1837
1838 RTLIL::Cell* RTLIL::Module::addDlatchsr(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
1839 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity, bool set_polarity, bool clr_polarity)
1840 {
1841 RTLIL::Cell *cell = addCell(name, "$dlatchsr");
1842 cell->parameters["\\EN_POLARITY"] = en_polarity;
1843 cell->parameters["\\SET_POLARITY"] = set_polarity;
1844 cell->parameters["\\CLR_POLARITY"] = clr_polarity;
1845 cell->parameters["\\WIDTH"] = sig_q.size();
1846 cell->setPort("\\EN", sig_en);
1847 cell->setPort("\\SET", sig_set);
1848 cell->setPort("\\CLR", sig_clr);
1849 cell->setPort("\\D", sig_d);
1850 cell->setPort("\\Q", sig_q);
1851 return cell;
1852 }
1853
1854 RTLIL::Cell* RTLIL::Module::addDffGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity)
1855 {
1856 RTLIL::Cell *cell = addCell(name, stringf("$_DFF_%c_", clk_polarity ? 'P' : 'N'));
1857 cell->setPort("\\C", sig_clk);
1858 cell->setPort("\\D", sig_d);
1859 cell->setPort("\\Q", sig_q);
1860 return cell;
1861 }
1862
1863 RTLIL::Cell* RTLIL::Module::addDffeGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, bool en_polarity)
1864 {
1865 RTLIL::Cell *cell = addCell(name, stringf("$_DFFE_%c%c_", clk_polarity ? 'P' : 'N', en_polarity ? 'P' : 'N'));
1866 cell->setPort("\\C", sig_clk);
1867 cell->setPort("\\E", sig_en);
1868 cell->setPort("\\D", sig_d);
1869 cell->setPort("\\Q", sig_q);
1870 return cell;
1871 }
1872
1873 RTLIL::Cell* RTLIL::Module::addDffsrGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
1874 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity)
1875 {
1876 RTLIL::Cell *cell = addCell(name, stringf("$_DFFSR_%c%c%c_", clk_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N'));
1877 cell->setPort("\\C", sig_clk);
1878 cell->setPort("\\S", sig_set);
1879 cell->setPort("\\R", sig_clr);
1880 cell->setPort("\\D", sig_d);
1881 cell->setPort("\\Q", sig_q);
1882 return cell;
1883 }
1884
1885 RTLIL::Cell* RTLIL::Module::addAdffGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_arst, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q,
1886 bool arst_value, bool clk_polarity, bool arst_polarity)
1887 {
1888 RTLIL::Cell *cell = addCell(name, stringf("$_DFF_%c%c%c_", clk_polarity ? 'P' : 'N', arst_polarity ? 'P' : 'N', arst_value ? '1' : '0'));
1889 cell->setPort("\\C", sig_clk);
1890 cell->setPort("\\R", sig_arst);
1891 cell->setPort("\\D", sig_d);
1892 cell->setPort("\\Q", sig_q);
1893 return cell;
1894 }
1895
1896 RTLIL::Cell* RTLIL::Module::addDlatchGate(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity)
1897 {
1898 RTLIL::Cell *cell = addCell(name, stringf("$_DLATCH_%c_", en_polarity ? 'P' : 'N'));
1899 cell->setPort("\\E", sig_en);
1900 cell->setPort("\\D", sig_d);
1901 cell->setPort("\\Q", sig_q);
1902 return cell;
1903 }
1904
1905 RTLIL::Cell* RTLIL::Module::addDlatchsrGate(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
1906 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity, bool set_polarity, bool clr_polarity)
1907 {
1908 RTLIL::Cell *cell = addCell(name, stringf("$_DLATCHSR_%c%c%c_", en_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N'));
1909 cell->setPort("\\E", sig_en);
1910 cell->setPort("\\S", sig_set);
1911 cell->setPort("\\R", sig_clr);
1912 cell->setPort("\\D", sig_d);
1913 cell->setPort("\\Q", sig_q);
1914 return cell;
1915 }
1916
1917
1918 RTLIL::Wire::Wire()
1919 {
1920 static unsigned int hashidx_count = 123456789;
1921 hashidx_count = mkhash_xorshift(hashidx_count);
1922 hashidx_ = hashidx_count;
1923
1924 module = nullptr;
1925 width = 1;
1926 start_offset = 0;
1927 port_id = 0;
1928 port_input = false;
1929 port_output = false;
1930 upto = false;
1931 }
1932
1933 RTLIL::Memory::Memory()
1934 {
1935 static unsigned int hashidx_count = 123456789;
1936 hashidx_count = mkhash_xorshift(hashidx_count);
1937 hashidx_ = hashidx_count;
1938
1939 width = 1;
1940 size = 0;
1941 }
1942
1943 RTLIL::Cell::Cell() : module(nullptr)
1944 {
1945 static unsigned int hashidx_count = 123456789;
1946 hashidx_count = mkhash_xorshift(hashidx_count);
1947 hashidx_ = hashidx_count;
1948
1949 // log("#memtrace# %p\n", this);
1950 memhasher();
1951 }
1952
1953 bool RTLIL::Cell::hasPort(RTLIL::IdString portname) const
1954 {
1955 return connections_.count(portname) != 0;
1956 }
1957
1958 void RTLIL::Cell::unsetPort(RTLIL::IdString portname)
1959 {
1960 RTLIL::SigSpec signal;
1961 auto conn_it = connections_.find(portname);
1962
1963 if (conn_it != connections_.end())
1964 {
1965 for (auto mon : module->monitors)
1966 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
1967
1968 if (module->design)
1969 for (auto mon : module->design->monitors)
1970 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
1971
1972 if (yosys_xtrace) {
1973 log("#X# Unconnect %s.%s.%s\n", log_id(this->module), log_id(this), log_id(portname));
1974 log_backtrace("-X- ", yosys_xtrace-1);
1975 }
1976
1977 connections_.erase(conn_it);
1978 }
1979 }
1980
1981 void RTLIL::Cell::setPort(RTLIL::IdString portname, RTLIL::SigSpec signal)
1982 {
1983 auto conn_it = connections_.find(portname);
1984
1985 if (conn_it == connections_.end()) {
1986 connections_[portname] = RTLIL::SigSpec();
1987 conn_it = connections_.find(portname);
1988 log_assert(conn_it != connections_.end());
1989 } else
1990 if (conn_it->second == signal)
1991 return;
1992
1993 for (auto mon : module->monitors)
1994 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
1995
1996 if (module->design)
1997 for (auto mon : module->design->monitors)
1998 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
1999
2000 if (yosys_xtrace) {
2001 log("#X# Connect %s.%s.%s = %s (%d)\n", log_id(this->module), log_id(this), log_id(portname), log_signal(signal), GetSize(signal));
2002 log_backtrace("-X- ", yosys_xtrace-1);
2003 }
2004
2005 conn_it->second = signal;
2006 }
2007
2008 const RTLIL::SigSpec &RTLIL::Cell::getPort(RTLIL::IdString portname) const
2009 {
2010 return connections_.at(portname);
2011 }
2012
2013 const dict<RTLIL::IdString, RTLIL::SigSpec> &RTLIL::Cell::connections() const
2014 {
2015 return connections_;
2016 }
2017
2018 bool RTLIL::Cell::known() const
2019 {
2020 if (yosys_celltypes.cell_known(type))
2021 return true;
2022 if (module && module->design && module->design->module(type))
2023 return true;
2024 return false;
2025 }
2026
2027 bool RTLIL::Cell::input(RTLIL::IdString portname) const
2028 {
2029 if (yosys_celltypes.cell_known(type))
2030 return yosys_celltypes.cell_input(type, portname);
2031 if (module && module->design) {
2032 RTLIL::Module *m = module->design->module(type);
2033 RTLIL::Wire *w = m ? m->wire(portname) : nullptr;
2034 return w && w->port_input;
2035 }
2036 return false;
2037 }
2038
2039 bool RTLIL::Cell::output(RTLIL::IdString portname) const
2040 {
2041 if (yosys_celltypes.cell_known(type))
2042 return yosys_celltypes.cell_output(type, portname);
2043 if (module && module->design) {
2044 RTLIL::Module *m = module->design->module(type);
2045 RTLIL::Wire *w = m ? m->wire(portname) : nullptr;
2046 return w && w->port_output;
2047 }
2048 return false;
2049 }
2050
2051 bool RTLIL::Cell::hasParam(RTLIL::IdString paramname) const
2052 {
2053 return parameters.count(paramname) != 0;
2054 }
2055
2056 void RTLIL::Cell::unsetParam(RTLIL::IdString paramname)
2057 {
2058 parameters.erase(paramname);
2059 }
2060
2061 void RTLIL::Cell::setParam(RTLIL::IdString paramname, RTLIL::Const value)
2062 {
2063 parameters[paramname] = value;
2064 }
2065
2066 const RTLIL::Const &RTLIL::Cell::getParam(RTLIL::IdString paramname) const
2067 {
2068 return parameters.at(paramname);
2069 }
2070
2071 void RTLIL::Cell::sort()
2072 {
2073 connections_.sort(sort_by_id_str());
2074 parameters.sort(sort_by_id_str());
2075 attributes.sort(sort_by_id_str());
2076 }
2077
2078 void RTLIL::Cell::check()
2079 {
2080 #ifndef NDEBUG
2081 InternalCellChecker checker(NULL, this);
2082 checker.check();
2083 #endif
2084 }
2085
2086 void RTLIL::Cell::fixup_parameters(bool set_a_signed, bool set_b_signed)
2087 {
2088 if (type.substr(0, 1) != "$" || type.substr(0, 2) == "$_" || type.substr(0, 8) == "$paramod" ||
2089 type.substr(0, 9) == "$verific$" || type.substr(0, 7) == "$array:" || type.substr(0, 8) == "$extern:")
2090 return;
2091
2092 if (type == "$mux" || type == "$pmux") {
2093 parameters["\\WIDTH"] = GetSize(connections_["\\Y"]);
2094 if (type == "$pmux")
2095 parameters["\\S_WIDTH"] = GetSize(connections_["\\S"]);
2096 check();
2097 return;
2098 }
2099
2100 if (type == "$lut") {
2101 parameters["\\WIDTH"] = GetSize(connections_["\\A"]);
2102 return;
2103 }
2104
2105 if (type == "$fa") {
2106 parameters["\\WIDTH"] = GetSize(connections_["\\Y"]);
2107 return;
2108 }
2109
2110 if (type == "$lcu") {
2111 parameters["\\WIDTH"] = GetSize(connections_["\\CO"]);
2112 return;
2113 }
2114
2115 bool signedness_ab = !type.in("$slice", "$concat", "$macc");
2116
2117 if (connections_.count("\\A")) {
2118 if (signedness_ab) {
2119 if (set_a_signed)
2120 parameters["\\A_SIGNED"] = true;
2121 else if (parameters.count("\\A_SIGNED") == 0)
2122 parameters["\\A_SIGNED"] = false;
2123 }
2124 parameters["\\A_WIDTH"] = GetSize(connections_["\\A"]);
2125 }
2126
2127 if (connections_.count("\\B")) {
2128 if (signedness_ab) {
2129 if (set_b_signed)
2130 parameters["\\B_SIGNED"] = true;
2131 else if (parameters.count("\\B_SIGNED") == 0)
2132 parameters["\\B_SIGNED"] = false;
2133 }
2134 parameters["\\B_WIDTH"] = GetSize(connections_["\\B"]);
2135 }
2136
2137 if (connections_.count("\\Y"))
2138 parameters["\\Y_WIDTH"] = GetSize(connections_["\\Y"]);
2139
2140 check();
2141 }
2142
2143 RTLIL::SigChunk::SigChunk()
2144 {
2145 wire = NULL;
2146 width = 0;
2147 offset = 0;
2148 }
2149
2150 RTLIL::SigChunk::SigChunk(const RTLIL::Const &value)
2151 {
2152 wire = NULL;
2153 data = value.bits;
2154 width = GetSize(data);
2155 offset = 0;
2156 }
2157
2158 RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire)
2159 {
2160 log_assert(wire != nullptr);
2161 this->wire = wire;
2162 this->width = wire->width;
2163 this->offset = 0;
2164 }
2165
2166 RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire, int offset, int width)
2167 {
2168 log_assert(wire != nullptr);
2169 this->wire = wire;
2170 this->width = width;
2171 this->offset = offset;
2172 }
2173
2174 RTLIL::SigChunk::SigChunk(const std::string &str)
2175 {
2176 wire = NULL;
2177 data = RTLIL::Const(str).bits;
2178 width = GetSize(data);
2179 offset = 0;
2180 }
2181
2182 RTLIL::SigChunk::SigChunk(int val, int width)
2183 {
2184 wire = NULL;
2185 data = RTLIL::Const(val, width).bits;
2186 this->width = GetSize(data);
2187 offset = 0;
2188 }
2189
2190 RTLIL::SigChunk::SigChunk(RTLIL::State bit, int width)
2191 {
2192 wire = NULL;
2193 data = RTLIL::Const(bit, width).bits;
2194 this->width = GetSize(data);
2195 offset = 0;
2196 }
2197
2198 RTLIL::SigChunk::SigChunk(RTLIL::SigBit bit)
2199 {
2200 wire = bit.wire;
2201 offset = 0;
2202 if (wire == NULL)
2203 data = RTLIL::Const(bit.data).bits;
2204 else
2205 offset = bit.offset;
2206 width = 1;
2207 }
2208
2209 RTLIL::SigChunk RTLIL::SigChunk::extract(int offset, int length) const
2210 {
2211 RTLIL::SigChunk ret;
2212 if (wire) {
2213 ret.wire = wire;
2214 ret.offset = this->offset + offset;
2215 ret.width = length;
2216 } else {
2217 for (int i = 0; i < length; i++)
2218 ret.data.push_back(data[offset+i]);
2219 ret.width = length;
2220 }
2221 return ret;
2222 }
2223
2224 bool RTLIL::SigChunk::operator <(const RTLIL::SigChunk &other) const
2225 {
2226 if (wire && other.wire)
2227 if (wire->name != other.wire->name)
2228 return wire->name < other.wire->name;
2229
2230 if (wire != other.wire)
2231 return wire < other.wire;
2232
2233 if (offset != other.offset)
2234 return offset < other.offset;
2235
2236 if (width != other.width)
2237 return width < other.width;
2238
2239 return data < other.data;
2240 }
2241
2242 bool RTLIL::SigChunk::operator ==(const RTLIL::SigChunk &other) const
2243 {
2244 return wire == other.wire && width == other.width && offset == other.offset && data == other.data;
2245 }
2246
2247 bool RTLIL::SigChunk::operator !=(const RTLIL::SigChunk &other) const
2248 {
2249 if (*this == other)
2250 return false;
2251 return true;
2252 }
2253
2254 RTLIL::SigSpec::SigSpec()
2255 {
2256 width_ = 0;
2257 hash_ = 0;
2258 }
2259
2260 RTLIL::SigSpec::SigSpec(const RTLIL::SigSpec &other)
2261 {
2262 *this = other;
2263 }
2264
2265 RTLIL::SigSpec::SigSpec(std::initializer_list<RTLIL::SigSpec> parts)
2266 {
2267 cover("kernel.rtlil.sigspec.init.list");
2268
2269 width_ = 0;
2270 hash_ = 0;
2271
2272 std::vector<RTLIL::SigSpec> parts_vec(parts.begin(), parts.end());
2273 for (auto it = parts_vec.rbegin(); it != parts_vec.rend(); it++)
2274 append(*it);
2275 }
2276
2277 const RTLIL::SigSpec &RTLIL::SigSpec::operator=(const RTLIL::SigSpec &other)
2278 {
2279 cover("kernel.rtlil.sigspec.assign");
2280
2281 width_ = other.width_;
2282 hash_ = other.hash_;
2283 chunks_ = other.chunks_;
2284 bits_.clear();
2285
2286 if (!other.bits_.empty())
2287 {
2288 RTLIL::SigChunk *last = NULL;
2289 int last_end_offset = 0;
2290
2291 for (auto &bit : other.bits_) {
2292 if (last && bit.wire == last->wire) {
2293 if (bit.wire == NULL) {
2294 last->data.push_back(bit.data);
2295 last->width++;
2296 continue;
2297 } else if (last_end_offset == bit.offset) {
2298 last_end_offset++;
2299 last->width++;
2300 continue;
2301 }
2302 }
2303 chunks_.push_back(bit);
2304 last = &chunks_.back();
2305 last_end_offset = bit.offset + 1;
2306 }
2307
2308 check();
2309 }
2310
2311 return *this;
2312 }
2313
2314 RTLIL::SigSpec::SigSpec(const RTLIL::Const &value)
2315 {
2316 cover("kernel.rtlil.sigspec.init.const");
2317
2318 chunks_.push_back(RTLIL::SigChunk(value));
2319 width_ = chunks_.back().width;
2320 hash_ = 0;
2321 check();
2322 }
2323
2324 RTLIL::SigSpec::SigSpec(const RTLIL::SigChunk &chunk)
2325 {
2326 cover("kernel.rtlil.sigspec.init.chunk");
2327
2328 chunks_.push_back(chunk);
2329 width_ = chunks_.back().width;
2330 hash_ = 0;
2331 check();
2332 }
2333
2334 RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire)
2335 {
2336 cover("kernel.rtlil.sigspec.init.wire");
2337
2338 chunks_.push_back(RTLIL::SigChunk(wire));
2339 width_ = chunks_.back().width;
2340 hash_ = 0;
2341 check();
2342 }
2343
2344 RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire, int offset, int width)
2345 {
2346 cover("kernel.rtlil.sigspec.init.wire_part");
2347
2348 chunks_.push_back(RTLIL::SigChunk(wire, offset, width));
2349 width_ = chunks_.back().width;
2350 hash_ = 0;
2351 check();
2352 }
2353
2354 RTLIL::SigSpec::SigSpec(const std::string &str)
2355 {
2356 cover("kernel.rtlil.sigspec.init.str");
2357
2358 chunks_.push_back(RTLIL::SigChunk(str));
2359 width_ = chunks_.back().width;
2360 hash_ = 0;
2361 check();
2362 }
2363
2364 RTLIL::SigSpec::SigSpec(int val, int width)
2365 {
2366 cover("kernel.rtlil.sigspec.init.int");
2367
2368 chunks_.push_back(RTLIL::SigChunk(val, width));
2369 width_ = width;
2370 hash_ = 0;
2371 check();
2372 }
2373
2374 RTLIL::SigSpec::SigSpec(RTLIL::State bit, int width)
2375 {
2376 cover("kernel.rtlil.sigspec.init.state");
2377
2378 chunks_.push_back(RTLIL::SigChunk(bit, width));
2379 width_ = width;
2380 hash_ = 0;
2381 check();
2382 }
2383
2384 RTLIL::SigSpec::SigSpec(RTLIL::SigBit bit, int width)
2385 {
2386 cover("kernel.rtlil.sigspec.init.bit");
2387
2388 if (bit.wire == NULL)
2389 chunks_.push_back(RTLIL::SigChunk(bit.data, width));
2390 else
2391 for (int i = 0; i < width; i++)
2392 chunks_.push_back(bit);
2393 width_ = width;
2394 hash_ = 0;
2395 check();
2396 }
2397
2398 RTLIL::SigSpec::SigSpec(std::vector<RTLIL::SigChunk> chunks)
2399 {
2400 cover("kernel.rtlil.sigspec.init.stdvec_chunks");
2401
2402 width_ = 0;
2403 hash_ = 0;
2404 for (auto &c : chunks)
2405 append(c);
2406 check();
2407 }
2408
2409 RTLIL::SigSpec::SigSpec(std::vector<RTLIL::SigBit> bits)
2410 {
2411 cover("kernel.rtlil.sigspec.init.stdvec_bits");
2412
2413 width_ = 0;
2414 hash_ = 0;
2415 for (auto &bit : bits)
2416 append_bit(bit);
2417 check();
2418 }
2419
2420 RTLIL::SigSpec::SigSpec(pool<RTLIL::SigBit> bits)
2421 {
2422 cover("kernel.rtlil.sigspec.init.pool_bits");
2423
2424 width_ = 0;
2425 hash_ = 0;
2426 for (auto &bit : bits)
2427 append_bit(bit);
2428 check();
2429 }
2430
2431 RTLIL::SigSpec::SigSpec(std::set<RTLIL::SigBit> bits)
2432 {
2433 cover("kernel.rtlil.sigspec.init.stdset_bits");
2434
2435 width_ = 0;
2436 hash_ = 0;
2437 for (auto &bit : bits)
2438 append_bit(bit);
2439 check();
2440 }
2441
2442 RTLIL::SigSpec::SigSpec(bool bit)
2443 {
2444 cover("kernel.rtlil.sigspec.init.bool");
2445
2446 width_ = 0;
2447 hash_ = 0;
2448 append_bit(bit);
2449 check();
2450 }
2451
2452 void RTLIL::SigSpec::pack() const
2453 {
2454 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
2455
2456 if (that->bits_.empty())
2457 return;
2458
2459 cover("kernel.rtlil.sigspec.convert.pack");
2460 log_assert(that->chunks_.empty());
2461
2462 std::vector<RTLIL::SigBit> old_bits;
2463 old_bits.swap(that->bits_);
2464
2465 RTLIL::SigChunk *last = NULL;
2466 int last_end_offset = 0;
2467
2468 for (auto &bit : old_bits) {
2469 if (last && bit.wire == last->wire) {
2470 if (bit.wire == NULL) {
2471 last->data.push_back(bit.data);
2472 last->width++;
2473 continue;
2474 } else if (last_end_offset == bit.offset) {
2475 last_end_offset++;
2476 last->width++;
2477 continue;
2478 }
2479 }
2480 that->chunks_.push_back(bit);
2481 last = &that->chunks_.back();
2482 last_end_offset = bit.offset + 1;
2483 }
2484
2485 check();
2486 }
2487
2488 void RTLIL::SigSpec::unpack() const
2489 {
2490 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
2491
2492 if (that->chunks_.empty())
2493 return;
2494
2495 cover("kernel.rtlil.sigspec.convert.unpack");
2496 log_assert(that->bits_.empty());
2497
2498 that->bits_.reserve(that->width_);
2499 for (auto &c : that->chunks_)
2500 for (int i = 0; i < c.width; i++)
2501 that->bits_.push_back(RTLIL::SigBit(c, i));
2502
2503 that->chunks_.clear();
2504 that->hash_ = 0;
2505 }
2506
2507 void RTLIL::SigSpec::updhash() const
2508 {
2509 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
2510
2511 if (that->hash_ != 0)
2512 return;
2513
2514 cover("kernel.rtlil.sigspec.hash");
2515 that->pack();
2516
2517 that->hash_ = mkhash_init;
2518 for (auto &c : that->chunks_)
2519 if (c.wire == NULL) {
2520 for (auto &v : c.data)
2521 that->hash_ = mkhash(that->hash_, v);
2522 } else {
2523 that->hash_ = mkhash(that->hash_, c.wire->name.index_);
2524 that->hash_ = mkhash(that->hash_, c.offset);
2525 that->hash_ = mkhash(that->hash_, c.width);
2526 }
2527
2528 if (that->hash_ == 0)
2529 that->hash_ = 1;
2530 }
2531
2532 void RTLIL::SigSpec::sort()
2533 {
2534 unpack();
2535 cover("kernel.rtlil.sigspec.sort");
2536 std::sort(bits_.begin(), bits_.end());
2537 }
2538
2539 void RTLIL::SigSpec::sort_and_unify()
2540 {
2541 cover("kernel.rtlil.sigspec.sort_and_unify");
2542 *this = this->to_sigbit_set();
2543 }
2544
2545 void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with)
2546 {
2547 replace(pattern, with, this);
2548 }
2549
2550 void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with, RTLIL::SigSpec *other) const
2551 {
2552 log_assert(pattern.width_ == with.width_);
2553
2554 pattern.unpack();
2555 with.unpack();
2556
2557 dict<RTLIL::SigBit, RTLIL::SigBit> rules;
2558
2559 for (int i = 0; i < GetSize(pattern.bits_); i++)
2560 if (pattern.bits_[i].wire != NULL)
2561 rules[pattern.bits_[i]] = with.bits_[i];
2562
2563 replace(rules, other);
2564 }
2565
2566 void RTLIL::SigSpec::replace(const dict<RTLIL::SigBit, RTLIL::SigBit> &rules)
2567 {
2568 replace(rules, this);
2569 }
2570
2571 void RTLIL::SigSpec::replace(const dict<RTLIL::SigBit, RTLIL::SigBit> &rules, RTLIL::SigSpec *other) const
2572 {
2573 cover("kernel.rtlil.sigspec.replace_dict");
2574
2575 log_assert(other != NULL);
2576 log_assert(width_ == other->width_);
2577
2578 unpack();
2579 other->unpack();
2580
2581 for (int i = 0; i < GetSize(bits_); i++) {
2582 auto it = rules.find(bits_[i]);
2583 if (it != rules.end())
2584 other->bits_[i] = it->second;
2585 }
2586
2587 other->check();
2588 }
2589
2590 void RTLIL::SigSpec::replace(const std::map<RTLIL::SigBit, RTLIL::SigBit> &rules)
2591 {
2592 replace(rules, this);
2593 }
2594
2595 void RTLIL::SigSpec::replace(const std::map<RTLIL::SigBit, RTLIL::SigBit> &rules, RTLIL::SigSpec *other) const
2596 {
2597 cover("kernel.rtlil.sigspec.replace_map");
2598
2599 log_assert(other != NULL);
2600 log_assert(width_ == other->width_);
2601
2602 unpack();
2603 other->unpack();
2604
2605 for (int i = 0; i < GetSize(bits_); i++) {
2606 auto it = rules.find(bits_[i]);
2607 if (it != rules.end())
2608 other->bits_[i] = it->second;
2609 }
2610
2611 other->check();
2612 }
2613
2614 void RTLIL::SigSpec::remove(const RTLIL::SigSpec &pattern)
2615 {
2616 remove2(pattern, NULL);
2617 }
2618
2619 void RTLIL::SigSpec::remove(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other) const
2620 {
2621 RTLIL::SigSpec tmp = *this;
2622 tmp.remove2(pattern, other);
2623 }
2624
2625 void RTLIL::SigSpec::remove2(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other)
2626 {
2627 pool<RTLIL::SigBit> pattern_bits = pattern.to_sigbit_pool();
2628 remove2(pattern_bits, other);
2629 }
2630
2631 void RTLIL::SigSpec::remove(const pool<RTLIL::SigBit> &pattern)
2632 {
2633 remove2(pattern, NULL);
2634 }
2635
2636 void RTLIL::SigSpec::remove(const pool<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other) const
2637 {
2638 RTLIL::SigSpec tmp = *this;
2639 tmp.remove2(pattern, other);
2640 }
2641
2642 void RTLIL::SigSpec::remove2(const pool<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other)
2643 {
2644 if (other)
2645 cover("kernel.rtlil.sigspec.remove_other");
2646 else
2647 cover("kernel.rtlil.sigspec.remove");
2648
2649 unpack();
2650
2651 if (other != NULL) {
2652 log_assert(width_ == other->width_);
2653 other->unpack();
2654 }
2655
2656 std::vector<RTLIL::SigBit> new_bits, new_other_bits;
2657
2658 new_bits.resize(GetSize(bits_));
2659 if (other != NULL)
2660 new_other_bits.resize(GetSize(bits_));
2661
2662 int k = 0;
2663 for (int i = 0; i < GetSize(bits_); i++) {
2664 if (bits_[i].wire != NULL && pattern.count(bits_[i]))
2665 continue;
2666 if (other != NULL)
2667 new_other_bits[k] = other->bits_[i];
2668 new_bits[k++] = bits_[i];
2669 }
2670
2671 new_bits.resize(k);
2672 if (other != NULL)
2673 new_other_bits.resize(k);
2674
2675 bits_.swap(new_bits);
2676 width_ = GetSize(bits_);
2677
2678 if (other != NULL) {
2679 other->bits_.swap(new_other_bits);
2680 other->width_ = GetSize(other->bits_);
2681 }
2682
2683 check();
2684 }
2685
2686 RTLIL::SigSpec RTLIL::SigSpec::extract(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec *other) const
2687 {
2688 pool<RTLIL::SigBit> pattern_bits = pattern.to_sigbit_pool();
2689 return extract(pattern_bits, other);
2690 }
2691
2692 RTLIL::SigSpec RTLIL::SigSpec::extract(const pool<RTLIL::SigBit> &pattern, const RTLIL::SigSpec *other) const
2693 {
2694 if (other)
2695 cover("kernel.rtlil.sigspec.extract_other");
2696 else
2697 cover("kernel.rtlil.sigspec.extract");
2698
2699 log_assert(other == NULL || width_ == other->width_);
2700
2701 std::vector<RTLIL::SigBit> bits_match = to_sigbit_vector();
2702 RTLIL::SigSpec ret;
2703
2704 if (other) {
2705 std::vector<RTLIL::SigBit> bits_other = other->to_sigbit_vector();
2706 for (int i = 0; i < width_; i++)
2707 if (bits_match[i].wire && pattern.count(bits_match[i]))
2708 ret.append_bit(bits_other[i]);
2709 } else {
2710 for (int i = 0; i < width_; i++)
2711 if (bits_match[i].wire && pattern.count(bits_match[i]))
2712 ret.append_bit(bits_match[i]);
2713 }
2714
2715 ret.check();
2716 return ret;
2717 }
2718
2719 void RTLIL::SigSpec::replace(int offset, const RTLIL::SigSpec &with)
2720 {
2721 cover("kernel.rtlil.sigspec.replace_pos");
2722
2723 unpack();
2724 with.unpack();
2725
2726 log_assert(offset >= 0);
2727 log_assert(with.width_ >= 0);
2728 log_assert(offset+with.width_ <= width_);
2729
2730 for (int i = 0; i < with.width_; i++)
2731 bits_.at(offset + i) = with.bits_.at(i);
2732
2733 check();
2734 }
2735
2736 void RTLIL::SigSpec::remove_const()
2737 {
2738 if (packed())
2739 {
2740 cover("kernel.rtlil.sigspec.remove_const.packed");
2741
2742 std::vector<RTLIL::SigChunk> new_chunks;
2743 new_chunks.reserve(GetSize(chunks_));
2744
2745 width_ = 0;
2746 for (auto &chunk : chunks_)
2747 if (chunk.wire != NULL) {
2748 new_chunks.push_back(chunk);
2749 width_ += chunk.width;
2750 }
2751
2752 chunks_.swap(new_chunks);
2753 }
2754 else
2755 {
2756 cover("kernel.rtlil.sigspec.remove_const.unpacked");
2757
2758 std::vector<RTLIL::SigBit> new_bits;
2759 new_bits.reserve(width_);
2760
2761 for (auto &bit : bits_)
2762 if (bit.wire != NULL)
2763 new_bits.push_back(bit);
2764
2765 bits_.swap(new_bits);
2766 width_ = bits_.size();
2767 }
2768
2769 check();
2770 }
2771
2772 void RTLIL::SigSpec::remove(int offset, int length)
2773 {
2774 cover("kernel.rtlil.sigspec.remove_pos");
2775
2776 unpack();
2777
2778 log_assert(offset >= 0);
2779 log_assert(length >= 0);
2780 log_assert(offset + length <= width_);
2781
2782 bits_.erase(bits_.begin() + offset, bits_.begin() + offset + length);
2783 width_ = bits_.size();
2784
2785 check();
2786 }
2787
2788 RTLIL::SigSpec RTLIL::SigSpec::extract(int offset, int length) const
2789 {
2790 unpack();
2791 cover("kernel.rtlil.sigspec.extract_pos");
2792 return std::vector<RTLIL::SigBit>(bits_.begin() + offset, bits_.begin() + offset + length);
2793 }
2794
2795 void RTLIL::SigSpec::append(const RTLIL::SigSpec &signal)
2796 {
2797 if (signal.width_ == 0)
2798 return;
2799
2800 if (width_ == 0) {
2801 *this = signal;
2802 return;
2803 }
2804
2805 cover("kernel.rtlil.sigspec.append");
2806
2807 if (packed() != signal.packed()) {
2808 pack();
2809 signal.pack();
2810 }
2811
2812 if (packed())
2813 for (auto &other_c : signal.chunks_)
2814 {
2815 auto &my_last_c = chunks_.back();
2816 if (my_last_c.wire == NULL && other_c.wire == NULL) {
2817 auto &this_data = my_last_c.data;
2818 auto &other_data = other_c.data;
2819 this_data.insert(this_data.end(), other_data.begin(), other_data.end());
2820 my_last_c.width += other_c.width;
2821 } else
2822 if (my_last_c.wire == other_c.wire && my_last_c.offset + my_last_c.width == other_c.offset) {
2823 my_last_c.width += other_c.width;
2824 } else
2825 chunks_.push_back(other_c);
2826 }
2827 else
2828 bits_.insert(bits_.end(), signal.bits_.begin(), signal.bits_.end());
2829
2830 width_ += signal.width_;
2831 check();
2832 }
2833
2834 void RTLIL::SigSpec::append_bit(const RTLIL::SigBit &bit)
2835 {
2836 if (packed())
2837 {
2838 cover("kernel.rtlil.sigspec.append_bit.packed");
2839
2840 if (chunks_.size() == 0)
2841 chunks_.push_back(bit);
2842 else
2843 if (bit.wire == NULL)
2844 if (chunks_.back().wire == NULL) {
2845 chunks_.back().data.push_back(bit.data);
2846 chunks_.back().width++;
2847 } else
2848 chunks_.push_back(bit);
2849 else
2850 if (chunks_.back().wire == bit.wire && chunks_.back().offset + chunks_.back().width == bit.offset)
2851 chunks_.back().width++;
2852 else
2853 chunks_.push_back(bit);
2854 }
2855 else
2856 {
2857 cover("kernel.rtlil.sigspec.append_bit.unpacked");
2858 bits_.push_back(bit);
2859 }
2860
2861 width_++;
2862 check();
2863 }
2864
2865 void RTLIL::SigSpec::extend_u0(int width, bool is_signed)
2866 {
2867 cover("kernel.rtlil.sigspec.extend_u0");
2868
2869 pack();
2870
2871 if (width_ > width)
2872 remove(width, width_ - width);
2873
2874 if (width_ < width) {
2875 RTLIL::SigBit padding = width_ > 0 ? (*this)[width_ - 1] : RTLIL::State::S0;
2876 if (!is_signed)
2877 padding = RTLIL::State::S0;
2878 while (width_ < width)
2879 append(padding);
2880 }
2881
2882 }
2883
2884 RTLIL::SigSpec RTLIL::SigSpec::repeat(int num) const
2885 {
2886 cover("kernel.rtlil.sigspec.repeat");
2887
2888 RTLIL::SigSpec sig;
2889 for (int i = 0; i < num; i++)
2890 sig.append(*this);
2891 return sig;
2892 }
2893
2894 #ifndef NDEBUG
2895 void RTLIL::SigSpec::check() const
2896 {
2897 if (width_ > 64)
2898 {
2899 cover("kernel.rtlil.sigspec.check.skip");
2900 }
2901 else if (packed())
2902 {
2903 cover("kernel.rtlil.sigspec.check.packed");
2904
2905 int w = 0;
2906 for (size_t i = 0; i < chunks_.size(); i++) {
2907 const RTLIL::SigChunk chunk = chunks_[i];
2908 if (chunk.wire == NULL) {
2909 if (i > 0)
2910 log_assert(chunks_[i-1].wire != NULL);
2911 log_assert(chunk.offset == 0);
2912 log_assert(chunk.data.size() == (size_t)chunk.width);
2913 } else {
2914 if (i > 0 && chunks_[i-1].wire == chunk.wire)
2915 log_assert(chunk.offset != chunks_[i-1].offset + chunks_[i-1].width);
2916 log_assert(chunk.offset >= 0);
2917 log_assert(chunk.width >= 0);
2918 log_assert(chunk.offset + chunk.width <= chunk.wire->width);
2919 log_assert(chunk.data.size() == 0);
2920 }
2921 w += chunk.width;
2922 }
2923 log_assert(w == width_);
2924 log_assert(bits_.empty());
2925 }
2926 else
2927 {
2928 cover("kernel.rtlil.sigspec.check.unpacked");
2929
2930 log_assert(width_ == GetSize(bits_));
2931 log_assert(chunks_.empty());
2932 }
2933 }
2934 #endif
2935
2936 bool RTLIL::SigSpec::operator <(const RTLIL::SigSpec &other) const
2937 {
2938 cover("kernel.rtlil.sigspec.comp_lt");
2939
2940 if (this == &other)
2941 return false;
2942
2943 if (width_ != other.width_)
2944 return width_ < other.width_;
2945
2946 pack();
2947 other.pack();
2948
2949 if (chunks_.size() != other.chunks_.size())
2950 return chunks_.size() < other.chunks_.size();
2951
2952 updhash();
2953 other.updhash();
2954
2955 if (hash_ != other.hash_)
2956 return hash_ < other.hash_;
2957
2958 for (size_t i = 0; i < chunks_.size(); i++)
2959 if (chunks_[i] != other.chunks_[i]) {
2960 cover("kernel.rtlil.sigspec.comp_lt.hash_collision");
2961 return chunks_[i] < other.chunks_[i];
2962 }
2963
2964 cover("kernel.rtlil.sigspec.comp_lt.equal");
2965 return false;
2966 }
2967
2968 bool RTLIL::SigSpec::operator ==(const RTLIL::SigSpec &other) const
2969 {
2970 cover("kernel.rtlil.sigspec.comp_eq");
2971
2972 if (this == &other)
2973 return true;
2974
2975 if (width_ != other.width_)
2976 return false;
2977
2978 pack();
2979 other.pack();
2980
2981 if (chunks_.size() != chunks_.size())
2982 return false;
2983
2984 updhash();
2985 other.updhash();
2986
2987 if (hash_ != other.hash_)
2988 return false;
2989
2990 for (size_t i = 0; i < chunks_.size(); i++)
2991 if (chunks_[i] != other.chunks_[i]) {
2992 cover("kernel.rtlil.sigspec.comp_eq.hash_collision");
2993 return false;
2994 }
2995
2996 cover("kernel.rtlil.sigspec.comp_eq.equal");
2997 return true;
2998 }
2999
3000 bool RTLIL::SigSpec::is_wire() const
3001 {
3002 cover("kernel.rtlil.sigspec.is_wire");
3003
3004 pack();
3005 return GetSize(chunks_) == 1 && chunks_[0].wire && chunks_[0].wire->width == width_;
3006 }
3007
3008 bool RTLIL::SigSpec::is_chunk() const
3009 {
3010 cover("kernel.rtlil.sigspec.is_chunk");
3011
3012 pack();
3013 return GetSize(chunks_) == 1;
3014 }
3015
3016 bool RTLIL::SigSpec::is_fully_const() const
3017 {
3018 cover("kernel.rtlil.sigspec.is_fully_const");
3019
3020 pack();
3021 for (auto it = chunks_.begin(); it != chunks_.end(); it++)
3022 if (it->width > 0 && it->wire != NULL)
3023 return false;
3024 return true;
3025 }
3026
3027 bool RTLIL::SigSpec::is_fully_zero() const
3028 {
3029 cover("kernel.rtlil.sigspec.is_fully_zero");
3030
3031 pack();
3032 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
3033 if (it->width > 0 && it->wire != NULL)
3034 return false;
3035 for (size_t i = 0; i < it->data.size(); i++)
3036 if (it->data[i] != RTLIL::State::S0)
3037 return false;
3038 }
3039 return true;
3040 }
3041
3042 bool RTLIL::SigSpec::is_fully_def() const
3043 {
3044 cover("kernel.rtlil.sigspec.is_fully_def");
3045
3046 pack();
3047 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
3048 if (it->width > 0 && it->wire != NULL)
3049 return false;
3050 for (size_t i = 0; i < it->data.size(); i++)
3051 if (it->data[i] != RTLIL::State::S0 && it->data[i] != RTLIL::State::S1)
3052 return false;
3053 }
3054 return true;
3055 }
3056
3057 bool RTLIL::SigSpec::is_fully_undef() const
3058 {
3059 cover("kernel.rtlil.sigspec.is_fully_undef");
3060
3061 pack();
3062 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
3063 if (it->width > 0 && it->wire != NULL)
3064 return false;
3065 for (size_t i = 0; i < it->data.size(); i++)
3066 if (it->data[i] != RTLIL::State::Sx && it->data[i] != RTLIL::State::Sz)
3067 return false;
3068 }
3069 return true;
3070 }
3071
3072 bool RTLIL::SigSpec::has_const() const
3073 {
3074 cover("kernel.rtlil.sigspec.has_const");
3075
3076 pack();
3077 for (auto it = chunks_.begin(); it != chunks_.end(); it++)
3078 if (it->width > 0 && it->wire == NULL)
3079 return true;
3080 return false;
3081 }
3082
3083 bool RTLIL::SigSpec::has_marked_bits() const
3084 {
3085 cover("kernel.rtlil.sigspec.has_marked_bits");
3086
3087 pack();
3088 for (auto it = chunks_.begin(); it != chunks_.end(); it++)
3089 if (it->width > 0 && it->wire == NULL) {
3090 for (size_t i = 0; i < it->data.size(); i++)
3091 if (it->data[i] == RTLIL::State::Sm)
3092 return true;
3093 }
3094 return false;
3095 }
3096
3097 bool RTLIL::SigSpec::as_bool() const
3098 {
3099 cover("kernel.rtlil.sigspec.as_bool");
3100
3101 pack();
3102 log_assert(is_fully_const() && GetSize(chunks_) <= 1);
3103 if (width_)
3104 return RTLIL::Const(chunks_[0].data).as_bool();
3105 return false;
3106 }
3107
3108 int RTLIL::SigSpec::as_int(bool is_signed) const
3109 {
3110 cover("kernel.rtlil.sigspec.as_int");
3111
3112 pack();
3113 log_assert(is_fully_const() && GetSize(chunks_) <= 1);
3114 if (width_)
3115 return RTLIL::Const(chunks_[0].data).as_int(is_signed);
3116 return 0;
3117 }
3118
3119 std::string RTLIL::SigSpec::as_string() const
3120 {
3121 cover("kernel.rtlil.sigspec.as_string");
3122
3123 pack();
3124 std::string str;
3125 for (size_t i = chunks_.size(); i > 0; i--) {
3126 const RTLIL::SigChunk &chunk = chunks_[i-1];
3127 if (chunk.wire != NULL)
3128 for (int j = 0; j < chunk.width; j++)
3129 str += "?";
3130 else
3131 str += RTLIL::Const(chunk.data).as_string();
3132 }
3133 return str;
3134 }
3135
3136 RTLIL::Const RTLIL::SigSpec::as_const() const
3137 {
3138 cover("kernel.rtlil.sigspec.as_const");
3139
3140 pack();
3141 log_assert(is_fully_const() && GetSize(chunks_) <= 1);
3142 if (width_)
3143 return chunks_[0].data;
3144 return RTLIL::Const();
3145 }
3146
3147 RTLIL::Wire *RTLIL::SigSpec::as_wire() const
3148 {
3149 cover("kernel.rtlil.sigspec.as_wire");
3150
3151 pack();
3152 log_assert(is_wire());
3153 return chunks_[0].wire;
3154 }
3155
3156 RTLIL::SigChunk RTLIL::SigSpec::as_chunk() const
3157 {
3158 cover("kernel.rtlil.sigspec.as_chunk");
3159
3160 pack();
3161 log_assert(is_chunk());
3162 return chunks_[0];
3163 }
3164
3165 bool RTLIL::SigSpec::match(std::string pattern) const
3166 {
3167 cover("kernel.rtlil.sigspec.match");
3168
3169 pack();
3170 std::string str = as_string();
3171 log_assert(pattern.size() == str.size());
3172
3173 for (size_t i = 0; i < pattern.size(); i++) {
3174 if (pattern[i] == ' ')
3175 continue;
3176 if (pattern[i] == '*') {
3177 if (str[i] != 'z' && str[i] != 'x')
3178 return false;
3179 continue;
3180 }
3181 if (pattern[i] != str[i])
3182 return false;
3183 }
3184
3185 return true;
3186 }
3187
3188 std::set<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_set() const
3189 {
3190 cover("kernel.rtlil.sigspec.to_sigbit_set");
3191
3192 pack();
3193 std::set<RTLIL::SigBit> sigbits;
3194 for (auto &c : chunks_)
3195 for (int i = 0; i < c.width; i++)
3196 sigbits.insert(RTLIL::SigBit(c, i));
3197 return sigbits;
3198 }
3199
3200 pool<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_pool() const
3201 {
3202 cover("kernel.rtlil.sigspec.to_sigbit_pool");
3203
3204 pack();
3205 pool<RTLIL::SigBit> sigbits;
3206 for (auto &c : chunks_)
3207 for (int i = 0; i < c.width; i++)
3208 sigbits.insert(RTLIL::SigBit(c, i));
3209 return sigbits;
3210 }
3211
3212 std::vector<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_vector() const
3213 {
3214 cover("kernel.rtlil.sigspec.to_sigbit_vector");
3215
3216 unpack();
3217 return bits_;
3218 }
3219
3220 std::map<RTLIL::SigBit, RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_map(const RTLIL::SigSpec &other) const
3221 {
3222 cover("kernel.rtlil.sigspec.to_sigbit_map");
3223
3224 unpack();
3225 other.unpack();
3226
3227 log_assert(width_ == other.width_);
3228
3229 std::map<RTLIL::SigBit, RTLIL::SigBit> new_map;
3230 for (int i = 0; i < width_; i++)
3231 new_map[bits_[i]] = other.bits_[i];
3232
3233 return new_map;
3234 }
3235
3236 dict<RTLIL::SigBit, RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_dict(const RTLIL::SigSpec &other) const
3237 {
3238 cover("kernel.rtlil.sigspec.to_sigbit_dict");
3239
3240 unpack();
3241 other.unpack();
3242
3243 log_assert(width_ == other.width_);
3244
3245 dict<RTLIL::SigBit, RTLIL::SigBit> new_map;
3246 for (int i = 0; i < width_; i++)
3247 new_map[bits_[i]] = other.bits_[i];
3248
3249 return new_map;
3250 }
3251
3252 RTLIL::SigBit RTLIL::SigSpec::to_single_sigbit() const
3253 {
3254 cover("kernel.rtlil.sigspec.to_single_sigbit");
3255
3256 pack();
3257 log_assert(width_ == 1);
3258 for (auto &c : chunks_)
3259 if (c.width)
3260 return RTLIL::SigBit(c);
3261 log_abort();
3262 }
3263
3264 static void sigspec_parse_split(std::vector<std::string> &tokens, const std::string &text, char sep)
3265 {
3266 size_t start = 0, end = 0;
3267 while ((end = text.find(sep, start)) != std::string::npos) {
3268 tokens.push_back(text.substr(start, end - start));
3269 start = end + 1;
3270 }
3271 tokens.push_back(text.substr(start));
3272 }
3273
3274 static int sigspec_parse_get_dummy_line_num()
3275 {
3276 return 0;
3277 }
3278
3279 bool RTLIL::SigSpec::parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str)
3280 {
3281 cover("kernel.rtlil.sigspec.parse");
3282
3283 std::vector<std::string> tokens;
3284 sigspec_parse_split(tokens, str, ',');
3285
3286 sig = RTLIL::SigSpec();
3287 for (int tokidx = int(tokens.size())-1; tokidx >= 0; tokidx--)
3288 {
3289 std::string netname = tokens[tokidx];
3290 std::string indices;
3291
3292 if (netname.size() == 0)
3293 continue;
3294
3295 if (('0' <= netname[0] && netname[0] <= '9') || netname[0] == '\'') {
3296 cover("kernel.rtlil.sigspec.parse.const");
3297 AST::get_line_num = sigspec_parse_get_dummy_line_num;
3298 AST::AstNode *ast = VERILOG_FRONTEND::const2ast(netname);
3299 if (ast == NULL)
3300 return false;
3301 sig.append(RTLIL::Const(ast->bits));
3302 delete ast;
3303 continue;
3304 }
3305
3306 if (module == NULL)
3307 return false;
3308
3309 cover("kernel.rtlil.sigspec.parse.net");
3310
3311 if (netname[0] != '$' && netname[0] != '\\')
3312 netname = "\\" + netname;
3313
3314 if (module->wires_.count(netname) == 0) {
3315 size_t indices_pos = netname.size()-1;
3316 if (indices_pos > 2 && netname[indices_pos] == ']')
3317 {
3318 indices_pos--;
3319 while (indices_pos > 0 && ('0' <= netname[indices_pos] && netname[indices_pos] <= '9')) indices_pos--;
3320 if (indices_pos > 0 && netname[indices_pos] == ':') {
3321 indices_pos--;
3322 while (indices_pos > 0 && ('0' <= netname[indices_pos] && netname[indices_pos] <= '9')) indices_pos--;
3323 }
3324 if (indices_pos > 0 && netname[indices_pos] == '[') {
3325 indices = netname.substr(indices_pos);
3326 netname = netname.substr(0, indices_pos);
3327 }
3328 }
3329 }
3330
3331 if (module->wires_.count(netname) == 0)
3332 return false;
3333
3334 RTLIL::Wire *wire = module->wires_.at(netname);
3335 if (!indices.empty()) {
3336 std::vector<std::string> index_tokens;
3337 sigspec_parse_split(index_tokens, indices.substr(1, indices.size()-2), ':');
3338 if (index_tokens.size() == 1) {
3339 cover("kernel.rtlil.sigspec.parse.bit_sel");
3340 int a = atoi(index_tokens.at(0).c_str());
3341 if (a < 0 || a >= wire->width)
3342 return false;
3343 sig.append(RTLIL::SigSpec(wire, a));
3344 } else {
3345 cover("kernel.rtlil.sigspec.parse.part_sel");
3346 int a = atoi(index_tokens.at(0).c_str());
3347 int b = atoi(index_tokens.at(1).c_str());
3348 if (a > b) {
3349 int tmp = a;
3350 a = b, b = tmp;
3351 }
3352 if (a < 0 || a >= wire->width)
3353 return false;
3354 if (b < 0 || b >= wire->width)
3355 return false;
3356 sig.append(RTLIL::SigSpec(wire, a, b-a+1));
3357 }
3358 } else
3359 sig.append(wire);
3360 }
3361
3362 return true;
3363 }
3364
3365 bool RTLIL::SigSpec::parse_sel(RTLIL::SigSpec &sig, RTLIL::Design *design, RTLIL::Module *module, std::string str)
3366 {
3367 if (str.empty() || str[0] != '@')
3368 return parse(sig, module, str);
3369
3370 cover("kernel.rtlil.sigspec.parse.sel");
3371
3372 str = RTLIL::escape_id(str.substr(1));
3373 if (design->selection_vars.count(str) == 0)
3374 return false;
3375
3376 sig = RTLIL::SigSpec();
3377 RTLIL::Selection &sel = design->selection_vars.at(str);
3378 for (auto &it : module->wires_)
3379 if (sel.selected_member(module->name, it.first))
3380 sig.append(it.second);
3381
3382 return true;
3383 }
3384
3385 bool RTLIL::SigSpec::parse_rhs(const RTLIL::SigSpec &lhs, RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str)
3386 {
3387 if (str == "0") {
3388 cover("kernel.rtlil.sigspec.parse.rhs_zeros");
3389 sig = RTLIL::SigSpec(RTLIL::State::S0, lhs.width_);
3390 return true;
3391 }
3392
3393 if (str == "~0") {
3394 cover("kernel.rtlil.sigspec.parse.rhs_ones");
3395 sig = RTLIL::SigSpec(RTLIL::State::S1, lhs.width_);
3396 return true;
3397 }
3398
3399 if (lhs.chunks_.size() == 1) {
3400 char *p = (char*)str.c_str(), *endptr;
3401 long int val = strtol(p, &endptr, 10);
3402 if (endptr && endptr != p && *endptr == 0) {
3403 sig = RTLIL::SigSpec(val, lhs.width_);
3404 cover("kernel.rtlil.sigspec.parse.rhs_dec");
3405 return true;
3406 }
3407 }
3408
3409 return parse(sig, module, str);
3410 }
3411
3412 RTLIL::CaseRule::~CaseRule()
3413 {
3414 for (auto it = switches.begin(); it != switches.end(); it++)
3415 delete *it;
3416 }
3417
3418 RTLIL::CaseRule *RTLIL::CaseRule::clone() const
3419 {
3420 RTLIL::CaseRule *new_caserule = new RTLIL::CaseRule;
3421 new_caserule->compare = compare;
3422 new_caserule->actions = actions;
3423 for (auto &it : switches)
3424 new_caserule->switches.push_back(it->clone());
3425 return new_caserule;
3426 }
3427
3428 RTLIL::SwitchRule::~SwitchRule()
3429 {
3430 for (auto it = cases.begin(); it != cases.end(); it++)
3431 delete *it;
3432 }
3433
3434 RTLIL::SwitchRule *RTLIL::SwitchRule::clone() const
3435 {
3436 RTLIL::SwitchRule *new_switchrule = new RTLIL::SwitchRule;
3437 new_switchrule->signal = signal;
3438 new_switchrule->attributes = attributes;
3439 for (auto &it : cases)
3440 new_switchrule->cases.push_back(it->clone());
3441 return new_switchrule;
3442
3443 }
3444
3445 RTLIL::SyncRule *RTLIL::SyncRule::clone() const
3446 {
3447 RTLIL::SyncRule *new_syncrule = new RTLIL::SyncRule;
3448 new_syncrule->type = type;
3449 new_syncrule->signal = signal;
3450 new_syncrule->actions = actions;
3451 return new_syncrule;
3452 }
3453
3454 RTLIL::Process::~Process()
3455 {
3456 for (auto it = syncs.begin(); it != syncs.end(); it++)
3457 delete *it;
3458 }
3459
3460 RTLIL::Process *RTLIL::Process::clone() const
3461 {
3462 RTLIL::Process *new_proc = new RTLIL::Process;
3463
3464 new_proc->name = name;
3465 new_proc->attributes = attributes;
3466
3467 RTLIL::CaseRule *rc_ptr = root_case.clone();
3468 new_proc->root_case = *rc_ptr;
3469 rc_ptr->switches.clear();
3470 delete rc_ptr;
3471
3472 for (auto &it : syncs)
3473 new_proc->syncs.push_back(it->clone());
3474
3475 return new_proc;
3476 }
3477
3478 YOSYS_NAMESPACE_END
3479