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kernel/mem: Add functions to emulate read port enable/init/reset signals.
[yosys.git] / kernel / rtlil.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 #include "kernel/yosys.h"
21 #include "kernel/macc.h"
22 #include "kernel/celltypes.h"
23 #include "kernel/binding.h"
24 #include "frontends/verilog/verilog_frontend.h"
25 #include "frontends/verilog/preproc.h"
26 #include "backends/rtlil/rtlil_backend.h"
27
28 #include <string.h>
29 #include <algorithm>
30
31 YOSYS_NAMESPACE_BEGIN
32
33 RTLIL::IdString::destruct_guard_t RTLIL::IdString::destruct_guard;
34 std::vector<char*> RTLIL::IdString::global_id_storage_;
35 dict<char*, int, hash_cstr_ops> RTLIL::IdString::global_id_index_;
36 #ifndef YOSYS_NO_IDS_REFCNT
37 std::vector<int> RTLIL::IdString::global_refcount_storage_;
38 std::vector<int> RTLIL::IdString::global_free_idx_list_;
39 #endif
40 #ifdef YOSYS_USE_STICKY_IDS
41 int RTLIL::IdString::last_created_idx_[8];
42 int RTLIL::IdString::last_created_idx_ptr_;
43 #endif
44
45 #define X(_id) IdString RTLIL::ID::_id;
46 #include "kernel/constids.inc"
47 #undef X
48
49 dict<std::string, std::string> RTLIL::constpad;
50
51 const pool<IdString> &RTLIL::builtin_ff_cell_types() {
52 static const pool<IdString> res = {
53 ID($sr),
54 ID($ff),
55 ID($dff),
56 ID($dffe),
57 ID($dffsr),
58 ID($dffsre),
59 ID($adff),
60 ID($adffe),
61 ID($aldff),
62 ID($aldffe),
63 ID($sdff),
64 ID($sdffe),
65 ID($sdffce),
66 ID($dlatch),
67 ID($adlatch),
68 ID($dlatchsr),
69 ID($_DFFE_NN_),
70 ID($_DFFE_NP_),
71 ID($_DFFE_PN_),
72 ID($_DFFE_PP_),
73 ID($_DFFSR_NNN_),
74 ID($_DFFSR_NNP_),
75 ID($_DFFSR_NPN_),
76 ID($_DFFSR_NPP_),
77 ID($_DFFSR_PNN_),
78 ID($_DFFSR_PNP_),
79 ID($_DFFSR_PPN_),
80 ID($_DFFSR_PPP_),
81 ID($_DFFSRE_NNNN_),
82 ID($_DFFSRE_NNNP_),
83 ID($_DFFSRE_NNPN_),
84 ID($_DFFSRE_NNPP_),
85 ID($_DFFSRE_NPNN_),
86 ID($_DFFSRE_NPNP_),
87 ID($_DFFSRE_NPPN_),
88 ID($_DFFSRE_NPPP_),
89 ID($_DFFSRE_PNNN_),
90 ID($_DFFSRE_PNNP_),
91 ID($_DFFSRE_PNPN_),
92 ID($_DFFSRE_PNPP_),
93 ID($_DFFSRE_PPNN_),
94 ID($_DFFSRE_PPNP_),
95 ID($_DFFSRE_PPPN_),
96 ID($_DFFSRE_PPPP_),
97 ID($_DFF_N_),
98 ID($_DFF_P_),
99 ID($_DFF_NN0_),
100 ID($_DFF_NN1_),
101 ID($_DFF_NP0_),
102 ID($_DFF_NP1_),
103 ID($_DFF_PN0_),
104 ID($_DFF_PN1_),
105 ID($_DFF_PP0_),
106 ID($_DFF_PP1_),
107 ID($_DFFE_NN0N_),
108 ID($_DFFE_NN0P_),
109 ID($_DFFE_NN1N_),
110 ID($_DFFE_NN1P_),
111 ID($_DFFE_NP0N_),
112 ID($_DFFE_NP0P_),
113 ID($_DFFE_NP1N_),
114 ID($_DFFE_NP1P_),
115 ID($_DFFE_PN0N_),
116 ID($_DFFE_PN0P_),
117 ID($_DFFE_PN1N_),
118 ID($_DFFE_PN1P_),
119 ID($_DFFE_PP0N_),
120 ID($_DFFE_PP0P_),
121 ID($_DFFE_PP1N_),
122 ID($_DFFE_PP1P_),
123 ID($_ALDFF_NN_),
124 ID($_ALDFF_NP_),
125 ID($_ALDFF_PN_),
126 ID($_ALDFF_PP_),
127 ID($_ALDFFE_NNN_),
128 ID($_ALDFFE_NNP_),
129 ID($_ALDFFE_NPN_),
130 ID($_ALDFFE_NPP_),
131 ID($_ALDFFE_PNN_),
132 ID($_ALDFFE_PNP_),
133 ID($_ALDFFE_PPN_),
134 ID($_ALDFFE_PPP_),
135 ID($_SDFF_NN0_),
136 ID($_SDFF_NN1_),
137 ID($_SDFF_NP0_),
138 ID($_SDFF_NP1_),
139 ID($_SDFF_PN0_),
140 ID($_SDFF_PN1_),
141 ID($_SDFF_PP0_),
142 ID($_SDFF_PP1_),
143 ID($_SDFFE_NN0N_),
144 ID($_SDFFE_NN0P_),
145 ID($_SDFFE_NN1N_),
146 ID($_SDFFE_NN1P_),
147 ID($_SDFFE_NP0N_),
148 ID($_SDFFE_NP0P_),
149 ID($_SDFFE_NP1N_),
150 ID($_SDFFE_NP1P_),
151 ID($_SDFFE_PN0N_),
152 ID($_SDFFE_PN0P_),
153 ID($_SDFFE_PN1N_),
154 ID($_SDFFE_PN1P_),
155 ID($_SDFFE_PP0N_),
156 ID($_SDFFE_PP0P_),
157 ID($_SDFFE_PP1N_),
158 ID($_SDFFE_PP1P_),
159 ID($_SDFFCE_NN0N_),
160 ID($_SDFFCE_NN0P_),
161 ID($_SDFFCE_NN1N_),
162 ID($_SDFFCE_NN1P_),
163 ID($_SDFFCE_NP0N_),
164 ID($_SDFFCE_NP0P_),
165 ID($_SDFFCE_NP1N_),
166 ID($_SDFFCE_NP1P_),
167 ID($_SDFFCE_PN0N_),
168 ID($_SDFFCE_PN0P_),
169 ID($_SDFFCE_PN1N_),
170 ID($_SDFFCE_PN1P_),
171 ID($_SDFFCE_PP0N_),
172 ID($_SDFFCE_PP0P_),
173 ID($_SDFFCE_PP1N_),
174 ID($_SDFFCE_PP1P_),
175 ID($_SR_NN_),
176 ID($_SR_NP_),
177 ID($_SR_PN_),
178 ID($_SR_PP_),
179 ID($_DLATCH_N_),
180 ID($_DLATCH_P_),
181 ID($_DLATCH_NN0_),
182 ID($_DLATCH_NN1_),
183 ID($_DLATCH_NP0_),
184 ID($_DLATCH_NP1_),
185 ID($_DLATCH_PN0_),
186 ID($_DLATCH_PN1_),
187 ID($_DLATCH_PP0_),
188 ID($_DLATCH_PP1_),
189 ID($_DLATCHSR_NNN_),
190 ID($_DLATCHSR_NNP_),
191 ID($_DLATCHSR_NPN_),
192 ID($_DLATCHSR_NPP_),
193 ID($_DLATCHSR_PNN_),
194 ID($_DLATCHSR_PNP_),
195 ID($_DLATCHSR_PPN_),
196 ID($_DLATCHSR_PPP_),
197 ID($_FF_),
198 };
199 return res;
200 }
201
202 RTLIL::Const::Const()
203 {
204 flags = RTLIL::CONST_FLAG_NONE;
205 }
206
207 RTLIL::Const::Const(std::string str)
208 {
209 flags = RTLIL::CONST_FLAG_STRING;
210 for (int i = str.size()-1; i >= 0; i--) {
211 unsigned char ch = str[i];
212 for (int j = 0; j < 8; j++) {
213 bits.push_back((ch & 1) != 0 ? State::S1 : State::S0);
214 ch = ch >> 1;
215 }
216 }
217 }
218
219 RTLIL::Const::Const(int val, int width)
220 {
221 flags = RTLIL::CONST_FLAG_NONE;
222 for (int i = 0; i < width; i++) {
223 bits.push_back((val & 1) != 0 ? State::S1 : State::S0);
224 val = val >> 1;
225 }
226 }
227
228 RTLIL::Const::Const(RTLIL::State bit, int width)
229 {
230 flags = RTLIL::CONST_FLAG_NONE;
231 for (int i = 0; i < width; i++)
232 bits.push_back(bit);
233 }
234
235 RTLIL::Const::Const(const std::vector<bool> &bits)
236 {
237 flags = RTLIL::CONST_FLAG_NONE;
238 for (const auto &b : bits)
239 this->bits.emplace_back(b ? State::S1 : State::S0);
240 }
241
242 RTLIL::Const::Const(const RTLIL::Const &c)
243 {
244 flags = c.flags;
245 for (const auto &b : c.bits)
246 this->bits.push_back(b);
247 }
248
249 bool RTLIL::Const::operator <(const RTLIL::Const &other) const
250 {
251 if (bits.size() != other.bits.size())
252 return bits.size() < other.bits.size();
253 for (size_t i = 0; i < bits.size(); i++)
254 if (bits[i] != other.bits[i])
255 return bits[i] < other.bits[i];
256 return false;
257 }
258
259 bool RTLIL::Const::operator ==(const RTLIL::Const &other) const
260 {
261 return bits == other.bits;
262 }
263
264 bool RTLIL::Const::operator !=(const RTLIL::Const &other) const
265 {
266 return bits != other.bits;
267 }
268
269 bool RTLIL::Const::as_bool() const
270 {
271 for (size_t i = 0; i < bits.size(); i++)
272 if (bits[i] == State::S1)
273 return true;
274 return false;
275 }
276
277 int RTLIL::Const::as_int(bool is_signed) const
278 {
279 int32_t ret = 0;
280 for (size_t i = 0; i < bits.size() && i < 32; i++)
281 if (bits[i] == State::S1)
282 ret |= 1 << i;
283 if (is_signed && bits.back() == State::S1)
284 for (size_t i = bits.size(); i < 32; i++)
285 ret |= 1 << i;
286 return ret;
287 }
288
289 std::string RTLIL::Const::as_string() const
290 {
291 std::string ret;
292 ret.reserve(bits.size());
293 for (size_t i = bits.size(); i > 0; i--)
294 switch (bits[i-1]) {
295 case S0: ret += "0"; break;
296 case S1: ret += "1"; break;
297 case Sx: ret += "x"; break;
298 case Sz: ret += "z"; break;
299 case Sa: ret += "-"; break;
300 case Sm: ret += "m"; break;
301 }
302 return ret;
303 }
304
305 RTLIL::Const RTLIL::Const::from_string(const std::string &str)
306 {
307 Const c;
308 c.bits.reserve(str.size());
309 for (auto it = str.rbegin(); it != str.rend(); it++)
310 switch (*it) {
311 case '0': c.bits.push_back(State::S0); break;
312 case '1': c.bits.push_back(State::S1); break;
313 case 'x': c.bits.push_back(State::Sx); break;
314 case 'z': c.bits.push_back(State::Sz); break;
315 case 'm': c.bits.push_back(State::Sm); break;
316 default: c.bits.push_back(State::Sa);
317 }
318 return c;
319 }
320
321 std::string RTLIL::Const::decode_string() const
322 {
323 std::string string;
324 string.reserve(GetSize(bits)/8);
325 for (int i = 0; i < GetSize(bits); i += 8) {
326 char ch = 0;
327 for (int j = 0; j < 8 && i + j < int (bits.size()); j++)
328 if (bits[i + j] == RTLIL::State::S1)
329 ch |= 1 << j;
330 if (ch != 0)
331 string.append({ch});
332 }
333 std::reverse(string.begin(), string.end());
334 return string;
335 }
336
337 bool RTLIL::Const::is_fully_zero() const
338 {
339 cover("kernel.rtlil.const.is_fully_zero");
340
341 for (const auto &bit : bits)
342 if (bit != RTLIL::State::S0)
343 return false;
344
345 return true;
346 }
347
348 bool RTLIL::Const::is_fully_ones() const
349 {
350 cover("kernel.rtlil.const.is_fully_ones");
351
352 for (const auto &bit : bits)
353 if (bit != RTLIL::State::S1)
354 return false;
355
356 return true;
357 }
358
359 bool RTLIL::Const::is_fully_def() const
360 {
361 cover("kernel.rtlil.const.is_fully_def");
362
363 for (const auto &bit : bits)
364 if (bit != RTLIL::State::S0 && bit != RTLIL::State::S1)
365 return false;
366
367 return true;
368 }
369
370 bool RTLIL::Const::is_fully_undef() const
371 {
372 cover("kernel.rtlil.const.is_fully_undef");
373
374 for (const auto &bit : bits)
375 if (bit != RTLIL::State::Sx && bit != RTLIL::State::Sz)
376 return false;
377
378 return true;
379 }
380
381 bool RTLIL::Const::is_onehot(int *pos) const
382 {
383 cover("kernel.rtlil.const.is_onehot");
384
385 bool found = false;
386 for (int i = 0; i < GetSize(*this); i++) {
387 auto &bit = bits[i];
388 if (bit != RTLIL::State::S0 && bit != RTLIL::State::S1)
389 return false;
390 if (bit == RTLIL::State::S1) {
391 if (found)
392 return false;
393 if (pos)
394 *pos = i;
395 found = true;
396 }
397 }
398 return found;
399 }
400
401 bool RTLIL::AttrObject::has_attribute(RTLIL::IdString id) const
402 {
403 return attributes.count(id);
404 }
405
406 void RTLIL::AttrObject::set_bool_attribute(RTLIL::IdString id, bool value)
407 {
408 if (value)
409 attributes[id] = RTLIL::Const(1);
410 else
411 attributes.erase(id);
412 }
413
414 bool RTLIL::AttrObject::get_bool_attribute(RTLIL::IdString id) const
415 {
416 const auto it = attributes.find(id);
417 if (it == attributes.end())
418 return false;
419 return it->second.as_bool();
420 }
421
422 void RTLIL::AttrObject::set_string_attribute(RTLIL::IdString id, string value)
423 {
424 if (value.empty())
425 attributes.erase(id);
426 else
427 attributes[id] = value;
428 }
429
430 string RTLIL::AttrObject::get_string_attribute(RTLIL::IdString id) const
431 {
432 std::string value;
433 const auto it = attributes.find(id);
434 if (it != attributes.end())
435 value = it->second.decode_string();
436 return value;
437 }
438
439 void RTLIL::AttrObject::set_strpool_attribute(RTLIL::IdString id, const pool<string> &data)
440 {
441 string attrval;
442 for (const auto &s : data) {
443 if (!attrval.empty())
444 attrval += "|";
445 attrval += s;
446 }
447 set_string_attribute(id, attrval);
448 }
449
450 void RTLIL::AttrObject::add_strpool_attribute(RTLIL::IdString id, const pool<string> &data)
451 {
452 pool<string> union_data = get_strpool_attribute(id);
453 union_data.insert(data.begin(), data.end());
454 if (!union_data.empty())
455 set_strpool_attribute(id, union_data);
456 }
457
458 pool<string> RTLIL::AttrObject::get_strpool_attribute(RTLIL::IdString id) const
459 {
460 pool<string> data;
461 if (attributes.count(id) != 0)
462 for (auto s : split_tokens(get_string_attribute(id), "|"))
463 data.insert(s);
464 return data;
465 }
466
467 void RTLIL::AttrObject::set_hdlname_attribute(const vector<string> &hierarchy)
468 {
469 string attrval;
470 for (const auto &ident : hierarchy) {
471 if (!attrval.empty())
472 attrval += " ";
473 attrval += ident;
474 }
475 set_string_attribute(ID::hdlname, attrval);
476 }
477
478 vector<string> RTLIL::AttrObject::get_hdlname_attribute() const
479 {
480 return split_tokens(get_string_attribute(ID::hdlname), " ");
481 }
482
483 void RTLIL::AttrObject::set_intvec_attribute(RTLIL::IdString id, const vector<int> &data)
484 {
485 std::stringstream attrval;
486 for (auto &i : data) {
487 if (attrval.tellp() > 0)
488 attrval << " ";
489 attrval << i;
490 }
491 attributes[id] = RTLIL::Const(attrval.str());
492 }
493
494 vector<int> RTLIL::AttrObject::get_intvec_attribute(RTLIL::IdString id) const
495 {
496 vector<int> data;
497 auto it = attributes.find(id);
498 if (it != attributes.end())
499 for (const auto &s : split_tokens(attributes.at(id).decode_string())) {
500 char *end = nullptr;
501 errno = 0;
502 long value = strtol(s.c_str(), &end, 10);
503 if (end != s.c_str() + s.size())
504 log_cmd_error("Literal for intvec attribute has invalid format");
505 if (errno == ERANGE || value < INT_MIN || value > INT_MAX)
506 log_cmd_error("Literal for intvec attribute is out of range");
507 data.push_back(value);
508 }
509 return data;
510 }
511
512 bool RTLIL::Selection::selected_module(RTLIL::IdString mod_name) const
513 {
514 if (full_selection)
515 return true;
516 if (selected_modules.count(mod_name) > 0)
517 return true;
518 if (selected_members.count(mod_name) > 0)
519 return true;
520 return false;
521 }
522
523 bool RTLIL::Selection::selected_whole_module(RTLIL::IdString mod_name) const
524 {
525 if (full_selection)
526 return true;
527 if (selected_modules.count(mod_name) > 0)
528 return true;
529 return false;
530 }
531
532 bool RTLIL::Selection::selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const
533 {
534 if (full_selection)
535 return true;
536 if (selected_modules.count(mod_name) > 0)
537 return true;
538 if (selected_members.count(mod_name) > 0)
539 if (selected_members.at(mod_name).count(memb_name) > 0)
540 return true;
541 return false;
542 }
543
544 void RTLIL::Selection::optimize(RTLIL::Design *design)
545 {
546 if (full_selection) {
547 selected_modules.clear();
548 selected_members.clear();
549 return;
550 }
551
552 std::vector<RTLIL::IdString> del_list, add_list;
553
554 del_list.clear();
555 for (auto mod_name : selected_modules) {
556 if (design->modules_.count(mod_name) == 0)
557 del_list.push_back(mod_name);
558 selected_members.erase(mod_name);
559 }
560 for (auto mod_name : del_list)
561 selected_modules.erase(mod_name);
562
563 del_list.clear();
564 for (auto &it : selected_members)
565 if (design->modules_.count(it.first) == 0)
566 del_list.push_back(it.first);
567 for (auto mod_name : del_list)
568 selected_members.erase(mod_name);
569
570 for (auto &it : selected_members) {
571 del_list.clear();
572 for (auto memb_name : it.second)
573 if (design->modules_[it.first]->count_id(memb_name) == 0)
574 del_list.push_back(memb_name);
575 for (auto memb_name : del_list)
576 it.second.erase(memb_name);
577 }
578
579 del_list.clear();
580 add_list.clear();
581 for (auto &it : selected_members)
582 if (it.second.size() == 0)
583 del_list.push_back(it.first);
584 else if (it.second.size() == design->modules_[it.first]->wires_.size() + design->modules_[it.first]->memories.size() +
585 design->modules_[it.first]->cells_.size() + design->modules_[it.first]->processes.size())
586 add_list.push_back(it.first);
587 for (auto mod_name : del_list)
588 selected_members.erase(mod_name);
589 for (auto mod_name : add_list) {
590 selected_members.erase(mod_name);
591 selected_modules.insert(mod_name);
592 }
593
594 if (selected_modules.size() == design->modules_.size()) {
595 full_selection = true;
596 selected_modules.clear();
597 selected_members.clear();
598 }
599 }
600
601 RTLIL::Design::Design()
602 : verilog_defines (new define_map_t)
603 {
604 static unsigned int hashidx_count = 123456789;
605 hashidx_count = mkhash_xorshift(hashidx_count);
606 hashidx_ = hashidx_count;
607
608 refcount_modules_ = 0;
609 selection_stack.push_back(RTLIL::Selection());
610
611 #ifdef WITH_PYTHON
612 RTLIL::Design::get_all_designs()->insert(std::pair<unsigned int, RTLIL::Design*>(hashidx_, this));
613 #endif
614 }
615
616 RTLIL::Design::~Design()
617 {
618 for (auto &pr : modules_)
619 delete pr.second;
620 for (auto n : bindings_)
621 delete n;
622 for (auto n : verilog_packages)
623 delete n;
624 for (auto n : verilog_globals)
625 delete n;
626 #ifdef WITH_PYTHON
627 RTLIL::Design::get_all_designs()->erase(hashidx_);
628 #endif
629 }
630
631 #ifdef WITH_PYTHON
632 static std::map<unsigned int, RTLIL::Design*> all_designs;
633 std::map<unsigned int, RTLIL::Design*> *RTLIL::Design::get_all_designs(void)
634 {
635 return &all_designs;
636 }
637 #endif
638
639 RTLIL::ObjRange<RTLIL::Module*> RTLIL::Design::modules()
640 {
641 return RTLIL::ObjRange<RTLIL::Module*>(&modules_, &refcount_modules_);
642 }
643
644 RTLIL::Module *RTLIL::Design::module(RTLIL::IdString name)
645 {
646 return modules_.count(name) ? modules_.at(name) : NULL;
647 }
648
649 const RTLIL::Module *RTLIL::Design::module(RTLIL::IdString name) const
650 {
651 return modules_.count(name) ? modules_.at(name) : NULL;
652 }
653
654 RTLIL::Module *RTLIL::Design::top_module()
655 {
656 RTLIL::Module *module = nullptr;
657 int module_count = 0;
658
659 for (auto mod : selected_modules()) {
660 if (mod->get_bool_attribute(ID::top))
661 return mod;
662 module_count++;
663 module = mod;
664 }
665
666 return module_count == 1 ? module : nullptr;
667 }
668
669 void RTLIL::Design::add(RTLIL::Module *module)
670 {
671 log_assert(modules_.count(module->name) == 0);
672 log_assert(refcount_modules_ == 0);
673 modules_[module->name] = module;
674 module->design = this;
675
676 for (auto mon : monitors)
677 mon->notify_module_add(module);
678
679 if (yosys_xtrace) {
680 log("#X# New Module: %s\n", log_id(module));
681 log_backtrace("-X- ", yosys_xtrace-1);
682 }
683 }
684
685 void RTLIL::Design::add(RTLIL::Binding *binding)
686 {
687 log_assert(binding != nullptr);
688 bindings_.push_back(binding);
689 }
690
691 RTLIL::Module *RTLIL::Design::addModule(RTLIL::IdString name)
692 {
693 if (modules_.count(name) != 0)
694 log_error("Attempted to add new module named '%s', but a module by that name already exists\n", name.c_str());
695 log_assert(refcount_modules_ == 0);
696
697 RTLIL::Module *module = new RTLIL::Module;
698 modules_[name] = module;
699 module->design = this;
700 module->name = name;
701
702 for (auto mon : monitors)
703 mon->notify_module_add(module);
704
705 if (yosys_xtrace) {
706 log("#X# New Module: %s\n", log_id(module));
707 log_backtrace("-X- ", yosys_xtrace-1);
708 }
709
710 return module;
711 }
712
713 void RTLIL::Design::scratchpad_unset(const std::string &varname)
714 {
715 scratchpad.erase(varname);
716 }
717
718 void RTLIL::Design::scratchpad_set_int(const std::string &varname, int value)
719 {
720 scratchpad[varname] = stringf("%d", value);
721 }
722
723 void RTLIL::Design::scratchpad_set_bool(const std::string &varname, bool value)
724 {
725 scratchpad[varname] = value ? "true" : "false";
726 }
727
728 void RTLIL::Design::scratchpad_set_string(const std::string &varname, std::string value)
729 {
730 scratchpad[varname] = std::move(value);
731 }
732
733 int RTLIL::Design::scratchpad_get_int(const std::string &varname, int default_value) const
734 {
735 auto it = scratchpad.find(varname);
736 if (it == scratchpad.end())
737 return default_value;
738
739 const std::string &str = it->second;
740
741 if (str == "0" || str == "false")
742 return 0;
743
744 if (str == "1" || str == "true")
745 return 1;
746
747 char *endptr = nullptr;
748 long int parsed_value = strtol(str.c_str(), &endptr, 10);
749 return *endptr ? default_value : parsed_value;
750 }
751
752 bool RTLIL::Design::scratchpad_get_bool(const std::string &varname, bool default_value) const
753 {
754 auto it = scratchpad.find(varname);
755 if (it == scratchpad.end())
756 return default_value;
757
758 const std::string &str = it->second;
759
760 if (str == "0" || str == "false")
761 return false;
762
763 if (str == "1" || str == "true")
764 return true;
765
766 return default_value;
767 }
768
769 std::string RTLIL::Design::scratchpad_get_string(const std::string &varname, const std::string &default_value) const
770 {
771 auto it = scratchpad.find(varname);
772 if (it == scratchpad.end())
773 return default_value;
774
775 return it->second;
776 }
777
778 void RTLIL::Design::remove(RTLIL::Module *module)
779 {
780 for (auto mon : monitors)
781 mon->notify_module_del(module);
782
783 if (yosys_xtrace) {
784 log("#X# Remove Module: %s\n", log_id(module));
785 log_backtrace("-X- ", yosys_xtrace-1);
786 }
787
788 log_assert(modules_.at(module->name) == module);
789 log_assert(refcount_modules_ == 0);
790 modules_.erase(module->name);
791 delete module;
792 }
793
794 void RTLIL::Design::rename(RTLIL::Module *module, RTLIL::IdString new_name)
795 {
796 modules_.erase(module->name);
797 module->name = new_name;
798 add(module);
799 }
800
801 void RTLIL::Design::sort()
802 {
803 scratchpad.sort();
804 modules_.sort(sort_by_id_str());
805 for (auto &it : modules_)
806 it.second->sort();
807 }
808
809 void RTLIL::Design::check()
810 {
811 #ifndef NDEBUG
812 for (auto &it : modules_) {
813 log_assert(this == it.second->design);
814 log_assert(it.first == it.second->name);
815 log_assert(!it.first.empty());
816 it.second->check();
817 }
818 #endif
819 }
820
821 void RTLIL::Design::optimize()
822 {
823 for (auto &it : modules_)
824 it.second->optimize();
825 for (auto &it : selection_stack)
826 it.optimize(this);
827 for (auto &it : selection_vars)
828 it.second.optimize(this);
829 }
830
831 bool RTLIL::Design::selected_module(RTLIL::IdString mod_name) const
832 {
833 if (!selected_active_module.empty() && mod_name != selected_active_module)
834 return false;
835 if (selection_stack.size() == 0)
836 return true;
837 return selection_stack.back().selected_module(mod_name);
838 }
839
840 bool RTLIL::Design::selected_whole_module(RTLIL::IdString mod_name) const
841 {
842 if (!selected_active_module.empty() && mod_name != selected_active_module)
843 return false;
844 if (selection_stack.size() == 0)
845 return true;
846 return selection_stack.back().selected_whole_module(mod_name);
847 }
848
849 bool RTLIL::Design::selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const
850 {
851 if (!selected_active_module.empty() && mod_name != selected_active_module)
852 return false;
853 if (selection_stack.size() == 0)
854 return true;
855 return selection_stack.back().selected_member(mod_name, memb_name);
856 }
857
858 bool RTLIL::Design::selected_module(RTLIL::Module *mod) const
859 {
860 return selected_module(mod->name);
861 }
862
863 bool RTLIL::Design::selected_whole_module(RTLIL::Module *mod) const
864 {
865 return selected_whole_module(mod->name);
866 }
867
868 std::vector<RTLIL::Module*> RTLIL::Design::selected_modules() const
869 {
870 std::vector<RTLIL::Module*> result;
871 result.reserve(modules_.size());
872 for (auto &it : modules_)
873 if (selected_module(it.first) && !it.second->get_blackbox_attribute())
874 result.push_back(it.second);
875 return result;
876 }
877
878 std::vector<RTLIL::Module*> RTLIL::Design::selected_whole_modules() const
879 {
880 std::vector<RTLIL::Module*> result;
881 result.reserve(modules_.size());
882 for (auto &it : modules_)
883 if (selected_whole_module(it.first) && !it.second->get_blackbox_attribute())
884 result.push_back(it.second);
885 return result;
886 }
887
888 std::vector<RTLIL::Module*> RTLIL::Design::selected_whole_modules_warn(bool include_wb) const
889 {
890 std::vector<RTLIL::Module*> result;
891 result.reserve(modules_.size());
892 for (auto &it : modules_)
893 if (it.second->get_blackbox_attribute(include_wb))
894 continue;
895 else if (selected_whole_module(it.first))
896 result.push_back(it.second);
897 else if (selected_module(it.first))
898 log_warning("Ignoring partially selected module %s.\n", log_id(it.first));
899 return result;
900 }
901
902 RTLIL::Module::Module()
903 {
904 static unsigned int hashidx_count = 123456789;
905 hashidx_count = mkhash_xorshift(hashidx_count);
906 hashidx_ = hashidx_count;
907
908 design = nullptr;
909 refcount_wires_ = 0;
910 refcount_cells_ = 0;
911
912 #ifdef WITH_PYTHON
913 RTLIL::Module::get_all_modules()->insert(std::pair<unsigned int, RTLIL::Module*>(hashidx_, this));
914 #endif
915 }
916
917 RTLIL::Module::~Module()
918 {
919 for (auto &pr : wires_)
920 delete pr.second;
921 for (auto &pr : memories)
922 delete pr.second;
923 for (auto &pr : cells_)
924 delete pr.second;
925 for (auto &pr : processes)
926 delete pr.second;
927 for (auto binding : bindings_)
928 delete binding;
929 #ifdef WITH_PYTHON
930 RTLIL::Module::get_all_modules()->erase(hashidx_);
931 #endif
932 }
933
934 #ifdef WITH_PYTHON
935 static std::map<unsigned int, RTLIL::Module*> all_modules;
936 std::map<unsigned int, RTLIL::Module*> *RTLIL::Module::get_all_modules(void)
937 {
938 return &all_modules;
939 }
940 #endif
941
942 void RTLIL::Module::makeblackbox()
943 {
944 pool<RTLIL::Wire*> delwires;
945
946 for (auto it = wires_.begin(); it != wires_.end(); ++it)
947 if (!it->second->port_input && !it->second->port_output)
948 delwires.insert(it->second);
949
950 for (auto it = memories.begin(); it != memories.end(); ++it)
951 delete it->second;
952 memories.clear();
953
954 for (auto it = cells_.begin(); it != cells_.end(); ++it)
955 delete it->second;
956 cells_.clear();
957
958 for (auto it = processes.begin(); it != processes.end(); ++it)
959 delete it->second;
960 processes.clear();
961
962 connections_.clear();
963
964 remove(delwires);
965 set_bool_attribute(ID::blackbox);
966 }
967
968 void RTLIL::Module::expand_interfaces(RTLIL::Design *, const dict<RTLIL::IdString, RTLIL::Module *> &)
969 {
970 log_error("Class doesn't support expand_interfaces (module: `%s')!\n", id2cstr(name));
971 }
972
973 bool RTLIL::Module::reprocess_if_necessary(RTLIL::Design *)
974 {
975 return false;
976 }
977
978 RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, const dict<RTLIL::IdString, RTLIL::Const> &, bool mayfail)
979 {
980 if (mayfail)
981 return RTLIL::IdString();
982 log_error("Module `%s' is used with parameters but is not parametric!\n", id2cstr(name));
983 }
984
985
986 RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, const dict<RTLIL::IdString, RTLIL::Const> &, const dict<RTLIL::IdString, RTLIL::Module*> &, const dict<RTLIL::IdString, RTLIL::IdString> &, bool mayfail)
987 {
988 if (mayfail)
989 return RTLIL::IdString();
990 log_error("Module `%s' is used with parameters but is not parametric!\n", id2cstr(name));
991 }
992
993 size_t RTLIL::Module::count_id(RTLIL::IdString id)
994 {
995 return wires_.count(id) + memories.count(id) + cells_.count(id) + processes.count(id);
996 }
997
998 #ifndef NDEBUG
999 namespace {
1000 struct InternalCellChecker
1001 {
1002 RTLIL::Module *module;
1003 RTLIL::Cell *cell;
1004 pool<RTLIL::IdString> expected_params, expected_ports;
1005
1006 InternalCellChecker(RTLIL::Module *module, RTLIL::Cell *cell) : module(module), cell(cell) { }
1007
1008 void error(int linenr)
1009 {
1010 std::stringstream buf;
1011 RTLIL_BACKEND::dump_cell(buf, " ", cell);
1012
1013 log_error("Found error in internal cell %s%s%s (%s) at %s:%d:\n%s",
1014 module ? module->name.c_str() : "", module ? "." : "",
1015 cell->name.c_str(), cell->type.c_str(), __FILE__, linenr, buf.str().c_str());
1016 }
1017
1018 int param(RTLIL::IdString name)
1019 {
1020 auto it = cell->parameters.find(name);
1021 if (it == cell->parameters.end())
1022 error(__LINE__);
1023 expected_params.insert(name);
1024 return it->second.as_int();
1025 }
1026
1027 int param_bool(RTLIL::IdString name)
1028 {
1029 int v = param(name);
1030 if (GetSize(cell->parameters.at(name)) > 32)
1031 error(__LINE__);
1032 if (v != 0 && v != 1)
1033 error(__LINE__);
1034 return v;
1035 }
1036
1037 int param_bool(RTLIL::IdString name, bool expected)
1038 {
1039 int v = param_bool(name);
1040 if (v != expected)
1041 error(__LINE__);
1042 return v;
1043 }
1044
1045 void param_bits(RTLIL::IdString name, int width)
1046 {
1047 param(name);
1048 if (GetSize(cell->parameters.at(name).bits) != width)
1049 error(__LINE__);
1050 }
1051
1052 void port(RTLIL::IdString name, int width)
1053 {
1054 auto it = cell->connections_.find(name);
1055 if (it == cell->connections_.end())
1056 error(__LINE__);
1057 if (GetSize(it->second) != width)
1058 error(__LINE__);
1059 expected_ports.insert(name);
1060 }
1061
1062 void check_expected(bool check_matched_sign = false)
1063 {
1064 for (auto &para : cell->parameters)
1065 if (expected_params.count(para.first) == 0)
1066 error(__LINE__);
1067 for (auto &conn : cell->connections())
1068 if (expected_ports.count(conn.first) == 0)
1069 error(__LINE__);
1070
1071 if (check_matched_sign) {
1072 log_assert(expected_params.count(ID::A_SIGNED) != 0 && expected_params.count(ID::B_SIGNED) != 0);
1073 bool a_is_signed = cell->parameters.at(ID::A_SIGNED).as_bool();
1074 bool b_is_signed = cell->parameters.at(ID::B_SIGNED).as_bool();
1075 if (a_is_signed != b_is_signed)
1076 error(__LINE__);
1077 }
1078 }
1079
1080 void check()
1081 {
1082 if (!cell->type.begins_with("$") || cell->type.begins_with("$__") || cell->type.begins_with("$paramod") || cell->type.begins_with("$fmcombine") ||
1083 cell->type.begins_with("$verific$") || cell->type.begins_with("$array:") || cell->type.begins_with("$extern:"))
1084 return;
1085
1086 if (cell->type.in(ID($not), ID($pos), ID($neg))) {
1087 param_bool(ID::A_SIGNED);
1088 port(ID::A, param(ID::A_WIDTH));
1089 port(ID::Y, param(ID::Y_WIDTH));
1090 check_expected();
1091 return;
1092 }
1093
1094 if (cell->type.in(ID($and), ID($or), ID($xor), ID($xnor))) {
1095 param_bool(ID::A_SIGNED);
1096 param_bool(ID::B_SIGNED);
1097 port(ID::A, param(ID::A_WIDTH));
1098 port(ID::B, param(ID::B_WIDTH));
1099 port(ID::Y, param(ID::Y_WIDTH));
1100 check_expected(true);
1101 return;
1102 }
1103
1104 if (cell->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor), ID($reduce_bool))) {
1105 param_bool(ID::A_SIGNED);
1106 port(ID::A, param(ID::A_WIDTH));
1107 port(ID::Y, param(ID::Y_WIDTH));
1108 check_expected();
1109 return;
1110 }
1111
1112 if (cell->type.in(ID($shl), ID($shr), ID($sshl), ID($sshr))) {
1113 param_bool(ID::A_SIGNED);
1114 param_bool(ID::B_SIGNED, /*expected=*/false);
1115 port(ID::A, param(ID::A_WIDTH));
1116 port(ID::B, param(ID::B_WIDTH));
1117 port(ID::Y, param(ID::Y_WIDTH));
1118 check_expected(/*check_matched_sign=*/false);
1119 return;
1120 }
1121
1122 if (cell->type.in(ID($shift), ID($shiftx))) {
1123 if (cell->type == ID($shiftx)) {
1124 param_bool(ID::A_SIGNED, /*expected=*/false);
1125 } else {
1126 param_bool(ID::A_SIGNED);
1127 }
1128 param_bool(ID::B_SIGNED);
1129 port(ID::A, param(ID::A_WIDTH));
1130 port(ID::B, param(ID::B_WIDTH));
1131 port(ID::Y, param(ID::Y_WIDTH));
1132 check_expected(/*check_matched_sign=*/false);
1133 return;
1134 }
1135
1136 if (cell->type.in(ID($lt), ID($le), ID($eq), ID($ne), ID($eqx), ID($nex), ID($ge), ID($gt))) {
1137 param_bool(ID::A_SIGNED);
1138 param_bool(ID::B_SIGNED);
1139 port(ID::A, param(ID::A_WIDTH));
1140 port(ID::B, param(ID::B_WIDTH));
1141 port(ID::Y, param(ID::Y_WIDTH));
1142 check_expected(true);
1143 return;
1144 }
1145
1146 if (cell->type.in(ID($add), ID($sub), ID($mul), ID($div), ID($mod), ID($divfloor), ID($modfloor), ID($pow))) {
1147 param_bool(ID::A_SIGNED);
1148 param_bool(ID::B_SIGNED);
1149 port(ID::A, param(ID::A_WIDTH));
1150 port(ID::B, param(ID::B_WIDTH));
1151 port(ID::Y, param(ID::Y_WIDTH));
1152 check_expected(cell->type != ID($pow));
1153 return;
1154 }
1155
1156 if (cell->type == ID($fa)) {
1157 port(ID::A, param(ID::WIDTH));
1158 port(ID::B, param(ID::WIDTH));
1159 port(ID::C, param(ID::WIDTH));
1160 port(ID::X, param(ID::WIDTH));
1161 port(ID::Y, param(ID::WIDTH));
1162 check_expected();
1163 return;
1164 }
1165
1166 if (cell->type == ID($lcu)) {
1167 port(ID::P, param(ID::WIDTH));
1168 port(ID::G, param(ID::WIDTH));
1169 port(ID::CI, 1);
1170 port(ID::CO, param(ID::WIDTH));
1171 check_expected();
1172 return;
1173 }
1174
1175 if (cell->type == ID($alu)) {
1176 param_bool(ID::A_SIGNED);
1177 param_bool(ID::B_SIGNED);
1178 port(ID::A, param(ID::A_WIDTH));
1179 port(ID::B, param(ID::B_WIDTH));
1180 port(ID::CI, 1);
1181 port(ID::BI, 1);
1182 port(ID::X, param(ID::Y_WIDTH));
1183 port(ID::Y, param(ID::Y_WIDTH));
1184 port(ID::CO, param(ID::Y_WIDTH));
1185 check_expected(true);
1186 return;
1187 }
1188
1189 if (cell->type == ID($macc)) {
1190 param(ID::CONFIG);
1191 param(ID::CONFIG_WIDTH);
1192 port(ID::A, param(ID::A_WIDTH));
1193 port(ID::B, param(ID::B_WIDTH));
1194 port(ID::Y, param(ID::Y_WIDTH));
1195 check_expected();
1196 Macc().from_cell(cell);
1197 return;
1198 }
1199
1200 if (cell->type == ID($logic_not)) {
1201 param_bool(ID::A_SIGNED);
1202 port(ID::A, param(ID::A_WIDTH));
1203 port(ID::Y, param(ID::Y_WIDTH));
1204 check_expected();
1205 return;
1206 }
1207
1208 if (cell->type.in(ID($logic_and), ID($logic_or))) {
1209 param_bool(ID::A_SIGNED);
1210 param_bool(ID::B_SIGNED);
1211 port(ID::A, param(ID::A_WIDTH));
1212 port(ID::B, param(ID::B_WIDTH));
1213 port(ID::Y, param(ID::Y_WIDTH));
1214 check_expected(/*check_matched_sign=*/false);
1215 return;
1216 }
1217
1218 if (cell->type == ID($slice)) {
1219 param(ID::OFFSET);
1220 port(ID::A, param(ID::A_WIDTH));
1221 port(ID::Y, param(ID::Y_WIDTH));
1222 if (param(ID::OFFSET) + param(ID::Y_WIDTH) > param(ID::A_WIDTH))
1223 error(__LINE__);
1224 check_expected();
1225 return;
1226 }
1227
1228 if (cell->type == ID($concat)) {
1229 port(ID::A, param(ID::A_WIDTH));
1230 port(ID::B, param(ID::B_WIDTH));
1231 port(ID::Y, param(ID::A_WIDTH) + param(ID::B_WIDTH));
1232 check_expected();
1233 return;
1234 }
1235
1236 if (cell->type == ID($mux)) {
1237 port(ID::A, param(ID::WIDTH));
1238 port(ID::B, param(ID::WIDTH));
1239 port(ID::S, 1);
1240 port(ID::Y, param(ID::WIDTH));
1241 check_expected();
1242 return;
1243 }
1244
1245 if (cell->type == ID($pmux)) {
1246 port(ID::A, param(ID::WIDTH));
1247 port(ID::B, param(ID::WIDTH) * param(ID::S_WIDTH));
1248 port(ID::S, param(ID::S_WIDTH));
1249 port(ID::Y, param(ID::WIDTH));
1250 check_expected();
1251 return;
1252 }
1253
1254 if (cell->type == ID($lut)) {
1255 param(ID::LUT);
1256 port(ID::A, param(ID::WIDTH));
1257 port(ID::Y, 1);
1258 check_expected();
1259 return;
1260 }
1261
1262 if (cell->type == ID($sop)) {
1263 param(ID::DEPTH);
1264 param(ID::TABLE);
1265 port(ID::A, param(ID::WIDTH));
1266 port(ID::Y, 1);
1267 check_expected();
1268 return;
1269 }
1270
1271 if (cell->type == ID($sr)) {
1272 param_bool(ID::SET_POLARITY);
1273 param_bool(ID::CLR_POLARITY);
1274 port(ID::SET, param(ID::WIDTH));
1275 port(ID::CLR, param(ID::WIDTH));
1276 port(ID::Q, param(ID::WIDTH));
1277 check_expected();
1278 return;
1279 }
1280
1281 if (cell->type == ID($ff)) {
1282 port(ID::D, param(ID::WIDTH));
1283 port(ID::Q, param(ID::WIDTH));
1284 check_expected();
1285 return;
1286 }
1287
1288 if (cell->type == ID($dff)) {
1289 param_bool(ID::CLK_POLARITY);
1290 port(ID::CLK, 1);
1291 port(ID::D, param(ID::WIDTH));
1292 port(ID::Q, param(ID::WIDTH));
1293 check_expected();
1294 return;
1295 }
1296
1297 if (cell->type == ID($dffe)) {
1298 param_bool(ID::CLK_POLARITY);
1299 param_bool(ID::EN_POLARITY);
1300 port(ID::CLK, 1);
1301 port(ID::EN, 1);
1302 port(ID::D, param(ID::WIDTH));
1303 port(ID::Q, param(ID::WIDTH));
1304 check_expected();
1305 return;
1306 }
1307
1308 if (cell->type == ID($dffsr)) {
1309 param_bool(ID::CLK_POLARITY);
1310 param_bool(ID::SET_POLARITY);
1311 param_bool(ID::CLR_POLARITY);
1312 port(ID::CLK, 1);
1313 port(ID::SET, param(ID::WIDTH));
1314 port(ID::CLR, param(ID::WIDTH));
1315 port(ID::D, param(ID::WIDTH));
1316 port(ID::Q, param(ID::WIDTH));
1317 check_expected();
1318 return;
1319 }
1320
1321 if (cell->type == ID($dffsre)) {
1322 param_bool(ID::CLK_POLARITY);
1323 param_bool(ID::SET_POLARITY);
1324 param_bool(ID::CLR_POLARITY);
1325 param_bool(ID::EN_POLARITY);
1326 port(ID::CLK, 1);
1327 port(ID::EN, 1);
1328 port(ID::SET, param(ID::WIDTH));
1329 port(ID::CLR, param(ID::WIDTH));
1330 port(ID::D, param(ID::WIDTH));
1331 port(ID::Q, param(ID::WIDTH));
1332 check_expected();
1333 return;
1334 }
1335
1336 if (cell->type == ID($adff)) {
1337 param_bool(ID::CLK_POLARITY);
1338 param_bool(ID::ARST_POLARITY);
1339 param_bits(ID::ARST_VALUE, param(ID::WIDTH));
1340 port(ID::CLK, 1);
1341 port(ID::ARST, 1);
1342 port(ID::D, param(ID::WIDTH));
1343 port(ID::Q, param(ID::WIDTH));
1344 check_expected();
1345 return;
1346 }
1347
1348 if (cell->type == ID($sdff)) {
1349 param_bool(ID::CLK_POLARITY);
1350 param_bool(ID::SRST_POLARITY);
1351 param_bits(ID::SRST_VALUE, param(ID::WIDTH));
1352 port(ID::CLK, 1);
1353 port(ID::SRST, 1);
1354 port(ID::D, param(ID::WIDTH));
1355 port(ID::Q, param(ID::WIDTH));
1356 check_expected();
1357 return;
1358 }
1359
1360 if (cell->type.in(ID($sdffe), ID($sdffce))) {
1361 param_bool(ID::CLK_POLARITY);
1362 param_bool(ID::EN_POLARITY);
1363 param_bool(ID::SRST_POLARITY);
1364 param_bits(ID::SRST_VALUE, param(ID::WIDTH));
1365 port(ID::CLK, 1);
1366 port(ID::EN, 1);
1367 port(ID::SRST, 1);
1368 port(ID::D, param(ID::WIDTH));
1369 port(ID::Q, param(ID::WIDTH));
1370 check_expected();
1371 return;
1372 }
1373
1374 if (cell->type == ID($adffe)) {
1375 param_bool(ID::CLK_POLARITY);
1376 param_bool(ID::EN_POLARITY);
1377 param_bool(ID::ARST_POLARITY);
1378 param_bits(ID::ARST_VALUE, param(ID::WIDTH));
1379 port(ID::CLK, 1);
1380 port(ID::EN, 1);
1381 port(ID::ARST, 1);
1382 port(ID::D, param(ID::WIDTH));
1383 port(ID::Q, param(ID::WIDTH));
1384 check_expected();
1385 return;
1386 }
1387
1388 if (cell->type == ID($aldff)) {
1389 param_bool(ID::CLK_POLARITY);
1390 param_bool(ID::ALOAD_POLARITY);
1391 port(ID::CLK, 1);
1392 port(ID::ALOAD, 1);
1393 port(ID::D, param(ID::WIDTH));
1394 port(ID::AD, param(ID::WIDTH));
1395 port(ID::Q, param(ID::WIDTH));
1396 check_expected();
1397 return;
1398 }
1399
1400 if (cell->type == ID($aldffe)) {
1401 param_bool(ID::CLK_POLARITY);
1402 param_bool(ID::EN_POLARITY);
1403 param_bool(ID::ALOAD_POLARITY);
1404 port(ID::CLK, 1);
1405 port(ID::EN, 1);
1406 port(ID::ALOAD, 1);
1407 port(ID::D, param(ID::WIDTH));
1408 port(ID::AD, param(ID::WIDTH));
1409 port(ID::Q, param(ID::WIDTH));
1410 check_expected();
1411 return;
1412 }
1413
1414 if (cell->type == ID($dlatch)) {
1415 param_bool(ID::EN_POLARITY);
1416 port(ID::EN, 1);
1417 port(ID::D, param(ID::WIDTH));
1418 port(ID::Q, param(ID::WIDTH));
1419 check_expected();
1420 return;
1421 }
1422
1423 if (cell->type == ID($adlatch)) {
1424 param_bool(ID::EN_POLARITY);
1425 param_bool(ID::ARST_POLARITY);
1426 param_bits(ID::ARST_VALUE, param(ID::WIDTH));
1427 port(ID::EN, 1);
1428 port(ID::ARST, 1);
1429 port(ID::D, param(ID::WIDTH));
1430 port(ID::Q, param(ID::WIDTH));
1431 check_expected();
1432 return;
1433 }
1434
1435 if (cell->type == ID($dlatchsr)) {
1436 param_bool(ID::EN_POLARITY);
1437 param_bool(ID::SET_POLARITY);
1438 param_bool(ID::CLR_POLARITY);
1439 port(ID::EN, 1);
1440 port(ID::SET, param(ID::WIDTH));
1441 port(ID::CLR, param(ID::WIDTH));
1442 port(ID::D, param(ID::WIDTH));
1443 port(ID::Q, param(ID::WIDTH));
1444 check_expected();
1445 return;
1446 }
1447
1448 if (cell->type == ID($fsm)) {
1449 param(ID::NAME);
1450 param_bool(ID::CLK_POLARITY);
1451 param_bool(ID::ARST_POLARITY);
1452 param(ID::STATE_BITS);
1453 param(ID::STATE_NUM);
1454 param(ID::STATE_NUM_LOG2);
1455 param(ID::STATE_RST);
1456 param_bits(ID::STATE_TABLE, param(ID::STATE_BITS) * param(ID::STATE_NUM));
1457 param(ID::TRANS_NUM);
1458 param_bits(ID::TRANS_TABLE, param(ID::TRANS_NUM) * (2*param(ID::STATE_NUM_LOG2) + param(ID::CTRL_IN_WIDTH) + param(ID::CTRL_OUT_WIDTH)));
1459 port(ID::CLK, 1);
1460 port(ID::ARST, 1);
1461 port(ID::CTRL_IN, param(ID::CTRL_IN_WIDTH));
1462 port(ID::CTRL_OUT, param(ID::CTRL_OUT_WIDTH));
1463 check_expected();
1464 return;
1465 }
1466
1467 if (cell->type == ID($memrd)) {
1468 param(ID::MEMID);
1469 param_bool(ID::CLK_ENABLE);
1470 param_bool(ID::CLK_POLARITY);
1471 param_bool(ID::TRANSPARENT);
1472 port(ID::CLK, 1);
1473 port(ID::EN, 1);
1474 port(ID::ADDR, param(ID::ABITS));
1475 port(ID::DATA, param(ID::WIDTH));
1476 check_expected();
1477 return;
1478 }
1479
1480 if (cell->type == ID($memrd_v2)) {
1481 param(ID::MEMID);
1482 param_bool(ID::CLK_ENABLE);
1483 param_bool(ID::CLK_POLARITY);
1484 param(ID::TRANSPARENCY_MASK);
1485 param(ID::COLLISION_X_MASK);
1486 param_bool(ID::CE_OVER_SRST);
1487 param_bits(ID::ARST_VALUE, param(ID::WIDTH));
1488 param_bits(ID::SRST_VALUE, param(ID::WIDTH));
1489 param_bits(ID::INIT_VALUE, param(ID::WIDTH));
1490 port(ID::CLK, 1);
1491 port(ID::EN, 1);
1492 port(ID::ARST, 1);
1493 port(ID::SRST, 1);
1494 port(ID::ADDR, param(ID::ABITS));
1495 port(ID::DATA, param(ID::WIDTH));
1496 check_expected();
1497 return;
1498 }
1499
1500 if (cell->type == ID($memwr)) {
1501 param(ID::MEMID);
1502 param_bool(ID::CLK_ENABLE);
1503 param_bool(ID::CLK_POLARITY);
1504 param(ID::PRIORITY);
1505 port(ID::CLK, 1);
1506 port(ID::EN, param(ID::WIDTH));
1507 port(ID::ADDR, param(ID::ABITS));
1508 port(ID::DATA, param(ID::WIDTH));
1509 check_expected();
1510 return;
1511 }
1512
1513 if (cell->type == ID($memwr_v2)) {
1514 param(ID::MEMID);
1515 param_bool(ID::CLK_ENABLE);
1516 param_bool(ID::CLK_POLARITY);
1517 param(ID::PORTID);
1518 param(ID::PRIORITY_MASK);
1519 port(ID::CLK, 1);
1520 port(ID::EN, param(ID::WIDTH));
1521 port(ID::ADDR, param(ID::ABITS));
1522 port(ID::DATA, param(ID::WIDTH));
1523 check_expected();
1524 return;
1525 }
1526
1527 if (cell->type == ID($meminit)) {
1528 param(ID::MEMID);
1529 param(ID::PRIORITY);
1530 port(ID::ADDR, param(ID::ABITS));
1531 port(ID::DATA, param(ID::WIDTH) * param(ID::WORDS));
1532 check_expected();
1533 return;
1534 }
1535
1536 if (cell->type == ID($meminit_v2)) {
1537 param(ID::MEMID);
1538 param(ID::PRIORITY);
1539 port(ID::ADDR, param(ID::ABITS));
1540 port(ID::DATA, param(ID::WIDTH) * param(ID::WORDS));
1541 port(ID::EN, param(ID::WIDTH));
1542 check_expected();
1543 return;
1544 }
1545
1546 if (cell->type == ID($mem)) {
1547 param(ID::MEMID);
1548 param(ID::SIZE);
1549 param(ID::OFFSET);
1550 param(ID::INIT);
1551 param_bits(ID::RD_CLK_ENABLE, max(1, param(ID::RD_PORTS)));
1552 param_bits(ID::RD_CLK_POLARITY, max(1, param(ID::RD_PORTS)));
1553 param_bits(ID::RD_TRANSPARENT, max(1, param(ID::RD_PORTS)));
1554 param_bits(ID::WR_CLK_ENABLE, max(1, param(ID::WR_PORTS)));
1555 param_bits(ID::WR_CLK_POLARITY, max(1, param(ID::WR_PORTS)));
1556 port(ID::RD_CLK, param(ID::RD_PORTS));
1557 port(ID::RD_EN, param(ID::RD_PORTS));
1558 port(ID::RD_ADDR, param(ID::RD_PORTS) * param(ID::ABITS));
1559 port(ID::RD_DATA, param(ID::RD_PORTS) * param(ID::WIDTH));
1560 port(ID::WR_CLK, param(ID::WR_PORTS));
1561 port(ID::WR_EN, param(ID::WR_PORTS) * param(ID::WIDTH));
1562 port(ID::WR_ADDR, param(ID::WR_PORTS) * param(ID::ABITS));
1563 port(ID::WR_DATA, param(ID::WR_PORTS) * param(ID::WIDTH));
1564 check_expected();
1565 return;
1566 }
1567
1568 if (cell->type == ID($mem_v2)) {
1569 param(ID::MEMID);
1570 param(ID::SIZE);
1571 param(ID::OFFSET);
1572 param(ID::INIT);
1573 param_bits(ID::RD_CLK_ENABLE, max(1, param(ID::RD_PORTS)));
1574 param_bits(ID::RD_CLK_POLARITY, max(1, param(ID::RD_PORTS)));
1575 param_bits(ID::RD_TRANSPARENCY_MASK, max(1, param(ID::RD_PORTS) * param(ID::WR_PORTS)));
1576 param_bits(ID::RD_COLLISION_X_MASK, max(1, param(ID::RD_PORTS) * param(ID::WR_PORTS)));
1577 param_bits(ID::RD_WIDE_CONTINUATION, max(1, param(ID::RD_PORTS)));
1578 param_bits(ID::RD_CE_OVER_SRST, max(1, param(ID::RD_PORTS)));
1579 param_bits(ID::RD_ARST_VALUE, param(ID::RD_PORTS) * param(ID::WIDTH));
1580 param_bits(ID::RD_SRST_VALUE, param(ID::RD_PORTS) * param(ID::WIDTH));
1581 param_bits(ID::RD_INIT_VALUE, param(ID::RD_PORTS) * param(ID::WIDTH));
1582 param_bits(ID::WR_CLK_ENABLE, max(1, param(ID::WR_PORTS)));
1583 param_bits(ID::WR_CLK_POLARITY, max(1, param(ID::WR_PORTS)));
1584 param_bits(ID::WR_WIDE_CONTINUATION, max(1, param(ID::WR_PORTS)));
1585 param_bits(ID::WR_PRIORITY_MASK, max(1, param(ID::WR_PORTS) * param(ID::WR_PORTS)));
1586 port(ID::RD_CLK, param(ID::RD_PORTS));
1587 port(ID::RD_EN, param(ID::RD_PORTS));
1588 port(ID::RD_ARST, param(ID::RD_PORTS));
1589 port(ID::RD_SRST, param(ID::RD_PORTS));
1590 port(ID::RD_ADDR, param(ID::RD_PORTS) * param(ID::ABITS));
1591 port(ID::RD_DATA, param(ID::RD_PORTS) * param(ID::WIDTH));
1592 port(ID::WR_CLK, param(ID::WR_PORTS));
1593 port(ID::WR_EN, param(ID::WR_PORTS) * param(ID::WIDTH));
1594 port(ID::WR_ADDR, param(ID::WR_PORTS) * param(ID::ABITS));
1595 port(ID::WR_DATA, param(ID::WR_PORTS) * param(ID::WIDTH));
1596 check_expected();
1597 return;
1598 }
1599
1600 if (cell->type == ID($tribuf)) {
1601 port(ID::A, param(ID::WIDTH));
1602 port(ID::Y, param(ID::WIDTH));
1603 port(ID::EN, 1);
1604 check_expected();
1605 return;
1606 }
1607
1608 if (cell->type.in(ID($assert), ID($assume), ID($live), ID($fair), ID($cover))) {
1609 port(ID::A, 1);
1610 port(ID::EN, 1);
1611 check_expected();
1612 return;
1613 }
1614
1615 if (cell->type == ID($initstate)) {
1616 port(ID::Y, 1);
1617 check_expected();
1618 return;
1619 }
1620
1621 if (cell->type.in(ID($anyconst), ID($anyseq), ID($allconst), ID($allseq))) {
1622 port(ID::Y, param(ID::WIDTH));
1623 check_expected();
1624 return;
1625 }
1626
1627 if (cell->type == ID($equiv)) {
1628 port(ID::A, 1);
1629 port(ID::B, 1);
1630 port(ID::Y, 1);
1631 check_expected();
1632 return;
1633 }
1634
1635 if (cell->type.in(ID($specify2), ID($specify3))) {
1636 param_bool(ID::FULL);
1637 param_bool(ID::SRC_DST_PEN);
1638 param_bool(ID::SRC_DST_POL);
1639 param(ID::T_RISE_MIN);
1640 param(ID::T_RISE_TYP);
1641 param(ID::T_RISE_MAX);
1642 param(ID::T_FALL_MIN);
1643 param(ID::T_FALL_TYP);
1644 param(ID::T_FALL_MAX);
1645 port(ID::EN, 1);
1646 port(ID::SRC, param(ID::SRC_WIDTH));
1647 port(ID::DST, param(ID::DST_WIDTH));
1648 if (cell->type == ID($specify3)) {
1649 param_bool(ID::EDGE_EN);
1650 param_bool(ID::EDGE_POL);
1651 param_bool(ID::DAT_DST_PEN);
1652 param_bool(ID::DAT_DST_POL);
1653 port(ID::DAT, param(ID::DST_WIDTH));
1654 }
1655 check_expected();
1656 return;
1657 }
1658
1659 if (cell->type == ID($specrule)) {
1660 param(ID::TYPE);
1661 param_bool(ID::SRC_PEN);
1662 param_bool(ID::SRC_POL);
1663 param_bool(ID::DST_PEN);
1664 param_bool(ID::DST_POL);
1665 param(ID::T_LIMIT_MIN);
1666 param(ID::T_LIMIT_TYP);
1667 param(ID::T_LIMIT_MAX);
1668 param(ID::T_LIMIT2_MIN);
1669 param(ID::T_LIMIT2_TYP);
1670 param(ID::T_LIMIT2_MAX);
1671 port(ID::SRC_EN, 1);
1672 port(ID::DST_EN, 1);
1673 port(ID::SRC, param(ID::SRC_WIDTH));
1674 port(ID::DST, param(ID::DST_WIDTH));
1675 check_expected();
1676 return;
1677 }
1678
1679 if (cell->type == ID($_BUF_)) { port(ID::A,1); port(ID::Y,1); check_expected(); return; }
1680 if (cell->type == ID($_NOT_)) { port(ID::A,1); port(ID::Y,1); check_expected(); return; }
1681 if (cell->type == ID($_AND_)) { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; }
1682 if (cell->type == ID($_NAND_)) { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; }
1683 if (cell->type == ID($_OR_)) { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; }
1684 if (cell->type == ID($_NOR_)) { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; }
1685 if (cell->type == ID($_XOR_)) { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; }
1686 if (cell->type == ID($_XNOR_)) { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; }
1687 if (cell->type == ID($_ANDNOT_)) { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; }
1688 if (cell->type == ID($_ORNOT_)) { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; }
1689 if (cell->type == ID($_MUX_)) { port(ID::A,1); port(ID::B,1); port(ID::S,1); port(ID::Y,1); check_expected(); return; }
1690 if (cell->type == ID($_NMUX_)) { port(ID::A,1); port(ID::B,1); port(ID::S,1); port(ID::Y,1); check_expected(); return; }
1691 if (cell->type == ID($_AOI3_)) { port(ID::A,1); port(ID::B,1); port(ID::C,1); port(ID::Y,1); check_expected(); return; }
1692 if (cell->type == ID($_OAI3_)) { port(ID::A,1); port(ID::B,1); port(ID::C,1); port(ID::Y,1); check_expected(); return; }
1693 if (cell->type == ID($_AOI4_)) { port(ID::A,1); port(ID::B,1); port(ID::C,1); port(ID::D,1); port(ID::Y,1); check_expected(); return; }
1694 if (cell->type == ID($_OAI4_)) { port(ID::A,1); port(ID::B,1); port(ID::C,1); port(ID::D,1); port(ID::Y,1); check_expected(); return; }
1695
1696 if (cell->type == ID($_TBUF_)) { port(ID::A,1); port(ID::Y,1); port(ID::E,1); check_expected(); return; }
1697
1698 if (cell->type == ID($_MUX4_)) { port(ID::A,1); port(ID::B,1); port(ID::C,1); port(ID::D,1); port(ID::S,1); port(ID::T,1); port(ID::Y,1); check_expected(); return; }
1699 if (cell->type == ID($_MUX8_)) { port(ID::A,1); port(ID::B,1); port(ID::C,1); port(ID::D,1); port(ID::E,1); port(ID::F,1); port(ID::G,1); port(ID::H,1); port(ID::S,1); port(ID::T,1); port(ID::U,1); port(ID::Y,1); check_expected(); return; }
1700 if (cell->type == ID($_MUX16_)) { port(ID::A,1); port(ID::B,1); port(ID::C,1); port(ID::D,1); port(ID::E,1); port(ID::F,1); port(ID::G,1); port(ID::H,1); port(ID::I,1); port(ID::J,1); port(ID::K,1); port(ID::L,1); port(ID::M,1); port(ID::N,1); port(ID::O,1); port(ID::P,1); port(ID::S,1); port(ID::T,1); port(ID::U,1); port(ID::V,1); port(ID::Y,1); check_expected(); return; }
1701
1702 if (cell->type.in(ID($_SR_NN_), ID($_SR_NP_), ID($_SR_PN_), ID($_SR_PP_)))
1703 { port(ID::S,1); port(ID::R,1); port(ID::Q,1); check_expected(); return; }
1704
1705 if (cell->type == ID($_FF_)) { port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1706
1707 if (cell->type.in(ID($_DFF_N_), ID($_DFF_P_)))
1708 { port(ID::D,1); port(ID::Q,1); port(ID::C,1); check_expected(); return; }
1709
1710 if (cell->type.in(ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_)))
1711 { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::E,1); check_expected(); return; }
1712
1713 if (cell->type.in(
1714 ID($_DFF_NN0_), ID($_DFF_NN1_), ID($_DFF_NP0_), ID($_DFF_NP1_),
1715 ID($_DFF_PN0_), ID($_DFF_PN1_), ID($_DFF_PP0_), ID($_DFF_PP1_)))
1716 { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::R,1); check_expected(); return; }
1717
1718 if (cell->type.in(
1719 ID($_DFFE_NN0N_), ID($_DFFE_NN0P_), ID($_DFFE_NN1N_), ID($_DFFE_NN1P_),
1720 ID($_DFFE_NP0N_), ID($_DFFE_NP0P_), ID($_DFFE_NP1N_), ID($_DFFE_NP1P_),
1721 ID($_DFFE_PN0N_), ID($_DFFE_PN0P_), ID($_DFFE_PN1N_), ID($_DFFE_PN1P_),
1722 ID($_DFFE_PP0N_), ID($_DFFE_PP0P_), ID($_DFFE_PP1N_), ID($_DFFE_PP1P_)))
1723 { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::R,1); port(ID::E,1); check_expected(); return; }
1724
1725 if (cell->type.in(
1726 ID($_ALDFF_NN_), ID($_ALDFF_NP_), ID($_ALDFF_PN_), ID($_ALDFF_PP_)))
1727 { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::L,1); port(ID::AD,1); check_expected(); return; }
1728
1729 if (cell->type.in(
1730 ID($_ALDFFE_NNN_), ID($_ALDFFE_NNP_), ID($_ALDFFE_NPN_), ID($_ALDFFE_NPP_),
1731 ID($_ALDFFE_PNN_), ID($_ALDFFE_PNP_), ID($_ALDFFE_PPN_), ID($_ALDFFE_PPP_)))
1732 { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::L,1); port(ID::AD,1); port(ID::E,1); check_expected(); return; }
1733
1734 if (cell->type.in(
1735 ID($_DFFSR_NNN_), ID($_DFFSR_NNP_), ID($_DFFSR_NPN_), ID($_DFFSR_NPP_),
1736 ID($_DFFSR_PNN_), ID($_DFFSR_PNP_), ID($_DFFSR_PPN_), ID($_DFFSR_PPP_)))
1737 { port(ID::C,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1738
1739 if (cell->type.in(
1740 ID($_DFFSRE_NNNN_), ID($_DFFSRE_NNNP_), ID($_DFFSRE_NNPN_), ID($_DFFSRE_NNPP_),
1741 ID($_DFFSRE_NPNN_), ID($_DFFSRE_NPNP_), ID($_DFFSRE_NPPN_), ID($_DFFSRE_NPPP_),
1742 ID($_DFFSRE_PNNN_), ID($_DFFSRE_PNNP_), ID($_DFFSRE_PNPN_), ID($_DFFSRE_PNPP_),
1743 ID($_DFFSRE_PPNN_), ID($_DFFSRE_PPNP_), ID($_DFFSRE_PPPN_), ID($_DFFSRE_PPPP_)))
1744 { port(ID::C,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::E,1); port(ID::Q,1); check_expected(); return; }
1745
1746 if (cell->type.in(
1747 ID($_SDFF_NN0_), ID($_SDFF_NN1_), ID($_SDFF_NP0_), ID($_SDFF_NP1_),
1748 ID($_SDFF_PN0_), ID($_SDFF_PN1_), ID($_SDFF_PP0_), ID($_SDFF_PP1_)))
1749 { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::R,1); check_expected(); return; }
1750
1751 if (cell->type.in(
1752 ID($_SDFFE_NN0N_), ID($_SDFFE_NN0P_), ID($_SDFFE_NN1N_), ID($_SDFFE_NN1P_),
1753 ID($_SDFFE_NP0N_), ID($_SDFFE_NP0P_), ID($_SDFFE_NP1N_), ID($_SDFFE_NP1P_),
1754 ID($_SDFFE_PN0N_), ID($_SDFFE_PN0P_), ID($_SDFFE_PN1N_), ID($_SDFFE_PN1P_),
1755 ID($_SDFFE_PP0N_), ID($_SDFFE_PP0P_), ID($_SDFFE_PP1N_), ID($_SDFFE_PP1P_),
1756 ID($_SDFFCE_NN0N_), ID($_SDFFCE_NN0P_), ID($_SDFFCE_NN1N_), ID($_SDFFCE_NN1P_),
1757 ID($_SDFFCE_NP0N_), ID($_SDFFCE_NP0P_), ID($_SDFFCE_NP1N_), ID($_SDFFCE_NP1P_),
1758 ID($_SDFFCE_PN0N_), ID($_SDFFCE_PN0P_), ID($_SDFFCE_PN1N_), ID($_SDFFCE_PN1P_),
1759 ID($_SDFFCE_PP0N_), ID($_SDFFCE_PP0P_), ID($_SDFFCE_PP1N_), ID($_SDFFCE_PP1P_)))
1760 { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::R,1); port(ID::E,1); check_expected(); return; }
1761
1762 if (cell->type.in(ID($_DLATCH_N_), ID($_DLATCH_P_)))
1763 { port(ID::E,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1764
1765 if (cell->type.in(
1766 ID($_DLATCH_NN0_), ID($_DLATCH_NN1_), ID($_DLATCH_NP0_), ID($_DLATCH_NP1_),
1767 ID($_DLATCH_PN0_), ID($_DLATCH_PN1_), ID($_DLATCH_PP0_), ID($_DLATCH_PP1_)))
1768 { port(ID::E,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1769
1770 if (cell->type.in(
1771 ID($_DLATCHSR_NNN_), ID($_DLATCHSR_NNP_), ID($_DLATCHSR_NPN_), ID($_DLATCHSR_NPP_),
1772 ID($_DLATCHSR_PNN_), ID($_DLATCHSR_PNP_), ID($_DLATCHSR_PPN_), ID($_DLATCHSR_PPP_)))
1773 { port(ID::E,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1774
1775 error(__LINE__);
1776 }
1777 };
1778 }
1779 #endif
1780
1781 void RTLIL::Module::sort()
1782 {
1783 wires_.sort(sort_by_id_str());
1784 cells_.sort(sort_by_id_str());
1785 parameter_default_values.sort(sort_by_id_str());
1786 memories.sort(sort_by_id_str());
1787 processes.sort(sort_by_id_str());
1788 for (auto &it : cells_)
1789 it.second->sort();
1790 for (auto &it : wires_)
1791 it.second->attributes.sort(sort_by_id_str());
1792 for (auto &it : memories)
1793 it.second->attributes.sort(sort_by_id_str());
1794 }
1795
1796 void RTLIL::Module::check()
1797 {
1798 #ifndef NDEBUG
1799 std::vector<bool> ports_declared;
1800 for (auto &it : wires_) {
1801 log_assert(this == it.second->module);
1802 log_assert(it.first == it.second->name);
1803 log_assert(!it.first.empty());
1804 log_assert(it.second->width >= 0);
1805 log_assert(it.second->port_id >= 0);
1806 for (auto &it2 : it.second->attributes)
1807 log_assert(!it2.first.empty());
1808 if (it.second->port_id) {
1809 log_assert(GetSize(ports) >= it.second->port_id);
1810 log_assert(ports.at(it.second->port_id-1) == it.first);
1811 log_assert(it.second->port_input || it.second->port_output);
1812 if (GetSize(ports_declared) < it.second->port_id)
1813 ports_declared.resize(it.second->port_id);
1814 log_assert(ports_declared[it.second->port_id-1] == false);
1815 ports_declared[it.second->port_id-1] = true;
1816 } else
1817 log_assert(!it.second->port_input && !it.second->port_output);
1818 }
1819 for (auto port_declared : ports_declared)
1820 log_assert(port_declared == true);
1821 log_assert(GetSize(ports) == GetSize(ports_declared));
1822
1823 for (auto &it : memories) {
1824 log_assert(it.first == it.second->name);
1825 log_assert(!it.first.empty());
1826 log_assert(it.second->width >= 0);
1827 log_assert(it.second->size >= 0);
1828 for (auto &it2 : it.second->attributes)
1829 log_assert(!it2.first.empty());
1830 }
1831
1832 for (auto &it : cells_) {
1833 log_assert(this == it.second->module);
1834 log_assert(it.first == it.second->name);
1835 log_assert(!it.first.empty());
1836 log_assert(!it.second->type.empty());
1837 for (auto &it2 : it.second->connections()) {
1838 log_assert(!it2.first.empty());
1839 it2.second.check(this);
1840 }
1841 for (auto &it2 : it.second->attributes)
1842 log_assert(!it2.first.empty());
1843 for (auto &it2 : it.second->parameters)
1844 log_assert(!it2.first.empty());
1845 InternalCellChecker checker(this, it.second);
1846 checker.check();
1847 }
1848
1849 for (auto &it : processes) {
1850 log_assert(it.first == it.second->name);
1851 log_assert(!it.first.empty());
1852 log_assert(it.second->root_case.compare.empty());
1853 std::vector<CaseRule*> all_cases = {&it.second->root_case};
1854 for (size_t i = 0; i < all_cases.size(); i++) {
1855 for (auto &switch_it : all_cases[i]->switches) {
1856 for (auto &case_it : switch_it->cases) {
1857 for (auto &compare_it : case_it->compare) {
1858 log_assert(switch_it->signal.size() == compare_it.size());
1859 }
1860 all_cases.push_back(case_it);
1861 }
1862 }
1863 }
1864 for (auto &sync_it : it.second->syncs) {
1865 switch (sync_it->type) {
1866 case SyncType::ST0:
1867 case SyncType::ST1:
1868 case SyncType::STp:
1869 case SyncType::STn:
1870 case SyncType::STe:
1871 log_assert(!sync_it->signal.empty());
1872 break;
1873 case SyncType::STa:
1874 case SyncType::STg:
1875 case SyncType::STi:
1876 log_assert(sync_it->signal.empty());
1877 break;
1878 }
1879 }
1880 }
1881
1882 for (auto &it : connections_) {
1883 log_assert(it.first.size() == it.second.size());
1884 log_assert(!it.first.has_const());
1885 it.first.check(this);
1886 it.second.check(this);
1887 }
1888
1889 for (auto &it : attributes)
1890 log_assert(!it.first.empty());
1891 #endif
1892 }
1893
1894 void RTLIL::Module::optimize()
1895 {
1896 }
1897
1898 void RTLIL::Module::cloneInto(RTLIL::Module *new_mod) const
1899 {
1900 log_assert(new_mod->refcount_wires_ == 0);
1901 log_assert(new_mod->refcount_cells_ == 0);
1902
1903 new_mod->avail_parameters = avail_parameters;
1904 new_mod->parameter_default_values = parameter_default_values;
1905
1906 for (auto &conn : connections_)
1907 new_mod->connect(conn);
1908
1909 for (auto &attr : attributes)
1910 new_mod->attributes[attr.first] = attr.second;
1911
1912 for (auto &it : wires_)
1913 new_mod->addWire(it.first, it.second);
1914
1915 for (auto &it : memories)
1916 new_mod->addMemory(it.first, it.second);
1917
1918 for (auto &it : cells_)
1919 new_mod->addCell(it.first, it.second);
1920
1921 for (auto &it : processes)
1922 new_mod->addProcess(it.first, it.second);
1923
1924 struct RewriteSigSpecWorker
1925 {
1926 RTLIL::Module *mod;
1927 void operator()(RTLIL::SigSpec &sig)
1928 {
1929 sig.pack();
1930 for (auto &c : sig.chunks_)
1931 if (c.wire != NULL)
1932 c.wire = mod->wires_.at(c.wire->name);
1933 }
1934 };
1935
1936 RewriteSigSpecWorker rewriteSigSpecWorker;
1937 rewriteSigSpecWorker.mod = new_mod;
1938 new_mod->rewrite_sigspecs(rewriteSigSpecWorker);
1939 new_mod->fixup_ports();
1940 }
1941
1942 RTLIL::Module *RTLIL::Module::clone() const
1943 {
1944 RTLIL::Module *new_mod = new RTLIL::Module;
1945 new_mod->name = name;
1946 cloneInto(new_mod);
1947 return new_mod;
1948 }
1949
1950 bool RTLIL::Module::has_memories() const
1951 {
1952 return !memories.empty();
1953 }
1954
1955 bool RTLIL::Module::has_processes() const
1956 {
1957 return !processes.empty();
1958 }
1959
1960 bool RTLIL::Module::has_memories_warn() const
1961 {
1962 if (!memories.empty())
1963 log_warning("Ignoring module %s because it contains memories (run 'memory' command first).\n", log_id(this));
1964 return !memories.empty();
1965 }
1966
1967 bool RTLIL::Module::has_processes_warn() const
1968 {
1969 if (!processes.empty())
1970 log_warning("Ignoring module %s because it contains processes (run 'proc' command first).\n", log_id(this));
1971 return !processes.empty();
1972 }
1973
1974 std::vector<RTLIL::Wire*> RTLIL::Module::selected_wires() const
1975 {
1976 std::vector<RTLIL::Wire*> result;
1977 result.reserve(wires_.size());
1978 for (auto &it : wires_)
1979 if (design->selected(this, it.second))
1980 result.push_back(it.second);
1981 return result;
1982 }
1983
1984 std::vector<RTLIL::Cell*> RTLIL::Module::selected_cells() const
1985 {
1986 std::vector<RTLIL::Cell*> result;
1987 result.reserve(cells_.size());
1988 for (auto &it : cells_)
1989 if (design->selected(this, it.second))
1990 result.push_back(it.second);
1991 return result;
1992 }
1993
1994 void RTLIL::Module::add(RTLIL::Wire *wire)
1995 {
1996 log_assert(!wire->name.empty());
1997 log_assert(count_id(wire->name) == 0);
1998 log_assert(refcount_wires_ == 0);
1999 wires_[wire->name] = wire;
2000 wire->module = this;
2001 }
2002
2003 void RTLIL::Module::add(RTLIL::Cell *cell)
2004 {
2005 log_assert(!cell->name.empty());
2006 log_assert(count_id(cell->name) == 0);
2007 log_assert(refcount_cells_ == 0);
2008 cells_[cell->name] = cell;
2009 cell->module = this;
2010 }
2011
2012 void RTLIL::Module::add(RTLIL::Process *process)
2013 {
2014 log_assert(!process->name.empty());
2015 log_assert(count_id(process->name) == 0);
2016 processes[process->name] = process;
2017 process->module = this;
2018 }
2019
2020 void RTLIL::Module::add(RTLIL::Binding *binding)
2021 {
2022 log_assert(binding != nullptr);
2023 bindings_.push_back(binding);
2024 }
2025
2026 void RTLIL::Module::remove(const pool<RTLIL::Wire*> &wires)
2027 {
2028 log_assert(refcount_wires_ == 0);
2029
2030 struct DeleteWireWorker
2031 {
2032 RTLIL::Module *module;
2033 const pool<RTLIL::Wire*> *wires_p;
2034
2035 void operator()(RTLIL::SigSpec &sig) {
2036 sig.pack();
2037 for (auto &c : sig.chunks_)
2038 if (c.wire != NULL && wires_p->count(c.wire)) {
2039 c.wire = module->addWire(stringf("$delete_wire$%d", autoidx++), c.width);
2040 c.offset = 0;
2041 }
2042 }
2043
2044 void operator()(RTLIL::SigSpec &lhs, RTLIL::SigSpec &rhs) {
2045 log_assert(GetSize(lhs) == GetSize(rhs));
2046 lhs.unpack();
2047 rhs.unpack();
2048 for (int i = 0; i < GetSize(lhs); i++) {
2049 RTLIL::SigBit &lhs_bit = lhs.bits_[i];
2050 RTLIL::SigBit &rhs_bit = rhs.bits_[i];
2051 if ((lhs_bit.wire != nullptr && wires_p->count(lhs_bit.wire)) || (rhs_bit.wire != nullptr && wires_p->count(rhs_bit.wire))) {
2052 lhs_bit = State::Sx;
2053 rhs_bit = State::Sx;
2054 }
2055 }
2056 }
2057 };
2058
2059 DeleteWireWorker delete_wire_worker;
2060 delete_wire_worker.module = this;
2061 delete_wire_worker.wires_p = &wires;
2062 rewrite_sigspecs2(delete_wire_worker);
2063
2064 for (auto &it : wires) {
2065 log_assert(wires_.count(it->name) != 0);
2066 wires_.erase(it->name);
2067 delete it;
2068 }
2069 }
2070
2071 void RTLIL::Module::remove(RTLIL::Cell *cell)
2072 {
2073 while (!cell->connections_.empty())
2074 cell->unsetPort(cell->connections_.begin()->first);
2075
2076 log_assert(cells_.count(cell->name) != 0);
2077 log_assert(refcount_cells_ == 0);
2078 cells_.erase(cell->name);
2079 delete cell;
2080 }
2081
2082 void RTLIL::Module::remove(RTLIL::Process *process)
2083 {
2084 log_assert(processes.count(process->name) != 0);
2085 processes.erase(process->name);
2086 delete process;
2087 }
2088
2089 void RTLIL::Module::rename(RTLIL::Wire *wire, RTLIL::IdString new_name)
2090 {
2091 log_assert(wires_[wire->name] == wire);
2092 log_assert(refcount_wires_ == 0);
2093 wires_.erase(wire->name);
2094 wire->name = new_name;
2095 add(wire);
2096 }
2097
2098 void RTLIL::Module::rename(RTLIL::Cell *cell, RTLIL::IdString new_name)
2099 {
2100 log_assert(cells_[cell->name] == cell);
2101 log_assert(refcount_wires_ == 0);
2102 cells_.erase(cell->name);
2103 cell->name = new_name;
2104 add(cell);
2105 }
2106
2107 void RTLIL::Module::rename(RTLIL::IdString old_name, RTLIL::IdString new_name)
2108 {
2109 log_assert(count_id(old_name) != 0);
2110 if (wires_.count(old_name))
2111 rename(wires_.at(old_name), new_name);
2112 else if (cells_.count(old_name))
2113 rename(cells_.at(old_name), new_name);
2114 else
2115 log_abort();
2116 }
2117
2118 void RTLIL::Module::swap_names(RTLIL::Wire *w1, RTLIL::Wire *w2)
2119 {
2120 log_assert(wires_[w1->name] == w1);
2121 log_assert(wires_[w2->name] == w2);
2122 log_assert(refcount_wires_ == 0);
2123
2124 wires_.erase(w1->name);
2125 wires_.erase(w2->name);
2126
2127 std::swap(w1->name, w2->name);
2128
2129 wires_[w1->name] = w1;
2130 wires_[w2->name] = w2;
2131 }
2132
2133 void RTLIL::Module::swap_names(RTLIL::Cell *c1, RTLIL::Cell *c2)
2134 {
2135 log_assert(cells_[c1->name] == c1);
2136 log_assert(cells_[c2->name] == c2);
2137 log_assert(refcount_cells_ == 0);
2138
2139 cells_.erase(c1->name);
2140 cells_.erase(c2->name);
2141
2142 std::swap(c1->name, c2->name);
2143
2144 cells_[c1->name] = c1;
2145 cells_[c2->name] = c2;
2146 }
2147
2148 RTLIL::IdString RTLIL::Module::uniquify(RTLIL::IdString name)
2149 {
2150 int index = 0;
2151 return uniquify(name, index);
2152 }
2153
2154 RTLIL::IdString RTLIL::Module::uniquify(RTLIL::IdString name, int &index)
2155 {
2156 if (index == 0) {
2157 if (count_id(name) == 0)
2158 return name;
2159 index++;
2160 }
2161
2162 while (1) {
2163 RTLIL::IdString new_name = stringf("%s_%d", name.c_str(), index);
2164 if (count_id(new_name) == 0)
2165 return new_name;
2166 index++;
2167 }
2168 }
2169
2170 static bool fixup_ports_compare(const RTLIL::Wire *a, const RTLIL::Wire *b)
2171 {
2172 if (a->port_id && !b->port_id)
2173 return true;
2174 if (!a->port_id && b->port_id)
2175 return false;
2176
2177 if (a->port_id == b->port_id)
2178 return a->name < b->name;
2179 return a->port_id < b->port_id;
2180 }
2181
2182 void RTLIL::Module::connect(const RTLIL::SigSig &conn)
2183 {
2184 for (auto mon : monitors)
2185 mon->notify_connect(this, conn);
2186
2187 if (design)
2188 for (auto mon : design->monitors)
2189 mon->notify_connect(this, conn);
2190
2191 // ignore all attempts to assign constants to other constants
2192 if (conn.first.has_const()) {
2193 RTLIL::SigSig new_conn;
2194 for (int i = 0; i < GetSize(conn.first); i++)
2195 if (conn.first[i].wire) {
2196 new_conn.first.append(conn.first[i]);
2197 new_conn.second.append(conn.second[i]);
2198 }
2199 if (GetSize(new_conn.first))
2200 connect(new_conn);
2201 return;
2202 }
2203
2204 if (yosys_xtrace) {
2205 log("#X# Connect (SigSig) in %s: %s = %s (%d bits)\n", log_id(this), log_signal(conn.first), log_signal(conn.second), GetSize(conn.first));
2206 log_backtrace("-X- ", yosys_xtrace-1);
2207 }
2208
2209 log_assert(GetSize(conn.first) == GetSize(conn.second));
2210 connections_.push_back(conn);
2211 }
2212
2213 void RTLIL::Module::connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs)
2214 {
2215 connect(RTLIL::SigSig(lhs, rhs));
2216 }
2217
2218 void RTLIL::Module::new_connections(const std::vector<RTLIL::SigSig> &new_conn)
2219 {
2220 for (auto mon : monitors)
2221 mon->notify_connect(this, new_conn);
2222
2223 if (design)
2224 for (auto mon : design->monitors)
2225 mon->notify_connect(this, new_conn);
2226
2227 if (yosys_xtrace) {
2228 log("#X# New connections vector in %s:\n", log_id(this));
2229 for (auto &conn: new_conn)
2230 log("#X# %s = %s (%d bits)\n", log_signal(conn.first), log_signal(conn.second), GetSize(conn.first));
2231 log_backtrace("-X- ", yosys_xtrace-1);
2232 }
2233
2234 connections_ = new_conn;
2235 }
2236
2237 const std::vector<RTLIL::SigSig> &RTLIL::Module::connections() const
2238 {
2239 return connections_;
2240 }
2241
2242 void RTLIL::Module::fixup_ports()
2243 {
2244 std::vector<RTLIL::Wire*> all_ports;
2245
2246 for (auto &w : wires_)
2247 if (w.second->port_input || w.second->port_output)
2248 all_ports.push_back(w.second);
2249 else
2250 w.second->port_id = 0;
2251
2252 std::sort(all_ports.begin(), all_ports.end(), fixup_ports_compare);
2253
2254 ports.clear();
2255 for (size_t i = 0; i < all_ports.size(); i++) {
2256 ports.push_back(all_ports[i]->name);
2257 all_ports[i]->port_id = i+1;
2258 }
2259 }
2260
2261 RTLIL::Wire *RTLIL::Module::addWire(RTLIL::IdString name, int width)
2262 {
2263 RTLIL::Wire *wire = new RTLIL::Wire;
2264 wire->name = name;
2265 wire->width = width;
2266 add(wire);
2267 return wire;
2268 }
2269
2270 RTLIL::Wire *RTLIL::Module::addWire(RTLIL::IdString name, const RTLIL::Wire *other)
2271 {
2272 RTLIL::Wire *wire = addWire(name);
2273 wire->width = other->width;
2274 wire->start_offset = other->start_offset;
2275 wire->port_id = other->port_id;
2276 wire->port_input = other->port_input;
2277 wire->port_output = other->port_output;
2278 wire->upto = other->upto;
2279 wire->is_signed = other->is_signed;
2280 wire->attributes = other->attributes;
2281 return wire;
2282 }
2283
2284 RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, RTLIL::IdString type)
2285 {
2286 RTLIL::Cell *cell = new RTLIL::Cell;
2287 cell->name = name;
2288 cell->type = type;
2289 add(cell);
2290 return cell;
2291 }
2292
2293 RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, const RTLIL::Cell *other)
2294 {
2295 RTLIL::Cell *cell = addCell(name, other->type);
2296 cell->connections_ = other->connections_;
2297 cell->parameters = other->parameters;
2298 cell->attributes = other->attributes;
2299 return cell;
2300 }
2301
2302 RTLIL::Memory *RTLIL::Module::addMemory(RTLIL::IdString name, const RTLIL::Memory *other)
2303 {
2304 RTLIL::Memory *mem = new RTLIL::Memory;
2305 mem->name = name;
2306 mem->width = other->width;
2307 mem->start_offset = other->start_offset;
2308 mem->size = other->size;
2309 mem->attributes = other->attributes;
2310 memories[mem->name] = mem;
2311 return mem;
2312 }
2313
2314 RTLIL::Process *RTLIL::Module::addProcess(RTLIL::IdString name)
2315 {
2316 RTLIL::Process *proc = new RTLIL::Process;
2317 proc->name = name;
2318 add(proc);
2319 return proc;
2320 }
2321
2322 RTLIL::Process *RTLIL::Module::addProcess(RTLIL::IdString name, const RTLIL::Process *other)
2323 {
2324 RTLIL::Process *proc = other->clone();
2325 proc->name = name;
2326 add(proc);
2327 return proc;
2328 }
2329
2330 #define DEF_METHOD(_func, _y_size, _type) \
2331 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed, const std::string &src) { \
2332 RTLIL::Cell *cell = addCell(name, _type); \
2333 cell->parameters[ID::A_SIGNED] = is_signed; \
2334 cell->parameters[ID::A_WIDTH] = sig_a.size(); \
2335 cell->parameters[ID::Y_WIDTH] = sig_y.size(); \
2336 cell->setPort(ID::A, sig_a); \
2337 cell->setPort(ID::Y, sig_y); \
2338 cell->set_src_attribute(src); \
2339 return cell; \
2340 } \
2341 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed, const std::string &src) { \
2342 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
2343 add ## _func(name, sig_a, sig_y, is_signed, src); \
2344 return sig_y; \
2345 }
2346 DEF_METHOD(Not, sig_a.size(), ID($not))
2347 DEF_METHOD(Pos, sig_a.size(), ID($pos))
2348 DEF_METHOD(Neg, sig_a.size(), ID($neg))
2349 DEF_METHOD(ReduceAnd, 1, ID($reduce_and))
2350 DEF_METHOD(ReduceOr, 1, ID($reduce_or))
2351 DEF_METHOD(ReduceXor, 1, ID($reduce_xor))
2352 DEF_METHOD(ReduceXnor, 1, ID($reduce_xnor))
2353 DEF_METHOD(ReduceBool, 1, ID($reduce_bool))
2354 DEF_METHOD(LogicNot, 1, ID($logic_not))
2355 #undef DEF_METHOD
2356
2357 #define DEF_METHOD(_func, _y_size, _type) \
2358 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed, const std::string &src) { \
2359 RTLIL::Cell *cell = addCell(name, _type); \
2360 cell->parameters[ID::A_SIGNED] = is_signed; \
2361 cell->parameters[ID::B_SIGNED] = is_signed; \
2362 cell->parameters[ID::A_WIDTH] = sig_a.size(); \
2363 cell->parameters[ID::B_WIDTH] = sig_b.size(); \
2364 cell->parameters[ID::Y_WIDTH] = sig_y.size(); \
2365 cell->setPort(ID::A, sig_a); \
2366 cell->setPort(ID::B, sig_b); \
2367 cell->setPort(ID::Y, sig_y); \
2368 cell->set_src_attribute(src); \
2369 return cell; \
2370 } \
2371 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed, const std::string &src) { \
2372 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
2373 add ## _func(name, sig_a, sig_b, sig_y, is_signed, src); \
2374 return sig_y; \
2375 }
2376 DEF_METHOD(And, max(sig_a.size(), sig_b.size()), ID($and))
2377 DEF_METHOD(Or, max(sig_a.size(), sig_b.size()), ID($or))
2378 DEF_METHOD(Xor, max(sig_a.size(), sig_b.size()), ID($xor))
2379 DEF_METHOD(Xnor, max(sig_a.size(), sig_b.size()), ID($xnor))
2380 DEF_METHOD(Shift, sig_a.size(), ID($shift))
2381 DEF_METHOD(Shiftx, sig_a.size(), ID($shiftx))
2382 DEF_METHOD(Lt, 1, ID($lt))
2383 DEF_METHOD(Le, 1, ID($le))
2384 DEF_METHOD(Eq, 1, ID($eq))
2385 DEF_METHOD(Ne, 1, ID($ne))
2386 DEF_METHOD(Eqx, 1, ID($eqx))
2387 DEF_METHOD(Nex, 1, ID($nex))
2388 DEF_METHOD(Ge, 1, ID($ge))
2389 DEF_METHOD(Gt, 1, ID($gt))
2390 DEF_METHOD(Add, max(sig_a.size(), sig_b.size()), ID($add))
2391 DEF_METHOD(Sub, max(sig_a.size(), sig_b.size()), ID($sub))
2392 DEF_METHOD(Mul, max(sig_a.size(), sig_b.size()), ID($mul))
2393 DEF_METHOD(Div, max(sig_a.size(), sig_b.size()), ID($div))
2394 DEF_METHOD(Mod, max(sig_a.size(), sig_b.size()), ID($mod))
2395 DEF_METHOD(DivFloor, max(sig_a.size(), sig_b.size()), ID($divfloor))
2396 DEF_METHOD(ModFloor, max(sig_a.size(), sig_b.size()), ID($modfloor))
2397 DEF_METHOD(LogicAnd, 1, ID($logic_and))
2398 DEF_METHOD(LogicOr, 1, ID($logic_or))
2399 #undef DEF_METHOD
2400
2401 #define DEF_METHOD(_func, _y_size, _type) \
2402 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed, const std::string &src) { \
2403 RTLIL::Cell *cell = addCell(name, _type); \
2404 cell->parameters[ID::A_SIGNED] = is_signed; \
2405 cell->parameters[ID::B_SIGNED] = false; \
2406 cell->parameters[ID::A_WIDTH] = sig_a.size(); \
2407 cell->parameters[ID::B_WIDTH] = sig_b.size(); \
2408 cell->parameters[ID::Y_WIDTH] = sig_y.size(); \
2409 cell->setPort(ID::A, sig_a); \
2410 cell->setPort(ID::B, sig_b); \
2411 cell->setPort(ID::Y, sig_y); \
2412 cell->set_src_attribute(src); \
2413 return cell; \
2414 } \
2415 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed, const std::string &src) { \
2416 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
2417 add ## _func(name, sig_a, sig_b, sig_y, is_signed, src); \
2418 return sig_y; \
2419 }
2420 DEF_METHOD(Shl, sig_a.size(), ID($shl))
2421 DEF_METHOD(Shr, sig_a.size(), ID($shr))
2422 DEF_METHOD(Sshl, sig_a.size(), ID($sshl))
2423 DEF_METHOD(Sshr, sig_a.size(), ID($sshr))
2424 #undef DEF_METHOD
2425
2426 #define DEF_METHOD(_func, _type, _pmux) \
2427 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, const std::string &src) { \
2428 RTLIL::Cell *cell = addCell(name, _type); \
2429 cell->parameters[ID::WIDTH] = sig_a.size(); \
2430 if (_pmux) cell->parameters[ID::S_WIDTH] = sig_s.size(); \
2431 cell->setPort(ID::A, sig_a); \
2432 cell->setPort(ID::B, sig_b); \
2433 cell->setPort(ID::S, sig_s); \
2434 cell->setPort(ID::Y, sig_y); \
2435 cell->set_src_attribute(src); \
2436 return cell; \
2437 } \
2438 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const std::string &src) { \
2439 RTLIL::SigSpec sig_y = addWire(NEW_ID, sig_a.size()); \
2440 add ## _func(name, sig_a, sig_b, sig_s, sig_y, src); \
2441 return sig_y; \
2442 }
2443 DEF_METHOD(Mux, ID($mux), 0)
2444 DEF_METHOD(Pmux, ID($pmux), 1)
2445 #undef DEF_METHOD
2446
2447 #define DEF_METHOD_2(_func, _type, _P1, _P2) \
2448 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const std::string &src) { \
2449 RTLIL::Cell *cell = addCell(name, _type); \
2450 cell->setPort("\\" #_P1, sig1); \
2451 cell->setPort("\\" #_P2, sig2); \
2452 cell->set_src_attribute(src); \
2453 return cell; \
2454 } \
2455 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const std::string &src) { \
2456 RTLIL::SigBit sig2 = addWire(NEW_ID); \
2457 add ## _func(name, sig1, sig2, src); \
2458 return sig2; \
2459 }
2460 #define DEF_METHOD_3(_func, _type, _P1, _P2, _P3) \
2461 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const RTLIL::SigBit &sig3, const std::string &src) { \
2462 RTLIL::Cell *cell = addCell(name, _type); \
2463 cell->setPort("\\" #_P1, sig1); \
2464 cell->setPort("\\" #_P2, sig2); \
2465 cell->setPort("\\" #_P3, sig3); \
2466 cell->set_src_attribute(src); \
2467 return cell; \
2468 } \
2469 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const std::string &src) { \
2470 RTLIL::SigBit sig3 = addWire(NEW_ID); \
2471 add ## _func(name, sig1, sig2, sig3, src); \
2472 return sig3; \
2473 }
2474 #define DEF_METHOD_4(_func, _type, _P1, _P2, _P3, _P4) \
2475 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const RTLIL::SigBit &sig3, const RTLIL::SigBit &sig4, const std::string &src) { \
2476 RTLIL::Cell *cell = addCell(name, _type); \
2477 cell->setPort("\\" #_P1, sig1); \
2478 cell->setPort("\\" #_P2, sig2); \
2479 cell->setPort("\\" #_P3, sig3); \
2480 cell->setPort("\\" #_P4, sig4); \
2481 cell->set_src_attribute(src); \
2482 return cell; \
2483 } \
2484 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const RTLIL::SigBit &sig3, const std::string &src) { \
2485 RTLIL::SigBit sig4 = addWire(NEW_ID); \
2486 add ## _func(name, sig1, sig2, sig3, sig4, src); \
2487 return sig4; \
2488 }
2489 #define DEF_METHOD_5(_func, _type, _P1, _P2, _P3, _P4, _P5) \
2490 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const RTLIL::SigBit &sig3, const RTLIL::SigBit &sig4, const RTLIL::SigBit &sig5, const std::string &src) { \
2491 RTLIL::Cell *cell = addCell(name, _type); \
2492 cell->setPort("\\" #_P1, sig1); \
2493 cell->setPort("\\" #_P2, sig2); \
2494 cell->setPort("\\" #_P3, sig3); \
2495 cell->setPort("\\" #_P4, sig4); \
2496 cell->setPort("\\" #_P5, sig5); \
2497 cell->set_src_attribute(src); \
2498 return cell; \
2499 } \
2500 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const RTLIL::SigBit &sig3, const RTLIL::SigBit &sig4, const std::string &src) { \
2501 RTLIL::SigBit sig5 = addWire(NEW_ID); \
2502 add ## _func(name, sig1, sig2, sig3, sig4, sig5, src); \
2503 return sig5; \
2504 }
2505 DEF_METHOD_2(BufGate, ID($_BUF_), A, Y)
2506 DEF_METHOD_2(NotGate, ID($_NOT_), A, Y)
2507 DEF_METHOD_3(AndGate, ID($_AND_), A, B, Y)
2508 DEF_METHOD_3(NandGate, ID($_NAND_), A, B, Y)
2509 DEF_METHOD_3(OrGate, ID($_OR_), A, B, Y)
2510 DEF_METHOD_3(NorGate, ID($_NOR_), A, B, Y)
2511 DEF_METHOD_3(XorGate, ID($_XOR_), A, B, Y)
2512 DEF_METHOD_3(XnorGate, ID($_XNOR_), A, B, Y)
2513 DEF_METHOD_3(AndnotGate, ID($_ANDNOT_), A, B, Y)
2514 DEF_METHOD_3(OrnotGate, ID($_ORNOT_), A, B, Y)
2515 DEF_METHOD_4(MuxGate, ID($_MUX_), A, B, S, Y)
2516 DEF_METHOD_4(NmuxGate, ID($_NMUX_), A, B, S, Y)
2517 DEF_METHOD_4(Aoi3Gate, ID($_AOI3_), A, B, C, Y)
2518 DEF_METHOD_4(Oai3Gate, ID($_OAI3_), A, B, C, Y)
2519 DEF_METHOD_5(Aoi4Gate, ID($_AOI4_), A, B, C, D, Y)
2520 DEF_METHOD_5(Oai4Gate, ID($_OAI4_), A, B, C, D, Y)
2521 #undef DEF_METHOD_2
2522 #undef DEF_METHOD_3
2523 #undef DEF_METHOD_4
2524 #undef DEF_METHOD_5
2525
2526 RTLIL::Cell* RTLIL::Module::addPow(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool a_signed, bool b_signed, const std::string &src)
2527 {
2528 RTLIL::Cell *cell = addCell(name, ID($pow));
2529 cell->parameters[ID::A_SIGNED] = a_signed;
2530 cell->parameters[ID::B_SIGNED] = b_signed;
2531 cell->parameters[ID::A_WIDTH] = sig_a.size();
2532 cell->parameters[ID::B_WIDTH] = sig_b.size();
2533 cell->parameters[ID::Y_WIDTH] = sig_y.size();
2534 cell->setPort(ID::A, sig_a);
2535 cell->setPort(ID::B, sig_b);
2536 cell->setPort(ID::Y, sig_y);
2537 cell->set_src_attribute(src);
2538 return cell;
2539 }
2540
2541 RTLIL::Cell* RTLIL::Module::addSlice(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, RTLIL::Const offset, const std::string &src)
2542 {
2543 RTLIL::Cell *cell = addCell(name, ID($slice));
2544 cell->parameters[ID::A_WIDTH] = sig_a.size();
2545 cell->parameters[ID::Y_WIDTH] = sig_y.size();
2546 cell->parameters[ID::OFFSET] = offset;
2547 cell->setPort(ID::A, sig_a);
2548 cell->setPort(ID::Y, sig_y);
2549 cell->set_src_attribute(src);
2550 return cell;
2551 }
2552
2553 RTLIL::Cell* RTLIL::Module::addConcat(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, const std::string &src)
2554 {
2555 RTLIL::Cell *cell = addCell(name, ID($concat));
2556 cell->parameters[ID::A_WIDTH] = sig_a.size();
2557 cell->parameters[ID::B_WIDTH] = sig_b.size();
2558 cell->setPort(ID::A, sig_a);
2559 cell->setPort(ID::B, sig_b);
2560 cell->setPort(ID::Y, sig_y);
2561 cell->set_src_attribute(src);
2562 return cell;
2563 }
2564
2565 RTLIL::Cell* RTLIL::Module::addLut(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, RTLIL::Const lut, const std::string &src)
2566 {
2567 RTLIL::Cell *cell = addCell(name, ID($lut));
2568 cell->parameters[ID::LUT] = lut;
2569 cell->parameters[ID::WIDTH] = sig_a.size();
2570 cell->setPort(ID::A, sig_a);
2571 cell->setPort(ID::Y, sig_y);
2572 cell->set_src_attribute(src);
2573 return cell;
2574 }
2575
2576 RTLIL::Cell* RTLIL::Module::addTribuf(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_y, const std::string &src)
2577 {
2578 RTLIL::Cell *cell = addCell(name, ID($tribuf));
2579 cell->parameters[ID::WIDTH] = sig_a.size();
2580 cell->setPort(ID::A, sig_a);
2581 cell->setPort(ID::EN, sig_en);
2582 cell->setPort(ID::Y, sig_y);
2583 cell->set_src_attribute(src);
2584 return cell;
2585 }
2586
2587 RTLIL::Cell* RTLIL::Module::addAssert(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src)
2588 {
2589 RTLIL::Cell *cell = addCell(name, ID($assert));
2590 cell->setPort(ID::A, sig_a);
2591 cell->setPort(ID::EN, sig_en);
2592 cell->set_src_attribute(src);
2593 return cell;
2594 }
2595
2596 RTLIL::Cell* RTLIL::Module::addAssume(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src)
2597 {
2598 RTLIL::Cell *cell = addCell(name, ID($assume));
2599 cell->setPort(ID::A, sig_a);
2600 cell->setPort(ID::EN, sig_en);
2601 cell->set_src_attribute(src);
2602 return cell;
2603 }
2604
2605 RTLIL::Cell* RTLIL::Module::addLive(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src)
2606 {
2607 RTLIL::Cell *cell = addCell(name, ID($live));
2608 cell->setPort(ID::A, sig_a);
2609 cell->setPort(ID::EN, sig_en);
2610 cell->set_src_attribute(src);
2611 return cell;
2612 }
2613
2614 RTLIL::Cell* RTLIL::Module::addFair(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src)
2615 {
2616 RTLIL::Cell *cell = addCell(name, ID($fair));
2617 cell->setPort(ID::A, sig_a);
2618 cell->setPort(ID::EN, sig_en);
2619 cell->set_src_attribute(src);
2620 return cell;
2621 }
2622
2623 RTLIL::Cell* RTLIL::Module::addCover(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src)
2624 {
2625 RTLIL::Cell *cell = addCell(name, ID($cover));
2626 cell->setPort(ID::A, sig_a);
2627 cell->setPort(ID::EN, sig_en);
2628 cell->set_src_attribute(src);
2629 return cell;
2630 }
2631
2632 RTLIL::Cell* RTLIL::Module::addEquiv(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, const std::string &src)
2633 {
2634 RTLIL::Cell *cell = addCell(name, ID($equiv));
2635 cell->setPort(ID::A, sig_a);
2636 cell->setPort(ID::B, sig_b);
2637 cell->setPort(ID::Y, sig_y);
2638 cell->set_src_attribute(src);
2639 return cell;
2640 }
2641
2642 RTLIL::Cell* RTLIL::Module::addSr(RTLIL::IdString name, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, const RTLIL::SigSpec &sig_q, bool set_polarity, bool clr_polarity, const std::string &src)
2643 {
2644 RTLIL::Cell *cell = addCell(name, ID($sr));
2645 cell->parameters[ID::SET_POLARITY] = set_polarity;
2646 cell->parameters[ID::CLR_POLARITY] = clr_polarity;
2647 cell->parameters[ID::WIDTH] = sig_q.size();
2648 cell->setPort(ID::SET, sig_set);
2649 cell->setPort(ID::CLR, sig_clr);
2650 cell->setPort(ID::Q, sig_q);
2651 cell->set_src_attribute(src);
2652 return cell;
2653 }
2654
2655 RTLIL::Cell* RTLIL::Module::addFf(RTLIL::IdString name, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const std::string &src)
2656 {
2657 RTLIL::Cell *cell = addCell(name, ID($ff));
2658 cell->parameters[ID::WIDTH] = sig_q.size();
2659 cell->setPort(ID::D, sig_d);
2660 cell->setPort(ID::Q, sig_q);
2661 cell->set_src_attribute(src);
2662 return cell;
2663 }
2664
2665 RTLIL::Cell* RTLIL::Module::addDff(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, const std::string &src)
2666 {
2667 RTLIL::Cell *cell = addCell(name, ID($dff));
2668 cell->parameters[ID::CLK_POLARITY] = clk_polarity;
2669 cell->parameters[ID::WIDTH] = sig_q.size();
2670 cell->setPort(ID::CLK, sig_clk);
2671 cell->setPort(ID::D, sig_d);
2672 cell->setPort(ID::Q, sig_q);
2673 cell->set_src_attribute(src);
2674 return cell;
2675 }
2676
2677 RTLIL::Cell* RTLIL::Module::addDffe(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, bool en_polarity, const std::string &src)
2678 {
2679 RTLIL::Cell *cell = addCell(name, ID($dffe));
2680 cell->parameters[ID::CLK_POLARITY] = clk_polarity;
2681 cell->parameters[ID::EN_POLARITY] = en_polarity;
2682 cell->parameters[ID::WIDTH] = sig_q.size();
2683 cell->setPort(ID::CLK, sig_clk);
2684 cell->setPort(ID::EN, sig_en);
2685 cell->setPort(ID::D, sig_d);
2686 cell->setPort(ID::Q, sig_q);
2687 cell->set_src_attribute(src);
2688 return cell;
2689 }
2690
2691 RTLIL::Cell* RTLIL::Module::addDffsr(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,
2692 RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
2693 {
2694 RTLIL::Cell *cell = addCell(name, ID($dffsr));
2695 cell->parameters[ID::CLK_POLARITY] = clk_polarity;
2696 cell->parameters[ID::SET_POLARITY] = set_polarity;
2697 cell->parameters[ID::CLR_POLARITY] = clr_polarity;
2698 cell->parameters[ID::WIDTH] = sig_q.size();
2699 cell->setPort(ID::CLK, sig_clk);
2700 cell->setPort(ID::SET, sig_set);
2701 cell->setPort(ID::CLR, sig_clr);
2702 cell->setPort(ID::D, sig_d);
2703 cell->setPort(ID::Q, sig_q);
2704 cell->set_src_attribute(src);
2705 return cell;
2706 }
2707
2708 RTLIL::Cell* RTLIL::Module::addDffsre(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,
2709 RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, bool en_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
2710 {
2711 RTLIL::Cell *cell = addCell(name, ID($dffsre));
2712 cell->parameters[ID::CLK_POLARITY] = clk_polarity;
2713 cell->parameters[ID::EN_POLARITY] = en_polarity;
2714 cell->parameters[ID::SET_POLARITY] = set_polarity;
2715 cell->parameters[ID::CLR_POLARITY] = clr_polarity;
2716 cell->parameters[ID::WIDTH] = sig_q.size();
2717 cell->setPort(ID::CLK, sig_clk);
2718 cell->setPort(ID::EN, sig_en);
2719 cell->setPort(ID::SET, sig_set);
2720 cell->setPort(ID::CLR, sig_clr);
2721 cell->setPort(ID::D, sig_d);
2722 cell->setPort(ID::Q, sig_q);
2723 cell->set_src_attribute(src);
2724 return cell;
2725 }
2726
2727 RTLIL::Cell* RTLIL::Module::addAdff(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
2728 RTLIL::Const arst_value, bool clk_polarity, bool arst_polarity, const std::string &src)
2729 {
2730 RTLIL::Cell *cell = addCell(name, ID($adff));
2731 cell->parameters[ID::CLK_POLARITY] = clk_polarity;
2732 cell->parameters[ID::ARST_POLARITY] = arst_polarity;
2733 cell->parameters[ID::ARST_VALUE] = arst_value;
2734 cell->parameters[ID::WIDTH] = sig_q.size();
2735 cell->setPort(ID::CLK, sig_clk);
2736 cell->setPort(ID::ARST, sig_arst);
2737 cell->setPort(ID::D, sig_d);
2738 cell->setPort(ID::Q, sig_q);
2739 cell->set_src_attribute(src);
2740 return cell;
2741 }
2742
2743 RTLIL::Cell* RTLIL::Module::addAdffe(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
2744 RTLIL::Const arst_value, bool clk_polarity, bool en_polarity, bool arst_polarity, const std::string &src)
2745 {
2746 RTLIL::Cell *cell = addCell(name, ID($adffe));
2747 cell->parameters[ID::CLK_POLARITY] = clk_polarity;
2748 cell->parameters[ID::EN_POLARITY] = en_polarity;
2749 cell->parameters[ID::ARST_POLARITY] = arst_polarity;
2750 cell->parameters[ID::ARST_VALUE] = arst_value;
2751 cell->parameters[ID::WIDTH] = sig_q.size();
2752 cell->setPort(ID::CLK, sig_clk);
2753 cell->setPort(ID::EN, sig_en);
2754 cell->setPort(ID::ARST, sig_arst);
2755 cell->setPort(ID::D, sig_d);
2756 cell->setPort(ID::Q, sig_q);
2757 cell->set_src_attribute(src);
2758 return cell;
2759 }
2760
2761 RTLIL::Cell* RTLIL::Module::addAldff(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_aload, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
2762 const RTLIL::SigSpec &sig_ad, bool clk_polarity, bool aload_polarity, const std::string &src)
2763 {
2764 RTLIL::Cell *cell = addCell(name, ID($aldff));
2765 cell->parameters[ID::CLK_POLARITY] = clk_polarity;
2766 cell->parameters[ID::ALOAD_POLARITY] = aload_polarity;
2767 cell->parameters[ID::WIDTH] = sig_q.size();
2768 cell->setPort(ID::CLK, sig_clk);
2769 cell->setPort(ID::ALOAD, sig_aload);
2770 cell->setPort(ID::D, sig_d);
2771 cell->setPort(ID::AD, sig_ad);
2772 cell->setPort(ID::Q, sig_q);
2773 cell->set_src_attribute(src);
2774 return cell;
2775 }
2776
2777 RTLIL::Cell* RTLIL::Module::addAldffe(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_aload, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
2778 const RTLIL::SigSpec &sig_ad, bool clk_polarity, bool en_polarity, bool aload_polarity, const std::string &src)
2779 {
2780 RTLIL::Cell *cell = addCell(name, ID($aldffe));
2781 cell->parameters[ID::CLK_POLARITY] = clk_polarity;
2782 cell->parameters[ID::EN_POLARITY] = en_polarity;
2783 cell->parameters[ID::ALOAD_POLARITY] = aload_polarity;
2784 cell->parameters[ID::WIDTH] = sig_q.size();
2785 cell->setPort(ID::CLK, sig_clk);
2786 cell->setPort(ID::EN, sig_en);
2787 cell->setPort(ID::ALOAD, sig_aload);
2788 cell->setPort(ID::D, sig_d);
2789 cell->setPort(ID::AD, sig_ad);
2790 cell->setPort(ID::Q, sig_q);
2791 cell->set_src_attribute(src);
2792 return cell;
2793 }
2794
2795 RTLIL::Cell* RTLIL::Module::addSdff(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
2796 RTLIL::Const srst_value, bool clk_polarity, bool srst_polarity, const std::string &src)
2797 {
2798 RTLIL::Cell *cell = addCell(name, ID($sdff));
2799 cell->parameters[ID::CLK_POLARITY] = clk_polarity;
2800 cell->parameters[ID::SRST_POLARITY] = srst_polarity;
2801 cell->parameters[ID::SRST_VALUE] = srst_value;
2802 cell->parameters[ID::WIDTH] = sig_q.size();
2803 cell->setPort(ID::CLK, sig_clk);
2804 cell->setPort(ID::SRST, sig_srst);
2805 cell->setPort(ID::D, sig_d);
2806 cell->setPort(ID::Q, sig_q);
2807 cell->set_src_attribute(src);
2808 return cell;
2809 }
2810
2811 RTLIL::Cell* RTLIL::Module::addSdffe(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
2812 RTLIL::Const srst_value, bool clk_polarity, bool en_polarity, bool srst_polarity, const std::string &src)
2813 {
2814 RTLIL::Cell *cell = addCell(name, ID($sdffe));
2815 cell->parameters[ID::CLK_POLARITY] = clk_polarity;
2816 cell->parameters[ID::EN_POLARITY] = en_polarity;
2817 cell->parameters[ID::SRST_POLARITY] = srst_polarity;
2818 cell->parameters[ID::SRST_VALUE] = srst_value;
2819 cell->parameters[ID::WIDTH] = sig_q.size();
2820 cell->setPort(ID::CLK, sig_clk);
2821 cell->setPort(ID::EN, sig_en);
2822 cell->setPort(ID::SRST, sig_srst);
2823 cell->setPort(ID::D, sig_d);
2824 cell->setPort(ID::Q, sig_q);
2825 cell->set_src_attribute(src);
2826 return cell;
2827 }
2828
2829 RTLIL::Cell* RTLIL::Module::addSdffce(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
2830 RTLIL::Const srst_value, bool clk_polarity, bool en_polarity, bool srst_polarity, const std::string &src)
2831 {
2832 RTLIL::Cell *cell = addCell(name, ID($sdffce));
2833 cell->parameters[ID::CLK_POLARITY] = clk_polarity;
2834 cell->parameters[ID::EN_POLARITY] = en_polarity;
2835 cell->parameters[ID::SRST_POLARITY] = srst_polarity;
2836 cell->parameters[ID::SRST_VALUE] = srst_value;
2837 cell->parameters[ID::WIDTH] = sig_q.size();
2838 cell->setPort(ID::CLK, sig_clk);
2839 cell->setPort(ID::EN, sig_en);
2840 cell->setPort(ID::SRST, sig_srst);
2841 cell->setPort(ID::D, sig_d);
2842 cell->setPort(ID::Q, sig_q);
2843 cell->set_src_attribute(src);
2844 return cell;
2845 }
2846
2847 RTLIL::Cell* RTLIL::Module::addDlatch(RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity, const std::string &src)
2848 {
2849 RTLIL::Cell *cell = addCell(name, ID($dlatch));
2850 cell->parameters[ID::EN_POLARITY] = en_polarity;
2851 cell->parameters[ID::WIDTH] = sig_q.size();
2852 cell->setPort(ID::EN, sig_en);
2853 cell->setPort(ID::D, sig_d);
2854 cell->setPort(ID::Q, sig_q);
2855 cell->set_src_attribute(src);
2856 return cell;
2857 }
2858
2859 RTLIL::Cell* RTLIL::Module::addAdlatch(RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
2860 RTLIL::Const arst_value, bool en_polarity, bool arst_polarity, const std::string &src)
2861 {
2862 RTLIL::Cell *cell = addCell(name, ID($adlatch));
2863 cell->parameters[ID::EN_POLARITY] = en_polarity;
2864 cell->parameters[ID::ARST_POLARITY] = arst_polarity;
2865 cell->parameters[ID::ARST_VALUE] = arst_value;
2866 cell->parameters[ID::WIDTH] = sig_q.size();
2867 cell->setPort(ID::EN, sig_en);
2868 cell->setPort(ID::ARST, sig_arst);
2869 cell->setPort(ID::D, sig_d);
2870 cell->setPort(ID::Q, sig_q);
2871 cell->set_src_attribute(src);
2872 return cell;
2873 }
2874
2875 RTLIL::Cell* RTLIL::Module::addDlatchsr(RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,
2876 RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
2877 {
2878 RTLIL::Cell *cell = addCell(name, ID($dlatchsr));
2879 cell->parameters[ID::EN_POLARITY] = en_polarity;
2880 cell->parameters[ID::SET_POLARITY] = set_polarity;
2881 cell->parameters[ID::CLR_POLARITY] = clr_polarity;
2882 cell->parameters[ID::WIDTH] = sig_q.size();
2883 cell->setPort(ID::EN, sig_en);
2884 cell->setPort(ID::SET, sig_set);
2885 cell->setPort(ID::CLR, sig_clr);
2886 cell->setPort(ID::D, sig_d);
2887 cell->setPort(ID::Q, sig_q);
2888 cell->set_src_attribute(src);
2889 return cell;
2890 }
2891
2892 RTLIL::Cell* RTLIL::Module::addSrGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,
2893 const RTLIL::SigSpec &sig_q, bool set_polarity, bool clr_polarity, const std::string &src)
2894 {
2895 RTLIL::Cell *cell = addCell(name, stringf("$_SR_%c%c_", set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N'));
2896 cell->setPort(ID::S, sig_set);
2897 cell->setPort(ID::R, sig_clr);
2898 cell->setPort(ID::Q, sig_q);
2899 cell->set_src_attribute(src);
2900 return cell;
2901 }
2902
2903 RTLIL::Cell* RTLIL::Module::addFfGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const std::string &src)
2904 {
2905 RTLIL::Cell *cell = addCell(name, ID($_FF_));
2906 cell->setPort(ID::D, sig_d);
2907 cell->setPort(ID::Q, sig_q);
2908 cell->set_src_attribute(src);
2909 return cell;
2910 }
2911
2912 RTLIL::Cell* RTLIL::Module::addDffGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, const std::string &src)
2913 {
2914 RTLIL::Cell *cell = addCell(name, stringf("$_DFF_%c_", clk_polarity ? 'P' : 'N'));
2915 cell->setPort(ID::C, sig_clk);
2916 cell->setPort(ID::D, sig_d);
2917 cell->setPort(ID::Q, sig_q);
2918 cell->set_src_attribute(src);
2919 return cell;
2920 }
2921
2922 RTLIL::Cell* RTLIL::Module::addDffeGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, bool en_polarity, const std::string &src)
2923 {
2924 RTLIL::Cell *cell = addCell(name, stringf("$_DFFE_%c%c_", clk_polarity ? 'P' : 'N', en_polarity ? 'P' : 'N'));
2925 cell->setPort(ID::C, sig_clk);
2926 cell->setPort(ID::E, sig_en);
2927 cell->setPort(ID::D, sig_d);
2928 cell->setPort(ID::Q, sig_q);
2929 cell->set_src_attribute(src);
2930 return cell;
2931 }
2932
2933 RTLIL::Cell* RTLIL::Module::addDffsrGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,
2934 RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
2935 {
2936 RTLIL::Cell *cell = addCell(name, stringf("$_DFFSR_%c%c%c_", clk_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N'));
2937 cell->setPort(ID::C, sig_clk);
2938 cell->setPort(ID::S, sig_set);
2939 cell->setPort(ID::R, sig_clr);
2940 cell->setPort(ID::D, sig_d);
2941 cell->setPort(ID::Q, sig_q);
2942 cell->set_src_attribute(src);
2943 return cell;
2944 }
2945
2946 RTLIL::Cell* RTLIL::Module::addDffsreGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,
2947 RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, bool en_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
2948 {
2949 RTLIL::Cell *cell = addCell(name, stringf("$_DFFSRE_%c%c%c%c_", clk_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N', en_polarity ? 'P' : 'N'));
2950 cell->setPort(ID::C, sig_clk);
2951 cell->setPort(ID::S, sig_set);
2952 cell->setPort(ID::R, sig_clr);
2953 cell->setPort(ID::E, sig_en);
2954 cell->setPort(ID::D, sig_d);
2955 cell->setPort(ID::Q, sig_q);
2956 cell->set_src_attribute(src);
2957 return cell;
2958 }
2959
2960 RTLIL::Cell* RTLIL::Module::addAdffGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
2961 bool arst_value, bool clk_polarity, bool arst_polarity, const std::string &src)
2962 {
2963 RTLIL::Cell *cell = addCell(name, stringf("$_DFF_%c%c%c_", clk_polarity ? 'P' : 'N', arst_polarity ? 'P' : 'N', arst_value ? '1' : '0'));
2964 cell->setPort(ID::C, sig_clk);
2965 cell->setPort(ID::R, sig_arst);
2966 cell->setPort(ID::D, sig_d);
2967 cell->setPort(ID::Q, sig_q);
2968 cell->set_src_attribute(src);
2969 return cell;
2970 }
2971
2972 RTLIL::Cell* RTLIL::Module::addAdffeGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
2973 bool arst_value, bool clk_polarity, bool en_polarity, bool arst_polarity, const std::string &src)
2974 {
2975 RTLIL::Cell *cell = addCell(name, stringf("$_DFFE_%c%c%c%c_", clk_polarity ? 'P' : 'N', arst_polarity ? 'P' : 'N', arst_value ? '1' : '0', en_polarity ? 'P' : 'N'));
2976 cell->setPort(ID::C, sig_clk);
2977 cell->setPort(ID::R, sig_arst);
2978 cell->setPort(ID::E, sig_en);
2979 cell->setPort(ID::D, sig_d);
2980 cell->setPort(ID::Q, sig_q);
2981 cell->set_src_attribute(src);
2982 return cell;
2983 }
2984
2985 RTLIL::Cell* RTLIL::Module::addAldffGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_aload, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
2986 const RTLIL::SigSpec &sig_ad, bool clk_polarity, bool aload_polarity, const std::string &src)
2987 {
2988 RTLIL::Cell *cell = addCell(name, stringf("$_ALDFF_%c%c_", clk_polarity ? 'P' : 'N', aload_polarity ? 'P' : 'N'));
2989 cell->setPort(ID::C, sig_clk);
2990 cell->setPort(ID::L, sig_aload);
2991 cell->setPort(ID::D, sig_d);
2992 cell->setPort(ID::AD, sig_ad);
2993 cell->setPort(ID::Q, sig_q);
2994 cell->set_src_attribute(src);
2995 return cell;
2996 }
2997
2998 RTLIL::Cell* RTLIL::Module::addAldffeGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_aload, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
2999 const RTLIL::SigSpec &sig_ad, bool clk_polarity, bool en_polarity, bool aload_polarity, const std::string &src)
3000 {
3001 RTLIL::Cell *cell = addCell(name, stringf("$_ALDFFE_%c%c%c_", clk_polarity ? 'P' : 'N', aload_polarity ? 'P' : 'N', en_polarity ? 'P' : 'N'));
3002 cell->setPort(ID::C, sig_clk);
3003 cell->setPort(ID::L, sig_aload);
3004 cell->setPort(ID::E, sig_en);
3005 cell->setPort(ID::D, sig_d);
3006 cell->setPort(ID::AD, sig_ad);
3007 cell->setPort(ID::Q, sig_q);
3008 cell->set_src_attribute(src);
3009 return cell;
3010 }
3011
3012 RTLIL::Cell* RTLIL::Module::addSdffGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
3013 bool srst_value, bool clk_polarity, bool srst_polarity, const std::string &src)
3014 {
3015 RTLIL::Cell *cell = addCell(name, stringf("$_SDFF_%c%c%c_", clk_polarity ? 'P' : 'N', srst_polarity ? 'P' : 'N', srst_value ? '1' : '0'));
3016 cell->setPort(ID::C, sig_clk);
3017 cell->setPort(ID::R, sig_srst);
3018 cell->setPort(ID::D, sig_d);
3019 cell->setPort(ID::Q, sig_q);
3020 cell->set_src_attribute(src);
3021 return cell;
3022 }
3023
3024 RTLIL::Cell* RTLIL::Module::addSdffeGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
3025 bool srst_value, bool clk_polarity, bool en_polarity, bool srst_polarity, const std::string &src)
3026 {
3027 RTLIL::Cell *cell = addCell(name, stringf("$_SDFFE_%c%c%c%c_", clk_polarity ? 'P' : 'N', srst_polarity ? 'P' : 'N', srst_value ? '1' : '0', en_polarity ? 'P' : 'N'));
3028 cell->setPort(ID::C, sig_clk);
3029 cell->setPort(ID::R, sig_srst);
3030 cell->setPort(ID::E, sig_en);
3031 cell->setPort(ID::D, sig_d);
3032 cell->setPort(ID::Q, sig_q);
3033 cell->set_src_attribute(src);
3034 return cell;
3035 }
3036
3037 RTLIL::Cell* RTLIL::Module::addSdffceGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
3038 bool srst_value, bool clk_polarity, bool en_polarity, bool srst_polarity, const std::string &src)
3039 {
3040 RTLIL::Cell *cell = addCell(name, stringf("$_SDFFCE_%c%c%c%c_", clk_polarity ? 'P' : 'N', srst_polarity ? 'P' : 'N', srst_value ? '1' : '0', en_polarity ? 'P' : 'N'));
3041 cell->setPort(ID::C, sig_clk);
3042 cell->setPort(ID::R, sig_srst);
3043 cell->setPort(ID::E, sig_en);
3044 cell->setPort(ID::D, sig_d);
3045 cell->setPort(ID::Q, sig_q);
3046 cell->set_src_attribute(src);
3047 return cell;
3048 }
3049
3050 RTLIL::Cell* RTLIL::Module::addDlatchGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity, const std::string &src)
3051 {
3052 RTLIL::Cell *cell = addCell(name, stringf("$_DLATCH_%c_", en_polarity ? 'P' : 'N'));
3053 cell->setPort(ID::E, sig_en);
3054 cell->setPort(ID::D, sig_d);
3055 cell->setPort(ID::Q, sig_q);
3056 cell->set_src_attribute(src);
3057 return cell;
3058 }
3059
3060 RTLIL::Cell* RTLIL::Module::addAdlatchGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
3061 bool arst_value, bool en_polarity, bool arst_polarity, const std::string &src)
3062 {
3063 RTLIL::Cell *cell = addCell(name, stringf("$_DLATCH_%c%c%c_", en_polarity ? 'P' : 'N', arst_polarity ? 'P' : 'N', arst_value ? '1' : '0'));
3064 cell->setPort(ID::E, sig_en);
3065 cell->setPort(ID::R, sig_arst);
3066 cell->setPort(ID::D, sig_d);
3067 cell->setPort(ID::Q, sig_q);
3068 cell->set_src_attribute(src);
3069 return cell;
3070 }
3071
3072 RTLIL::Cell* RTLIL::Module::addDlatchsrGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,
3073 RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
3074 {
3075 RTLIL::Cell *cell = addCell(name, stringf("$_DLATCHSR_%c%c%c_", en_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N'));
3076 cell->setPort(ID::E, sig_en);
3077 cell->setPort(ID::S, sig_set);
3078 cell->setPort(ID::R, sig_clr);
3079 cell->setPort(ID::D, sig_d);
3080 cell->setPort(ID::Q, sig_q);
3081 cell->set_src_attribute(src);
3082 return cell;
3083 }
3084
3085 RTLIL::SigSpec RTLIL::Module::Anyconst(RTLIL::IdString name, int width, const std::string &src)
3086 {
3087 RTLIL::SigSpec sig = addWire(NEW_ID, width);
3088 Cell *cell = addCell(name, ID($anyconst));
3089 cell->setParam(ID::WIDTH, width);
3090 cell->setPort(ID::Y, sig);
3091 cell->set_src_attribute(src);
3092 return sig;
3093 }
3094
3095 RTLIL::SigSpec RTLIL::Module::Anyseq(RTLIL::IdString name, int width, const std::string &src)
3096 {
3097 RTLIL::SigSpec sig = addWire(NEW_ID, width);
3098 Cell *cell = addCell(name, ID($anyseq));
3099 cell->setParam(ID::WIDTH, width);
3100 cell->setPort(ID::Y, sig);
3101 cell->set_src_attribute(src);
3102 return sig;
3103 }
3104
3105 RTLIL::SigSpec RTLIL::Module::Allconst(RTLIL::IdString name, int width, const std::string &src)
3106 {
3107 RTLIL::SigSpec sig = addWire(NEW_ID, width);
3108 Cell *cell = addCell(name, ID($allconst));
3109 cell->setParam(ID::WIDTH, width);
3110 cell->setPort(ID::Y, sig);
3111 cell->set_src_attribute(src);
3112 return sig;
3113 }
3114
3115 RTLIL::SigSpec RTLIL::Module::Allseq(RTLIL::IdString name, int width, const std::string &src)
3116 {
3117 RTLIL::SigSpec sig = addWire(NEW_ID, width);
3118 Cell *cell = addCell(name, ID($allseq));
3119 cell->setParam(ID::WIDTH, width);
3120 cell->setPort(ID::Y, sig);
3121 cell->set_src_attribute(src);
3122 return sig;
3123 }
3124
3125 RTLIL::SigSpec RTLIL::Module::Initstate(RTLIL::IdString name, const std::string &src)
3126 {
3127 RTLIL::SigSpec sig = addWire(NEW_ID);
3128 Cell *cell = addCell(name, ID($initstate));
3129 cell->setPort(ID::Y, sig);
3130 cell->set_src_attribute(src);
3131 return sig;
3132 }
3133
3134 RTLIL::Wire::Wire()
3135 {
3136 static unsigned int hashidx_count = 123456789;
3137 hashidx_count = mkhash_xorshift(hashidx_count);
3138 hashidx_ = hashidx_count;
3139
3140 module = nullptr;
3141 width = 1;
3142 start_offset = 0;
3143 port_id = 0;
3144 port_input = false;
3145 port_output = false;
3146 upto = false;
3147 is_signed = false;
3148
3149 #ifdef WITH_PYTHON
3150 RTLIL::Wire::get_all_wires()->insert(std::pair<unsigned int, RTLIL::Wire*>(hashidx_, this));
3151 #endif
3152 }
3153
3154 RTLIL::Wire::~Wire()
3155 {
3156 #ifdef WITH_PYTHON
3157 RTLIL::Wire::get_all_wires()->erase(hashidx_);
3158 #endif
3159 }
3160
3161 #ifdef WITH_PYTHON
3162 static std::map<unsigned int, RTLIL::Wire*> all_wires;
3163 std::map<unsigned int, RTLIL::Wire*> *RTLIL::Wire::get_all_wires(void)
3164 {
3165 return &all_wires;
3166 }
3167 #endif
3168
3169 RTLIL::Memory::Memory()
3170 {
3171 static unsigned int hashidx_count = 123456789;
3172 hashidx_count = mkhash_xorshift(hashidx_count);
3173 hashidx_ = hashidx_count;
3174
3175 width = 1;
3176 start_offset = 0;
3177 size = 0;
3178 #ifdef WITH_PYTHON
3179 RTLIL::Memory::get_all_memorys()->insert(std::pair<unsigned int, RTLIL::Memory*>(hashidx_, this));
3180 #endif
3181 }
3182
3183 RTLIL::Process::Process() : module(nullptr)
3184 {
3185 static unsigned int hashidx_count = 123456789;
3186 hashidx_count = mkhash_xorshift(hashidx_count);
3187 hashidx_ = hashidx_count;
3188 }
3189
3190 RTLIL::Cell::Cell() : module(nullptr)
3191 {
3192 static unsigned int hashidx_count = 123456789;
3193 hashidx_count = mkhash_xorshift(hashidx_count);
3194 hashidx_ = hashidx_count;
3195
3196 // log("#memtrace# %p\n", this);
3197 memhasher();
3198
3199 #ifdef WITH_PYTHON
3200 RTLIL::Cell::get_all_cells()->insert(std::pair<unsigned int, RTLIL::Cell*>(hashidx_, this));
3201 #endif
3202 }
3203
3204 RTLIL::Cell::~Cell()
3205 {
3206 #ifdef WITH_PYTHON
3207 RTLIL::Cell::get_all_cells()->erase(hashidx_);
3208 #endif
3209 }
3210
3211 #ifdef WITH_PYTHON
3212 static std::map<unsigned int, RTLIL::Cell*> all_cells;
3213 std::map<unsigned int, RTLIL::Cell*> *RTLIL::Cell::get_all_cells(void)
3214 {
3215 return &all_cells;
3216 }
3217 #endif
3218
3219 bool RTLIL::Cell::hasPort(RTLIL::IdString portname) const
3220 {
3221 return connections_.count(portname) != 0;
3222 }
3223
3224 void RTLIL::Cell::unsetPort(RTLIL::IdString portname)
3225 {
3226 RTLIL::SigSpec signal;
3227 auto conn_it = connections_.find(portname);
3228
3229 if (conn_it != connections_.end())
3230 {
3231 for (auto mon : module->monitors)
3232 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
3233
3234 if (module->design)
3235 for (auto mon : module->design->monitors)
3236 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
3237
3238 if (yosys_xtrace) {
3239 log("#X# Unconnect %s.%s.%s\n", log_id(this->module), log_id(this), log_id(portname));
3240 log_backtrace("-X- ", yosys_xtrace-1);
3241 }
3242
3243 connections_.erase(conn_it);
3244 }
3245 }
3246
3247 void RTLIL::Cell::setPort(RTLIL::IdString portname, RTLIL::SigSpec signal)
3248 {
3249 auto r = connections_.insert(portname);
3250 auto conn_it = r.first;
3251 if (!r.second && conn_it->second == signal)
3252 return;
3253
3254 for (auto mon : module->monitors)
3255 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
3256
3257 if (module->design)
3258 for (auto mon : module->design->monitors)
3259 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
3260
3261 if (yosys_xtrace) {
3262 log("#X# Connect %s.%s.%s = %s (%d)\n", log_id(this->module), log_id(this), log_id(portname), log_signal(signal), GetSize(signal));
3263 log_backtrace("-X- ", yosys_xtrace-1);
3264 }
3265
3266 conn_it->second = std::move(signal);
3267 }
3268
3269 const RTLIL::SigSpec &RTLIL::Cell::getPort(RTLIL::IdString portname) const
3270 {
3271 return connections_.at(portname);
3272 }
3273
3274 const dict<RTLIL::IdString, RTLIL::SigSpec> &RTLIL::Cell::connections() const
3275 {
3276 return connections_;
3277 }
3278
3279 bool RTLIL::Cell::known() const
3280 {
3281 if (yosys_celltypes.cell_known(type))
3282 return true;
3283 if (module && module->design && module->design->module(type))
3284 return true;
3285 return false;
3286 }
3287
3288 bool RTLIL::Cell::input(RTLIL::IdString portname) const
3289 {
3290 if (yosys_celltypes.cell_known(type))
3291 return yosys_celltypes.cell_input(type, portname);
3292 if (module && module->design) {
3293 RTLIL::Module *m = module->design->module(type);
3294 RTLIL::Wire *w = m ? m->wire(portname) : nullptr;
3295 return w && w->port_input;
3296 }
3297 return false;
3298 }
3299
3300 bool RTLIL::Cell::output(RTLIL::IdString portname) const
3301 {
3302 if (yosys_celltypes.cell_known(type))
3303 return yosys_celltypes.cell_output(type, portname);
3304 if (module && module->design) {
3305 RTLIL::Module *m = module->design->module(type);
3306 RTLIL::Wire *w = m ? m->wire(portname) : nullptr;
3307 return w && w->port_output;
3308 }
3309 return false;
3310 }
3311
3312 bool RTLIL::Cell::hasParam(RTLIL::IdString paramname) const
3313 {
3314 return parameters.count(paramname) != 0;
3315 }
3316
3317 void RTLIL::Cell::unsetParam(RTLIL::IdString paramname)
3318 {
3319 parameters.erase(paramname);
3320 }
3321
3322 void RTLIL::Cell::setParam(RTLIL::IdString paramname, RTLIL::Const value)
3323 {
3324 parameters[paramname] = std::move(value);
3325 }
3326
3327 const RTLIL::Const &RTLIL::Cell::getParam(RTLIL::IdString paramname) const
3328 {
3329 const auto &it = parameters.find(paramname);
3330 if (it != parameters.end())
3331 return it->second;
3332 if (module && module->design) {
3333 RTLIL::Module *m = module->design->module(type);
3334 if (m)
3335 return m->parameter_default_values.at(paramname);
3336 }
3337 throw std::out_of_range("Cell::getParam()");
3338 }
3339
3340 void RTLIL::Cell::sort()
3341 {
3342 connections_.sort(sort_by_id_str());
3343 parameters.sort(sort_by_id_str());
3344 attributes.sort(sort_by_id_str());
3345 }
3346
3347 void RTLIL::Cell::check()
3348 {
3349 #ifndef NDEBUG
3350 InternalCellChecker checker(NULL, this);
3351 checker.check();
3352 #endif
3353 }
3354
3355 void RTLIL::Cell::fixup_parameters(bool set_a_signed, bool set_b_signed)
3356 {
3357 if (!type.begins_with("$") || type.begins_with("$_") || type.begins_with("$paramod") || type.begins_with("$fmcombine") ||
3358 type.begins_with("$verific$") || type.begins_with("$array:") || type.begins_with("$extern:"))
3359 return;
3360
3361 if (type == ID($mux) || type == ID($pmux)) {
3362 parameters[ID::WIDTH] = GetSize(connections_[ID::Y]);
3363 if (type == ID($pmux))
3364 parameters[ID::S_WIDTH] = GetSize(connections_[ID::S]);
3365 check();
3366 return;
3367 }
3368
3369 if (type == ID($lut) || type == ID($sop)) {
3370 parameters[ID::WIDTH] = GetSize(connections_[ID::A]);
3371 return;
3372 }
3373
3374 if (type == ID($fa)) {
3375 parameters[ID::WIDTH] = GetSize(connections_[ID::Y]);
3376 return;
3377 }
3378
3379 if (type == ID($lcu)) {
3380 parameters[ID::WIDTH] = GetSize(connections_[ID::CO]);
3381 return;
3382 }
3383
3384 bool signedness_ab = !type.in(ID($slice), ID($concat), ID($macc));
3385
3386 if (connections_.count(ID::A)) {
3387 if (signedness_ab) {
3388 if (set_a_signed)
3389 parameters[ID::A_SIGNED] = true;
3390 else if (parameters.count(ID::A_SIGNED) == 0)
3391 parameters[ID::A_SIGNED] = false;
3392 }
3393 parameters[ID::A_WIDTH] = GetSize(connections_[ID::A]);
3394 }
3395
3396 if (connections_.count(ID::B)) {
3397 if (signedness_ab) {
3398 if (set_b_signed)
3399 parameters[ID::B_SIGNED] = true;
3400 else if (parameters.count(ID::B_SIGNED) == 0)
3401 parameters[ID::B_SIGNED] = false;
3402 }
3403 parameters[ID::B_WIDTH] = GetSize(connections_[ID::B]);
3404 }
3405
3406 if (connections_.count(ID::Y))
3407 parameters[ID::Y_WIDTH] = GetSize(connections_[ID::Y]);
3408
3409 if (connections_.count(ID::Q))
3410 parameters[ID::WIDTH] = GetSize(connections_[ID::Q]);
3411
3412 check();
3413 }
3414
3415 bool RTLIL::Cell::has_memid() const
3416 {
3417 return type.in(ID($memwr), ID($memwr_v2), ID($memrd), ID($memrd_v2), ID($meminit), ID($meminit_v2));
3418 }
3419
3420 bool RTLIL::Cell::is_mem_cell() const
3421 {
3422 return type.in(ID($mem), ID($mem_v2)) || has_memid();
3423 }
3424
3425 RTLIL::SigChunk::SigChunk()
3426 {
3427 wire = NULL;
3428 width = 0;
3429 offset = 0;
3430 }
3431
3432 RTLIL::SigChunk::SigChunk(const RTLIL::Const &value)
3433 {
3434 wire = NULL;
3435 data = value.bits;
3436 width = GetSize(data);
3437 offset = 0;
3438 }
3439
3440 RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire)
3441 {
3442 log_assert(wire != nullptr);
3443 this->wire = wire;
3444 this->width = wire->width;
3445 this->offset = 0;
3446 }
3447
3448 RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire, int offset, int width)
3449 {
3450 log_assert(wire != nullptr);
3451 this->wire = wire;
3452 this->width = width;
3453 this->offset = offset;
3454 }
3455
3456 RTLIL::SigChunk::SigChunk(const std::string &str)
3457 {
3458 wire = NULL;
3459 data = RTLIL::Const(str).bits;
3460 width = GetSize(data);
3461 offset = 0;
3462 }
3463
3464 RTLIL::SigChunk::SigChunk(int val, int width)
3465 {
3466 wire = NULL;
3467 data = RTLIL::Const(val, width).bits;
3468 this->width = GetSize(data);
3469 offset = 0;
3470 }
3471
3472 RTLIL::SigChunk::SigChunk(RTLIL::State bit, int width)
3473 {
3474 wire = NULL;
3475 data = RTLIL::Const(bit, width).bits;
3476 this->width = GetSize(data);
3477 offset = 0;
3478 }
3479
3480 RTLIL::SigChunk::SigChunk(const RTLIL::SigBit &bit)
3481 {
3482 wire = bit.wire;
3483 offset = 0;
3484 if (wire == NULL)
3485 data = RTLIL::Const(bit.data).bits;
3486 else
3487 offset = bit.offset;
3488 width = 1;
3489 }
3490
3491 RTLIL::SigChunk::SigChunk(const RTLIL::SigChunk &sigchunk)
3492 {
3493 *this = sigchunk;
3494 }
3495
3496 RTLIL::SigChunk RTLIL::SigChunk::extract(int offset, int length) const
3497 {
3498 RTLIL::SigChunk ret;
3499 if (wire) {
3500 ret.wire = wire;
3501 ret.offset = this->offset + offset;
3502 ret.width = length;
3503 } else {
3504 for (int i = 0; i < length; i++)
3505 ret.data.push_back(data[offset+i]);
3506 ret.width = length;
3507 }
3508 return ret;
3509 }
3510
3511 bool RTLIL::SigChunk::operator <(const RTLIL::SigChunk &other) const
3512 {
3513 if (wire && other.wire)
3514 if (wire->name != other.wire->name)
3515 return wire->name < other.wire->name;
3516
3517 if (wire != other.wire)
3518 return wire < other.wire;
3519
3520 if (offset != other.offset)
3521 return offset < other.offset;
3522
3523 if (width != other.width)
3524 return width < other.width;
3525
3526 return data < other.data;
3527 }
3528
3529 bool RTLIL::SigChunk::operator ==(const RTLIL::SigChunk &other) const
3530 {
3531 return wire == other.wire && width == other.width && offset == other.offset && data == other.data;
3532 }
3533
3534 bool RTLIL::SigChunk::operator !=(const RTLIL::SigChunk &other) const
3535 {
3536 if (*this == other)
3537 return false;
3538 return true;
3539 }
3540
3541 RTLIL::SigSpec::SigSpec()
3542 {
3543 width_ = 0;
3544 hash_ = 0;
3545 }
3546
3547 RTLIL::SigSpec::SigSpec(const RTLIL::SigSpec &other)
3548 {
3549 *this = other;
3550 }
3551
3552 RTLIL::SigSpec::SigSpec(std::initializer_list<RTLIL::SigSpec> parts)
3553 {
3554 cover("kernel.rtlil.sigspec.init.list");
3555
3556 width_ = 0;
3557 hash_ = 0;
3558
3559 log_assert(parts.size() > 0);
3560 auto ie = parts.begin();
3561 auto it = ie + parts.size() - 1;
3562 while (it >= ie)
3563 append(*it--);
3564 }
3565
3566 RTLIL::SigSpec &RTLIL::SigSpec::operator=(const RTLIL::SigSpec &other)
3567 {
3568 cover("kernel.rtlil.sigspec.assign");
3569
3570 width_ = other.width_;
3571 hash_ = other.hash_;
3572 chunks_ = other.chunks_;
3573 bits_ = other.bits_;
3574 return *this;
3575 }
3576
3577 RTLIL::SigSpec::SigSpec(const RTLIL::Const &value)
3578 {
3579 cover("kernel.rtlil.sigspec.init.const");
3580
3581 if (GetSize(value) != 0) {
3582 chunks_.emplace_back(value);
3583 width_ = chunks_.back().width;
3584 } else {
3585 width_ = 0;
3586 }
3587 hash_ = 0;
3588 check();
3589 }
3590
3591 RTLIL::SigSpec::SigSpec(const RTLIL::SigChunk &chunk)
3592 {
3593 cover("kernel.rtlil.sigspec.init.chunk");
3594
3595 if (chunk.width != 0) {
3596 chunks_.emplace_back(chunk);
3597 width_ = chunks_.back().width;
3598 } else {
3599 width_ = 0;
3600 }
3601 hash_ = 0;
3602 check();
3603 }
3604
3605 RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire)
3606 {
3607 cover("kernel.rtlil.sigspec.init.wire");
3608
3609 if (wire->width != 0) {
3610 chunks_.emplace_back(wire);
3611 width_ = chunks_.back().width;
3612 } else {
3613 width_ = 0;
3614 }
3615 hash_ = 0;
3616 check();
3617 }
3618
3619 RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire, int offset, int width)
3620 {
3621 cover("kernel.rtlil.sigspec.init.wire_part");
3622
3623 if (width != 0) {
3624 chunks_.emplace_back(wire, offset, width);
3625 width_ = chunks_.back().width;
3626 } else {
3627 width_ = 0;
3628 }
3629 hash_ = 0;
3630 check();
3631 }
3632
3633 RTLIL::SigSpec::SigSpec(const std::string &str)
3634 {
3635 cover("kernel.rtlil.sigspec.init.str");
3636
3637 if (str.size() != 0) {
3638 chunks_.emplace_back(str);
3639 width_ = chunks_.back().width;
3640 } else {
3641 width_ = 0;
3642 }
3643 hash_ = 0;
3644 check();
3645 }
3646
3647 RTLIL::SigSpec::SigSpec(int val, int width)
3648 {
3649 cover("kernel.rtlil.sigspec.init.int");
3650
3651 if (width != 0)
3652 chunks_.emplace_back(val, width);
3653 width_ = width;
3654 hash_ = 0;
3655 check();
3656 }
3657
3658 RTLIL::SigSpec::SigSpec(RTLIL::State bit, int width)
3659 {
3660 cover("kernel.rtlil.sigspec.init.state");
3661
3662 if (width != 0)
3663 chunks_.emplace_back(bit, width);
3664 width_ = width;
3665 hash_ = 0;
3666 check();
3667 }
3668
3669 RTLIL::SigSpec::SigSpec(const RTLIL::SigBit &bit, int width)
3670 {
3671 cover("kernel.rtlil.sigspec.init.bit");
3672
3673 if (width != 0) {
3674 if (bit.wire == NULL)
3675 chunks_.emplace_back(bit.data, width);
3676 else
3677 for (int i = 0; i < width; i++)
3678 chunks_.push_back(bit);
3679 }
3680 width_ = width;
3681 hash_ = 0;
3682 check();
3683 }
3684
3685 RTLIL::SigSpec::SigSpec(const std::vector<RTLIL::SigChunk> &chunks)
3686 {
3687 cover("kernel.rtlil.sigspec.init.stdvec_chunks");
3688
3689 width_ = 0;
3690 hash_ = 0;
3691 for (const auto &c : chunks)
3692 append(c);
3693 check();
3694 }
3695
3696 RTLIL::SigSpec::SigSpec(const std::vector<RTLIL::SigBit> &bits)
3697 {
3698 cover("kernel.rtlil.sigspec.init.stdvec_bits");
3699
3700 width_ = 0;
3701 hash_ = 0;
3702 for (const auto &bit : bits)
3703 append(bit);
3704 check();
3705 }
3706
3707 RTLIL::SigSpec::SigSpec(const pool<RTLIL::SigBit> &bits)
3708 {
3709 cover("kernel.rtlil.sigspec.init.pool_bits");
3710
3711 width_ = 0;
3712 hash_ = 0;
3713 for (const auto &bit : bits)
3714 append(bit);
3715 check();
3716 }
3717
3718 RTLIL::SigSpec::SigSpec(const std::set<RTLIL::SigBit> &bits)
3719 {
3720 cover("kernel.rtlil.sigspec.init.stdset_bits");
3721
3722 width_ = 0;
3723 hash_ = 0;
3724 for (const auto &bit : bits)
3725 append(bit);
3726 check();
3727 }
3728
3729 RTLIL::SigSpec::SigSpec(bool bit)
3730 {
3731 cover("kernel.rtlil.sigspec.init.bool");
3732
3733 width_ = 0;
3734 hash_ = 0;
3735 append(SigBit(bit));
3736 check();
3737 }
3738
3739 void RTLIL::SigSpec::pack() const
3740 {
3741 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
3742
3743 if (that->bits_.empty())
3744 return;
3745
3746 cover("kernel.rtlil.sigspec.convert.pack");
3747 log_assert(that->chunks_.empty());
3748
3749 std::vector<RTLIL::SigBit> old_bits;
3750 old_bits.swap(that->bits_);
3751
3752 RTLIL::SigChunk *last = NULL;
3753 int last_end_offset = 0;
3754
3755 for (auto &bit : old_bits) {
3756 if (last && bit.wire == last->wire) {
3757 if (bit.wire == NULL) {
3758 last->data.push_back(bit.data);
3759 last->width++;
3760 continue;
3761 } else if (last_end_offset == bit.offset) {
3762 last_end_offset++;
3763 last->width++;
3764 continue;
3765 }
3766 }
3767 that->chunks_.push_back(bit);
3768 last = &that->chunks_.back();
3769 last_end_offset = bit.offset + 1;
3770 }
3771
3772 check();
3773 }
3774
3775 void RTLIL::SigSpec::unpack() const
3776 {
3777 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
3778
3779 if (that->chunks_.empty())
3780 return;
3781
3782 cover("kernel.rtlil.sigspec.convert.unpack");
3783 log_assert(that->bits_.empty());
3784
3785 that->bits_.reserve(that->width_);
3786 for (auto &c : that->chunks_)
3787 for (int i = 0; i < c.width; i++)
3788 that->bits_.emplace_back(c, i);
3789
3790 that->chunks_.clear();
3791 that->hash_ = 0;
3792 }
3793
3794 void RTLIL::SigSpec::updhash() const
3795 {
3796 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
3797
3798 if (that->hash_ != 0)
3799 return;
3800
3801 cover("kernel.rtlil.sigspec.hash");
3802 that->pack();
3803
3804 that->hash_ = mkhash_init;
3805 for (auto &c : that->chunks_)
3806 if (c.wire == NULL) {
3807 for (auto &v : c.data)
3808 that->hash_ = mkhash(that->hash_, v);
3809 } else {
3810 that->hash_ = mkhash(that->hash_, c.wire->name.index_);
3811 that->hash_ = mkhash(that->hash_, c.offset);
3812 that->hash_ = mkhash(that->hash_, c.width);
3813 }
3814
3815 if (that->hash_ == 0)
3816 that->hash_ = 1;
3817 }
3818
3819 void RTLIL::SigSpec::sort()
3820 {
3821 unpack();
3822 cover("kernel.rtlil.sigspec.sort");
3823 std::sort(bits_.begin(), bits_.end());
3824 }
3825
3826 void RTLIL::SigSpec::sort_and_unify()
3827 {
3828 unpack();
3829 cover("kernel.rtlil.sigspec.sort_and_unify");
3830
3831 // A copy of the bits vector is used to prevent duplicating the logic from
3832 // SigSpec::SigSpec(std::vector<SigBit>). This incurrs an extra copy but
3833 // that isn't showing up as significant in profiles.
3834 std::vector<SigBit> unique_bits = bits_;
3835 std::sort(unique_bits.begin(), unique_bits.end());
3836 auto last = std::unique(unique_bits.begin(), unique_bits.end());
3837 unique_bits.erase(last, unique_bits.end());
3838
3839 *this = unique_bits;
3840 }
3841
3842 void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with)
3843 {
3844 replace(pattern, with, this);
3845 }
3846
3847 void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with, RTLIL::SigSpec *other) const
3848 {
3849 log_assert(other != NULL);
3850 log_assert(width_ == other->width_);
3851 log_assert(pattern.width_ == with.width_);
3852
3853 pattern.unpack();
3854 with.unpack();
3855 unpack();
3856 other->unpack();
3857
3858 for (int i = 0; i < GetSize(pattern.bits_); i++) {
3859 if (pattern.bits_[i].wire != NULL) {
3860 for (int j = 0; j < GetSize(bits_); j++) {
3861 if (bits_[j] == pattern.bits_[i]) {
3862 other->bits_[j] = with.bits_[i];
3863 }
3864 }
3865 }
3866 }
3867
3868 other->check();
3869 }
3870
3871 void RTLIL::SigSpec::replace(const dict<RTLIL::SigBit, RTLIL::SigBit> &rules)
3872 {
3873 replace(rules, this);
3874 }
3875
3876 void RTLIL::SigSpec::replace(const dict<RTLIL::SigBit, RTLIL::SigBit> &rules, RTLIL::SigSpec *other) const
3877 {
3878 cover("kernel.rtlil.sigspec.replace_dict");
3879
3880 log_assert(other != NULL);
3881 log_assert(width_ == other->width_);
3882
3883 if (rules.empty()) return;
3884 unpack();
3885 other->unpack();
3886
3887 for (int i = 0; i < GetSize(bits_); i++) {
3888 auto it = rules.find(bits_[i]);
3889 if (it != rules.end())
3890 other->bits_[i] = it->second;
3891 }
3892
3893 other->check();
3894 }
3895
3896 void RTLIL::SigSpec::replace(const std::map<RTLIL::SigBit, RTLIL::SigBit> &rules)
3897 {
3898 replace(rules, this);
3899 }
3900
3901 void RTLIL::SigSpec::replace(const std::map<RTLIL::SigBit, RTLIL::SigBit> &rules, RTLIL::SigSpec *other) const
3902 {
3903 cover("kernel.rtlil.sigspec.replace_map");
3904
3905 log_assert(other != NULL);
3906 log_assert(width_ == other->width_);
3907
3908 if (rules.empty()) return;
3909 unpack();
3910 other->unpack();
3911
3912 for (int i = 0; i < GetSize(bits_); i++) {
3913 auto it = rules.find(bits_[i]);
3914 if (it != rules.end())
3915 other->bits_[i] = it->second;
3916 }
3917
3918 other->check();
3919 }
3920
3921 void RTLIL::SigSpec::remove(const RTLIL::SigSpec &pattern)
3922 {
3923 remove2(pattern, NULL);
3924 }
3925
3926 void RTLIL::SigSpec::remove(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other) const
3927 {
3928 RTLIL::SigSpec tmp = *this;
3929 tmp.remove2(pattern, other);
3930 }
3931
3932 void RTLIL::SigSpec::remove2(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other)
3933 {
3934 if (other)
3935 cover("kernel.rtlil.sigspec.remove_other");
3936 else
3937 cover("kernel.rtlil.sigspec.remove");
3938
3939 unpack();
3940 if (other != NULL) {
3941 log_assert(width_ == other->width_);
3942 other->unpack();
3943 }
3944
3945 for (int i = GetSize(bits_) - 1; i >= 0; i--)
3946 {
3947 if (bits_[i].wire == NULL) continue;
3948
3949 for (auto &pattern_chunk : pattern.chunks())
3950 if (bits_[i].wire == pattern_chunk.wire &&
3951 bits_[i].offset >= pattern_chunk.offset &&
3952 bits_[i].offset < pattern_chunk.offset + pattern_chunk.width) {
3953 bits_.erase(bits_.begin() + i);
3954 width_--;
3955 if (other != NULL) {
3956 other->bits_.erase(other->bits_.begin() + i);
3957 other->width_--;
3958 }
3959 break;
3960 }
3961 }
3962
3963 check();
3964 }
3965
3966 void RTLIL::SigSpec::remove(const pool<RTLIL::SigBit> &pattern)
3967 {
3968 remove2(pattern, NULL);
3969 }
3970
3971 void RTLIL::SigSpec::remove(const pool<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other) const
3972 {
3973 RTLIL::SigSpec tmp = *this;
3974 tmp.remove2(pattern, other);
3975 }
3976
3977 void RTLIL::SigSpec::remove2(const pool<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other)
3978 {
3979 if (other)
3980 cover("kernel.rtlil.sigspec.remove_other");
3981 else
3982 cover("kernel.rtlil.sigspec.remove");
3983
3984 unpack();
3985
3986 if (other != NULL) {
3987 log_assert(width_ == other->width_);
3988 other->unpack();
3989 }
3990
3991 for (int i = GetSize(bits_) - 1; i >= 0; i--) {
3992 if (bits_[i].wire != NULL && pattern.count(bits_[i])) {
3993 bits_.erase(bits_.begin() + i);
3994 width_--;
3995 if (other != NULL) {
3996 other->bits_.erase(other->bits_.begin() + i);
3997 other->width_--;
3998 }
3999 }
4000 }
4001
4002 check();
4003 }
4004
4005 void RTLIL::SigSpec::remove2(const std::set<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other)
4006 {
4007 if (other)
4008 cover("kernel.rtlil.sigspec.remove_other");
4009 else
4010 cover("kernel.rtlil.sigspec.remove");
4011
4012 unpack();
4013
4014 if (other != NULL) {
4015 log_assert(width_ == other->width_);
4016 other->unpack();
4017 }
4018
4019 for (int i = GetSize(bits_) - 1; i >= 0; i--) {
4020 if (bits_[i].wire != NULL && pattern.count(bits_[i])) {
4021 bits_.erase(bits_.begin() + i);
4022 width_--;
4023 if (other != NULL) {
4024 other->bits_.erase(other->bits_.begin() + i);
4025 other->width_--;
4026 }
4027 }
4028 }
4029
4030 check();
4031 }
4032
4033 RTLIL::SigSpec RTLIL::SigSpec::extract(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec *other) const
4034 {
4035 if (other)
4036 cover("kernel.rtlil.sigspec.extract_other");
4037 else
4038 cover("kernel.rtlil.sigspec.extract");
4039
4040 log_assert(other == NULL || width_ == other->width_);
4041
4042 RTLIL::SigSpec ret;
4043 std::vector<RTLIL::SigBit> bits_match = to_sigbit_vector();
4044
4045 for (auto& pattern_chunk : pattern.chunks()) {
4046 if (other) {
4047 std::vector<RTLIL::SigBit> bits_other = other->to_sigbit_vector();
4048 for (int i = 0; i < width_; i++)
4049 if (bits_match[i].wire &&
4050 bits_match[i].wire == pattern_chunk.wire &&
4051 bits_match[i].offset >= pattern_chunk.offset &&
4052 bits_match[i].offset < pattern_chunk.offset + pattern_chunk.width)
4053 ret.append(bits_other[i]);
4054 } else {
4055 for (int i = 0; i < width_; i++)
4056 if (bits_match[i].wire &&
4057 bits_match[i].wire == pattern_chunk.wire &&
4058 bits_match[i].offset >= pattern_chunk.offset &&
4059 bits_match[i].offset < pattern_chunk.offset + pattern_chunk.width)
4060 ret.append(bits_match[i]);
4061 }
4062 }
4063
4064 ret.check();
4065 return ret;
4066 }
4067
4068 RTLIL::SigSpec RTLIL::SigSpec::extract(const pool<RTLIL::SigBit> &pattern, const RTLIL::SigSpec *other) const
4069 {
4070 if (other)
4071 cover("kernel.rtlil.sigspec.extract_other");
4072 else
4073 cover("kernel.rtlil.sigspec.extract");
4074
4075 log_assert(other == NULL || width_ == other->width_);
4076
4077 std::vector<RTLIL::SigBit> bits_match = to_sigbit_vector();
4078 RTLIL::SigSpec ret;
4079
4080 if (other) {
4081 std::vector<RTLIL::SigBit> bits_other = other->to_sigbit_vector();
4082 for (int i = 0; i < width_; i++)
4083 if (bits_match[i].wire && pattern.count(bits_match[i]))
4084 ret.append(bits_other[i]);
4085 } else {
4086 for (int i = 0; i < width_; i++)
4087 if (bits_match[i].wire && pattern.count(bits_match[i]))
4088 ret.append(bits_match[i]);
4089 }
4090
4091 ret.check();
4092 return ret;
4093 }
4094
4095 void RTLIL::SigSpec::replace(int offset, const RTLIL::SigSpec &with)
4096 {
4097 cover("kernel.rtlil.sigspec.replace_pos");
4098
4099 unpack();
4100 with.unpack();
4101
4102 log_assert(offset >= 0);
4103 log_assert(with.width_ >= 0);
4104 log_assert(offset+with.width_ <= width_);
4105
4106 for (int i = 0; i < with.width_; i++)
4107 bits_.at(offset + i) = with.bits_.at(i);
4108
4109 check();
4110 }
4111
4112 void RTLIL::SigSpec::remove_const()
4113 {
4114 if (packed())
4115 {
4116 cover("kernel.rtlil.sigspec.remove_const.packed");
4117
4118 std::vector<RTLIL::SigChunk> new_chunks;
4119 new_chunks.reserve(GetSize(chunks_));
4120
4121 width_ = 0;
4122 for (auto &chunk : chunks_)
4123 if (chunk.wire != NULL) {
4124 if (!new_chunks.empty() &&
4125 new_chunks.back().wire == chunk.wire &&
4126 new_chunks.back().offset + new_chunks.back().width == chunk.offset) {
4127 new_chunks.back().width += chunk.width;
4128 } else {
4129 new_chunks.push_back(chunk);
4130 }
4131 width_ += chunk.width;
4132 }
4133
4134 chunks_.swap(new_chunks);
4135 }
4136 else
4137 {
4138 cover("kernel.rtlil.sigspec.remove_const.unpacked");
4139
4140 std::vector<RTLIL::SigBit> new_bits;
4141 new_bits.reserve(width_);
4142
4143 for (auto &bit : bits_)
4144 if (bit.wire != NULL)
4145 new_bits.push_back(bit);
4146
4147 bits_.swap(new_bits);
4148 width_ = bits_.size();
4149 }
4150
4151 check();
4152 }
4153
4154 void RTLIL::SigSpec::remove(int offset, int length)
4155 {
4156 cover("kernel.rtlil.sigspec.remove_pos");
4157
4158 unpack();
4159
4160 log_assert(offset >= 0);
4161 log_assert(length >= 0);
4162 log_assert(offset + length <= width_);
4163
4164 bits_.erase(bits_.begin() + offset, bits_.begin() + offset + length);
4165 width_ = bits_.size();
4166
4167 check();
4168 }
4169
4170 RTLIL::SigSpec RTLIL::SigSpec::extract(int offset, int length) const
4171 {
4172 unpack();
4173 cover("kernel.rtlil.sigspec.extract_pos");
4174 return std::vector<RTLIL::SigBit>(bits_.begin() + offset, bits_.begin() + offset + length);
4175 }
4176
4177 void RTLIL::SigSpec::append(const RTLIL::SigSpec &signal)
4178 {
4179 if (signal.width_ == 0)
4180 return;
4181
4182 if (width_ == 0) {
4183 *this = signal;
4184 return;
4185 }
4186
4187 cover("kernel.rtlil.sigspec.append");
4188
4189 if (packed() != signal.packed()) {
4190 pack();
4191 signal.pack();
4192 }
4193
4194 if (packed())
4195 for (auto &other_c : signal.chunks_)
4196 {
4197 auto &my_last_c = chunks_.back();
4198 if (my_last_c.wire == NULL && other_c.wire == NULL) {
4199 auto &this_data = my_last_c.data;
4200 auto &other_data = other_c.data;
4201 this_data.insert(this_data.end(), other_data.begin(), other_data.end());
4202 my_last_c.width += other_c.width;
4203 } else
4204 if (my_last_c.wire == other_c.wire && my_last_c.offset + my_last_c.width == other_c.offset) {
4205 my_last_c.width += other_c.width;
4206 } else
4207 chunks_.push_back(other_c);
4208 }
4209 else
4210 bits_.insert(bits_.end(), signal.bits_.begin(), signal.bits_.end());
4211
4212 width_ += signal.width_;
4213 check();
4214 }
4215
4216 void RTLIL::SigSpec::append(const RTLIL::SigBit &bit)
4217 {
4218 if (packed())
4219 {
4220 cover("kernel.rtlil.sigspec.append_bit.packed");
4221
4222 if (chunks_.size() == 0)
4223 chunks_.push_back(bit);
4224 else
4225 if (bit.wire == NULL)
4226 if (chunks_.back().wire == NULL) {
4227 chunks_.back().data.push_back(bit.data);
4228 chunks_.back().width++;
4229 } else
4230 chunks_.push_back(bit);
4231 else
4232 if (chunks_.back().wire == bit.wire && chunks_.back().offset + chunks_.back().width == bit.offset)
4233 chunks_.back().width++;
4234 else
4235 chunks_.push_back(bit);
4236 }
4237 else
4238 {
4239 cover("kernel.rtlil.sigspec.append_bit.unpacked");
4240 bits_.push_back(bit);
4241 }
4242
4243 width_++;
4244 check();
4245 }
4246
4247 void RTLIL::SigSpec::extend_u0(int width, bool is_signed)
4248 {
4249 cover("kernel.rtlil.sigspec.extend_u0");
4250
4251 pack();
4252
4253 if (width_ > width)
4254 remove(width, width_ - width);
4255
4256 if (width_ < width) {
4257 RTLIL::SigBit padding = width_ > 0 ? (*this)[width_ - 1] : RTLIL::State::Sx;
4258 if (!is_signed)
4259 padding = RTLIL::State::S0;
4260 while (width_ < width)
4261 append(padding);
4262 }
4263
4264 }
4265
4266 RTLIL::SigSpec RTLIL::SigSpec::repeat(int num) const
4267 {
4268 cover("kernel.rtlil.sigspec.repeat");
4269
4270 RTLIL::SigSpec sig;
4271 for (int i = 0; i < num; i++)
4272 sig.append(*this);
4273 return sig;
4274 }
4275
4276 #ifndef NDEBUG
4277 void RTLIL::SigSpec::check(Module *mod) const
4278 {
4279 if (width_ > 64)
4280 {
4281 cover("kernel.rtlil.sigspec.check.skip");
4282 }
4283 else if (packed())
4284 {
4285 cover("kernel.rtlil.sigspec.check.packed");
4286
4287 int w = 0;
4288 for (size_t i = 0; i < chunks_.size(); i++) {
4289 const RTLIL::SigChunk &chunk = chunks_[i];
4290 log_assert(chunk.width != 0);
4291 if (chunk.wire == NULL) {
4292 if (i > 0)
4293 log_assert(chunks_[i-1].wire != NULL);
4294 log_assert(chunk.offset == 0);
4295 log_assert(chunk.data.size() == (size_t)chunk.width);
4296 } else {
4297 if (i > 0 && chunks_[i-1].wire == chunk.wire)
4298 log_assert(chunk.offset != chunks_[i-1].offset + chunks_[i-1].width);
4299 log_assert(chunk.offset >= 0);
4300 log_assert(chunk.width >= 0);
4301 log_assert(chunk.offset + chunk.width <= chunk.wire->width);
4302 log_assert(chunk.data.size() == 0);
4303 if (mod != nullptr)
4304 log_assert(chunk.wire->module == mod);
4305 }
4306 w += chunk.width;
4307 }
4308 log_assert(w == width_);
4309 log_assert(bits_.empty());
4310 }
4311 else
4312 {
4313 cover("kernel.rtlil.sigspec.check.unpacked");
4314
4315 if (mod != nullptr) {
4316 for (size_t i = 0; i < bits_.size(); i++)
4317 if (bits_[i].wire != nullptr)
4318 log_assert(bits_[i].wire->module == mod);
4319 }
4320
4321 log_assert(width_ == GetSize(bits_));
4322 log_assert(chunks_.empty());
4323 }
4324 }
4325 #endif
4326
4327 bool RTLIL::SigSpec::operator <(const RTLIL::SigSpec &other) const
4328 {
4329 cover("kernel.rtlil.sigspec.comp_lt");
4330
4331 if (this == &other)
4332 return false;
4333
4334 if (width_ != other.width_)
4335 return width_ < other.width_;
4336
4337 pack();
4338 other.pack();
4339
4340 if (chunks_.size() != other.chunks_.size())
4341 return chunks_.size() < other.chunks_.size();
4342
4343 updhash();
4344 other.updhash();
4345
4346 if (hash_ != other.hash_)
4347 return hash_ < other.hash_;
4348
4349 for (size_t i = 0; i < chunks_.size(); i++)
4350 if (chunks_[i] != other.chunks_[i]) {
4351 cover("kernel.rtlil.sigspec.comp_lt.hash_collision");
4352 return chunks_[i] < other.chunks_[i];
4353 }
4354
4355 cover("kernel.rtlil.sigspec.comp_lt.equal");
4356 return false;
4357 }
4358
4359 bool RTLIL::SigSpec::operator ==(const RTLIL::SigSpec &other) const
4360 {
4361 cover("kernel.rtlil.sigspec.comp_eq");
4362
4363 if (this == &other)
4364 return true;
4365
4366 if (width_ != other.width_)
4367 return false;
4368
4369 // Without this, SigSpec() == SigSpec(State::S0, 0) will fail
4370 // since the RHS will contain one SigChunk of width 0 causing
4371 // the size check below to fail
4372 if (width_ == 0)
4373 return true;
4374
4375 pack();
4376 other.pack();
4377
4378 if (chunks_.size() != other.chunks_.size())
4379 return false;
4380
4381 updhash();
4382 other.updhash();
4383
4384 if (hash_ != other.hash_)
4385 return false;
4386
4387 for (size_t i = 0; i < chunks_.size(); i++)
4388 if (chunks_[i] != other.chunks_[i]) {
4389 cover("kernel.rtlil.sigspec.comp_eq.hash_collision");
4390 return false;
4391 }
4392
4393 cover("kernel.rtlil.sigspec.comp_eq.equal");
4394 return true;
4395 }
4396
4397 bool RTLIL::SigSpec::is_wire() const
4398 {
4399 cover("kernel.rtlil.sigspec.is_wire");
4400
4401 pack();
4402 return GetSize(chunks_) == 1 && chunks_[0].wire && chunks_[0].wire->width == width_;
4403 }
4404
4405 bool RTLIL::SigSpec::is_chunk() const
4406 {
4407 cover("kernel.rtlil.sigspec.is_chunk");
4408
4409 pack();
4410 return GetSize(chunks_) == 1;
4411 }
4412
4413 bool RTLIL::SigSpec::is_fully_const() const
4414 {
4415 cover("kernel.rtlil.sigspec.is_fully_const");
4416
4417 pack();
4418 for (auto it = chunks_.begin(); it != chunks_.end(); it++)
4419 if (it->width > 0 && it->wire != NULL)
4420 return false;
4421 return true;
4422 }
4423
4424 bool RTLIL::SigSpec::is_fully_zero() const
4425 {
4426 cover("kernel.rtlil.sigspec.is_fully_zero");
4427
4428 pack();
4429 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
4430 if (it->width > 0 && it->wire != NULL)
4431 return false;
4432 for (size_t i = 0; i < it->data.size(); i++)
4433 if (it->data[i] != RTLIL::State::S0)
4434 return false;
4435 }
4436 return true;
4437 }
4438
4439 bool RTLIL::SigSpec::is_fully_ones() const
4440 {
4441 cover("kernel.rtlil.sigspec.is_fully_ones");
4442
4443 pack();
4444 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
4445 if (it->width > 0 && it->wire != NULL)
4446 return false;
4447 for (size_t i = 0; i < it->data.size(); i++)
4448 if (it->data[i] != RTLIL::State::S1)
4449 return false;
4450 }
4451 return true;
4452 }
4453
4454 bool RTLIL::SigSpec::is_fully_def() const
4455 {
4456 cover("kernel.rtlil.sigspec.is_fully_def");
4457
4458 pack();
4459 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
4460 if (it->width > 0 && it->wire != NULL)
4461 return false;
4462 for (size_t i = 0; i < it->data.size(); i++)
4463 if (it->data[i] != RTLIL::State::S0 && it->data[i] != RTLIL::State::S1)
4464 return false;
4465 }
4466 return true;
4467 }
4468
4469 bool RTLIL::SigSpec::is_fully_undef() const
4470 {
4471 cover("kernel.rtlil.sigspec.is_fully_undef");
4472
4473 pack();
4474 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
4475 if (it->width > 0 && it->wire != NULL)
4476 return false;
4477 for (size_t i = 0; i < it->data.size(); i++)
4478 if (it->data[i] != RTLIL::State::Sx && it->data[i] != RTLIL::State::Sz)
4479 return false;
4480 }
4481 return true;
4482 }
4483
4484 bool RTLIL::SigSpec::has_const() const
4485 {
4486 cover("kernel.rtlil.sigspec.has_const");
4487
4488 pack();
4489 for (auto it = chunks_.begin(); it != chunks_.end(); it++)
4490 if (it->width > 0 && it->wire == NULL)
4491 return true;
4492 return false;
4493 }
4494
4495 bool RTLIL::SigSpec::has_marked_bits() const
4496 {
4497 cover("kernel.rtlil.sigspec.has_marked_bits");
4498
4499 pack();
4500 for (auto it = chunks_.begin(); it != chunks_.end(); it++)
4501 if (it->width > 0 && it->wire == NULL) {
4502 for (size_t i = 0; i < it->data.size(); i++)
4503 if (it->data[i] == RTLIL::State::Sm)
4504 return true;
4505 }
4506 return false;
4507 }
4508
4509 bool RTLIL::SigSpec::is_onehot(int *pos) const
4510 {
4511 cover("kernel.rtlil.sigspec.is_onehot");
4512
4513 pack();
4514 if (!is_fully_const())
4515 return false;
4516 log_assert(GetSize(chunks_) <= 1);
4517 if (width_)
4518 return RTLIL::Const(chunks_[0].data).is_onehot(pos);
4519 return false;
4520 }
4521
4522 bool RTLIL::SigSpec::as_bool() const
4523 {
4524 cover("kernel.rtlil.sigspec.as_bool");
4525
4526 pack();
4527 log_assert(is_fully_const() && GetSize(chunks_) <= 1);
4528 if (width_)
4529 return RTLIL::Const(chunks_[0].data).as_bool();
4530 return false;
4531 }
4532
4533 int RTLIL::SigSpec::as_int(bool is_signed) const
4534 {
4535 cover("kernel.rtlil.sigspec.as_int");
4536
4537 pack();
4538 log_assert(is_fully_const() && GetSize(chunks_) <= 1);
4539 if (width_)
4540 return RTLIL::Const(chunks_[0].data).as_int(is_signed);
4541 return 0;
4542 }
4543
4544 std::string RTLIL::SigSpec::as_string() const
4545 {
4546 cover("kernel.rtlil.sigspec.as_string");
4547
4548 pack();
4549 std::string str;
4550 str.reserve(size());
4551 for (size_t i = chunks_.size(); i > 0; i--) {
4552 const RTLIL::SigChunk &chunk = chunks_[i-1];
4553 if (chunk.wire != NULL)
4554 str.append(chunk.width, '?');
4555 else
4556 str += RTLIL::Const(chunk.data).as_string();
4557 }
4558 return str;
4559 }
4560
4561 RTLIL::Const RTLIL::SigSpec::as_const() const
4562 {
4563 cover("kernel.rtlil.sigspec.as_const");
4564
4565 pack();
4566 log_assert(is_fully_const() && GetSize(chunks_) <= 1);
4567 if (width_)
4568 return chunks_[0].data;
4569 return RTLIL::Const();
4570 }
4571
4572 RTLIL::Wire *RTLIL::SigSpec::as_wire() const
4573 {
4574 cover("kernel.rtlil.sigspec.as_wire");
4575
4576 pack();
4577 log_assert(is_wire());
4578 return chunks_[0].wire;
4579 }
4580
4581 RTLIL::SigChunk RTLIL::SigSpec::as_chunk() const
4582 {
4583 cover("kernel.rtlil.sigspec.as_chunk");
4584
4585 pack();
4586 log_assert(is_chunk());
4587 return chunks_[0];
4588 }
4589
4590 RTLIL::SigBit RTLIL::SigSpec::as_bit() const
4591 {
4592 cover("kernel.rtlil.sigspec.as_bit");
4593
4594 log_assert(width_ == 1);
4595 if (packed())
4596 return RTLIL::SigBit(*chunks_.begin());
4597 else
4598 return bits_[0];
4599 }
4600
4601 bool RTLIL::SigSpec::match(const char* pattern) const
4602 {
4603 cover("kernel.rtlil.sigspec.match");
4604
4605 unpack();
4606 log_assert(int(strlen(pattern)) == GetSize(bits_));
4607
4608 for (auto it = bits_.rbegin(); it != bits_.rend(); it++, pattern++) {
4609 if (*pattern == ' ')
4610 continue;
4611 if (*pattern == '*') {
4612 if (*it != State::Sz && *it != State::Sx)
4613 return false;
4614 continue;
4615 }
4616 if (*pattern == '0') {
4617 if (*it != State::S0)
4618 return false;
4619 } else
4620 if (*pattern == '1') {
4621 if (*it != State::S1)
4622 return false;
4623 } else
4624 log_abort();
4625 }
4626
4627 return true;
4628 }
4629
4630 std::set<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_set() const
4631 {
4632 cover("kernel.rtlil.sigspec.to_sigbit_set");
4633
4634 pack();
4635 std::set<RTLIL::SigBit> sigbits;
4636 for (auto &c : chunks_)
4637 for (int i = 0; i < c.width; i++)
4638 sigbits.insert(RTLIL::SigBit(c, i));
4639 return sigbits;
4640 }
4641
4642 pool<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_pool() const
4643 {
4644 cover("kernel.rtlil.sigspec.to_sigbit_pool");
4645
4646 pack();
4647 pool<RTLIL::SigBit> sigbits;
4648 sigbits.reserve(size());
4649 for (auto &c : chunks_)
4650 for (int i = 0; i < c.width; i++)
4651 sigbits.insert(RTLIL::SigBit(c, i));
4652 return sigbits;
4653 }
4654
4655 std::vector<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_vector() const
4656 {
4657 cover("kernel.rtlil.sigspec.to_sigbit_vector");
4658
4659 unpack();
4660 return bits_;
4661 }
4662
4663 std::map<RTLIL::SigBit, RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_map(const RTLIL::SigSpec &other) const
4664 {
4665 cover("kernel.rtlil.sigspec.to_sigbit_map");
4666
4667 unpack();
4668 other.unpack();
4669
4670 log_assert(width_ == other.width_);
4671
4672 std::map<RTLIL::SigBit, RTLIL::SigBit> new_map;
4673 for (int i = 0; i < width_; i++)
4674 new_map[bits_[i]] = other.bits_[i];
4675
4676 return new_map;
4677 }
4678
4679 dict<RTLIL::SigBit, RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_dict(const RTLIL::SigSpec &other) const
4680 {
4681 cover("kernel.rtlil.sigspec.to_sigbit_dict");
4682
4683 unpack();
4684 other.unpack();
4685
4686 log_assert(width_ == other.width_);
4687
4688 dict<RTLIL::SigBit, RTLIL::SigBit> new_map;
4689 new_map.reserve(size());
4690 for (int i = 0; i < width_; i++)
4691 new_map[bits_[i]] = other.bits_[i];
4692
4693 return new_map;
4694 }
4695
4696 static void sigspec_parse_split(std::vector<std::string> &tokens, const std::string &text, char sep)
4697 {
4698 size_t start = 0, end = 0;
4699 while ((end = text.find(sep, start)) != std::string::npos) {
4700 tokens.push_back(text.substr(start, end - start));
4701 start = end + 1;
4702 }
4703 tokens.push_back(text.substr(start));
4704 }
4705
4706 static int sigspec_parse_get_dummy_line_num()
4707 {
4708 return 0;
4709 }
4710
4711 bool RTLIL::SigSpec::parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str)
4712 {
4713 cover("kernel.rtlil.sigspec.parse");
4714
4715 AST::current_filename = "input";
4716
4717 std::vector<std::string> tokens;
4718 sigspec_parse_split(tokens, str, ',');
4719
4720 sig = RTLIL::SigSpec();
4721 for (int tokidx = int(tokens.size())-1; tokidx >= 0; tokidx--)
4722 {
4723 std::string netname = tokens[tokidx];
4724 std::string indices;
4725
4726 if (netname.size() == 0)
4727 continue;
4728
4729 if (('0' <= netname[0] && netname[0] <= '9') || netname[0] == '\'') {
4730 cover("kernel.rtlil.sigspec.parse.const");
4731 AST::get_line_num = sigspec_parse_get_dummy_line_num;
4732 AST::AstNode *ast = VERILOG_FRONTEND::const2ast(netname);
4733 if (ast == NULL)
4734 return false;
4735 sig.append(RTLIL::Const(ast->bits));
4736 delete ast;
4737 continue;
4738 }
4739
4740 if (module == NULL)
4741 return false;
4742
4743 cover("kernel.rtlil.sigspec.parse.net");
4744
4745 if (netname[0] != '$' && netname[0] != '\\')
4746 netname = "\\" + netname;
4747
4748 if (module->wires_.count(netname) == 0) {
4749 size_t indices_pos = netname.size()-1;
4750 if (indices_pos > 2 && netname[indices_pos] == ']')
4751 {
4752 indices_pos--;
4753 while (indices_pos > 0 && ('0' <= netname[indices_pos] && netname[indices_pos] <= '9')) indices_pos--;
4754 if (indices_pos > 0 && netname[indices_pos] == ':') {
4755 indices_pos--;
4756 while (indices_pos > 0 && ('0' <= netname[indices_pos] && netname[indices_pos] <= '9')) indices_pos--;
4757 }
4758 if (indices_pos > 0 && netname[indices_pos] == '[') {
4759 indices = netname.substr(indices_pos);
4760 netname = netname.substr(0, indices_pos);
4761 }
4762 }
4763 }
4764
4765 if (module->wires_.count(netname) == 0)
4766 return false;
4767
4768 RTLIL::Wire *wire = module->wires_.at(netname);
4769 if (!indices.empty()) {
4770 std::vector<std::string> index_tokens;
4771 sigspec_parse_split(index_tokens, indices.substr(1, indices.size()-2), ':');
4772 if (index_tokens.size() == 1) {
4773 cover("kernel.rtlil.sigspec.parse.bit_sel");
4774 int a = atoi(index_tokens.at(0).c_str());
4775 if (a < 0 || a >= wire->width)
4776 return false;
4777 sig.append(RTLIL::SigSpec(wire, a));
4778 } else {
4779 cover("kernel.rtlil.sigspec.parse.part_sel");
4780 int a = atoi(index_tokens.at(0).c_str());
4781 int b = atoi(index_tokens.at(1).c_str());
4782 if (a > b) {
4783 int tmp = a;
4784 a = b, b = tmp;
4785 }
4786 if (a < 0 || a >= wire->width)
4787 return false;
4788 if (b < 0 || b >= wire->width)
4789 return false;
4790 sig.append(RTLIL::SigSpec(wire, a, b-a+1));
4791 }
4792 } else
4793 sig.append(wire);
4794 }
4795
4796 return true;
4797 }
4798
4799 bool RTLIL::SigSpec::parse_sel(RTLIL::SigSpec &sig, RTLIL::Design *design, RTLIL::Module *module, std::string str)
4800 {
4801 if (str.empty() || str[0] != '@')
4802 return parse(sig, module, str);
4803
4804 cover("kernel.rtlil.sigspec.parse.sel");
4805
4806 str = RTLIL::escape_id(str.substr(1));
4807 if (design->selection_vars.count(str) == 0)
4808 return false;
4809
4810 sig = RTLIL::SigSpec();
4811 RTLIL::Selection &sel = design->selection_vars.at(str);
4812 for (auto &it : module->wires_)
4813 if (sel.selected_member(module->name, it.first))
4814 sig.append(it.second);
4815
4816 return true;
4817 }
4818
4819 bool RTLIL::SigSpec::parse_rhs(const RTLIL::SigSpec &lhs, RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str)
4820 {
4821 if (str == "0") {
4822 cover("kernel.rtlil.sigspec.parse.rhs_zeros");
4823 sig = RTLIL::SigSpec(RTLIL::State::S0, lhs.width_);
4824 return true;
4825 }
4826
4827 if (str == "~0") {
4828 cover("kernel.rtlil.sigspec.parse.rhs_ones");
4829 sig = RTLIL::SigSpec(RTLIL::State::S1, lhs.width_);
4830 return true;
4831 }
4832
4833 if (lhs.chunks_.size() == 1) {
4834 char *p = (char*)str.c_str(), *endptr;
4835 long int val = strtol(p, &endptr, 10);
4836 if (endptr && endptr != p && *endptr == 0) {
4837 sig = RTLIL::SigSpec(val, lhs.width_);
4838 cover("kernel.rtlil.sigspec.parse.rhs_dec");
4839 return true;
4840 }
4841 }
4842
4843 return parse(sig, module, str);
4844 }
4845
4846 RTLIL::CaseRule::~CaseRule()
4847 {
4848 for (auto it = switches.begin(); it != switches.end(); it++)
4849 delete *it;
4850 }
4851
4852 bool RTLIL::CaseRule::empty() const
4853 {
4854 return actions.empty() && switches.empty();
4855 }
4856
4857 RTLIL::CaseRule *RTLIL::CaseRule::clone() const
4858 {
4859 RTLIL::CaseRule *new_caserule = new RTLIL::CaseRule;
4860 new_caserule->compare = compare;
4861 new_caserule->actions = actions;
4862 for (auto &it : switches)
4863 new_caserule->switches.push_back(it->clone());
4864 return new_caserule;
4865 }
4866
4867 RTLIL::SwitchRule::~SwitchRule()
4868 {
4869 for (auto it = cases.begin(); it != cases.end(); it++)
4870 delete *it;
4871 }
4872
4873 bool RTLIL::SwitchRule::empty() const
4874 {
4875 return cases.empty();
4876 }
4877
4878 RTLIL::SwitchRule *RTLIL::SwitchRule::clone() const
4879 {
4880 RTLIL::SwitchRule *new_switchrule = new RTLIL::SwitchRule;
4881 new_switchrule->signal = signal;
4882 new_switchrule->attributes = attributes;
4883 for (auto &it : cases)
4884 new_switchrule->cases.push_back(it->clone());
4885 return new_switchrule;
4886
4887 }
4888
4889 RTLIL::SyncRule *RTLIL::SyncRule::clone() const
4890 {
4891 RTLIL::SyncRule *new_syncrule = new RTLIL::SyncRule;
4892 new_syncrule->type = type;
4893 new_syncrule->signal = signal;
4894 new_syncrule->actions = actions;
4895 new_syncrule->mem_write_actions = mem_write_actions;
4896 return new_syncrule;
4897 }
4898
4899 RTLIL::Process::~Process()
4900 {
4901 for (auto it = syncs.begin(); it != syncs.end(); it++)
4902 delete *it;
4903 }
4904
4905 RTLIL::Process *RTLIL::Process::clone() const
4906 {
4907 RTLIL::Process *new_proc = new RTLIL::Process;
4908
4909 new_proc->name = name;
4910 new_proc->attributes = attributes;
4911
4912 RTLIL::CaseRule *rc_ptr = root_case.clone();
4913 new_proc->root_case = *rc_ptr;
4914 rc_ptr->switches.clear();
4915 delete rc_ptr;
4916
4917 for (auto &it : syncs)
4918 new_proc->syncs.push_back(it->clone());
4919
4920 return new_proc;
4921 }
4922
4923 #ifdef WITH_PYTHON
4924 RTLIL::Memory::~Memory()
4925 {
4926 RTLIL::Memory::get_all_memorys()->erase(hashidx_);
4927 }
4928 static std::map<unsigned int, RTLIL::Memory*> all_memorys;
4929 std::map<unsigned int, RTLIL::Memory*> *RTLIL::Memory::get_all_memorys(void)
4930 {
4931 return &all_memorys;
4932 }
4933 #endif
4934 YOSYS_NAMESPACE_END