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efinix: Nuke efinix_gbuf in favor of clkbufmap.
[yosys.git] / kernel / rtlil.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 #include "kernel/yosys.h"
21 #include "kernel/macc.h"
22 #include "kernel/celltypes.h"
23 #include "frontends/verilog/verilog_frontend.h"
24 #include "frontends/verilog/preproc.h"
25 #include "backends/ilang/ilang_backend.h"
26
27 #include <string.h>
28 #include <algorithm>
29
30 YOSYS_NAMESPACE_BEGIN
31
32 RTLIL::IdString::destruct_guard_t RTLIL::IdString::destruct_guard;
33 std::vector<char*> RTLIL::IdString::global_id_storage_;
34 dict<char*, int, hash_cstr_ops> RTLIL::IdString::global_id_index_;
35 #ifndef YOSYS_NO_IDS_REFCNT
36 std::vector<int> RTLIL::IdString::global_refcount_storage_;
37 std::vector<int> RTLIL::IdString::global_free_idx_list_;
38 #endif
39 #ifdef YOSYS_USE_STICKY_IDS
40 int RTLIL::IdString::last_created_idx_[8];
41 int RTLIL::IdString::last_created_idx_ptr_;
42 #endif
43
44 #define X(_id) IdString RTLIL::ID::_id;
45 #include "kernel/constids.inc"
46 #undef X
47
48 dict<std::string, std::string> RTLIL::constpad;
49
50 const pool<IdString> &RTLIL::builtin_ff_cell_types() {
51 static const pool<IdString> res = {
52 ID($sr),
53 ID($ff),
54 ID($dff),
55 ID($dffe),
56 ID($dffsr),
57 ID($dffsre),
58 ID($adff),
59 ID($adffe),
60 ID($sdff),
61 ID($sdffe),
62 ID($sdffce),
63 ID($dlatch),
64 ID($adlatch),
65 ID($dlatchsr),
66 ID($_DFFE_NN_),
67 ID($_DFFE_NP_),
68 ID($_DFFE_PN_),
69 ID($_DFFE_PP_),
70 ID($_DFFSR_NNN_),
71 ID($_DFFSR_NNP_),
72 ID($_DFFSR_NPN_),
73 ID($_DFFSR_NPP_),
74 ID($_DFFSR_PNN_),
75 ID($_DFFSR_PNP_),
76 ID($_DFFSR_PPN_),
77 ID($_DFFSR_PPP_),
78 ID($_DFFSRE_NNNN_),
79 ID($_DFFSRE_NNNP_),
80 ID($_DFFSRE_NNPN_),
81 ID($_DFFSRE_NNPP_),
82 ID($_DFFSRE_NPNN_),
83 ID($_DFFSRE_NPNP_),
84 ID($_DFFSRE_NPPN_),
85 ID($_DFFSRE_NPPP_),
86 ID($_DFFSRE_PNNN_),
87 ID($_DFFSRE_PNNP_),
88 ID($_DFFSRE_PNPN_),
89 ID($_DFFSRE_PNPP_),
90 ID($_DFFSRE_PPNN_),
91 ID($_DFFSRE_PPNP_),
92 ID($_DFFSRE_PPPN_),
93 ID($_DFFSRE_PPPP_),
94 ID($_DFF_N_),
95 ID($_DFF_P_),
96 ID($_DFF_NN0_),
97 ID($_DFF_NN1_),
98 ID($_DFF_NP0_),
99 ID($_DFF_NP1_),
100 ID($_DFF_PN0_),
101 ID($_DFF_PN1_),
102 ID($_DFF_PP0_),
103 ID($_DFF_PP1_),
104 ID($_DFFE_NN0N_),
105 ID($_DFFE_NN0P_),
106 ID($_DFFE_NN1N_),
107 ID($_DFFE_NN1P_),
108 ID($_DFFE_NP0N_),
109 ID($_DFFE_NP0P_),
110 ID($_DFFE_NP1N_),
111 ID($_DFFE_NP1P_),
112 ID($_DFFE_PN0N_),
113 ID($_DFFE_PN0P_),
114 ID($_DFFE_PN1N_),
115 ID($_DFFE_PN1P_),
116 ID($_DFFE_PP0N_),
117 ID($_DFFE_PP0P_),
118 ID($_DFFE_PP1N_),
119 ID($_DFFE_PP1P_),
120 ID($_SDFF_NN0_),
121 ID($_SDFF_NN1_),
122 ID($_SDFF_NP0_),
123 ID($_SDFF_NP1_),
124 ID($_SDFF_PN0_),
125 ID($_SDFF_PN1_),
126 ID($_SDFF_PP0_),
127 ID($_SDFF_PP1_),
128 ID($_SDFFE_NN0N_),
129 ID($_SDFFE_NN0P_),
130 ID($_SDFFE_NN1N_),
131 ID($_SDFFE_NN1P_),
132 ID($_SDFFE_NP0N_),
133 ID($_SDFFE_NP0P_),
134 ID($_SDFFE_NP1N_),
135 ID($_SDFFE_NP1P_),
136 ID($_SDFFE_PN0N_),
137 ID($_SDFFE_PN0P_),
138 ID($_SDFFE_PN1N_),
139 ID($_SDFFE_PN1P_),
140 ID($_SDFFE_PP0N_),
141 ID($_SDFFE_PP0P_),
142 ID($_SDFFE_PP1N_),
143 ID($_SDFFE_PP1P_),
144 ID($_SDFFCE_NN0N_),
145 ID($_SDFFCE_NN0P_),
146 ID($_SDFFCE_NN1N_),
147 ID($_SDFFCE_NN1P_),
148 ID($_SDFFCE_NP0N_),
149 ID($_SDFFCE_NP0P_),
150 ID($_SDFFCE_NP1N_),
151 ID($_SDFFCE_NP1P_),
152 ID($_SDFFCE_PN0N_),
153 ID($_SDFFCE_PN0P_),
154 ID($_SDFFCE_PN1N_),
155 ID($_SDFFCE_PN1P_),
156 ID($_SDFFCE_PP0N_),
157 ID($_SDFFCE_PP0P_),
158 ID($_SDFFCE_PP1N_),
159 ID($_SDFFCE_PP1P_),
160 ID($_SR_NN_),
161 ID($_SR_NP_),
162 ID($_SR_PN_),
163 ID($_SR_PP_),
164 ID($_DLATCH_N_),
165 ID($_DLATCH_P_),
166 ID($_DLATCH_NN0_),
167 ID($_DLATCH_NN1_),
168 ID($_DLATCH_NP0_),
169 ID($_DLATCH_NP1_),
170 ID($_DLATCH_PN0_),
171 ID($_DLATCH_PN1_),
172 ID($_DLATCH_PP0_),
173 ID($_DLATCH_PP1_),
174 ID($_DLATCHSR_NNN_),
175 ID($_DLATCHSR_NNP_),
176 ID($_DLATCHSR_NPN_),
177 ID($_DLATCHSR_NPP_),
178 ID($_DLATCHSR_PNN_),
179 ID($_DLATCHSR_PNP_),
180 ID($_DLATCHSR_PPN_),
181 ID($_DLATCHSR_PPP_),
182 ID($_FF_),
183 };
184 return res;
185 }
186
187 RTLIL::Const::Const()
188 {
189 flags = RTLIL::CONST_FLAG_NONE;
190 }
191
192 RTLIL::Const::Const(std::string str)
193 {
194 flags = RTLIL::CONST_FLAG_STRING;
195 for (int i = str.size()-1; i >= 0; i--) {
196 unsigned char ch = str[i];
197 for (int j = 0; j < 8; j++) {
198 bits.push_back((ch & 1) != 0 ? State::S1 : State::S0);
199 ch = ch >> 1;
200 }
201 }
202 }
203
204 RTLIL::Const::Const(int val, int width)
205 {
206 flags = RTLIL::CONST_FLAG_NONE;
207 for (int i = 0; i < width; i++) {
208 bits.push_back((val & 1) != 0 ? State::S1 : State::S0);
209 val = val >> 1;
210 }
211 }
212
213 RTLIL::Const::Const(RTLIL::State bit, int width)
214 {
215 flags = RTLIL::CONST_FLAG_NONE;
216 for (int i = 0; i < width; i++)
217 bits.push_back(bit);
218 }
219
220 RTLIL::Const::Const(const std::vector<bool> &bits)
221 {
222 flags = RTLIL::CONST_FLAG_NONE;
223 for (const auto &b : bits)
224 this->bits.emplace_back(b ? State::S1 : State::S0);
225 }
226
227 RTLIL::Const::Const(const RTLIL::Const &c)
228 {
229 flags = c.flags;
230 for (const auto &b : c.bits)
231 this->bits.push_back(b);
232 }
233
234 bool RTLIL::Const::operator <(const RTLIL::Const &other) const
235 {
236 if (bits.size() != other.bits.size())
237 return bits.size() < other.bits.size();
238 for (size_t i = 0; i < bits.size(); i++)
239 if (bits[i] != other.bits[i])
240 return bits[i] < other.bits[i];
241 return false;
242 }
243
244 bool RTLIL::Const::operator ==(const RTLIL::Const &other) const
245 {
246 return bits == other.bits;
247 }
248
249 bool RTLIL::Const::operator !=(const RTLIL::Const &other) const
250 {
251 return bits != other.bits;
252 }
253
254 bool RTLIL::Const::as_bool() const
255 {
256 for (size_t i = 0; i < bits.size(); i++)
257 if (bits[i] == State::S1)
258 return true;
259 return false;
260 }
261
262 int RTLIL::Const::as_int(bool is_signed) const
263 {
264 int32_t ret = 0;
265 for (size_t i = 0; i < bits.size() && i < 32; i++)
266 if (bits[i] == State::S1)
267 ret |= 1 << i;
268 if (is_signed && bits.back() == State::S1)
269 for (size_t i = bits.size(); i < 32; i++)
270 ret |= 1 << i;
271 return ret;
272 }
273
274 std::string RTLIL::Const::as_string() const
275 {
276 std::string ret;
277 ret.reserve(bits.size());
278 for (size_t i = bits.size(); i > 0; i--)
279 switch (bits[i-1]) {
280 case S0: ret += "0"; break;
281 case S1: ret += "1"; break;
282 case Sx: ret += "x"; break;
283 case Sz: ret += "z"; break;
284 case Sa: ret += "-"; break;
285 case Sm: ret += "m"; break;
286 }
287 return ret;
288 }
289
290 RTLIL::Const RTLIL::Const::from_string(const std::string &str)
291 {
292 Const c;
293 c.bits.reserve(str.size());
294 for (auto it = str.rbegin(); it != str.rend(); it++)
295 switch (*it) {
296 case '0': c.bits.push_back(State::S0); break;
297 case '1': c.bits.push_back(State::S1); break;
298 case 'x': c.bits.push_back(State::Sx); break;
299 case 'z': c.bits.push_back(State::Sz); break;
300 case 'm': c.bits.push_back(State::Sm); break;
301 default: c.bits.push_back(State::Sa);
302 }
303 return c;
304 }
305
306 std::string RTLIL::Const::decode_string() const
307 {
308 std::string string;
309 string.reserve(GetSize(bits)/8);
310 for (int i = 0; i < GetSize(bits); i += 8) {
311 char ch = 0;
312 for (int j = 0; j < 8 && i + j < int (bits.size()); j++)
313 if (bits[i + j] == RTLIL::State::S1)
314 ch |= 1 << j;
315 if (ch != 0)
316 string.append({ch});
317 }
318 std::reverse(string.begin(), string.end());
319 return string;
320 }
321
322 bool RTLIL::Const::is_fully_zero() const
323 {
324 cover("kernel.rtlil.const.is_fully_zero");
325
326 for (const auto &bit : bits)
327 if (bit != RTLIL::State::S0)
328 return false;
329
330 return true;
331 }
332
333 bool RTLIL::Const::is_fully_ones() const
334 {
335 cover("kernel.rtlil.const.is_fully_ones");
336
337 for (const auto &bit : bits)
338 if (bit != RTLIL::State::S1)
339 return false;
340
341 return true;
342 }
343
344 bool RTLIL::Const::is_fully_def() const
345 {
346 cover("kernel.rtlil.const.is_fully_def");
347
348 for (const auto &bit : bits)
349 if (bit != RTLIL::State::S0 && bit != RTLIL::State::S1)
350 return false;
351
352 return true;
353 }
354
355 bool RTLIL::Const::is_fully_undef() const
356 {
357 cover("kernel.rtlil.const.is_fully_undef");
358
359 for (const auto &bit : bits)
360 if (bit != RTLIL::State::Sx && bit != RTLIL::State::Sz)
361 return false;
362
363 return true;
364 }
365
366 bool RTLIL::AttrObject::has_attribute(RTLIL::IdString id) const
367 {
368 return attributes.count(id);
369 }
370
371 void RTLIL::AttrObject::set_bool_attribute(RTLIL::IdString id, bool value)
372 {
373 if (value)
374 attributes[id] = RTLIL::Const(1);
375 else
376 attributes.erase(id);
377 }
378
379 bool RTLIL::AttrObject::get_bool_attribute(RTLIL::IdString id) const
380 {
381 const auto it = attributes.find(id);
382 if (it == attributes.end())
383 return false;
384 return it->second.as_bool();
385 }
386
387 void RTLIL::AttrObject::set_string_attribute(RTLIL::IdString id, string value)
388 {
389 if (value.empty())
390 attributes.erase(id);
391 else
392 attributes[id] = value;
393 }
394
395 string RTLIL::AttrObject::get_string_attribute(RTLIL::IdString id) const
396 {
397 std::string value;
398 const auto it = attributes.find(id);
399 if (it != attributes.end())
400 value = it->second.decode_string();
401 return value;
402 }
403
404 void RTLIL::AttrObject::set_strpool_attribute(RTLIL::IdString id, const pool<string> &data)
405 {
406 string attrval;
407 for (const auto &s : data) {
408 if (!attrval.empty())
409 attrval += "|";
410 attrval += s;
411 }
412 set_string_attribute(id, attrval);
413 }
414
415 void RTLIL::AttrObject::add_strpool_attribute(RTLIL::IdString id, const pool<string> &data)
416 {
417 pool<string> union_data = get_strpool_attribute(id);
418 union_data.insert(data.begin(), data.end());
419 if (!union_data.empty())
420 set_strpool_attribute(id, union_data);
421 }
422
423 pool<string> RTLIL::AttrObject::get_strpool_attribute(RTLIL::IdString id) const
424 {
425 pool<string> data;
426 if (attributes.count(id) != 0)
427 for (auto s : split_tokens(get_string_attribute(id), "|"))
428 data.insert(s);
429 return data;
430 }
431
432 void RTLIL::AttrObject::set_hdlname_attribute(const vector<string> &hierarchy)
433 {
434 string attrval;
435 for (const auto &ident : hierarchy) {
436 if (!attrval.empty())
437 attrval += " ";
438 attrval += ident;
439 }
440 set_string_attribute(ID::hdlname, attrval);
441 }
442
443 vector<string> RTLIL::AttrObject::get_hdlname_attribute() const
444 {
445 return split_tokens(get_string_attribute(ID::hdlname), " ");
446 }
447
448 bool RTLIL::Selection::selected_module(RTLIL::IdString mod_name) const
449 {
450 if (full_selection)
451 return true;
452 if (selected_modules.count(mod_name) > 0)
453 return true;
454 if (selected_members.count(mod_name) > 0)
455 return true;
456 return false;
457 }
458
459 bool RTLIL::Selection::selected_whole_module(RTLIL::IdString mod_name) const
460 {
461 if (full_selection)
462 return true;
463 if (selected_modules.count(mod_name) > 0)
464 return true;
465 return false;
466 }
467
468 bool RTLIL::Selection::selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const
469 {
470 if (full_selection)
471 return true;
472 if (selected_modules.count(mod_name) > 0)
473 return true;
474 if (selected_members.count(mod_name) > 0)
475 if (selected_members.at(mod_name).count(memb_name) > 0)
476 return true;
477 return false;
478 }
479
480 void RTLIL::Selection::optimize(RTLIL::Design *design)
481 {
482 if (full_selection) {
483 selected_modules.clear();
484 selected_members.clear();
485 return;
486 }
487
488 std::vector<RTLIL::IdString> del_list, add_list;
489
490 del_list.clear();
491 for (auto mod_name : selected_modules) {
492 if (design->modules_.count(mod_name) == 0)
493 del_list.push_back(mod_name);
494 selected_members.erase(mod_name);
495 }
496 for (auto mod_name : del_list)
497 selected_modules.erase(mod_name);
498
499 del_list.clear();
500 for (auto &it : selected_members)
501 if (design->modules_.count(it.first) == 0)
502 del_list.push_back(it.first);
503 for (auto mod_name : del_list)
504 selected_members.erase(mod_name);
505
506 for (auto &it : selected_members) {
507 del_list.clear();
508 for (auto memb_name : it.second)
509 if (design->modules_[it.first]->count_id(memb_name) == 0)
510 del_list.push_back(memb_name);
511 for (auto memb_name : del_list)
512 it.second.erase(memb_name);
513 }
514
515 del_list.clear();
516 add_list.clear();
517 for (auto &it : selected_members)
518 if (it.second.size() == 0)
519 del_list.push_back(it.first);
520 else if (it.second.size() == design->modules_[it.first]->wires_.size() + design->modules_[it.first]->memories.size() +
521 design->modules_[it.first]->cells_.size() + design->modules_[it.first]->processes.size())
522 add_list.push_back(it.first);
523 for (auto mod_name : del_list)
524 selected_members.erase(mod_name);
525 for (auto mod_name : add_list) {
526 selected_members.erase(mod_name);
527 selected_modules.insert(mod_name);
528 }
529
530 if (selected_modules.size() == design->modules_.size()) {
531 full_selection = true;
532 selected_modules.clear();
533 selected_members.clear();
534 }
535 }
536
537 RTLIL::Design::Design()
538 : verilog_defines (new define_map_t)
539 {
540 static unsigned int hashidx_count = 123456789;
541 hashidx_count = mkhash_xorshift(hashidx_count);
542 hashidx_ = hashidx_count;
543
544 refcount_modules_ = 0;
545 selection_stack.push_back(RTLIL::Selection());
546
547 #ifdef WITH_PYTHON
548 RTLIL::Design::get_all_designs()->insert(std::pair<unsigned int, RTLIL::Design*>(hashidx_, this));
549 #endif
550 }
551
552 RTLIL::Design::~Design()
553 {
554 for (auto it = modules_.begin(); it != modules_.end(); ++it)
555 delete it->second;
556 for (auto n : verilog_packages)
557 delete n;
558 for (auto n : verilog_globals)
559 delete n;
560 #ifdef WITH_PYTHON
561 RTLIL::Design::get_all_designs()->erase(hashidx_);
562 #endif
563 }
564
565 #ifdef WITH_PYTHON
566 static std::map<unsigned int, RTLIL::Design*> all_designs;
567 std::map<unsigned int, RTLIL::Design*> *RTLIL::Design::get_all_designs(void)
568 {
569 return &all_designs;
570 }
571 #endif
572
573 RTLIL::ObjRange<RTLIL::Module*> RTLIL::Design::modules()
574 {
575 return RTLIL::ObjRange<RTLIL::Module*>(&modules_, &refcount_modules_);
576 }
577
578 RTLIL::Module *RTLIL::Design::module(RTLIL::IdString name)
579 {
580 return modules_.count(name) ? modules_.at(name) : NULL;
581 }
582
583 RTLIL::Module *RTLIL::Design::top_module()
584 {
585 RTLIL::Module *module = nullptr;
586 int module_count = 0;
587
588 for (auto mod : selected_modules()) {
589 if (mod->get_bool_attribute(ID::top))
590 return mod;
591 module_count++;
592 module = mod;
593 }
594
595 return module_count == 1 ? module : nullptr;
596 }
597
598 void RTLIL::Design::add(RTLIL::Module *module)
599 {
600 log_assert(modules_.count(module->name) == 0);
601 log_assert(refcount_modules_ == 0);
602 modules_[module->name] = module;
603 module->design = this;
604
605 for (auto mon : monitors)
606 mon->notify_module_add(module);
607
608 if (yosys_xtrace) {
609 log("#X# New Module: %s\n", log_id(module));
610 log_backtrace("-X- ", yosys_xtrace-1);
611 }
612 }
613
614 RTLIL::Module *RTLIL::Design::addModule(RTLIL::IdString name)
615 {
616 log_assert(modules_.count(name) == 0);
617 log_assert(refcount_modules_ == 0);
618
619 RTLIL::Module *module = new RTLIL::Module;
620 modules_[name] = module;
621 module->design = this;
622 module->name = name;
623
624 for (auto mon : monitors)
625 mon->notify_module_add(module);
626
627 if (yosys_xtrace) {
628 log("#X# New Module: %s\n", log_id(module));
629 log_backtrace("-X- ", yosys_xtrace-1);
630 }
631
632 return module;
633 }
634
635 void RTLIL::Design::scratchpad_unset(const std::string &varname)
636 {
637 scratchpad.erase(varname);
638 }
639
640 void RTLIL::Design::scratchpad_set_int(const std::string &varname, int value)
641 {
642 scratchpad[varname] = stringf("%d", value);
643 }
644
645 void RTLIL::Design::scratchpad_set_bool(const std::string &varname, bool value)
646 {
647 scratchpad[varname] = value ? "true" : "false";
648 }
649
650 void RTLIL::Design::scratchpad_set_string(const std::string &varname, std::string value)
651 {
652 scratchpad[varname] = std::move(value);
653 }
654
655 int RTLIL::Design::scratchpad_get_int(const std::string &varname, int default_value) const
656 {
657 auto it = scratchpad.find(varname);
658 if (it == scratchpad.end())
659 return default_value;
660
661 const std::string &str = it->second;
662
663 if (str == "0" || str == "false")
664 return 0;
665
666 if (str == "1" || str == "true")
667 return 1;
668
669 char *endptr = nullptr;
670 long int parsed_value = strtol(str.c_str(), &endptr, 10);
671 return *endptr ? default_value : parsed_value;
672 }
673
674 bool RTLIL::Design::scratchpad_get_bool(const std::string &varname, bool default_value) const
675 {
676 auto it = scratchpad.find(varname);
677 if (it == scratchpad.end())
678 return default_value;
679
680 const std::string &str = it->second;
681
682 if (str == "0" || str == "false")
683 return false;
684
685 if (str == "1" || str == "true")
686 return true;
687
688 return default_value;
689 }
690
691 std::string RTLIL::Design::scratchpad_get_string(const std::string &varname, const std::string &default_value) const
692 {
693 auto it = scratchpad.find(varname);
694 if (it == scratchpad.end())
695 return default_value;
696
697 return it->second;
698 }
699
700 void RTLIL::Design::remove(RTLIL::Module *module)
701 {
702 for (auto mon : monitors)
703 mon->notify_module_del(module);
704
705 if (yosys_xtrace) {
706 log("#X# Remove Module: %s\n", log_id(module));
707 log_backtrace("-X- ", yosys_xtrace-1);
708 }
709
710 log_assert(modules_.at(module->name) == module);
711 log_assert(refcount_modules_ == 0);
712 modules_.erase(module->name);
713 delete module;
714 }
715
716 void RTLIL::Design::rename(RTLIL::Module *module, RTLIL::IdString new_name)
717 {
718 modules_.erase(module->name);
719 module->name = new_name;
720 add(module);
721 }
722
723 void RTLIL::Design::sort()
724 {
725 scratchpad.sort();
726 modules_.sort(sort_by_id_str());
727 for (auto &it : modules_)
728 it.second->sort();
729 }
730
731 void RTLIL::Design::check()
732 {
733 #ifndef NDEBUG
734 for (auto &it : modules_) {
735 log_assert(this == it.second->design);
736 log_assert(it.first == it.second->name);
737 log_assert(!it.first.empty());
738 it.second->check();
739 }
740 #endif
741 }
742
743 void RTLIL::Design::optimize()
744 {
745 for (auto &it : modules_)
746 it.second->optimize();
747 for (auto &it : selection_stack)
748 it.optimize(this);
749 for (auto &it : selection_vars)
750 it.second.optimize(this);
751 }
752
753 bool RTLIL::Design::selected_module(RTLIL::IdString mod_name) const
754 {
755 if (!selected_active_module.empty() && mod_name != selected_active_module)
756 return false;
757 if (selection_stack.size() == 0)
758 return true;
759 return selection_stack.back().selected_module(mod_name);
760 }
761
762 bool RTLIL::Design::selected_whole_module(RTLIL::IdString mod_name) const
763 {
764 if (!selected_active_module.empty() && mod_name != selected_active_module)
765 return false;
766 if (selection_stack.size() == 0)
767 return true;
768 return selection_stack.back().selected_whole_module(mod_name);
769 }
770
771 bool RTLIL::Design::selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const
772 {
773 if (!selected_active_module.empty() && mod_name != selected_active_module)
774 return false;
775 if (selection_stack.size() == 0)
776 return true;
777 return selection_stack.back().selected_member(mod_name, memb_name);
778 }
779
780 bool RTLIL::Design::selected_module(RTLIL::Module *mod) const
781 {
782 return selected_module(mod->name);
783 }
784
785 bool RTLIL::Design::selected_whole_module(RTLIL::Module *mod) const
786 {
787 return selected_whole_module(mod->name);
788 }
789
790 std::vector<RTLIL::Module*> RTLIL::Design::selected_modules() const
791 {
792 std::vector<RTLIL::Module*> result;
793 result.reserve(modules_.size());
794 for (auto &it : modules_)
795 if (selected_module(it.first) && !it.second->get_blackbox_attribute())
796 result.push_back(it.second);
797 return result;
798 }
799
800 std::vector<RTLIL::Module*> RTLIL::Design::selected_whole_modules() const
801 {
802 std::vector<RTLIL::Module*> result;
803 result.reserve(modules_.size());
804 for (auto &it : modules_)
805 if (selected_whole_module(it.first) && !it.second->get_blackbox_attribute())
806 result.push_back(it.second);
807 return result;
808 }
809
810 std::vector<RTLIL::Module*> RTLIL::Design::selected_whole_modules_warn() const
811 {
812 std::vector<RTLIL::Module*> result;
813 result.reserve(modules_.size());
814 for (auto &it : modules_)
815 if (it.second->get_blackbox_attribute())
816 continue;
817 else if (selected_whole_module(it.first))
818 result.push_back(it.second);
819 else if (selected_module(it.first))
820 log_warning("Ignoring partially selected module %s.\n", log_id(it.first));
821 return result;
822 }
823
824 RTLIL::Module::Module()
825 {
826 static unsigned int hashidx_count = 123456789;
827 hashidx_count = mkhash_xorshift(hashidx_count);
828 hashidx_ = hashidx_count;
829
830 design = nullptr;
831 refcount_wires_ = 0;
832 refcount_cells_ = 0;
833
834 #ifdef WITH_PYTHON
835 RTLIL::Module::get_all_modules()->insert(std::pair<unsigned int, RTLIL::Module*>(hashidx_, this));
836 #endif
837 }
838
839 RTLIL::Module::~Module()
840 {
841 for (auto it = wires_.begin(); it != wires_.end(); ++it)
842 delete it->second;
843 for (auto it = memories.begin(); it != memories.end(); ++it)
844 delete it->second;
845 for (auto it = cells_.begin(); it != cells_.end(); ++it)
846 delete it->second;
847 for (auto it = processes.begin(); it != processes.end(); ++it)
848 delete it->second;
849 #ifdef WITH_PYTHON
850 RTLIL::Module::get_all_modules()->erase(hashidx_);
851 #endif
852 }
853
854 #ifdef WITH_PYTHON
855 static std::map<unsigned int, RTLIL::Module*> all_modules;
856 std::map<unsigned int, RTLIL::Module*> *RTLIL::Module::get_all_modules(void)
857 {
858 return &all_modules;
859 }
860 #endif
861
862 void RTLIL::Module::makeblackbox()
863 {
864 pool<RTLIL::Wire*> delwires;
865
866 for (auto it = wires_.begin(); it != wires_.end(); ++it)
867 if (!it->second->port_input && !it->second->port_output)
868 delwires.insert(it->second);
869
870 for (auto it = memories.begin(); it != memories.end(); ++it)
871 delete it->second;
872 memories.clear();
873
874 for (auto it = cells_.begin(); it != cells_.end(); ++it)
875 delete it->second;
876 cells_.clear();
877
878 for (auto it = processes.begin(); it != processes.end(); ++it)
879 delete it->second;
880 processes.clear();
881
882 connections_.clear();
883
884 remove(delwires);
885 set_bool_attribute(ID::blackbox);
886 }
887
888 void RTLIL::Module::reprocess_module(RTLIL::Design *, const dict<RTLIL::IdString, RTLIL::Module *> &)
889 {
890 log_error("Cannot reprocess_module module `%s' !\n", id2cstr(name));
891 }
892
893 RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, const dict<RTLIL::IdString, RTLIL::Const> &, bool mayfail)
894 {
895 if (mayfail)
896 return RTLIL::IdString();
897 log_error("Module `%s' is used with parameters but is not parametric!\n", id2cstr(name));
898 }
899
900
901 RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, const dict<RTLIL::IdString, RTLIL::Const> &, const dict<RTLIL::IdString, RTLIL::Module*> &, const dict<RTLIL::IdString, RTLIL::IdString> &, bool mayfail)
902 {
903 if (mayfail)
904 return RTLIL::IdString();
905 log_error("Module `%s' is used with parameters but is not parametric!\n", id2cstr(name));
906 }
907
908 size_t RTLIL::Module::count_id(RTLIL::IdString id)
909 {
910 return wires_.count(id) + memories.count(id) + cells_.count(id) + processes.count(id);
911 }
912
913 #ifndef NDEBUG
914 namespace {
915 struct InternalCellChecker
916 {
917 RTLIL::Module *module;
918 RTLIL::Cell *cell;
919 pool<RTLIL::IdString> expected_params, expected_ports;
920
921 InternalCellChecker(RTLIL::Module *module, RTLIL::Cell *cell) : module(module), cell(cell) { }
922
923 void error(int linenr)
924 {
925 std::stringstream buf;
926 ILANG_BACKEND::dump_cell(buf, " ", cell);
927
928 log_error("Found error in internal cell %s%s%s (%s) at %s:%d:\n%s",
929 module ? module->name.c_str() : "", module ? "." : "",
930 cell->name.c_str(), cell->type.c_str(), __FILE__, linenr, buf.str().c_str());
931 }
932
933 int param(RTLIL::IdString name)
934 {
935 auto it = cell->parameters.find(name);
936 if (it == cell->parameters.end())
937 error(__LINE__);
938 expected_params.insert(name);
939 return it->second.as_int();
940 }
941
942 int param_bool(RTLIL::IdString name)
943 {
944 int v = param(name);
945 if (GetSize(cell->parameters.at(name)) > 32)
946 error(__LINE__);
947 if (v != 0 && v != 1)
948 error(__LINE__);
949 return v;
950 }
951
952 int param_bool(RTLIL::IdString name, bool expected)
953 {
954 int v = param_bool(name);
955 if (v != expected)
956 error(__LINE__);
957 return v;
958 }
959
960 void param_bits(RTLIL::IdString name, int width)
961 {
962 param(name);
963 if (GetSize(cell->parameters.at(name).bits) != width)
964 error(__LINE__);
965 }
966
967 void port(RTLIL::IdString name, int width)
968 {
969 auto it = cell->connections_.find(name);
970 if (it == cell->connections_.end())
971 error(__LINE__);
972 if (GetSize(it->second) != width)
973 error(__LINE__);
974 expected_ports.insert(name);
975 }
976
977 void check_expected(bool check_matched_sign = false)
978 {
979 for (auto &para : cell->parameters)
980 if (expected_params.count(para.first) == 0)
981 error(__LINE__);
982 for (auto &conn : cell->connections())
983 if (expected_ports.count(conn.first) == 0)
984 error(__LINE__);
985
986 if (check_matched_sign) {
987 log_assert(expected_params.count(ID::A_SIGNED) != 0 && expected_params.count(ID::B_SIGNED) != 0);
988 bool a_is_signed = cell->parameters.at(ID::A_SIGNED).as_bool();
989 bool b_is_signed = cell->parameters.at(ID::B_SIGNED).as_bool();
990 if (a_is_signed != b_is_signed)
991 error(__LINE__);
992 }
993 }
994
995 void check()
996 {
997 if (!cell->type.begins_with("$") || cell->type.begins_with("$__") || cell->type.begins_with("$paramod") || cell->type.begins_with("$fmcombine") ||
998 cell->type.begins_with("$verific$") || cell->type.begins_with("$array:") || cell->type.begins_with("$extern:"))
999 return;
1000
1001 if (cell->type.in(ID($not), ID($pos), ID($neg))) {
1002 param_bool(ID::A_SIGNED);
1003 port(ID::A, param(ID::A_WIDTH));
1004 port(ID::Y, param(ID::Y_WIDTH));
1005 check_expected();
1006 return;
1007 }
1008
1009 if (cell->type.in(ID($and), ID($or), ID($xor), ID($xnor))) {
1010 param_bool(ID::A_SIGNED);
1011 param_bool(ID::B_SIGNED);
1012 port(ID::A, param(ID::A_WIDTH));
1013 port(ID::B, param(ID::B_WIDTH));
1014 port(ID::Y, param(ID::Y_WIDTH));
1015 check_expected(true);
1016 return;
1017 }
1018
1019 if (cell->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor), ID($reduce_bool))) {
1020 param_bool(ID::A_SIGNED);
1021 port(ID::A, param(ID::A_WIDTH));
1022 port(ID::Y, param(ID::Y_WIDTH));
1023 check_expected();
1024 return;
1025 }
1026
1027 if (cell->type.in(ID($shl), ID($shr), ID($sshl), ID($sshr))) {
1028 param_bool(ID::A_SIGNED);
1029 param_bool(ID::B_SIGNED, /*expected=*/false);
1030 port(ID::A, param(ID::A_WIDTH));
1031 port(ID::B, param(ID::B_WIDTH));
1032 port(ID::Y, param(ID::Y_WIDTH));
1033 check_expected(/*check_matched_sign=*/false);
1034 return;
1035 }
1036
1037 if (cell->type.in(ID($shift), ID($shiftx))) {
1038 param_bool(ID::A_SIGNED);
1039 param_bool(ID::B_SIGNED);
1040 port(ID::A, param(ID::A_WIDTH));
1041 port(ID::B, param(ID::B_WIDTH));
1042 port(ID::Y, param(ID::Y_WIDTH));
1043 check_expected(/*check_matched_sign=*/false);
1044 return;
1045 }
1046
1047 if (cell->type.in(ID($lt), ID($le), ID($eq), ID($ne), ID($eqx), ID($nex), ID($ge), ID($gt))) {
1048 param_bool(ID::A_SIGNED);
1049 param_bool(ID::B_SIGNED);
1050 port(ID::A, param(ID::A_WIDTH));
1051 port(ID::B, param(ID::B_WIDTH));
1052 port(ID::Y, param(ID::Y_WIDTH));
1053 check_expected(true);
1054 return;
1055 }
1056
1057 if (cell->type.in(ID($add), ID($sub), ID($mul), ID($div), ID($mod), ID($divfloor), ID($modfloor), ID($pow))) {
1058 param_bool(ID::A_SIGNED);
1059 param_bool(ID::B_SIGNED);
1060 port(ID::A, param(ID::A_WIDTH));
1061 port(ID::B, param(ID::B_WIDTH));
1062 port(ID::Y, param(ID::Y_WIDTH));
1063 check_expected(cell->type != ID($pow));
1064 return;
1065 }
1066
1067 if (cell->type == ID($fa)) {
1068 port(ID::A, param(ID::WIDTH));
1069 port(ID::B, param(ID::WIDTH));
1070 port(ID::C, param(ID::WIDTH));
1071 port(ID::X, param(ID::WIDTH));
1072 port(ID::Y, param(ID::WIDTH));
1073 check_expected();
1074 return;
1075 }
1076
1077 if (cell->type == ID($lcu)) {
1078 port(ID::P, param(ID::WIDTH));
1079 port(ID::G, param(ID::WIDTH));
1080 port(ID::CI, 1);
1081 port(ID::CO, param(ID::WIDTH));
1082 check_expected();
1083 return;
1084 }
1085
1086 if (cell->type == ID($alu)) {
1087 param_bool(ID::A_SIGNED);
1088 param_bool(ID::B_SIGNED);
1089 port(ID::A, param(ID::A_WIDTH));
1090 port(ID::B, param(ID::B_WIDTH));
1091 port(ID::CI, 1);
1092 port(ID::BI, 1);
1093 port(ID::X, param(ID::Y_WIDTH));
1094 port(ID::Y, param(ID::Y_WIDTH));
1095 port(ID::CO, param(ID::Y_WIDTH));
1096 check_expected(true);
1097 return;
1098 }
1099
1100 if (cell->type == ID($macc)) {
1101 param(ID::CONFIG);
1102 param(ID::CONFIG_WIDTH);
1103 port(ID::A, param(ID::A_WIDTH));
1104 port(ID::B, param(ID::B_WIDTH));
1105 port(ID::Y, param(ID::Y_WIDTH));
1106 check_expected();
1107 Macc().from_cell(cell);
1108 return;
1109 }
1110
1111 if (cell->type == ID($logic_not)) {
1112 param_bool(ID::A_SIGNED);
1113 port(ID::A, param(ID::A_WIDTH));
1114 port(ID::Y, param(ID::Y_WIDTH));
1115 check_expected();
1116 return;
1117 }
1118
1119 if (cell->type.in(ID($logic_and), ID($logic_or))) {
1120 param_bool(ID::A_SIGNED);
1121 param_bool(ID::B_SIGNED);
1122 port(ID::A, param(ID::A_WIDTH));
1123 port(ID::B, param(ID::B_WIDTH));
1124 port(ID::Y, param(ID::Y_WIDTH));
1125 check_expected(/*check_matched_sign=*/false);
1126 return;
1127 }
1128
1129 if (cell->type == ID($slice)) {
1130 param(ID::OFFSET);
1131 port(ID::A, param(ID::A_WIDTH));
1132 port(ID::Y, param(ID::Y_WIDTH));
1133 if (param(ID::OFFSET) + param(ID::Y_WIDTH) > param(ID::A_WIDTH))
1134 error(__LINE__);
1135 check_expected();
1136 return;
1137 }
1138
1139 if (cell->type == ID($concat)) {
1140 port(ID::A, param(ID::A_WIDTH));
1141 port(ID::B, param(ID::B_WIDTH));
1142 port(ID::Y, param(ID::A_WIDTH) + param(ID::B_WIDTH));
1143 check_expected();
1144 return;
1145 }
1146
1147 if (cell->type == ID($mux)) {
1148 port(ID::A, param(ID::WIDTH));
1149 port(ID::B, param(ID::WIDTH));
1150 port(ID::S, 1);
1151 port(ID::Y, param(ID::WIDTH));
1152 check_expected();
1153 return;
1154 }
1155
1156 if (cell->type == ID($pmux)) {
1157 port(ID::A, param(ID::WIDTH));
1158 port(ID::B, param(ID::WIDTH) * param(ID::S_WIDTH));
1159 port(ID::S, param(ID::S_WIDTH));
1160 port(ID::Y, param(ID::WIDTH));
1161 check_expected();
1162 return;
1163 }
1164
1165 if (cell->type == ID($lut)) {
1166 param(ID::LUT);
1167 port(ID::A, param(ID::WIDTH));
1168 port(ID::Y, 1);
1169 check_expected();
1170 return;
1171 }
1172
1173 if (cell->type == ID($sop)) {
1174 param(ID::DEPTH);
1175 param(ID::TABLE);
1176 port(ID::A, param(ID::WIDTH));
1177 port(ID::Y, 1);
1178 check_expected();
1179 return;
1180 }
1181
1182 if (cell->type == ID($sr)) {
1183 param_bool(ID::SET_POLARITY);
1184 param_bool(ID::CLR_POLARITY);
1185 port(ID::SET, param(ID::WIDTH));
1186 port(ID::CLR, param(ID::WIDTH));
1187 port(ID::Q, param(ID::WIDTH));
1188 check_expected();
1189 return;
1190 }
1191
1192 if (cell->type == ID($ff)) {
1193 port(ID::D, param(ID::WIDTH));
1194 port(ID::Q, param(ID::WIDTH));
1195 check_expected();
1196 return;
1197 }
1198
1199 if (cell->type == ID($dff)) {
1200 param_bool(ID::CLK_POLARITY);
1201 port(ID::CLK, 1);
1202 port(ID::D, param(ID::WIDTH));
1203 port(ID::Q, param(ID::WIDTH));
1204 check_expected();
1205 return;
1206 }
1207
1208 if (cell->type == ID($dffe)) {
1209 param_bool(ID::CLK_POLARITY);
1210 param_bool(ID::EN_POLARITY);
1211 port(ID::CLK, 1);
1212 port(ID::EN, 1);
1213 port(ID::D, param(ID::WIDTH));
1214 port(ID::Q, param(ID::WIDTH));
1215 check_expected();
1216 return;
1217 }
1218
1219 if (cell->type == ID($dffsr)) {
1220 param_bool(ID::CLK_POLARITY);
1221 param_bool(ID::SET_POLARITY);
1222 param_bool(ID::CLR_POLARITY);
1223 port(ID::CLK, 1);
1224 port(ID::SET, param(ID::WIDTH));
1225 port(ID::CLR, param(ID::WIDTH));
1226 port(ID::D, param(ID::WIDTH));
1227 port(ID::Q, param(ID::WIDTH));
1228 check_expected();
1229 return;
1230 }
1231
1232 if (cell->type == ID($dffsre)) {
1233 param_bool(ID::CLK_POLARITY);
1234 param_bool(ID::SET_POLARITY);
1235 param_bool(ID::CLR_POLARITY);
1236 param_bool(ID::EN_POLARITY);
1237 port(ID::CLK, 1);
1238 port(ID::EN, 1);
1239 port(ID::SET, param(ID::WIDTH));
1240 port(ID::CLR, param(ID::WIDTH));
1241 port(ID::D, param(ID::WIDTH));
1242 port(ID::Q, param(ID::WIDTH));
1243 check_expected();
1244 return;
1245 }
1246
1247 if (cell->type == ID($adff)) {
1248 param_bool(ID::CLK_POLARITY);
1249 param_bool(ID::ARST_POLARITY);
1250 param_bits(ID::ARST_VALUE, param(ID::WIDTH));
1251 port(ID::CLK, 1);
1252 port(ID::ARST, 1);
1253 port(ID::D, param(ID::WIDTH));
1254 port(ID::Q, param(ID::WIDTH));
1255 check_expected();
1256 return;
1257 }
1258
1259 if (cell->type == ID($sdff)) {
1260 param_bool(ID::CLK_POLARITY);
1261 param_bool(ID::SRST_POLARITY);
1262 param_bits(ID::SRST_VALUE, param(ID::WIDTH));
1263 port(ID::CLK, 1);
1264 port(ID::SRST, 1);
1265 port(ID::D, param(ID::WIDTH));
1266 port(ID::Q, param(ID::WIDTH));
1267 check_expected();
1268 return;
1269 }
1270
1271 if (cell->type.in(ID($sdffe), ID($sdffce))) {
1272 param_bool(ID::CLK_POLARITY);
1273 param_bool(ID::EN_POLARITY);
1274 param_bool(ID::SRST_POLARITY);
1275 param_bits(ID::SRST_VALUE, param(ID::WIDTH));
1276 port(ID::CLK, 1);
1277 port(ID::EN, 1);
1278 port(ID::SRST, 1);
1279 port(ID::D, param(ID::WIDTH));
1280 port(ID::Q, param(ID::WIDTH));
1281 check_expected();
1282 return;
1283 }
1284
1285 if (cell->type == ID($adffe)) {
1286 param_bool(ID::CLK_POLARITY);
1287 param_bool(ID::EN_POLARITY);
1288 param_bool(ID::ARST_POLARITY);
1289 param_bits(ID::ARST_VALUE, param(ID::WIDTH));
1290 port(ID::CLK, 1);
1291 port(ID::EN, 1);
1292 port(ID::ARST, 1);
1293 port(ID::D, param(ID::WIDTH));
1294 port(ID::Q, param(ID::WIDTH));
1295 check_expected();
1296 return;
1297 }
1298
1299 if (cell->type == ID($dlatch)) {
1300 param_bool(ID::EN_POLARITY);
1301 port(ID::EN, 1);
1302 port(ID::D, param(ID::WIDTH));
1303 port(ID::Q, param(ID::WIDTH));
1304 check_expected();
1305 return;
1306 }
1307
1308 if (cell->type == ID($adlatch)) {
1309 param_bool(ID::EN_POLARITY);
1310 param_bool(ID::ARST_POLARITY);
1311 param_bits(ID::ARST_VALUE, param(ID::WIDTH));
1312 port(ID::EN, 1);
1313 port(ID::ARST, 1);
1314 port(ID::D, param(ID::WIDTH));
1315 port(ID::Q, param(ID::WIDTH));
1316 check_expected();
1317 return;
1318 }
1319
1320 if (cell->type == ID($dlatchsr)) {
1321 param_bool(ID::EN_POLARITY);
1322 param_bool(ID::SET_POLARITY);
1323 param_bool(ID::CLR_POLARITY);
1324 port(ID::EN, 1);
1325 port(ID::SET, param(ID::WIDTH));
1326 port(ID::CLR, param(ID::WIDTH));
1327 port(ID::D, param(ID::WIDTH));
1328 port(ID::Q, param(ID::WIDTH));
1329 check_expected();
1330 return;
1331 }
1332
1333 if (cell->type == ID($fsm)) {
1334 param(ID::NAME);
1335 param_bool(ID::CLK_POLARITY);
1336 param_bool(ID::ARST_POLARITY);
1337 param(ID::STATE_BITS);
1338 param(ID::STATE_NUM);
1339 param(ID::STATE_NUM_LOG2);
1340 param(ID::STATE_RST);
1341 param_bits(ID::STATE_TABLE, param(ID::STATE_BITS) * param(ID::STATE_NUM));
1342 param(ID::TRANS_NUM);
1343 param_bits(ID::TRANS_TABLE, param(ID::TRANS_NUM) * (2*param(ID::STATE_NUM_LOG2) + param(ID::CTRL_IN_WIDTH) + param(ID::CTRL_OUT_WIDTH)));
1344 port(ID::CLK, 1);
1345 port(ID::ARST, 1);
1346 port(ID::CTRL_IN, param(ID::CTRL_IN_WIDTH));
1347 port(ID::CTRL_OUT, param(ID::CTRL_OUT_WIDTH));
1348 check_expected();
1349 return;
1350 }
1351
1352 if (cell->type == ID($memrd)) {
1353 param(ID::MEMID);
1354 param_bool(ID::CLK_ENABLE);
1355 param_bool(ID::CLK_POLARITY);
1356 param_bool(ID::TRANSPARENT);
1357 port(ID::CLK, 1);
1358 port(ID::EN, 1);
1359 port(ID::ADDR, param(ID::ABITS));
1360 port(ID::DATA, param(ID::WIDTH));
1361 check_expected();
1362 return;
1363 }
1364
1365 if (cell->type == ID($memwr)) {
1366 param(ID::MEMID);
1367 param_bool(ID::CLK_ENABLE);
1368 param_bool(ID::CLK_POLARITY);
1369 param(ID::PRIORITY);
1370 port(ID::CLK, 1);
1371 port(ID::EN, param(ID::WIDTH));
1372 port(ID::ADDR, param(ID::ABITS));
1373 port(ID::DATA, param(ID::WIDTH));
1374 check_expected();
1375 return;
1376 }
1377
1378 if (cell->type == ID($meminit)) {
1379 param(ID::MEMID);
1380 param(ID::PRIORITY);
1381 port(ID::ADDR, param(ID::ABITS));
1382 port(ID::DATA, param(ID::WIDTH) * param(ID::WORDS));
1383 check_expected();
1384 return;
1385 }
1386
1387 if (cell->type == ID($mem)) {
1388 param(ID::MEMID);
1389 param(ID::SIZE);
1390 param(ID::OFFSET);
1391 param(ID::INIT);
1392 param_bits(ID::RD_CLK_ENABLE, max(1, param(ID::RD_PORTS)));
1393 param_bits(ID::RD_CLK_POLARITY, max(1, param(ID::RD_PORTS)));
1394 param_bits(ID::RD_TRANSPARENT, max(1, param(ID::RD_PORTS)));
1395 param_bits(ID::WR_CLK_ENABLE, max(1, param(ID::WR_PORTS)));
1396 param_bits(ID::WR_CLK_POLARITY, max(1, param(ID::WR_PORTS)));
1397 port(ID::RD_CLK, param(ID::RD_PORTS));
1398 port(ID::RD_EN, param(ID::RD_PORTS));
1399 port(ID::RD_ADDR, param(ID::RD_PORTS) * param(ID::ABITS));
1400 port(ID::RD_DATA, param(ID::RD_PORTS) * param(ID::WIDTH));
1401 port(ID::WR_CLK, param(ID::WR_PORTS));
1402 port(ID::WR_EN, param(ID::WR_PORTS) * param(ID::WIDTH));
1403 port(ID::WR_ADDR, param(ID::WR_PORTS) * param(ID::ABITS));
1404 port(ID::WR_DATA, param(ID::WR_PORTS) * param(ID::WIDTH));
1405 check_expected();
1406 return;
1407 }
1408
1409 if (cell->type == ID($tribuf)) {
1410 port(ID::A, param(ID::WIDTH));
1411 port(ID::Y, param(ID::WIDTH));
1412 port(ID::EN, 1);
1413 check_expected();
1414 return;
1415 }
1416
1417 if (cell->type.in(ID($assert), ID($assume), ID($live), ID($fair), ID($cover))) {
1418 port(ID::A, 1);
1419 port(ID::EN, 1);
1420 check_expected();
1421 return;
1422 }
1423
1424 if (cell->type == ID($initstate)) {
1425 port(ID::Y, 1);
1426 check_expected();
1427 return;
1428 }
1429
1430 if (cell->type.in(ID($anyconst), ID($anyseq), ID($allconst), ID($allseq))) {
1431 port(ID::Y, param(ID::WIDTH));
1432 check_expected();
1433 return;
1434 }
1435
1436 if (cell->type == ID($equiv)) {
1437 port(ID::A, 1);
1438 port(ID::B, 1);
1439 port(ID::Y, 1);
1440 check_expected();
1441 return;
1442 }
1443
1444 if (cell->type.in(ID($specify2), ID($specify3))) {
1445 param_bool(ID::FULL);
1446 param_bool(ID::SRC_DST_PEN);
1447 param_bool(ID::SRC_DST_POL);
1448 param(ID::T_RISE_MIN);
1449 param(ID::T_RISE_TYP);
1450 param(ID::T_RISE_MAX);
1451 param(ID::T_FALL_MIN);
1452 param(ID::T_FALL_TYP);
1453 param(ID::T_FALL_MAX);
1454 port(ID::EN, 1);
1455 port(ID::SRC, param(ID::SRC_WIDTH));
1456 port(ID::DST, param(ID::DST_WIDTH));
1457 if (cell->type == ID($specify3)) {
1458 param_bool(ID::EDGE_EN);
1459 param_bool(ID::EDGE_POL);
1460 param_bool(ID::DAT_DST_PEN);
1461 param_bool(ID::DAT_DST_POL);
1462 port(ID::DAT, param(ID::DST_WIDTH));
1463 }
1464 check_expected();
1465 return;
1466 }
1467
1468 if (cell->type == ID($specrule)) {
1469 param(ID::TYPE);
1470 param_bool(ID::SRC_PEN);
1471 param_bool(ID::SRC_POL);
1472 param_bool(ID::DST_PEN);
1473 param_bool(ID::DST_POL);
1474 param(ID::T_LIMIT_MIN);
1475 param(ID::T_LIMIT_TYP);
1476 param(ID::T_LIMIT_MAX);
1477 param(ID::T_LIMIT2_MIN);
1478 param(ID::T_LIMIT2_TYP);
1479 param(ID::T_LIMIT2_MAX);
1480 port(ID::SRC_EN, 1);
1481 port(ID::DST_EN, 1);
1482 port(ID::SRC, param(ID::SRC_WIDTH));
1483 port(ID::DST, param(ID::DST_WIDTH));
1484 check_expected();
1485 return;
1486 }
1487
1488 if (cell->type == ID($_BUF_)) { port(ID::A,1); port(ID::Y,1); check_expected(); return; }
1489 if (cell->type == ID($_NOT_)) { port(ID::A,1); port(ID::Y,1); check_expected(); return; }
1490 if (cell->type == ID($_AND_)) { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; }
1491 if (cell->type == ID($_NAND_)) { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; }
1492 if (cell->type == ID($_OR_)) { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; }
1493 if (cell->type == ID($_NOR_)) { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; }
1494 if (cell->type == ID($_XOR_)) { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; }
1495 if (cell->type == ID($_XNOR_)) { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; }
1496 if (cell->type == ID($_ANDNOT_)) { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; }
1497 if (cell->type == ID($_ORNOT_)) { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; }
1498 if (cell->type == ID($_MUX_)) { port(ID::A,1); port(ID::B,1); port(ID::S,1); port(ID::Y,1); check_expected(); return; }
1499 if (cell->type == ID($_NMUX_)) { port(ID::A,1); port(ID::B,1); port(ID::S,1); port(ID::Y,1); check_expected(); return; }
1500 if (cell->type == ID($_AOI3_)) { port(ID::A,1); port(ID::B,1); port(ID::C,1); port(ID::Y,1); check_expected(); return; }
1501 if (cell->type == ID($_OAI3_)) { port(ID::A,1); port(ID::B,1); port(ID::C,1); port(ID::Y,1); check_expected(); return; }
1502 if (cell->type == ID($_AOI4_)) { port(ID::A,1); port(ID::B,1); port(ID::C,1); port(ID::D,1); port(ID::Y,1); check_expected(); return; }
1503 if (cell->type == ID($_OAI4_)) { port(ID::A,1); port(ID::B,1); port(ID::C,1); port(ID::D,1); port(ID::Y,1); check_expected(); return; }
1504
1505 if (cell->type == ID($_TBUF_)) { port(ID::A,1); port(ID::Y,1); port(ID::E,1); check_expected(); return; }
1506
1507 if (cell->type == ID($_MUX4_)) { port(ID::A,1); port(ID::B,1); port(ID::C,1); port(ID::D,1); port(ID::S,1); port(ID::T,1); port(ID::Y,1); check_expected(); return; }
1508 if (cell->type == ID($_MUX8_)) { port(ID::A,1); port(ID::B,1); port(ID::C,1); port(ID::D,1); port(ID::E,1); port(ID::F,1); port(ID::G,1); port(ID::H,1); port(ID::S,1); port(ID::T,1); port(ID::U,1); port(ID::Y,1); check_expected(); return; }
1509 if (cell->type == ID($_MUX16_)) { port(ID::A,1); port(ID::B,1); port(ID::C,1); port(ID::D,1); port(ID::E,1); port(ID::F,1); port(ID::G,1); port(ID::H,1); port(ID::I,1); port(ID::J,1); port(ID::K,1); port(ID::L,1); port(ID::M,1); port(ID::N,1); port(ID::O,1); port(ID::P,1); port(ID::S,1); port(ID::T,1); port(ID::U,1); port(ID::V,1); port(ID::Y,1); check_expected(); return; }
1510
1511 if (cell->type.in(ID($_SR_NN_), ID($_SR_NP_), ID($_SR_PN_), ID($_SR_PP_)))
1512 { port(ID::S,1); port(ID::R,1); port(ID::Q,1); check_expected(); return; }
1513
1514 if (cell->type == ID($_FF_)) { port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1515
1516 if (cell->type.in(ID($_DFF_N_), ID($_DFF_P_)))
1517 { port(ID::D,1); port(ID::Q,1); port(ID::C,1); check_expected(); return; }
1518
1519 if (cell->type.in(ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_)))
1520 { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::E,1); check_expected(); return; }
1521
1522 if (cell->type.in(
1523 ID($_DFF_NN0_), ID($_DFF_NN1_), ID($_DFF_NP0_), ID($_DFF_NP1_),
1524 ID($_DFF_PN0_), ID($_DFF_PN1_), ID($_DFF_PP0_), ID($_DFF_PP1_)))
1525 { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::R,1); check_expected(); return; }
1526
1527 if (cell->type.in(
1528 ID($_DFFE_NN0N_), ID($_DFFE_NN0P_), ID($_DFFE_NN1N_), ID($_DFFE_NN1P_),
1529 ID($_DFFE_NP0N_), ID($_DFFE_NP0P_), ID($_DFFE_NP1N_), ID($_DFFE_NP1P_),
1530 ID($_DFFE_PN0N_), ID($_DFFE_PN0P_), ID($_DFFE_PN1N_), ID($_DFFE_PN1P_),
1531 ID($_DFFE_PP0N_), ID($_DFFE_PP0P_), ID($_DFFE_PP1N_), ID($_DFFE_PP1P_)))
1532 { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::R,1); port(ID::E,1); check_expected(); return; }
1533
1534 if (cell->type.in(
1535 ID($_DFFSR_NNN_), ID($_DFFSR_NNP_), ID($_DFFSR_NPN_), ID($_DFFSR_NPP_),
1536 ID($_DFFSR_PNN_), ID($_DFFSR_PNP_), ID($_DFFSR_PPN_), ID($_DFFSR_PPP_)))
1537 { port(ID::C,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1538
1539 if (cell->type.in(
1540 ID($_DFFSRE_NNNN_), ID($_DFFSRE_NNNP_), ID($_DFFSRE_NNPN_), ID($_DFFSRE_NNPP_),
1541 ID($_DFFSRE_NPNN_), ID($_DFFSRE_NPNP_), ID($_DFFSRE_NPPN_), ID($_DFFSRE_NPPP_),
1542 ID($_DFFSRE_PNNN_), ID($_DFFSRE_PNNP_), ID($_DFFSRE_PNPN_), ID($_DFFSRE_PNPP_),
1543 ID($_DFFSRE_PPNN_), ID($_DFFSRE_PPNP_), ID($_DFFSRE_PPPN_), ID($_DFFSRE_PPPP_)))
1544 { port(ID::C,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::E,1); port(ID::Q,1); check_expected(); return; }
1545
1546 if (cell->type.in(
1547 ID($_SDFF_NN0_), ID($_SDFF_NN1_), ID($_SDFF_NP0_), ID($_SDFF_NP1_),
1548 ID($_SDFF_PN0_), ID($_SDFF_PN1_), ID($_SDFF_PP0_), ID($_SDFF_PP1_)))
1549 { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::R,1); check_expected(); return; }
1550
1551 if (cell->type.in(
1552 ID($_SDFFE_NN0N_), ID($_SDFFE_NN0P_), ID($_SDFFE_NN1N_), ID($_SDFFE_NN1P_),
1553 ID($_SDFFE_NP0N_), ID($_SDFFE_NP0P_), ID($_SDFFE_NP1N_), ID($_SDFFE_NP1P_),
1554 ID($_SDFFE_PN0N_), ID($_SDFFE_PN0P_), ID($_SDFFE_PN1N_), ID($_SDFFE_PN1P_),
1555 ID($_SDFFE_PP0N_), ID($_SDFFE_PP0P_), ID($_SDFFE_PP1N_), ID($_SDFFE_PP1P_),
1556 ID($_SDFFCE_NN0N_), ID($_SDFFCE_NN0P_), ID($_SDFFCE_NN1N_), ID($_SDFFCE_NN1P_),
1557 ID($_SDFFCE_NP0N_), ID($_SDFFCE_NP0P_), ID($_SDFFCE_NP1N_), ID($_SDFFCE_NP1P_),
1558 ID($_SDFFCE_PN0N_), ID($_SDFFCE_PN0P_), ID($_SDFFCE_PN1N_), ID($_SDFFCE_PN1P_),
1559 ID($_SDFFCE_PP0N_), ID($_SDFFCE_PP0P_), ID($_SDFFCE_PP1N_), ID($_SDFFCE_PP1P_)))
1560 { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::R,1); port(ID::E,1); check_expected(); return; }
1561
1562 if (cell->type.in(ID($_DLATCH_N_), ID($_DLATCH_P_)))
1563 { port(ID::E,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1564
1565 if (cell->type.in(
1566 ID($_DLATCH_NN0_), ID($_DLATCH_NN1_), ID($_DLATCH_NP0_), ID($_DLATCH_NP1_),
1567 ID($_DLATCH_PN0_), ID($_DLATCH_PN1_), ID($_DLATCH_PP0_), ID($_DLATCH_PP1_)))
1568 { port(ID::E,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1569
1570 if (cell->type.in(
1571 ID($_DLATCHSR_NNN_), ID($_DLATCHSR_NNP_), ID($_DLATCHSR_NPN_), ID($_DLATCHSR_NPP_),
1572 ID($_DLATCHSR_PNN_), ID($_DLATCHSR_PNP_), ID($_DLATCHSR_PPN_), ID($_DLATCHSR_PPP_)))
1573 { port(ID::E,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1574
1575 error(__LINE__);
1576 }
1577 };
1578 }
1579 #endif
1580
1581 void RTLIL::Module::sort()
1582 {
1583 wires_.sort(sort_by_id_str());
1584 cells_.sort(sort_by_id_str());
1585 parameter_default_values.sort(sort_by_id_str());
1586 memories.sort(sort_by_id_str());
1587 processes.sort(sort_by_id_str());
1588 for (auto &it : cells_)
1589 it.second->sort();
1590 for (auto &it : wires_)
1591 it.second->attributes.sort(sort_by_id_str());
1592 for (auto &it : memories)
1593 it.second->attributes.sort(sort_by_id_str());
1594 }
1595
1596 void RTLIL::Module::check()
1597 {
1598 #ifndef NDEBUG
1599 std::vector<bool> ports_declared;
1600 for (auto &it : wires_) {
1601 log_assert(this == it.second->module);
1602 log_assert(it.first == it.second->name);
1603 log_assert(!it.first.empty());
1604 log_assert(it.second->width >= 0);
1605 log_assert(it.second->port_id >= 0);
1606 for (auto &it2 : it.second->attributes)
1607 log_assert(!it2.first.empty());
1608 if (it.second->port_id) {
1609 log_assert(GetSize(ports) >= it.second->port_id);
1610 log_assert(ports.at(it.second->port_id-1) == it.first);
1611 log_assert(it.second->port_input || it.second->port_output);
1612 if (GetSize(ports_declared) < it.second->port_id)
1613 ports_declared.resize(it.second->port_id);
1614 log_assert(ports_declared[it.second->port_id-1] == false);
1615 ports_declared[it.second->port_id-1] = true;
1616 } else
1617 log_assert(!it.second->port_input && !it.second->port_output);
1618 }
1619 for (auto port_declared : ports_declared)
1620 log_assert(port_declared == true);
1621 log_assert(GetSize(ports) == GetSize(ports_declared));
1622
1623 for (auto &it : memories) {
1624 log_assert(it.first == it.second->name);
1625 log_assert(!it.first.empty());
1626 log_assert(it.second->width >= 0);
1627 log_assert(it.second->size >= 0);
1628 for (auto &it2 : it.second->attributes)
1629 log_assert(!it2.first.empty());
1630 }
1631
1632 for (auto &it : cells_) {
1633 log_assert(this == it.second->module);
1634 log_assert(it.first == it.second->name);
1635 log_assert(!it.first.empty());
1636 log_assert(!it.second->type.empty());
1637 for (auto &it2 : it.second->connections()) {
1638 log_assert(!it2.first.empty());
1639 it2.second.check();
1640 }
1641 for (auto &it2 : it.second->attributes)
1642 log_assert(!it2.first.empty());
1643 for (auto &it2 : it.second->parameters)
1644 log_assert(!it2.first.empty());
1645 InternalCellChecker checker(this, it.second);
1646 checker.check();
1647 }
1648
1649 for (auto &it : processes) {
1650 log_assert(it.first == it.second->name);
1651 log_assert(!it.first.empty());
1652 log_assert(it.second->root_case.compare.empty());
1653 std::vector<CaseRule*> all_cases = {&it.second->root_case};
1654 for (size_t i = 0; i < all_cases.size(); i++) {
1655 for (auto &switch_it : all_cases[i]->switches) {
1656 for (auto &case_it : switch_it->cases) {
1657 for (auto &compare_it : case_it->compare) {
1658 log_assert(switch_it->signal.size() == compare_it.size());
1659 }
1660 all_cases.push_back(case_it);
1661 }
1662 }
1663 }
1664 for (auto &sync_it : it.second->syncs) {
1665 switch (sync_it->type) {
1666 case SyncType::ST0:
1667 case SyncType::ST1:
1668 case SyncType::STp:
1669 case SyncType::STn:
1670 case SyncType::STe:
1671 log_assert(!sync_it->signal.empty());
1672 break;
1673 case SyncType::STa:
1674 case SyncType::STg:
1675 case SyncType::STi:
1676 log_assert(sync_it->signal.empty());
1677 break;
1678 }
1679 }
1680 }
1681
1682 for (auto &it : connections_) {
1683 log_assert(it.first.size() == it.second.size());
1684 log_assert(!it.first.has_const());
1685 it.first.check();
1686 it.second.check();
1687 }
1688
1689 for (auto &it : attributes)
1690 log_assert(!it.first.empty());
1691 #endif
1692 }
1693
1694 void RTLIL::Module::optimize()
1695 {
1696 }
1697
1698 void RTLIL::Module::cloneInto(RTLIL::Module *new_mod) const
1699 {
1700 log_assert(new_mod->refcount_wires_ == 0);
1701 log_assert(new_mod->refcount_cells_ == 0);
1702
1703 new_mod->avail_parameters = avail_parameters;
1704 new_mod->parameter_default_values = parameter_default_values;
1705
1706 for (auto &conn : connections_)
1707 new_mod->connect(conn);
1708
1709 for (auto &attr : attributes)
1710 new_mod->attributes[attr.first] = attr.second;
1711
1712 for (auto &it : wires_)
1713 new_mod->addWire(it.first, it.second);
1714
1715 for (auto &it : memories)
1716 new_mod->addMemory(it.first, it.second);
1717
1718 for (auto &it : cells_)
1719 new_mod->addCell(it.first, it.second);
1720
1721 for (auto &it : processes)
1722 new_mod->addProcess(it.first, it.second);
1723
1724 struct RewriteSigSpecWorker
1725 {
1726 RTLIL::Module *mod;
1727 void operator()(RTLIL::SigSpec &sig)
1728 {
1729 sig.pack();
1730 for (auto &c : sig.chunks_)
1731 if (c.wire != NULL)
1732 c.wire = mod->wires_.at(c.wire->name);
1733 }
1734 };
1735
1736 RewriteSigSpecWorker rewriteSigSpecWorker;
1737 rewriteSigSpecWorker.mod = new_mod;
1738 new_mod->rewrite_sigspecs(rewriteSigSpecWorker);
1739 new_mod->fixup_ports();
1740 }
1741
1742 RTLIL::Module *RTLIL::Module::clone() const
1743 {
1744 RTLIL::Module *new_mod = new RTLIL::Module;
1745 new_mod->name = name;
1746 cloneInto(new_mod);
1747 return new_mod;
1748 }
1749
1750 bool RTLIL::Module::has_memories() const
1751 {
1752 return !memories.empty();
1753 }
1754
1755 bool RTLIL::Module::has_processes() const
1756 {
1757 return !processes.empty();
1758 }
1759
1760 bool RTLIL::Module::has_memories_warn() const
1761 {
1762 if (!memories.empty())
1763 log_warning("Ignoring module %s because it contains memories (run 'memory' command first).\n", log_id(this));
1764 return !memories.empty();
1765 }
1766
1767 bool RTLIL::Module::has_processes_warn() const
1768 {
1769 if (!processes.empty())
1770 log_warning("Ignoring module %s because it contains processes (run 'proc' command first).\n", log_id(this));
1771 return !processes.empty();
1772 }
1773
1774 std::vector<RTLIL::Wire*> RTLIL::Module::selected_wires() const
1775 {
1776 std::vector<RTLIL::Wire*> result;
1777 result.reserve(wires_.size());
1778 for (auto &it : wires_)
1779 if (design->selected(this, it.second))
1780 result.push_back(it.second);
1781 return result;
1782 }
1783
1784 std::vector<RTLIL::Cell*> RTLIL::Module::selected_cells() const
1785 {
1786 std::vector<RTLIL::Cell*> result;
1787 result.reserve(cells_.size());
1788 for (auto &it : cells_)
1789 if (design->selected(this, it.second))
1790 result.push_back(it.second);
1791 return result;
1792 }
1793
1794 void RTLIL::Module::add(RTLIL::Wire *wire)
1795 {
1796 log_assert(!wire->name.empty());
1797 log_assert(count_id(wire->name) == 0);
1798 log_assert(refcount_wires_ == 0);
1799 wires_[wire->name] = wire;
1800 wire->module = this;
1801 }
1802
1803 void RTLIL::Module::add(RTLIL::Cell *cell)
1804 {
1805 log_assert(!cell->name.empty());
1806 log_assert(count_id(cell->name) == 0);
1807 log_assert(refcount_cells_ == 0);
1808 cells_[cell->name] = cell;
1809 cell->module = this;
1810 }
1811
1812 void RTLIL::Module::remove(const pool<RTLIL::Wire*> &wires)
1813 {
1814 log_assert(refcount_wires_ == 0);
1815
1816 struct DeleteWireWorker
1817 {
1818 RTLIL::Module *module;
1819 const pool<RTLIL::Wire*> *wires_p;
1820
1821 void operator()(RTLIL::SigSpec &sig) {
1822 sig.pack();
1823 for (auto &c : sig.chunks_)
1824 if (c.wire != NULL && wires_p->count(c.wire)) {
1825 c.wire = module->addWire(NEW_ID, c.width);
1826 c.offset = 0;
1827 }
1828 }
1829
1830 void operator()(RTLIL::SigSpec &lhs, RTLIL::SigSpec &rhs) {
1831 log_assert(GetSize(lhs) == GetSize(rhs));
1832 lhs.unpack();
1833 rhs.unpack();
1834 for (int i = 0; i < GetSize(lhs); i++) {
1835 RTLIL::SigBit &lhs_bit = lhs.bits_[i];
1836 RTLIL::SigBit &rhs_bit = rhs.bits_[i];
1837 if ((lhs_bit.wire != nullptr && wires_p->count(lhs_bit.wire)) || (rhs_bit.wire != nullptr && wires_p->count(rhs_bit.wire))) {
1838 lhs_bit = State::Sx;
1839 rhs_bit = State::Sx;
1840 }
1841 }
1842 }
1843 };
1844
1845 DeleteWireWorker delete_wire_worker;
1846 delete_wire_worker.module = this;
1847 delete_wire_worker.wires_p = &wires;
1848 rewrite_sigspecs2(delete_wire_worker);
1849
1850 for (auto &it : wires) {
1851 log_assert(wires_.count(it->name) != 0);
1852 wires_.erase(it->name);
1853 delete it;
1854 }
1855 }
1856
1857 void RTLIL::Module::remove(RTLIL::Cell *cell)
1858 {
1859 while (!cell->connections_.empty())
1860 cell->unsetPort(cell->connections_.begin()->first);
1861
1862 log_assert(cells_.count(cell->name) != 0);
1863 log_assert(refcount_cells_ == 0);
1864 cells_.erase(cell->name);
1865 delete cell;
1866 }
1867
1868 void RTLIL::Module::rename(RTLIL::Wire *wire, RTLIL::IdString new_name)
1869 {
1870 log_assert(wires_[wire->name] == wire);
1871 log_assert(refcount_wires_ == 0);
1872 wires_.erase(wire->name);
1873 wire->name = new_name;
1874 add(wire);
1875 }
1876
1877 void RTLIL::Module::rename(RTLIL::Cell *cell, RTLIL::IdString new_name)
1878 {
1879 log_assert(cells_[cell->name] == cell);
1880 log_assert(refcount_wires_ == 0);
1881 cells_.erase(cell->name);
1882 cell->name = new_name;
1883 add(cell);
1884 }
1885
1886 void RTLIL::Module::rename(RTLIL::IdString old_name, RTLIL::IdString new_name)
1887 {
1888 log_assert(count_id(old_name) != 0);
1889 if (wires_.count(old_name))
1890 rename(wires_.at(old_name), new_name);
1891 else if (cells_.count(old_name))
1892 rename(cells_.at(old_name), new_name);
1893 else
1894 log_abort();
1895 }
1896
1897 void RTLIL::Module::swap_names(RTLIL::Wire *w1, RTLIL::Wire *w2)
1898 {
1899 log_assert(wires_[w1->name] == w1);
1900 log_assert(wires_[w2->name] == w2);
1901 log_assert(refcount_wires_ == 0);
1902
1903 wires_.erase(w1->name);
1904 wires_.erase(w2->name);
1905
1906 std::swap(w1->name, w2->name);
1907
1908 wires_[w1->name] = w1;
1909 wires_[w2->name] = w2;
1910 }
1911
1912 void RTLIL::Module::swap_names(RTLIL::Cell *c1, RTLIL::Cell *c2)
1913 {
1914 log_assert(cells_[c1->name] == c1);
1915 log_assert(cells_[c2->name] == c2);
1916 log_assert(refcount_cells_ == 0);
1917
1918 cells_.erase(c1->name);
1919 cells_.erase(c2->name);
1920
1921 std::swap(c1->name, c2->name);
1922
1923 cells_[c1->name] = c1;
1924 cells_[c2->name] = c2;
1925 }
1926
1927 RTLIL::IdString RTLIL::Module::uniquify(RTLIL::IdString name)
1928 {
1929 int index = 0;
1930 return uniquify(name, index);
1931 }
1932
1933 RTLIL::IdString RTLIL::Module::uniquify(RTLIL::IdString name, int &index)
1934 {
1935 if (index == 0) {
1936 if (count_id(name) == 0)
1937 return name;
1938 index++;
1939 }
1940
1941 while (1) {
1942 RTLIL::IdString new_name = stringf("%s_%d", name.c_str(), index);
1943 if (count_id(new_name) == 0)
1944 return new_name;
1945 index++;
1946 }
1947 }
1948
1949 static bool fixup_ports_compare(const RTLIL::Wire *a, const RTLIL::Wire *b)
1950 {
1951 if (a->port_id && !b->port_id)
1952 return true;
1953 if (!a->port_id && b->port_id)
1954 return false;
1955
1956 if (a->port_id == b->port_id)
1957 return a->name < b->name;
1958 return a->port_id < b->port_id;
1959 }
1960
1961 void RTLIL::Module::connect(const RTLIL::SigSig &conn)
1962 {
1963 for (auto mon : monitors)
1964 mon->notify_connect(this, conn);
1965
1966 if (design)
1967 for (auto mon : design->monitors)
1968 mon->notify_connect(this, conn);
1969
1970 // ignore all attempts to assign constants to other constants
1971 if (conn.first.has_const()) {
1972 RTLIL::SigSig new_conn;
1973 for (int i = 0; i < GetSize(conn.first); i++)
1974 if (conn.first[i].wire) {
1975 new_conn.first.append(conn.first[i]);
1976 new_conn.second.append(conn.second[i]);
1977 }
1978 if (GetSize(new_conn.first))
1979 connect(new_conn);
1980 return;
1981 }
1982
1983 if (yosys_xtrace) {
1984 log("#X# Connect (SigSig) in %s: %s = %s (%d bits)\n", log_id(this), log_signal(conn.first), log_signal(conn.second), GetSize(conn.first));
1985 log_backtrace("-X- ", yosys_xtrace-1);
1986 }
1987
1988 log_assert(GetSize(conn.first) == GetSize(conn.second));
1989 connections_.push_back(conn);
1990 }
1991
1992 void RTLIL::Module::connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs)
1993 {
1994 connect(RTLIL::SigSig(lhs, rhs));
1995 }
1996
1997 void RTLIL::Module::new_connections(const std::vector<RTLIL::SigSig> &new_conn)
1998 {
1999 for (auto mon : monitors)
2000 mon->notify_connect(this, new_conn);
2001
2002 if (design)
2003 for (auto mon : design->monitors)
2004 mon->notify_connect(this, new_conn);
2005
2006 if (yosys_xtrace) {
2007 log("#X# New connections vector in %s:\n", log_id(this));
2008 for (auto &conn: new_conn)
2009 log("#X# %s = %s (%d bits)\n", log_signal(conn.first), log_signal(conn.second), GetSize(conn.first));
2010 log_backtrace("-X- ", yosys_xtrace-1);
2011 }
2012
2013 connections_ = new_conn;
2014 }
2015
2016 const std::vector<RTLIL::SigSig> &RTLIL::Module::connections() const
2017 {
2018 return connections_;
2019 }
2020
2021 void RTLIL::Module::fixup_ports()
2022 {
2023 std::vector<RTLIL::Wire*> all_ports;
2024
2025 for (auto &w : wires_)
2026 if (w.second->port_input || w.second->port_output)
2027 all_ports.push_back(w.second);
2028 else
2029 w.second->port_id = 0;
2030
2031 std::sort(all_ports.begin(), all_ports.end(), fixup_ports_compare);
2032
2033 ports.clear();
2034 for (size_t i = 0; i < all_ports.size(); i++) {
2035 ports.push_back(all_ports[i]->name);
2036 all_ports[i]->port_id = i+1;
2037 }
2038 }
2039
2040 RTLIL::Wire *RTLIL::Module::addWire(RTLIL::IdString name, int width)
2041 {
2042 RTLIL::Wire *wire = new RTLIL::Wire;
2043 wire->name = name;
2044 wire->width = width;
2045 add(wire);
2046 return wire;
2047 }
2048
2049 RTLIL::Wire *RTLIL::Module::addWire(RTLIL::IdString name, const RTLIL::Wire *other)
2050 {
2051 RTLIL::Wire *wire = addWire(name);
2052 wire->width = other->width;
2053 wire->start_offset = other->start_offset;
2054 wire->port_id = other->port_id;
2055 wire->port_input = other->port_input;
2056 wire->port_output = other->port_output;
2057 wire->upto = other->upto;
2058 wire->is_signed = other->is_signed;
2059 wire->attributes = other->attributes;
2060 return wire;
2061 }
2062
2063 RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, RTLIL::IdString type)
2064 {
2065 RTLIL::Cell *cell = new RTLIL::Cell;
2066 cell->name = name;
2067 cell->type = type;
2068 add(cell);
2069 return cell;
2070 }
2071
2072 RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, const RTLIL::Cell *other)
2073 {
2074 RTLIL::Cell *cell = addCell(name, other->type);
2075 cell->connections_ = other->connections_;
2076 cell->parameters = other->parameters;
2077 cell->attributes = other->attributes;
2078 return cell;
2079 }
2080
2081 RTLIL::Memory *RTLIL::Module::addMemory(RTLIL::IdString name, const RTLIL::Memory *other)
2082 {
2083 RTLIL::Memory *mem = new RTLIL::Memory;
2084 mem->name = name;
2085 mem->width = other->width;
2086 mem->start_offset = other->start_offset;
2087 mem->size = other->size;
2088 mem->attributes = other->attributes;
2089 memories[mem->name] = mem;
2090 return mem;
2091 }
2092
2093 RTLIL::Process *RTLIL::Module::addProcess(RTLIL::IdString name, const RTLIL::Process *other)
2094 {
2095 RTLIL::Process *proc = other->clone();
2096 proc->name = name;
2097 processes[name] = proc;
2098 return proc;
2099 }
2100
2101 #define DEF_METHOD(_func, _y_size, _type) \
2102 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed, const std::string &src) { \
2103 RTLIL::Cell *cell = addCell(name, _type); \
2104 cell->parameters[ID::A_SIGNED] = is_signed; \
2105 cell->parameters[ID::A_WIDTH] = sig_a.size(); \
2106 cell->parameters[ID::Y_WIDTH] = sig_y.size(); \
2107 cell->setPort(ID::A, sig_a); \
2108 cell->setPort(ID::Y, sig_y); \
2109 cell->set_src_attribute(src); \
2110 return cell; \
2111 } \
2112 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed, const std::string &src) { \
2113 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
2114 add ## _func(name, sig_a, sig_y, is_signed, src); \
2115 return sig_y; \
2116 }
2117 DEF_METHOD(Not, sig_a.size(), ID($not))
2118 DEF_METHOD(Pos, sig_a.size(), ID($pos))
2119 DEF_METHOD(Neg, sig_a.size(), ID($neg))
2120 DEF_METHOD(ReduceAnd, 1, ID($reduce_and))
2121 DEF_METHOD(ReduceOr, 1, ID($reduce_or))
2122 DEF_METHOD(ReduceXor, 1, ID($reduce_xor))
2123 DEF_METHOD(ReduceXnor, 1, ID($reduce_xnor))
2124 DEF_METHOD(ReduceBool, 1, ID($reduce_bool))
2125 DEF_METHOD(LogicNot, 1, ID($logic_not))
2126 #undef DEF_METHOD
2127
2128 #define DEF_METHOD(_func, _y_size, _type) \
2129 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed, const std::string &src) { \
2130 RTLIL::Cell *cell = addCell(name, _type); \
2131 cell->parameters[ID::A_SIGNED] = is_signed; \
2132 cell->parameters[ID::B_SIGNED] = is_signed; \
2133 cell->parameters[ID::A_WIDTH] = sig_a.size(); \
2134 cell->parameters[ID::B_WIDTH] = sig_b.size(); \
2135 cell->parameters[ID::Y_WIDTH] = sig_y.size(); \
2136 cell->setPort(ID::A, sig_a); \
2137 cell->setPort(ID::B, sig_b); \
2138 cell->setPort(ID::Y, sig_y); \
2139 cell->set_src_attribute(src); \
2140 return cell; \
2141 } \
2142 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed, const std::string &src) { \
2143 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
2144 add ## _func(name, sig_a, sig_b, sig_y, is_signed, src); \
2145 return sig_y; \
2146 }
2147 DEF_METHOD(And, max(sig_a.size(), sig_b.size()), ID($and))
2148 DEF_METHOD(Or, max(sig_a.size(), sig_b.size()), ID($or))
2149 DEF_METHOD(Xor, max(sig_a.size(), sig_b.size()), ID($xor))
2150 DEF_METHOD(Xnor, max(sig_a.size(), sig_b.size()), ID($xnor))
2151 DEF_METHOD(Shift, sig_a.size(), ID($shift))
2152 DEF_METHOD(Shiftx, sig_a.size(), ID($shiftx))
2153 DEF_METHOD(Lt, 1, ID($lt))
2154 DEF_METHOD(Le, 1, ID($le))
2155 DEF_METHOD(Eq, 1, ID($eq))
2156 DEF_METHOD(Ne, 1, ID($ne))
2157 DEF_METHOD(Eqx, 1, ID($eqx))
2158 DEF_METHOD(Nex, 1, ID($nex))
2159 DEF_METHOD(Ge, 1, ID($ge))
2160 DEF_METHOD(Gt, 1, ID($gt))
2161 DEF_METHOD(Add, max(sig_a.size(), sig_b.size()), ID($add))
2162 DEF_METHOD(Sub, max(sig_a.size(), sig_b.size()), ID($sub))
2163 DEF_METHOD(Mul, max(sig_a.size(), sig_b.size()), ID($mul))
2164 DEF_METHOD(Div, max(sig_a.size(), sig_b.size()), ID($div))
2165 DEF_METHOD(Mod, max(sig_a.size(), sig_b.size()), ID($mod))
2166 DEF_METHOD(DivFloor, max(sig_a.size(), sig_b.size()), ID($divfloor))
2167 DEF_METHOD(ModFloor, max(sig_a.size(), sig_b.size()), ID($modfloor))
2168 DEF_METHOD(LogicAnd, 1, ID($logic_and))
2169 DEF_METHOD(LogicOr, 1, ID($logic_or))
2170 #undef DEF_METHOD
2171
2172 #define DEF_METHOD(_func, _y_size, _type) \
2173 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed, const std::string &src) { \
2174 RTLIL::Cell *cell = addCell(name, _type); \
2175 cell->parameters[ID::A_SIGNED] = is_signed; \
2176 cell->parameters[ID::B_SIGNED] = false; \
2177 cell->parameters[ID::A_WIDTH] = sig_a.size(); \
2178 cell->parameters[ID::B_WIDTH] = sig_b.size(); \
2179 cell->parameters[ID::Y_WIDTH] = sig_y.size(); \
2180 cell->setPort(ID::A, sig_a); \
2181 cell->setPort(ID::B, sig_b); \
2182 cell->setPort(ID::Y, sig_y); \
2183 cell->set_src_attribute(src); \
2184 return cell; \
2185 } \
2186 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed, const std::string &src) { \
2187 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
2188 add ## _func(name, sig_a, sig_b, sig_y, is_signed, src); \
2189 return sig_y; \
2190 }
2191 DEF_METHOD(Shl, sig_a.size(), ID($shl))
2192 DEF_METHOD(Shr, sig_a.size(), ID($shr))
2193 DEF_METHOD(Sshl, sig_a.size(), ID($sshl))
2194 DEF_METHOD(Sshr, sig_a.size(), ID($sshr))
2195 #undef DEF_METHOD
2196
2197 #define DEF_METHOD(_func, _type, _pmux) \
2198 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, const std::string &src) { \
2199 RTLIL::Cell *cell = addCell(name, _type); \
2200 cell->parameters[ID::WIDTH] = sig_a.size(); \
2201 if (_pmux) cell->parameters[ID::S_WIDTH] = sig_s.size(); \
2202 cell->setPort(ID::A, sig_a); \
2203 cell->setPort(ID::B, sig_b); \
2204 cell->setPort(ID::S, sig_s); \
2205 cell->setPort(ID::Y, sig_y); \
2206 cell->set_src_attribute(src); \
2207 return cell; \
2208 } \
2209 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const std::string &src) { \
2210 RTLIL::SigSpec sig_y = addWire(NEW_ID, sig_a.size()); \
2211 add ## _func(name, sig_a, sig_b, sig_s, sig_y, src); \
2212 return sig_y; \
2213 }
2214 DEF_METHOD(Mux, ID($mux), 0)
2215 DEF_METHOD(Pmux, ID($pmux), 1)
2216 #undef DEF_METHOD
2217
2218 #define DEF_METHOD_2(_func, _type, _P1, _P2) \
2219 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const std::string &src) { \
2220 RTLIL::Cell *cell = addCell(name, _type); \
2221 cell->setPort("\\" #_P1, sig1); \
2222 cell->setPort("\\" #_P2, sig2); \
2223 cell->set_src_attribute(src); \
2224 return cell; \
2225 } \
2226 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const std::string &src) { \
2227 RTLIL::SigBit sig2 = addWire(NEW_ID); \
2228 add ## _func(name, sig1, sig2, src); \
2229 return sig2; \
2230 }
2231 #define DEF_METHOD_3(_func, _type, _P1, _P2, _P3) \
2232 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const RTLIL::SigBit &sig3, const std::string &src) { \
2233 RTLIL::Cell *cell = addCell(name, _type); \
2234 cell->setPort("\\" #_P1, sig1); \
2235 cell->setPort("\\" #_P2, sig2); \
2236 cell->setPort("\\" #_P3, sig3); \
2237 cell->set_src_attribute(src); \
2238 return cell; \
2239 } \
2240 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const std::string &src) { \
2241 RTLIL::SigBit sig3 = addWire(NEW_ID); \
2242 add ## _func(name, sig1, sig2, sig3, src); \
2243 return sig3; \
2244 }
2245 #define DEF_METHOD_4(_func, _type, _P1, _P2, _P3, _P4) \
2246 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const RTLIL::SigBit &sig3, const RTLIL::SigBit &sig4, const std::string &src) { \
2247 RTLIL::Cell *cell = addCell(name, _type); \
2248 cell->setPort("\\" #_P1, sig1); \
2249 cell->setPort("\\" #_P2, sig2); \
2250 cell->setPort("\\" #_P3, sig3); \
2251 cell->setPort("\\" #_P4, sig4); \
2252 cell->set_src_attribute(src); \
2253 return cell; \
2254 } \
2255 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const RTLIL::SigBit &sig3, const std::string &src) { \
2256 RTLIL::SigBit sig4 = addWire(NEW_ID); \
2257 add ## _func(name, sig1, sig2, sig3, sig4, src); \
2258 return sig4; \
2259 }
2260 #define DEF_METHOD_5(_func, _type, _P1, _P2, _P3, _P4, _P5) \
2261 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const RTLIL::SigBit &sig3, const RTLIL::SigBit &sig4, const RTLIL::SigBit &sig5, const std::string &src) { \
2262 RTLIL::Cell *cell = addCell(name, _type); \
2263 cell->setPort("\\" #_P1, sig1); \
2264 cell->setPort("\\" #_P2, sig2); \
2265 cell->setPort("\\" #_P3, sig3); \
2266 cell->setPort("\\" #_P4, sig4); \
2267 cell->setPort("\\" #_P5, sig5); \
2268 cell->set_src_attribute(src); \
2269 return cell; \
2270 } \
2271 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const RTLIL::SigBit &sig3, const RTLIL::SigBit &sig4, const std::string &src) { \
2272 RTLIL::SigBit sig5 = addWire(NEW_ID); \
2273 add ## _func(name, sig1, sig2, sig3, sig4, sig5, src); \
2274 return sig5; \
2275 }
2276 DEF_METHOD_2(BufGate, ID($_BUF_), A, Y)
2277 DEF_METHOD_2(NotGate, ID($_NOT_), A, Y)
2278 DEF_METHOD_3(AndGate, ID($_AND_), A, B, Y)
2279 DEF_METHOD_3(NandGate, ID($_NAND_), A, B, Y)
2280 DEF_METHOD_3(OrGate, ID($_OR_), A, B, Y)
2281 DEF_METHOD_3(NorGate, ID($_NOR_), A, B, Y)
2282 DEF_METHOD_3(XorGate, ID($_XOR_), A, B, Y)
2283 DEF_METHOD_3(XnorGate, ID($_XNOR_), A, B, Y)
2284 DEF_METHOD_3(AndnotGate, ID($_ANDNOT_), A, B, Y)
2285 DEF_METHOD_3(OrnotGate, ID($_ORNOT_), A, B, Y)
2286 DEF_METHOD_4(MuxGate, ID($_MUX_), A, B, S, Y)
2287 DEF_METHOD_4(NmuxGate, ID($_NMUX_), A, B, S, Y)
2288 DEF_METHOD_4(Aoi3Gate, ID($_AOI3_), A, B, C, Y)
2289 DEF_METHOD_4(Oai3Gate, ID($_OAI3_), A, B, C, Y)
2290 DEF_METHOD_5(Aoi4Gate, ID($_AOI4_), A, B, C, D, Y)
2291 DEF_METHOD_5(Oai4Gate, ID($_OAI4_), A, B, C, D, Y)
2292 #undef DEF_METHOD_2
2293 #undef DEF_METHOD_3
2294 #undef DEF_METHOD_4
2295 #undef DEF_METHOD_5
2296
2297 RTLIL::Cell* RTLIL::Module::addPow(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool a_signed, bool b_signed, const std::string &src)
2298 {
2299 RTLIL::Cell *cell = addCell(name, ID($pow));
2300 cell->parameters[ID::A_SIGNED] = a_signed;
2301 cell->parameters[ID::B_SIGNED] = b_signed;
2302 cell->parameters[ID::A_WIDTH] = sig_a.size();
2303 cell->parameters[ID::B_WIDTH] = sig_b.size();
2304 cell->parameters[ID::Y_WIDTH] = sig_y.size();
2305 cell->setPort(ID::A, sig_a);
2306 cell->setPort(ID::B, sig_b);
2307 cell->setPort(ID::Y, sig_y);
2308 cell->set_src_attribute(src);
2309 return cell;
2310 }
2311
2312 RTLIL::Cell* RTLIL::Module::addSlice(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, RTLIL::Const offset, const std::string &src)
2313 {
2314 RTLIL::Cell *cell = addCell(name, ID($slice));
2315 cell->parameters[ID::A_WIDTH] = sig_a.size();
2316 cell->parameters[ID::Y_WIDTH] = sig_y.size();
2317 cell->parameters[ID::OFFSET] = offset;
2318 cell->setPort(ID::A, sig_a);
2319 cell->setPort(ID::Y, sig_y);
2320 cell->set_src_attribute(src);
2321 return cell;
2322 }
2323
2324 RTLIL::Cell* RTLIL::Module::addConcat(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, const std::string &src)
2325 {
2326 RTLIL::Cell *cell = addCell(name, ID($concat));
2327 cell->parameters[ID::A_WIDTH] = sig_a.size();
2328 cell->parameters[ID::B_WIDTH] = sig_b.size();
2329 cell->setPort(ID::A, sig_a);
2330 cell->setPort(ID::B, sig_b);
2331 cell->setPort(ID::Y, sig_y);
2332 cell->set_src_attribute(src);
2333 return cell;
2334 }
2335
2336 RTLIL::Cell* RTLIL::Module::addLut(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, RTLIL::Const lut, const std::string &src)
2337 {
2338 RTLIL::Cell *cell = addCell(name, ID($lut));
2339 cell->parameters[ID::LUT] = lut;
2340 cell->parameters[ID::WIDTH] = sig_a.size();
2341 cell->setPort(ID::A, sig_a);
2342 cell->setPort(ID::Y, sig_y);
2343 cell->set_src_attribute(src);
2344 return cell;
2345 }
2346
2347 RTLIL::Cell* RTLIL::Module::addTribuf(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_y, const std::string &src)
2348 {
2349 RTLIL::Cell *cell = addCell(name, ID($tribuf));
2350 cell->parameters[ID::WIDTH] = sig_a.size();
2351 cell->setPort(ID::A, sig_a);
2352 cell->setPort(ID::EN, sig_en);
2353 cell->setPort(ID::Y, sig_y);
2354 cell->set_src_attribute(src);
2355 return cell;
2356 }
2357
2358 RTLIL::Cell* RTLIL::Module::addAssert(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src)
2359 {
2360 RTLIL::Cell *cell = addCell(name, ID($assert));
2361 cell->setPort(ID::A, sig_a);
2362 cell->setPort(ID::EN, sig_en);
2363 cell->set_src_attribute(src);
2364 return cell;
2365 }
2366
2367 RTLIL::Cell* RTLIL::Module::addAssume(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src)
2368 {
2369 RTLIL::Cell *cell = addCell(name, ID($assume));
2370 cell->setPort(ID::A, sig_a);
2371 cell->setPort(ID::EN, sig_en);
2372 cell->set_src_attribute(src);
2373 return cell;
2374 }
2375
2376 RTLIL::Cell* RTLIL::Module::addLive(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src)
2377 {
2378 RTLIL::Cell *cell = addCell(name, ID($live));
2379 cell->setPort(ID::A, sig_a);
2380 cell->setPort(ID::EN, sig_en);
2381 cell->set_src_attribute(src);
2382 return cell;
2383 }
2384
2385 RTLIL::Cell* RTLIL::Module::addFair(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src)
2386 {
2387 RTLIL::Cell *cell = addCell(name, ID($fair));
2388 cell->setPort(ID::A, sig_a);
2389 cell->setPort(ID::EN, sig_en);
2390 cell->set_src_attribute(src);
2391 return cell;
2392 }
2393
2394 RTLIL::Cell* RTLIL::Module::addCover(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src)
2395 {
2396 RTLIL::Cell *cell = addCell(name, ID($cover));
2397 cell->setPort(ID::A, sig_a);
2398 cell->setPort(ID::EN, sig_en);
2399 cell->set_src_attribute(src);
2400 return cell;
2401 }
2402
2403 RTLIL::Cell* RTLIL::Module::addEquiv(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, const std::string &src)
2404 {
2405 RTLIL::Cell *cell = addCell(name, ID($equiv));
2406 cell->setPort(ID::A, sig_a);
2407 cell->setPort(ID::B, sig_b);
2408 cell->setPort(ID::Y, sig_y);
2409 cell->set_src_attribute(src);
2410 return cell;
2411 }
2412
2413 RTLIL::Cell* RTLIL::Module::addSr(RTLIL::IdString name, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, const RTLIL::SigSpec &sig_q, bool set_polarity, bool clr_polarity, const std::string &src)
2414 {
2415 RTLIL::Cell *cell = addCell(name, ID($sr));
2416 cell->parameters[ID::SET_POLARITY] = set_polarity;
2417 cell->parameters[ID::CLR_POLARITY] = clr_polarity;
2418 cell->parameters[ID::WIDTH] = sig_q.size();
2419 cell->setPort(ID::SET, sig_set);
2420 cell->setPort(ID::CLR, sig_clr);
2421 cell->setPort(ID::Q, sig_q);
2422 cell->set_src_attribute(src);
2423 return cell;
2424 }
2425
2426 RTLIL::Cell* RTLIL::Module::addFf(RTLIL::IdString name, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const std::string &src)
2427 {
2428 RTLIL::Cell *cell = addCell(name, ID($ff));
2429 cell->parameters[ID::WIDTH] = sig_q.size();
2430 cell->setPort(ID::D, sig_d);
2431 cell->setPort(ID::Q, sig_q);
2432 cell->set_src_attribute(src);
2433 return cell;
2434 }
2435
2436 RTLIL::Cell* RTLIL::Module::addDff(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, const std::string &src)
2437 {
2438 RTLIL::Cell *cell = addCell(name, ID($dff));
2439 cell->parameters[ID::CLK_POLARITY] = clk_polarity;
2440 cell->parameters[ID::WIDTH] = sig_q.size();
2441 cell->setPort(ID::CLK, sig_clk);
2442 cell->setPort(ID::D, sig_d);
2443 cell->setPort(ID::Q, sig_q);
2444 cell->set_src_attribute(src);
2445 return cell;
2446 }
2447
2448 RTLIL::Cell* RTLIL::Module::addDffe(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, bool en_polarity, const std::string &src)
2449 {
2450 RTLIL::Cell *cell = addCell(name, ID($dffe));
2451 cell->parameters[ID::CLK_POLARITY] = clk_polarity;
2452 cell->parameters[ID::EN_POLARITY] = en_polarity;
2453 cell->parameters[ID::WIDTH] = sig_q.size();
2454 cell->setPort(ID::CLK, sig_clk);
2455 cell->setPort(ID::EN, sig_en);
2456 cell->setPort(ID::D, sig_d);
2457 cell->setPort(ID::Q, sig_q);
2458 cell->set_src_attribute(src);
2459 return cell;
2460 }
2461
2462 RTLIL::Cell* RTLIL::Module::addDffsr(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,
2463 RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
2464 {
2465 RTLIL::Cell *cell = addCell(name, ID($dffsr));
2466 cell->parameters[ID::CLK_POLARITY] = clk_polarity;
2467 cell->parameters[ID::SET_POLARITY] = set_polarity;
2468 cell->parameters[ID::CLR_POLARITY] = clr_polarity;
2469 cell->parameters[ID::WIDTH] = sig_q.size();
2470 cell->setPort(ID::CLK, sig_clk);
2471 cell->setPort(ID::SET, sig_set);
2472 cell->setPort(ID::CLR, sig_clr);
2473 cell->setPort(ID::D, sig_d);
2474 cell->setPort(ID::Q, sig_q);
2475 cell->set_src_attribute(src);
2476 return cell;
2477 }
2478
2479 RTLIL::Cell* RTLIL::Module::addDffsre(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,
2480 RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, bool en_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
2481 {
2482 RTLIL::Cell *cell = addCell(name, ID($dffsre));
2483 cell->parameters[ID::CLK_POLARITY] = clk_polarity;
2484 cell->parameters[ID::EN_POLARITY] = en_polarity;
2485 cell->parameters[ID::SET_POLARITY] = set_polarity;
2486 cell->parameters[ID::CLR_POLARITY] = clr_polarity;
2487 cell->parameters[ID::WIDTH] = sig_q.size();
2488 cell->setPort(ID::CLK, sig_clk);
2489 cell->setPort(ID::EN, sig_en);
2490 cell->setPort(ID::SET, sig_set);
2491 cell->setPort(ID::CLR, sig_clr);
2492 cell->setPort(ID::D, sig_d);
2493 cell->setPort(ID::Q, sig_q);
2494 cell->set_src_attribute(src);
2495 return cell;
2496 }
2497
2498 RTLIL::Cell* RTLIL::Module::addAdff(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
2499 RTLIL::Const arst_value, bool clk_polarity, bool arst_polarity, const std::string &src)
2500 {
2501 RTLIL::Cell *cell = addCell(name, ID($adff));
2502 cell->parameters[ID::CLK_POLARITY] = clk_polarity;
2503 cell->parameters[ID::ARST_POLARITY] = arst_polarity;
2504 cell->parameters[ID::ARST_VALUE] = arst_value;
2505 cell->parameters[ID::WIDTH] = sig_q.size();
2506 cell->setPort(ID::CLK, sig_clk);
2507 cell->setPort(ID::ARST, sig_arst);
2508 cell->setPort(ID::D, sig_d);
2509 cell->setPort(ID::Q, sig_q);
2510 cell->set_src_attribute(src);
2511 return cell;
2512 }
2513
2514 RTLIL::Cell* RTLIL::Module::addAdffe(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
2515 RTLIL::Const arst_value, bool clk_polarity, bool en_polarity, bool arst_polarity, const std::string &src)
2516 {
2517 RTLIL::Cell *cell = addCell(name, ID($adffe));
2518 cell->parameters[ID::CLK_POLARITY] = clk_polarity;
2519 cell->parameters[ID::EN_POLARITY] = en_polarity;
2520 cell->parameters[ID::ARST_POLARITY] = arst_polarity;
2521 cell->parameters[ID::ARST_VALUE] = arst_value;
2522 cell->parameters[ID::WIDTH] = sig_q.size();
2523 cell->setPort(ID::CLK, sig_clk);
2524 cell->setPort(ID::EN, sig_en);
2525 cell->setPort(ID::ARST, sig_arst);
2526 cell->setPort(ID::D, sig_d);
2527 cell->setPort(ID::Q, sig_q);
2528 cell->set_src_attribute(src);
2529 return cell;
2530 }
2531
2532 RTLIL::Cell* RTLIL::Module::addSdff(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
2533 RTLIL::Const srst_value, bool clk_polarity, bool srst_polarity, const std::string &src)
2534 {
2535 RTLIL::Cell *cell = addCell(name, ID($sdff));
2536 cell->parameters[ID::CLK_POLARITY] = clk_polarity;
2537 cell->parameters[ID::SRST_POLARITY] = srst_polarity;
2538 cell->parameters[ID::SRST_VALUE] = srst_value;
2539 cell->parameters[ID::WIDTH] = sig_q.size();
2540 cell->setPort(ID::CLK, sig_clk);
2541 cell->setPort(ID::SRST, sig_srst);
2542 cell->setPort(ID::D, sig_d);
2543 cell->setPort(ID::Q, sig_q);
2544 cell->set_src_attribute(src);
2545 return cell;
2546 }
2547
2548 RTLIL::Cell* RTLIL::Module::addSdffe(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
2549 RTLIL::Const srst_value, bool clk_polarity, bool en_polarity, bool srst_polarity, const std::string &src)
2550 {
2551 RTLIL::Cell *cell = addCell(name, ID($sdffe));
2552 cell->parameters[ID::CLK_POLARITY] = clk_polarity;
2553 cell->parameters[ID::EN_POLARITY] = en_polarity;
2554 cell->parameters[ID::SRST_POLARITY] = srst_polarity;
2555 cell->parameters[ID::SRST_VALUE] = srst_value;
2556 cell->parameters[ID::WIDTH] = sig_q.size();
2557 cell->setPort(ID::CLK, sig_clk);
2558 cell->setPort(ID::EN, sig_en);
2559 cell->setPort(ID::SRST, sig_srst);
2560 cell->setPort(ID::D, sig_d);
2561 cell->setPort(ID::Q, sig_q);
2562 cell->set_src_attribute(src);
2563 return cell;
2564 }
2565
2566 RTLIL::Cell* RTLIL::Module::addSdffce(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
2567 RTLIL::Const srst_value, bool clk_polarity, bool en_polarity, bool srst_polarity, const std::string &src)
2568 {
2569 RTLIL::Cell *cell = addCell(name, ID($sdffce));
2570 cell->parameters[ID::CLK_POLARITY] = clk_polarity;
2571 cell->parameters[ID::EN_POLARITY] = en_polarity;
2572 cell->parameters[ID::SRST_POLARITY] = srst_polarity;
2573 cell->parameters[ID::SRST_VALUE] = srst_value;
2574 cell->parameters[ID::WIDTH] = sig_q.size();
2575 cell->setPort(ID::CLK, sig_clk);
2576 cell->setPort(ID::EN, sig_en);
2577 cell->setPort(ID::SRST, sig_srst);
2578 cell->setPort(ID::D, sig_d);
2579 cell->setPort(ID::Q, sig_q);
2580 cell->set_src_attribute(src);
2581 return cell;
2582 }
2583
2584 RTLIL::Cell* RTLIL::Module::addDlatch(RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity, const std::string &src)
2585 {
2586 RTLIL::Cell *cell = addCell(name, ID($dlatch));
2587 cell->parameters[ID::EN_POLARITY] = en_polarity;
2588 cell->parameters[ID::WIDTH] = sig_q.size();
2589 cell->setPort(ID::EN, sig_en);
2590 cell->setPort(ID::D, sig_d);
2591 cell->setPort(ID::Q, sig_q);
2592 cell->set_src_attribute(src);
2593 return cell;
2594 }
2595
2596 RTLIL::Cell* RTLIL::Module::addAdlatch(RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
2597 RTLIL::Const arst_value, bool en_polarity, bool arst_polarity, const std::string &src)
2598 {
2599 RTLIL::Cell *cell = addCell(name, ID($adlatch));
2600 cell->parameters[ID::EN_POLARITY] = en_polarity;
2601 cell->parameters[ID::ARST_POLARITY] = arst_polarity;
2602 cell->parameters[ID::ARST_VALUE] = arst_value;
2603 cell->parameters[ID::WIDTH] = sig_q.size();
2604 cell->setPort(ID::EN, sig_en);
2605 cell->setPort(ID::ARST, sig_arst);
2606 cell->setPort(ID::D, sig_d);
2607 cell->setPort(ID::Q, sig_q);
2608 cell->set_src_attribute(src);
2609 return cell;
2610 }
2611
2612 RTLIL::Cell* RTLIL::Module::addDlatchsr(RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,
2613 RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
2614 {
2615 RTLIL::Cell *cell = addCell(name, ID($dlatchsr));
2616 cell->parameters[ID::EN_POLARITY] = en_polarity;
2617 cell->parameters[ID::SET_POLARITY] = set_polarity;
2618 cell->parameters[ID::CLR_POLARITY] = clr_polarity;
2619 cell->parameters[ID::WIDTH] = sig_q.size();
2620 cell->setPort(ID::EN, sig_en);
2621 cell->setPort(ID::SET, sig_set);
2622 cell->setPort(ID::CLR, sig_clr);
2623 cell->setPort(ID::D, sig_d);
2624 cell->setPort(ID::Q, sig_q);
2625 cell->set_src_attribute(src);
2626 return cell;
2627 }
2628
2629 RTLIL::Cell* RTLIL::Module::addSrGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,
2630 const RTLIL::SigSpec &sig_q, bool set_polarity, bool clr_polarity, const std::string &src)
2631 {
2632 RTLIL::Cell *cell = addCell(name, stringf("$_SR_%c%c_", set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N'));
2633 cell->setPort(ID::S, sig_set);
2634 cell->setPort(ID::R, sig_clr);
2635 cell->setPort(ID::Q, sig_q);
2636 cell->set_src_attribute(src);
2637 return cell;
2638 }
2639
2640 RTLIL::Cell* RTLIL::Module::addFfGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const std::string &src)
2641 {
2642 RTLIL::Cell *cell = addCell(name, ID($_FF_));
2643 cell->setPort(ID::D, sig_d);
2644 cell->setPort(ID::Q, sig_q);
2645 cell->set_src_attribute(src);
2646 return cell;
2647 }
2648
2649 RTLIL::Cell* RTLIL::Module::addDffGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, const std::string &src)
2650 {
2651 RTLIL::Cell *cell = addCell(name, stringf("$_DFF_%c_", clk_polarity ? 'P' : 'N'));
2652 cell->setPort(ID::C, sig_clk);
2653 cell->setPort(ID::D, sig_d);
2654 cell->setPort(ID::Q, sig_q);
2655 cell->set_src_attribute(src);
2656 return cell;
2657 }
2658
2659 RTLIL::Cell* RTLIL::Module::addDffeGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, bool en_polarity, const std::string &src)
2660 {
2661 RTLIL::Cell *cell = addCell(name, stringf("$_DFFE_%c%c_", clk_polarity ? 'P' : 'N', en_polarity ? 'P' : 'N'));
2662 cell->setPort(ID::C, sig_clk);
2663 cell->setPort(ID::E, sig_en);
2664 cell->setPort(ID::D, sig_d);
2665 cell->setPort(ID::Q, sig_q);
2666 cell->set_src_attribute(src);
2667 return cell;
2668 }
2669
2670 RTLIL::Cell* RTLIL::Module::addDffsrGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,
2671 RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
2672 {
2673 RTLIL::Cell *cell = addCell(name, stringf("$_DFFSR_%c%c%c_", clk_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N'));
2674 cell->setPort(ID::C, sig_clk);
2675 cell->setPort(ID::S, sig_set);
2676 cell->setPort(ID::R, sig_clr);
2677 cell->setPort(ID::D, sig_d);
2678 cell->setPort(ID::Q, sig_q);
2679 cell->set_src_attribute(src);
2680 return cell;
2681 }
2682
2683 RTLIL::Cell* RTLIL::Module::addDffsreGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,
2684 RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, bool en_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
2685 {
2686 RTLIL::Cell *cell = addCell(name, stringf("$_DFFSRE_%c%c%c%c_", clk_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N', en_polarity ? 'P' : 'N'));
2687 cell->setPort(ID::C, sig_clk);
2688 cell->setPort(ID::S, sig_set);
2689 cell->setPort(ID::R, sig_clr);
2690 cell->setPort(ID::E, sig_en);
2691 cell->setPort(ID::D, sig_d);
2692 cell->setPort(ID::Q, sig_q);
2693 cell->set_src_attribute(src);
2694 return cell;
2695 }
2696
2697 RTLIL::Cell* RTLIL::Module::addAdffGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
2698 bool arst_value, bool clk_polarity, bool arst_polarity, const std::string &src)
2699 {
2700 RTLIL::Cell *cell = addCell(name, stringf("$_DFF_%c%c%c_", clk_polarity ? 'P' : 'N', arst_polarity ? 'P' : 'N', arst_value ? '1' : '0'));
2701 cell->setPort(ID::C, sig_clk);
2702 cell->setPort(ID::R, sig_arst);
2703 cell->setPort(ID::D, sig_d);
2704 cell->setPort(ID::Q, sig_q);
2705 cell->set_src_attribute(src);
2706 return cell;
2707 }
2708
2709 RTLIL::Cell* RTLIL::Module::addAdffeGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
2710 bool arst_value, bool clk_polarity, bool en_polarity, bool arst_polarity, const std::string &src)
2711 {
2712 RTLIL::Cell *cell = addCell(name, stringf("$_DFFE_%c%c%c%c_", clk_polarity ? 'P' : 'N', arst_polarity ? 'P' : 'N', arst_value ? '1' : '0', en_polarity ? 'P' : 'N'));
2713 cell->setPort(ID::C, sig_clk);
2714 cell->setPort(ID::R, sig_arst);
2715 cell->setPort(ID::E, sig_en);
2716 cell->setPort(ID::D, sig_d);
2717 cell->setPort(ID::Q, sig_q);
2718 cell->set_src_attribute(src);
2719 return cell;
2720 }
2721
2722 RTLIL::Cell* RTLIL::Module::addSdffGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
2723 bool srst_value, bool clk_polarity, bool srst_polarity, const std::string &src)
2724 {
2725 RTLIL::Cell *cell = addCell(name, stringf("$_SDFF_%c%c%c_", clk_polarity ? 'P' : 'N', srst_polarity ? 'P' : 'N', srst_value ? '1' : '0'));
2726 cell->setPort(ID::C, sig_clk);
2727 cell->setPort(ID::R, sig_srst);
2728 cell->setPort(ID::D, sig_d);
2729 cell->setPort(ID::Q, sig_q);
2730 cell->set_src_attribute(src);
2731 return cell;
2732 }
2733
2734 RTLIL::Cell* RTLIL::Module::addSdffeGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
2735 bool srst_value, bool clk_polarity, bool en_polarity, bool srst_polarity, const std::string &src)
2736 {
2737 RTLIL::Cell *cell = addCell(name, stringf("$_SDFFE_%c%c%c%c_", clk_polarity ? 'P' : 'N', srst_polarity ? 'P' : 'N', srst_value ? '1' : '0', en_polarity ? 'P' : 'N'));
2738 cell->setPort(ID::C, sig_clk);
2739 cell->setPort(ID::R, sig_srst);
2740 cell->setPort(ID::E, sig_en);
2741 cell->setPort(ID::D, sig_d);
2742 cell->setPort(ID::Q, sig_q);
2743 cell->set_src_attribute(src);
2744 return cell;
2745 }
2746
2747 RTLIL::Cell* RTLIL::Module::addSdffceGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
2748 bool srst_value, bool clk_polarity, bool en_polarity, bool srst_polarity, const std::string &src)
2749 {
2750 RTLIL::Cell *cell = addCell(name, stringf("$_SDFFCE_%c%c%c%c_", clk_polarity ? 'P' : 'N', srst_polarity ? 'P' : 'N', srst_value ? '1' : '0', en_polarity ? 'P' : 'N'));
2751 cell->setPort(ID::C, sig_clk);
2752 cell->setPort(ID::R, sig_srst);
2753 cell->setPort(ID::E, sig_en);
2754 cell->setPort(ID::D, sig_d);
2755 cell->setPort(ID::Q, sig_q);
2756 cell->set_src_attribute(src);
2757 return cell;
2758 }
2759
2760 RTLIL::Cell* RTLIL::Module::addDlatchGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity, const std::string &src)
2761 {
2762 RTLIL::Cell *cell = addCell(name, stringf("$_DLATCH_%c_", en_polarity ? 'P' : 'N'));
2763 cell->setPort(ID::E, sig_en);
2764 cell->setPort(ID::D, sig_d);
2765 cell->setPort(ID::Q, sig_q);
2766 cell->set_src_attribute(src);
2767 return cell;
2768 }
2769
2770 RTLIL::Cell* RTLIL::Module::addAdlatchGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
2771 bool arst_value, bool en_polarity, bool arst_polarity, const std::string &src)
2772 {
2773 RTLIL::Cell *cell = addCell(name, stringf("$_DLATCH_%c%c%c_", en_polarity ? 'P' : 'N', arst_polarity ? 'P' : 'N', arst_value ? '1' : '0'));
2774 cell->setPort(ID::E, sig_en);
2775 cell->setPort(ID::R, sig_arst);
2776 cell->setPort(ID::D, sig_d);
2777 cell->setPort(ID::Q, sig_q);
2778 cell->set_src_attribute(src);
2779 return cell;
2780 }
2781
2782 RTLIL::Cell* RTLIL::Module::addDlatchsrGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,
2783 RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
2784 {
2785 RTLIL::Cell *cell = addCell(name, stringf("$_DLATCHSR_%c%c%c_", en_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N'));
2786 cell->setPort(ID::E, sig_en);
2787 cell->setPort(ID::S, sig_set);
2788 cell->setPort(ID::R, sig_clr);
2789 cell->setPort(ID::D, sig_d);
2790 cell->setPort(ID::Q, sig_q);
2791 cell->set_src_attribute(src);
2792 return cell;
2793 }
2794
2795 RTLIL::SigSpec RTLIL::Module::Anyconst(RTLIL::IdString name, int width, const std::string &src)
2796 {
2797 RTLIL::SigSpec sig = addWire(NEW_ID, width);
2798 Cell *cell = addCell(name, ID($anyconst));
2799 cell->setParam(ID::WIDTH, width);
2800 cell->setPort(ID::Y, sig);
2801 cell->set_src_attribute(src);
2802 return sig;
2803 }
2804
2805 RTLIL::SigSpec RTLIL::Module::Anyseq(RTLIL::IdString name, int width, const std::string &src)
2806 {
2807 RTLIL::SigSpec sig = addWire(NEW_ID, width);
2808 Cell *cell = addCell(name, ID($anyseq));
2809 cell->setParam(ID::WIDTH, width);
2810 cell->setPort(ID::Y, sig);
2811 cell->set_src_attribute(src);
2812 return sig;
2813 }
2814
2815 RTLIL::SigSpec RTLIL::Module::Allconst(RTLIL::IdString name, int width, const std::string &src)
2816 {
2817 RTLIL::SigSpec sig = addWire(NEW_ID, width);
2818 Cell *cell = addCell(name, ID($allconst));
2819 cell->setParam(ID::WIDTH, width);
2820 cell->setPort(ID::Y, sig);
2821 cell->set_src_attribute(src);
2822 return sig;
2823 }
2824
2825 RTLIL::SigSpec RTLIL::Module::Allseq(RTLIL::IdString name, int width, const std::string &src)
2826 {
2827 RTLIL::SigSpec sig = addWire(NEW_ID, width);
2828 Cell *cell = addCell(name, ID($allseq));
2829 cell->setParam(ID::WIDTH, width);
2830 cell->setPort(ID::Y, sig);
2831 cell->set_src_attribute(src);
2832 return sig;
2833 }
2834
2835 RTLIL::SigSpec RTLIL::Module::Initstate(RTLIL::IdString name, const std::string &src)
2836 {
2837 RTLIL::SigSpec sig = addWire(NEW_ID);
2838 Cell *cell = addCell(name, ID($initstate));
2839 cell->setPort(ID::Y, sig);
2840 cell->set_src_attribute(src);
2841 return sig;
2842 }
2843
2844 RTLIL::Wire::Wire()
2845 {
2846 static unsigned int hashidx_count = 123456789;
2847 hashidx_count = mkhash_xorshift(hashidx_count);
2848 hashidx_ = hashidx_count;
2849
2850 module = nullptr;
2851 width = 1;
2852 start_offset = 0;
2853 port_id = 0;
2854 port_input = false;
2855 port_output = false;
2856 upto = false;
2857 is_signed = false;
2858
2859 #ifdef WITH_PYTHON
2860 RTLIL::Wire::get_all_wires()->insert(std::pair<unsigned int, RTLIL::Wire*>(hashidx_, this));
2861 #endif
2862 }
2863
2864 RTLIL::Wire::~Wire()
2865 {
2866 #ifdef WITH_PYTHON
2867 RTLIL::Wire::get_all_wires()->erase(hashidx_);
2868 #endif
2869 }
2870
2871 #ifdef WITH_PYTHON
2872 static std::map<unsigned int, RTLIL::Wire*> all_wires;
2873 std::map<unsigned int, RTLIL::Wire*> *RTLIL::Wire::get_all_wires(void)
2874 {
2875 return &all_wires;
2876 }
2877 #endif
2878
2879 RTLIL::Memory::Memory()
2880 {
2881 static unsigned int hashidx_count = 123456789;
2882 hashidx_count = mkhash_xorshift(hashidx_count);
2883 hashidx_ = hashidx_count;
2884
2885 width = 1;
2886 start_offset = 0;
2887 size = 0;
2888 #ifdef WITH_PYTHON
2889 RTLIL::Memory::get_all_memorys()->insert(std::pair<unsigned int, RTLIL::Memory*>(hashidx_, this));
2890 #endif
2891 }
2892
2893 RTLIL::Cell::Cell() : module(nullptr)
2894 {
2895 static unsigned int hashidx_count = 123456789;
2896 hashidx_count = mkhash_xorshift(hashidx_count);
2897 hashidx_ = hashidx_count;
2898
2899 // log("#memtrace# %p\n", this);
2900 memhasher();
2901
2902 #ifdef WITH_PYTHON
2903 RTLIL::Cell::get_all_cells()->insert(std::pair<unsigned int, RTLIL::Cell*>(hashidx_, this));
2904 #endif
2905 }
2906
2907 RTLIL::Cell::~Cell()
2908 {
2909 #ifdef WITH_PYTHON
2910 RTLIL::Cell::get_all_cells()->erase(hashidx_);
2911 #endif
2912 }
2913
2914 #ifdef WITH_PYTHON
2915 static std::map<unsigned int, RTLIL::Cell*> all_cells;
2916 std::map<unsigned int, RTLIL::Cell*> *RTLIL::Cell::get_all_cells(void)
2917 {
2918 return &all_cells;
2919 }
2920 #endif
2921
2922 bool RTLIL::Cell::hasPort(RTLIL::IdString portname) const
2923 {
2924 return connections_.count(portname) != 0;
2925 }
2926
2927 void RTLIL::Cell::unsetPort(RTLIL::IdString portname)
2928 {
2929 RTLIL::SigSpec signal;
2930 auto conn_it = connections_.find(portname);
2931
2932 if (conn_it != connections_.end())
2933 {
2934 for (auto mon : module->monitors)
2935 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
2936
2937 if (module->design)
2938 for (auto mon : module->design->monitors)
2939 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
2940
2941 if (yosys_xtrace) {
2942 log("#X# Unconnect %s.%s.%s\n", log_id(this->module), log_id(this), log_id(portname));
2943 log_backtrace("-X- ", yosys_xtrace-1);
2944 }
2945
2946 connections_.erase(conn_it);
2947 }
2948 }
2949
2950 void RTLIL::Cell::setPort(RTLIL::IdString portname, RTLIL::SigSpec signal)
2951 {
2952 auto r = connections_.insert(portname);
2953 auto conn_it = r.first;
2954 if (!r.second && conn_it->second == signal)
2955 return;
2956
2957 for (auto mon : module->monitors)
2958 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
2959
2960 if (module->design)
2961 for (auto mon : module->design->monitors)
2962 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
2963
2964 if (yosys_xtrace) {
2965 log("#X# Connect %s.%s.%s = %s (%d)\n", log_id(this->module), log_id(this), log_id(portname), log_signal(signal), GetSize(signal));
2966 log_backtrace("-X- ", yosys_xtrace-1);
2967 }
2968
2969 conn_it->second = std::move(signal);
2970 }
2971
2972 const RTLIL::SigSpec &RTLIL::Cell::getPort(RTLIL::IdString portname) const
2973 {
2974 return connections_.at(portname);
2975 }
2976
2977 const dict<RTLIL::IdString, RTLIL::SigSpec> &RTLIL::Cell::connections() const
2978 {
2979 return connections_;
2980 }
2981
2982 bool RTLIL::Cell::known() const
2983 {
2984 if (yosys_celltypes.cell_known(type))
2985 return true;
2986 if (module && module->design && module->design->module(type))
2987 return true;
2988 return false;
2989 }
2990
2991 bool RTLIL::Cell::input(RTLIL::IdString portname) const
2992 {
2993 if (yosys_celltypes.cell_known(type))
2994 return yosys_celltypes.cell_input(type, portname);
2995 if (module && module->design) {
2996 RTLIL::Module *m = module->design->module(type);
2997 RTLIL::Wire *w = m ? m->wire(portname) : nullptr;
2998 return w && w->port_input;
2999 }
3000 return false;
3001 }
3002
3003 bool RTLIL::Cell::output(RTLIL::IdString portname) const
3004 {
3005 if (yosys_celltypes.cell_known(type))
3006 return yosys_celltypes.cell_output(type, portname);
3007 if (module && module->design) {
3008 RTLIL::Module *m = module->design->module(type);
3009 RTLIL::Wire *w = m ? m->wire(portname) : nullptr;
3010 return w && w->port_output;
3011 }
3012 return false;
3013 }
3014
3015 bool RTLIL::Cell::hasParam(RTLIL::IdString paramname) const
3016 {
3017 return parameters.count(paramname) != 0;
3018 }
3019
3020 void RTLIL::Cell::unsetParam(RTLIL::IdString paramname)
3021 {
3022 parameters.erase(paramname);
3023 }
3024
3025 void RTLIL::Cell::setParam(RTLIL::IdString paramname, RTLIL::Const value)
3026 {
3027 parameters[paramname] = std::move(value);
3028 }
3029
3030 const RTLIL::Const &RTLIL::Cell::getParam(RTLIL::IdString paramname) const
3031 {
3032 const auto &it = parameters.find(paramname);
3033 if (it != parameters.end())
3034 return it->second;
3035 if (module && module->design) {
3036 RTLIL::Module *m = module->design->module(type);
3037 if (m)
3038 return m->parameter_default_values.at(paramname);
3039 }
3040 throw std::out_of_range("Cell::getParam()");
3041 }
3042
3043 void RTLIL::Cell::sort()
3044 {
3045 connections_.sort(sort_by_id_str());
3046 parameters.sort(sort_by_id_str());
3047 attributes.sort(sort_by_id_str());
3048 }
3049
3050 void RTLIL::Cell::check()
3051 {
3052 #ifndef NDEBUG
3053 InternalCellChecker checker(NULL, this);
3054 checker.check();
3055 #endif
3056 }
3057
3058 void RTLIL::Cell::fixup_parameters(bool set_a_signed, bool set_b_signed)
3059 {
3060 if (!type.begins_with("$") || type.begins_with("$_") || type.begins_with("$paramod") || type.begins_with("$fmcombine") ||
3061 type.begins_with("$verific$") || type.begins_with("$array:") || type.begins_with("$extern:"))
3062 return;
3063
3064 if (type == ID($mux) || type == ID($pmux)) {
3065 parameters[ID::WIDTH] = GetSize(connections_[ID::Y]);
3066 if (type == ID($pmux))
3067 parameters[ID::S_WIDTH] = GetSize(connections_[ID::S]);
3068 check();
3069 return;
3070 }
3071
3072 if (type == ID($lut) || type == ID($sop)) {
3073 parameters[ID::WIDTH] = GetSize(connections_[ID::A]);
3074 return;
3075 }
3076
3077 if (type == ID($fa)) {
3078 parameters[ID::WIDTH] = GetSize(connections_[ID::Y]);
3079 return;
3080 }
3081
3082 if (type == ID($lcu)) {
3083 parameters[ID::WIDTH] = GetSize(connections_[ID::CO]);
3084 return;
3085 }
3086
3087 bool signedness_ab = !type.in(ID($slice), ID($concat), ID($macc));
3088
3089 if (connections_.count(ID::A)) {
3090 if (signedness_ab) {
3091 if (set_a_signed)
3092 parameters[ID::A_SIGNED] = true;
3093 else if (parameters.count(ID::A_SIGNED) == 0)
3094 parameters[ID::A_SIGNED] = false;
3095 }
3096 parameters[ID::A_WIDTH] = GetSize(connections_[ID::A]);
3097 }
3098
3099 if (connections_.count(ID::B)) {
3100 if (signedness_ab) {
3101 if (set_b_signed)
3102 parameters[ID::B_SIGNED] = true;
3103 else if (parameters.count(ID::B_SIGNED) == 0)
3104 parameters[ID::B_SIGNED] = false;
3105 }
3106 parameters[ID::B_WIDTH] = GetSize(connections_[ID::B]);
3107 }
3108
3109 if (connections_.count(ID::Y))
3110 parameters[ID::Y_WIDTH] = GetSize(connections_[ID::Y]);
3111
3112 if (connections_.count(ID::Q))
3113 parameters[ID::WIDTH] = GetSize(connections_[ID::Q]);
3114
3115 check();
3116 }
3117
3118 RTLIL::SigChunk::SigChunk()
3119 {
3120 wire = NULL;
3121 width = 0;
3122 offset = 0;
3123 }
3124
3125 RTLIL::SigChunk::SigChunk(const RTLIL::Const &value)
3126 {
3127 wire = NULL;
3128 data = value.bits;
3129 width = GetSize(data);
3130 offset = 0;
3131 }
3132
3133 RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire)
3134 {
3135 log_assert(wire != nullptr);
3136 this->wire = wire;
3137 this->width = wire->width;
3138 this->offset = 0;
3139 }
3140
3141 RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire, int offset, int width)
3142 {
3143 log_assert(wire != nullptr);
3144 this->wire = wire;
3145 this->width = width;
3146 this->offset = offset;
3147 }
3148
3149 RTLIL::SigChunk::SigChunk(const std::string &str)
3150 {
3151 wire = NULL;
3152 data = RTLIL::Const(str).bits;
3153 width = GetSize(data);
3154 offset = 0;
3155 }
3156
3157 RTLIL::SigChunk::SigChunk(int val, int width)
3158 {
3159 wire = NULL;
3160 data = RTLIL::Const(val, width).bits;
3161 this->width = GetSize(data);
3162 offset = 0;
3163 }
3164
3165 RTLIL::SigChunk::SigChunk(RTLIL::State bit, int width)
3166 {
3167 wire = NULL;
3168 data = RTLIL::Const(bit, width).bits;
3169 this->width = GetSize(data);
3170 offset = 0;
3171 }
3172
3173 RTLIL::SigChunk::SigChunk(const RTLIL::SigBit &bit)
3174 {
3175 wire = bit.wire;
3176 offset = 0;
3177 if (wire == NULL)
3178 data = RTLIL::Const(bit.data).bits;
3179 else
3180 offset = bit.offset;
3181 width = 1;
3182 }
3183
3184 RTLIL::SigChunk::SigChunk(const RTLIL::SigChunk &sigchunk)
3185 {
3186 *this = sigchunk;
3187 }
3188
3189 RTLIL::SigChunk RTLIL::SigChunk::extract(int offset, int length) const
3190 {
3191 RTLIL::SigChunk ret;
3192 if (wire) {
3193 ret.wire = wire;
3194 ret.offset = this->offset + offset;
3195 ret.width = length;
3196 } else {
3197 for (int i = 0; i < length; i++)
3198 ret.data.push_back(data[offset+i]);
3199 ret.width = length;
3200 }
3201 return ret;
3202 }
3203
3204 bool RTLIL::SigChunk::operator <(const RTLIL::SigChunk &other) const
3205 {
3206 if (wire && other.wire)
3207 if (wire->name != other.wire->name)
3208 return wire->name < other.wire->name;
3209
3210 if (wire != other.wire)
3211 return wire < other.wire;
3212
3213 if (offset != other.offset)
3214 return offset < other.offset;
3215
3216 if (width != other.width)
3217 return width < other.width;
3218
3219 return data < other.data;
3220 }
3221
3222 bool RTLIL::SigChunk::operator ==(const RTLIL::SigChunk &other) const
3223 {
3224 return wire == other.wire && width == other.width && offset == other.offset && data == other.data;
3225 }
3226
3227 bool RTLIL::SigChunk::operator !=(const RTLIL::SigChunk &other) const
3228 {
3229 if (*this == other)
3230 return false;
3231 return true;
3232 }
3233
3234 RTLIL::SigSpec::SigSpec()
3235 {
3236 width_ = 0;
3237 hash_ = 0;
3238 }
3239
3240 RTLIL::SigSpec::SigSpec(const RTLIL::SigSpec &other)
3241 {
3242 *this = other;
3243 }
3244
3245 RTLIL::SigSpec::SigSpec(std::initializer_list<RTLIL::SigSpec> parts)
3246 {
3247 cover("kernel.rtlil.sigspec.init.list");
3248
3249 width_ = 0;
3250 hash_ = 0;
3251
3252 log_assert(parts.size() > 0);
3253 auto ie = parts.begin();
3254 auto it = ie + parts.size() - 1;
3255 while (it >= ie)
3256 append(*it--);
3257 }
3258
3259 RTLIL::SigSpec &RTLIL::SigSpec::operator=(const RTLIL::SigSpec &other)
3260 {
3261 cover("kernel.rtlil.sigspec.assign");
3262
3263 width_ = other.width_;
3264 hash_ = other.hash_;
3265 chunks_ = other.chunks_;
3266 bits_ = other.bits_;
3267 return *this;
3268 }
3269
3270 RTLIL::SigSpec::SigSpec(const RTLIL::Const &value)
3271 {
3272 cover("kernel.rtlil.sigspec.init.const");
3273
3274 chunks_.emplace_back(value);
3275 width_ = chunks_.back().width;
3276 hash_ = 0;
3277 check();
3278 }
3279
3280 RTLIL::SigSpec::SigSpec(const RTLIL::SigChunk &chunk)
3281 {
3282 cover("kernel.rtlil.sigspec.init.chunk");
3283
3284 chunks_.emplace_back(chunk);
3285 width_ = chunks_.back().width;
3286 hash_ = 0;
3287 check();
3288 }
3289
3290 RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire)
3291 {
3292 cover("kernel.rtlil.sigspec.init.wire");
3293
3294 chunks_.emplace_back(wire);
3295 width_ = chunks_.back().width;
3296 hash_ = 0;
3297 check();
3298 }
3299
3300 RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire, int offset, int width)
3301 {
3302 cover("kernel.rtlil.sigspec.init.wire_part");
3303
3304 chunks_.emplace_back(wire, offset, width);
3305 width_ = chunks_.back().width;
3306 hash_ = 0;
3307 check();
3308 }
3309
3310 RTLIL::SigSpec::SigSpec(const std::string &str)
3311 {
3312 cover("kernel.rtlil.sigspec.init.str");
3313
3314 chunks_.emplace_back(str);
3315 width_ = chunks_.back().width;
3316 hash_ = 0;
3317 check();
3318 }
3319
3320 RTLIL::SigSpec::SigSpec(int val, int width)
3321 {
3322 cover("kernel.rtlil.sigspec.init.int");
3323
3324 chunks_.emplace_back(val, width);
3325 width_ = width;
3326 hash_ = 0;
3327 check();
3328 }
3329
3330 RTLIL::SigSpec::SigSpec(RTLIL::State bit, int width)
3331 {
3332 cover("kernel.rtlil.sigspec.init.state");
3333
3334 chunks_.emplace_back(bit, width);
3335 width_ = width;
3336 hash_ = 0;
3337 check();
3338 }
3339
3340 RTLIL::SigSpec::SigSpec(const RTLIL::SigBit &bit, int width)
3341 {
3342 cover("kernel.rtlil.sigspec.init.bit");
3343
3344 if (bit.wire == NULL)
3345 chunks_.emplace_back(bit.data, width);
3346 else
3347 for (int i = 0; i < width; i++)
3348 chunks_.push_back(bit);
3349 width_ = width;
3350 hash_ = 0;
3351 check();
3352 }
3353
3354 RTLIL::SigSpec::SigSpec(const std::vector<RTLIL::SigChunk> &chunks)
3355 {
3356 cover("kernel.rtlil.sigspec.init.stdvec_chunks");
3357
3358 width_ = 0;
3359 hash_ = 0;
3360 for (const auto &c : chunks)
3361 append(c);
3362 check();
3363 }
3364
3365 RTLIL::SigSpec::SigSpec(const std::vector<RTLIL::SigBit> &bits)
3366 {
3367 cover("kernel.rtlil.sigspec.init.stdvec_bits");
3368
3369 width_ = 0;
3370 hash_ = 0;
3371 for (const auto &bit : bits)
3372 append(bit);
3373 check();
3374 }
3375
3376 RTLIL::SigSpec::SigSpec(const pool<RTLIL::SigBit> &bits)
3377 {
3378 cover("kernel.rtlil.sigspec.init.pool_bits");
3379
3380 width_ = 0;
3381 hash_ = 0;
3382 for (const auto &bit : bits)
3383 append(bit);
3384 check();
3385 }
3386
3387 RTLIL::SigSpec::SigSpec(const std::set<RTLIL::SigBit> &bits)
3388 {
3389 cover("kernel.rtlil.sigspec.init.stdset_bits");
3390
3391 width_ = 0;
3392 hash_ = 0;
3393 for (const auto &bit : bits)
3394 append(bit);
3395 check();
3396 }
3397
3398 RTLIL::SigSpec::SigSpec(bool bit)
3399 {
3400 cover("kernel.rtlil.sigspec.init.bool");
3401
3402 width_ = 0;
3403 hash_ = 0;
3404 append(SigBit(bit));
3405 check();
3406 }
3407
3408 void RTLIL::SigSpec::pack() const
3409 {
3410 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
3411
3412 if (that->bits_.empty())
3413 return;
3414
3415 cover("kernel.rtlil.sigspec.convert.pack");
3416 log_assert(that->chunks_.empty());
3417
3418 std::vector<RTLIL::SigBit> old_bits;
3419 old_bits.swap(that->bits_);
3420
3421 RTLIL::SigChunk *last = NULL;
3422 int last_end_offset = 0;
3423
3424 for (auto &bit : old_bits) {
3425 if (last && bit.wire == last->wire) {
3426 if (bit.wire == NULL) {
3427 last->data.push_back(bit.data);
3428 last->width++;
3429 continue;
3430 } else if (last_end_offset == bit.offset) {
3431 last_end_offset++;
3432 last->width++;
3433 continue;
3434 }
3435 }
3436 that->chunks_.push_back(bit);
3437 last = &that->chunks_.back();
3438 last_end_offset = bit.offset + 1;
3439 }
3440
3441 check();
3442 }
3443
3444 void RTLIL::SigSpec::unpack() const
3445 {
3446 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
3447
3448 if (that->chunks_.empty())
3449 return;
3450
3451 cover("kernel.rtlil.sigspec.convert.unpack");
3452 log_assert(that->bits_.empty());
3453
3454 that->bits_.reserve(that->width_);
3455 for (auto &c : that->chunks_)
3456 for (int i = 0; i < c.width; i++)
3457 that->bits_.emplace_back(c, i);
3458
3459 that->chunks_.clear();
3460 that->hash_ = 0;
3461 }
3462
3463 void RTLIL::SigSpec::updhash() const
3464 {
3465 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
3466
3467 if (that->hash_ != 0)
3468 return;
3469
3470 cover("kernel.rtlil.sigspec.hash");
3471 that->pack();
3472
3473 that->hash_ = mkhash_init;
3474 for (auto &c : that->chunks_)
3475 if (c.wire == NULL) {
3476 for (auto &v : c.data)
3477 that->hash_ = mkhash(that->hash_, v);
3478 } else {
3479 that->hash_ = mkhash(that->hash_, c.wire->name.index_);
3480 that->hash_ = mkhash(that->hash_, c.offset);
3481 that->hash_ = mkhash(that->hash_, c.width);
3482 }
3483
3484 if (that->hash_ == 0)
3485 that->hash_ = 1;
3486 }
3487
3488 void RTLIL::SigSpec::sort()
3489 {
3490 unpack();
3491 cover("kernel.rtlil.sigspec.sort");
3492 std::sort(bits_.begin(), bits_.end());
3493 }
3494
3495 void RTLIL::SigSpec::sort_and_unify()
3496 {
3497 unpack();
3498 cover("kernel.rtlil.sigspec.sort_and_unify");
3499
3500 // A copy of the bits vector is used to prevent duplicating the logic from
3501 // SigSpec::SigSpec(std::vector<SigBit>). This incurrs an extra copy but
3502 // that isn't showing up as significant in profiles.
3503 std::vector<SigBit> unique_bits = bits_;
3504 std::sort(unique_bits.begin(), unique_bits.end());
3505 auto last = std::unique(unique_bits.begin(), unique_bits.end());
3506 unique_bits.erase(last, unique_bits.end());
3507
3508 *this = unique_bits;
3509 }
3510
3511 void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with)
3512 {
3513 replace(pattern, with, this);
3514 }
3515
3516 void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with, RTLIL::SigSpec *other) const
3517 {
3518 log_assert(other != NULL);
3519 log_assert(width_ == other->width_);
3520 log_assert(pattern.width_ == with.width_);
3521
3522 pattern.unpack();
3523 with.unpack();
3524 unpack();
3525 other->unpack();
3526
3527 for (int i = 0; i < GetSize(pattern.bits_); i++) {
3528 if (pattern.bits_[i].wire != NULL) {
3529 for (int j = 0; j < GetSize(bits_); j++) {
3530 if (bits_[j] == pattern.bits_[i]) {
3531 other->bits_[j] = with.bits_[i];
3532 }
3533 }
3534 }
3535 }
3536
3537 other->check();
3538 }
3539
3540 void RTLIL::SigSpec::replace(const dict<RTLIL::SigBit, RTLIL::SigBit> &rules)
3541 {
3542 replace(rules, this);
3543 }
3544
3545 void RTLIL::SigSpec::replace(const dict<RTLIL::SigBit, RTLIL::SigBit> &rules, RTLIL::SigSpec *other) const
3546 {
3547 cover("kernel.rtlil.sigspec.replace_dict");
3548
3549 log_assert(other != NULL);
3550 log_assert(width_ == other->width_);
3551
3552 if (rules.empty()) return;
3553 unpack();
3554 other->unpack();
3555
3556 for (int i = 0; i < GetSize(bits_); i++) {
3557 auto it = rules.find(bits_[i]);
3558 if (it != rules.end())
3559 other->bits_[i] = it->second;
3560 }
3561
3562 other->check();
3563 }
3564
3565 void RTLIL::SigSpec::replace(const std::map<RTLIL::SigBit, RTLIL::SigBit> &rules)
3566 {
3567 replace(rules, this);
3568 }
3569
3570 void RTLIL::SigSpec::replace(const std::map<RTLIL::SigBit, RTLIL::SigBit> &rules, RTLIL::SigSpec *other) const
3571 {
3572 cover("kernel.rtlil.sigspec.replace_map");
3573
3574 log_assert(other != NULL);
3575 log_assert(width_ == other->width_);
3576
3577 if (rules.empty()) return;
3578 unpack();
3579 other->unpack();
3580
3581 for (int i = 0; i < GetSize(bits_); i++) {
3582 auto it = rules.find(bits_[i]);
3583 if (it != rules.end())
3584 other->bits_[i] = it->second;
3585 }
3586
3587 other->check();
3588 }
3589
3590 void RTLIL::SigSpec::remove(const RTLIL::SigSpec &pattern)
3591 {
3592 remove2(pattern, NULL);
3593 }
3594
3595 void RTLIL::SigSpec::remove(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other) const
3596 {
3597 RTLIL::SigSpec tmp = *this;
3598 tmp.remove2(pattern, other);
3599 }
3600
3601 void RTLIL::SigSpec::remove2(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other)
3602 {
3603 if (other)
3604 cover("kernel.rtlil.sigspec.remove_other");
3605 else
3606 cover("kernel.rtlil.sigspec.remove");
3607
3608 unpack();
3609 if (other != NULL) {
3610 log_assert(width_ == other->width_);
3611 other->unpack();
3612 }
3613
3614 for (int i = GetSize(bits_) - 1; i >= 0; i--)
3615 {
3616 if (bits_[i].wire == NULL) continue;
3617
3618 for (auto &pattern_chunk : pattern.chunks())
3619 if (bits_[i].wire == pattern_chunk.wire &&
3620 bits_[i].offset >= pattern_chunk.offset &&
3621 bits_[i].offset < pattern_chunk.offset + pattern_chunk.width) {
3622 bits_.erase(bits_.begin() + i);
3623 width_--;
3624 if (other != NULL) {
3625 other->bits_.erase(other->bits_.begin() + i);
3626 other->width_--;
3627 }
3628 break;
3629 }
3630 }
3631
3632 check();
3633 }
3634
3635 void RTLIL::SigSpec::remove(const pool<RTLIL::SigBit> &pattern)
3636 {
3637 remove2(pattern, NULL);
3638 }
3639
3640 void RTLIL::SigSpec::remove(const pool<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other) const
3641 {
3642 RTLIL::SigSpec tmp = *this;
3643 tmp.remove2(pattern, other);
3644 }
3645
3646 void RTLIL::SigSpec::remove2(const pool<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other)
3647 {
3648 if (other)
3649 cover("kernel.rtlil.sigspec.remove_other");
3650 else
3651 cover("kernel.rtlil.sigspec.remove");
3652
3653 unpack();
3654
3655 if (other != NULL) {
3656 log_assert(width_ == other->width_);
3657 other->unpack();
3658 }
3659
3660 for (int i = GetSize(bits_) - 1; i >= 0; i--) {
3661 if (bits_[i].wire != NULL && pattern.count(bits_[i])) {
3662 bits_.erase(bits_.begin() + i);
3663 width_--;
3664 if (other != NULL) {
3665 other->bits_.erase(other->bits_.begin() + i);
3666 other->width_--;
3667 }
3668 }
3669 }
3670
3671 check();
3672 }
3673
3674 void RTLIL::SigSpec::remove2(const std::set<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other)
3675 {
3676 if (other)
3677 cover("kernel.rtlil.sigspec.remove_other");
3678 else
3679 cover("kernel.rtlil.sigspec.remove");
3680
3681 unpack();
3682
3683 if (other != NULL) {
3684 log_assert(width_ == other->width_);
3685 other->unpack();
3686 }
3687
3688 for (int i = GetSize(bits_) - 1; i >= 0; i--) {
3689 if (bits_[i].wire != NULL && pattern.count(bits_[i])) {
3690 bits_.erase(bits_.begin() + i);
3691 width_--;
3692 if (other != NULL) {
3693 other->bits_.erase(other->bits_.begin() + i);
3694 other->width_--;
3695 }
3696 }
3697 }
3698
3699 check();
3700 }
3701
3702 RTLIL::SigSpec RTLIL::SigSpec::extract(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec *other) const
3703 {
3704 if (other)
3705 cover("kernel.rtlil.sigspec.extract_other");
3706 else
3707 cover("kernel.rtlil.sigspec.extract");
3708
3709 log_assert(other == NULL || width_ == other->width_);
3710
3711 RTLIL::SigSpec ret;
3712 std::vector<RTLIL::SigBit> bits_match = to_sigbit_vector();
3713
3714 for (auto& pattern_chunk : pattern.chunks()) {
3715 if (other) {
3716 std::vector<RTLIL::SigBit> bits_other = other->to_sigbit_vector();
3717 for (int i = 0; i < width_; i++)
3718 if (bits_match[i].wire &&
3719 bits_match[i].wire == pattern_chunk.wire &&
3720 bits_match[i].offset >= pattern_chunk.offset &&
3721 bits_match[i].offset < pattern_chunk.offset + pattern_chunk.width)
3722 ret.append(bits_other[i]);
3723 } else {
3724 for (int i = 0; i < width_; i++)
3725 if (bits_match[i].wire &&
3726 bits_match[i].wire == pattern_chunk.wire &&
3727 bits_match[i].offset >= pattern_chunk.offset &&
3728 bits_match[i].offset < pattern_chunk.offset + pattern_chunk.width)
3729 ret.append(bits_match[i]);
3730 }
3731 }
3732
3733 ret.check();
3734 return ret;
3735 }
3736
3737 RTLIL::SigSpec RTLIL::SigSpec::extract(const pool<RTLIL::SigBit> &pattern, const RTLIL::SigSpec *other) const
3738 {
3739 if (other)
3740 cover("kernel.rtlil.sigspec.extract_other");
3741 else
3742 cover("kernel.rtlil.sigspec.extract");
3743
3744 log_assert(other == NULL || width_ == other->width_);
3745
3746 std::vector<RTLIL::SigBit> bits_match = to_sigbit_vector();
3747 RTLIL::SigSpec ret;
3748
3749 if (other) {
3750 std::vector<RTLIL::SigBit> bits_other = other->to_sigbit_vector();
3751 for (int i = 0; i < width_; i++)
3752 if (bits_match[i].wire && pattern.count(bits_match[i]))
3753 ret.append(bits_other[i]);
3754 } else {
3755 for (int i = 0; i < width_; i++)
3756 if (bits_match[i].wire && pattern.count(bits_match[i]))
3757 ret.append(bits_match[i]);
3758 }
3759
3760 ret.check();
3761 return ret;
3762 }
3763
3764 void RTLIL::SigSpec::replace(int offset, const RTLIL::SigSpec &with)
3765 {
3766 cover("kernel.rtlil.sigspec.replace_pos");
3767
3768 unpack();
3769 with.unpack();
3770
3771 log_assert(offset >= 0);
3772 log_assert(with.width_ >= 0);
3773 log_assert(offset+with.width_ <= width_);
3774
3775 for (int i = 0; i < with.width_; i++)
3776 bits_.at(offset + i) = with.bits_.at(i);
3777
3778 check();
3779 }
3780
3781 void RTLIL::SigSpec::remove_const()
3782 {
3783 if (packed())
3784 {
3785 cover("kernel.rtlil.sigspec.remove_const.packed");
3786
3787 std::vector<RTLIL::SigChunk> new_chunks;
3788 new_chunks.reserve(GetSize(chunks_));
3789
3790 width_ = 0;
3791 for (auto &chunk : chunks_)
3792 if (chunk.wire != NULL) {
3793 new_chunks.push_back(chunk);
3794 width_ += chunk.width;
3795 }
3796
3797 chunks_.swap(new_chunks);
3798 }
3799 else
3800 {
3801 cover("kernel.rtlil.sigspec.remove_const.unpacked");
3802
3803 std::vector<RTLIL::SigBit> new_bits;
3804 new_bits.reserve(width_);
3805
3806 for (auto &bit : bits_)
3807 if (bit.wire != NULL)
3808 new_bits.push_back(bit);
3809
3810 bits_.swap(new_bits);
3811 width_ = bits_.size();
3812 }
3813
3814 check();
3815 }
3816
3817 void RTLIL::SigSpec::remove(int offset, int length)
3818 {
3819 cover("kernel.rtlil.sigspec.remove_pos");
3820
3821 unpack();
3822
3823 log_assert(offset >= 0);
3824 log_assert(length >= 0);
3825 log_assert(offset + length <= width_);
3826
3827 bits_.erase(bits_.begin() + offset, bits_.begin() + offset + length);
3828 width_ = bits_.size();
3829
3830 check();
3831 }
3832
3833 RTLIL::SigSpec RTLIL::SigSpec::extract(int offset, int length) const
3834 {
3835 unpack();
3836 cover("kernel.rtlil.sigspec.extract_pos");
3837 return std::vector<RTLIL::SigBit>(bits_.begin() + offset, bits_.begin() + offset + length);
3838 }
3839
3840 void RTLIL::SigSpec::append(const RTLIL::SigSpec &signal)
3841 {
3842 if (signal.width_ == 0)
3843 return;
3844
3845 if (width_ == 0) {
3846 *this = signal;
3847 return;
3848 }
3849
3850 cover("kernel.rtlil.sigspec.append");
3851
3852 if (packed() != signal.packed()) {
3853 pack();
3854 signal.pack();
3855 }
3856
3857 if (packed())
3858 for (auto &other_c : signal.chunks_)
3859 {
3860 auto &my_last_c = chunks_.back();
3861 if (my_last_c.wire == NULL && other_c.wire == NULL) {
3862 auto &this_data = my_last_c.data;
3863 auto &other_data = other_c.data;
3864 this_data.insert(this_data.end(), other_data.begin(), other_data.end());
3865 my_last_c.width += other_c.width;
3866 } else
3867 if (my_last_c.wire == other_c.wire && my_last_c.offset + my_last_c.width == other_c.offset) {
3868 my_last_c.width += other_c.width;
3869 } else
3870 chunks_.push_back(other_c);
3871 }
3872 else
3873 bits_.insert(bits_.end(), signal.bits_.begin(), signal.bits_.end());
3874
3875 width_ += signal.width_;
3876 check();
3877 }
3878
3879 void RTLIL::SigSpec::append(const RTLIL::SigBit &bit)
3880 {
3881 if (packed())
3882 {
3883 cover("kernel.rtlil.sigspec.append_bit.packed");
3884
3885 if (chunks_.size() == 0)
3886 chunks_.push_back(bit);
3887 else
3888 if (bit.wire == NULL)
3889 if (chunks_.back().wire == NULL) {
3890 chunks_.back().data.push_back(bit.data);
3891 chunks_.back().width++;
3892 } else
3893 chunks_.push_back(bit);
3894 else
3895 if (chunks_.back().wire == bit.wire && chunks_.back().offset + chunks_.back().width == bit.offset)
3896 chunks_.back().width++;
3897 else
3898 chunks_.push_back(bit);
3899 }
3900 else
3901 {
3902 cover("kernel.rtlil.sigspec.append_bit.unpacked");
3903 bits_.push_back(bit);
3904 }
3905
3906 width_++;
3907 check();
3908 }
3909
3910 void RTLIL::SigSpec::extend_u0(int width, bool is_signed)
3911 {
3912 cover("kernel.rtlil.sigspec.extend_u0");
3913
3914 pack();
3915
3916 if (width_ > width)
3917 remove(width, width_ - width);
3918
3919 if (width_ < width) {
3920 RTLIL::SigBit padding = width_ > 0 ? (*this)[width_ - 1] : RTLIL::State::Sx;
3921 if (!is_signed)
3922 padding = RTLIL::State::S0;
3923 while (width_ < width)
3924 append(padding);
3925 }
3926
3927 }
3928
3929 RTLIL::SigSpec RTLIL::SigSpec::repeat(int num) const
3930 {
3931 cover("kernel.rtlil.sigspec.repeat");
3932
3933 RTLIL::SigSpec sig;
3934 for (int i = 0; i < num; i++)
3935 sig.append(*this);
3936 return sig;
3937 }
3938
3939 #ifndef NDEBUG
3940 void RTLIL::SigSpec::check() const
3941 {
3942 if (width_ > 64)
3943 {
3944 cover("kernel.rtlil.sigspec.check.skip");
3945 }
3946 else if (packed())
3947 {
3948 cover("kernel.rtlil.sigspec.check.packed");
3949
3950 int w = 0;
3951 for (size_t i = 0; i < chunks_.size(); i++) {
3952 const RTLIL::SigChunk &chunk = chunks_[i];
3953 if (chunk.wire == NULL) {
3954 if (i > 0)
3955 log_assert(chunks_[i-1].wire != NULL);
3956 log_assert(chunk.offset == 0);
3957 log_assert(chunk.data.size() == (size_t)chunk.width);
3958 } else {
3959 if (i > 0 && chunks_[i-1].wire == chunk.wire)
3960 log_assert(chunk.offset != chunks_[i-1].offset + chunks_[i-1].width);
3961 log_assert(chunk.offset >= 0);
3962 log_assert(chunk.width >= 0);
3963 log_assert(chunk.offset + chunk.width <= chunk.wire->width);
3964 log_assert(chunk.data.size() == 0);
3965 }
3966 w += chunk.width;
3967 }
3968 log_assert(w == width_);
3969 log_assert(bits_.empty());
3970 }
3971 else
3972 {
3973 cover("kernel.rtlil.sigspec.check.unpacked");
3974
3975 log_assert(width_ == GetSize(bits_));
3976 log_assert(chunks_.empty());
3977 }
3978 }
3979 #endif
3980
3981 bool RTLIL::SigSpec::operator <(const RTLIL::SigSpec &other) const
3982 {
3983 cover("kernel.rtlil.sigspec.comp_lt");
3984
3985 if (this == &other)
3986 return false;
3987
3988 if (width_ != other.width_)
3989 return width_ < other.width_;
3990
3991 pack();
3992 other.pack();
3993
3994 if (chunks_.size() != other.chunks_.size())
3995 return chunks_.size() < other.chunks_.size();
3996
3997 updhash();
3998 other.updhash();
3999
4000 if (hash_ != other.hash_)
4001 return hash_ < other.hash_;
4002
4003 for (size_t i = 0; i < chunks_.size(); i++)
4004 if (chunks_[i] != other.chunks_[i]) {
4005 cover("kernel.rtlil.sigspec.comp_lt.hash_collision");
4006 return chunks_[i] < other.chunks_[i];
4007 }
4008
4009 cover("kernel.rtlil.sigspec.comp_lt.equal");
4010 return false;
4011 }
4012
4013 bool RTLIL::SigSpec::operator ==(const RTLIL::SigSpec &other) const
4014 {
4015 cover("kernel.rtlil.sigspec.comp_eq");
4016
4017 if (this == &other)
4018 return true;
4019
4020 if (width_ != other.width_)
4021 return false;
4022
4023 // Without this, SigSpec() == SigSpec(State::S0, 0) will fail
4024 // since the RHS will contain one SigChunk of width 0 causing
4025 // the size check below to fail
4026 if (width_ == 0)
4027 return true;
4028
4029 pack();
4030 other.pack();
4031
4032 if (chunks_.size() != other.chunks_.size())
4033 return false;
4034
4035 updhash();
4036 other.updhash();
4037
4038 if (hash_ != other.hash_)
4039 return false;
4040
4041 for (size_t i = 0; i < chunks_.size(); i++)
4042 if (chunks_[i] != other.chunks_[i]) {
4043 cover("kernel.rtlil.sigspec.comp_eq.hash_collision");
4044 return false;
4045 }
4046
4047 cover("kernel.rtlil.sigspec.comp_eq.equal");
4048 return true;
4049 }
4050
4051 bool RTLIL::SigSpec::is_wire() const
4052 {
4053 cover("kernel.rtlil.sigspec.is_wire");
4054
4055 pack();
4056 return GetSize(chunks_) == 1 && chunks_[0].wire && chunks_[0].wire->width == width_;
4057 }
4058
4059 bool RTLIL::SigSpec::is_chunk() const
4060 {
4061 cover("kernel.rtlil.sigspec.is_chunk");
4062
4063 pack();
4064 return GetSize(chunks_) == 1;
4065 }
4066
4067 bool RTLIL::SigSpec::is_fully_const() const
4068 {
4069 cover("kernel.rtlil.sigspec.is_fully_const");
4070
4071 pack();
4072 for (auto it = chunks_.begin(); it != chunks_.end(); it++)
4073 if (it->width > 0 && it->wire != NULL)
4074 return false;
4075 return true;
4076 }
4077
4078 bool RTLIL::SigSpec::is_fully_zero() const
4079 {
4080 cover("kernel.rtlil.sigspec.is_fully_zero");
4081
4082 pack();
4083 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
4084 if (it->width > 0 && it->wire != NULL)
4085 return false;
4086 for (size_t i = 0; i < it->data.size(); i++)
4087 if (it->data[i] != RTLIL::State::S0)
4088 return false;
4089 }
4090 return true;
4091 }
4092
4093 bool RTLIL::SigSpec::is_fully_ones() const
4094 {
4095 cover("kernel.rtlil.sigspec.is_fully_ones");
4096
4097 pack();
4098 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
4099 if (it->width > 0 && it->wire != NULL)
4100 return false;
4101 for (size_t i = 0; i < it->data.size(); i++)
4102 if (it->data[i] != RTLIL::State::S1)
4103 return false;
4104 }
4105 return true;
4106 }
4107
4108 bool RTLIL::SigSpec::is_fully_def() const
4109 {
4110 cover("kernel.rtlil.sigspec.is_fully_def");
4111
4112 pack();
4113 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
4114 if (it->width > 0 && it->wire != NULL)
4115 return false;
4116 for (size_t i = 0; i < it->data.size(); i++)
4117 if (it->data[i] != RTLIL::State::S0 && it->data[i] != RTLIL::State::S1)
4118 return false;
4119 }
4120 return true;
4121 }
4122
4123 bool RTLIL::SigSpec::is_fully_undef() const
4124 {
4125 cover("kernel.rtlil.sigspec.is_fully_undef");
4126
4127 pack();
4128 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
4129 if (it->width > 0 && it->wire != NULL)
4130 return false;
4131 for (size_t i = 0; i < it->data.size(); i++)
4132 if (it->data[i] != RTLIL::State::Sx && it->data[i] != RTLIL::State::Sz)
4133 return false;
4134 }
4135 return true;
4136 }
4137
4138 bool RTLIL::SigSpec::has_const() const
4139 {
4140 cover("kernel.rtlil.sigspec.has_const");
4141
4142 pack();
4143 for (auto it = chunks_.begin(); it != chunks_.end(); it++)
4144 if (it->width > 0 && it->wire == NULL)
4145 return true;
4146 return false;
4147 }
4148
4149 bool RTLIL::SigSpec::has_marked_bits() const
4150 {
4151 cover("kernel.rtlil.sigspec.has_marked_bits");
4152
4153 pack();
4154 for (auto it = chunks_.begin(); it != chunks_.end(); it++)
4155 if (it->width > 0 && it->wire == NULL) {
4156 for (size_t i = 0; i < it->data.size(); i++)
4157 if (it->data[i] == RTLIL::State::Sm)
4158 return true;
4159 }
4160 return false;
4161 }
4162
4163 bool RTLIL::SigSpec::as_bool() const
4164 {
4165 cover("kernel.rtlil.sigspec.as_bool");
4166
4167 pack();
4168 log_assert(is_fully_const() && GetSize(chunks_) <= 1);
4169 if (width_)
4170 return RTLIL::Const(chunks_[0].data).as_bool();
4171 return false;
4172 }
4173
4174 int RTLIL::SigSpec::as_int(bool is_signed) const
4175 {
4176 cover("kernel.rtlil.sigspec.as_int");
4177
4178 pack();
4179 log_assert(is_fully_const() && GetSize(chunks_) <= 1);
4180 if (width_)
4181 return RTLIL::Const(chunks_[0].data).as_int(is_signed);
4182 return 0;
4183 }
4184
4185 std::string RTLIL::SigSpec::as_string() const
4186 {
4187 cover("kernel.rtlil.sigspec.as_string");
4188
4189 pack();
4190 std::string str;
4191 str.reserve(size());
4192 for (size_t i = chunks_.size(); i > 0; i--) {
4193 const RTLIL::SigChunk &chunk = chunks_[i-1];
4194 if (chunk.wire != NULL)
4195 str.append(chunk.width, '?');
4196 else
4197 str += RTLIL::Const(chunk.data).as_string();
4198 }
4199 return str;
4200 }
4201
4202 RTLIL::Const RTLIL::SigSpec::as_const() const
4203 {
4204 cover("kernel.rtlil.sigspec.as_const");
4205
4206 pack();
4207 log_assert(is_fully_const() && GetSize(chunks_) <= 1);
4208 if (width_)
4209 return chunks_[0].data;
4210 return RTLIL::Const();
4211 }
4212
4213 RTLIL::Wire *RTLIL::SigSpec::as_wire() const
4214 {
4215 cover("kernel.rtlil.sigspec.as_wire");
4216
4217 pack();
4218 log_assert(is_wire());
4219 return chunks_[0].wire;
4220 }
4221
4222 RTLIL::SigChunk RTLIL::SigSpec::as_chunk() const
4223 {
4224 cover("kernel.rtlil.sigspec.as_chunk");
4225
4226 pack();
4227 log_assert(is_chunk());
4228 return chunks_[0];
4229 }
4230
4231 RTLIL::SigBit RTLIL::SigSpec::as_bit() const
4232 {
4233 cover("kernel.rtlil.sigspec.as_bit");
4234
4235 log_assert(width_ == 1);
4236 if (packed())
4237 return RTLIL::SigBit(*chunks_.begin());
4238 else
4239 return bits_[0];
4240 }
4241
4242 bool RTLIL::SigSpec::match(const char* pattern) const
4243 {
4244 cover("kernel.rtlil.sigspec.match");
4245
4246 unpack();
4247 log_assert(int(strlen(pattern)) == GetSize(bits_));
4248
4249 for (auto it = bits_.rbegin(); it != bits_.rend(); it++, pattern++) {
4250 if (*pattern == ' ')
4251 continue;
4252 if (*pattern == '*') {
4253 if (*it != State::Sz && *it != State::Sx)
4254 return false;
4255 continue;
4256 }
4257 if (*pattern == '0') {
4258 if (*it != State::S0)
4259 return false;
4260 } else
4261 if (*pattern == '1') {
4262 if (*it != State::S1)
4263 return false;
4264 } else
4265 log_abort();
4266 }
4267
4268 return true;
4269 }
4270
4271 std::set<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_set() const
4272 {
4273 cover("kernel.rtlil.sigspec.to_sigbit_set");
4274
4275 pack();
4276 std::set<RTLIL::SigBit> sigbits;
4277 for (auto &c : chunks_)
4278 for (int i = 0; i < c.width; i++)
4279 sigbits.insert(RTLIL::SigBit(c, i));
4280 return sigbits;
4281 }
4282
4283 pool<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_pool() const
4284 {
4285 cover("kernel.rtlil.sigspec.to_sigbit_pool");
4286
4287 pack();
4288 pool<RTLIL::SigBit> sigbits;
4289 sigbits.reserve(size());
4290 for (auto &c : chunks_)
4291 for (int i = 0; i < c.width; i++)
4292 sigbits.insert(RTLIL::SigBit(c, i));
4293 return sigbits;
4294 }
4295
4296 std::vector<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_vector() const
4297 {
4298 cover("kernel.rtlil.sigspec.to_sigbit_vector");
4299
4300 unpack();
4301 return bits_;
4302 }
4303
4304 std::map<RTLIL::SigBit, RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_map(const RTLIL::SigSpec &other) const
4305 {
4306 cover("kernel.rtlil.sigspec.to_sigbit_map");
4307
4308 unpack();
4309 other.unpack();
4310
4311 log_assert(width_ == other.width_);
4312
4313 std::map<RTLIL::SigBit, RTLIL::SigBit> new_map;
4314 for (int i = 0; i < width_; i++)
4315 new_map[bits_[i]] = other.bits_[i];
4316
4317 return new_map;
4318 }
4319
4320 dict<RTLIL::SigBit, RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_dict(const RTLIL::SigSpec &other) const
4321 {
4322 cover("kernel.rtlil.sigspec.to_sigbit_dict");
4323
4324 unpack();
4325 other.unpack();
4326
4327 log_assert(width_ == other.width_);
4328
4329 dict<RTLIL::SigBit, RTLIL::SigBit> new_map;
4330 new_map.reserve(size());
4331 for (int i = 0; i < width_; i++)
4332 new_map[bits_[i]] = other.bits_[i];
4333
4334 return new_map;
4335 }
4336
4337 static void sigspec_parse_split(std::vector<std::string> &tokens, const std::string &text, char sep)
4338 {
4339 size_t start = 0, end = 0;
4340 while ((end = text.find(sep, start)) != std::string::npos) {
4341 tokens.push_back(text.substr(start, end - start));
4342 start = end + 1;
4343 }
4344 tokens.push_back(text.substr(start));
4345 }
4346
4347 static int sigspec_parse_get_dummy_line_num()
4348 {
4349 return 0;
4350 }
4351
4352 bool RTLIL::SigSpec::parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str)
4353 {
4354 cover("kernel.rtlil.sigspec.parse");
4355
4356 AST::current_filename = "input";
4357
4358 std::vector<std::string> tokens;
4359 sigspec_parse_split(tokens, str, ',');
4360
4361 sig = RTLIL::SigSpec();
4362 for (int tokidx = int(tokens.size())-1; tokidx >= 0; tokidx--)
4363 {
4364 std::string netname = tokens[tokidx];
4365 std::string indices;
4366
4367 if (netname.size() == 0)
4368 continue;
4369
4370 if (('0' <= netname[0] && netname[0] <= '9') || netname[0] == '\'') {
4371 cover("kernel.rtlil.sigspec.parse.const");
4372 AST::get_line_num = sigspec_parse_get_dummy_line_num;
4373 AST::AstNode *ast = VERILOG_FRONTEND::const2ast(netname);
4374 if (ast == NULL)
4375 return false;
4376 sig.append(RTLIL::Const(ast->bits));
4377 delete ast;
4378 continue;
4379 }
4380
4381 if (module == NULL)
4382 return false;
4383
4384 cover("kernel.rtlil.sigspec.parse.net");
4385
4386 if (netname[0] != '$' && netname[0] != '\\')
4387 netname = "\\" + netname;
4388
4389 if (module->wires_.count(netname) == 0) {
4390 size_t indices_pos = netname.size()-1;
4391 if (indices_pos > 2 && netname[indices_pos] == ']')
4392 {
4393 indices_pos--;
4394 while (indices_pos > 0 && ('0' <= netname[indices_pos] && netname[indices_pos] <= '9')) indices_pos--;
4395 if (indices_pos > 0 && netname[indices_pos] == ':') {
4396 indices_pos--;
4397 while (indices_pos > 0 && ('0' <= netname[indices_pos] && netname[indices_pos] <= '9')) indices_pos--;
4398 }
4399 if (indices_pos > 0 && netname[indices_pos] == '[') {
4400 indices = netname.substr(indices_pos);
4401 netname = netname.substr(0, indices_pos);
4402 }
4403 }
4404 }
4405
4406 if (module->wires_.count(netname) == 0)
4407 return false;
4408
4409 RTLIL::Wire *wire = module->wires_.at(netname);
4410 if (!indices.empty()) {
4411 std::vector<std::string> index_tokens;
4412 sigspec_parse_split(index_tokens, indices.substr(1, indices.size()-2), ':');
4413 if (index_tokens.size() == 1) {
4414 cover("kernel.rtlil.sigspec.parse.bit_sel");
4415 int a = atoi(index_tokens.at(0).c_str());
4416 if (a < 0 || a >= wire->width)
4417 return false;
4418 sig.append(RTLIL::SigSpec(wire, a));
4419 } else {
4420 cover("kernel.rtlil.sigspec.parse.part_sel");
4421 int a = atoi(index_tokens.at(0).c_str());
4422 int b = atoi(index_tokens.at(1).c_str());
4423 if (a > b) {
4424 int tmp = a;
4425 a = b, b = tmp;
4426 }
4427 if (a < 0 || a >= wire->width)
4428 return false;
4429 if (b < 0 || b >= wire->width)
4430 return false;
4431 sig.append(RTLIL::SigSpec(wire, a, b-a+1));
4432 }
4433 } else
4434 sig.append(wire);
4435 }
4436
4437 return true;
4438 }
4439
4440 bool RTLIL::SigSpec::parse_sel(RTLIL::SigSpec &sig, RTLIL::Design *design, RTLIL::Module *module, std::string str)
4441 {
4442 if (str.empty() || str[0] != '@')
4443 return parse(sig, module, str);
4444
4445 cover("kernel.rtlil.sigspec.parse.sel");
4446
4447 str = RTLIL::escape_id(str.substr(1));
4448 if (design->selection_vars.count(str) == 0)
4449 return false;
4450
4451 sig = RTLIL::SigSpec();
4452 RTLIL::Selection &sel = design->selection_vars.at(str);
4453 for (auto &it : module->wires_)
4454 if (sel.selected_member(module->name, it.first))
4455 sig.append(it.second);
4456
4457 return true;
4458 }
4459
4460 bool RTLIL::SigSpec::parse_rhs(const RTLIL::SigSpec &lhs, RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str)
4461 {
4462 if (str == "0") {
4463 cover("kernel.rtlil.sigspec.parse.rhs_zeros");
4464 sig = RTLIL::SigSpec(RTLIL::State::S0, lhs.width_);
4465 return true;
4466 }
4467
4468 if (str == "~0") {
4469 cover("kernel.rtlil.sigspec.parse.rhs_ones");
4470 sig = RTLIL::SigSpec(RTLIL::State::S1, lhs.width_);
4471 return true;
4472 }
4473
4474 if (lhs.chunks_.size() == 1) {
4475 char *p = (char*)str.c_str(), *endptr;
4476 long int val = strtol(p, &endptr, 10);
4477 if (endptr && endptr != p && *endptr == 0) {
4478 sig = RTLIL::SigSpec(val, lhs.width_);
4479 cover("kernel.rtlil.sigspec.parse.rhs_dec");
4480 return true;
4481 }
4482 }
4483
4484 return parse(sig, module, str);
4485 }
4486
4487 RTLIL::CaseRule::~CaseRule()
4488 {
4489 for (auto it = switches.begin(); it != switches.end(); it++)
4490 delete *it;
4491 }
4492
4493 bool RTLIL::CaseRule::empty() const
4494 {
4495 return actions.empty() && switches.empty();
4496 }
4497
4498 RTLIL::CaseRule *RTLIL::CaseRule::clone() const
4499 {
4500 RTLIL::CaseRule *new_caserule = new RTLIL::CaseRule;
4501 new_caserule->compare = compare;
4502 new_caserule->actions = actions;
4503 for (auto &it : switches)
4504 new_caserule->switches.push_back(it->clone());
4505 return new_caserule;
4506 }
4507
4508 RTLIL::SwitchRule::~SwitchRule()
4509 {
4510 for (auto it = cases.begin(); it != cases.end(); it++)
4511 delete *it;
4512 }
4513
4514 bool RTLIL::SwitchRule::empty() const
4515 {
4516 return cases.empty();
4517 }
4518
4519 RTLIL::SwitchRule *RTLIL::SwitchRule::clone() const
4520 {
4521 RTLIL::SwitchRule *new_switchrule = new RTLIL::SwitchRule;
4522 new_switchrule->signal = signal;
4523 new_switchrule->attributes = attributes;
4524 for (auto &it : cases)
4525 new_switchrule->cases.push_back(it->clone());
4526 return new_switchrule;
4527
4528 }
4529
4530 RTLIL::SyncRule *RTLIL::SyncRule::clone() const
4531 {
4532 RTLIL::SyncRule *new_syncrule = new RTLIL::SyncRule;
4533 new_syncrule->type = type;
4534 new_syncrule->signal = signal;
4535 new_syncrule->actions = actions;
4536 return new_syncrule;
4537 }
4538
4539 RTLIL::Process::~Process()
4540 {
4541 for (auto it = syncs.begin(); it != syncs.end(); it++)
4542 delete *it;
4543 }
4544
4545 RTLIL::Process *RTLIL::Process::clone() const
4546 {
4547 RTLIL::Process *new_proc = new RTLIL::Process;
4548
4549 new_proc->name = name;
4550 new_proc->attributes = attributes;
4551
4552 RTLIL::CaseRule *rc_ptr = root_case.clone();
4553 new_proc->root_case = *rc_ptr;
4554 rc_ptr->switches.clear();
4555 delete rc_ptr;
4556
4557 for (auto &it : syncs)
4558 new_proc->syncs.push_back(it->clone());
4559
4560 return new_proc;
4561 }
4562
4563 #ifdef WITH_PYTHON
4564 RTLIL::Memory::~Memory()
4565 {
4566 RTLIL::Memory::get_all_memorys()->erase(hashidx_);
4567 }
4568 static std::map<unsigned int, RTLIL::Memory*> all_memorys;
4569 std::map<unsigned int, RTLIL::Memory*> *RTLIL::Memory::get_all_memorys(void)
4570 {
4571 return &all_memorys;
4572 }
4573 #endif
4574 YOSYS_NAMESPACE_END