2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include "kernel/yosys.h"
21 #include "kernel/macc.h"
22 #include "kernel/celltypes.h"
23 #include "frontends/verilog/verilog_frontend.h"
24 #include "frontends/verilog/preproc.h"
25 #include "backends/ilang/ilang_backend.h"
32 RTLIL::IdString::destruct_guard_t
RTLIL::IdString::destruct_guard
;
33 std::vector
<char*> RTLIL::IdString::global_id_storage_
;
34 dict
<char*, int, hash_cstr_ops
> RTLIL::IdString::global_id_index_
;
35 #ifndef YOSYS_NO_IDS_REFCNT
36 std::vector
<int> RTLIL::IdString::global_refcount_storage_
;
37 std::vector
<int> RTLIL::IdString::global_free_idx_list_
;
39 #ifdef YOSYS_USE_STICKY_IDS
40 int RTLIL::IdString::last_created_idx_
[8];
41 int RTLIL::IdString::last_created_idx_ptr_
;
44 #define X(_id) IdString RTLIL::ID::_id;
45 #include "kernel/constids.inc"
48 dict
<std::string
, std::string
> RTLIL::constpad
;
50 const pool
<IdString
> &RTLIL::builtin_ff_cell_types() {
51 static const pool
<IdString
> res
= {
187 RTLIL::Const::Const()
189 flags
= RTLIL::CONST_FLAG_NONE
;
192 RTLIL::Const::Const(std::string str
)
194 flags
= RTLIL::CONST_FLAG_STRING
;
195 for (int i
= str
.size()-1; i
>= 0; i
--) {
196 unsigned char ch
= str
[i
];
197 for (int j
= 0; j
< 8; j
++) {
198 bits
.push_back((ch
& 1) != 0 ? State::S1
: State::S0
);
204 RTLIL::Const::Const(int val
, int width
)
206 flags
= RTLIL::CONST_FLAG_NONE
;
207 for (int i
= 0; i
< width
; i
++) {
208 bits
.push_back((val
& 1) != 0 ? State::S1
: State::S0
);
213 RTLIL::Const::Const(RTLIL::State bit
, int width
)
215 flags
= RTLIL::CONST_FLAG_NONE
;
216 for (int i
= 0; i
< width
; i
++)
220 RTLIL::Const::Const(const std::vector
<bool> &bits
)
222 flags
= RTLIL::CONST_FLAG_NONE
;
223 for (const auto &b
: bits
)
224 this->bits
.emplace_back(b
? State::S1
: State::S0
);
227 RTLIL::Const::Const(const RTLIL::Const
&c
)
230 for (const auto &b
: c
.bits
)
231 this->bits
.push_back(b
);
234 bool RTLIL::Const::operator <(const RTLIL::Const
&other
) const
236 if (bits
.size() != other
.bits
.size())
237 return bits
.size() < other
.bits
.size();
238 for (size_t i
= 0; i
< bits
.size(); i
++)
239 if (bits
[i
] != other
.bits
[i
])
240 return bits
[i
] < other
.bits
[i
];
244 bool RTLIL::Const::operator ==(const RTLIL::Const
&other
) const
246 return bits
== other
.bits
;
249 bool RTLIL::Const::operator !=(const RTLIL::Const
&other
) const
251 return bits
!= other
.bits
;
254 bool RTLIL::Const::as_bool() const
256 for (size_t i
= 0; i
< bits
.size(); i
++)
257 if (bits
[i
] == State::S1
)
262 int RTLIL::Const::as_int(bool is_signed
) const
265 for (size_t i
= 0; i
< bits
.size() && i
< 32; i
++)
266 if (bits
[i
] == State::S1
)
268 if (is_signed
&& bits
.back() == State::S1
)
269 for (size_t i
= bits
.size(); i
< 32; i
++)
274 std::string
RTLIL::Const::as_string() const
277 ret
.reserve(bits
.size());
278 for (size_t i
= bits
.size(); i
> 0; i
--)
280 case S0
: ret
+= "0"; break;
281 case S1
: ret
+= "1"; break;
282 case Sx
: ret
+= "x"; break;
283 case Sz
: ret
+= "z"; break;
284 case Sa
: ret
+= "-"; break;
285 case Sm
: ret
+= "m"; break;
290 RTLIL::Const
RTLIL::Const::from_string(const std::string
&str
)
293 c
.bits
.reserve(str
.size());
294 for (auto it
= str
.rbegin(); it
!= str
.rend(); it
++)
296 case '0': c
.bits
.push_back(State::S0
); break;
297 case '1': c
.bits
.push_back(State::S1
); break;
298 case 'x': c
.bits
.push_back(State::Sx
); break;
299 case 'z': c
.bits
.push_back(State::Sz
); break;
300 case 'm': c
.bits
.push_back(State::Sm
); break;
301 default: c
.bits
.push_back(State::Sa
);
306 std::string
RTLIL::Const::decode_string() const
309 string
.reserve(GetSize(bits
)/8);
310 for (int i
= 0; i
< GetSize(bits
); i
+= 8) {
312 for (int j
= 0; j
< 8 && i
+ j
< int (bits
.size()); j
++)
313 if (bits
[i
+ j
] == RTLIL::State::S1
)
318 std::reverse(string
.begin(), string
.end());
322 bool RTLIL::Const::is_fully_zero() const
324 cover("kernel.rtlil.const.is_fully_zero");
326 for (const auto &bit
: bits
)
327 if (bit
!= RTLIL::State::S0
)
333 bool RTLIL::Const::is_fully_ones() const
335 cover("kernel.rtlil.const.is_fully_ones");
337 for (const auto &bit
: bits
)
338 if (bit
!= RTLIL::State::S1
)
344 bool RTLIL::Const::is_fully_def() const
346 cover("kernel.rtlil.const.is_fully_def");
348 for (const auto &bit
: bits
)
349 if (bit
!= RTLIL::State::S0
&& bit
!= RTLIL::State::S1
)
355 bool RTLIL::Const::is_fully_undef() const
357 cover("kernel.rtlil.const.is_fully_undef");
359 for (const auto &bit
: bits
)
360 if (bit
!= RTLIL::State::Sx
&& bit
!= RTLIL::State::Sz
)
366 bool RTLIL::AttrObject::has_attribute(RTLIL::IdString id
) const
368 return attributes
.count(id
);
371 void RTLIL::AttrObject::set_bool_attribute(RTLIL::IdString id
, bool value
)
374 attributes
[id
] = RTLIL::Const(1);
376 attributes
.erase(id
);
379 bool RTLIL::AttrObject::get_bool_attribute(RTLIL::IdString id
) const
381 const auto it
= attributes
.find(id
);
382 if (it
== attributes
.end())
384 return it
->second
.as_bool();
387 void RTLIL::AttrObject::set_string_attribute(RTLIL::IdString id
, string value
)
390 attributes
.erase(id
);
392 attributes
[id
] = value
;
395 string
RTLIL::AttrObject::get_string_attribute(RTLIL::IdString id
) const
398 const auto it
= attributes
.find(id
);
399 if (it
!= attributes
.end())
400 value
= it
->second
.decode_string();
404 void RTLIL::AttrObject::set_strpool_attribute(RTLIL::IdString id
, const pool
<string
> &data
)
407 for (const auto &s
: data
) {
408 if (!attrval
.empty())
412 set_string_attribute(id
, attrval
);
415 void RTLIL::AttrObject::add_strpool_attribute(RTLIL::IdString id
, const pool
<string
> &data
)
417 pool
<string
> union_data
= get_strpool_attribute(id
);
418 union_data
.insert(data
.begin(), data
.end());
419 if (!union_data
.empty())
420 set_strpool_attribute(id
, union_data
);
423 pool
<string
> RTLIL::AttrObject::get_strpool_attribute(RTLIL::IdString id
) const
426 if (attributes
.count(id
) != 0)
427 for (auto s
: split_tokens(get_string_attribute(id
), "|"))
432 void RTLIL::AttrObject::set_hdlname_attribute(const vector
<string
> &hierarchy
)
435 for (const auto &ident
: hierarchy
) {
436 if (!attrval
.empty())
440 set_string_attribute(ID::hdlname
, attrval
);
443 vector
<string
> RTLIL::AttrObject::get_hdlname_attribute() const
445 return split_tokens(get_string_attribute(ID::hdlname
), " ");
448 bool RTLIL::Selection::selected_module(RTLIL::IdString mod_name
) const
452 if (selected_modules
.count(mod_name
) > 0)
454 if (selected_members
.count(mod_name
) > 0)
459 bool RTLIL::Selection::selected_whole_module(RTLIL::IdString mod_name
) const
463 if (selected_modules
.count(mod_name
) > 0)
468 bool RTLIL::Selection::selected_member(RTLIL::IdString mod_name
, RTLIL::IdString memb_name
) const
472 if (selected_modules
.count(mod_name
) > 0)
474 if (selected_members
.count(mod_name
) > 0)
475 if (selected_members
.at(mod_name
).count(memb_name
) > 0)
480 void RTLIL::Selection::optimize(RTLIL::Design
*design
)
482 if (full_selection
) {
483 selected_modules
.clear();
484 selected_members
.clear();
488 std::vector
<RTLIL::IdString
> del_list
, add_list
;
491 for (auto mod_name
: selected_modules
) {
492 if (design
->modules_
.count(mod_name
) == 0)
493 del_list
.push_back(mod_name
);
494 selected_members
.erase(mod_name
);
496 for (auto mod_name
: del_list
)
497 selected_modules
.erase(mod_name
);
500 for (auto &it
: selected_members
)
501 if (design
->modules_
.count(it
.first
) == 0)
502 del_list
.push_back(it
.first
);
503 for (auto mod_name
: del_list
)
504 selected_members
.erase(mod_name
);
506 for (auto &it
: selected_members
) {
508 for (auto memb_name
: it
.second
)
509 if (design
->modules_
[it
.first
]->count_id(memb_name
) == 0)
510 del_list
.push_back(memb_name
);
511 for (auto memb_name
: del_list
)
512 it
.second
.erase(memb_name
);
517 for (auto &it
: selected_members
)
518 if (it
.second
.size() == 0)
519 del_list
.push_back(it
.first
);
520 else if (it
.second
.size() == design
->modules_
[it
.first
]->wires_
.size() + design
->modules_
[it
.first
]->memories
.size() +
521 design
->modules_
[it
.first
]->cells_
.size() + design
->modules_
[it
.first
]->processes
.size())
522 add_list
.push_back(it
.first
);
523 for (auto mod_name
: del_list
)
524 selected_members
.erase(mod_name
);
525 for (auto mod_name
: add_list
) {
526 selected_members
.erase(mod_name
);
527 selected_modules
.insert(mod_name
);
530 if (selected_modules
.size() == design
->modules_
.size()) {
531 full_selection
= true;
532 selected_modules
.clear();
533 selected_members
.clear();
537 RTLIL::Design::Design()
538 : verilog_defines (new define_map_t
)
540 static unsigned int hashidx_count
= 123456789;
541 hashidx_count
= mkhash_xorshift(hashidx_count
);
542 hashidx_
= hashidx_count
;
544 refcount_modules_
= 0;
545 selection_stack
.push_back(RTLIL::Selection());
548 RTLIL::Design::get_all_designs()->insert(std::pair
<unsigned int, RTLIL::Design
*>(hashidx_
, this));
552 RTLIL::Design::~Design()
554 for (auto it
= modules_
.begin(); it
!= modules_
.end(); ++it
)
556 for (auto n
: verilog_packages
)
558 for (auto n
: verilog_globals
)
561 RTLIL::Design::get_all_designs()->erase(hashidx_
);
566 static std::map
<unsigned int, RTLIL::Design
*> all_designs
;
567 std::map
<unsigned int, RTLIL::Design
*> *RTLIL::Design::get_all_designs(void)
573 RTLIL::ObjRange
<RTLIL::Module
*> RTLIL::Design::modules()
575 return RTLIL::ObjRange
<RTLIL::Module
*>(&modules_
, &refcount_modules_
);
578 RTLIL::Module
*RTLIL::Design::module(RTLIL::IdString name
)
580 return modules_
.count(name
) ? modules_
.at(name
) : NULL
;
583 RTLIL::Module
*RTLIL::Design::top_module()
585 RTLIL::Module
*module
= nullptr;
586 int module_count
= 0;
588 for (auto mod
: selected_modules()) {
589 if (mod
->get_bool_attribute(ID::top
))
595 return module_count
== 1 ? module
: nullptr;
598 void RTLIL::Design::add(RTLIL::Module
*module
)
600 log_assert(modules_
.count(module
->name
) == 0);
601 log_assert(refcount_modules_
== 0);
602 modules_
[module
->name
] = module
;
603 module
->design
= this;
605 for (auto mon
: monitors
)
606 mon
->notify_module_add(module
);
609 log("#X# New Module: %s\n", log_id(module
));
610 log_backtrace("-X- ", yosys_xtrace
-1);
614 RTLIL::Module
*RTLIL::Design::addModule(RTLIL::IdString name
)
616 log_assert(modules_
.count(name
) == 0);
617 log_assert(refcount_modules_
== 0);
619 RTLIL::Module
*module
= new RTLIL::Module
;
620 modules_
[name
] = module
;
621 module
->design
= this;
624 for (auto mon
: monitors
)
625 mon
->notify_module_add(module
);
628 log("#X# New Module: %s\n", log_id(module
));
629 log_backtrace("-X- ", yosys_xtrace
-1);
635 void RTLIL::Design::scratchpad_unset(const std::string
&varname
)
637 scratchpad
.erase(varname
);
640 void RTLIL::Design::scratchpad_set_int(const std::string
&varname
, int value
)
642 scratchpad
[varname
] = stringf("%d", value
);
645 void RTLIL::Design::scratchpad_set_bool(const std::string
&varname
, bool value
)
647 scratchpad
[varname
] = value
? "true" : "false";
650 void RTLIL::Design::scratchpad_set_string(const std::string
&varname
, std::string value
)
652 scratchpad
[varname
] = std::move(value
);
655 int RTLIL::Design::scratchpad_get_int(const std::string
&varname
, int default_value
) const
657 auto it
= scratchpad
.find(varname
);
658 if (it
== scratchpad
.end())
659 return default_value
;
661 const std::string
&str
= it
->second
;
663 if (str
== "0" || str
== "false")
666 if (str
== "1" || str
== "true")
669 char *endptr
= nullptr;
670 long int parsed_value
= strtol(str
.c_str(), &endptr
, 10);
671 return *endptr
? default_value
: parsed_value
;
674 bool RTLIL::Design::scratchpad_get_bool(const std::string
&varname
, bool default_value
) const
676 auto it
= scratchpad
.find(varname
);
677 if (it
== scratchpad
.end())
678 return default_value
;
680 const std::string
&str
= it
->second
;
682 if (str
== "0" || str
== "false")
685 if (str
== "1" || str
== "true")
688 return default_value
;
691 std::string
RTLIL::Design::scratchpad_get_string(const std::string
&varname
, const std::string
&default_value
) const
693 auto it
= scratchpad
.find(varname
);
694 if (it
== scratchpad
.end())
695 return default_value
;
700 void RTLIL::Design::remove(RTLIL::Module
*module
)
702 for (auto mon
: monitors
)
703 mon
->notify_module_del(module
);
706 log("#X# Remove Module: %s\n", log_id(module
));
707 log_backtrace("-X- ", yosys_xtrace
-1);
710 log_assert(modules_
.at(module
->name
) == module
);
711 log_assert(refcount_modules_
== 0);
712 modules_
.erase(module
->name
);
716 void RTLIL::Design::rename(RTLIL::Module
*module
, RTLIL::IdString new_name
)
718 modules_
.erase(module
->name
);
719 module
->name
= new_name
;
723 void RTLIL::Design::sort()
726 modules_
.sort(sort_by_id_str());
727 for (auto &it
: modules_
)
731 void RTLIL::Design::check()
734 for (auto &it
: modules_
) {
735 log_assert(this == it
.second
->design
);
736 log_assert(it
.first
== it
.second
->name
);
737 log_assert(!it
.first
.empty());
743 void RTLIL::Design::optimize()
745 for (auto &it
: modules_
)
746 it
.second
->optimize();
747 for (auto &it
: selection_stack
)
749 for (auto &it
: selection_vars
)
750 it
.second
.optimize(this);
753 bool RTLIL::Design::selected_module(RTLIL::IdString mod_name
) const
755 if (!selected_active_module
.empty() && mod_name
!= selected_active_module
)
757 if (selection_stack
.size() == 0)
759 return selection_stack
.back().selected_module(mod_name
);
762 bool RTLIL::Design::selected_whole_module(RTLIL::IdString mod_name
) const
764 if (!selected_active_module
.empty() && mod_name
!= selected_active_module
)
766 if (selection_stack
.size() == 0)
768 return selection_stack
.back().selected_whole_module(mod_name
);
771 bool RTLIL::Design::selected_member(RTLIL::IdString mod_name
, RTLIL::IdString memb_name
) const
773 if (!selected_active_module
.empty() && mod_name
!= selected_active_module
)
775 if (selection_stack
.size() == 0)
777 return selection_stack
.back().selected_member(mod_name
, memb_name
);
780 bool RTLIL::Design::selected_module(RTLIL::Module
*mod
) const
782 return selected_module(mod
->name
);
785 bool RTLIL::Design::selected_whole_module(RTLIL::Module
*mod
) const
787 return selected_whole_module(mod
->name
);
790 std::vector
<RTLIL::Module
*> RTLIL::Design::selected_modules() const
792 std::vector
<RTLIL::Module
*> result
;
793 result
.reserve(modules_
.size());
794 for (auto &it
: modules_
)
795 if (selected_module(it
.first
) && !it
.second
->get_blackbox_attribute())
796 result
.push_back(it
.second
);
800 std::vector
<RTLIL::Module
*> RTLIL::Design::selected_whole_modules() const
802 std::vector
<RTLIL::Module
*> result
;
803 result
.reserve(modules_
.size());
804 for (auto &it
: modules_
)
805 if (selected_whole_module(it
.first
) && !it
.second
->get_blackbox_attribute())
806 result
.push_back(it
.second
);
810 std::vector
<RTLIL::Module
*> RTLIL::Design::selected_whole_modules_warn() const
812 std::vector
<RTLIL::Module
*> result
;
813 result
.reserve(modules_
.size());
814 for (auto &it
: modules_
)
815 if (it
.second
->get_blackbox_attribute())
817 else if (selected_whole_module(it
.first
))
818 result
.push_back(it
.second
);
819 else if (selected_module(it
.first
))
820 log_warning("Ignoring partially selected module %s.\n", log_id(it
.first
));
824 RTLIL::Module::Module()
826 static unsigned int hashidx_count
= 123456789;
827 hashidx_count
= mkhash_xorshift(hashidx_count
);
828 hashidx_
= hashidx_count
;
835 RTLIL::Module::get_all_modules()->insert(std::pair
<unsigned int, RTLIL::Module
*>(hashidx_
, this));
839 RTLIL::Module::~Module()
841 for (auto it
= wires_
.begin(); it
!= wires_
.end(); ++it
)
843 for (auto it
= memories
.begin(); it
!= memories
.end(); ++it
)
845 for (auto it
= cells_
.begin(); it
!= cells_
.end(); ++it
)
847 for (auto it
= processes
.begin(); it
!= processes
.end(); ++it
)
850 RTLIL::Module::get_all_modules()->erase(hashidx_
);
855 static std::map
<unsigned int, RTLIL::Module
*> all_modules
;
856 std::map
<unsigned int, RTLIL::Module
*> *RTLIL::Module::get_all_modules(void)
862 void RTLIL::Module::makeblackbox()
864 pool
<RTLIL::Wire
*> delwires
;
866 for (auto it
= wires_
.begin(); it
!= wires_
.end(); ++it
)
867 if (!it
->second
->port_input
&& !it
->second
->port_output
)
868 delwires
.insert(it
->second
);
870 for (auto it
= memories
.begin(); it
!= memories
.end(); ++it
)
874 for (auto it
= cells_
.begin(); it
!= cells_
.end(); ++it
)
878 for (auto it
= processes
.begin(); it
!= processes
.end(); ++it
)
882 connections_
.clear();
885 set_bool_attribute(ID::blackbox
);
888 void RTLIL::Module::reprocess_module(RTLIL::Design
*, const dict
<RTLIL::IdString
, RTLIL::Module
*> &)
890 log_error("Cannot reprocess_module module `%s' !\n", id2cstr(name
));
893 RTLIL::IdString
RTLIL::Module::derive(RTLIL::Design
*, const dict
<RTLIL::IdString
, RTLIL::Const
> &, bool mayfail
)
896 return RTLIL::IdString();
897 log_error("Module `%s' is used with parameters but is not parametric!\n", id2cstr(name
));
901 RTLIL::IdString
RTLIL::Module::derive(RTLIL::Design
*, const dict
<RTLIL::IdString
, RTLIL::Const
> &, const dict
<RTLIL::IdString
, RTLIL::Module
*> &, const dict
<RTLIL::IdString
, RTLIL::IdString
> &, bool mayfail
)
904 return RTLIL::IdString();
905 log_error("Module `%s' is used with parameters but is not parametric!\n", id2cstr(name
));
908 size_t RTLIL::Module::count_id(RTLIL::IdString id
)
910 return wires_
.count(id
) + memories
.count(id
) + cells_
.count(id
) + processes
.count(id
);
915 struct InternalCellChecker
917 RTLIL::Module
*module
;
919 pool
<RTLIL::IdString
> expected_params
, expected_ports
;
921 InternalCellChecker(RTLIL::Module
*module
, RTLIL::Cell
*cell
) : module(module
), cell(cell
) { }
923 void error(int linenr
)
925 std::stringstream buf
;
926 ILANG_BACKEND::dump_cell(buf
, " ", cell
);
928 log_error("Found error in internal cell %s%s%s (%s) at %s:%d:\n%s",
929 module
? module
->name
.c_str() : "", module
? "." : "",
930 cell
->name
.c_str(), cell
->type
.c_str(), __FILE__
, linenr
, buf
.str().c_str());
933 int param(RTLIL::IdString name
)
935 auto it
= cell
->parameters
.find(name
);
936 if (it
== cell
->parameters
.end())
938 expected_params
.insert(name
);
939 return it
->second
.as_int();
942 int param_bool(RTLIL::IdString name
)
945 if (GetSize(cell
->parameters
.at(name
)) > 32)
947 if (v
!= 0 && v
!= 1)
952 int param_bool(RTLIL::IdString name
, bool expected
)
954 int v
= param_bool(name
);
960 void param_bits(RTLIL::IdString name
, int width
)
963 if (GetSize(cell
->parameters
.at(name
).bits
) != width
)
967 void port(RTLIL::IdString name
, int width
)
969 auto it
= cell
->connections_
.find(name
);
970 if (it
== cell
->connections_
.end())
972 if (GetSize(it
->second
) != width
)
974 expected_ports
.insert(name
);
977 void check_expected(bool check_matched_sign
= false)
979 for (auto ¶
: cell
->parameters
)
980 if (expected_params
.count(para
.first
) == 0)
982 for (auto &conn
: cell
->connections())
983 if (expected_ports
.count(conn
.first
) == 0)
986 if (check_matched_sign
) {
987 log_assert(expected_params
.count(ID::A_SIGNED
) != 0 && expected_params
.count(ID::B_SIGNED
) != 0);
988 bool a_is_signed
= cell
->parameters
.at(ID::A_SIGNED
).as_bool();
989 bool b_is_signed
= cell
->parameters
.at(ID::B_SIGNED
).as_bool();
990 if (a_is_signed
!= b_is_signed
)
997 if (!cell
->type
.begins_with("$") || cell
->type
.begins_with("$__") || cell
->type
.begins_with("$paramod") || cell
->type
.begins_with("$fmcombine") ||
998 cell
->type
.begins_with("$verific$") || cell
->type
.begins_with("$array:") || cell
->type
.begins_with("$extern:"))
1001 if (cell
->type
.in(ID($
not), ID($pos
), ID($neg
))) {
1002 param_bool(ID::A_SIGNED
);
1003 port(ID::A
, param(ID::A_WIDTH
));
1004 port(ID::Y
, param(ID::Y_WIDTH
));
1009 if (cell
->type
.in(ID($
and), ID($
or), ID($
xor), ID($xnor
))) {
1010 param_bool(ID::A_SIGNED
);
1011 param_bool(ID::B_SIGNED
);
1012 port(ID::A
, param(ID::A_WIDTH
));
1013 port(ID::B
, param(ID::B_WIDTH
));
1014 port(ID::Y
, param(ID::Y_WIDTH
));
1015 check_expected(true);
1019 if (cell
->type
.in(ID($reduce_and
), ID($reduce_or
), ID($reduce_xor
), ID($reduce_xnor
), ID($reduce_bool
))) {
1020 param_bool(ID::A_SIGNED
);
1021 port(ID::A
, param(ID::A_WIDTH
));
1022 port(ID::Y
, param(ID::Y_WIDTH
));
1027 if (cell
->type
.in(ID($shl
), ID($shr
), ID($sshl
), ID($sshr
))) {
1028 param_bool(ID::A_SIGNED
);
1029 param_bool(ID::B_SIGNED
, /*expected=*/false);
1030 port(ID::A
, param(ID::A_WIDTH
));
1031 port(ID::B
, param(ID::B_WIDTH
));
1032 port(ID::Y
, param(ID::Y_WIDTH
));
1033 check_expected(/*check_matched_sign=*/false);
1037 if (cell
->type
.in(ID($shift
), ID($shiftx
))) {
1038 param_bool(ID::A_SIGNED
);
1039 param_bool(ID::B_SIGNED
);
1040 port(ID::A
, param(ID::A_WIDTH
));
1041 port(ID::B
, param(ID::B_WIDTH
));
1042 port(ID::Y
, param(ID::Y_WIDTH
));
1043 check_expected(/*check_matched_sign=*/false);
1047 if (cell
->type
.in(ID($lt
), ID($le
), ID($eq
), ID($ne
), ID($eqx
), ID($nex
), ID($ge
), ID($gt
))) {
1048 param_bool(ID::A_SIGNED
);
1049 param_bool(ID::B_SIGNED
);
1050 port(ID::A
, param(ID::A_WIDTH
));
1051 port(ID::B
, param(ID::B_WIDTH
));
1052 port(ID::Y
, param(ID::Y_WIDTH
));
1053 check_expected(true);
1057 if (cell
->type
.in(ID($add
), ID($sub
), ID($mul
), ID($div
), ID($mod
), ID($divfloor
), ID($modfloor
), ID($pow
))) {
1058 param_bool(ID::A_SIGNED
);
1059 param_bool(ID::B_SIGNED
);
1060 port(ID::A
, param(ID::A_WIDTH
));
1061 port(ID::B
, param(ID::B_WIDTH
));
1062 port(ID::Y
, param(ID::Y_WIDTH
));
1063 check_expected(cell
->type
!= ID($pow
));
1067 if (cell
->type
== ID($fa
)) {
1068 port(ID::A
, param(ID::WIDTH
));
1069 port(ID::B
, param(ID::WIDTH
));
1070 port(ID::C
, param(ID::WIDTH
));
1071 port(ID::X
, param(ID::WIDTH
));
1072 port(ID::Y
, param(ID::WIDTH
));
1077 if (cell
->type
== ID($lcu
)) {
1078 port(ID::P
, param(ID::WIDTH
));
1079 port(ID::G
, param(ID::WIDTH
));
1081 port(ID::CO
, param(ID::WIDTH
));
1086 if (cell
->type
== ID($alu
)) {
1087 param_bool(ID::A_SIGNED
);
1088 param_bool(ID::B_SIGNED
);
1089 port(ID::A
, param(ID::A_WIDTH
));
1090 port(ID::B
, param(ID::B_WIDTH
));
1093 port(ID::X
, param(ID::Y_WIDTH
));
1094 port(ID::Y
, param(ID::Y_WIDTH
));
1095 port(ID::CO
, param(ID::Y_WIDTH
));
1096 check_expected(true);
1100 if (cell
->type
== ID($macc
)) {
1102 param(ID::CONFIG_WIDTH
);
1103 port(ID::A
, param(ID::A_WIDTH
));
1104 port(ID::B
, param(ID::B_WIDTH
));
1105 port(ID::Y
, param(ID::Y_WIDTH
));
1107 Macc().from_cell(cell
);
1111 if (cell
->type
== ID($logic_not
)) {
1112 param_bool(ID::A_SIGNED
);
1113 port(ID::A
, param(ID::A_WIDTH
));
1114 port(ID::Y
, param(ID::Y_WIDTH
));
1119 if (cell
->type
.in(ID($logic_and
), ID($logic_or
))) {
1120 param_bool(ID::A_SIGNED
);
1121 param_bool(ID::B_SIGNED
);
1122 port(ID::A
, param(ID::A_WIDTH
));
1123 port(ID::B
, param(ID::B_WIDTH
));
1124 port(ID::Y
, param(ID::Y_WIDTH
));
1125 check_expected(/*check_matched_sign=*/false);
1129 if (cell
->type
== ID($slice
)) {
1131 port(ID::A
, param(ID::A_WIDTH
));
1132 port(ID::Y
, param(ID::Y_WIDTH
));
1133 if (param(ID::OFFSET
) + param(ID::Y_WIDTH
) > param(ID::A_WIDTH
))
1139 if (cell
->type
== ID($concat
)) {
1140 port(ID::A
, param(ID::A_WIDTH
));
1141 port(ID::B
, param(ID::B_WIDTH
));
1142 port(ID::Y
, param(ID::A_WIDTH
) + param(ID::B_WIDTH
));
1147 if (cell
->type
== ID($mux
)) {
1148 port(ID::A
, param(ID::WIDTH
));
1149 port(ID::B
, param(ID::WIDTH
));
1151 port(ID::Y
, param(ID::WIDTH
));
1156 if (cell
->type
== ID($pmux
)) {
1157 port(ID::A
, param(ID::WIDTH
));
1158 port(ID::B
, param(ID::WIDTH
) * param(ID::S_WIDTH
));
1159 port(ID::S
, param(ID::S_WIDTH
));
1160 port(ID::Y
, param(ID::WIDTH
));
1165 if (cell
->type
== ID($lut
)) {
1167 port(ID::A
, param(ID::WIDTH
));
1173 if (cell
->type
== ID($sop
)) {
1176 port(ID::A
, param(ID::WIDTH
));
1182 if (cell
->type
== ID($sr
)) {
1183 param_bool(ID::SET_POLARITY
);
1184 param_bool(ID::CLR_POLARITY
);
1185 port(ID::SET
, param(ID::WIDTH
));
1186 port(ID::CLR
, param(ID::WIDTH
));
1187 port(ID::Q
, param(ID::WIDTH
));
1192 if (cell
->type
== ID($ff
)) {
1193 port(ID::D
, param(ID::WIDTH
));
1194 port(ID::Q
, param(ID::WIDTH
));
1199 if (cell
->type
== ID($dff
)) {
1200 param_bool(ID::CLK_POLARITY
);
1202 port(ID::D
, param(ID::WIDTH
));
1203 port(ID::Q
, param(ID::WIDTH
));
1208 if (cell
->type
== ID($dffe
)) {
1209 param_bool(ID::CLK_POLARITY
);
1210 param_bool(ID::EN_POLARITY
);
1213 port(ID::D
, param(ID::WIDTH
));
1214 port(ID::Q
, param(ID::WIDTH
));
1219 if (cell
->type
== ID($dffsr
)) {
1220 param_bool(ID::CLK_POLARITY
);
1221 param_bool(ID::SET_POLARITY
);
1222 param_bool(ID::CLR_POLARITY
);
1224 port(ID::SET
, param(ID::WIDTH
));
1225 port(ID::CLR
, param(ID::WIDTH
));
1226 port(ID::D
, param(ID::WIDTH
));
1227 port(ID::Q
, param(ID::WIDTH
));
1232 if (cell
->type
== ID($dffsre
)) {
1233 param_bool(ID::CLK_POLARITY
);
1234 param_bool(ID::SET_POLARITY
);
1235 param_bool(ID::CLR_POLARITY
);
1236 param_bool(ID::EN_POLARITY
);
1239 port(ID::SET
, param(ID::WIDTH
));
1240 port(ID::CLR
, param(ID::WIDTH
));
1241 port(ID::D
, param(ID::WIDTH
));
1242 port(ID::Q
, param(ID::WIDTH
));
1247 if (cell
->type
== ID($adff
)) {
1248 param_bool(ID::CLK_POLARITY
);
1249 param_bool(ID::ARST_POLARITY
);
1250 param_bits(ID::ARST_VALUE
, param(ID::WIDTH
));
1253 port(ID::D
, param(ID::WIDTH
));
1254 port(ID::Q
, param(ID::WIDTH
));
1259 if (cell
->type
== ID($sdff
)) {
1260 param_bool(ID::CLK_POLARITY
);
1261 param_bool(ID::SRST_POLARITY
);
1262 param_bits(ID::SRST_VALUE
, param(ID::WIDTH
));
1265 port(ID::D
, param(ID::WIDTH
));
1266 port(ID::Q
, param(ID::WIDTH
));
1271 if (cell
->type
.in(ID($sdffe
), ID($sdffce
))) {
1272 param_bool(ID::CLK_POLARITY
);
1273 param_bool(ID::EN_POLARITY
);
1274 param_bool(ID::SRST_POLARITY
);
1275 param_bits(ID::SRST_VALUE
, param(ID::WIDTH
));
1279 port(ID::D
, param(ID::WIDTH
));
1280 port(ID::Q
, param(ID::WIDTH
));
1285 if (cell
->type
== ID($adffe
)) {
1286 param_bool(ID::CLK_POLARITY
);
1287 param_bool(ID::EN_POLARITY
);
1288 param_bool(ID::ARST_POLARITY
);
1289 param_bits(ID::ARST_VALUE
, param(ID::WIDTH
));
1293 port(ID::D
, param(ID::WIDTH
));
1294 port(ID::Q
, param(ID::WIDTH
));
1299 if (cell
->type
== ID($dlatch
)) {
1300 param_bool(ID::EN_POLARITY
);
1302 port(ID::D
, param(ID::WIDTH
));
1303 port(ID::Q
, param(ID::WIDTH
));
1308 if (cell
->type
== ID($adlatch
)) {
1309 param_bool(ID::EN_POLARITY
);
1310 param_bool(ID::ARST_POLARITY
);
1311 param_bits(ID::ARST_VALUE
, param(ID::WIDTH
));
1314 port(ID::D
, param(ID::WIDTH
));
1315 port(ID::Q
, param(ID::WIDTH
));
1320 if (cell
->type
== ID($dlatchsr
)) {
1321 param_bool(ID::EN_POLARITY
);
1322 param_bool(ID::SET_POLARITY
);
1323 param_bool(ID::CLR_POLARITY
);
1325 port(ID::SET
, param(ID::WIDTH
));
1326 port(ID::CLR
, param(ID::WIDTH
));
1327 port(ID::D
, param(ID::WIDTH
));
1328 port(ID::Q
, param(ID::WIDTH
));
1333 if (cell
->type
== ID($fsm
)) {
1335 param_bool(ID::CLK_POLARITY
);
1336 param_bool(ID::ARST_POLARITY
);
1337 param(ID::STATE_BITS
);
1338 param(ID::STATE_NUM
);
1339 param(ID::STATE_NUM_LOG2
);
1340 param(ID::STATE_RST
);
1341 param_bits(ID::STATE_TABLE
, param(ID::STATE_BITS
) * param(ID::STATE_NUM
));
1342 param(ID::TRANS_NUM
);
1343 param_bits(ID::TRANS_TABLE
, param(ID::TRANS_NUM
) * (2*param(ID::STATE_NUM_LOG2
) + param(ID::CTRL_IN_WIDTH
) + param(ID::CTRL_OUT_WIDTH
)));
1346 port(ID::CTRL_IN
, param(ID::CTRL_IN_WIDTH
));
1347 port(ID::CTRL_OUT
, param(ID::CTRL_OUT_WIDTH
));
1352 if (cell
->type
== ID($memrd
)) {
1354 param_bool(ID::CLK_ENABLE
);
1355 param_bool(ID::CLK_POLARITY
);
1356 param_bool(ID::TRANSPARENT
);
1359 port(ID::ADDR
, param(ID::ABITS
));
1360 port(ID::DATA
, param(ID::WIDTH
));
1365 if (cell
->type
== ID($memwr
)) {
1367 param_bool(ID::CLK_ENABLE
);
1368 param_bool(ID::CLK_POLARITY
);
1369 param(ID::PRIORITY
);
1371 port(ID::EN
, param(ID::WIDTH
));
1372 port(ID::ADDR
, param(ID::ABITS
));
1373 port(ID::DATA
, param(ID::WIDTH
));
1378 if (cell
->type
== ID($meminit
)) {
1380 param(ID::PRIORITY
);
1381 port(ID::ADDR
, param(ID::ABITS
));
1382 port(ID::DATA
, param(ID::WIDTH
) * param(ID::WORDS
));
1387 if (cell
->type
== ID($mem
)) {
1392 param_bits(ID::RD_CLK_ENABLE
, max(1, param(ID::RD_PORTS
)));
1393 param_bits(ID::RD_CLK_POLARITY
, max(1, param(ID::RD_PORTS
)));
1394 param_bits(ID::RD_TRANSPARENT
, max(1, param(ID::RD_PORTS
)));
1395 param_bits(ID::WR_CLK_ENABLE
, max(1, param(ID::WR_PORTS
)));
1396 param_bits(ID::WR_CLK_POLARITY
, max(1, param(ID::WR_PORTS
)));
1397 port(ID::RD_CLK
, param(ID::RD_PORTS
));
1398 port(ID::RD_EN
, param(ID::RD_PORTS
));
1399 port(ID::RD_ADDR
, param(ID::RD_PORTS
) * param(ID::ABITS
));
1400 port(ID::RD_DATA
, param(ID::RD_PORTS
) * param(ID::WIDTH
));
1401 port(ID::WR_CLK
, param(ID::WR_PORTS
));
1402 port(ID::WR_EN
, param(ID::WR_PORTS
) * param(ID::WIDTH
));
1403 port(ID::WR_ADDR
, param(ID::WR_PORTS
) * param(ID::ABITS
));
1404 port(ID::WR_DATA
, param(ID::WR_PORTS
) * param(ID::WIDTH
));
1409 if (cell
->type
== ID($tribuf
)) {
1410 port(ID::A
, param(ID::WIDTH
));
1411 port(ID::Y
, param(ID::WIDTH
));
1417 if (cell
->type
.in(ID($
assert), ID($assume
), ID($live
), ID($fair
), ID($cover
))) {
1424 if (cell
->type
== ID($initstate
)) {
1430 if (cell
->type
.in(ID($anyconst
), ID($anyseq
), ID($allconst
), ID($allseq
))) {
1431 port(ID::Y
, param(ID::WIDTH
));
1436 if (cell
->type
== ID($equiv
)) {
1444 if (cell
->type
.in(ID($specify2
), ID($specify3
))) {
1445 param_bool(ID::FULL
);
1446 param_bool(ID::SRC_DST_PEN
);
1447 param_bool(ID::SRC_DST_POL
);
1448 param(ID::T_RISE_MIN
);
1449 param(ID::T_RISE_TYP
);
1450 param(ID::T_RISE_MAX
);
1451 param(ID::T_FALL_MIN
);
1452 param(ID::T_FALL_TYP
);
1453 param(ID::T_FALL_MAX
);
1455 port(ID::SRC
, param(ID::SRC_WIDTH
));
1456 port(ID::DST
, param(ID::DST_WIDTH
));
1457 if (cell
->type
== ID($specify3
)) {
1458 param_bool(ID::EDGE_EN
);
1459 param_bool(ID::EDGE_POL
);
1460 param_bool(ID::DAT_DST_PEN
);
1461 param_bool(ID::DAT_DST_POL
);
1462 port(ID::DAT
, param(ID::DST_WIDTH
));
1468 if (cell
->type
== ID($specrule
)) {
1470 param_bool(ID::SRC_PEN
);
1471 param_bool(ID::SRC_POL
);
1472 param_bool(ID::DST_PEN
);
1473 param_bool(ID::DST_POL
);
1474 param(ID::T_LIMIT_MIN
);
1475 param(ID::T_LIMIT_TYP
);
1476 param(ID::T_LIMIT_MAX
);
1477 param(ID::T_LIMIT2_MIN
);
1478 param(ID::T_LIMIT2_TYP
);
1479 param(ID::T_LIMIT2_MAX
);
1480 port(ID::SRC_EN
, 1);
1481 port(ID::DST_EN
, 1);
1482 port(ID::SRC
, param(ID::SRC_WIDTH
));
1483 port(ID::DST
, param(ID::DST_WIDTH
));
1488 if (cell
->type
== ID($_BUF_
)) { port(ID::A
,1); port(ID::Y
,1); check_expected(); return; }
1489 if (cell
->type
== ID($_NOT_
)) { port(ID::A
,1); port(ID::Y
,1); check_expected(); return; }
1490 if (cell
->type
== ID($_AND_
)) { port(ID::A
,1); port(ID::B
,1); port(ID::Y
,1); check_expected(); return; }
1491 if (cell
->type
== ID($_NAND_
)) { port(ID::A
,1); port(ID::B
,1); port(ID::Y
,1); check_expected(); return; }
1492 if (cell
->type
== ID($_OR_
)) { port(ID::A
,1); port(ID::B
,1); port(ID::Y
,1); check_expected(); return; }
1493 if (cell
->type
== ID($_NOR_
)) { port(ID::A
,1); port(ID::B
,1); port(ID::Y
,1); check_expected(); return; }
1494 if (cell
->type
== ID($_XOR_
)) { port(ID::A
,1); port(ID::B
,1); port(ID::Y
,1); check_expected(); return; }
1495 if (cell
->type
== ID($_XNOR_
)) { port(ID::A
,1); port(ID::B
,1); port(ID::Y
,1); check_expected(); return; }
1496 if (cell
->type
== ID($_ANDNOT_
)) { port(ID::A
,1); port(ID::B
,1); port(ID::Y
,1); check_expected(); return; }
1497 if (cell
->type
== ID($_ORNOT_
)) { port(ID::A
,1); port(ID::B
,1); port(ID::Y
,1); check_expected(); return; }
1498 if (cell
->type
== ID($_MUX_
)) { port(ID::A
,1); port(ID::B
,1); port(ID::S
,1); port(ID::Y
,1); check_expected(); return; }
1499 if (cell
->type
== ID($_NMUX_
)) { port(ID::A
,1); port(ID::B
,1); port(ID::S
,1); port(ID::Y
,1); check_expected(); return; }
1500 if (cell
->type
== ID($_AOI3_
)) { port(ID::A
,1); port(ID::B
,1); port(ID::C
,1); port(ID::Y
,1); check_expected(); return; }
1501 if (cell
->type
== ID($_OAI3_
)) { port(ID::A
,1); port(ID::B
,1); port(ID::C
,1); port(ID::Y
,1); check_expected(); return; }
1502 if (cell
->type
== ID($_AOI4_
)) { port(ID::A
,1); port(ID::B
,1); port(ID::C
,1); port(ID::D
,1); port(ID::Y
,1); check_expected(); return; }
1503 if (cell
->type
== ID($_OAI4_
)) { port(ID::A
,1); port(ID::B
,1); port(ID::C
,1); port(ID::D
,1); port(ID::Y
,1); check_expected(); return; }
1505 if (cell
->type
== ID($_TBUF_
)) { port(ID::A
,1); port(ID::Y
,1); port(ID::E
,1); check_expected(); return; }
1507 if (cell
->type
== ID($_MUX4_
)) { port(ID::A
,1); port(ID::B
,1); port(ID::C
,1); port(ID::D
,1); port(ID::S
,1); port(ID::T
,1); port(ID::Y
,1); check_expected(); return; }
1508 if (cell
->type
== ID($_MUX8_
)) { port(ID::A
,1); port(ID::B
,1); port(ID::C
,1); port(ID::D
,1); port(ID::E
,1); port(ID::F
,1); port(ID::G
,1); port(ID::H
,1); port(ID::S
,1); port(ID::T
,1); port(ID::U
,1); port(ID::Y
,1); check_expected(); return; }
1509 if (cell
->type
== ID($_MUX16_
)) { port(ID::A
,1); port(ID::B
,1); port(ID::C
,1); port(ID::D
,1); port(ID::E
,1); port(ID::F
,1); port(ID::G
,1); port(ID::H
,1); port(ID::I
,1); port(ID::J
,1); port(ID::K
,1); port(ID::L
,1); port(ID::M
,1); port(ID::N
,1); port(ID::O
,1); port(ID::P
,1); port(ID::S
,1); port(ID::T
,1); port(ID::U
,1); port(ID::V
,1); port(ID::Y
,1); check_expected(); return; }
1511 if (cell
->type
.in(ID($_SR_NN_
), ID($_SR_NP_
), ID($_SR_PN_
), ID($_SR_PP_
)))
1512 { port(ID::S
,1); port(ID::R
,1); port(ID::Q
,1); check_expected(); return; }
1514 if (cell
->type
== ID($_FF_
)) { port(ID::D
,1); port(ID::Q
,1); check_expected(); return; }
1516 if (cell
->type
.in(ID($_DFF_N_
), ID($_DFF_P_
)))
1517 { port(ID::D
,1); port(ID::Q
,1); port(ID::C
,1); check_expected(); return; }
1519 if (cell
->type
.in(ID($_DFFE_NN_
), ID($_DFFE_NP_
), ID($_DFFE_PN_
), ID($_DFFE_PP_
)))
1520 { port(ID::D
,1); port(ID::Q
,1); port(ID::C
,1); port(ID::E
,1); check_expected(); return; }
1523 ID($_DFF_NN0_
), ID($_DFF_NN1_
), ID($_DFF_NP0_
), ID($_DFF_NP1_
),
1524 ID($_DFF_PN0_
), ID($_DFF_PN1_
), ID($_DFF_PP0_
), ID($_DFF_PP1_
)))
1525 { port(ID::D
,1); port(ID::Q
,1); port(ID::C
,1); port(ID::R
,1); check_expected(); return; }
1528 ID($_DFFE_NN0N_
), ID($_DFFE_NN0P_
), ID($_DFFE_NN1N_
), ID($_DFFE_NN1P_
),
1529 ID($_DFFE_NP0N_
), ID($_DFFE_NP0P_
), ID($_DFFE_NP1N_
), ID($_DFFE_NP1P_
),
1530 ID($_DFFE_PN0N_
), ID($_DFFE_PN0P_
), ID($_DFFE_PN1N_
), ID($_DFFE_PN1P_
),
1531 ID($_DFFE_PP0N_
), ID($_DFFE_PP0P_
), ID($_DFFE_PP1N_
), ID($_DFFE_PP1P_
)))
1532 { port(ID::D
,1); port(ID::Q
,1); port(ID::C
,1); port(ID::R
,1); port(ID::E
,1); check_expected(); return; }
1535 ID($_DFFSR_NNN_
), ID($_DFFSR_NNP_
), ID($_DFFSR_NPN_
), ID($_DFFSR_NPP_
),
1536 ID($_DFFSR_PNN_
), ID($_DFFSR_PNP_
), ID($_DFFSR_PPN_
), ID($_DFFSR_PPP_
)))
1537 { port(ID::C
,1); port(ID::S
,1); port(ID::R
,1); port(ID::D
,1); port(ID::Q
,1); check_expected(); return; }
1540 ID($_DFFSRE_NNNN_
), ID($_DFFSRE_NNNP_
), ID($_DFFSRE_NNPN_
), ID($_DFFSRE_NNPP_
),
1541 ID($_DFFSRE_NPNN_
), ID($_DFFSRE_NPNP_
), ID($_DFFSRE_NPPN_
), ID($_DFFSRE_NPPP_
),
1542 ID($_DFFSRE_PNNN_
), ID($_DFFSRE_PNNP_
), ID($_DFFSRE_PNPN_
), ID($_DFFSRE_PNPP_
),
1543 ID($_DFFSRE_PPNN_
), ID($_DFFSRE_PPNP_
), ID($_DFFSRE_PPPN_
), ID($_DFFSRE_PPPP_
)))
1544 { port(ID::C
,1); port(ID::S
,1); port(ID::R
,1); port(ID::D
,1); port(ID::E
,1); port(ID::Q
,1); check_expected(); return; }
1547 ID($_SDFF_NN0_
), ID($_SDFF_NN1_
), ID($_SDFF_NP0_
), ID($_SDFF_NP1_
),
1548 ID($_SDFF_PN0_
), ID($_SDFF_PN1_
), ID($_SDFF_PP0_
), ID($_SDFF_PP1_
)))
1549 { port(ID::D
,1); port(ID::Q
,1); port(ID::C
,1); port(ID::R
,1); check_expected(); return; }
1552 ID($_SDFFE_NN0N_
), ID($_SDFFE_NN0P_
), ID($_SDFFE_NN1N_
), ID($_SDFFE_NN1P_
),
1553 ID($_SDFFE_NP0N_
), ID($_SDFFE_NP0P_
), ID($_SDFFE_NP1N_
), ID($_SDFFE_NP1P_
),
1554 ID($_SDFFE_PN0N_
), ID($_SDFFE_PN0P_
), ID($_SDFFE_PN1N_
), ID($_SDFFE_PN1P_
),
1555 ID($_SDFFE_PP0N_
), ID($_SDFFE_PP0P_
), ID($_SDFFE_PP1N_
), ID($_SDFFE_PP1P_
),
1556 ID($_SDFFCE_NN0N_
), ID($_SDFFCE_NN0P_
), ID($_SDFFCE_NN1N_
), ID($_SDFFCE_NN1P_
),
1557 ID($_SDFFCE_NP0N_
), ID($_SDFFCE_NP0P_
), ID($_SDFFCE_NP1N_
), ID($_SDFFCE_NP1P_
),
1558 ID($_SDFFCE_PN0N_
), ID($_SDFFCE_PN0P_
), ID($_SDFFCE_PN1N_
), ID($_SDFFCE_PN1P_
),
1559 ID($_SDFFCE_PP0N_
), ID($_SDFFCE_PP0P_
), ID($_SDFFCE_PP1N_
), ID($_SDFFCE_PP1P_
)))
1560 { port(ID::D
,1); port(ID::Q
,1); port(ID::C
,1); port(ID::R
,1); port(ID::E
,1); check_expected(); return; }
1562 if (cell
->type
.in(ID($_DLATCH_N_
), ID($_DLATCH_P_
)))
1563 { port(ID::E
,1); port(ID::D
,1); port(ID::Q
,1); check_expected(); return; }
1566 ID($_DLATCH_NN0_
), ID($_DLATCH_NN1_
), ID($_DLATCH_NP0_
), ID($_DLATCH_NP1_
),
1567 ID($_DLATCH_PN0_
), ID($_DLATCH_PN1_
), ID($_DLATCH_PP0_
), ID($_DLATCH_PP1_
)))
1568 { port(ID::E
,1); port(ID::R
,1); port(ID::D
,1); port(ID::Q
,1); check_expected(); return; }
1571 ID($_DLATCHSR_NNN_
), ID($_DLATCHSR_NNP_
), ID($_DLATCHSR_NPN_
), ID($_DLATCHSR_NPP_
),
1572 ID($_DLATCHSR_PNN_
), ID($_DLATCHSR_PNP_
), ID($_DLATCHSR_PPN_
), ID($_DLATCHSR_PPP_
)))
1573 { port(ID::E
,1); port(ID::S
,1); port(ID::R
,1); port(ID::D
,1); port(ID::Q
,1); check_expected(); return; }
1581 void RTLIL::Module::sort()
1583 wires_
.sort(sort_by_id_str());
1584 cells_
.sort(sort_by_id_str());
1585 parameter_default_values
.sort(sort_by_id_str());
1586 memories
.sort(sort_by_id_str());
1587 processes
.sort(sort_by_id_str());
1588 for (auto &it
: cells_
)
1590 for (auto &it
: wires_
)
1591 it
.second
->attributes
.sort(sort_by_id_str());
1592 for (auto &it
: memories
)
1593 it
.second
->attributes
.sort(sort_by_id_str());
1596 void RTLIL::Module::check()
1599 std::vector
<bool> ports_declared
;
1600 for (auto &it
: wires_
) {
1601 log_assert(this == it
.second
->module
);
1602 log_assert(it
.first
== it
.second
->name
);
1603 log_assert(!it
.first
.empty());
1604 log_assert(it
.second
->width
>= 0);
1605 log_assert(it
.second
->port_id
>= 0);
1606 for (auto &it2
: it
.second
->attributes
)
1607 log_assert(!it2
.first
.empty());
1608 if (it
.second
->port_id
) {
1609 log_assert(GetSize(ports
) >= it
.second
->port_id
);
1610 log_assert(ports
.at(it
.second
->port_id
-1) == it
.first
);
1611 log_assert(it
.second
->port_input
|| it
.second
->port_output
);
1612 if (GetSize(ports_declared
) < it
.second
->port_id
)
1613 ports_declared
.resize(it
.second
->port_id
);
1614 log_assert(ports_declared
[it
.second
->port_id
-1] == false);
1615 ports_declared
[it
.second
->port_id
-1] = true;
1617 log_assert(!it
.second
->port_input
&& !it
.second
->port_output
);
1619 for (auto port_declared
: ports_declared
)
1620 log_assert(port_declared
== true);
1621 log_assert(GetSize(ports
) == GetSize(ports_declared
));
1623 for (auto &it
: memories
) {
1624 log_assert(it
.first
== it
.second
->name
);
1625 log_assert(!it
.first
.empty());
1626 log_assert(it
.second
->width
>= 0);
1627 log_assert(it
.second
->size
>= 0);
1628 for (auto &it2
: it
.second
->attributes
)
1629 log_assert(!it2
.first
.empty());
1632 for (auto &it
: cells_
) {
1633 log_assert(this == it
.second
->module
);
1634 log_assert(it
.first
== it
.second
->name
);
1635 log_assert(!it
.first
.empty());
1636 log_assert(!it
.second
->type
.empty());
1637 for (auto &it2
: it
.second
->connections()) {
1638 log_assert(!it2
.first
.empty());
1641 for (auto &it2
: it
.second
->attributes
)
1642 log_assert(!it2
.first
.empty());
1643 for (auto &it2
: it
.second
->parameters
)
1644 log_assert(!it2
.first
.empty());
1645 InternalCellChecker
checker(this, it
.second
);
1649 for (auto &it
: processes
) {
1650 log_assert(it
.first
== it
.second
->name
);
1651 log_assert(!it
.first
.empty());
1652 log_assert(it
.second
->root_case
.compare
.empty());
1653 std::vector
<CaseRule
*> all_cases
= {&it
.second
->root_case
};
1654 for (size_t i
= 0; i
< all_cases
.size(); i
++) {
1655 for (auto &switch_it
: all_cases
[i
]->switches
) {
1656 for (auto &case_it
: switch_it
->cases
) {
1657 for (auto &compare_it
: case_it
->compare
) {
1658 log_assert(switch_it
->signal
.size() == compare_it
.size());
1660 all_cases
.push_back(case_it
);
1664 for (auto &sync_it
: it
.second
->syncs
) {
1665 switch (sync_it
->type
) {
1671 log_assert(!sync_it
->signal
.empty());
1676 log_assert(sync_it
->signal
.empty());
1682 for (auto &it
: connections_
) {
1683 log_assert(it
.first
.size() == it
.second
.size());
1684 log_assert(!it
.first
.has_const());
1689 for (auto &it
: attributes
)
1690 log_assert(!it
.first
.empty());
1694 void RTLIL::Module::optimize()
1698 void RTLIL::Module::cloneInto(RTLIL::Module
*new_mod
) const
1700 log_assert(new_mod
->refcount_wires_
== 0);
1701 log_assert(new_mod
->refcount_cells_
== 0);
1703 new_mod
->avail_parameters
= avail_parameters
;
1704 new_mod
->parameter_default_values
= parameter_default_values
;
1706 for (auto &conn
: connections_
)
1707 new_mod
->connect(conn
);
1709 for (auto &attr
: attributes
)
1710 new_mod
->attributes
[attr
.first
] = attr
.second
;
1712 for (auto &it
: wires_
)
1713 new_mod
->addWire(it
.first
, it
.second
);
1715 for (auto &it
: memories
)
1716 new_mod
->addMemory(it
.first
, it
.second
);
1718 for (auto &it
: cells_
)
1719 new_mod
->addCell(it
.first
, it
.second
);
1721 for (auto &it
: processes
)
1722 new_mod
->addProcess(it
.first
, it
.second
);
1724 struct RewriteSigSpecWorker
1727 void operator()(RTLIL::SigSpec
&sig
)
1730 for (auto &c
: sig
.chunks_
)
1732 c
.wire
= mod
->wires_
.at(c
.wire
->name
);
1736 RewriteSigSpecWorker rewriteSigSpecWorker
;
1737 rewriteSigSpecWorker
.mod
= new_mod
;
1738 new_mod
->rewrite_sigspecs(rewriteSigSpecWorker
);
1739 new_mod
->fixup_ports();
1742 RTLIL::Module
*RTLIL::Module::clone() const
1744 RTLIL::Module
*new_mod
= new RTLIL::Module
;
1745 new_mod
->name
= name
;
1750 bool RTLIL::Module::has_memories() const
1752 return !memories
.empty();
1755 bool RTLIL::Module::has_processes() const
1757 return !processes
.empty();
1760 bool RTLIL::Module::has_memories_warn() const
1762 if (!memories
.empty())
1763 log_warning("Ignoring module %s because it contains memories (run 'memory' command first).\n", log_id(this));
1764 return !memories
.empty();
1767 bool RTLIL::Module::has_processes_warn() const
1769 if (!processes
.empty())
1770 log_warning("Ignoring module %s because it contains processes (run 'proc' command first).\n", log_id(this));
1771 return !processes
.empty();
1774 std::vector
<RTLIL::Wire
*> RTLIL::Module::selected_wires() const
1776 std::vector
<RTLIL::Wire
*> result
;
1777 result
.reserve(wires_
.size());
1778 for (auto &it
: wires_
)
1779 if (design
->selected(this, it
.second
))
1780 result
.push_back(it
.second
);
1784 std::vector
<RTLIL::Cell
*> RTLIL::Module::selected_cells() const
1786 std::vector
<RTLIL::Cell
*> result
;
1787 result
.reserve(cells_
.size());
1788 for (auto &it
: cells_
)
1789 if (design
->selected(this, it
.second
))
1790 result
.push_back(it
.second
);
1794 void RTLIL::Module::add(RTLIL::Wire
*wire
)
1796 log_assert(!wire
->name
.empty());
1797 log_assert(count_id(wire
->name
) == 0);
1798 log_assert(refcount_wires_
== 0);
1799 wires_
[wire
->name
] = wire
;
1800 wire
->module
= this;
1803 void RTLIL::Module::add(RTLIL::Cell
*cell
)
1805 log_assert(!cell
->name
.empty());
1806 log_assert(count_id(cell
->name
) == 0);
1807 log_assert(refcount_cells_
== 0);
1808 cells_
[cell
->name
] = cell
;
1809 cell
->module
= this;
1812 void RTLIL::Module::remove(const pool
<RTLIL::Wire
*> &wires
)
1814 log_assert(refcount_wires_
== 0);
1816 struct DeleteWireWorker
1818 RTLIL::Module
*module
;
1819 const pool
<RTLIL::Wire
*> *wires_p
;
1821 void operator()(RTLIL::SigSpec
&sig
) {
1823 for (auto &c
: sig
.chunks_
)
1824 if (c
.wire
!= NULL
&& wires_p
->count(c
.wire
)) {
1825 c
.wire
= module
->addWire(NEW_ID
, c
.width
);
1830 void operator()(RTLIL::SigSpec
&lhs
, RTLIL::SigSpec
&rhs
) {
1831 log_assert(GetSize(lhs
) == GetSize(rhs
));
1834 for (int i
= 0; i
< GetSize(lhs
); i
++) {
1835 RTLIL::SigBit
&lhs_bit
= lhs
.bits_
[i
];
1836 RTLIL::SigBit
&rhs_bit
= rhs
.bits_
[i
];
1837 if ((lhs_bit
.wire
!= nullptr && wires_p
->count(lhs_bit
.wire
)) || (rhs_bit
.wire
!= nullptr && wires_p
->count(rhs_bit
.wire
))) {
1838 lhs_bit
= State::Sx
;
1839 rhs_bit
= State::Sx
;
1845 DeleteWireWorker delete_wire_worker
;
1846 delete_wire_worker
.module
= this;
1847 delete_wire_worker
.wires_p
= &wires
;
1848 rewrite_sigspecs2(delete_wire_worker
);
1850 for (auto &it
: wires
) {
1851 log_assert(wires_
.count(it
->name
) != 0);
1852 wires_
.erase(it
->name
);
1857 void RTLIL::Module::remove(RTLIL::Cell
*cell
)
1859 while (!cell
->connections_
.empty())
1860 cell
->unsetPort(cell
->connections_
.begin()->first
);
1862 log_assert(cells_
.count(cell
->name
) != 0);
1863 log_assert(refcount_cells_
== 0);
1864 cells_
.erase(cell
->name
);
1868 void RTLIL::Module::rename(RTLIL::Wire
*wire
, RTLIL::IdString new_name
)
1870 log_assert(wires_
[wire
->name
] == wire
);
1871 log_assert(refcount_wires_
== 0);
1872 wires_
.erase(wire
->name
);
1873 wire
->name
= new_name
;
1877 void RTLIL::Module::rename(RTLIL::Cell
*cell
, RTLIL::IdString new_name
)
1879 log_assert(cells_
[cell
->name
] == cell
);
1880 log_assert(refcount_wires_
== 0);
1881 cells_
.erase(cell
->name
);
1882 cell
->name
= new_name
;
1886 void RTLIL::Module::rename(RTLIL::IdString old_name
, RTLIL::IdString new_name
)
1888 log_assert(count_id(old_name
) != 0);
1889 if (wires_
.count(old_name
))
1890 rename(wires_
.at(old_name
), new_name
);
1891 else if (cells_
.count(old_name
))
1892 rename(cells_
.at(old_name
), new_name
);
1897 void RTLIL::Module::swap_names(RTLIL::Wire
*w1
, RTLIL::Wire
*w2
)
1899 log_assert(wires_
[w1
->name
] == w1
);
1900 log_assert(wires_
[w2
->name
] == w2
);
1901 log_assert(refcount_wires_
== 0);
1903 wires_
.erase(w1
->name
);
1904 wires_
.erase(w2
->name
);
1906 std::swap(w1
->name
, w2
->name
);
1908 wires_
[w1
->name
] = w1
;
1909 wires_
[w2
->name
] = w2
;
1912 void RTLIL::Module::swap_names(RTLIL::Cell
*c1
, RTLIL::Cell
*c2
)
1914 log_assert(cells_
[c1
->name
] == c1
);
1915 log_assert(cells_
[c2
->name
] == c2
);
1916 log_assert(refcount_cells_
== 0);
1918 cells_
.erase(c1
->name
);
1919 cells_
.erase(c2
->name
);
1921 std::swap(c1
->name
, c2
->name
);
1923 cells_
[c1
->name
] = c1
;
1924 cells_
[c2
->name
] = c2
;
1927 RTLIL::IdString
RTLIL::Module::uniquify(RTLIL::IdString name
)
1930 return uniquify(name
, index
);
1933 RTLIL::IdString
RTLIL::Module::uniquify(RTLIL::IdString name
, int &index
)
1936 if (count_id(name
) == 0)
1942 RTLIL::IdString new_name
= stringf("%s_%d", name
.c_str(), index
);
1943 if (count_id(new_name
) == 0)
1949 static bool fixup_ports_compare(const RTLIL::Wire
*a
, const RTLIL::Wire
*b
)
1951 if (a
->port_id
&& !b
->port_id
)
1953 if (!a
->port_id
&& b
->port_id
)
1956 if (a
->port_id
== b
->port_id
)
1957 return a
->name
< b
->name
;
1958 return a
->port_id
< b
->port_id
;
1961 void RTLIL::Module::connect(const RTLIL::SigSig
&conn
)
1963 for (auto mon
: monitors
)
1964 mon
->notify_connect(this, conn
);
1967 for (auto mon
: design
->monitors
)
1968 mon
->notify_connect(this, conn
);
1970 // ignore all attempts to assign constants to other constants
1971 if (conn
.first
.has_const()) {
1972 RTLIL::SigSig new_conn
;
1973 for (int i
= 0; i
< GetSize(conn
.first
); i
++)
1974 if (conn
.first
[i
].wire
) {
1975 new_conn
.first
.append(conn
.first
[i
]);
1976 new_conn
.second
.append(conn
.second
[i
]);
1978 if (GetSize(new_conn
.first
))
1984 log("#X# Connect (SigSig) in %s: %s = %s (%d bits)\n", log_id(this), log_signal(conn
.first
), log_signal(conn
.second
), GetSize(conn
.first
));
1985 log_backtrace("-X- ", yosys_xtrace
-1);
1988 log_assert(GetSize(conn
.first
) == GetSize(conn
.second
));
1989 connections_
.push_back(conn
);
1992 void RTLIL::Module::connect(const RTLIL::SigSpec
&lhs
, const RTLIL::SigSpec
&rhs
)
1994 connect(RTLIL::SigSig(lhs
, rhs
));
1997 void RTLIL::Module::new_connections(const std::vector
<RTLIL::SigSig
> &new_conn
)
1999 for (auto mon
: monitors
)
2000 mon
->notify_connect(this, new_conn
);
2003 for (auto mon
: design
->monitors
)
2004 mon
->notify_connect(this, new_conn
);
2007 log("#X# New connections vector in %s:\n", log_id(this));
2008 for (auto &conn
: new_conn
)
2009 log("#X# %s = %s (%d bits)\n", log_signal(conn
.first
), log_signal(conn
.second
), GetSize(conn
.first
));
2010 log_backtrace("-X- ", yosys_xtrace
-1);
2013 connections_
= new_conn
;
2016 const std::vector
<RTLIL::SigSig
> &RTLIL::Module::connections() const
2018 return connections_
;
2021 void RTLIL::Module::fixup_ports()
2023 std::vector
<RTLIL::Wire
*> all_ports
;
2025 for (auto &w
: wires_
)
2026 if (w
.second
->port_input
|| w
.second
->port_output
)
2027 all_ports
.push_back(w
.second
);
2029 w
.second
->port_id
= 0;
2031 std::sort(all_ports
.begin(), all_ports
.end(), fixup_ports_compare
);
2034 for (size_t i
= 0; i
< all_ports
.size(); i
++) {
2035 ports
.push_back(all_ports
[i
]->name
);
2036 all_ports
[i
]->port_id
= i
+1;
2040 RTLIL::Wire
*RTLIL::Module::addWire(RTLIL::IdString name
, int width
)
2042 RTLIL::Wire
*wire
= new RTLIL::Wire
;
2044 wire
->width
= width
;
2049 RTLIL::Wire
*RTLIL::Module::addWire(RTLIL::IdString name
, const RTLIL::Wire
*other
)
2051 RTLIL::Wire
*wire
= addWire(name
);
2052 wire
->width
= other
->width
;
2053 wire
->start_offset
= other
->start_offset
;
2054 wire
->port_id
= other
->port_id
;
2055 wire
->port_input
= other
->port_input
;
2056 wire
->port_output
= other
->port_output
;
2057 wire
->upto
= other
->upto
;
2058 wire
->is_signed
= other
->is_signed
;
2059 wire
->attributes
= other
->attributes
;
2063 RTLIL::Cell
*RTLIL::Module::addCell(RTLIL::IdString name
, RTLIL::IdString type
)
2065 RTLIL::Cell
*cell
= new RTLIL::Cell
;
2072 RTLIL::Cell
*RTLIL::Module::addCell(RTLIL::IdString name
, const RTLIL::Cell
*other
)
2074 RTLIL::Cell
*cell
= addCell(name
, other
->type
);
2075 cell
->connections_
= other
->connections_
;
2076 cell
->parameters
= other
->parameters
;
2077 cell
->attributes
= other
->attributes
;
2081 RTLIL::Memory
*RTLIL::Module::addMemory(RTLIL::IdString name
, const RTLIL::Memory
*other
)
2083 RTLIL::Memory
*mem
= new RTLIL::Memory
;
2085 mem
->width
= other
->width
;
2086 mem
->start_offset
= other
->start_offset
;
2087 mem
->size
= other
->size
;
2088 mem
->attributes
= other
->attributes
;
2089 memories
[mem
->name
] = mem
;
2093 RTLIL::Process
*RTLIL::Module::addProcess(RTLIL::IdString name
, const RTLIL::Process
*other
)
2095 RTLIL::Process
*proc
= other
->clone();
2097 processes
[name
] = proc
;
2101 #define DEF_METHOD(_func, _y_size, _type) \
2102 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed, const std::string &src) { \
2103 RTLIL::Cell *cell = addCell(name, _type); \
2104 cell->parameters[ID::A_SIGNED] = is_signed; \
2105 cell->parameters[ID::A_WIDTH] = sig_a.size(); \
2106 cell->parameters[ID::Y_WIDTH] = sig_y.size(); \
2107 cell->setPort(ID::A, sig_a); \
2108 cell->setPort(ID::Y, sig_y); \
2109 cell->set_src_attribute(src); \
2112 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed, const std::string &src) { \
2113 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
2114 add ## _func(name, sig_a, sig_y, is_signed, src); \
2117 DEF_METHOD(Not
, sig_a
.size(), ID($
not))
2118 DEF_METHOD(Pos
, sig_a
.size(), ID($pos
))
2119 DEF_METHOD(Neg
, sig_a
.size(), ID($neg
))
2120 DEF_METHOD(ReduceAnd
, 1, ID($reduce_and
))
2121 DEF_METHOD(ReduceOr
, 1, ID($reduce_or
))
2122 DEF_METHOD(ReduceXor
, 1, ID($reduce_xor
))
2123 DEF_METHOD(ReduceXnor
, 1, ID($reduce_xnor
))
2124 DEF_METHOD(ReduceBool
, 1, ID($reduce_bool
))
2125 DEF_METHOD(LogicNot
, 1, ID($logic_not
))
2128 #define DEF_METHOD(_func, _y_size, _type) \
2129 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed, const std::string &src) { \
2130 RTLIL::Cell *cell = addCell(name, _type); \
2131 cell->parameters[ID::A_SIGNED] = is_signed; \
2132 cell->parameters[ID::B_SIGNED] = is_signed; \
2133 cell->parameters[ID::A_WIDTH] = sig_a.size(); \
2134 cell->parameters[ID::B_WIDTH] = sig_b.size(); \
2135 cell->parameters[ID::Y_WIDTH] = sig_y.size(); \
2136 cell->setPort(ID::A, sig_a); \
2137 cell->setPort(ID::B, sig_b); \
2138 cell->setPort(ID::Y, sig_y); \
2139 cell->set_src_attribute(src); \
2142 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed, const std::string &src) { \
2143 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
2144 add ## _func(name, sig_a, sig_b, sig_y, is_signed, src); \
2147 DEF_METHOD(And
, max(sig_a
.size(), sig_b
.size()), ID($
and))
2148 DEF_METHOD(Or
, max(sig_a
.size(), sig_b
.size()), ID($
or))
2149 DEF_METHOD(Xor
, max(sig_a
.size(), sig_b
.size()), ID($
xor))
2150 DEF_METHOD(Xnor
, max(sig_a
.size(), sig_b
.size()), ID($xnor
))
2151 DEF_METHOD(Shift
, sig_a
.size(), ID($shift
))
2152 DEF_METHOD(Shiftx
, sig_a
.size(), ID($shiftx
))
2153 DEF_METHOD(Lt
, 1, ID($lt
))
2154 DEF_METHOD(Le
, 1, ID($le
))
2155 DEF_METHOD(Eq
, 1, ID($eq
))
2156 DEF_METHOD(Ne
, 1, ID($ne
))
2157 DEF_METHOD(Eqx
, 1, ID($eqx
))
2158 DEF_METHOD(Nex
, 1, ID($nex
))
2159 DEF_METHOD(Ge
, 1, ID($ge
))
2160 DEF_METHOD(Gt
, 1, ID($gt
))
2161 DEF_METHOD(Add
, max(sig_a
.size(), sig_b
.size()), ID($add
))
2162 DEF_METHOD(Sub
, max(sig_a
.size(), sig_b
.size()), ID($sub
))
2163 DEF_METHOD(Mul
, max(sig_a
.size(), sig_b
.size()), ID($mul
))
2164 DEF_METHOD(Div
, max(sig_a
.size(), sig_b
.size()), ID($div
))
2165 DEF_METHOD(Mod
, max(sig_a
.size(), sig_b
.size()), ID($mod
))
2166 DEF_METHOD(DivFloor
, max(sig_a
.size(), sig_b
.size()), ID($divfloor
))
2167 DEF_METHOD(ModFloor
, max(sig_a
.size(), sig_b
.size()), ID($modfloor
))
2168 DEF_METHOD(LogicAnd
, 1, ID($logic_and
))
2169 DEF_METHOD(LogicOr
, 1, ID($logic_or
))
2172 #define DEF_METHOD(_func, _y_size, _type) \
2173 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed, const std::string &src) { \
2174 RTLIL::Cell *cell = addCell(name, _type); \
2175 cell->parameters[ID::A_SIGNED] = is_signed; \
2176 cell->parameters[ID::B_SIGNED] = false; \
2177 cell->parameters[ID::A_WIDTH] = sig_a.size(); \
2178 cell->parameters[ID::B_WIDTH] = sig_b.size(); \
2179 cell->parameters[ID::Y_WIDTH] = sig_y.size(); \
2180 cell->setPort(ID::A, sig_a); \
2181 cell->setPort(ID::B, sig_b); \
2182 cell->setPort(ID::Y, sig_y); \
2183 cell->set_src_attribute(src); \
2186 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed, const std::string &src) { \
2187 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
2188 add ## _func(name, sig_a, sig_b, sig_y, is_signed, src); \
2191 DEF_METHOD(Shl
, sig_a
.size(), ID($shl
))
2192 DEF_METHOD(Shr
, sig_a
.size(), ID($shr
))
2193 DEF_METHOD(Sshl
, sig_a
.size(), ID($sshl
))
2194 DEF_METHOD(Sshr
, sig_a
.size(), ID($sshr
))
2197 #define DEF_METHOD(_func, _type, _pmux) \
2198 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, const std::string &src) { \
2199 RTLIL::Cell *cell = addCell(name, _type); \
2200 cell->parameters[ID::WIDTH] = sig_a.size(); \
2201 if (_pmux) cell->parameters[ID::S_WIDTH] = sig_s.size(); \
2202 cell->setPort(ID::A, sig_a); \
2203 cell->setPort(ID::B, sig_b); \
2204 cell->setPort(ID::S, sig_s); \
2205 cell->setPort(ID::Y, sig_y); \
2206 cell->set_src_attribute(src); \
2209 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const std::string &src) { \
2210 RTLIL::SigSpec sig_y = addWire(NEW_ID, sig_a.size()); \
2211 add ## _func(name, sig_a, sig_b, sig_s, sig_y, src); \
2214 DEF_METHOD(Mux
, ID($mux
), 0)
2215 DEF_METHOD(Pmux
, ID($pmux
), 1)
2218 #define DEF_METHOD_2(_func, _type, _P1, _P2) \
2219 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const std::string &src) { \
2220 RTLIL::Cell *cell = addCell(name, _type); \
2221 cell->setPort("\\" #_P1, sig1); \
2222 cell->setPort("\\" #_P2, sig2); \
2223 cell->set_src_attribute(src); \
2226 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const std::string &src) { \
2227 RTLIL::SigBit sig2 = addWire(NEW_ID); \
2228 add ## _func(name, sig1, sig2, src); \
2231 #define DEF_METHOD_3(_func, _type, _P1, _P2, _P3) \
2232 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const RTLIL::SigBit &sig3, const std::string &src) { \
2233 RTLIL::Cell *cell = addCell(name, _type); \
2234 cell->setPort("\\" #_P1, sig1); \
2235 cell->setPort("\\" #_P2, sig2); \
2236 cell->setPort("\\" #_P3, sig3); \
2237 cell->set_src_attribute(src); \
2240 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const std::string &src) { \
2241 RTLIL::SigBit sig3 = addWire(NEW_ID); \
2242 add ## _func(name, sig1, sig2, sig3, src); \
2245 #define DEF_METHOD_4(_func, _type, _P1, _P2, _P3, _P4) \
2246 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const RTLIL::SigBit &sig3, const RTLIL::SigBit &sig4, const std::string &src) { \
2247 RTLIL::Cell *cell = addCell(name, _type); \
2248 cell->setPort("\\" #_P1, sig1); \
2249 cell->setPort("\\" #_P2, sig2); \
2250 cell->setPort("\\" #_P3, sig3); \
2251 cell->setPort("\\" #_P4, sig4); \
2252 cell->set_src_attribute(src); \
2255 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const RTLIL::SigBit &sig3, const std::string &src) { \
2256 RTLIL::SigBit sig4 = addWire(NEW_ID); \
2257 add ## _func(name, sig1, sig2, sig3, sig4, src); \
2260 #define DEF_METHOD_5(_func, _type, _P1, _P2, _P3, _P4, _P5) \
2261 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const RTLIL::SigBit &sig3, const RTLIL::SigBit &sig4, const RTLIL::SigBit &sig5, const std::string &src) { \
2262 RTLIL::Cell *cell = addCell(name, _type); \
2263 cell->setPort("\\" #_P1, sig1); \
2264 cell->setPort("\\" #_P2, sig2); \
2265 cell->setPort("\\" #_P3, sig3); \
2266 cell->setPort("\\" #_P4, sig4); \
2267 cell->setPort("\\" #_P5, sig5); \
2268 cell->set_src_attribute(src); \
2271 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const RTLIL::SigBit &sig3, const RTLIL::SigBit &sig4, const std::string &src) { \
2272 RTLIL::SigBit sig5 = addWire(NEW_ID); \
2273 add ## _func(name, sig1, sig2, sig3, sig4, sig5, src); \
2276 DEF_METHOD_2(BufGate
, ID($_BUF_
), A
, Y
)
2277 DEF_METHOD_2(NotGate
, ID($_NOT_
), A
, Y
)
2278 DEF_METHOD_3(AndGate
, ID($_AND_
), A
, B
, Y
)
2279 DEF_METHOD_3(NandGate
, ID($_NAND_
), A
, B
, Y
)
2280 DEF_METHOD_3(OrGate
, ID($_OR_
), A
, B
, Y
)
2281 DEF_METHOD_3(NorGate
, ID($_NOR_
), A
, B
, Y
)
2282 DEF_METHOD_3(XorGate
, ID($_XOR_
), A
, B
, Y
)
2283 DEF_METHOD_3(XnorGate
, ID($_XNOR_
), A
, B
, Y
)
2284 DEF_METHOD_3(AndnotGate
, ID($_ANDNOT_
), A
, B
, Y
)
2285 DEF_METHOD_3(OrnotGate
, ID($_ORNOT_
), A
, B
, Y
)
2286 DEF_METHOD_4(MuxGate
, ID($_MUX_
), A
, B
, S
, Y
)
2287 DEF_METHOD_4(NmuxGate
, ID($_NMUX_
), A
, B
, S
, Y
)
2288 DEF_METHOD_4(Aoi3Gate
, ID($_AOI3_
), A
, B
, C
, Y
)
2289 DEF_METHOD_4(Oai3Gate
, ID($_OAI3_
), A
, B
, C
, Y
)
2290 DEF_METHOD_5(Aoi4Gate
, ID($_AOI4_
), A
, B
, C
, D
, Y
)
2291 DEF_METHOD_5(Oai4Gate
, ID($_OAI4_
), A
, B
, C
, D
, Y
)
2297 RTLIL::Cell
* RTLIL::Module::addPow(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_a
, const RTLIL::SigSpec
&sig_b
, const RTLIL::SigSpec
&sig_y
, bool a_signed
, bool b_signed
, const std::string
&src
)
2299 RTLIL::Cell
*cell
= addCell(name
, ID($pow
));
2300 cell
->parameters
[ID::A_SIGNED
] = a_signed
;
2301 cell
->parameters
[ID::B_SIGNED
] = b_signed
;
2302 cell
->parameters
[ID::A_WIDTH
] = sig_a
.size();
2303 cell
->parameters
[ID::B_WIDTH
] = sig_b
.size();
2304 cell
->parameters
[ID::Y_WIDTH
] = sig_y
.size();
2305 cell
->setPort(ID::A
, sig_a
);
2306 cell
->setPort(ID::B
, sig_b
);
2307 cell
->setPort(ID::Y
, sig_y
);
2308 cell
->set_src_attribute(src
);
2312 RTLIL::Cell
* RTLIL::Module::addSlice(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_a
, const RTLIL::SigSpec
&sig_y
, RTLIL::Const offset
, const std::string
&src
)
2314 RTLIL::Cell
*cell
= addCell(name
, ID($slice
));
2315 cell
->parameters
[ID::A_WIDTH
] = sig_a
.size();
2316 cell
->parameters
[ID::Y_WIDTH
] = sig_y
.size();
2317 cell
->parameters
[ID::OFFSET
] = offset
;
2318 cell
->setPort(ID::A
, sig_a
);
2319 cell
->setPort(ID::Y
, sig_y
);
2320 cell
->set_src_attribute(src
);
2324 RTLIL::Cell
* RTLIL::Module::addConcat(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_a
, const RTLIL::SigSpec
&sig_b
, const RTLIL::SigSpec
&sig_y
, const std::string
&src
)
2326 RTLIL::Cell
*cell
= addCell(name
, ID($concat
));
2327 cell
->parameters
[ID::A_WIDTH
] = sig_a
.size();
2328 cell
->parameters
[ID::B_WIDTH
] = sig_b
.size();
2329 cell
->setPort(ID::A
, sig_a
);
2330 cell
->setPort(ID::B
, sig_b
);
2331 cell
->setPort(ID::Y
, sig_y
);
2332 cell
->set_src_attribute(src
);
2336 RTLIL::Cell
* RTLIL::Module::addLut(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_a
, const RTLIL::SigSpec
&sig_y
, RTLIL::Const lut
, const std::string
&src
)
2338 RTLIL::Cell
*cell
= addCell(name
, ID($lut
));
2339 cell
->parameters
[ID::LUT
] = lut
;
2340 cell
->parameters
[ID::WIDTH
] = sig_a
.size();
2341 cell
->setPort(ID::A
, sig_a
);
2342 cell
->setPort(ID::Y
, sig_y
);
2343 cell
->set_src_attribute(src
);
2347 RTLIL::Cell
* RTLIL::Module::addTribuf(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_a
, const RTLIL::SigSpec
&sig_en
, const RTLIL::SigSpec
&sig_y
, const std::string
&src
)
2349 RTLIL::Cell
*cell
= addCell(name
, ID($tribuf
));
2350 cell
->parameters
[ID::WIDTH
] = sig_a
.size();
2351 cell
->setPort(ID::A
, sig_a
);
2352 cell
->setPort(ID::EN
, sig_en
);
2353 cell
->setPort(ID::Y
, sig_y
);
2354 cell
->set_src_attribute(src
);
2358 RTLIL::Cell
* RTLIL::Module::addAssert(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_a
, const RTLIL::SigSpec
&sig_en
, const std::string
&src
)
2360 RTLIL::Cell
*cell
= addCell(name
, ID($
assert));
2361 cell
->setPort(ID::A
, sig_a
);
2362 cell
->setPort(ID::EN
, sig_en
);
2363 cell
->set_src_attribute(src
);
2367 RTLIL::Cell
* RTLIL::Module::addAssume(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_a
, const RTLIL::SigSpec
&sig_en
, const std::string
&src
)
2369 RTLIL::Cell
*cell
= addCell(name
, ID($assume
));
2370 cell
->setPort(ID::A
, sig_a
);
2371 cell
->setPort(ID::EN
, sig_en
);
2372 cell
->set_src_attribute(src
);
2376 RTLIL::Cell
* RTLIL::Module::addLive(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_a
, const RTLIL::SigSpec
&sig_en
, const std::string
&src
)
2378 RTLIL::Cell
*cell
= addCell(name
, ID($live
));
2379 cell
->setPort(ID::A
, sig_a
);
2380 cell
->setPort(ID::EN
, sig_en
);
2381 cell
->set_src_attribute(src
);
2385 RTLIL::Cell
* RTLIL::Module::addFair(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_a
, const RTLIL::SigSpec
&sig_en
, const std::string
&src
)
2387 RTLIL::Cell
*cell
= addCell(name
, ID($fair
));
2388 cell
->setPort(ID::A
, sig_a
);
2389 cell
->setPort(ID::EN
, sig_en
);
2390 cell
->set_src_attribute(src
);
2394 RTLIL::Cell
* RTLIL::Module::addCover(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_a
, const RTLIL::SigSpec
&sig_en
, const std::string
&src
)
2396 RTLIL::Cell
*cell
= addCell(name
, ID($cover
));
2397 cell
->setPort(ID::A
, sig_a
);
2398 cell
->setPort(ID::EN
, sig_en
);
2399 cell
->set_src_attribute(src
);
2403 RTLIL::Cell
* RTLIL::Module::addEquiv(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_a
, const RTLIL::SigSpec
&sig_b
, const RTLIL::SigSpec
&sig_y
, const std::string
&src
)
2405 RTLIL::Cell
*cell
= addCell(name
, ID($equiv
));
2406 cell
->setPort(ID::A
, sig_a
);
2407 cell
->setPort(ID::B
, sig_b
);
2408 cell
->setPort(ID::Y
, sig_y
);
2409 cell
->set_src_attribute(src
);
2413 RTLIL::Cell
* RTLIL::Module::addSr(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_set
, const RTLIL::SigSpec
&sig_clr
, const RTLIL::SigSpec
&sig_q
, bool set_polarity
, bool clr_polarity
, const std::string
&src
)
2415 RTLIL::Cell
*cell
= addCell(name
, ID($sr
));
2416 cell
->parameters
[ID::SET_POLARITY
] = set_polarity
;
2417 cell
->parameters
[ID::CLR_POLARITY
] = clr_polarity
;
2418 cell
->parameters
[ID::WIDTH
] = sig_q
.size();
2419 cell
->setPort(ID::SET
, sig_set
);
2420 cell
->setPort(ID::CLR
, sig_clr
);
2421 cell
->setPort(ID::Q
, sig_q
);
2422 cell
->set_src_attribute(src
);
2426 RTLIL::Cell
* RTLIL::Module::addFf(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_d
, const RTLIL::SigSpec
&sig_q
, const std::string
&src
)
2428 RTLIL::Cell
*cell
= addCell(name
, ID($ff
));
2429 cell
->parameters
[ID::WIDTH
] = sig_q
.size();
2430 cell
->setPort(ID::D
, sig_d
);
2431 cell
->setPort(ID::Q
, sig_q
);
2432 cell
->set_src_attribute(src
);
2436 RTLIL::Cell
* RTLIL::Module::addDff(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_clk
, const RTLIL::SigSpec
&sig_d
, const RTLIL::SigSpec
&sig_q
, bool clk_polarity
, const std::string
&src
)
2438 RTLIL::Cell
*cell
= addCell(name
, ID($dff
));
2439 cell
->parameters
[ID::CLK_POLARITY
] = clk_polarity
;
2440 cell
->parameters
[ID::WIDTH
] = sig_q
.size();
2441 cell
->setPort(ID::CLK
, sig_clk
);
2442 cell
->setPort(ID::D
, sig_d
);
2443 cell
->setPort(ID::Q
, sig_q
);
2444 cell
->set_src_attribute(src
);
2448 RTLIL::Cell
* RTLIL::Module::addDffe(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_clk
, const RTLIL::SigSpec
&sig_en
, const RTLIL::SigSpec
&sig_d
, const RTLIL::SigSpec
&sig_q
, bool clk_polarity
, bool en_polarity
, const std::string
&src
)
2450 RTLIL::Cell
*cell
= addCell(name
, ID($dffe
));
2451 cell
->parameters
[ID::CLK_POLARITY
] = clk_polarity
;
2452 cell
->parameters
[ID::EN_POLARITY
] = en_polarity
;
2453 cell
->parameters
[ID::WIDTH
] = sig_q
.size();
2454 cell
->setPort(ID::CLK
, sig_clk
);
2455 cell
->setPort(ID::EN
, sig_en
);
2456 cell
->setPort(ID::D
, sig_d
);
2457 cell
->setPort(ID::Q
, sig_q
);
2458 cell
->set_src_attribute(src
);
2462 RTLIL::Cell
* RTLIL::Module::addDffsr(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_clk
, const RTLIL::SigSpec
&sig_set
, const RTLIL::SigSpec
&sig_clr
,
2463 RTLIL::SigSpec sig_d
, const RTLIL::SigSpec
&sig_q
, bool clk_polarity
, bool set_polarity
, bool clr_polarity
, const std::string
&src
)
2465 RTLIL::Cell
*cell
= addCell(name
, ID($dffsr
));
2466 cell
->parameters
[ID::CLK_POLARITY
] = clk_polarity
;
2467 cell
->parameters
[ID::SET_POLARITY
] = set_polarity
;
2468 cell
->parameters
[ID::CLR_POLARITY
] = clr_polarity
;
2469 cell
->parameters
[ID::WIDTH
] = sig_q
.size();
2470 cell
->setPort(ID::CLK
, sig_clk
);
2471 cell
->setPort(ID::SET
, sig_set
);
2472 cell
->setPort(ID::CLR
, sig_clr
);
2473 cell
->setPort(ID::D
, sig_d
);
2474 cell
->setPort(ID::Q
, sig_q
);
2475 cell
->set_src_attribute(src
);
2479 RTLIL::Cell
* RTLIL::Module::addDffsre(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_clk
, const RTLIL::SigSpec
&sig_en
, const RTLIL::SigSpec
&sig_set
, const RTLIL::SigSpec
&sig_clr
,
2480 RTLIL::SigSpec sig_d
, const RTLIL::SigSpec
&sig_q
, bool clk_polarity
, bool en_polarity
, bool set_polarity
, bool clr_polarity
, const std::string
&src
)
2482 RTLIL::Cell
*cell
= addCell(name
, ID($dffsre
));
2483 cell
->parameters
[ID::CLK_POLARITY
] = clk_polarity
;
2484 cell
->parameters
[ID::EN_POLARITY
] = en_polarity
;
2485 cell
->parameters
[ID::SET_POLARITY
] = set_polarity
;
2486 cell
->parameters
[ID::CLR_POLARITY
] = clr_polarity
;
2487 cell
->parameters
[ID::WIDTH
] = sig_q
.size();
2488 cell
->setPort(ID::CLK
, sig_clk
);
2489 cell
->setPort(ID::EN
, sig_en
);
2490 cell
->setPort(ID::SET
, sig_set
);
2491 cell
->setPort(ID::CLR
, sig_clr
);
2492 cell
->setPort(ID::D
, sig_d
);
2493 cell
->setPort(ID::Q
, sig_q
);
2494 cell
->set_src_attribute(src
);
2498 RTLIL::Cell
* RTLIL::Module::addAdff(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_clk
, const RTLIL::SigSpec
&sig_arst
, const RTLIL::SigSpec
&sig_d
, const RTLIL::SigSpec
&sig_q
,
2499 RTLIL::Const arst_value
, bool clk_polarity
, bool arst_polarity
, const std::string
&src
)
2501 RTLIL::Cell
*cell
= addCell(name
, ID($adff
));
2502 cell
->parameters
[ID::CLK_POLARITY
] = clk_polarity
;
2503 cell
->parameters
[ID::ARST_POLARITY
] = arst_polarity
;
2504 cell
->parameters
[ID::ARST_VALUE
] = arst_value
;
2505 cell
->parameters
[ID::WIDTH
] = sig_q
.size();
2506 cell
->setPort(ID::CLK
, sig_clk
);
2507 cell
->setPort(ID::ARST
, sig_arst
);
2508 cell
->setPort(ID::D
, sig_d
);
2509 cell
->setPort(ID::Q
, sig_q
);
2510 cell
->set_src_attribute(src
);
2514 RTLIL::Cell
* RTLIL::Module::addAdffe(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_clk
, const RTLIL::SigSpec
&sig_en
, const RTLIL::SigSpec
&sig_arst
, const RTLIL::SigSpec
&sig_d
, const RTLIL::SigSpec
&sig_q
,
2515 RTLIL::Const arst_value
, bool clk_polarity
, bool en_polarity
, bool arst_polarity
, const std::string
&src
)
2517 RTLIL::Cell
*cell
= addCell(name
, ID($adffe
));
2518 cell
->parameters
[ID::CLK_POLARITY
] = clk_polarity
;
2519 cell
->parameters
[ID::EN_POLARITY
] = en_polarity
;
2520 cell
->parameters
[ID::ARST_POLARITY
] = arst_polarity
;
2521 cell
->parameters
[ID::ARST_VALUE
] = arst_value
;
2522 cell
->parameters
[ID::WIDTH
] = sig_q
.size();
2523 cell
->setPort(ID::CLK
, sig_clk
);
2524 cell
->setPort(ID::EN
, sig_en
);
2525 cell
->setPort(ID::ARST
, sig_arst
);
2526 cell
->setPort(ID::D
, sig_d
);
2527 cell
->setPort(ID::Q
, sig_q
);
2528 cell
->set_src_attribute(src
);
2532 RTLIL::Cell
* RTLIL::Module::addSdff(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_clk
, const RTLIL::SigSpec
&sig_srst
, const RTLIL::SigSpec
&sig_d
, const RTLIL::SigSpec
&sig_q
,
2533 RTLIL::Const srst_value
, bool clk_polarity
, bool srst_polarity
, const std::string
&src
)
2535 RTLIL::Cell
*cell
= addCell(name
, ID($sdff
));
2536 cell
->parameters
[ID::CLK_POLARITY
] = clk_polarity
;
2537 cell
->parameters
[ID::SRST_POLARITY
] = srst_polarity
;
2538 cell
->parameters
[ID::SRST_VALUE
] = srst_value
;
2539 cell
->parameters
[ID::WIDTH
] = sig_q
.size();
2540 cell
->setPort(ID::CLK
, sig_clk
);
2541 cell
->setPort(ID::SRST
, sig_srst
);
2542 cell
->setPort(ID::D
, sig_d
);
2543 cell
->setPort(ID::Q
, sig_q
);
2544 cell
->set_src_attribute(src
);
2548 RTLIL::Cell
* RTLIL::Module::addSdffe(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_clk
, const RTLIL::SigSpec
&sig_en
, const RTLIL::SigSpec
&sig_srst
, const RTLIL::SigSpec
&sig_d
, const RTLIL::SigSpec
&sig_q
,
2549 RTLIL::Const srst_value
, bool clk_polarity
, bool en_polarity
, bool srst_polarity
, const std::string
&src
)
2551 RTLIL::Cell
*cell
= addCell(name
, ID($sdffe
));
2552 cell
->parameters
[ID::CLK_POLARITY
] = clk_polarity
;
2553 cell
->parameters
[ID::EN_POLARITY
] = en_polarity
;
2554 cell
->parameters
[ID::SRST_POLARITY
] = srst_polarity
;
2555 cell
->parameters
[ID::SRST_VALUE
] = srst_value
;
2556 cell
->parameters
[ID::WIDTH
] = sig_q
.size();
2557 cell
->setPort(ID::CLK
, sig_clk
);
2558 cell
->setPort(ID::EN
, sig_en
);
2559 cell
->setPort(ID::SRST
, sig_srst
);
2560 cell
->setPort(ID::D
, sig_d
);
2561 cell
->setPort(ID::Q
, sig_q
);
2562 cell
->set_src_attribute(src
);
2566 RTLIL::Cell
* RTLIL::Module::addSdffce(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_clk
, const RTLIL::SigSpec
&sig_en
, const RTLIL::SigSpec
&sig_srst
, const RTLIL::SigSpec
&sig_d
, const RTLIL::SigSpec
&sig_q
,
2567 RTLIL::Const srst_value
, bool clk_polarity
, bool en_polarity
, bool srst_polarity
, const std::string
&src
)
2569 RTLIL::Cell
*cell
= addCell(name
, ID($sdffce
));
2570 cell
->parameters
[ID::CLK_POLARITY
] = clk_polarity
;
2571 cell
->parameters
[ID::EN_POLARITY
] = en_polarity
;
2572 cell
->parameters
[ID::SRST_POLARITY
] = srst_polarity
;
2573 cell
->parameters
[ID::SRST_VALUE
] = srst_value
;
2574 cell
->parameters
[ID::WIDTH
] = sig_q
.size();
2575 cell
->setPort(ID::CLK
, sig_clk
);
2576 cell
->setPort(ID::EN
, sig_en
);
2577 cell
->setPort(ID::SRST
, sig_srst
);
2578 cell
->setPort(ID::D
, sig_d
);
2579 cell
->setPort(ID::Q
, sig_q
);
2580 cell
->set_src_attribute(src
);
2584 RTLIL::Cell
* RTLIL::Module::addDlatch(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_en
, const RTLIL::SigSpec
&sig_d
, const RTLIL::SigSpec
&sig_q
, bool en_polarity
, const std::string
&src
)
2586 RTLIL::Cell
*cell
= addCell(name
, ID($dlatch
));
2587 cell
->parameters
[ID::EN_POLARITY
] = en_polarity
;
2588 cell
->parameters
[ID::WIDTH
] = sig_q
.size();
2589 cell
->setPort(ID::EN
, sig_en
);
2590 cell
->setPort(ID::D
, sig_d
);
2591 cell
->setPort(ID::Q
, sig_q
);
2592 cell
->set_src_attribute(src
);
2596 RTLIL::Cell
* RTLIL::Module::addAdlatch(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_en
, const RTLIL::SigSpec
&sig_arst
, const RTLIL::SigSpec
&sig_d
, const RTLIL::SigSpec
&sig_q
,
2597 RTLIL::Const arst_value
, bool en_polarity
, bool arst_polarity
, const std::string
&src
)
2599 RTLIL::Cell
*cell
= addCell(name
, ID($adlatch
));
2600 cell
->parameters
[ID::EN_POLARITY
] = en_polarity
;
2601 cell
->parameters
[ID::ARST_POLARITY
] = arst_polarity
;
2602 cell
->parameters
[ID::ARST_VALUE
] = arst_value
;
2603 cell
->parameters
[ID::WIDTH
] = sig_q
.size();
2604 cell
->setPort(ID::EN
, sig_en
);
2605 cell
->setPort(ID::ARST
, sig_arst
);
2606 cell
->setPort(ID::D
, sig_d
);
2607 cell
->setPort(ID::Q
, sig_q
);
2608 cell
->set_src_attribute(src
);
2612 RTLIL::Cell
* RTLIL::Module::addDlatchsr(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_en
, const RTLIL::SigSpec
&sig_set
, const RTLIL::SigSpec
&sig_clr
,
2613 RTLIL::SigSpec sig_d
, const RTLIL::SigSpec
&sig_q
, bool en_polarity
, bool set_polarity
, bool clr_polarity
, const std::string
&src
)
2615 RTLIL::Cell
*cell
= addCell(name
, ID($dlatchsr
));
2616 cell
->parameters
[ID::EN_POLARITY
] = en_polarity
;
2617 cell
->parameters
[ID::SET_POLARITY
] = set_polarity
;
2618 cell
->parameters
[ID::CLR_POLARITY
] = clr_polarity
;
2619 cell
->parameters
[ID::WIDTH
] = sig_q
.size();
2620 cell
->setPort(ID::EN
, sig_en
);
2621 cell
->setPort(ID::SET
, sig_set
);
2622 cell
->setPort(ID::CLR
, sig_clr
);
2623 cell
->setPort(ID::D
, sig_d
);
2624 cell
->setPort(ID::Q
, sig_q
);
2625 cell
->set_src_attribute(src
);
2629 RTLIL::Cell
* RTLIL::Module::addSrGate(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_set
, const RTLIL::SigSpec
&sig_clr
,
2630 const RTLIL::SigSpec
&sig_q
, bool set_polarity
, bool clr_polarity
, const std::string
&src
)
2632 RTLIL::Cell
*cell
= addCell(name
, stringf("$_SR_%c%c_", set_polarity
? 'P' : 'N', clr_polarity
? 'P' : 'N'));
2633 cell
->setPort(ID::S
, sig_set
);
2634 cell
->setPort(ID::R
, sig_clr
);
2635 cell
->setPort(ID::Q
, sig_q
);
2636 cell
->set_src_attribute(src
);
2640 RTLIL::Cell
* RTLIL::Module::addFfGate(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_d
, const RTLIL::SigSpec
&sig_q
, const std::string
&src
)
2642 RTLIL::Cell
*cell
= addCell(name
, ID($_FF_
));
2643 cell
->setPort(ID::D
, sig_d
);
2644 cell
->setPort(ID::Q
, sig_q
);
2645 cell
->set_src_attribute(src
);
2649 RTLIL::Cell
* RTLIL::Module::addDffGate(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_clk
, const RTLIL::SigSpec
&sig_d
, const RTLIL::SigSpec
&sig_q
, bool clk_polarity
, const std::string
&src
)
2651 RTLIL::Cell
*cell
= addCell(name
, stringf("$_DFF_%c_", clk_polarity
? 'P' : 'N'));
2652 cell
->setPort(ID::C
, sig_clk
);
2653 cell
->setPort(ID::D
, sig_d
);
2654 cell
->setPort(ID::Q
, sig_q
);
2655 cell
->set_src_attribute(src
);
2659 RTLIL::Cell
* RTLIL::Module::addDffeGate(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_clk
, const RTLIL::SigSpec
&sig_en
, const RTLIL::SigSpec
&sig_d
, const RTLIL::SigSpec
&sig_q
, bool clk_polarity
, bool en_polarity
, const std::string
&src
)
2661 RTLIL::Cell
*cell
= addCell(name
, stringf("$_DFFE_%c%c_", clk_polarity
? 'P' : 'N', en_polarity
? 'P' : 'N'));
2662 cell
->setPort(ID::C
, sig_clk
);
2663 cell
->setPort(ID::E
, sig_en
);
2664 cell
->setPort(ID::D
, sig_d
);
2665 cell
->setPort(ID::Q
, sig_q
);
2666 cell
->set_src_attribute(src
);
2670 RTLIL::Cell
* RTLIL::Module::addDffsrGate(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_clk
, const RTLIL::SigSpec
&sig_set
, const RTLIL::SigSpec
&sig_clr
,
2671 RTLIL::SigSpec sig_d
, const RTLIL::SigSpec
&sig_q
, bool clk_polarity
, bool set_polarity
, bool clr_polarity
, const std::string
&src
)
2673 RTLIL::Cell
*cell
= addCell(name
, stringf("$_DFFSR_%c%c%c_", clk_polarity
? 'P' : 'N', set_polarity
? 'P' : 'N', clr_polarity
? 'P' : 'N'));
2674 cell
->setPort(ID::C
, sig_clk
);
2675 cell
->setPort(ID::S
, sig_set
);
2676 cell
->setPort(ID::R
, sig_clr
);
2677 cell
->setPort(ID::D
, sig_d
);
2678 cell
->setPort(ID::Q
, sig_q
);
2679 cell
->set_src_attribute(src
);
2683 RTLIL::Cell
* RTLIL::Module::addDffsreGate(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_clk
, const RTLIL::SigSpec
&sig_en
, const RTLIL::SigSpec
&sig_set
, const RTLIL::SigSpec
&sig_clr
,
2684 RTLIL::SigSpec sig_d
, const RTLIL::SigSpec
&sig_q
, bool clk_polarity
, bool en_polarity
, bool set_polarity
, bool clr_polarity
, const std::string
&src
)
2686 RTLIL::Cell
*cell
= addCell(name
, stringf("$_DFFSRE_%c%c%c%c_", clk_polarity
? 'P' : 'N', set_polarity
? 'P' : 'N', clr_polarity
? 'P' : 'N', en_polarity
? 'P' : 'N'));
2687 cell
->setPort(ID::C
, sig_clk
);
2688 cell
->setPort(ID::S
, sig_set
);
2689 cell
->setPort(ID::R
, sig_clr
);
2690 cell
->setPort(ID::E
, sig_en
);
2691 cell
->setPort(ID::D
, sig_d
);
2692 cell
->setPort(ID::Q
, sig_q
);
2693 cell
->set_src_attribute(src
);
2697 RTLIL::Cell
* RTLIL::Module::addAdffGate(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_clk
, const RTLIL::SigSpec
&sig_arst
, const RTLIL::SigSpec
&sig_d
, const RTLIL::SigSpec
&sig_q
,
2698 bool arst_value
, bool clk_polarity
, bool arst_polarity
, const std::string
&src
)
2700 RTLIL::Cell
*cell
= addCell(name
, stringf("$_DFF_%c%c%c_", clk_polarity
? 'P' : 'N', arst_polarity
? 'P' : 'N', arst_value
? '1' : '0'));
2701 cell
->setPort(ID::C
, sig_clk
);
2702 cell
->setPort(ID::R
, sig_arst
);
2703 cell
->setPort(ID::D
, sig_d
);
2704 cell
->setPort(ID::Q
, sig_q
);
2705 cell
->set_src_attribute(src
);
2709 RTLIL::Cell
* RTLIL::Module::addAdffeGate(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_clk
, const RTLIL::SigSpec
&sig_en
, const RTLIL::SigSpec
&sig_arst
, const RTLIL::SigSpec
&sig_d
, const RTLIL::SigSpec
&sig_q
,
2710 bool arst_value
, bool clk_polarity
, bool en_polarity
, bool arst_polarity
, const std::string
&src
)
2712 RTLIL::Cell
*cell
= addCell(name
, stringf("$_DFFE_%c%c%c%c_", clk_polarity
? 'P' : 'N', arst_polarity
? 'P' : 'N', arst_value
? '1' : '0', en_polarity
? 'P' : 'N'));
2713 cell
->setPort(ID::C
, sig_clk
);
2714 cell
->setPort(ID::R
, sig_arst
);
2715 cell
->setPort(ID::E
, sig_en
);
2716 cell
->setPort(ID::D
, sig_d
);
2717 cell
->setPort(ID::Q
, sig_q
);
2718 cell
->set_src_attribute(src
);
2722 RTLIL::Cell
* RTLIL::Module::addSdffGate(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_clk
, const RTLIL::SigSpec
&sig_srst
, const RTLIL::SigSpec
&sig_d
, const RTLIL::SigSpec
&sig_q
,
2723 bool srst_value
, bool clk_polarity
, bool srst_polarity
, const std::string
&src
)
2725 RTLIL::Cell
*cell
= addCell(name
, stringf("$_SDFF_%c%c%c_", clk_polarity
? 'P' : 'N', srst_polarity
? 'P' : 'N', srst_value
? '1' : '0'));
2726 cell
->setPort(ID::C
, sig_clk
);
2727 cell
->setPort(ID::R
, sig_srst
);
2728 cell
->setPort(ID::D
, sig_d
);
2729 cell
->setPort(ID::Q
, sig_q
);
2730 cell
->set_src_attribute(src
);
2734 RTLIL::Cell
* RTLIL::Module::addSdffeGate(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_clk
, const RTLIL::SigSpec
&sig_en
, const RTLIL::SigSpec
&sig_srst
, const RTLIL::SigSpec
&sig_d
, const RTLIL::SigSpec
&sig_q
,
2735 bool srst_value
, bool clk_polarity
, bool en_polarity
, bool srst_polarity
, const std::string
&src
)
2737 RTLIL::Cell
*cell
= addCell(name
, stringf("$_SDFFE_%c%c%c%c_", clk_polarity
? 'P' : 'N', srst_polarity
? 'P' : 'N', srst_value
? '1' : '0', en_polarity
? 'P' : 'N'));
2738 cell
->setPort(ID::C
, sig_clk
);
2739 cell
->setPort(ID::R
, sig_srst
);
2740 cell
->setPort(ID::E
, sig_en
);
2741 cell
->setPort(ID::D
, sig_d
);
2742 cell
->setPort(ID::Q
, sig_q
);
2743 cell
->set_src_attribute(src
);
2747 RTLIL::Cell
* RTLIL::Module::addSdffceGate(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_clk
, const RTLIL::SigSpec
&sig_en
, const RTLIL::SigSpec
&sig_srst
, const RTLIL::SigSpec
&sig_d
, const RTLIL::SigSpec
&sig_q
,
2748 bool srst_value
, bool clk_polarity
, bool en_polarity
, bool srst_polarity
, const std::string
&src
)
2750 RTLIL::Cell
*cell
= addCell(name
, stringf("$_SDFFCE_%c%c%c%c_", clk_polarity
? 'P' : 'N', srst_polarity
? 'P' : 'N', srst_value
? '1' : '0', en_polarity
? 'P' : 'N'));
2751 cell
->setPort(ID::C
, sig_clk
);
2752 cell
->setPort(ID::R
, sig_srst
);
2753 cell
->setPort(ID::E
, sig_en
);
2754 cell
->setPort(ID::D
, sig_d
);
2755 cell
->setPort(ID::Q
, sig_q
);
2756 cell
->set_src_attribute(src
);
2760 RTLIL::Cell
* RTLIL::Module::addDlatchGate(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_en
, const RTLIL::SigSpec
&sig_d
, const RTLIL::SigSpec
&sig_q
, bool en_polarity
, const std::string
&src
)
2762 RTLIL::Cell
*cell
= addCell(name
, stringf("$_DLATCH_%c_", en_polarity
? 'P' : 'N'));
2763 cell
->setPort(ID::E
, sig_en
);
2764 cell
->setPort(ID::D
, sig_d
);
2765 cell
->setPort(ID::Q
, sig_q
);
2766 cell
->set_src_attribute(src
);
2770 RTLIL::Cell
* RTLIL::Module::addAdlatchGate(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_en
, const RTLIL::SigSpec
&sig_arst
, const RTLIL::SigSpec
&sig_d
, const RTLIL::SigSpec
&sig_q
,
2771 bool arst_value
, bool en_polarity
, bool arst_polarity
, const std::string
&src
)
2773 RTLIL::Cell
*cell
= addCell(name
, stringf("$_DLATCH_%c%c%c_", en_polarity
? 'P' : 'N', arst_polarity
? 'P' : 'N', arst_value
? '1' : '0'));
2774 cell
->setPort(ID::E
, sig_en
);
2775 cell
->setPort(ID::R
, sig_arst
);
2776 cell
->setPort(ID::D
, sig_d
);
2777 cell
->setPort(ID::Q
, sig_q
);
2778 cell
->set_src_attribute(src
);
2782 RTLIL::Cell
* RTLIL::Module::addDlatchsrGate(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_en
, const RTLIL::SigSpec
&sig_set
, const RTLIL::SigSpec
&sig_clr
,
2783 RTLIL::SigSpec sig_d
, const RTLIL::SigSpec
&sig_q
, bool en_polarity
, bool set_polarity
, bool clr_polarity
, const std::string
&src
)
2785 RTLIL::Cell
*cell
= addCell(name
, stringf("$_DLATCHSR_%c%c%c_", en_polarity
? 'P' : 'N', set_polarity
? 'P' : 'N', clr_polarity
? 'P' : 'N'));
2786 cell
->setPort(ID::E
, sig_en
);
2787 cell
->setPort(ID::S
, sig_set
);
2788 cell
->setPort(ID::R
, sig_clr
);
2789 cell
->setPort(ID::D
, sig_d
);
2790 cell
->setPort(ID::Q
, sig_q
);
2791 cell
->set_src_attribute(src
);
2795 RTLIL::SigSpec
RTLIL::Module::Anyconst(RTLIL::IdString name
, int width
, const std::string
&src
)
2797 RTLIL::SigSpec sig
= addWire(NEW_ID
, width
);
2798 Cell
*cell
= addCell(name
, ID($anyconst
));
2799 cell
->setParam(ID::WIDTH
, width
);
2800 cell
->setPort(ID::Y
, sig
);
2801 cell
->set_src_attribute(src
);
2805 RTLIL::SigSpec
RTLIL::Module::Anyseq(RTLIL::IdString name
, int width
, const std::string
&src
)
2807 RTLIL::SigSpec sig
= addWire(NEW_ID
, width
);
2808 Cell
*cell
= addCell(name
, ID($anyseq
));
2809 cell
->setParam(ID::WIDTH
, width
);
2810 cell
->setPort(ID::Y
, sig
);
2811 cell
->set_src_attribute(src
);
2815 RTLIL::SigSpec
RTLIL::Module::Allconst(RTLIL::IdString name
, int width
, const std::string
&src
)
2817 RTLIL::SigSpec sig
= addWire(NEW_ID
, width
);
2818 Cell
*cell
= addCell(name
, ID($allconst
));
2819 cell
->setParam(ID::WIDTH
, width
);
2820 cell
->setPort(ID::Y
, sig
);
2821 cell
->set_src_attribute(src
);
2825 RTLIL::SigSpec
RTLIL::Module::Allseq(RTLIL::IdString name
, int width
, const std::string
&src
)
2827 RTLIL::SigSpec sig
= addWire(NEW_ID
, width
);
2828 Cell
*cell
= addCell(name
, ID($allseq
));
2829 cell
->setParam(ID::WIDTH
, width
);
2830 cell
->setPort(ID::Y
, sig
);
2831 cell
->set_src_attribute(src
);
2835 RTLIL::SigSpec
RTLIL::Module::Initstate(RTLIL::IdString name
, const std::string
&src
)
2837 RTLIL::SigSpec sig
= addWire(NEW_ID
);
2838 Cell
*cell
= addCell(name
, ID($initstate
));
2839 cell
->setPort(ID::Y
, sig
);
2840 cell
->set_src_attribute(src
);
2846 static unsigned int hashidx_count
= 123456789;
2847 hashidx_count
= mkhash_xorshift(hashidx_count
);
2848 hashidx_
= hashidx_count
;
2855 port_output
= false;
2860 RTLIL::Wire::get_all_wires()->insert(std::pair
<unsigned int, RTLIL::Wire
*>(hashidx_
, this));
2864 RTLIL::Wire::~Wire()
2867 RTLIL::Wire::get_all_wires()->erase(hashidx_
);
2872 static std::map
<unsigned int, RTLIL::Wire
*> all_wires
;
2873 std::map
<unsigned int, RTLIL::Wire
*> *RTLIL::Wire::get_all_wires(void)
2879 RTLIL::Memory::Memory()
2881 static unsigned int hashidx_count
= 123456789;
2882 hashidx_count
= mkhash_xorshift(hashidx_count
);
2883 hashidx_
= hashidx_count
;
2889 RTLIL::Memory::get_all_memorys()->insert(std::pair
<unsigned int, RTLIL::Memory
*>(hashidx_
, this));
2893 RTLIL::Cell::Cell() : module(nullptr)
2895 static unsigned int hashidx_count
= 123456789;
2896 hashidx_count
= mkhash_xorshift(hashidx_count
);
2897 hashidx_
= hashidx_count
;
2899 // log("#memtrace# %p\n", this);
2903 RTLIL::Cell::get_all_cells()->insert(std::pair
<unsigned int, RTLIL::Cell
*>(hashidx_
, this));
2907 RTLIL::Cell::~Cell()
2910 RTLIL::Cell::get_all_cells()->erase(hashidx_
);
2915 static std::map
<unsigned int, RTLIL::Cell
*> all_cells
;
2916 std::map
<unsigned int, RTLIL::Cell
*> *RTLIL::Cell::get_all_cells(void)
2922 bool RTLIL::Cell::hasPort(RTLIL::IdString portname
) const
2924 return connections_
.count(portname
) != 0;
2927 void RTLIL::Cell::unsetPort(RTLIL::IdString portname
)
2929 RTLIL::SigSpec signal
;
2930 auto conn_it
= connections_
.find(portname
);
2932 if (conn_it
!= connections_
.end())
2934 for (auto mon
: module
->monitors
)
2935 mon
->notify_connect(this, conn_it
->first
, conn_it
->second
, signal
);
2938 for (auto mon
: module
->design
->monitors
)
2939 mon
->notify_connect(this, conn_it
->first
, conn_it
->second
, signal
);
2942 log("#X# Unconnect %s.%s.%s\n", log_id(this->module
), log_id(this), log_id(portname
));
2943 log_backtrace("-X- ", yosys_xtrace
-1);
2946 connections_
.erase(conn_it
);
2950 void RTLIL::Cell::setPort(RTLIL::IdString portname
, RTLIL::SigSpec signal
)
2952 auto r
= connections_
.insert(portname
);
2953 auto conn_it
= r
.first
;
2954 if (!r
.second
&& conn_it
->second
== signal
)
2957 for (auto mon
: module
->monitors
)
2958 mon
->notify_connect(this, conn_it
->first
, conn_it
->second
, signal
);
2961 for (auto mon
: module
->design
->monitors
)
2962 mon
->notify_connect(this, conn_it
->first
, conn_it
->second
, signal
);
2965 log("#X# Connect %s.%s.%s = %s (%d)\n", log_id(this->module
), log_id(this), log_id(portname
), log_signal(signal
), GetSize(signal
));
2966 log_backtrace("-X- ", yosys_xtrace
-1);
2969 conn_it
->second
= std::move(signal
);
2972 const RTLIL::SigSpec
&RTLIL::Cell::getPort(RTLIL::IdString portname
) const
2974 return connections_
.at(portname
);
2977 const dict
<RTLIL::IdString
, RTLIL::SigSpec
> &RTLIL::Cell::connections() const
2979 return connections_
;
2982 bool RTLIL::Cell::known() const
2984 if (yosys_celltypes
.cell_known(type
))
2986 if (module
&& module
->design
&& module
->design
->module(type
))
2991 bool RTLIL::Cell::input(RTLIL::IdString portname
) const
2993 if (yosys_celltypes
.cell_known(type
))
2994 return yosys_celltypes
.cell_input(type
, portname
);
2995 if (module
&& module
->design
) {
2996 RTLIL::Module
*m
= module
->design
->module(type
);
2997 RTLIL::Wire
*w
= m
? m
->wire(portname
) : nullptr;
2998 return w
&& w
->port_input
;
3003 bool RTLIL::Cell::output(RTLIL::IdString portname
) const
3005 if (yosys_celltypes
.cell_known(type
))
3006 return yosys_celltypes
.cell_output(type
, portname
);
3007 if (module
&& module
->design
) {
3008 RTLIL::Module
*m
= module
->design
->module(type
);
3009 RTLIL::Wire
*w
= m
? m
->wire(portname
) : nullptr;
3010 return w
&& w
->port_output
;
3015 bool RTLIL::Cell::hasParam(RTLIL::IdString paramname
) const
3017 return parameters
.count(paramname
) != 0;
3020 void RTLIL::Cell::unsetParam(RTLIL::IdString paramname
)
3022 parameters
.erase(paramname
);
3025 void RTLIL::Cell::setParam(RTLIL::IdString paramname
, RTLIL::Const value
)
3027 parameters
[paramname
] = std::move(value
);
3030 const RTLIL::Const
&RTLIL::Cell::getParam(RTLIL::IdString paramname
) const
3032 const auto &it
= parameters
.find(paramname
);
3033 if (it
!= parameters
.end())
3035 if (module
&& module
->design
) {
3036 RTLIL::Module
*m
= module
->design
->module(type
);
3038 return m
->parameter_default_values
.at(paramname
);
3040 throw std::out_of_range("Cell::getParam()");
3043 void RTLIL::Cell::sort()
3045 connections_
.sort(sort_by_id_str());
3046 parameters
.sort(sort_by_id_str());
3047 attributes
.sort(sort_by_id_str());
3050 void RTLIL::Cell::check()
3053 InternalCellChecker
checker(NULL
, this);
3058 void RTLIL::Cell::fixup_parameters(bool set_a_signed
, bool set_b_signed
)
3060 if (!type
.begins_with("$") || type
.begins_with("$_") || type
.begins_with("$paramod") || type
.begins_with("$fmcombine") ||
3061 type
.begins_with("$verific$") || type
.begins_with("$array:") || type
.begins_with("$extern:"))
3064 if (type
== ID($mux
) || type
== ID($pmux
)) {
3065 parameters
[ID::WIDTH
] = GetSize(connections_
[ID::Y
]);
3066 if (type
== ID($pmux
))
3067 parameters
[ID::S_WIDTH
] = GetSize(connections_
[ID::S
]);
3072 if (type
== ID($lut
) || type
== ID($sop
)) {
3073 parameters
[ID::WIDTH
] = GetSize(connections_
[ID::A
]);
3077 if (type
== ID($fa
)) {
3078 parameters
[ID::WIDTH
] = GetSize(connections_
[ID::Y
]);
3082 if (type
== ID($lcu
)) {
3083 parameters
[ID::WIDTH
] = GetSize(connections_
[ID::CO
]);
3087 bool signedness_ab
= !type
.in(ID($slice
), ID($concat
), ID($macc
));
3089 if (connections_
.count(ID::A
)) {
3090 if (signedness_ab
) {
3092 parameters
[ID::A_SIGNED
] = true;
3093 else if (parameters
.count(ID::A_SIGNED
) == 0)
3094 parameters
[ID::A_SIGNED
] = false;
3096 parameters
[ID::A_WIDTH
] = GetSize(connections_
[ID::A
]);
3099 if (connections_
.count(ID::B
)) {
3100 if (signedness_ab
) {
3102 parameters
[ID::B_SIGNED
] = true;
3103 else if (parameters
.count(ID::B_SIGNED
) == 0)
3104 parameters
[ID::B_SIGNED
] = false;
3106 parameters
[ID::B_WIDTH
] = GetSize(connections_
[ID::B
]);
3109 if (connections_
.count(ID::Y
))
3110 parameters
[ID::Y_WIDTH
] = GetSize(connections_
[ID::Y
]);
3112 if (connections_
.count(ID::Q
))
3113 parameters
[ID::WIDTH
] = GetSize(connections_
[ID::Q
]);
3118 RTLIL::SigChunk::SigChunk()
3125 RTLIL::SigChunk::SigChunk(const RTLIL::Const
&value
)
3129 width
= GetSize(data
);
3133 RTLIL::SigChunk::SigChunk(RTLIL::Wire
*wire
)
3135 log_assert(wire
!= nullptr);
3137 this->width
= wire
->width
;
3141 RTLIL::SigChunk::SigChunk(RTLIL::Wire
*wire
, int offset
, int width
)
3143 log_assert(wire
!= nullptr);
3145 this->width
= width
;
3146 this->offset
= offset
;
3149 RTLIL::SigChunk::SigChunk(const std::string
&str
)
3152 data
= RTLIL::Const(str
).bits
;
3153 width
= GetSize(data
);
3157 RTLIL::SigChunk::SigChunk(int val
, int width
)
3160 data
= RTLIL::Const(val
, width
).bits
;
3161 this->width
= GetSize(data
);
3165 RTLIL::SigChunk::SigChunk(RTLIL::State bit
, int width
)
3168 data
= RTLIL::Const(bit
, width
).bits
;
3169 this->width
= GetSize(data
);
3173 RTLIL::SigChunk::SigChunk(const RTLIL::SigBit
&bit
)
3178 data
= RTLIL::Const(bit
.data
).bits
;
3180 offset
= bit
.offset
;
3184 RTLIL::SigChunk::SigChunk(const RTLIL::SigChunk
&sigchunk
)
3189 RTLIL::SigChunk
RTLIL::SigChunk::extract(int offset
, int length
) const
3191 RTLIL::SigChunk ret
;
3194 ret
.offset
= this->offset
+ offset
;
3197 for (int i
= 0; i
< length
; i
++)
3198 ret
.data
.push_back(data
[offset
+i
]);
3204 bool RTLIL::SigChunk::operator <(const RTLIL::SigChunk
&other
) const
3206 if (wire
&& other
.wire
)
3207 if (wire
->name
!= other
.wire
->name
)
3208 return wire
->name
< other
.wire
->name
;
3210 if (wire
!= other
.wire
)
3211 return wire
< other
.wire
;
3213 if (offset
!= other
.offset
)
3214 return offset
< other
.offset
;
3216 if (width
!= other
.width
)
3217 return width
< other
.width
;
3219 return data
< other
.data
;
3222 bool RTLIL::SigChunk::operator ==(const RTLIL::SigChunk
&other
) const
3224 return wire
== other
.wire
&& width
== other
.width
&& offset
== other
.offset
&& data
== other
.data
;
3227 bool RTLIL::SigChunk::operator !=(const RTLIL::SigChunk
&other
) const
3234 RTLIL::SigSpec::SigSpec()
3240 RTLIL::SigSpec::SigSpec(const RTLIL::SigSpec
&other
)
3245 RTLIL::SigSpec::SigSpec(std::initializer_list
<RTLIL::SigSpec
> parts
)
3247 cover("kernel.rtlil.sigspec.init.list");
3252 log_assert(parts
.size() > 0);
3253 auto ie
= parts
.begin();
3254 auto it
= ie
+ parts
.size() - 1;
3259 RTLIL::SigSpec
&RTLIL::SigSpec::operator=(const RTLIL::SigSpec
&other
)
3261 cover("kernel.rtlil.sigspec.assign");
3263 width_
= other
.width_
;
3264 hash_
= other
.hash_
;
3265 chunks_
= other
.chunks_
;
3266 bits_
= other
.bits_
;
3270 RTLIL::SigSpec::SigSpec(const RTLIL::Const
&value
)
3272 cover("kernel.rtlil.sigspec.init.const");
3274 chunks_
.emplace_back(value
);
3275 width_
= chunks_
.back().width
;
3280 RTLIL::SigSpec::SigSpec(const RTLIL::SigChunk
&chunk
)
3282 cover("kernel.rtlil.sigspec.init.chunk");
3284 chunks_
.emplace_back(chunk
);
3285 width_
= chunks_
.back().width
;
3290 RTLIL::SigSpec::SigSpec(RTLIL::Wire
*wire
)
3292 cover("kernel.rtlil.sigspec.init.wire");
3294 chunks_
.emplace_back(wire
);
3295 width_
= chunks_
.back().width
;
3300 RTLIL::SigSpec::SigSpec(RTLIL::Wire
*wire
, int offset
, int width
)
3302 cover("kernel.rtlil.sigspec.init.wire_part");
3304 chunks_
.emplace_back(wire
, offset
, width
);
3305 width_
= chunks_
.back().width
;
3310 RTLIL::SigSpec::SigSpec(const std::string
&str
)
3312 cover("kernel.rtlil.sigspec.init.str");
3314 chunks_
.emplace_back(str
);
3315 width_
= chunks_
.back().width
;
3320 RTLIL::SigSpec::SigSpec(int val
, int width
)
3322 cover("kernel.rtlil.sigspec.init.int");
3324 chunks_
.emplace_back(val
, width
);
3330 RTLIL::SigSpec::SigSpec(RTLIL::State bit
, int width
)
3332 cover("kernel.rtlil.sigspec.init.state");
3334 chunks_
.emplace_back(bit
, width
);
3340 RTLIL::SigSpec::SigSpec(const RTLIL::SigBit
&bit
, int width
)
3342 cover("kernel.rtlil.sigspec.init.bit");
3344 if (bit
.wire
== NULL
)
3345 chunks_
.emplace_back(bit
.data
, width
);
3347 for (int i
= 0; i
< width
; i
++)
3348 chunks_
.push_back(bit
);
3354 RTLIL::SigSpec::SigSpec(const std::vector
<RTLIL::SigChunk
> &chunks
)
3356 cover("kernel.rtlil.sigspec.init.stdvec_chunks");
3360 for (const auto &c
: chunks
)
3365 RTLIL::SigSpec::SigSpec(const std::vector
<RTLIL::SigBit
> &bits
)
3367 cover("kernel.rtlil.sigspec.init.stdvec_bits");
3371 for (const auto &bit
: bits
)
3376 RTLIL::SigSpec::SigSpec(const pool
<RTLIL::SigBit
> &bits
)
3378 cover("kernel.rtlil.sigspec.init.pool_bits");
3382 for (const auto &bit
: bits
)
3387 RTLIL::SigSpec::SigSpec(const std::set
<RTLIL::SigBit
> &bits
)
3389 cover("kernel.rtlil.sigspec.init.stdset_bits");
3393 for (const auto &bit
: bits
)
3398 RTLIL::SigSpec::SigSpec(bool bit
)
3400 cover("kernel.rtlil.sigspec.init.bool");
3404 append(SigBit(bit
));
3408 void RTLIL::SigSpec::pack() const
3410 RTLIL::SigSpec
*that
= (RTLIL::SigSpec
*)this;
3412 if (that
->bits_
.empty())
3415 cover("kernel.rtlil.sigspec.convert.pack");
3416 log_assert(that
->chunks_
.empty());
3418 std::vector
<RTLIL::SigBit
> old_bits
;
3419 old_bits
.swap(that
->bits_
);
3421 RTLIL::SigChunk
*last
= NULL
;
3422 int last_end_offset
= 0;
3424 for (auto &bit
: old_bits
) {
3425 if (last
&& bit
.wire
== last
->wire
) {
3426 if (bit
.wire
== NULL
) {
3427 last
->data
.push_back(bit
.data
);
3430 } else if (last_end_offset
== bit
.offset
) {
3436 that
->chunks_
.push_back(bit
);
3437 last
= &that
->chunks_
.back();
3438 last_end_offset
= bit
.offset
+ 1;
3444 void RTLIL::SigSpec::unpack() const
3446 RTLIL::SigSpec
*that
= (RTLIL::SigSpec
*)this;
3448 if (that
->chunks_
.empty())
3451 cover("kernel.rtlil.sigspec.convert.unpack");
3452 log_assert(that
->bits_
.empty());
3454 that
->bits_
.reserve(that
->width_
);
3455 for (auto &c
: that
->chunks_
)
3456 for (int i
= 0; i
< c
.width
; i
++)
3457 that
->bits_
.emplace_back(c
, i
);
3459 that
->chunks_
.clear();
3463 void RTLIL::SigSpec::updhash() const
3465 RTLIL::SigSpec
*that
= (RTLIL::SigSpec
*)this;
3467 if (that
->hash_
!= 0)
3470 cover("kernel.rtlil.sigspec.hash");
3473 that
->hash_
= mkhash_init
;
3474 for (auto &c
: that
->chunks_
)
3475 if (c
.wire
== NULL
) {
3476 for (auto &v
: c
.data
)
3477 that
->hash_
= mkhash(that
->hash_
, v
);
3479 that
->hash_
= mkhash(that
->hash_
, c
.wire
->name
.index_
);
3480 that
->hash_
= mkhash(that
->hash_
, c
.offset
);
3481 that
->hash_
= mkhash(that
->hash_
, c
.width
);
3484 if (that
->hash_
== 0)
3488 void RTLIL::SigSpec::sort()
3491 cover("kernel.rtlil.sigspec.sort");
3492 std::sort(bits_
.begin(), bits_
.end());
3495 void RTLIL::SigSpec::sort_and_unify()
3498 cover("kernel.rtlil.sigspec.sort_and_unify");
3500 // A copy of the bits vector is used to prevent duplicating the logic from
3501 // SigSpec::SigSpec(std::vector<SigBit>). This incurrs an extra copy but
3502 // that isn't showing up as significant in profiles.
3503 std::vector
<SigBit
> unique_bits
= bits_
;
3504 std::sort(unique_bits
.begin(), unique_bits
.end());
3505 auto last
= std::unique(unique_bits
.begin(), unique_bits
.end());
3506 unique_bits
.erase(last
, unique_bits
.end());
3508 *this = unique_bits
;
3511 void RTLIL::SigSpec::replace(const RTLIL::SigSpec
&pattern
, const RTLIL::SigSpec
&with
)
3513 replace(pattern
, with
, this);
3516 void RTLIL::SigSpec::replace(const RTLIL::SigSpec
&pattern
, const RTLIL::SigSpec
&with
, RTLIL::SigSpec
*other
) const
3518 log_assert(other
!= NULL
);
3519 log_assert(width_
== other
->width_
);
3520 log_assert(pattern
.width_
== with
.width_
);
3527 for (int i
= 0; i
< GetSize(pattern
.bits_
); i
++) {
3528 if (pattern
.bits_
[i
].wire
!= NULL
) {
3529 for (int j
= 0; j
< GetSize(bits_
); j
++) {
3530 if (bits_
[j
] == pattern
.bits_
[i
]) {
3531 other
->bits_
[j
] = with
.bits_
[i
];
3540 void RTLIL::SigSpec::replace(const dict
<RTLIL::SigBit
, RTLIL::SigBit
> &rules
)
3542 replace(rules
, this);
3545 void RTLIL::SigSpec::replace(const dict
<RTLIL::SigBit
, RTLIL::SigBit
> &rules
, RTLIL::SigSpec
*other
) const
3547 cover("kernel.rtlil.sigspec.replace_dict");
3549 log_assert(other
!= NULL
);
3550 log_assert(width_
== other
->width_
);
3552 if (rules
.empty()) return;
3556 for (int i
= 0; i
< GetSize(bits_
); i
++) {
3557 auto it
= rules
.find(bits_
[i
]);
3558 if (it
!= rules
.end())
3559 other
->bits_
[i
] = it
->second
;
3565 void RTLIL::SigSpec::replace(const std::map
<RTLIL::SigBit
, RTLIL::SigBit
> &rules
)
3567 replace(rules
, this);
3570 void RTLIL::SigSpec::replace(const std::map
<RTLIL::SigBit
, RTLIL::SigBit
> &rules
, RTLIL::SigSpec
*other
) const
3572 cover("kernel.rtlil.sigspec.replace_map");
3574 log_assert(other
!= NULL
);
3575 log_assert(width_
== other
->width_
);
3577 if (rules
.empty()) return;
3581 for (int i
= 0; i
< GetSize(bits_
); i
++) {
3582 auto it
= rules
.find(bits_
[i
]);
3583 if (it
!= rules
.end())
3584 other
->bits_
[i
] = it
->second
;
3590 void RTLIL::SigSpec::remove(const RTLIL::SigSpec
&pattern
)
3592 remove2(pattern
, NULL
);
3595 void RTLIL::SigSpec::remove(const RTLIL::SigSpec
&pattern
, RTLIL::SigSpec
*other
) const
3597 RTLIL::SigSpec tmp
= *this;
3598 tmp
.remove2(pattern
, other
);
3601 void RTLIL::SigSpec::remove2(const RTLIL::SigSpec
&pattern
, RTLIL::SigSpec
*other
)
3604 cover("kernel.rtlil.sigspec.remove_other");
3606 cover("kernel.rtlil.sigspec.remove");
3609 if (other
!= NULL
) {
3610 log_assert(width_
== other
->width_
);
3614 for (int i
= GetSize(bits_
) - 1; i
>= 0; i
--)
3616 if (bits_
[i
].wire
== NULL
) continue;
3618 for (auto &pattern_chunk
: pattern
.chunks())
3619 if (bits_
[i
].wire
== pattern_chunk
.wire
&&
3620 bits_
[i
].offset
>= pattern_chunk
.offset
&&
3621 bits_
[i
].offset
< pattern_chunk
.offset
+ pattern_chunk
.width
) {
3622 bits_
.erase(bits_
.begin() + i
);
3624 if (other
!= NULL
) {
3625 other
->bits_
.erase(other
->bits_
.begin() + i
);
3635 void RTLIL::SigSpec::remove(const pool
<RTLIL::SigBit
> &pattern
)
3637 remove2(pattern
, NULL
);
3640 void RTLIL::SigSpec::remove(const pool
<RTLIL::SigBit
> &pattern
, RTLIL::SigSpec
*other
) const
3642 RTLIL::SigSpec tmp
= *this;
3643 tmp
.remove2(pattern
, other
);
3646 void RTLIL::SigSpec::remove2(const pool
<RTLIL::SigBit
> &pattern
, RTLIL::SigSpec
*other
)
3649 cover("kernel.rtlil.sigspec.remove_other");
3651 cover("kernel.rtlil.sigspec.remove");
3655 if (other
!= NULL
) {
3656 log_assert(width_
== other
->width_
);
3660 for (int i
= GetSize(bits_
) - 1; i
>= 0; i
--) {
3661 if (bits_
[i
].wire
!= NULL
&& pattern
.count(bits_
[i
])) {
3662 bits_
.erase(bits_
.begin() + i
);
3664 if (other
!= NULL
) {
3665 other
->bits_
.erase(other
->bits_
.begin() + i
);
3674 void RTLIL::SigSpec::remove2(const std::set
<RTLIL::SigBit
> &pattern
, RTLIL::SigSpec
*other
)
3677 cover("kernel.rtlil.sigspec.remove_other");
3679 cover("kernel.rtlil.sigspec.remove");
3683 if (other
!= NULL
) {
3684 log_assert(width_
== other
->width_
);
3688 for (int i
= GetSize(bits_
) - 1; i
>= 0; i
--) {
3689 if (bits_
[i
].wire
!= NULL
&& pattern
.count(bits_
[i
])) {
3690 bits_
.erase(bits_
.begin() + i
);
3692 if (other
!= NULL
) {
3693 other
->bits_
.erase(other
->bits_
.begin() + i
);
3702 RTLIL::SigSpec
RTLIL::SigSpec::extract(const RTLIL::SigSpec
&pattern
, const RTLIL::SigSpec
*other
) const
3705 cover("kernel.rtlil.sigspec.extract_other");
3707 cover("kernel.rtlil.sigspec.extract");
3709 log_assert(other
== NULL
|| width_
== other
->width_
);
3712 std::vector
<RTLIL::SigBit
> bits_match
= to_sigbit_vector();
3714 for (auto& pattern_chunk
: pattern
.chunks()) {
3716 std::vector
<RTLIL::SigBit
> bits_other
= other
->to_sigbit_vector();
3717 for (int i
= 0; i
< width_
; i
++)
3718 if (bits_match
[i
].wire
&&
3719 bits_match
[i
].wire
== pattern_chunk
.wire
&&
3720 bits_match
[i
].offset
>= pattern_chunk
.offset
&&
3721 bits_match
[i
].offset
< pattern_chunk
.offset
+ pattern_chunk
.width
)
3722 ret
.append(bits_other
[i
]);
3724 for (int i
= 0; i
< width_
; i
++)
3725 if (bits_match
[i
].wire
&&
3726 bits_match
[i
].wire
== pattern_chunk
.wire
&&
3727 bits_match
[i
].offset
>= pattern_chunk
.offset
&&
3728 bits_match
[i
].offset
< pattern_chunk
.offset
+ pattern_chunk
.width
)
3729 ret
.append(bits_match
[i
]);
3737 RTLIL::SigSpec
RTLIL::SigSpec::extract(const pool
<RTLIL::SigBit
> &pattern
, const RTLIL::SigSpec
*other
) const
3740 cover("kernel.rtlil.sigspec.extract_other");
3742 cover("kernel.rtlil.sigspec.extract");
3744 log_assert(other
== NULL
|| width_
== other
->width_
);
3746 std::vector
<RTLIL::SigBit
> bits_match
= to_sigbit_vector();
3750 std::vector
<RTLIL::SigBit
> bits_other
= other
->to_sigbit_vector();
3751 for (int i
= 0; i
< width_
; i
++)
3752 if (bits_match
[i
].wire
&& pattern
.count(bits_match
[i
]))
3753 ret
.append(bits_other
[i
]);
3755 for (int i
= 0; i
< width_
; i
++)
3756 if (bits_match
[i
].wire
&& pattern
.count(bits_match
[i
]))
3757 ret
.append(bits_match
[i
]);
3764 void RTLIL::SigSpec::replace(int offset
, const RTLIL::SigSpec
&with
)
3766 cover("kernel.rtlil.sigspec.replace_pos");
3771 log_assert(offset
>= 0);
3772 log_assert(with
.width_
>= 0);
3773 log_assert(offset
+with
.width_
<= width_
);
3775 for (int i
= 0; i
< with
.width_
; i
++)
3776 bits_
.at(offset
+ i
) = with
.bits_
.at(i
);
3781 void RTLIL::SigSpec::remove_const()
3785 cover("kernel.rtlil.sigspec.remove_const.packed");
3787 std::vector
<RTLIL::SigChunk
> new_chunks
;
3788 new_chunks
.reserve(GetSize(chunks_
));
3791 for (auto &chunk
: chunks_
)
3792 if (chunk
.wire
!= NULL
) {
3793 new_chunks
.push_back(chunk
);
3794 width_
+= chunk
.width
;
3797 chunks_
.swap(new_chunks
);
3801 cover("kernel.rtlil.sigspec.remove_const.unpacked");
3803 std::vector
<RTLIL::SigBit
> new_bits
;
3804 new_bits
.reserve(width_
);
3806 for (auto &bit
: bits_
)
3807 if (bit
.wire
!= NULL
)
3808 new_bits
.push_back(bit
);
3810 bits_
.swap(new_bits
);
3811 width_
= bits_
.size();
3817 void RTLIL::SigSpec::remove(int offset
, int length
)
3819 cover("kernel.rtlil.sigspec.remove_pos");
3823 log_assert(offset
>= 0);
3824 log_assert(length
>= 0);
3825 log_assert(offset
+ length
<= width_
);
3827 bits_
.erase(bits_
.begin() + offset
, bits_
.begin() + offset
+ length
);
3828 width_
= bits_
.size();
3833 RTLIL::SigSpec
RTLIL::SigSpec::extract(int offset
, int length
) const
3836 cover("kernel.rtlil.sigspec.extract_pos");
3837 return std::vector
<RTLIL::SigBit
>(bits_
.begin() + offset
, bits_
.begin() + offset
+ length
);
3840 void RTLIL::SigSpec::append(const RTLIL::SigSpec
&signal
)
3842 if (signal
.width_
== 0)
3850 cover("kernel.rtlil.sigspec.append");
3852 if (packed() != signal
.packed()) {
3858 for (auto &other_c
: signal
.chunks_
)
3860 auto &my_last_c
= chunks_
.back();
3861 if (my_last_c
.wire
== NULL
&& other_c
.wire
== NULL
) {
3862 auto &this_data
= my_last_c
.data
;
3863 auto &other_data
= other_c
.data
;
3864 this_data
.insert(this_data
.end(), other_data
.begin(), other_data
.end());
3865 my_last_c
.width
+= other_c
.width
;
3867 if (my_last_c
.wire
== other_c
.wire
&& my_last_c
.offset
+ my_last_c
.width
== other_c
.offset
) {
3868 my_last_c
.width
+= other_c
.width
;
3870 chunks_
.push_back(other_c
);
3873 bits_
.insert(bits_
.end(), signal
.bits_
.begin(), signal
.bits_
.end());
3875 width_
+= signal
.width_
;
3879 void RTLIL::SigSpec::append(const RTLIL::SigBit
&bit
)
3883 cover("kernel.rtlil.sigspec.append_bit.packed");
3885 if (chunks_
.size() == 0)
3886 chunks_
.push_back(bit
);
3888 if (bit
.wire
== NULL
)
3889 if (chunks_
.back().wire
== NULL
) {
3890 chunks_
.back().data
.push_back(bit
.data
);
3891 chunks_
.back().width
++;
3893 chunks_
.push_back(bit
);
3895 if (chunks_
.back().wire
== bit
.wire
&& chunks_
.back().offset
+ chunks_
.back().width
== bit
.offset
)
3896 chunks_
.back().width
++;
3898 chunks_
.push_back(bit
);
3902 cover("kernel.rtlil.sigspec.append_bit.unpacked");
3903 bits_
.push_back(bit
);
3910 void RTLIL::SigSpec::extend_u0(int width
, bool is_signed
)
3912 cover("kernel.rtlil.sigspec.extend_u0");
3917 remove(width
, width_
- width
);
3919 if (width_
< width
) {
3920 RTLIL::SigBit padding
= width_
> 0 ? (*this)[width_
- 1] : RTLIL::State::Sx
;
3922 padding
= RTLIL::State::S0
;
3923 while (width_
< width
)
3929 RTLIL::SigSpec
RTLIL::SigSpec::repeat(int num
) const
3931 cover("kernel.rtlil.sigspec.repeat");
3934 for (int i
= 0; i
< num
; i
++)
3940 void RTLIL::SigSpec::check() const
3944 cover("kernel.rtlil.sigspec.check.skip");
3948 cover("kernel.rtlil.sigspec.check.packed");
3951 for (size_t i
= 0; i
< chunks_
.size(); i
++) {
3952 const RTLIL::SigChunk
&chunk
= chunks_
[i
];
3953 if (chunk
.wire
== NULL
) {
3955 log_assert(chunks_
[i
-1].wire
!= NULL
);
3956 log_assert(chunk
.offset
== 0);
3957 log_assert(chunk
.data
.size() == (size_t)chunk
.width
);
3959 if (i
> 0 && chunks_
[i
-1].wire
== chunk
.wire
)
3960 log_assert(chunk
.offset
!= chunks_
[i
-1].offset
+ chunks_
[i
-1].width
);
3961 log_assert(chunk
.offset
>= 0);
3962 log_assert(chunk
.width
>= 0);
3963 log_assert(chunk
.offset
+ chunk
.width
<= chunk
.wire
->width
);
3964 log_assert(chunk
.data
.size() == 0);
3968 log_assert(w
== width_
);
3969 log_assert(bits_
.empty());
3973 cover("kernel.rtlil.sigspec.check.unpacked");
3975 log_assert(width_
== GetSize(bits_
));
3976 log_assert(chunks_
.empty());
3981 bool RTLIL::SigSpec::operator <(const RTLIL::SigSpec
&other
) const
3983 cover("kernel.rtlil.sigspec.comp_lt");
3988 if (width_
!= other
.width_
)
3989 return width_
< other
.width_
;
3994 if (chunks_
.size() != other
.chunks_
.size())
3995 return chunks_
.size() < other
.chunks_
.size();
4000 if (hash_
!= other
.hash_
)
4001 return hash_
< other
.hash_
;
4003 for (size_t i
= 0; i
< chunks_
.size(); i
++)
4004 if (chunks_
[i
] != other
.chunks_
[i
]) {
4005 cover("kernel.rtlil.sigspec.comp_lt.hash_collision");
4006 return chunks_
[i
] < other
.chunks_
[i
];
4009 cover("kernel.rtlil.sigspec.comp_lt.equal");
4013 bool RTLIL::SigSpec::operator ==(const RTLIL::SigSpec
&other
) const
4015 cover("kernel.rtlil.sigspec.comp_eq");
4020 if (width_
!= other
.width_
)
4023 // Without this, SigSpec() == SigSpec(State::S0, 0) will fail
4024 // since the RHS will contain one SigChunk of width 0 causing
4025 // the size check below to fail
4032 if (chunks_
.size() != other
.chunks_
.size())
4038 if (hash_
!= other
.hash_
)
4041 for (size_t i
= 0; i
< chunks_
.size(); i
++)
4042 if (chunks_
[i
] != other
.chunks_
[i
]) {
4043 cover("kernel.rtlil.sigspec.comp_eq.hash_collision");
4047 cover("kernel.rtlil.sigspec.comp_eq.equal");
4051 bool RTLIL::SigSpec::is_wire() const
4053 cover("kernel.rtlil.sigspec.is_wire");
4056 return GetSize(chunks_
) == 1 && chunks_
[0].wire
&& chunks_
[0].wire
->width
== width_
;
4059 bool RTLIL::SigSpec::is_chunk() const
4061 cover("kernel.rtlil.sigspec.is_chunk");
4064 return GetSize(chunks_
) == 1;
4067 bool RTLIL::SigSpec::is_fully_const() const
4069 cover("kernel.rtlil.sigspec.is_fully_const");
4072 for (auto it
= chunks_
.begin(); it
!= chunks_
.end(); it
++)
4073 if (it
->width
> 0 && it
->wire
!= NULL
)
4078 bool RTLIL::SigSpec::is_fully_zero() const
4080 cover("kernel.rtlil.sigspec.is_fully_zero");
4083 for (auto it
= chunks_
.begin(); it
!= chunks_
.end(); it
++) {
4084 if (it
->width
> 0 && it
->wire
!= NULL
)
4086 for (size_t i
= 0; i
< it
->data
.size(); i
++)
4087 if (it
->data
[i
] != RTLIL::State::S0
)
4093 bool RTLIL::SigSpec::is_fully_ones() const
4095 cover("kernel.rtlil.sigspec.is_fully_ones");
4098 for (auto it
= chunks_
.begin(); it
!= chunks_
.end(); it
++) {
4099 if (it
->width
> 0 && it
->wire
!= NULL
)
4101 for (size_t i
= 0; i
< it
->data
.size(); i
++)
4102 if (it
->data
[i
] != RTLIL::State::S1
)
4108 bool RTLIL::SigSpec::is_fully_def() const
4110 cover("kernel.rtlil.sigspec.is_fully_def");
4113 for (auto it
= chunks_
.begin(); it
!= chunks_
.end(); it
++) {
4114 if (it
->width
> 0 && it
->wire
!= NULL
)
4116 for (size_t i
= 0; i
< it
->data
.size(); i
++)
4117 if (it
->data
[i
] != RTLIL::State::S0
&& it
->data
[i
] != RTLIL::State::S1
)
4123 bool RTLIL::SigSpec::is_fully_undef() const
4125 cover("kernel.rtlil.sigspec.is_fully_undef");
4128 for (auto it
= chunks_
.begin(); it
!= chunks_
.end(); it
++) {
4129 if (it
->width
> 0 && it
->wire
!= NULL
)
4131 for (size_t i
= 0; i
< it
->data
.size(); i
++)
4132 if (it
->data
[i
] != RTLIL::State::Sx
&& it
->data
[i
] != RTLIL::State::Sz
)
4138 bool RTLIL::SigSpec::has_const() const
4140 cover("kernel.rtlil.sigspec.has_const");
4143 for (auto it
= chunks_
.begin(); it
!= chunks_
.end(); it
++)
4144 if (it
->width
> 0 && it
->wire
== NULL
)
4149 bool RTLIL::SigSpec::has_marked_bits() const
4151 cover("kernel.rtlil.sigspec.has_marked_bits");
4154 for (auto it
= chunks_
.begin(); it
!= chunks_
.end(); it
++)
4155 if (it
->width
> 0 && it
->wire
== NULL
) {
4156 for (size_t i
= 0; i
< it
->data
.size(); i
++)
4157 if (it
->data
[i
] == RTLIL::State::Sm
)
4163 bool RTLIL::SigSpec::as_bool() const
4165 cover("kernel.rtlil.sigspec.as_bool");
4168 log_assert(is_fully_const() && GetSize(chunks_
) <= 1);
4170 return RTLIL::Const(chunks_
[0].data
).as_bool();
4174 int RTLIL::SigSpec::as_int(bool is_signed
) const
4176 cover("kernel.rtlil.sigspec.as_int");
4179 log_assert(is_fully_const() && GetSize(chunks_
) <= 1);
4181 return RTLIL::Const(chunks_
[0].data
).as_int(is_signed
);
4185 std::string
RTLIL::SigSpec::as_string() const
4187 cover("kernel.rtlil.sigspec.as_string");
4191 str
.reserve(size());
4192 for (size_t i
= chunks_
.size(); i
> 0; i
--) {
4193 const RTLIL::SigChunk
&chunk
= chunks_
[i
-1];
4194 if (chunk
.wire
!= NULL
)
4195 str
.append(chunk
.width
, '?');
4197 str
+= RTLIL::Const(chunk
.data
).as_string();
4202 RTLIL::Const
RTLIL::SigSpec::as_const() const
4204 cover("kernel.rtlil.sigspec.as_const");
4207 log_assert(is_fully_const() && GetSize(chunks_
) <= 1);
4209 return chunks_
[0].data
;
4210 return RTLIL::Const();
4213 RTLIL::Wire
*RTLIL::SigSpec::as_wire() const
4215 cover("kernel.rtlil.sigspec.as_wire");
4218 log_assert(is_wire());
4219 return chunks_
[0].wire
;
4222 RTLIL::SigChunk
RTLIL::SigSpec::as_chunk() const
4224 cover("kernel.rtlil.sigspec.as_chunk");
4227 log_assert(is_chunk());
4231 RTLIL::SigBit
RTLIL::SigSpec::as_bit() const
4233 cover("kernel.rtlil.sigspec.as_bit");
4235 log_assert(width_
== 1);
4237 return RTLIL::SigBit(*chunks_
.begin());
4242 bool RTLIL::SigSpec::match(const char* pattern
) const
4244 cover("kernel.rtlil.sigspec.match");
4247 log_assert(int(strlen(pattern
)) == GetSize(bits_
));
4249 for (auto it
= bits_
.rbegin(); it
!= bits_
.rend(); it
++, pattern
++) {
4250 if (*pattern
== ' ')
4252 if (*pattern
== '*') {
4253 if (*it
!= State::Sz
&& *it
!= State::Sx
)
4257 if (*pattern
== '0') {
4258 if (*it
!= State::S0
)
4261 if (*pattern
== '1') {
4262 if (*it
!= State::S1
)
4271 std::set
<RTLIL::SigBit
> RTLIL::SigSpec::to_sigbit_set() const
4273 cover("kernel.rtlil.sigspec.to_sigbit_set");
4276 std::set
<RTLIL::SigBit
> sigbits
;
4277 for (auto &c
: chunks_
)
4278 for (int i
= 0; i
< c
.width
; i
++)
4279 sigbits
.insert(RTLIL::SigBit(c
, i
));
4283 pool
<RTLIL::SigBit
> RTLIL::SigSpec::to_sigbit_pool() const
4285 cover("kernel.rtlil.sigspec.to_sigbit_pool");
4288 pool
<RTLIL::SigBit
> sigbits
;
4289 sigbits
.reserve(size());
4290 for (auto &c
: chunks_
)
4291 for (int i
= 0; i
< c
.width
; i
++)
4292 sigbits
.insert(RTLIL::SigBit(c
, i
));
4296 std::vector
<RTLIL::SigBit
> RTLIL::SigSpec::to_sigbit_vector() const
4298 cover("kernel.rtlil.sigspec.to_sigbit_vector");
4304 std::map
<RTLIL::SigBit
, RTLIL::SigBit
> RTLIL::SigSpec::to_sigbit_map(const RTLIL::SigSpec
&other
) const
4306 cover("kernel.rtlil.sigspec.to_sigbit_map");
4311 log_assert(width_
== other
.width_
);
4313 std::map
<RTLIL::SigBit
, RTLIL::SigBit
> new_map
;
4314 for (int i
= 0; i
< width_
; i
++)
4315 new_map
[bits_
[i
]] = other
.bits_
[i
];
4320 dict
<RTLIL::SigBit
, RTLIL::SigBit
> RTLIL::SigSpec::to_sigbit_dict(const RTLIL::SigSpec
&other
) const
4322 cover("kernel.rtlil.sigspec.to_sigbit_dict");
4327 log_assert(width_
== other
.width_
);
4329 dict
<RTLIL::SigBit
, RTLIL::SigBit
> new_map
;
4330 new_map
.reserve(size());
4331 for (int i
= 0; i
< width_
; i
++)
4332 new_map
[bits_
[i
]] = other
.bits_
[i
];
4337 static void sigspec_parse_split(std::vector
<std::string
> &tokens
, const std::string
&text
, char sep
)
4339 size_t start
= 0, end
= 0;
4340 while ((end
= text
.find(sep
, start
)) != std::string::npos
) {
4341 tokens
.push_back(text
.substr(start
, end
- start
));
4344 tokens
.push_back(text
.substr(start
));
4347 static int sigspec_parse_get_dummy_line_num()
4352 bool RTLIL::SigSpec::parse(RTLIL::SigSpec
&sig
, RTLIL::Module
*module
, std::string str
)
4354 cover("kernel.rtlil.sigspec.parse");
4356 AST::current_filename
= "input";
4358 std::vector
<std::string
> tokens
;
4359 sigspec_parse_split(tokens
, str
, ',');
4361 sig
= RTLIL::SigSpec();
4362 for (int tokidx
= int(tokens
.size())-1; tokidx
>= 0; tokidx
--)
4364 std::string netname
= tokens
[tokidx
];
4365 std::string indices
;
4367 if (netname
.size() == 0)
4370 if (('0' <= netname
[0] && netname
[0] <= '9') || netname
[0] == '\'') {
4371 cover("kernel.rtlil.sigspec.parse.const");
4372 AST::get_line_num
= sigspec_parse_get_dummy_line_num
;
4373 AST::AstNode
*ast
= VERILOG_FRONTEND::const2ast(netname
);
4376 sig
.append(RTLIL::Const(ast
->bits
));
4384 cover("kernel.rtlil.sigspec.parse.net");
4386 if (netname
[0] != '$' && netname
[0] != '\\')
4387 netname
= "\\" + netname
;
4389 if (module
->wires_
.count(netname
) == 0) {
4390 size_t indices_pos
= netname
.size()-1;
4391 if (indices_pos
> 2 && netname
[indices_pos
] == ']')
4394 while (indices_pos
> 0 && ('0' <= netname
[indices_pos
] && netname
[indices_pos
] <= '9')) indices_pos
--;
4395 if (indices_pos
> 0 && netname
[indices_pos
] == ':') {
4397 while (indices_pos
> 0 && ('0' <= netname
[indices_pos
] && netname
[indices_pos
] <= '9')) indices_pos
--;
4399 if (indices_pos
> 0 && netname
[indices_pos
] == '[') {
4400 indices
= netname
.substr(indices_pos
);
4401 netname
= netname
.substr(0, indices_pos
);
4406 if (module
->wires_
.count(netname
) == 0)
4409 RTLIL::Wire
*wire
= module
->wires_
.at(netname
);
4410 if (!indices
.empty()) {
4411 std::vector
<std::string
> index_tokens
;
4412 sigspec_parse_split(index_tokens
, indices
.substr(1, indices
.size()-2), ':');
4413 if (index_tokens
.size() == 1) {
4414 cover("kernel.rtlil.sigspec.parse.bit_sel");
4415 int a
= atoi(index_tokens
.at(0).c_str());
4416 if (a
< 0 || a
>= wire
->width
)
4418 sig
.append(RTLIL::SigSpec(wire
, a
));
4420 cover("kernel.rtlil.sigspec.parse.part_sel");
4421 int a
= atoi(index_tokens
.at(0).c_str());
4422 int b
= atoi(index_tokens
.at(1).c_str());
4427 if (a
< 0 || a
>= wire
->width
)
4429 if (b
< 0 || b
>= wire
->width
)
4431 sig
.append(RTLIL::SigSpec(wire
, a
, b
-a
+1));
4440 bool RTLIL::SigSpec::parse_sel(RTLIL::SigSpec
&sig
, RTLIL::Design
*design
, RTLIL::Module
*module
, std::string str
)
4442 if (str
.empty() || str
[0] != '@')
4443 return parse(sig
, module
, str
);
4445 cover("kernel.rtlil.sigspec.parse.sel");
4447 str
= RTLIL::escape_id(str
.substr(1));
4448 if (design
->selection_vars
.count(str
) == 0)
4451 sig
= RTLIL::SigSpec();
4452 RTLIL::Selection
&sel
= design
->selection_vars
.at(str
);
4453 for (auto &it
: module
->wires_
)
4454 if (sel
.selected_member(module
->name
, it
.first
))
4455 sig
.append(it
.second
);
4460 bool RTLIL::SigSpec::parse_rhs(const RTLIL::SigSpec
&lhs
, RTLIL::SigSpec
&sig
, RTLIL::Module
*module
, std::string str
)
4463 cover("kernel.rtlil.sigspec.parse.rhs_zeros");
4464 sig
= RTLIL::SigSpec(RTLIL::State::S0
, lhs
.width_
);
4469 cover("kernel.rtlil.sigspec.parse.rhs_ones");
4470 sig
= RTLIL::SigSpec(RTLIL::State::S1
, lhs
.width_
);
4474 if (lhs
.chunks_
.size() == 1) {
4475 char *p
= (char*)str
.c_str(), *endptr
;
4476 long int val
= strtol(p
, &endptr
, 10);
4477 if (endptr
&& endptr
!= p
&& *endptr
== 0) {
4478 sig
= RTLIL::SigSpec(val
, lhs
.width_
);
4479 cover("kernel.rtlil.sigspec.parse.rhs_dec");
4484 return parse(sig
, module
, str
);
4487 RTLIL::CaseRule::~CaseRule()
4489 for (auto it
= switches
.begin(); it
!= switches
.end(); it
++)
4493 bool RTLIL::CaseRule::empty() const
4495 return actions
.empty() && switches
.empty();
4498 RTLIL::CaseRule
*RTLIL::CaseRule::clone() const
4500 RTLIL::CaseRule
*new_caserule
= new RTLIL::CaseRule
;
4501 new_caserule
->compare
= compare
;
4502 new_caserule
->actions
= actions
;
4503 for (auto &it
: switches
)
4504 new_caserule
->switches
.push_back(it
->clone());
4505 return new_caserule
;
4508 RTLIL::SwitchRule::~SwitchRule()
4510 for (auto it
= cases
.begin(); it
!= cases
.end(); it
++)
4514 bool RTLIL::SwitchRule::empty() const
4516 return cases
.empty();
4519 RTLIL::SwitchRule
*RTLIL::SwitchRule::clone() const
4521 RTLIL::SwitchRule
*new_switchrule
= new RTLIL::SwitchRule
;
4522 new_switchrule
->signal
= signal
;
4523 new_switchrule
->attributes
= attributes
;
4524 for (auto &it
: cases
)
4525 new_switchrule
->cases
.push_back(it
->clone());
4526 return new_switchrule
;
4530 RTLIL::SyncRule
*RTLIL::SyncRule::clone() const
4532 RTLIL::SyncRule
*new_syncrule
= new RTLIL::SyncRule
;
4533 new_syncrule
->type
= type
;
4534 new_syncrule
->signal
= signal
;
4535 new_syncrule
->actions
= actions
;
4536 return new_syncrule
;
4539 RTLIL::Process::~Process()
4541 for (auto it
= syncs
.begin(); it
!= syncs
.end(); it
++)
4545 RTLIL::Process
*RTLIL::Process::clone() const
4547 RTLIL::Process
*new_proc
= new RTLIL::Process
;
4549 new_proc
->name
= name
;
4550 new_proc
->attributes
= attributes
;
4552 RTLIL::CaseRule
*rc_ptr
= root_case
.clone();
4553 new_proc
->root_case
= *rc_ptr
;
4554 rc_ptr
->switches
.clear();
4557 for (auto &it
: syncs
)
4558 new_proc
->syncs
.push_back(it
->clone());
4564 RTLIL::Memory::~Memory()
4566 RTLIL::Memory::get_all_memorys()->erase(hashidx_
);
4568 static std::map
<unsigned int, RTLIL::Memory
*> all_memorys
;
4569 std::map
<unsigned int, RTLIL::Memory
*> *RTLIL::Memory::get_all_memorys(void)
4571 return &all_memorys
;