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[yosys.git] / kernel / rtlil.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 #include "kernel/yosys.h"
21 #include "kernel/macc.h"
22 #include "frontends/verilog/verilog_frontend.h"
23 #include "backends/ilang/ilang_backend.h"
24
25 #include <string.h>
26 #include <algorithm>
27
28 YOSYS_NAMESPACE_BEGIN
29
30 RTLIL::IdString::destruct_guard_t RTLIL::IdString::destruct_guard;
31 std::vector<int> RTLIL::IdString::global_refcount_storage_;
32 std::vector<char*> RTLIL::IdString::global_id_storage_;
33 dict<char*, int, hash_cstr_ops> RTLIL::IdString::global_id_index_;
34 std::vector<int> RTLIL::IdString::global_free_idx_list_;
35
36 RTLIL::Const::Const()
37 {
38 flags = RTLIL::CONST_FLAG_NONE;
39 }
40
41 RTLIL::Const::Const(std::string str)
42 {
43 flags = RTLIL::CONST_FLAG_STRING;
44 for (int i = str.size()-1; i >= 0; i--) {
45 unsigned char ch = str[i];
46 for (int j = 0; j < 8; j++) {
47 bits.push_back((ch & 1) != 0 ? RTLIL::S1 : RTLIL::S0);
48 ch = ch >> 1;
49 }
50 }
51 }
52
53 RTLIL::Const::Const(int val, int width)
54 {
55 flags = RTLIL::CONST_FLAG_NONE;
56 for (int i = 0; i < width; i++) {
57 bits.push_back((val & 1) != 0 ? RTLIL::S1 : RTLIL::S0);
58 val = val >> 1;
59 }
60 }
61
62 RTLIL::Const::Const(RTLIL::State bit, int width)
63 {
64 flags = RTLIL::CONST_FLAG_NONE;
65 for (int i = 0; i < width; i++)
66 bits.push_back(bit);
67 }
68
69 RTLIL::Const::Const(const std::vector<bool> &bits)
70 {
71 flags = RTLIL::CONST_FLAG_NONE;
72 for (auto b : bits)
73 this->bits.push_back(b ? RTLIL::S1 : RTLIL::S0);
74 }
75
76 bool RTLIL::Const::operator <(const RTLIL::Const &other) const
77 {
78 if (bits.size() != other.bits.size())
79 return bits.size() < other.bits.size();
80 for (size_t i = 0; i < bits.size(); i++)
81 if (bits[i] != other.bits[i])
82 return bits[i] < other.bits[i];
83 return false;
84 }
85
86 bool RTLIL::Const::operator ==(const RTLIL::Const &other) const
87 {
88 return bits == other.bits;
89 }
90
91 bool RTLIL::Const::operator !=(const RTLIL::Const &other) const
92 {
93 return bits != other.bits;
94 }
95
96 bool RTLIL::Const::as_bool() const
97 {
98 for (size_t i = 0; i < bits.size(); i++)
99 if (bits[i] == RTLIL::S1)
100 return true;
101 return false;
102 }
103
104 int RTLIL::Const::as_int(bool is_signed) const
105 {
106 int32_t ret = 0;
107 for (size_t i = 0; i < bits.size() && i < 32; i++)
108 if (bits[i] == RTLIL::S1)
109 ret |= 1 << i;
110 if (is_signed && bits.back() == RTLIL::S1)
111 for (size_t i = bits.size(); i < 32; i++)
112 ret |= 1 << i;
113 return ret;
114 }
115
116 std::string RTLIL::Const::as_string() const
117 {
118 std::string ret;
119 for (size_t i = bits.size(); i > 0; i--)
120 switch (bits[i-1]) {
121 case S0: ret += "0"; break;
122 case S1: ret += "1"; break;
123 case Sx: ret += "x"; break;
124 case Sz: ret += "z"; break;
125 case Sa: ret += "-"; break;
126 case Sm: ret += "m"; break;
127 }
128 return ret;
129 }
130
131 std::string RTLIL::Const::decode_string() const
132 {
133 std::string string;
134 std::vector <char> string_chars;
135 for (int i = 0; i < int (bits.size()); i += 8) {
136 char ch = 0;
137 for (int j = 0; j < 8 && i + j < int (bits.size()); j++)
138 if (bits[i + j] == RTLIL::State::S1)
139 ch |= 1 << j;
140 if (ch != 0)
141 string_chars.push_back(ch);
142 }
143 for (int i = int (string_chars.size()) - 1; i >= 0; i--)
144 string += string_chars[i];
145 return string;
146 }
147
148 bool RTLIL::Selection::selected_module(RTLIL::IdString mod_name) const
149 {
150 if (full_selection)
151 return true;
152 if (selected_modules.count(mod_name) > 0)
153 return true;
154 if (selected_members.count(mod_name) > 0)
155 return true;
156 return false;
157 }
158
159 bool RTLIL::Selection::selected_whole_module(RTLIL::IdString mod_name) const
160 {
161 if (full_selection)
162 return true;
163 if (selected_modules.count(mod_name) > 0)
164 return true;
165 return false;
166 }
167
168 bool RTLIL::Selection::selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const
169 {
170 if (full_selection)
171 return true;
172 if (selected_modules.count(mod_name) > 0)
173 return true;
174 if (selected_members.count(mod_name) > 0)
175 if (selected_members.at(mod_name).count(memb_name) > 0)
176 return true;
177 return false;
178 }
179
180 void RTLIL::Selection::optimize(RTLIL::Design *design)
181 {
182 if (full_selection) {
183 selected_modules.clear();
184 selected_members.clear();
185 return;
186 }
187
188 std::vector<RTLIL::IdString> del_list, add_list;
189
190 del_list.clear();
191 for (auto mod_name : selected_modules) {
192 if (design->modules_.count(mod_name) == 0)
193 del_list.push_back(mod_name);
194 selected_members.erase(mod_name);
195 }
196 for (auto mod_name : del_list)
197 selected_modules.erase(mod_name);
198
199 del_list.clear();
200 for (auto &it : selected_members)
201 if (design->modules_.count(it.first) == 0)
202 del_list.push_back(it.first);
203 for (auto mod_name : del_list)
204 selected_members.erase(mod_name);
205
206 for (auto &it : selected_members) {
207 del_list.clear();
208 for (auto memb_name : it.second)
209 if (design->modules_[it.first]->count_id(memb_name) == 0)
210 del_list.push_back(memb_name);
211 for (auto memb_name : del_list)
212 it.second.erase(memb_name);
213 }
214
215 del_list.clear();
216 add_list.clear();
217 for (auto &it : selected_members)
218 if (it.second.size() == 0)
219 del_list.push_back(it.first);
220 else if (it.second.size() == design->modules_[it.first]->wires_.size() + design->modules_[it.first]->memories.size() +
221 design->modules_[it.first]->cells_.size() + design->modules_[it.first]->processes.size())
222 add_list.push_back(it.first);
223 for (auto mod_name : del_list)
224 selected_members.erase(mod_name);
225 for (auto mod_name : add_list) {
226 selected_members.erase(mod_name);
227 selected_modules.insert(mod_name);
228 }
229
230 if (selected_modules.size() == design->modules_.size()) {
231 full_selection = true;
232 selected_modules.clear();
233 selected_members.clear();
234 }
235 }
236
237 RTLIL::Design::Design()
238 {
239 static unsigned int hashidx_count = 123456789;
240 hashidx_count = mkhash_xorshift(hashidx_count);
241 hashidx_ = hashidx_count;
242
243 refcount_modules_ = 0;
244 selection_stack.push_back(RTLIL::Selection());
245 }
246
247 RTLIL::Design::~Design()
248 {
249 for (auto it = modules_.begin(); it != modules_.end(); ++it)
250 delete it->second;
251 }
252
253 RTLIL::ObjRange<RTLIL::Module*> RTLIL::Design::modules()
254 {
255 return RTLIL::ObjRange<RTLIL::Module*>(&modules_, &refcount_modules_);
256 }
257
258 RTLIL::Module *RTLIL::Design::module(RTLIL::IdString name)
259 {
260 return modules_.count(name) ? modules_.at(name) : NULL;
261 }
262
263 void RTLIL::Design::add(RTLIL::Module *module)
264 {
265 log_assert(modules_.count(module->name) == 0);
266 log_assert(refcount_modules_ == 0);
267 modules_[module->name] = module;
268 module->design = this;
269
270 for (auto mon : monitors)
271 mon->notify_module_add(module);
272 }
273
274 RTLIL::Module *RTLIL::Design::addModule(RTLIL::IdString name)
275 {
276 log_assert(modules_.count(name) == 0);
277 log_assert(refcount_modules_ == 0);
278
279 RTLIL::Module *module = new RTLIL::Module;
280 modules_[name] = module;
281 module->design = this;
282 module->name = name;
283
284 for (auto mon : monitors)
285 mon->notify_module_add(module);
286
287 return module;
288 }
289
290 void RTLIL::Design::scratchpad_unset(std::string varname)
291 {
292 scratchpad.erase(varname);
293 }
294
295 void RTLIL::Design::scratchpad_set_int(std::string varname, int value)
296 {
297 scratchpad[varname] = stringf("%d", value);
298 }
299
300 void RTLIL::Design::scratchpad_set_bool(std::string varname, bool value)
301 {
302 scratchpad[varname] = value ? "true" : "false";
303 }
304
305 void RTLIL::Design::scratchpad_set_string(std::string varname, std::string value)
306 {
307 scratchpad[varname] = value;
308 }
309
310 int RTLIL::Design::scratchpad_get_int(std::string varname, int default_value) const
311 {
312 if (scratchpad.count(varname) == 0)
313 return default_value;
314
315 std::string str = scratchpad.at(varname);
316
317 if (str == "0" || str == "false")
318 return 0;
319
320 if (str == "1" || str == "true")
321 return 1;
322
323 char *endptr = nullptr;
324 long int parsed_value = strtol(str.c_str(), &endptr, 10);
325 return *endptr ? default_value : parsed_value;
326 }
327
328 bool RTLIL::Design::scratchpad_get_bool(std::string varname, bool default_value) const
329 {
330 if (scratchpad.count(varname) == 0)
331 return default_value;
332
333 std::string str = scratchpad.at(varname);
334
335 if (str == "0" || str == "false")
336 return false;
337
338 if (str == "1" || str == "true")
339 return true;
340
341 return default_value;
342 }
343
344 std::string RTLIL::Design::scratchpad_get_string(std::string varname, std::string default_value) const
345 {
346 if (scratchpad.count(varname) == 0)
347 return default_value;
348 return scratchpad.at(varname);
349 }
350
351 void RTLIL::Design::remove(RTLIL::Module *module)
352 {
353 for (auto mon : monitors)
354 mon->notify_module_del(module);
355
356 log_assert(modules_.at(module->name) == module);
357 modules_.erase(module->name);
358 delete module;
359 }
360
361 void RTLIL::Design::check()
362 {
363 #ifndef NDEBUG
364 for (auto &it : modules_) {
365 log_assert(this == it.second->design);
366 log_assert(it.first == it.second->name);
367 log_assert(!it.first.empty());
368 it.second->check();
369 }
370 #endif
371 }
372
373 void RTLIL::Design::optimize()
374 {
375 for (auto &it : modules_)
376 it.second->optimize();
377 for (auto &it : selection_stack)
378 it.optimize(this);
379 for (auto &it : selection_vars)
380 it.second.optimize(this);
381 }
382
383 bool RTLIL::Design::selected_module(RTLIL::IdString mod_name) const
384 {
385 if (!selected_active_module.empty() && mod_name != selected_active_module)
386 return false;
387 if (selection_stack.size() == 0)
388 return true;
389 return selection_stack.back().selected_module(mod_name);
390 }
391
392 bool RTLIL::Design::selected_whole_module(RTLIL::IdString mod_name) const
393 {
394 if (!selected_active_module.empty() && mod_name != selected_active_module)
395 return false;
396 if (selection_stack.size() == 0)
397 return true;
398 return selection_stack.back().selected_whole_module(mod_name);
399 }
400
401 bool RTLIL::Design::selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const
402 {
403 if (!selected_active_module.empty() && mod_name != selected_active_module)
404 return false;
405 if (selection_stack.size() == 0)
406 return true;
407 return selection_stack.back().selected_member(mod_name, memb_name);
408 }
409
410 bool RTLIL::Design::selected_module(RTLIL::Module *mod) const
411 {
412 return selected_module(mod->name);
413 }
414
415 bool RTLIL::Design::selected_whole_module(RTLIL::Module *mod) const
416 {
417 return selected_whole_module(mod->name);
418 }
419
420 std::vector<RTLIL::Module*> RTLIL::Design::selected_modules() const
421 {
422 std::vector<RTLIL::Module*> result;
423 result.reserve(modules_.size());
424 for (auto &it : modules_)
425 if (selected_module(it.first))
426 result.push_back(it.second);
427 return result;
428 }
429
430 std::vector<RTLIL::Module*> RTLIL::Design::selected_whole_modules() const
431 {
432 std::vector<RTLIL::Module*> result;
433 result.reserve(modules_.size());
434 for (auto &it : modules_)
435 if (selected_whole_module(it.first))
436 result.push_back(it.second);
437 return result;
438 }
439
440 std::vector<RTLIL::Module*> RTLIL::Design::selected_whole_modules_warn() const
441 {
442 std::vector<RTLIL::Module*> result;
443 result.reserve(modules_.size());
444 for (auto &it : modules_)
445 if (selected_whole_module(it.first))
446 result.push_back(it.second);
447 else if (selected_module(it.first))
448 log_warning("Ignoring partially selected module %s.\n", log_id(it.first));
449 return result;
450 }
451
452 RTLIL::Module::Module()
453 {
454 static unsigned int hashidx_count = 123456789;
455 hashidx_count = mkhash_xorshift(hashidx_count);
456 hashidx_ = hashidx_count;
457
458 design = nullptr;
459 refcount_wires_ = 0;
460 refcount_cells_ = 0;
461 }
462
463 RTLIL::Module::~Module()
464 {
465 for (auto it = wires_.begin(); it != wires_.end(); ++it)
466 delete it->second;
467 for (auto it = memories.begin(); it != memories.end(); ++it)
468 delete it->second;
469 for (auto it = cells_.begin(); it != cells_.end(); ++it)
470 delete it->second;
471 for (auto it = processes.begin(); it != processes.end(); ++it)
472 delete it->second;
473 }
474
475 RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, dict<RTLIL::IdString, RTLIL::Const>)
476 {
477 log_error("Module `%s' is used with parameters but is not parametric!\n", id2cstr(name));
478 }
479
480 size_t RTLIL::Module::count_id(RTLIL::IdString id)
481 {
482 return wires_.count(id) + memories.count(id) + cells_.count(id) + processes.count(id);
483 }
484
485 #ifndef NDEBUG
486 namespace {
487 struct InternalCellChecker
488 {
489 RTLIL::Module *module;
490 RTLIL::Cell *cell;
491 pool<RTLIL::IdString> expected_params, expected_ports;
492
493 InternalCellChecker(RTLIL::Module *module, RTLIL::Cell *cell) : module(module), cell(cell) { }
494
495 void error(int linenr)
496 {
497 std::stringstream buf;
498 ILANG_BACKEND::dump_cell(buf, " ", cell);
499
500 log_error("Found error in internal cell %s%s%s (%s) at %s:%d:\n%s",
501 module ? module->name.c_str() : "", module ? "." : "",
502 cell->name.c_str(), cell->type.c_str(), __FILE__, linenr, buf.str().c_str());
503 }
504
505 int param(const char *name)
506 {
507 if (cell->parameters.count(name) == 0)
508 error(__LINE__);
509 expected_params.insert(name);
510 return cell->parameters.at(name).as_int();
511 }
512
513 int param_bool(const char *name)
514 {
515 int v = param(name);
516 if (cell->parameters.at(name).bits.size() > 32)
517 error(__LINE__);
518 if (v != 0 && v != 1)
519 error(__LINE__);
520 return v;
521 }
522
523 void param_bits(const char *name, int width)
524 {
525 param(name);
526 if (int(cell->parameters.at(name).bits.size()) != width)
527 error(__LINE__);
528 }
529
530 void port(const char *name, int width)
531 {
532 if (!cell->hasPort(name))
533 error(__LINE__);
534 if (cell->getPort(name).size() != width)
535 error(__LINE__);
536 expected_ports.insert(name);
537 }
538
539 void check_expected(bool check_matched_sign = true)
540 {
541 for (auto &para : cell->parameters)
542 if (expected_params.count(para.first) == 0)
543 error(__LINE__);
544 for (auto &conn : cell->connections())
545 if (expected_ports.count(conn.first) == 0)
546 error(__LINE__);
547
548 if (expected_params.count("\\A_SIGNED") != 0 && expected_params.count("\\B_SIGNED") && check_matched_sign) {
549 bool a_is_signed = param("\\A_SIGNED") != 0;
550 bool b_is_signed = param("\\B_SIGNED") != 0;
551 if (a_is_signed != b_is_signed)
552 error(__LINE__);
553 }
554 }
555
556 void check_gate(const char *ports)
557 {
558 if (cell->parameters.size() != 0)
559 error(__LINE__);
560
561 for (const char *p = ports; *p; p++) {
562 char portname[3] = { '\\', *p, 0 };
563 if (!cell->hasPort(portname))
564 error(__LINE__);
565 if (cell->getPort(portname).size() != 1)
566 error(__LINE__);
567 }
568
569 for (auto &conn : cell->connections()) {
570 if (conn.first.size() != 2 || conn.first[0] != '\\')
571 error(__LINE__);
572 if (strchr(ports, conn.first[1]) == NULL)
573 error(__LINE__);
574 }
575 }
576
577 void check()
578 {
579 if (cell->type.substr(0, 1) != "$" || cell->type.substr(0, 3) == "$__" || cell->type.substr(0, 8) == "$paramod" ||
580 cell->type.substr(0, 9) == "$verific$" || cell->type.substr(0, 7) == "$array:" || cell->type.substr(0, 8) == "$extern:")
581 return;
582
583 if (cell->type.in("$not", "$pos", "$neg")) {
584 param_bool("\\A_SIGNED");
585 port("\\A", param("\\A_WIDTH"));
586 port("\\Y", param("\\Y_WIDTH"));
587 check_expected();
588 return;
589 }
590
591 if (cell->type.in("$and", "$or", "$xor", "$xnor")) {
592 param_bool("\\A_SIGNED");
593 param_bool("\\B_SIGNED");
594 port("\\A", param("\\A_WIDTH"));
595 port("\\B", param("\\B_WIDTH"));
596 port("\\Y", param("\\Y_WIDTH"));
597 check_expected();
598 return;
599 }
600
601 if (cell->type.in("$reduce_and", "$reduce_or", "$reduce_xor", "$reduce_xnor", "$reduce_bool")) {
602 param_bool("\\A_SIGNED");
603 port("\\A", param("\\A_WIDTH"));
604 port("\\Y", param("\\Y_WIDTH"));
605 check_expected();
606 return;
607 }
608
609 if (cell->type.in("$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx")) {
610 param_bool("\\A_SIGNED");
611 param_bool("\\B_SIGNED");
612 port("\\A", param("\\A_WIDTH"));
613 port("\\B", param("\\B_WIDTH"));
614 port("\\Y", param("\\Y_WIDTH"));
615 check_expected(false);
616 return;
617 }
618
619 if (cell->type.in("$lt", "$le", "$eq", "$ne", "$eqx", "$nex", "$ge", "$gt")) {
620 param_bool("\\A_SIGNED");
621 param_bool("\\B_SIGNED");
622 port("\\A", param("\\A_WIDTH"));
623 port("\\B", param("\\B_WIDTH"));
624 port("\\Y", param("\\Y_WIDTH"));
625 check_expected();
626 return;
627 }
628
629 if (cell->type.in("$add", "$sub", "$mul", "$div", "$mod", "$pow")) {
630 param_bool("\\A_SIGNED");
631 param_bool("\\B_SIGNED");
632 port("\\A", param("\\A_WIDTH"));
633 port("\\B", param("\\B_WIDTH"));
634 port("\\Y", param("\\Y_WIDTH"));
635 check_expected(cell->type != "$pow");
636 return;
637 }
638
639 if (cell->type == "$fa") {
640 port("\\A", param("\\WIDTH"));
641 port("\\B", param("\\WIDTH"));
642 port("\\C", param("\\WIDTH"));
643 port("\\X", param("\\WIDTH"));
644 port("\\Y", param("\\WIDTH"));
645 check_expected();
646 return;
647 }
648
649 if (cell->type == "$lcu") {
650 port("\\P", param("\\WIDTH"));
651 port("\\G", param("\\WIDTH"));
652 port("\\CI", 1);
653 port("\\CO", param("\\WIDTH"));
654 check_expected();
655 return;
656 }
657
658 if (cell->type == "$alu") {
659 param_bool("\\A_SIGNED");
660 param_bool("\\B_SIGNED");
661 port("\\A", param("\\A_WIDTH"));
662 port("\\B", param("\\B_WIDTH"));
663 port("\\CI", 1);
664 port("\\BI", 1);
665 port("\\X", param("\\Y_WIDTH"));
666 port("\\Y", param("\\Y_WIDTH"));
667 port("\\CO", param("\\Y_WIDTH"));
668 check_expected();
669 return;
670 }
671
672 if (cell->type == "$macc") {
673 param("\\CONFIG");
674 param("\\CONFIG_WIDTH");
675 port("\\A", param("\\A_WIDTH"));
676 port("\\B", param("\\B_WIDTH"));
677 port("\\Y", param("\\Y_WIDTH"));
678 check_expected();
679 Macc().from_cell(cell);
680 return;
681 }
682
683 if (cell->type == "$logic_not") {
684 param_bool("\\A_SIGNED");
685 port("\\A", param("\\A_WIDTH"));
686 port("\\Y", param("\\Y_WIDTH"));
687 check_expected();
688 return;
689 }
690
691 if (cell->type == "$logic_and" || cell->type == "$logic_or") {
692 param_bool("\\A_SIGNED");
693 param_bool("\\B_SIGNED");
694 port("\\A", param("\\A_WIDTH"));
695 port("\\B", param("\\B_WIDTH"));
696 port("\\Y", param("\\Y_WIDTH"));
697 check_expected(false);
698 return;
699 }
700
701 if (cell->type == "$slice") {
702 param("\\OFFSET");
703 port("\\A", param("\\A_WIDTH"));
704 port("\\Y", param("\\Y_WIDTH"));
705 if (param("\\OFFSET") + param("\\Y_WIDTH") > param("\\A_WIDTH"))
706 error(__LINE__);
707 check_expected();
708 return;
709 }
710
711 if (cell->type == "$concat") {
712 port("\\A", param("\\A_WIDTH"));
713 port("\\B", param("\\B_WIDTH"));
714 port("\\Y", param("\\A_WIDTH") + param("\\B_WIDTH"));
715 check_expected();
716 return;
717 }
718
719 if (cell->type == "$mux") {
720 port("\\A", param("\\WIDTH"));
721 port("\\B", param("\\WIDTH"));
722 port("\\S", 1);
723 port("\\Y", param("\\WIDTH"));
724 check_expected();
725 return;
726 }
727
728 if (cell->type == "$pmux") {
729 port("\\A", param("\\WIDTH"));
730 port("\\B", param("\\WIDTH") * param("\\S_WIDTH"));
731 port("\\S", param("\\S_WIDTH"));
732 port("\\Y", param("\\WIDTH"));
733 check_expected();
734 return;
735 }
736
737 if (cell->type == "$lut") {
738 param("\\LUT");
739 port("\\A", param("\\WIDTH"));
740 port("\\Y", 1);
741 check_expected();
742 return;
743 }
744
745 if (cell->type == "$sr") {
746 param_bool("\\SET_POLARITY");
747 param_bool("\\CLR_POLARITY");
748 port("\\SET", param("\\WIDTH"));
749 port("\\CLR", param("\\WIDTH"));
750 port("\\Q", param("\\WIDTH"));
751 check_expected();
752 return;
753 }
754
755 if (cell->type == "$dff") {
756 param_bool("\\CLK_POLARITY");
757 port("\\CLK", 1);
758 port("\\D", param("\\WIDTH"));
759 port("\\Q", param("\\WIDTH"));
760 check_expected();
761 return;
762 }
763
764 if (cell->type == "$dffe") {
765 param_bool("\\CLK_POLARITY");
766 param_bool("\\EN_POLARITY");
767 port("\\CLK", 1);
768 port("\\EN", 1);
769 port("\\D", param("\\WIDTH"));
770 port("\\Q", param("\\WIDTH"));
771 check_expected();
772 return;
773 }
774
775 if (cell->type == "$dffsr") {
776 param_bool("\\CLK_POLARITY");
777 param_bool("\\SET_POLARITY");
778 param_bool("\\CLR_POLARITY");
779 port("\\CLK", 1);
780 port("\\SET", param("\\WIDTH"));
781 port("\\CLR", param("\\WIDTH"));
782 port("\\D", param("\\WIDTH"));
783 port("\\Q", param("\\WIDTH"));
784 check_expected();
785 return;
786 }
787
788 if (cell->type == "$adff") {
789 param_bool("\\CLK_POLARITY");
790 param_bool("\\ARST_POLARITY");
791 param_bits("\\ARST_VALUE", param("\\WIDTH"));
792 port("\\CLK", 1);
793 port("\\ARST", 1);
794 port("\\D", param("\\WIDTH"));
795 port("\\Q", param("\\WIDTH"));
796 check_expected();
797 return;
798 }
799
800 if (cell->type == "$dlatch") {
801 param_bool("\\EN_POLARITY");
802 port("\\EN", 1);
803 port("\\D", param("\\WIDTH"));
804 port("\\Q", param("\\WIDTH"));
805 check_expected();
806 return;
807 }
808
809 if (cell->type == "$dlatchsr") {
810 param_bool("\\EN_POLARITY");
811 param_bool("\\SET_POLARITY");
812 param_bool("\\CLR_POLARITY");
813 port("\\EN", 1);
814 port("\\SET", param("\\WIDTH"));
815 port("\\CLR", param("\\WIDTH"));
816 port("\\D", param("\\WIDTH"));
817 port("\\Q", param("\\WIDTH"));
818 check_expected();
819 return;
820 }
821
822 if (cell->type == "$fsm") {
823 param("\\NAME");
824 param_bool("\\CLK_POLARITY");
825 param_bool("\\ARST_POLARITY");
826 param("\\STATE_BITS");
827 param("\\STATE_NUM");
828 param("\\STATE_NUM_LOG2");
829 param("\\STATE_RST");
830 param_bits("\\STATE_TABLE", param("\\STATE_BITS") * param("\\STATE_NUM"));
831 param("\\TRANS_NUM");
832 param_bits("\\TRANS_TABLE", param("\\TRANS_NUM") * (2*param("\\STATE_NUM_LOG2") + param("\\CTRL_IN_WIDTH") + param("\\CTRL_OUT_WIDTH")));
833 port("\\CLK", 1);
834 port("\\ARST", 1);
835 port("\\CTRL_IN", param("\\CTRL_IN_WIDTH"));
836 port("\\CTRL_OUT", param("\\CTRL_OUT_WIDTH"));
837 check_expected();
838 return;
839 }
840
841 if (cell->type == "$memrd") {
842 param("\\MEMID");
843 param_bool("\\CLK_ENABLE");
844 param_bool("\\CLK_POLARITY");
845 param_bool("\\TRANSPARENT");
846 port("\\CLK", 1);
847 port("\\ADDR", param("\\ABITS"));
848 port("\\DATA", param("\\WIDTH"));
849 check_expected();
850 return;
851 }
852
853 if (cell->type == "$memwr") {
854 param("\\MEMID");
855 param_bool("\\CLK_ENABLE");
856 param_bool("\\CLK_POLARITY");
857 param("\\PRIORITY");
858 port("\\CLK", 1);
859 port("\\EN", param("\\WIDTH"));
860 port("\\ADDR", param("\\ABITS"));
861 port("\\DATA", param("\\WIDTH"));
862 check_expected();
863 return;
864 }
865
866 if (cell->type == "$mem") {
867 param("\\MEMID");
868 param("\\SIZE");
869 param("\\OFFSET");
870 param_bits("\\RD_CLK_ENABLE", param("\\RD_PORTS"));
871 param_bits("\\RD_CLK_POLARITY", param("\\RD_PORTS"));
872 param_bits("\\RD_TRANSPARENT", param("\\RD_PORTS"));
873 param_bits("\\WR_CLK_ENABLE", param("\\WR_PORTS"));
874 param_bits("\\WR_CLK_POLARITY", param("\\WR_PORTS"));
875 port("\\RD_CLK", param("\\RD_PORTS"));
876 port("\\RD_ADDR", param("\\RD_PORTS") * param("\\ABITS"));
877 port("\\RD_DATA", param("\\RD_PORTS") * param("\\WIDTH"));
878 port("\\WR_CLK", param("\\WR_PORTS"));
879 port("\\WR_EN", param("\\WR_PORTS") * param("\\WIDTH"));
880 port("\\WR_ADDR", param("\\WR_PORTS") * param("\\ABITS"));
881 port("\\WR_DATA", param("\\WR_PORTS") * param("\\WIDTH"));
882 check_expected();
883 return;
884 }
885
886 if (cell->type == "$assert") {
887 port("\\A", 1);
888 port("\\EN", 1);
889 check_expected();
890 return;
891 }
892
893 if (cell->type == "$_BUF_") { check_gate("AY"); return; }
894 if (cell->type == "$_NOT_") { check_gate("AY"); return; }
895 if (cell->type == "$_AND_") { check_gate("ABY"); return; }
896 if (cell->type == "$_NAND_") { check_gate("ABY"); return; }
897 if (cell->type == "$_OR_") { check_gate("ABY"); return; }
898 if (cell->type == "$_NOR_") { check_gate("ABY"); return; }
899 if (cell->type == "$_XOR_") { check_gate("ABY"); return; }
900 if (cell->type == "$_XNOR_") { check_gate("ABY"); return; }
901 if (cell->type == "$_MUX_") { check_gate("ABSY"); return; }
902 if (cell->type == "$_AOI3_") { check_gate("ABCY"); return; }
903 if (cell->type == "$_OAI3_") { check_gate("ABCY"); return; }
904 if (cell->type == "$_AOI4_") { check_gate("ABCDY"); return; }
905 if (cell->type == "$_OAI4_") { check_gate("ABCDY"); return; }
906
907 if (cell->type == "$_SR_NN_") { check_gate("SRQ"); return; }
908 if (cell->type == "$_SR_NP_") { check_gate("SRQ"); return; }
909 if (cell->type == "$_SR_PN_") { check_gate("SRQ"); return; }
910 if (cell->type == "$_SR_PP_") { check_gate("SRQ"); return; }
911
912 if (cell->type == "$_DFF_N_") { check_gate("DQC"); return; }
913 if (cell->type == "$_DFF_P_") { check_gate("DQC"); return; }
914
915 if (cell->type == "$_DFFE_NN_") { check_gate("DQCE"); return; }
916 if (cell->type == "$_DFFE_NP_") { check_gate("DQCE"); return; }
917 if (cell->type == "$_DFFE_PN_") { check_gate("DQCE"); return; }
918 if (cell->type == "$_DFFE_PP_") { check_gate("DQCE"); return; }
919
920 if (cell->type == "$_DFF_NN0_") { check_gate("DQCR"); return; }
921 if (cell->type == "$_DFF_NN1_") { check_gate("DQCR"); return; }
922 if (cell->type == "$_DFF_NP0_") { check_gate("DQCR"); return; }
923 if (cell->type == "$_DFF_NP1_") { check_gate("DQCR"); return; }
924 if (cell->type == "$_DFF_PN0_") { check_gate("DQCR"); return; }
925 if (cell->type == "$_DFF_PN1_") { check_gate("DQCR"); return; }
926 if (cell->type == "$_DFF_PP0_") { check_gate("DQCR"); return; }
927 if (cell->type == "$_DFF_PP1_") { check_gate("DQCR"); return; }
928
929 if (cell->type == "$_DFFSR_NNN_") { check_gate("CSRDQ"); return; }
930 if (cell->type == "$_DFFSR_NNP_") { check_gate("CSRDQ"); return; }
931 if (cell->type == "$_DFFSR_NPN_") { check_gate("CSRDQ"); return; }
932 if (cell->type == "$_DFFSR_NPP_") { check_gate("CSRDQ"); return; }
933 if (cell->type == "$_DFFSR_PNN_") { check_gate("CSRDQ"); return; }
934 if (cell->type == "$_DFFSR_PNP_") { check_gate("CSRDQ"); return; }
935 if (cell->type == "$_DFFSR_PPN_") { check_gate("CSRDQ"); return; }
936 if (cell->type == "$_DFFSR_PPP_") { check_gate("CSRDQ"); return; }
937
938 if (cell->type == "$_DLATCH_N_") { check_gate("EDQ"); return; }
939 if (cell->type == "$_DLATCH_P_") { check_gate("EDQ"); return; }
940
941 if (cell->type == "$_DLATCHSR_NNN_") { check_gate("ESRDQ"); return; }
942 if (cell->type == "$_DLATCHSR_NNP_") { check_gate("ESRDQ"); return; }
943 if (cell->type == "$_DLATCHSR_NPN_") { check_gate("ESRDQ"); return; }
944 if (cell->type == "$_DLATCHSR_NPP_") { check_gate("ESRDQ"); return; }
945 if (cell->type == "$_DLATCHSR_PNN_") { check_gate("ESRDQ"); return; }
946 if (cell->type == "$_DLATCHSR_PNP_") { check_gate("ESRDQ"); return; }
947 if (cell->type == "$_DLATCHSR_PPN_") { check_gate("ESRDQ"); return; }
948 if (cell->type == "$_DLATCHSR_PPP_") { check_gate("ESRDQ"); return; }
949
950 error(__LINE__);
951 }
952 };
953 }
954 #endif
955
956 void RTLIL::Module::check()
957 {
958 #ifndef NDEBUG
959 std::vector<bool> ports_declared;
960 for (auto &it : wires_) {
961 log_assert(this == it.second->module);
962 log_assert(it.first == it.second->name);
963 log_assert(!it.first.empty());
964 log_assert(it.second->width >= 0);
965 log_assert(it.second->port_id >= 0);
966 for (auto &it2 : it.second->attributes)
967 log_assert(!it2.first.empty());
968 if (it.second->port_id) {
969 log_assert(GetSize(ports) >= it.second->port_id);
970 log_assert(ports.at(it.second->port_id-1) == it.first);
971 log_assert(it.second->port_input || it.second->port_output);
972 if (GetSize(ports_declared) < it.second->port_id)
973 ports_declared.resize(it.second->port_id);
974 log_assert(ports_declared[it.second->port_id-1] == false);
975 ports_declared[it.second->port_id-1] = true;
976 } else
977 log_assert(!it.second->port_input && !it.second->port_output);
978 }
979 for (auto port_declared : ports_declared)
980 log_assert(port_declared == true);
981 log_assert(GetSize(ports) == GetSize(ports_declared));
982
983 for (auto &it : memories) {
984 log_assert(it.first == it.second->name);
985 log_assert(!it.first.empty());
986 log_assert(it.second->width >= 0);
987 log_assert(it.second->size >= 0);
988 for (auto &it2 : it.second->attributes)
989 log_assert(!it2.first.empty());
990 }
991
992 for (auto &it : cells_) {
993 log_assert(this == it.second->module);
994 log_assert(it.first == it.second->name);
995 log_assert(!it.first.empty());
996 log_assert(!it.second->type.empty());
997 for (auto &it2 : it.second->connections()) {
998 log_assert(!it2.first.empty());
999 it2.second.check();
1000 }
1001 for (auto &it2 : it.second->attributes)
1002 log_assert(!it2.first.empty());
1003 for (auto &it2 : it.second->parameters)
1004 log_assert(!it2.first.empty());
1005 InternalCellChecker checker(this, it.second);
1006 checker.check();
1007 }
1008
1009 for (auto &it : processes) {
1010 log_assert(it.first == it.second->name);
1011 log_assert(!it.first.empty());
1012 // FIXME: More checks here..
1013 }
1014
1015 for (auto &it : connections_) {
1016 log_assert(it.first.size() == it.second.size());
1017 it.first.check();
1018 it.second.check();
1019 }
1020
1021 for (auto &it : attributes)
1022 log_assert(!it.first.empty());
1023 #endif
1024 }
1025
1026 void RTLIL::Module::optimize()
1027 {
1028 }
1029
1030 void RTLIL::Module::cloneInto(RTLIL::Module *new_mod) const
1031 {
1032 log_assert(new_mod->refcount_wires_ == 0);
1033 log_assert(new_mod->refcount_cells_ == 0);
1034
1035 new_mod->connections_ = connections_;
1036 new_mod->attributes = attributes;
1037
1038 for (auto &it : wires_)
1039 new_mod->addWire(it.first, it.second);
1040
1041 for (auto &it : memories)
1042 new_mod->memories[it.first] = new RTLIL::Memory(*it.second);
1043
1044 for (auto &it : cells_)
1045 new_mod->addCell(it.first, it.second);
1046
1047 for (auto &it : processes)
1048 new_mod->processes[it.first] = it.second->clone();
1049
1050 struct RewriteSigSpecWorker
1051 {
1052 RTLIL::Module *mod;
1053 void operator()(RTLIL::SigSpec &sig)
1054 {
1055 std::vector<RTLIL::SigChunk> chunks = sig.chunks();
1056 for (auto &c : chunks)
1057 if (c.wire != NULL)
1058 c.wire = mod->wires_.at(c.wire->name);
1059 sig = chunks;
1060 }
1061 };
1062
1063 RewriteSigSpecWorker rewriteSigSpecWorker;
1064 rewriteSigSpecWorker.mod = new_mod;
1065 new_mod->rewrite_sigspecs(rewriteSigSpecWorker);
1066 new_mod->fixup_ports();
1067 }
1068
1069 RTLIL::Module *RTLIL::Module::clone() const
1070 {
1071 RTLIL::Module *new_mod = new RTLIL::Module;
1072 new_mod->name = name;
1073 cloneInto(new_mod);
1074 return new_mod;
1075 }
1076
1077 bool RTLIL::Module::has_memories() const
1078 {
1079 return !memories.empty();
1080 }
1081
1082 bool RTLIL::Module::has_processes() const
1083 {
1084 return !processes.empty();
1085 }
1086
1087 bool RTLIL::Module::has_memories_warn() const
1088 {
1089 if (!memories.empty())
1090 log_warning("Ignoring module %s because it contains memories (run 'memory' command first).\n", log_id(this));
1091 return !memories.empty();
1092 }
1093
1094 bool RTLIL::Module::has_processes_warn() const
1095 {
1096 if (!processes.empty())
1097 log_warning("Ignoring module %s because it contains processes (run 'proc' command first).\n", log_id(this));
1098 return !processes.empty();
1099 }
1100
1101 std::vector<RTLIL::Wire*> RTLIL::Module::selected_wires() const
1102 {
1103 std::vector<RTLIL::Wire*> result;
1104 result.reserve(wires_.size());
1105 for (auto &it : wires_)
1106 if (design->selected(this, it.second))
1107 result.push_back(it.second);
1108 return result;
1109 }
1110
1111 std::vector<RTLIL::Cell*> RTLIL::Module::selected_cells() const
1112 {
1113 std::vector<RTLIL::Cell*> result;
1114 result.reserve(wires_.size());
1115 for (auto &it : cells_)
1116 if (design->selected(this, it.second))
1117 result.push_back(it.second);
1118 return result;
1119 }
1120
1121 void RTLIL::Module::add(RTLIL::Wire *wire)
1122 {
1123 log_assert(!wire->name.empty());
1124 log_assert(count_id(wire->name) == 0);
1125 log_assert(refcount_wires_ == 0);
1126 wires_[wire->name] = wire;
1127 wire->module = this;
1128 }
1129
1130 void RTLIL::Module::add(RTLIL::Cell *cell)
1131 {
1132 log_assert(!cell->name.empty());
1133 log_assert(count_id(cell->name) == 0);
1134 log_assert(refcount_cells_ == 0);
1135 cells_[cell->name] = cell;
1136 cell->module = this;
1137 }
1138
1139 namespace {
1140 struct DeleteWireWorker
1141 {
1142 RTLIL::Module *module;
1143 const pool<RTLIL::Wire*> *wires_p;
1144
1145 void operator()(RTLIL::SigSpec &sig) {
1146 std::vector<RTLIL::SigChunk> chunks = sig;
1147 for (auto &c : chunks)
1148 if (c.wire != NULL && wires_p->count(c.wire)) {
1149 c.wire = module->addWire(NEW_ID, c.width);
1150 c.offset = 0;
1151 }
1152 sig = chunks;
1153 }
1154 };
1155 }
1156
1157 void RTLIL::Module::remove(const pool<RTLIL::Wire*> &wires)
1158 {
1159 log_assert(refcount_wires_ == 0);
1160
1161 DeleteWireWorker delete_wire_worker;
1162 delete_wire_worker.module = this;
1163 delete_wire_worker.wires_p = &wires;
1164 rewrite_sigspecs(delete_wire_worker);
1165
1166 for (auto &it : wires) {
1167 log_assert(wires_.count(it->name) != 0);
1168 wires_.erase(it->name);
1169 delete it;
1170 }
1171 }
1172
1173 void RTLIL::Module::remove(RTLIL::Cell *cell)
1174 {
1175 while (!cell->connections_.empty())
1176 cell->unsetPort(cell->connections_.begin()->first);
1177
1178 log_assert(cells_.count(cell->name) != 0);
1179 log_assert(refcount_cells_ == 0);
1180 cells_.erase(cell->name);
1181 delete cell;
1182 }
1183
1184 void RTLIL::Module::rename(RTLIL::Wire *wire, RTLIL::IdString new_name)
1185 {
1186 log_assert(wires_[wire->name] == wire);
1187 log_assert(refcount_wires_ == 0);
1188 wires_.erase(wire->name);
1189 wire->name = new_name;
1190 add(wire);
1191 }
1192
1193 void RTLIL::Module::rename(RTLIL::Cell *cell, RTLIL::IdString new_name)
1194 {
1195 log_assert(cells_[cell->name] == cell);
1196 log_assert(refcount_wires_ == 0);
1197 cells_.erase(cell->name);
1198 cell->name = new_name;
1199 add(cell);
1200 }
1201
1202 void RTLIL::Module::rename(RTLIL::IdString old_name, RTLIL::IdString new_name)
1203 {
1204 log_assert(count_id(old_name) != 0);
1205 if (wires_.count(old_name))
1206 rename(wires_.at(old_name), new_name);
1207 else if (cells_.count(old_name))
1208 rename(cells_.at(old_name), new_name);
1209 else
1210 log_abort();
1211 }
1212
1213 void RTLIL::Module::swap_names(RTLIL::Wire *w1, RTLIL::Wire *w2)
1214 {
1215 log_assert(wires_[w1->name] == w1);
1216 log_assert(wires_[w2->name] == w2);
1217 log_assert(refcount_wires_ == 0);
1218
1219 wires_.erase(w1->name);
1220 wires_.erase(w2->name);
1221
1222 std::swap(w1->name, w2->name);
1223
1224 wires_[w1->name] = w1;
1225 wires_[w2->name] = w2;
1226 }
1227
1228 void RTLIL::Module::swap_names(RTLIL::Cell *c1, RTLIL::Cell *c2)
1229 {
1230 log_assert(cells_[c1->name] == c1);
1231 log_assert(cells_[c2->name] == c2);
1232 log_assert(refcount_cells_ == 0);
1233
1234 cells_.erase(c1->name);
1235 cells_.erase(c2->name);
1236
1237 std::swap(c1->name, c2->name);
1238
1239 cells_[c1->name] = c1;
1240 cells_[c2->name] = c2;
1241 }
1242
1243 RTLIL::IdString RTLIL::Module::uniquify(RTLIL::IdString name)
1244 {
1245 int index = 0;
1246 return uniquify(name, index);
1247 }
1248
1249 RTLIL::IdString RTLIL::Module::uniquify(RTLIL::IdString name, int &index)
1250 {
1251 if (index == 0) {
1252 if (count_id(name) == 0)
1253 return name;
1254 index++;
1255 }
1256
1257 while (1) {
1258 RTLIL::IdString new_name = stringf("%s_%d", name.c_str(), index);
1259 if (count_id(new_name) == 0)
1260 return new_name;
1261 index++;
1262 }
1263 }
1264
1265 static bool fixup_ports_compare(const RTLIL::Wire *a, const RTLIL::Wire *b)
1266 {
1267 if (a->port_id && !b->port_id)
1268 return true;
1269 if (!a->port_id && b->port_id)
1270 return false;
1271
1272 if (a->port_id == b->port_id)
1273 return a->name < b->name;
1274 return a->port_id < b->port_id;
1275 }
1276
1277 void RTLIL::Module::connect(const RTLIL::SigSig &conn)
1278 {
1279 for (auto mon : monitors)
1280 mon->notify_connect(this, conn);
1281
1282 if (design)
1283 for (auto mon : design->monitors)
1284 mon->notify_connect(this, conn);
1285
1286 connections_.push_back(conn);
1287 }
1288
1289 void RTLIL::Module::connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs)
1290 {
1291 connect(RTLIL::SigSig(lhs, rhs));
1292 }
1293
1294 void RTLIL::Module::new_connections(const std::vector<RTLIL::SigSig> &new_conn)
1295 {
1296 for (auto mon : monitors)
1297 mon->notify_connect(this, new_conn);
1298
1299 if (design)
1300 for (auto mon : design->monitors)
1301 mon->notify_connect(this, new_conn);
1302
1303 connections_ = new_conn;
1304 }
1305
1306 const std::vector<RTLIL::SigSig> &RTLIL::Module::connections() const
1307 {
1308 return connections_;
1309 }
1310
1311 void RTLIL::Module::fixup_ports()
1312 {
1313 std::vector<RTLIL::Wire*> all_ports;
1314
1315 for (auto &w : wires_)
1316 if (w.second->port_input || w.second->port_output)
1317 all_ports.push_back(w.second);
1318 else
1319 w.second->port_id = 0;
1320
1321 std::sort(all_ports.begin(), all_ports.end(), fixup_ports_compare);
1322
1323 ports.clear();
1324 for (size_t i = 0; i < all_ports.size(); i++) {
1325 ports.push_back(all_ports[i]->name);
1326 all_ports[i]->port_id = i+1;
1327 }
1328 }
1329
1330 RTLIL::Wire *RTLIL::Module::addWire(RTLIL::IdString name, int width)
1331 {
1332 RTLIL::Wire *wire = new RTLIL::Wire;
1333 wire->name = name;
1334 wire->width = width;
1335 add(wire);
1336 return wire;
1337 }
1338
1339 RTLIL::Wire *RTLIL::Module::addWire(RTLIL::IdString name, const RTLIL::Wire *other)
1340 {
1341 RTLIL::Wire *wire = addWire(name);
1342 wire->width = other->width;
1343 wire->start_offset = other->start_offset;
1344 wire->port_id = other->port_id;
1345 wire->port_input = other->port_input;
1346 wire->port_output = other->port_output;
1347 wire->upto = other->upto;
1348 wire->attributes = other->attributes;
1349 return wire;
1350 }
1351
1352 RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, RTLIL::IdString type)
1353 {
1354 RTLIL::Cell *cell = new RTLIL::Cell;
1355 cell->name = name;
1356 cell->type = type;
1357 add(cell);
1358 return cell;
1359 }
1360
1361 RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, const RTLIL::Cell *other)
1362 {
1363 RTLIL::Cell *cell = addCell(name, other->type);
1364 cell->connections_ = other->connections_;
1365 cell->parameters = other->parameters;
1366 cell->attributes = other->attributes;
1367 return cell;
1368 }
1369
1370 #define DEF_METHOD(_func, _y_size, _type) \
1371 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed) { \
1372 RTLIL::Cell *cell = addCell(name, _type); \
1373 cell->parameters["\\A_SIGNED"] = is_signed; \
1374 cell->parameters["\\A_WIDTH"] = sig_a.size(); \
1375 cell->parameters["\\Y_WIDTH"] = sig_y.size(); \
1376 cell->setPort("\\A", sig_a); \
1377 cell->setPort("\\Y", sig_y); \
1378 return cell; \
1379 } \
1380 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed) { \
1381 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
1382 add ## _func(name, sig_a, sig_y, is_signed); \
1383 return sig_y; \
1384 }
1385 DEF_METHOD(Not, sig_a.size(), "$not")
1386 DEF_METHOD(Pos, sig_a.size(), "$pos")
1387 DEF_METHOD(Neg, sig_a.size(), "$neg")
1388 DEF_METHOD(ReduceAnd, 1, "$reduce_and")
1389 DEF_METHOD(ReduceOr, 1, "$reduce_or")
1390 DEF_METHOD(ReduceXor, 1, "$reduce_xor")
1391 DEF_METHOD(ReduceXnor, 1, "$reduce_xnor")
1392 DEF_METHOD(ReduceBool, 1, "$reduce_bool")
1393 DEF_METHOD(LogicNot, 1, "$logic_not")
1394 #undef DEF_METHOD
1395
1396 #define DEF_METHOD(_func, _y_size, _type) \
1397 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed) { \
1398 RTLIL::Cell *cell = addCell(name, _type); \
1399 cell->parameters["\\A_SIGNED"] = is_signed; \
1400 cell->parameters["\\B_SIGNED"] = is_signed; \
1401 cell->parameters["\\A_WIDTH"] = sig_a.size(); \
1402 cell->parameters["\\B_WIDTH"] = sig_b.size(); \
1403 cell->parameters["\\Y_WIDTH"] = sig_y.size(); \
1404 cell->setPort("\\A", sig_a); \
1405 cell->setPort("\\B", sig_b); \
1406 cell->setPort("\\Y", sig_y); \
1407 return cell; \
1408 } \
1409 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed) { \
1410 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
1411 add ## _func(name, sig_a, sig_b, sig_y, is_signed); \
1412 return sig_y; \
1413 }
1414 DEF_METHOD(And, std::max(sig_a.size(), sig_b.size()), "$and")
1415 DEF_METHOD(Or, std::max(sig_a.size(), sig_b.size()), "$or")
1416 DEF_METHOD(Xor, std::max(sig_a.size(), sig_b.size()), "$xor")
1417 DEF_METHOD(Xnor, std::max(sig_a.size(), sig_b.size()), "$xnor")
1418 DEF_METHOD(Shl, sig_a.size(), "$shl")
1419 DEF_METHOD(Shr, sig_a.size(), "$shr")
1420 DEF_METHOD(Sshl, sig_a.size(), "$sshl")
1421 DEF_METHOD(Sshr, sig_a.size(), "$sshr")
1422 DEF_METHOD(Shift, sig_a.size(), "$shift")
1423 DEF_METHOD(Shiftx, sig_a.size(), "$shiftx")
1424 DEF_METHOD(Lt, 1, "$lt")
1425 DEF_METHOD(Le, 1, "$le")
1426 DEF_METHOD(Eq, 1, "$eq")
1427 DEF_METHOD(Ne, 1, "$ne")
1428 DEF_METHOD(Eqx, 1, "$eqx")
1429 DEF_METHOD(Nex, 1, "$nex")
1430 DEF_METHOD(Ge, 1, "$ge")
1431 DEF_METHOD(Gt, 1, "$gt")
1432 DEF_METHOD(Add, std::max(sig_a.size(), sig_b.size()), "$add")
1433 DEF_METHOD(Sub, std::max(sig_a.size(), sig_b.size()), "$sub")
1434 DEF_METHOD(Mul, std::max(sig_a.size(), sig_b.size()), "$mul")
1435 DEF_METHOD(Div, std::max(sig_a.size(), sig_b.size()), "$div")
1436 DEF_METHOD(Mod, std::max(sig_a.size(), sig_b.size()), "$mod")
1437 DEF_METHOD(LogicAnd, 1, "$logic_and")
1438 DEF_METHOD(LogicOr, 1, "$logic_or")
1439 #undef DEF_METHOD
1440
1441 #define DEF_METHOD(_func, _type, _pmux) \
1442 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, RTLIL::SigSpec sig_y) { \
1443 RTLIL::Cell *cell = addCell(name, _type); \
1444 cell->parameters["\\WIDTH"] = sig_a.size(); \
1445 if (_pmux) cell->parameters["\\S_WIDTH"] = sig_s.size(); \
1446 cell->setPort("\\A", sig_a); \
1447 cell->setPort("\\B", sig_b); \
1448 cell->setPort("\\S", sig_s); \
1449 cell->setPort("\\Y", sig_y); \
1450 return cell; \
1451 } \
1452 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s) { \
1453 RTLIL::SigSpec sig_y = addWire(NEW_ID, sig_a.size()); \
1454 add ## _func(name, sig_a, sig_b, sig_s, sig_y); \
1455 return sig_y; \
1456 }
1457 DEF_METHOD(Mux, "$mux", 0)
1458 DEF_METHOD(Pmux, "$pmux", 1)
1459 #undef DEF_METHOD
1460
1461 #define DEF_METHOD_2(_func, _type, _P1, _P2) \
1462 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2) { \
1463 RTLIL::Cell *cell = addCell(name, _type); \
1464 cell->setPort("\\" #_P1, sig1); \
1465 cell->setPort("\\" #_P2, sig2); \
1466 return cell; \
1467 } \
1468 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1) { \
1469 RTLIL::SigBit sig2 = addWire(NEW_ID); \
1470 add ## _func(name, sig1, sig2); \
1471 return sig2; \
1472 }
1473 #define DEF_METHOD_3(_func, _type, _P1, _P2, _P3) \
1474 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3) { \
1475 RTLIL::Cell *cell = addCell(name, _type); \
1476 cell->setPort("\\" #_P1, sig1); \
1477 cell->setPort("\\" #_P2, sig2); \
1478 cell->setPort("\\" #_P3, sig3); \
1479 return cell; \
1480 } \
1481 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2) { \
1482 RTLIL::SigBit sig3 = addWire(NEW_ID); \
1483 add ## _func(name, sig1, sig2, sig3); \
1484 return sig3; \
1485 }
1486 #define DEF_METHOD_4(_func, _type, _P1, _P2, _P3, _P4) \
1487 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, RTLIL::SigBit sig4) { \
1488 RTLIL::Cell *cell = addCell(name, _type); \
1489 cell->setPort("\\" #_P1, sig1); \
1490 cell->setPort("\\" #_P2, sig2); \
1491 cell->setPort("\\" #_P3, sig3); \
1492 cell->setPort("\\" #_P4, sig4); \
1493 return cell; \
1494 } \
1495 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3) { \
1496 RTLIL::SigBit sig4 = addWire(NEW_ID); \
1497 add ## _func(name, sig1, sig2, sig3, sig4); \
1498 return sig4; \
1499 }
1500 #define DEF_METHOD_5(_func, _type, _P1, _P2, _P3, _P4, _P5) \
1501 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, RTLIL::SigBit sig4, RTLIL::SigBit sig5) { \
1502 RTLIL::Cell *cell = addCell(name, _type); \
1503 cell->setPort("\\" #_P1, sig1); \
1504 cell->setPort("\\" #_P2, sig2); \
1505 cell->setPort("\\" #_P3, sig3); \
1506 cell->setPort("\\" #_P4, sig4); \
1507 cell->setPort("\\" #_P5, sig5); \
1508 return cell; \
1509 } \
1510 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, RTLIL::SigBit sig4) { \
1511 RTLIL::SigBit sig5 = addWire(NEW_ID); \
1512 add ## _func(name, sig1, sig2, sig3, sig4, sig5); \
1513 return sig5; \
1514 }
1515 DEF_METHOD_2(NotGate, "$_NOT_", A, Y)
1516 DEF_METHOD_3(AndGate, "$_AND_", A, B, Y)
1517 DEF_METHOD_3(NandGate, "$_NAND_", A, B, Y)
1518 DEF_METHOD_3(OrGate, "$_OR_", A, B, Y)
1519 DEF_METHOD_3(NorGate, "$_NOR_", A, B, Y)
1520 DEF_METHOD_3(XorGate, "$_XOR_", A, B, Y)
1521 DEF_METHOD_3(XnorGate, "$_XNOR_", A, B, Y)
1522 DEF_METHOD_4(MuxGate, "$_MUX_", A, B, S, Y)
1523 DEF_METHOD_4(Aoi3Gate, "$_AOI3_", A, B, C, Y)
1524 DEF_METHOD_4(Oai3Gate, "$_OAI3_", A, B, C, Y)
1525 DEF_METHOD_5(Aoi4Gate, "$_AOI4_", A, B, C, D, Y)
1526 DEF_METHOD_5(Oai4Gate, "$_OAI4_", A, B, C, D, Y)
1527 #undef DEF_METHOD_2
1528 #undef DEF_METHOD_3
1529 #undef DEF_METHOD_4
1530 #undef DEF_METHOD_5
1531
1532 RTLIL::Cell* RTLIL::Module::addPow(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool a_signed, bool b_signed)
1533 {
1534 RTLIL::Cell *cell = addCell(name, "$pow");
1535 cell->parameters["\\A_SIGNED"] = a_signed;
1536 cell->parameters["\\B_SIGNED"] = b_signed;
1537 cell->parameters["\\A_WIDTH"] = sig_a.size();
1538 cell->parameters["\\B_WIDTH"] = sig_b.size();
1539 cell->parameters["\\Y_WIDTH"] = sig_y.size();
1540 cell->setPort("\\A", sig_a);
1541 cell->setPort("\\B", sig_b);
1542 cell->setPort("\\Y", sig_y);
1543 return cell;
1544 }
1545
1546 RTLIL::Cell* RTLIL::Module::addSlice(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, RTLIL::Const offset)
1547 {
1548 RTLIL::Cell *cell = addCell(name, "$slice");
1549 cell->parameters["\\A_WIDTH"] = sig_a.size();
1550 cell->parameters["\\Y_WIDTH"] = sig_y.size();
1551 cell->parameters["\\OFFSET"] = offset;
1552 cell->setPort("\\A", sig_a);
1553 cell->setPort("\\Y", sig_y);
1554 return cell;
1555 }
1556
1557 RTLIL::Cell* RTLIL::Module::addConcat(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y)
1558 {
1559 RTLIL::Cell *cell = addCell(name, "$concat");
1560 cell->parameters["\\A_WIDTH"] = sig_a.size();
1561 cell->parameters["\\B_WIDTH"] = sig_b.size();
1562 cell->setPort("\\A", sig_a);
1563 cell->setPort("\\B", sig_b);
1564 cell->setPort("\\Y", sig_y);
1565 return cell;
1566 }
1567
1568 RTLIL::Cell* RTLIL::Module::addLut(RTLIL::IdString name, RTLIL::SigSpec sig_i, RTLIL::SigSpec sig_o, RTLIL::Const lut)
1569 {
1570 RTLIL::Cell *cell = addCell(name, "$lut");
1571 cell->parameters["\\LUT"] = lut;
1572 cell->parameters["\\WIDTH"] = sig_i.size();
1573 cell->setPort("\\A", sig_i);
1574 cell->setPort("\\Y", sig_o);
1575 return cell;
1576 }
1577
1578 RTLIL::Cell* RTLIL::Module::addAssert(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en)
1579 {
1580 RTLIL::Cell *cell = addCell(name, "$assert");
1581 cell->setPort("\\A", sig_a);
1582 cell->setPort("\\EN", sig_en);
1583 return cell;
1584 }
1585
1586 RTLIL::Cell* RTLIL::Module::addSr(RTLIL::IdString name, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr, RTLIL::SigSpec sig_q, bool set_polarity, bool clr_polarity)
1587 {
1588 RTLIL::Cell *cell = addCell(name, "$sr");
1589 cell->parameters["\\SET_POLARITY"] = set_polarity;
1590 cell->parameters["\\CLR_POLARITY"] = clr_polarity;
1591 cell->parameters["\\WIDTH"] = sig_q.size();
1592 cell->setPort("\\SET", sig_set);
1593 cell->setPort("\\CLR", sig_clr);
1594 cell->setPort("\\Q", sig_q);
1595 return cell;
1596 }
1597
1598 RTLIL::Cell* RTLIL::Module::addDff(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity)
1599 {
1600 RTLIL::Cell *cell = addCell(name, "$dff");
1601 cell->parameters["\\CLK_POLARITY"] = clk_polarity;
1602 cell->parameters["\\WIDTH"] = sig_q.size();
1603 cell->setPort("\\CLK", sig_clk);
1604 cell->setPort("\\D", sig_d);
1605 cell->setPort("\\Q", sig_q);
1606 return cell;
1607 }
1608
1609 RTLIL::Cell* RTLIL::Module::addDffe(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, bool en_polarity)
1610 {
1611 RTLIL::Cell *cell = addCell(name, "$dffe");
1612 cell->parameters["\\CLK_POLARITY"] = clk_polarity;
1613 cell->parameters["\\EN_POLARITY"] = en_polarity;
1614 cell->parameters["\\WIDTH"] = sig_q.size();
1615 cell->setPort("\\CLK", sig_clk);
1616 cell->setPort("\\EN", sig_en);
1617 cell->setPort("\\D", sig_d);
1618 cell->setPort("\\Q", sig_q);
1619 return cell;
1620 }
1621
1622 RTLIL::Cell* RTLIL::Module::addDffsr(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
1623 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity)
1624 {
1625 RTLIL::Cell *cell = addCell(name, "$dffsr");
1626 cell->parameters["\\CLK_POLARITY"] = clk_polarity;
1627 cell->parameters["\\SET_POLARITY"] = set_polarity;
1628 cell->parameters["\\CLR_POLARITY"] = clr_polarity;
1629 cell->parameters["\\WIDTH"] = sig_q.size();
1630 cell->setPort("\\CLK", sig_clk);
1631 cell->setPort("\\SET", sig_set);
1632 cell->setPort("\\CLR", sig_clr);
1633 cell->setPort("\\D", sig_d);
1634 cell->setPort("\\Q", sig_q);
1635 return cell;
1636 }
1637
1638 RTLIL::Cell* RTLIL::Module::addAdff(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_arst, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q,
1639 RTLIL::Const arst_value, bool clk_polarity, bool arst_polarity)
1640 {
1641 RTLIL::Cell *cell = addCell(name, "$adff");
1642 cell->parameters["\\CLK_POLARITY"] = clk_polarity;
1643 cell->parameters["\\ARST_POLARITY"] = arst_polarity;
1644 cell->parameters["\\ARST_VALUE"] = arst_value;
1645 cell->parameters["\\WIDTH"] = sig_q.size();
1646 cell->setPort("\\CLK", sig_clk);
1647 cell->setPort("\\ARST", sig_arst);
1648 cell->setPort("\\D", sig_d);
1649 cell->setPort("\\Q", sig_q);
1650 return cell;
1651 }
1652
1653 RTLIL::Cell* RTLIL::Module::addDlatch(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity)
1654 {
1655 RTLIL::Cell *cell = addCell(name, "$dlatch");
1656 cell->parameters["\\EN_POLARITY"] = en_polarity;
1657 cell->parameters["\\WIDTH"] = sig_q.size();
1658 cell->setPort("\\EN", sig_en);
1659 cell->setPort("\\D", sig_d);
1660 cell->setPort("\\Q", sig_q);
1661 return cell;
1662 }
1663
1664 RTLIL::Cell* RTLIL::Module::addDlatchsr(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
1665 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity, bool set_polarity, bool clr_polarity)
1666 {
1667 RTLIL::Cell *cell = addCell(name, "$dlatchsr");
1668 cell->parameters["\\EN_POLARITY"] = en_polarity;
1669 cell->parameters["\\SET_POLARITY"] = set_polarity;
1670 cell->parameters["\\CLR_POLARITY"] = clr_polarity;
1671 cell->parameters["\\WIDTH"] = sig_q.size();
1672 cell->setPort("\\EN", sig_en);
1673 cell->setPort("\\SET", sig_set);
1674 cell->setPort("\\CLR", sig_clr);
1675 cell->setPort("\\D", sig_d);
1676 cell->setPort("\\Q", sig_q);
1677 return cell;
1678 }
1679
1680 RTLIL::Cell* RTLIL::Module::addDffGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity)
1681 {
1682 RTLIL::Cell *cell = addCell(name, stringf("$_DFF_%c_", clk_polarity ? 'P' : 'N'));
1683 cell->setPort("\\C", sig_clk);
1684 cell->setPort("\\D", sig_d);
1685 cell->setPort("\\Q", sig_q);
1686 return cell;
1687 }
1688
1689 RTLIL::Cell* RTLIL::Module::addDffeGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, bool en_polarity)
1690 {
1691 RTLIL::Cell *cell = addCell(name, stringf("$_DFFE_%c%c_", clk_polarity ? 'P' : 'N', en_polarity ? 'P' : 'N'));
1692 cell->setPort("\\C", sig_clk);
1693 cell->setPort("\\E", sig_en);
1694 cell->setPort("\\D", sig_d);
1695 cell->setPort("\\Q", sig_q);
1696 return cell;
1697 }
1698
1699 RTLIL::Cell* RTLIL::Module::addDffsrGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
1700 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity)
1701 {
1702 RTLIL::Cell *cell = addCell(name, stringf("$_DFFSR_%c%c%c_", clk_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N'));
1703 cell->setPort("\\C", sig_clk);
1704 cell->setPort("\\S", sig_set);
1705 cell->setPort("\\R", sig_clr);
1706 cell->setPort("\\D", sig_d);
1707 cell->setPort("\\Q", sig_q);
1708 return cell;
1709 }
1710
1711 RTLIL::Cell* RTLIL::Module::addAdffGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_arst, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q,
1712 bool arst_value, bool clk_polarity, bool arst_polarity)
1713 {
1714 RTLIL::Cell *cell = addCell(name, stringf("$_DFF_%c%c%c_", clk_polarity ? 'P' : 'N', arst_polarity ? 'P' : 'N', arst_value ? '1' : '0'));
1715 cell->setPort("\\C", sig_clk);
1716 cell->setPort("\\R", sig_arst);
1717 cell->setPort("\\D", sig_d);
1718 cell->setPort("\\Q", sig_q);
1719 return cell;
1720 }
1721
1722 RTLIL::Cell* RTLIL::Module::addDlatchGate(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity)
1723 {
1724 RTLIL::Cell *cell = addCell(name, stringf("$_DLATCH_%c_", en_polarity ? 'P' : 'N'));
1725 cell->setPort("\\E", sig_en);
1726 cell->setPort("\\D", sig_d);
1727 cell->setPort("\\Q", sig_q);
1728 return cell;
1729 }
1730
1731 RTLIL::Cell* RTLIL::Module::addDlatchsrGate(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
1732 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity, bool set_polarity, bool clr_polarity)
1733 {
1734 RTLIL::Cell *cell = addCell(name, stringf("$_DLATCHSR_%c%c%c_", en_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N'));
1735 cell->setPort("\\E", sig_en);
1736 cell->setPort("\\S", sig_set);
1737 cell->setPort("\\R", sig_clr);
1738 cell->setPort("\\D", sig_d);
1739 cell->setPort("\\Q", sig_q);
1740 return cell;
1741 }
1742
1743
1744 RTLIL::Wire::Wire()
1745 {
1746 static unsigned int hashidx_count = 123456789;
1747 hashidx_count = mkhash_xorshift(hashidx_count);
1748 hashidx_ = hashidx_count;
1749
1750 module = nullptr;
1751 width = 1;
1752 start_offset = 0;
1753 port_id = 0;
1754 port_input = false;
1755 port_output = false;
1756 upto = false;
1757 }
1758
1759 RTLIL::Memory::Memory()
1760 {
1761 static unsigned int hashidx_count = 123456789;
1762 hashidx_count = mkhash_xorshift(hashidx_count);
1763 hashidx_ = hashidx_count;
1764
1765 width = 1;
1766 size = 0;
1767 }
1768
1769 RTLIL::Cell::Cell() : module(nullptr)
1770 {
1771 static unsigned int hashidx_count = 123456789;
1772 hashidx_count = mkhash_xorshift(hashidx_count);
1773 hashidx_ = hashidx_count;
1774
1775 // log("#memtrace# %p\n", this);
1776 memhasher();
1777 }
1778
1779 bool RTLIL::Cell::hasPort(RTLIL::IdString portname) const
1780 {
1781 return connections_.count(portname) != 0;
1782 }
1783
1784 void RTLIL::Cell::unsetPort(RTLIL::IdString portname)
1785 {
1786 RTLIL::SigSpec signal;
1787 auto conn_it = connections_.find(portname);
1788
1789 if (conn_it != connections_.end())
1790 {
1791 for (auto mon : module->monitors)
1792 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
1793
1794 if (module->design)
1795 for (auto mon : module->design->monitors)
1796 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
1797
1798 connections_.erase(conn_it);
1799 }
1800 }
1801
1802 void RTLIL::Cell::setPort(RTLIL::IdString portname, RTLIL::SigSpec signal)
1803 {
1804 auto conn_it = connections_.find(portname);
1805
1806 if (conn_it == connections_.end()) {
1807 connections_[portname] = RTLIL::SigSpec();
1808 conn_it = connections_.find(portname);
1809 log_assert(conn_it != connections_.end());
1810 }
1811
1812 for (auto mon : module->monitors)
1813 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
1814
1815 if (module->design)
1816 for (auto mon : module->design->monitors)
1817 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
1818
1819 conn_it->second = signal;
1820 }
1821
1822 const RTLIL::SigSpec &RTLIL::Cell::getPort(RTLIL::IdString portname) const
1823 {
1824 return connections_.at(portname);
1825 }
1826
1827 const dict<RTLIL::IdString, RTLIL::SigSpec> &RTLIL::Cell::connections() const
1828 {
1829 return connections_;
1830 }
1831
1832 bool RTLIL::Cell::hasParam(RTLIL::IdString paramname) const
1833 {
1834 return parameters.count(paramname) != 0;
1835 }
1836
1837 void RTLIL::Cell::unsetParam(RTLIL::IdString paramname)
1838 {
1839 parameters.erase(paramname);
1840 }
1841
1842 void RTLIL::Cell::setParam(RTLIL::IdString paramname, RTLIL::Const value)
1843 {
1844 parameters[paramname] = value;
1845 }
1846
1847 const RTLIL::Const &RTLIL::Cell::getParam(RTLIL::IdString paramname) const
1848 {
1849 return parameters.at(paramname);
1850 }
1851
1852 void RTLIL::Cell::check()
1853 {
1854 #ifndef NDEBUG
1855 InternalCellChecker checker(NULL, this);
1856 checker.check();
1857 #endif
1858 }
1859
1860 void RTLIL::Cell::fixup_parameters(bool set_a_signed, bool set_b_signed)
1861 {
1862 if (type.substr(0, 1) != "$" || type.substr(0, 2) == "$_" || type.substr(0, 8) == "$paramod" ||
1863 type.substr(0, 9) == "$verific$" || type.substr(0, 7) == "$array:" || type.substr(0, 8) == "$extern:")
1864 return;
1865
1866 if (type == "$mux" || type == "$pmux") {
1867 parameters["\\WIDTH"] = GetSize(connections_["\\Y"]);
1868 if (type == "$pmux")
1869 parameters["\\S_WIDTH"] = GetSize(connections_["\\S"]);
1870 check();
1871 return;
1872 }
1873
1874 if (type == "$lut") {
1875 parameters["\\WIDTH"] = GetSize(connections_["\\A"]);
1876 return;
1877 }
1878
1879 if (type == "$fa") {
1880 parameters["\\WIDTH"] = GetSize(connections_["\\Y"]);
1881 return;
1882 }
1883
1884 if (type == "$lcu") {
1885 parameters["\\WIDTH"] = GetSize(connections_["\\CO"]);
1886 return;
1887 }
1888
1889 bool signedness_ab = !type.in("$slice", "$concat", "$macc");
1890
1891 if (connections_.count("\\A")) {
1892 if (signedness_ab) {
1893 if (set_a_signed)
1894 parameters["\\A_SIGNED"] = true;
1895 else if (parameters.count("\\A_SIGNED") == 0)
1896 parameters["\\A_SIGNED"] = false;
1897 }
1898 parameters["\\A_WIDTH"] = GetSize(connections_["\\A"]);
1899 }
1900
1901 if (connections_.count("\\B")) {
1902 if (signedness_ab) {
1903 if (set_b_signed)
1904 parameters["\\B_SIGNED"] = true;
1905 else if (parameters.count("\\B_SIGNED") == 0)
1906 parameters["\\B_SIGNED"] = false;
1907 }
1908 parameters["\\B_WIDTH"] = GetSize(connections_["\\B"]);
1909 }
1910
1911 if (connections_.count("\\Y"))
1912 parameters["\\Y_WIDTH"] = GetSize(connections_["\\Y"]);
1913
1914 check();
1915 }
1916
1917 RTLIL::SigChunk::SigChunk()
1918 {
1919 wire = NULL;
1920 width = 0;
1921 offset = 0;
1922 }
1923
1924 RTLIL::SigChunk::SigChunk(const RTLIL::Const &value)
1925 {
1926 wire = NULL;
1927 data = value.bits;
1928 width = GetSize(data);
1929 offset = 0;
1930 }
1931
1932 RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire)
1933 {
1934 log_assert(wire != nullptr);
1935 this->wire = wire;
1936 this->width = wire->width;
1937 this->offset = 0;
1938 }
1939
1940 RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire, int offset, int width)
1941 {
1942 log_assert(wire != nullptr);
1943 this->wire = wire;
1944 this->width = width;
1945 this->offset = offset;
1946 }
1947
1948 RTLIL::SigChunk::SigChunk(const std::string &str)
1949 {
1950 wire = NULL;
1951 data = RTLIL::Const(str).bits;
1952 width = GetSize(data);
1953 offset = 0;
1954 }
1955
1956 RTLIL::SigChunk::SigChunk(int val, int width)
1957 {
1958 wire = NULL;
1959 data = RTLIL::Const(val, width).bits;
1960 this->width = GetSize(data);
1961 offset = 0;
1962 }
1963
1964 RTLIL::SigChunk::SigChunk(RTLIL::State bit, int width)
1965 {
1966 wire = NULL;
1967 data = RTLIL::Const(bit, width).bits;
1968 this->width = GetSize(data);
1969 offset = 0;
1970 }
1971
1972 RTLIL::SigChunk::SigChunk(RTLIL::SigBit bit)
1973 {
1974 wire = bit.wire;
1975 offset = 0;
1976 if (wire == NULL)
1977 data = RTLIL::Const(bit.data).bits;
1978 else
1979 offset = bit.offset;
1980 width = 1;
1981 }
1982
1983 RTLIL::SigChunk RTLIL::SigChunk::extract(int offset, int length) const
1984 {
1985 RTLIL::SigChunk ret;
1986 if (wire) {
1987 ret.wire = wire;
1988 ret.offset = this->offset + offset;
1989 ret.width = length;
1990 } else {
1991 for (int i = 0; i < length; i++)
1992 ret.data.push_back(data[offset+i]);
1993 ret.width = length;
1994 }
1995 return ret;
1996 }
1997
1998 bool RTLIL::SigChunk::operator <(const RTLIL::SigChunk &other) const
1999 {
2000 if (wire && other.wire)
2001 if (wire->name != other.wire->name)
2002 return wire->name < other.wire->name;
2003
2004 if (wire != other.wire)
2005 return wire < other.wire;
2006
2007 if (offset != other.offset)
2008 return offset < other.offset;
2009
2010 if (width != other.width)
2011 return width < other.width;
2012
2013 return data < other.data;
2014 }
2015
2016 bool RTLIL::SigChunk::operator ==(const RTLIL::SigChunk &other) const
2017 {
2018 return wire == other.wire && width == other.width && offset == other.offset && data == other.data;
2019 }
2020
2021 bool RTLIL::SigChunk::operator !=(const RTLIL::SigChunk &other) const
2022 {
2023 if (*this == other)
2024 return false;
2025 return true;
2026 }
2027
2028 RTLIL::SigSpec::SigSpec()
2029 {
2030 width_ = 0;
2031 hash_ = 0;
2032 }
2033
2034 RTLIL::SigSpec::SigSpec(const RTLIL::SigSpec &other)
2035 {
2036 *this = other;
2037 }
2038
2039 RTLIL::SigSpec::SigSpec(std::initializer_list<RTLIL::SigSpec> parts)
2040 {
2041 cover("kernel.rtlil.sigspec.init.list");
2042
2043 width_ = 0;
2044 hash_ = 0;
2045
2046 std::vector<RTLIL::SigSpec> parts_vec(parts.begin(), parts.end());
2047 for (auto it = parts_vec.rbegin(); it != parts_vec.rend(); it++)
2048 append(*it);
2049 }
2050
2051 const RTLIL::SigSpec &RTLIL::SigSpec::operator=(const RTLIL::SigSpec &other)
2052 {
2053 cover("kernel.rtlil.sigspec.assign");
2054
2055 width_ = other.width_;
2056 hash_ = other.hash_;
2057 chunks_ = other.chunks_;
2058 bits_.clear();
2059
2060 if (!other.bits_.empty())
2061 {
2062 RTLIL::SigChunk *last = NULL;
2063 int last_end_offset = 0;
2064
2065 for (auto &bit : other.bits_) {
2066 if (last && bit.wire == last->wire) {
2067 if (bit.wire == NULL) {
2068 last->data.push_back(bit.data);
2069 last->width++;
2070 continue;
2071 } else if (last_end_offset == bit.offset) {
2072 last_end_offset++;
2073 last->width++;
2074 continue;
2075 }
2076 }
2077 chunks_.push_back(bit);
2078 last = &chunks_.back();
2079 last_end_offset = bit.offset + 1;
2080 }
2081
2082 check();
2083 }
2084
2085 return *this;
2086 }
2087
2088 RTLIL::SigSpec::SigSpec(const RTLIL::Const &value)
2089 {
2090 cover("kernel.rtlil.sigspec.init.const");
2091
2092 chunks_.push_back(RTLIL::SigChunk(value));
2093 width_ = chunks_.back().width;
2094 hash_ = 0;
2095 check();
2096 }
2097
2098 RTLIL::SigSpec::SigSpec(const RTLIL::SigChunk &chunk)
2099 {
2100 cover("kernel.rtlil.sigspec.init.chunk");
2101
2102 chunks_.push_back(chunk);
2103 width_ = chunks_.back().width;
2104 hash_ = 0;
2105 check();
2106 }
2107
2108 RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire)
2109 {
2110 cover("kernel.rtlil.sigspec.init.wire");
2111
2112 chunks_.push_back(RTLIL::SigChunk(wire));
2113 width_ = chunks_.back().width;
2114 hash_ = 0;
2115 check();
2116 }
2117
2118 RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire, int offset, int width)
2119 {
2120 cover("kernel.rtlil.sigspec.init.wire_part");
2121
2122 chunks_.push_back(RTLIL::SigChunk(wire, offset, width));
2123 width_ = chunks_.back().width;
2124 hash_ = 0;
2125 check();
2126 }
2127
2128 RTLIL::SigSpec::SigSpec(const std::string &str)
2129 {
2130 cover("kernel.rtlil.sigspec.init.str");
2131
2132 chunks_.push_back(RTLIL::SigChunk(str));
2133 width_ = chunks_.back().width;
2134 hash_ = 0;
2135 check();
2136 }
2137
2138 RTLIL::SigSpec::SigSpec(int val, int width)
2139 {
2140 cover("kernel.rtlil.sigspec.init.int");
2141
2142 chunks_.push_back(RTLIL::SigChunk(val, width));
2143 width_ = width;
2144 hash_ = 0;
2145 check();
2146 }
2147
2148 RTLIL::SigSpec::SigSpec(RTLIL::State bit, int width)
2149 {
2150 cover("kernel.rtlil.sigspec.init.state");
2151
2152 chunks_.push_back(RTLIL::SigChunk(bit, width));
2153 width_ = width;
2154 hash_ = 0;
2155 check();
2156 }
2157
2158 RTLIL::SigSpec::SigSpec(RTLIL::SigBit bit, int width)
2159 {
2160 cover("kernel.rtlil.sigspec.init.bit");
2161
2162 if (bit.wire == NULL)
2163 chunks_.push_back(RTLIL::SigChunk(bit.data, width));
2164 else
2165 for (int i = 0; i < width; i++)
2166 chunks_.push_back(bit);
2167 width_ = width;
2168 hash_ = 0;
2169 check();
2170 }
2171
2172 RTLIL::SigSpec::SigSpec(std::vector<RTLIL::SigChunk> chunks)
2173 {
2174 cover("kernel.rtlil.sigspec.init.stdvec_chunks");
2175
2176 width_ = 0;
2177 hash_ = 0;
2178 for (auto &c : chunks)
2179 append(c);
2180 check();
2181 }
2182
2183 RTLIL::SigSpec::SigSpec(std::vector<RTLIL::SigBit> bits)
2184 {
2185 cover("kernel.rtlil.sigspec.init.stdvec_bits");
2186
2187 width_ = 0;
2188 hash_ = 0;
2189 for (auto &bit : bits)
2190 append_bit(bit);
2191 check();
2192 }
2193
2194 RTLIL::SigSpec::SigSpec(pool<RTLIL::SigBit> bits)
2195 {
2196 cover("kernel.rtlil.sigspec.init.pool_bits");
2197
2198 width_ = 0;
2199 hash_ = 0;
2200 for (auto &bit : bits)
2201 append_bit(bit);
2202 check();
2203 }
2204
2205 RTLIL::SigSpec::SigSpec(std::set<RTLIL::SigBit> bits)
2206 {
2207 cover("kernel.rtlil.sigspec.init.stdset_bits");
2208
2209 width_ = 0;
2210 hash_ = 0;
2211 for (auto &bit : bits)
2212 append_bit(bit);
2213 check();
2214 }
2215
2216 RTLIL::SigSpec::SigSpec(bool bit)
2217 {
2218 cover("kernel.rtlil.sigspec.init.bool");
2219
2220 width_ = 0;
2221 hash_ = 0;
2222 append_bit(bit);
2223 check();
2224 }
2225
2226 void RTLIL::SigSpec::pack() const
2227 {
2228 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
2229
2230 if (that->bits_.empty())
2231 return;
2232
2233 cover("kernel.rtlil.sigspec.convert.pack");
2234 log_assert(that->chunks_.empty());
2235
2236 std::vector<RTLIL::SigBit> old_bits;
2237 old_bits.swap(that->bits_);
2238
2239 RTLIL::SigChunk *last = NULL;
2240 int last_end_offset = 0;
2241
2242 for (auto &bit : old_bits) {
2243 if (last && bit.wire == last->wire) {
2244 if (bit.wire == NULL) {
2245 last->data.push_back(bit.data);
2246 last->width++;
2247 continue;
2248 } else if (last_end_offset == bit.offset) {
2249 last_end_offset++;
2250 last->width++;
2251 continue;
2252 }
2253 }
2254 that->chunks_.push_back(bit);
2255 last = &that->chunks_.back();
2256 last_end_offset = bit.offset + 1;
2257 }
2258
2259 check();
2260 }
2261
2262 void RTLIL::SigSpec::unpack() const
2263 {
2264 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
2265
2266 if (that->chunks_.empty())
2267 return;
2268
2269 cover("kernel.rtlil.sigspec.convert.unpack");
2270 log_assert(that->bits_.empty());
2271
2272 that->bits_.reserve(that->width_);
2273 for (auto &c : that->chunks_)
2274 for (int i = 0; i < c.width; i++)
2275 that->bits_.push_back(RTLIL::SigBit(c, i));
2276
2277 that->chunks_.clear();
2278 that->hash_ = 0;
2279 }
2280
2281 void RTLIL::SigSpec::updhash() const
2282 {
2283 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
2284
2285 if (that->hash_ != 0)
2286 return;
2287
2288 cover("kernel.rtlil.sigspec.hash");
2289 that->pack();
2290
2291 that->hash_ = 5381;
2292 for (auto &c : that->chunks_)
2293 if (c.wire == NULL) {
2294 for (auto &v : c.data)
2295 that->hash_ = mkhash(that->hash_, v);
2296 } else {
2297 that->hash_ = mkhash(that->hash_, c.wire->name.index_);
2298 that->hash_ = mkhash(that->hash_, c.offset);
2299 that->hash_ = mkhash(that->hash_, c.width);
2300 }
2301
2302 if (that->hash_ == 0)
2303 that->hash_ = 1;
2304 }
2305
2306 void RTLIL::SigSpec::sort()
2307 {
2308 unpack();
2309 cover("kernel.rtlil.sigspec.sort");
2310 std::sort(bits_.begin(), bits_.end());
2311 }
2312
2313 void RTLIL::SigSpec::sort_and_unify()
2314 {
2315 cover("kernel.rtlil.sigspec.sort_and_unify");
2316 *this = this->to_sigbit_set();
2317 }
2318
2319 void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with)
2320 {
2321 replace(pattern, with, this);
2322 }
2323
2324 void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with, RTLIL::SigSpec *other) const
2325 {
2326 log_assert(pattern.width_ == with.width_);
2327
2328 pattern.unpack();
2329 with.unpack();
2330
2331 dict<RTLIL::SigBit, RTLIL::SigBit> rules;
2332
2333 for (int i = 0; i < GetSize(pattern.bits_); i++)
2334 if (pattern.bits_[i].wire != NULL)
2335 rules[pattern.bits_[i]] = with.bits_[i];
2336
2337 replace(rules, other);
2338 }
2339
2340 void RTLIL::SigSpec::replace(const dict<RTLIL::SigBit, RTLIL::SigBit> &rules)
2341 {
2342 replace(rules, this);
2343 }
2344
2345 void RTLIL::SigSpec::replace(const dict<RTLIL::SigBit, RTLIL::SigBit> &rules, RTLIL::SigSpec *other) const
2346 {
2347 cover("kernel.rtlil.sigspec.replace_dict");
2348
2349 log_assert(other != NULL);
2350 log_assert(width_ == other->width_);
2351
2352 unpack();
2353 other->unpack();
2354
2355 for (int i = 0; i < GetSize(bits_); i++) {
2356 auto it = rules.find(bits_[i]);
2357 if (it != rules.end())
2358 other->bits_[i] = it->second;
2359 }
2360
2361 other->check();
2362 }
2363
2364 void RTLIL::SigSpec::replace(const std::map<RTLIL::SigBit, RTLIL::SigBit> &rules)
2365 {
2366 replace(rules, this);
2367 }
2368
2369 void RTLIL::SigSpec::replace(const std::map<RTLIL::SigBit, RTLIL::SigBit> &rules, RTLIL::SigSpec *other) const
2370 {
2371 cover("kernel.rtlil.sigspec.replace_map");
2372
2373 log_assert(other != NULL);
2374 log_assert(width_ == other->width_);
2375
2376 unpack();
2377 other->unpack();
2378
2379 for (int i = 0; i < GetSize(bits_); i++) {
2380 auto it = rules.find(bits_[i]);
2381 if (it != rules.end())
2382 other->bits_[i] = it->second;
2383 }
2384
2385 other->check();
2386 }
2387
2388 void RTLIL::SigSpec::remove(const RTLIL::SigSpec &pattern)
2389 {
2390 remove2(pattern, NULL);
2391 }
2392
2393 void RTLIL::SigSpec::remove(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other) const
2394 {
2395 RTLIL::SigSpec tmp = *this;
2396 tmp.remove2(pattern, other);
2397 }
2398
2399 void RTLIL::SigSpec::remove2(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other)
2400 {
2401 pool<RTLIL::SigBit> pattern_bits = pattern.to_sigbit_pool();
2402 remove2(pattern_bits, other);
2403 }
2404
2405 void RTLIL::SigSpec::remove(const pool<RTLIL::SigBit> &pattern)
2406 {
2407 remove2(pattern, NULL);
2408 }
2409
2410 void RTLIL::SigSpec::remove(const pool<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other) const
2411 {
2412 RTLIL::SigSpec tmp = *this;
2413 tmp.remove2(pattern, other);
2414 }
2415
2416 void RTLIL::SigSpec::remove2(const pool<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other)
2417 {
2418 if (other)
2419 cover("kernel.rtlil.sigspec.remove_other");
2420 else
2421 cover("kernel.rtlil.sigspec.remove");
2422
2423 unpack();
2424
2425 if (other != NULL) {
2426 log_assert(width_ == other->width_);
2427 other->unpack();
2428 }
2429
2430 std::vector<RTLIL::SigBit> new_bits, new_other_bits;
2431
2432 new_bits.resize(GetSize(bits_));
2433 if (other != NULL)
2434 new_other_bits.resize(GetSize(bits_));
2435
2436 int k = 0;
2437 for (int i = 0; i < GetSize(bits_); i++) {
2438 if (bits_[i].wire != NULL && pattern.count(bits_[i]))
2439 continue;
2440 if (other != NULL)
2441 new_other_bits[k] = other->bits_[i];
2442 new_bits[k++] = bits_[i];
2443 }
2444
2445 new_bits.resize(k);
2446 if (other != NULL)
2447 new_other_bits.resize(k);
2448
2449 bits_.swap(new_bits);
2450 width_ = GetSize(bits_);
2451
2452 if (other != NULL) {
2453 other->bits_.swap(new_other_bits);
2454 other->width_ = GetSize(other->bits_);
2455 }
2456
2457 check();
2458 }
2459
2460 RTLIL::SigSpec RTLIL::SigSpec::extract(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec *other) const
2461 {
2462 pool<RTLIL::SigBit> pattern_bits = pattern.to_sigbit_pool();
2463 return extract(pattern_bits, other);
2464 }
2465
2466 RTLIL::SigSpec RTLIL::SigSpec::extract(const pool<RTLIL::SigBit> &pattern, const RTLIL::SigSpec *other) const
2467 {
2468 if (other)
2469 cover("kernel.rtlil.sigspec.extract_other");
2470 else
2471 cover("kernel.rtlil.sigspec.extract");
2472
2473 log_assert(other == NULL || width_ == other->width_);
2474
2475 std::vector<RTLIL::SigBit> bits_match = to_sigbit_vector();
2476 RTLIL::SigSpec ret;
2477
2478 if (other) {
2479 std::vector<RTLIL::SigBit> bits_other = other->to_sigbit_vector();
2480 for (int i = 0; i < width_; i++)
2481 if (bits_match[i].wire && pattern.count(bits_match[i]))
2482 ret.append_bit(bits_other[i]);
2483 } else {
2484 for (int i = 0; i < width_; i++)
2485 if (bits_match[i].wire && pattern.count(bits_match[i]))
2486 ret.append_bit(bits_match[i]);
2487 }
2488
2489 ret.check();
2490 return ret;
2491 }
2492
2493 void RTLIL::SigSpec::replace(int offset, const RTLIL::SigSpec &with)
2494 {
2495 cover("kernel.rtlil.sigspec.replace_pos");
2496
2497 unpack();
2498 with.unpack();
2499
2500 log_assert(offset >= 0);
2501 log_assert(with.width_ >= 0);
2502 log_assert(offset+with.width_ <= width_);
2503
2504 for (int i = 0; i < with.width_; i++)
2505 bits_.at(offset + i) = with.bits_.at(i);
2506
2507 check();
2508 }
2509
2510 void RTLIL::SigSpec::remove_const()
2511 {
2512 if (packed())
2513 {
2514 cover("kernel.rtlil.sigspec.remove_const.packed");
2515
2516 std::vector<RTLIL::SigChunk> new_chunks;
2517 new_chunks.reserve(GetSize(chunks_));
2518
2519 width_ = 0;
2520 for (auto &chunk : chunks_)
2521 if (chunk.wire != NULL) {
2522 new_chunks.push_back(chunk);
2523 width_ += chunk.width;
2524 }
2525
2526 chunks_.swap(new_chunks);
2527 }
2528 else
2529 {
2530 cover("kernel.rtlil.sigspec.remove_const.unpacked");
2531
2532 std::vector<RTLIL::SigBit> new_bits;
2533 new_bits.reserve(width_);
2534
2535 for (auto &bit : bits_)
2536 if (bit.wire != NULL)
2537 new_bits.push_back(bit);
2538
2539 bits_.swap(new_bits);
2540 width_ = bits_.size();
2541 }
2542
2543 check();
2544 }
2545
2546 void RTLIL::SigSpec::remove(int offset, int length)
2547 {
2548 cover("kernel.rtlil.sigspec.remove_pos");
2549
2550 unpack();
2551
2552 log_assert(offset >= 0);
2553 log_assert(length >= 0);
2554 log_assert(offset + length <= width_);
2555
2556 bits_.erase(bits_.begin() + offset, bits_.begin() + offset + length);
2557 width_ = bits_.size();
2558
2559 check();
2560 }
2561
2562 RTLIL::SigSpec RTLIL::SigSpec::extract(int offset, int length) const
2563 {
2564 unpack();
2565 cover("kernel.rtlil.sigspec.extract_pos");
2566 return std::vector<RTLIL::SigBit>(bits_.begin() + offset, bits_.begin() + offset + length);
2567 }
2568
2569 void RTLIL::SigSpec::append(const RTLIL::SigSpec &signal)
2570 {
2571 if (signal.width_ == 0)
2572 return;
2573
2574 if (width_ == 0) {
2575 *this = signal;
2576 return;
2577 }
2578
2579 cover("kernel.rtlil.sigspec.append");
2580
2581 if (packed() != signal.packed()) {
2582 pack();
2583 signal.pack();
2584 }
2585
2586 if (packed())
2587 for (auto &other_c : signal.chunks_)
2588 {
2589 auto &my_last_c = chunks_.back();
2590 if (my_last_c.wire == NULL && other_c.wire == NULL) {
2591 auto &this_data = my_last_c.data;
2592 auto &other_data = other_c.data;
2593 this_data.insert(this_data.end(), other_data.begin(), other_data.end());
2594 my_last_c.width += other_c.width;
2595 } else
2596 if (my_last_c.wire == other_c.wire && my_last_c.offset + my_last_c.width == other_c.offset) {
2597 my_last_c.width += other_c.width;
2598 } else
2599 chunks_.push_back(other_c);
2600 }
2601 else
2602 bits_.insert(bits_.end(), signal.bits_.begin(), signal.bits_.end());
2603
2604 width_ += signal.width_;
2605 check();
2606 }
2607
2608 void RTLIL::SigSpec::append_bit(const RTLIL::SigBit &bit)
2609 {
2610 if (packed())
2611 {
2612 cover("kernel.rtlil.sigspec.append_bit.packed");
2613
2614 if (chunks_.size() == 0)
2615 chunks_.push_back(bit);
2616 else
2617 if (bit.wire == NULL)
2618 if (chunks_.back().wire == NULL) {
2619 chunks_.back().data.push_back(bit.data);
2620 chunks_.back().width++;
2621 } else
2622 chunks_.push_back(bit);
2623 else
2624 if (chunks_.back().wire == bit.wire && chunks_.back().offset + chunks_.back().width == bit.offset)
2625 chunks_.back().width++;
2626 else
2627 chunks_.push_back(bit);
2628 }
2629 else
2630 {
2631 cover("kernel.rtlil.sigspec.append_bit.unpacked");
2632 bits_.push_back(bit);
2633 }
2634
2635 width_++;
2636 check();
2637 }
2638
2639 void RTLIL::SigSpec::extend_xx(int width, bool is_signed)
2640 {
2641 cover("kernel.rtlil.sigspec.extend_xx");
2642
2643 pack();
2644
2645 if (width_ > width)
2646 remove(width, width_ - width);
2647
2648 if (width_ < width) {
2649 RTLIL::SigBit padding = width_ > 0 ? (*this)[width_ - 1] : RTLIL::State::S0;
2650 if (!is_signed && (padding == RTLIL::State::S1 || padding.wire))
2651 padding = RTLIL::State::S0;
2652 while (width_ < width)
2653 append(padding);
2654 }
2655 }
2656
2657 void RTLIL::SigSpec::extend_u0(int width, bool is_signed)
2658 {
2659 cover("kernel.rtlil.sigspec.extend_u0");
2660
2661 pack();
2662
2663 if (width_ > width)
2664 remove(width, width_ - width);
2665
2666 if (width_ < width) {
2667 RTLIL::SigBit padding = width_ > 0 ? (*this)[width_ - 1] : RTLIL::State::S0;
2668 if (!is_signed)
2669 padding = RTLIL::State::S0;
2670 while (width_ < width)
2671 append(padding);
2672 }
2673
2674 }
2675
2676 RTLIL::SigSpec RTLIL::SigSpec::repeat(int num) const
2677 {
2678 cover("kernel.rtlil.sigspec.repeat");
2679
2680 RTLIL::SigSpec sig;
2681 for (int i = 0; i < num; i++)
2682 sig.append(*this);
2683 return sig;
2684 }
2685
2686 #ifndef NDEBUG
2687 void RTLIL::SigSpec::check() const
2688 {
2689 if (width_ > 64)
2690 {
2691 cover("kernel.rtlil.sigspec.check.skip");
2692 }
2693 else if (packed())
2694 {
2695 cover("kernel.rtlil.sigspec.check.packed");
2696
2697 int w = 0;
2698 for (size_t i = 0; i < chunks_.size(); i++) {
2699 const RTLIL::SigChunk chunk = chunks_[i];
2700 if (chunk.wire == NULL) {
2701 if (i > 0)
2702 log_assert(chunks_[i-1].wire != NULL);
2703 log_assert(chunk.offset == 0);
2704 log_assert(chunk.data.size() == (size_t)chunk.width);
2705 } else {
2706 if (i > 0 && chunks_[i-1].wire == chunk.wire)
2707 log_assert(chunk.offset != chunks_[i-1].offset + chunks_[i-1].width);
2708 log_assert(chunk.offset >= 0);
2709 log_assert(chunk.width >= 0);
2710 log_assert(chunk.offset + chunk.width <= chunk.wire->width);
2711 log_assert(chunk.data.size() == 0);
2712 }
2713 w += chunk.width;
2714 }
2715 log_assert(w == width_);
2716 log_assert(bits_.empty());
2717 }
2718 else
2719 {
2720 cover("kernel.rtlil.sigspec.check.unpacked");
2721
2722 log_assert(width_ == GetSize(bits_));
2723 log_assert(chunks_.empty());
2724 }
2725 }
2726 #endif
2727
2728 bool RTLIL::SigSpec::operator <(const RTLIL::SigSpec &other) const
2729 {
2730 cover("kernel.rtlil.sigspec.comp_lt");
2731
2732 if (this == &other)
2733 return false;
2734
2735 if (width_ != other.width_)
2736 return width_ < other.width_;
2737
2738 pack();
2739 other.pack();
2740
2741 if (chunks_.size() != other.chunks_.size())
2742 return chunks_.size() < other.chunks_.size();
2743
2744 updhash();
2745 other.updhash();
2746
2747 if (hash_ != other.hash_)
2748 return hash_ < other.hash_;
2749
2750 for (size_t i = 0; i < chunks_.size(); i++)
2751 if (chunks_[i] != other.chunks_[i]) {
2752 cover("kernel.rtlil.sigspec.comp_lt.hash_collision");
2753 return chunks_[i] < other.chunks_[i];
2754 }
2755
2756 cover("kernel.rtlil.sigspec.comp_lt.equal");
2757 return false;
2758 }
2759
2760 bool RTLIL::SigSpec::operator ==(const RTLIL::SigSpec &other) const
2761 {
2762 cover("kernel.rtlil.sigspec.comp_eq");
2763
2764 if (this == &other)
2765 return true;
2766
2767 if (width_ != other.width_)
2768 return false;
2769
2770 pack();
2771 other.pack();
2772
2773 if (chunks_.size() != chunks_.size())
2774 return false;
2775
2776 updhash();
2777 other.updhash();
2778
2779 if (hash_ != other.hash_)
2780 return false;
2781
2782 for (size_t i = 0; i < chunks_.size(); i++)
2783 if (chunks_[i] != other.chunks_[i]) {
2784 cover("kernel.rtlil.sigspec.comp_eq.hash_collision");
2785 return false;
2786 }
2787
2788 cover("kernel.rtlil.sigspec.comp_eq.equal");
2789 return true;
2790 }
2791
2792 bool RTLIL::SigSpec::is_wire() const
2793 {
2794 cover("kernel.rtlil.sigspec.is_wire");
2795
2796 pack();
2797 return GetSize(chunks_) == 1 && chunks_[0].wire && chunks_[0].wire->width == width_;
2798 }
2799
2800 bool RTLIL::SigSpec::is_chunk() const
2801 {
2802 cover("kernel.rtlil.sigspec.is_chunk");
2803
2804 pack();
2805 return GetSize(chunks_) == 1;
2806 }
2807
2808 bool RTLIL::SigSpec::is_fully_const() const
2809 {
2810 cover("kernel.rtlil.sigspec.is_fully_const");
2811
2812 pack();
2813 for (auto it = chunks_.begin(); it != chunks_.end(); it++)
2814 if (it->width > 0 && it->wire != NULL)
2815 return false;
2816 return true;
2817 }
2818
2819 bool RTLIL::SigSpec::is_fully_def() const
2820 {
2821 cover("kernel.rtlil.sigspec.is_fully_def");
2822
2823 pack();
2824 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
2825 if (it->width > 0 && it->wire != NULL)
2826 return false;
2827 for (size_t i = 0; i < it->data.size(); i++)
2828 if (it->data[i] != RTLIL::State::S0 && it->data[i] != RTLIL::State::S1)
2829 return false;
2830 }
2831 return true;
2832 }
2833
2834 bool RTLIL::SigSpec::is_fully_undef() const
2835 {
2836 cover("kernel.rtlil.sigspec.is_fully_undef");
2837
2838 pack();
2839 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
2840 if (it->width > 0 && it->wire != NULL)
2841 return false;
2842 for (size_t i = 0; i < it->data.size(); i++)
2843 if (it->data[i] != RTLIL::State::Sx && it->data[i] != RTLIL::State::Sz)
2844 return false;
2845 }
2846 return true;
2847 }
2848
2849 bool RTLIL::SigSpec::has_marked_bits() const
2850 {
2851 cover("kernel.rtlil.sigspec.has_marked_bits");
2852
2853 pack();
2854 for (auto it = chunks_.begin(); it != chunks_.end(); it++)
2855 if (it->width > 0 && it->wire == NULL) {
2856 for (size_t i = 0; i < it->data.size(); i++)
2857 if (it->data[i] == RTLIL::State::Sm)
2858 return true;
2859 }
2860 return false;
2861 }
2862
2863 bool RTLIL::SigSpec::as_bool() const
2864 {
2865 cover("kernel.rtlil.sigspec.as_bool");
2866
2867 pack();
2868 log_assert(is_fully_const() && GetSize(chunks_) <= 1);
2869 if (width_)
2870 return RTLIL::Const(chunks_[0].data).as_bool();
2871 return false;
2872 }
2873
2874 int RTLIL::SigSpec::as_int(bool is_signed) const
2875 {
2876 cover("kernel.rtlil.sigspec.as_int");
2877
2878 pack();
2879 log_assert(is_fully_const() && GetSize(chunks_) <= 1);
2880 if (width_)
2881 return RTLIL::Const(chunks_[0].data).as_int(is_signed);
2882 return 0;
2883 }
2884
2885 std::string RTLIL::SigSpec::as_string() const
2886 {
2887 cover("kernel.rtlil.sigspec.as_string");
2888
2889 pack();
2890 std::string str;
2891 for (size_t i = chunks_.size(); i > 0; i--) {
2892 const RTLIL::SigChunk &chunk = chunks_[i-1];
2893 if (chunk.wire != NULL)
2894 for (int j = 0; j < chunk.width; j++)
2895 str += "?";
2896 else
2897 str += RTLIL::Const(chunk.data).as_string();
2898 }
2899 return str;
2900 }
2901
2902 RTLIL::Const RTLIL::SigSpec::as_const() const
2903 {
2904 cover("kernel.rtlil.sigspec.as_const");
2905
2906 pack();
2907 log_assert(is_fully_const() && GetSize(chunks_) <= 1);
2908 if (width_)
2909 return chunks_[0].data;
2910 return RTLIL::Const();
2911 }
2912
2913 RTLIL::Wire *RTLIL::SigSpec::as_wire() const
2914 {
2915 cover("kernel.rtlil.sigspec.as_wire");
2916
2917 pack();
2918 log_assert(is_wire());
2919 return chunks_[0].wire;
2920 }
2921
2922 RTLIL::SigChunk RTLIL::SigSpec::as_chunk() const
2923 {
2924 cover("kernel.rtlil.sigspec.as_chunk");
2925
2926 pack();
2927 log_assert(is_chunk());
2928 return chunks_[0];
2929 }
2930
2931 bool RTLIL::SigSpec::match(std::string pattern) const
2932 {
2933 cover("kernel.rtlil.sigspec.match");
2934
2935 pack();
2936 std::string str = as_string();
2937 log_assert(pattern.size() == str.size());
2938
2939 for (size_t i = 0; i < pattern.size(); i++) {
2940 if (pattern[i] == ' ')
2941 continue;
2942 if (pattern[i] == '*') {
2943 if (str[i] != 'z' && str[i] != 'x')
2944 return false;
2945 continue;
2946 }
2947 if (pattern[i] != str[i])
2948 return false;
2949 }
2950
2951 return true;
2952 }
2953
2954 std::set<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_set() const
2955 {
2956 cover("kernel.rtlil.sigspec.to_sigbit_set");
2957
2958 pack();
2959 std::set<RTLIL::SigBit> sigbits;
2960 for (auto &c : chunks_)
2961 for (int i = 0; i < c.width; i++)
2962 sigbits.insert(RTLIL::SigBit(c, i));
2963 return sigbits;
2964 }
2965
2966 pool<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_pool() const
2967 {
2968 cover("kernel.rtlil.sigspec.to_sigbit_pool");
2969
2970 pack();
2971 pool<RTLIL::SigBit> sigbits;
2972 for (auto &c : chunks_)
2973 for (int i = 0; i < c.width; i++)
2974 sigbits.insert(RTLIL::SigBit(c, i));
2975 return sigbits;
2976 }
2977
2978 std::vector<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_vector() const
2979 {
2980 cover("kernel.rtlil.sigspec.to_sigbit_vector");
2981
2982 unpack();
2983 return bits_;
2984 }
2985
2986 std::map<RTLIL::SigBit, RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_map(const RTLIL::SigSpec &other) const
2987 {
2988 cover("kernel.rtlil.sigspec.to_sigbit_map");
2989
2990 unpack();
2991 other.unpack();
2992
2993 log_assert(width_ == other.width_);
2994
2995 std::map<RTLIL::SigBit, RTLIL::SigBit> new_map;
2996 for (int i = 0; i < width_; i++)
2997 new_map[bits_[i]] = other.bits_[i];
2998
2999 return new_map;
3000 }
3001
3002 dict<RTLIL::SigBit, RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_dict(const RTLIL::SigSpec &other) const
3003 {
3004 cover("kernel.rtlil.sigspec.to_sigbit_dict");
3005
3006 unpack();
3007 other.unpack();
3008
3009 log_assert(width_ == other.width_);
3010
3011 dict<RTLIL::SigBit, RTLIL::SigBit> new_map;
3012 for (int i = 0; i < width_; i++)
3013 new_map[bits_[i]] = other.bits_[i];
3014
3015 return new_map;
3016 }
3017
3018 RTLIL::SigBit RTLIL::SigSpec::to_single_sigbit() const
3019 {
3020 cover("kernel.rtlil.sigspec.to_single_sigbit");
3021
3022 pack();
3023 log_assert(width_ == 1);
3024 for (auto &c : chunks_)
3025 if (c.width)
3026 return RTLIL::SigBit(c);
3027 log_abort();
3028 }
3029
3030 static void sigspec_parse_split(std::vector<std::string> &tokens, const std::string &text, char sep)
3031 {
3032 size_t start = 0, end = 0;
3033 while ((end = text.find(sep, start)) != std::string::npos) {
3034 tokens.push_back(text.substr(start, end - start));
3035 start = end + 1;
3036 }
3037 tokens.push_back(text.substr(start));
3038 }
3039
3040 static int sigspec_parse_get_dummy_line_num()
3041 {
3042 return 0;
3043 }
3044
3045 bool RTLIL::SigSpec::parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str)
3046 {
3047 cover("kernel.rtlil.sigspec.parse");
3048
3049 std::vector<std::string> tokens;
3050 sigspec_parse_split(tokens, str, ',');
3051
3052 sig = RTLIL::SigSpec();
3053 for (int tokidx = int(tokens.size())-1; tokidx >= 0; tokidx--)
3054 {
3055 std::string netname = tokens[tokidx];
3056 std::string indices;
3057
3058 if (netname.size() == 0)
3059 continue;
3060
3061 if (('0' <= netname[0] && netname[0] <= '9') || netname[0] == '\'') {
3062 cover("kernel.rtlil.sigspec.parse.const");
3063 AST::get_line_num = sigspec_parse_get_dummy_line_num;
3064 AST::AstNode *ast = VERILOG_FRONTEND::const2ast(netname);
3065 if (ast == NULL)
3066 return false;
3067 sig.append(RTLIL::Const(ast->bits));
3068 delete ast;
3069 continue;
3070 }
3071
3072 if (module == NULL)
3073 return false;
3074
3075 cover("kernel.rtlil.sigspec.parse.net");
3076
3077 if (netname[0] != '$' && netname[0] != '\\')
3078 netname = "\\" + netname;
3079
3080 if (module->wires_.count(netname) == 0) {
3081 size_t indices_pos = netname.size()-1;
3082 if (indices_pos > 2 && netname[indices_pos] == ']')
3083 {
3084 indices_pos--;
3085 while (indices_pos > 0 && ('0' <= netname[indices_pos] && netname[indices_pos] <= '9')) indices_pos--;
3086 if (indices_pos > 0 && netname[indices_pos] == ':') {
3087 indices_pos--;
3088 while (indices_pos > 0 && ('0' <= netname[indices_pos] && netname[indices_pos] <= '9')) indices_pos--;
3089 }
3090 if (indices_pos > 0 && netname[indices_pos] == '[') {
3091 indices = netname.substr(indices_pos);
3092 netname = netname.substr(0, indices_pos);
3093 }
3094 }
3095 }
3096
3097 if (module->wires_.count(netname) == 0)
3098 return false;
3099
3100 RTLIL::Wire *wire = module->wires_.at(netname);
3101 if (!indices.empty()) {
3102 std::vector<std::string> index_tokens;
3103 sigspec_parse_split(index_tokens, indices.substr(1, indices.size()-2), ':');
3104 if (index_tokens.size() == 1) {
3105 cover("kernel.rtlil.sigspec.parse.bit_sel");
3106 int a = atoi(index_tokens.at(0).c_str());
3107 if (a < 0 || a >= wire->width)
3108 return false;
3109 sig.append(RTLIL::SigSpec(wire, a));
3110 } else {
3111 cover("kernel.rtlil.sigspec.parse.part_sel");
3112 int a = atoi(index_tokens.at(0).c_str());
3113 int b = atoi(index_tokens.at(1).c_str());
3114 if (a > b) {
3115 int tmp = a;
3116 a = b, b = tmp;
3117 }
3118 if (a < 0 || a >= wire->width)
3119 return false;
3120 if (b < 0 || b >= wire->width)
3121 return false;
3122 sig.append(RTLIL::SigSpec(wire, a, b-a+1));
3123 }
3124 } else
3125 sig.append(wire);
3126 }
3127
3128 return true;
3129 }
3130
3131 bool RTLIL::SigSpec::parse_sel(RTLIL::SigSpec &sig, RTLIL::Design *design, RTLIL::Module *module, std::string str)
3132 {
3133 if (str.empty() || str[0] != '@')
3134 return parse(sig, module, str);
3135
3136 cover("kernel.rtlil.sigspec.parse.sel");
3137
3138 str = RTLIL::escape_id(str.substr(1));
3139 if (design->selection_vars.count(str) == 0)
3140 return false;
3141
3142 sig = RTLIL::SigSpec();
3143 RTLIL::Selection &sel = design->selection_vars.at(str);
3144 for (auto &it : module->wires_)
3145 if (sel.selected_member(module->name, it.first))
3146 sig.append(it.second);
3147
3148 return true;
3149 }
3150
3151 bool RTLIL::SigSpec::parse_rhs(const RTLIL::SigSpec &lhs, RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str)
3152 {
3153 if (str == "0") {
3154 cover("kernel.rtlil.sigspec.parse.rhs_zeros");
3155 sig = RTLIL::SigSpec(RTLIL::State::S0, lhs.width_);
3156 return true;
3157 }
3158
3159 if (str == "~0") {
3160 cover("kernel.rtlil.sigspec.parse.rhs_ones");
3161 sig = RTLIL::SigSpec(RTLIL::State::S1, lhs.width_);
3162 return true;
3163 }
3164
3165 if (lhs.chunks_.size() == 1) {
3166 char *p = (char*)str.c_str(), *endptr;
3167 long int val = strtol(p, &endptr, 10);
3168 if (endptr && endptr != p && *endptr == 0) {
3169 sig = RTLIL::SigSpec(val, lhs.width_);
3170 cover("kernel.rtlil.sigspec.parse.rhs_dec");
3171 return true;
3172 }
3173 }
3174
3175 return parse(sig, module, str);
3176 }
3177
3178 RTLIL::CaseRule::~CaseRule()
3179 {
3180 for (auto it = switches.begin(); it != switches.end(); it++)
3181 delete *it;
3182 }
3183
3184 RTLIL::CaseRule *RTLIL::CaseRule::clone() const
3185 {
3186 RTLIL::CaseRule *new_caserule = new RTLIL::CaseRule;
3187 new_caserule->compare = compare;
3188 new_caserule->actions = actions;
3189 for (auto &it : switches)
3190 new_caserule->switches.push_back(it->clone());
3191 return new_caserule;
3192 }
3193
3194 RTLIL::SwitchRule::~SwitchRule()
3195 {
3196 for (auto it = cases.begin(); it != cases.end(); it++)
3197 delete *it;
3198 }
3199
3200 RTLIL::SwitchRule *RTLIL::SwitchRule::clone() const
3201 {
3202 RTLIL::SwitchRule *new_switchrule = new RTLIL::SwitchRule;
3203 new_switchrule->signal = signal;
3204 new_switchrule->attributes = attributes;
3205 for (auto &it : cases)
3206 new_switchrule->cases.push_back(it->clone());
3207 return new_switchrule;
3208
3209 }
3210
3211 RTLIL::SyncRule *RTLIL::SyncRule::clone() const
3212 {
3213 RTLIL::SyncRule *new_syncrule = new RTLIL::SyncRule;
3214 new_syncrule->type = type;
3215 new_syncrule->signal = signal;
3216 new_syncrule->actions = actions;
3217 return new_syncrule;
3218 }
3219
3220 RTLIL::Process::~Process()
3221 {
3222 for (auto it = syncs.begin(); it != syncs.end(); it++)
3223 delete *it;
3224 }
3225
3226 RTLIL::Process *RTLIL::Process::clone() const
3227 {
3228 RTLIL::Process *new_proc = new RTLIL::Process;
3229
3230 new_proc->name = name;
3231 new_proc->attributes = attributes;
3232
3233 RTLIL::CaseRule *rc_ptr = root_case.clone();
3234 new_proc->root_case = *rc_ptr;
3235 rc_ptr->switches.clear();
3236 delete rc_ptr;
3237
3238 for (auto &it : syncs)
3239 new_proc->syncs.push_back(it->clone());
3240
3241 return new_proc;
3242 }
3243
3244 YOSYS_NAMESPACE_END
3245