projects / yosys.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
rtlil: Make Process handling more uniform with Cell and Wire.
[yosys.git] / kernel / rtlil.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 #include "kernel/yosys.h"
21 #include "kernel/macc.h"
22 #include "kernel/celltypes.h"
23 #include "frontends/verilog/verilog_frontend.h"
24 #include "frontends/verilog/preproc.h"
25 #include "backends/rtlil/rtlil_backend.h"
26
27 #include <string.h>
28 #include <algorithm>
29
30 YOSYS_NAMESPACE_BEGIN
31
32 RTLIL::IdString::destruct_guard_t RTLIL::IdString::destruct_guard;
33 std::vector<char*> RTLIL::IdString::global_id_storage_;
34 dict<char*, int, hash_cstr_ops> RTLIL::IdString::global_id_index_;
35 #ifndef YOSYS_NO_IDS_REFCNT
36 std::vector<int> RTLIL::IdString::global_refcount_storage_;
37 std::vector<int> RTLIL::IdString::global_free_idx_list_;
38 #endif
39 #ifdef YOSYS_USE_STICKY_IDS
40 int RTLIL::IdString::last_created_idx_[8];
41 int RTLIL::IdString::last_created_idx_ptr_;
42 #endif
43
44 #define X(_id) IdString RTLIL::ID::_id;
45 #include "kernel/constids.inc"
46 #undef X
47
48 dict<std::string, std::string> RTLIL::constpad;
49
50 const pool<IdString> &RTLIL::builtin_ff_cell_types() {
51 static const pool<IdString> res = {
52 ID($sr),
53 ID($ff),
54 ID($dff),
55 ID($dffe),
56 ID($dffsr),
57 ID($dffsre),
58 ID($adff),
59 ID($adffe),
60 ID($sdff),
61 ID($sdffe),
62 ID($sdffce),
63 ID($dlatch),
64 ID($adlatch),
65 ID($dlatchsr),
66 ID($_DFFE_NN_),
67 ID($_DFFE_NP_),
68 ID($_DFFE_PN_),
69 ID($_DFFE_PP_),
70 ID($_DFFSR_NNN_),
71 ID($_DFFSR_NNP_),
72 ID($_DFFSR_NPN_),
73 ID($_DFFSR_NPP_),
74 ID($_DFFSR_PNN_),
75 ID($_DFFSR_PNP_),
76 ID($_DFFSR_PPN_),
77 ID($_DFFSR_PPP_),
78 ID($_DFFSRE_NNNN_),
79 ID($_DFFSRE_NNNP_),
80 ID($_DFFSRE_NNPN_),
81 ID($_DFFSRE_NNPP_),
82 ID($_DFFSRE_NPNN_),
83 ID($_DFFSRE_NPNP_),
84 ID($_DFFSRE_NPPN_),
85 ID($_DFFSRE_NPPP_),
86 ID($_DFFSRE_PNNN_),
87 ID($_DFFSRE_PNNP_),
88 ID($_DFFSRE_PNPN_),
89 ID($_DFFSRE_PNPP_),
90 ID($_DFFSRE_PPNN_),
91 ID($_DFFSRE_PPNP_),
92 ID($_DFFSRE_PPPN_),
93 ID($_DFFSRE_PPPP_),
94 ID($_DFF_N_),
95 ID($_DFF_P_),
96 ID($_DFF_NN0_),
97 ID($_DFF_NN1_),
98 ID($_DFF_NP0_),
99 ID($_DFF_NP1_),
100 ID($_DFF_PN0_),
101 ID($_DFF_PN1_),
102 ID($_DFF_PP0_),
103 ID($_DFF_PP1_),
104 ID($_DFFE_NN0N_),
105 ID($_DFFE_NN0P_),
106 ID($_DFFE_NN1N_),
107 ID($_DFFE_NN1P_),
108 ID($_DFFE_NP0N_),
109 ID($_DFFE_NP0P_),
110 ID($_DFFE_NP1N_),
111 ID($_DFFE_NP1P_),
112 ID($_DFFE_PN0N_),
113 ID($_DFFE_PN0P_),
114 ID($_DFFE_PN1N_),
115 ID($_DFFE_PN1P_),
116 ID($_DFFE_PP0N_),
117 ID($_DFFE_PP0P_),
118 ID($_DFFE_PP1N_),
119 ID($_DFFE_PP1P_),
120 ID($_SDFF_NN0_),
121 ID($_SDFF_NN1_),
122 ID($_SDFF_NP0_),
123 ID($_SDFF_NP1_),
124 ID($_SDFF_PN0_),
125 ID($_SDFF_PN1_),
126 ID($_SDFF_PP0_),
127 ID($_SDFF_PP1_),
128 ID($_SDFFE_NN0N_),
129 ID($_SDFFE_NN0P_),
130 ID($_SDFFE_NN1N_),
131 ID($_SDFFE_NN1P_),
132 ID($_SDFFE_NP0N_),
133 ID($_SDFFE_NP0P_),
134 ID($_SDFFE_NP1N_),
135 ID($_SDFFE_NP1P_),
136 ID($_SDFFE_PN0N_),
137 ID($_SDFFE_PN0P_),
138 ID($_SDFFE_PN1N_),
139 ID($_SDFFE_PN1P_),
140 ID($_SDFFE_PP0N_),
141 ID($_SDFFE_PP0P_),
142 ID($_SDFFE_PP1N_),
143 ID($_SDFFE_PP1P_),
144 ID($_SDFFCE_NN0N_),
145 ID($_SDFFCE_NN0P_),
146 ID($_SDFFCE_NN1N_),
147 ID($_SDFFCE_NN1P_),
148 ID($_SDFFCE_NP0N_),
149 ID($_SDFFCE_NP0P_),
150 ID($_SDFFCE_NP1N_),
151 ID($_SDFFCE_NP1P_),
152 ID($_SDFFCE_PN0N_),
153 ID($_SDFFCE_PN0P_),
154 ID($_SDFFCE_PN1N_),
155 ID($_SDFFCE_PN1P_),
156 ID($_SDFFCE_PP0N_),
157 ID($_SDFFCE_PP0P_),
158 ID($_SDFFCE_PP1N_),
159 ID($_SDFFCE_PP1P_),
160 ID($_SR_NN_),
161 ID($_SR_NP_),
162 ID($_SR_PN_),
163 ID($_SR_PP_),
164 ID($_DLATCH_N_),
165 ID($_DLATCH_P_),
166 ID($_DLATCH_NN0_),
167 ID($_DLATCH_NN1_),
168 ID($_DLATCH_NP0_),
169 ID($_DLATCH_NP1_),
170 ID($_DLATCH_PN0_),
171 ID($_DLATCH_PN1_),
172 ID($_DLATCH_PP0_),
173 ID($_DLATCH_PP1_),
174 ID($_DLATCHSR_NNN_),
175 ID($_DLATCHSR_NNP_),
176 ID($_DLATCHSR_NPN_),
177 ID($_DLATCHSR_NPP_),
178 ID($_DLATCHSR_PNN_),
179 ID($_DLATCHSR_PNP_),
180 ID($_DLATCHSR_PPN_),
181 ID($_DLATCHSR_PPP_),
182 ID($_FF_),
183 };
184 return res;
185 }
186
187 RTLIL::Const::Const()
188 {
189 flags = RTLIL::CONST_FLAG_NONE;
190 }
191
192 RTLIL::Const::Const(std::string str)
193 {
194 flags = RTLIL::CONST_FLAG_STRING;
195 for (int i = str.size()-1; i >= 0; i--) {
196 unsigned char ch = str[i];
197 for (int j = 0; j < 8; j++) {
198 bits.push_back((ch & 1) != 0 ? State::S1 : State::S0);
199 ch = ch >> 1;
200 }
201 }
202 }
203
204 RTLIL::Const::Const(int val, int width)
205 {
206 flags = RTLIL::CONST_FLAG_NONE;
207 for (int i = 0; i < width; i++) {
208 bits.push_back((val & 1) != 0 ? State::S1 : State::S0);
209 val = val >> 1;
210 }
211 }
212
213 RTLIL::Const::Const(RTLIL::State bit, int width)
214 {
215 flags = RTLIL::CONST_FLAG_NONE;
216 for (int i = 0; i < width; i++)
217 bits.push_back(bit);
218 }
219
220 RTLIL::Const::Const(const std::vector<bool> &bits)
221 {
222 flags = RTLIL::CONST_FLAG_NONE;
223 for (const auto &b : bits)
224 this->bits.emplace_back(b ? State::S1 : State::S0);
225 }
226
227 RTLIL::Const::Const(const RTLIL::Const &c)
228 {
229 flags = c.flags;
230 for (const auto &b : c.bits)
231 this->bits.push_back(b);
232 }
233
234 bool RTLIL::Const::operator <(const RTLIL::Const &other) const
235 {
236 if (bits.size() != other.bits.size())
237 return bits.size() < other.bits.size();
238 for (size_t i = 0; i < bits.size(); i++)
239 if (bits[i] != other.bits[i])
240 return bits[i] < other.bits[i];
241 return false;
242 }
243
244 bool RTLIL::Const::operator ==(const RTLIL::Const &other) const
245 {
246 return bits == other.bits;
247 }
248
249 bool RTLIL::Const::operator !=(const RTLIL::Const &other) const
250 {
251 return bits != other.bits;
252 }
253
254 bool RTLIL::Const::as_bool() const
255 {
256 for (size_t i = 0; i < bits.size(); i++)
257 if (bits[i] == State::S1)
258 return true;
259 return false;
260 }
261
262 int RTLIL::Const::as_int(bool is_signed) const
263 {
264 int32_t ret = 0;
265 for (size_t i = 0; i < bits.size() && i < 32; i++)
266 if (bits[i] == State::S1)
267 ret |= 1 << i;
268 if (is_signed && bits.back() == State::S1)
269 for (size_t i = bits.size(); i < 32; i++)
270 ret |= 1 << i;
271 return ret;
272 }
273
274 std::string RTLIL::Const::as_string() const
275 {
276 std::string ret;
277 ret.reserve(bits.size());
278 for (size_t i = bits.size(); i > 0; i--)
279 switch (bits[i-1]) {
280 case S0: ret += "0"; break;
281 case S1: ret += "1"; break;
282 case Sx: ret += "x"; break;
283 case Sz: ret += "z"; break;
284 case Sa: ret += "-"; break;
285 case Sm: ret += "m"; break;
286 }
287 return ret;
288 }
289
290 RTLIL::Const RTLIL::Const::from_string(const std::string &str)
291 {
292 Const c;
293 c.bits.reserve(str.size());
294 for (auto it = str.rbegin(); it != str.rend(); it++)
295 switch (*it) {
296 case '0': c.bits.push_back(State::S0); break;
297 case '1': c.bits.push_back(State::S1); break;
298 case 'x': c.bits.push_back(State::Sx); break;
299 case 'z': c.bits.push_back(State::Sz); break;
300 case 'm': c.bits.push_back(State::Sm); break;
301 default: c.bits.push_back(State::Sa);
302 }
303 return c;
304 }
305
306 std::string RTLIL::Const::decode_string() const
307 {
308 std::string string;
309 string.reserve(GetSize(bits)/8);
310 for (int i = 0; i < GetSize(bits); i += 8) {
311 char ch = 0;
312 for (int j = 0; j < 8 && i + j < int (bits.size()); j++)
313 if (bits[i + j] == RTLIL::State::S1)
314 ch |= 1 << j;
315 if (ch != 0)
316 string.append({ch});
317 }
318 std::reverse(string.begin(), string.end());
319 return string;
320 }
321
322 bool RTLIL::Const::is_fully_zero() const
323 {
324 cover("kernel.rtlil.const.is_fully_zero");
325
326 for (const auto &bit : bits)
327 if (bit != RTLIL::State::S0)
328 return false;
329
330 return true;
331 }
332
333 bool RTLIL::Const::is_fully_ones() const
334 {
335 cover("kernel.rtlil.const.is_fully_ones");
336
337 for (const auto &bit : bits)
338 if (bit != RTLIL::State::S1)
339 return false;
340
341 return true;
342 }
343
344 bool RTLIL::Const::is_fully_def() const
345 {
346 cover("kernel.rtlil.const.is_fully_def");
347
348 for (const auto &bit : bits)
349 if (bit != RTLIL::State::S0 && bit != RTLIL::State::S1)
350 return false;
351
352 return true;
353 }
354
355 bool RTLIL::Const::is_fully_undef() const
356 {
357 cover("kernel.rtlil.const.is_fully_undef");
358
359 for (const auto &bit : bits)
360 if (bit != RTLIL::State::Sx && bit != RTLIL::State::Sz)
361 return false;
362
363 return true;
364 }
365
366 bool RTLIL::Const::is_onehot(int *pos) const
367 {
368 cover("kernel.rtlil.const.is_onehot");
369
370 bool found = false;
371 for (int i = 0; i < GetSize(*this); i++) {
372 auto &bit = bits[i];
373 if (bit != RTLIL::State::S0 && bit != RTLIL::State::S1)
374 return false;
375 if (bit == RTLIL::State::S1) {
376 if (found)
377 return false;
378 if (pos)
379 *pos = i;
380 found = true;
381 }
382 }
383 return found;
384 }
385
386 bool RTLIL::AttrObject::has_attribute(RTLIL::IdString id) const
387 {
388 return attributes.count(id);
389 }
390
391 void RTLIL::AttrObject::set_bool_attribute(RTLIL::IdString id, bool value)
392 {
393 if (value)
394 attributes[id] = RTLIL::Const(1);
395 else
396 attributes.erase(id);
397 }
398
399 bool RTLIL::AttrObject::get_bool_attribute(RTLIL::IdString id) const
400 {
401 const auto it = attributes.find(id);
402 if (it == attributes.end())
403 return false;
404 return it->second.as_bool();
405 }
406
407 void RTLIL::AttrObject::set_string_attribute(RTLIL::IdString id, string value)
408 {
409 if (value.empty())
410 attributes.erase(id);
411 else
412 attributes[id] = value;
413 }
414
415 string RTLIL::AttrObject::get_string_attribute(RTLIL::IdString id) const
416 {
417 std::string value;
418 const auto it = attributes.find(id);
419 if (it != attributes.end())
420 value = it->second.decode_string();
421 return value;
422 }
423
424 void RTLIL::AttrObject::set_strpool_attribute(RTLIL::IdString id, const pool<string> &data)
425 {
426 string attrval;
427 for (const auto &s : data) {
428 if (!attrval.empty())
429 attrval += "|";
430 attrval += s;
431 }
432 set_string_attribute(id, attrval);
433 }
434
435 void RTLIL::AttrObject::add_strpool_attribute(RTLIL::IdString id, const pool<string> &data)
436 {
437 pool<string> union_data = get_strpool_attribute(id);
438 union_data.insert(data.begin(), data.end());
439 if (!union_data.empty())
440 set_strpool_attribute(id, union_data);
441 }
442
443 pool<string> RTLIL::AttrObject::get_strpool_attribute(RTLIL::IdString id) const
444 {
445 pool<string> data;
446 if (attributes.count(id) != 0)
447 for (auto s : split_tokens(get_string_attribute(id), "|"))
448 data.insert(s);
449 return data;
450 }
451
452 void RTLIL::AttrObject::set_hdlname_attribute(const vector<string> &hierarchy)
453 {
454 string attrval;
455 for (const auto &ident : hierarchy) {
456 if (!attrval.empty())
457 attrval += " ";
458 attrval += ident;
459 }
460 set_string_attribute(ID::hdlname, attrval);
461 }
462
463 vector<string> RTLIL::AttrObject::get_hdlname_attribute() const
464 {
465 return split_tokens(get_string_attribute(ID::hdlname), " ");
466 }
467
468 bool RTLIL::Selection::selected_module(RTLIL::IdString mod_name) const
469 {
470 if (full_selection)
471 return true;
472 if (selected_modules.count(mod_name) > 0)
473 return true;
474 if (selected_members.count(mod_name) > 0)
475 return true;
476 return false;
477 }
478
479 bool RTLIL::Selection::selected_whole_module(RTLIL::IdString mod_name) const
480 {
481 if (full_selection)
482 return true;
483 if (selected_modules.count(mod_name) > 0)
484 return true;
485 return false;
486 }
487
488 bool RTLIL::Selection::selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const
489 {
490 if (full_selection)
491 return true;
492 if (selected_modules.count(mod_name) > 0)
493 return true;
494 if (selected_members.count(mod_name) > 0)
495 if (selected_members.at(mod_name).count(memb_name) > 0)
496 return true;
497 return false;
498 }
499
500 void RTLIL::Selection::optimize(RTLIL::Design *design)
501 {
502 if (full_selection) {
503 selected_modules.clear();
504 selected_members.clear();
505 return;
506 }
507
508 std::vector<RTLIL::IdString> del_list, add_list;
509
510 del_list.clear();
511 for (auto mod_name : selected_modules) {
512 if (design->modules_.count(mod_name) == 0)
513 del_list.push_back(mod_name);
514 selected_members.erase(mod_name);
515 }
516 for (auto mod_name : del_list)
517 selected_modules.erase(mod_name);
518
519 del_list.clear();
520 for (auto &it : selected_members)
521 if (design->modules_.count(it.first) == 0)
522 del_list.push_back(it.first);
523 for (auto mod_name : del_list)
524 selected_members.erase(mod_name);
525
526 for (auto &it : selected_members) {
527 del_list.clear();
528 for (auto memb_name : it.second)
529 if (design->modules_[it.first]->count_id(memb_name) == 0)
530 del_list.push_back(memb_name);
531 for (auto memb_name : del_list)
532 it.second.erase(memb_name);
533 }
534
535 del_list.clear();
536 add_list.clear();
537 for (auto &it : selected_members)
538 if (it.second.size() == 0)
539 del_list.push_back(it.first);
540 else if (it.second.size() == design->modules_[it.first]->wires_.size() + design->modules_[it.first]->memories.size() +
541 design->modules_[it.first]->cells_.size() + design->modules_[it.first]->processes.size())
542 add_list.push_back(it.first);
543 for (auto mod_name : del_list)
544 selected_members.erase(mod_name);
545 for (auto mod_name : add_list) {
546 selected_members.erase(mod_name);
547 selected_modules.insert(mod_name);
548 }
549
550 if (selected_modules.size() == design->modules_.size()) {
551 full_selection = true;
552 selected_modules.clear();
553 selected_members.clear();
554 }
555 }
556
557 RTLIL::Design::Design()
558 : verilog_defines (new define_map_t)
559 {
560 static unsigned int hashidx_count = 123456789;
561 hashidx_count = mkhash_xorshift(hashidx_count);
562 hashidx_ = hashidx_count;
563
564 refcount_modules_ = 0;
565 selection_stack.push_back(RTLIL::Selection());
566
567 #ifdef WITH_PYTHON
568 RTLIL::Design::get_all_designs()->insert(std::pair<unsigned int, RTLIL::Design*>(hashidx_, this));
569 #endif
570 }
571
572 RTLIL::Design::~Design()
573 {
574 for (auto &pr : modules_)
575 delete pr.second;
576 for (auto n : verilog_packages)
577 delete n;
578 for (auto n : verilog_globals)
579 delete n;
580 #ifdef WITH_PYTHON
581 RTLIL::Design::get_all_designs()->erase(hashidx_);
582 #endif
583 }
584
585 #ifdef WITH_PYTHON
586 static std::map<unsigned int, RTLIL::Design*> all_designs;
587 std::map<unsigned int, RTLIL::Design*> *RTLIL::Design::get_all_designs(void)
588 {
589 return &all_designs;
590 }
591 #endif
592
593 RTLIL::ObjRange<RTLIL::Module*> RTLIL::Design::modules()
594 {
595 return RTLIL::ObjRange<RTLIL::Module*>(&modules_, &refcount_modules_);
596 }
597
598 RTLIL::Module *RTLIL::Design::module(RTLIL::IdString name)
599 {
600 return modules_.count(name) ? modules_.at(name) : NULL;
601 }
602
603 const RTLIL::Module *RTLIL::Design::module(RTLIL::IdString name) const
604 {
605 return modules_.count(name) ? modules_.at(name) : NULL;
606 }
607
608 RTLIL::Module *RTLIL::Design::top_module()
609 {
610 RTLIL::Module *module = nullptr;
611 int module_count = 0;
612
613 for (auto mod : selected_modules()) {
614 if (mod->get_bool_attribute(ID::top))
615 return mod;
616 module_count++;
617 module = mod;
618 }
619
620 return module_count == 1 ? module : nullptr;
621 }
622
623 void RTLIL::Design::add(RTLIL::Module *module)
624 {
625 log_assert(modules_.count(module->name) == 0);
626 log_assert(refcount_modules_ == 0);
627 modules_[module->name] = module;
628 module->design = this;
629
630 for (auto mon : monitors)
631 mon->notify_module_add(module);
632
633 if (yosys_xtrace) {
634 log("#X# New Module: %s\n", log_id(module));
635 log_backtrace("-X- ", yosys_xtrace-1);
636 }
637 }
638
639 RTLIL::Module *RTLIL::Design::addModule(RTLIL::IdString name)
640 {
641 if (modules_.count(name) != 0)
642 log_error("Attempted to add new module named '%s', but a module by that name already exists\n", name.c_str());
643 log_assert(refcount_modules_ == 0);
644
645 RTLIL::Module *module = new RTLIL::Module;
646 modules_[name] = module;
647 module->design = this;
648 module->name = name;
649
650 for (auto mon : monitors)
651 mon->notify_module_add(module);
652
653 if (yosys_xtrace) {
654 log("#X# New Module: %s\n", log_id(module));
655 log_backtrace("-X- ", yosys_xtrace-1);
656 }
657
658 return module;
659 }
660
661 void RTLIL::Design::scratchpad_unset(const std::string &varname)
662 {
663 scratchpad.erase(varname);
664 }
665
666 void RTLIL::Design::scratchpad_set_int(const std::string &varname, int value)
667 {
668 scratchpad[varname] = stringf("%d", value);
669 }
670
671 void RTLIL::Design::scratchpad_set_bool(const std::string &varname, bool value)
672 {
673 scratchpad[varname] = value ? "true" : "false";
674 }
675
676 void RTLIL::Design::scratchpad_set_string(const std::string &varname, std::string value)
677 {
678 scratchpad[varname] = std::move(value);
679 }
680
681 int RTLIL::Design::scratchpad_get_int(const std::string &varname, int default_value) const
682 {
683 auto it = scratchpad.find(varname);
684 if (it == scratchpad.end())
685 return default_value;
686
687 const std::string &str = it->second;
688
689 if (str == "0" || str == "false")
690 return 0;
691
692 if (str == "1" || str == "true")
693 return 1;
694
695 char *endptr = nullptr;
696 long int parsed_value = strtol(str.c_str(), &endptr, 10);
697 return *endptr ? default_value : parsed_value;
698 }
699
700 bool RTLIL::Design::scratchpad_get_bool(const std::string &varname, bool default_value) const
701 {
702 auto it = scratchpad.find(varname);
703 if (it == scratchpad.end())
704 return default_value;
705
706 const std::string &str = it->second;
707
708 if (str == "0" || str == "false")
709 return false;
710
711 if (str == "1" || str == "true")
712 return true;
713
714 return default_value;
715 }
716
717 std::string RTLIL::Design::scratchpad_get_string(const std::string &varname, const std::string &default_value) const
718 {
719 auto it = scratchpad.find(varname);
720 if (it == scratchpad.end())
721 return default_value;
722
723 return it->second;
724 }
725
726 void RTLIL::Design::remove(RTLIL::Module *module)
727 {
728 for (auto mon : monitors)
729 mon->notify_module_del(module);
730
731 if (yosys_xtrace) {
732 log("#X# Remove Module: %s\n", log_id(module));
733 log_backtrace("-X- ", yosys_xtrace-1);
734 }
735
736 log_assert(modules_.at(module->name) == module);
737 log_assert(refcount_modules_ == 0);
738 modules_.erase(module->name);
739 delete module;
740 }
741
742 void RTLIL::Design::rename(RTLIL::Module *module, RTLIL::IdString new_name)
743 {
744 modules_.erase(module->name);
745 module->name = new_name;
746 add(module);
747 }
748
749 void RTLIL::Design::sort()
750 {
751 scratchpad.sort();
752 modules_.sort(sort_by_id_str());
753 for (auto &it : modules_)
754 it.second->sort();
755 }
756
757 void RTLIL::Design::check()
758 {
759 #ifndef NDEBUG
760 for (auto &it : modules_) {
761 log_assert(this == it.second->design);
762 log_assert(it.first == it.second->name);
763 log_assert(!it.first.empty());
764 it.second->check();
765 }
766 #endif
767 }
768
769 void RTLIL::Design::optimize()
770 {
771 for (auto &it : modules_)
772 it.second->optimize();
773 for (auto &it : selection_stack)
774 it.optimize(this);
775 for (auto &it : selection_vars)
776 it.second.optimize(this);
777 }
778
779 bool RTLIL::Design::selected_module(RTLIL::IdString mod_name) const
780 {
781 if (!selected_active_module.empty() && mod_name != selected_active_module)
782 return false;
783 if (selection_stack.size() == 0)
784 return true;
785 return selection_stack.back().selected_module(mod_name);
786 }
787
788 bool RTLIL::Design::selected_whole_module(RTLIL::IdString mod_name) const
789 {
790 if (!selected_active_module.empty() && mod_name != selected_active_module)
791 return false;
792 if (selection_stack.size() == 0)
793 return true;
794 return selection_stack.back().selected_whole_module(mod_name);
795 }
796
797 bool RTLIL::Design::selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const
798 {
799 if (!selected_active_module.empty() && mod_name != selected_active_module)
800 return false;
801 if (selection_stack.size() == 0)
802 return true;
803 return selection_stack.back().selected_member(mod_name, memb_name);
804 }
805
806 bool RTLIL::Design::selected_module(RTLIL::Module *mod) const
807 {
808 return selected_module(mod->name);
809 }
810
811 bool RTLIL::Design::selected_whole_module(RTLIL::Module *mod) const
812 {
813 return selected_whole_module(mod->name);
814 }
815
816 std::vector<RTLIL::Module*> RTLIL::Design::selected_modules() const
817 {
818 std::vector<RTLIL::Module*> result;
819 result.reserve(modules_.size());
820 for (auto &it : modules_)
821 if (selected_module(it.first) && !it.second->get_blackbox_attribute())
822 result.push_back(it.second);
823 return result;
824 }
825
826 std::vector<RTLIL::Module*> RTLIL::Design::selected_whole_modules() const
827 {
828 std::vector<RTLIL::Module*> result;
829 result.reserve(modules_.size());
830 for (auto &it : modules_)
831 if (selected_whole_module(it.first) && !it.second->get_blackbox_attribute())
832 result.push_back(it.second);
833 return result;
834 }
835
836 std::vector<RTLIL::Module*> RTLIL::Design::selected_whole_modules_warn(bool include_wb) const
837 {
838 std::vector<RTLIL::Module*> result;
839 result.reserve(modules_.size());
840 for (auto &it : modules_)
841 if (it.second->get_blackbox_attribute(include_wb))
842 continue;
843 else if (selected_whole_module(it.first))
844 result.push_back(it.second);
845 else if (selected_module(it.first))
846 log_warning("Ignoring partially selected module %s.\n", log_id(it.first));
847 return result;
848 }
849
850 RTLIL::Module::Module()
851 {
852 static unsigned int hashidx_count = 123456789;
853 hashidx_count = mkhash_xorshift(hashidx_count);
854 hashidx_ = hashidx_count;
855
856 design = nullptr;
857 refcount_wires_ = 0;
858 refcount_cells_ = 0;
859
860 #ifdef WITH_PYTHON
861 RTLIL::Module::get_all_modules()->insert(std::pair<unsigned int, RTLIL::Module*>(hashidx_, this));
862 #endif
863 }
864
865 RTLIL::Module::~Module()
866 {
867 for (auto &pr : wires_)
868 delete pr.second;
869 for (auto &pr : memories)
870 delete pr.second;
871 for (auto &pr : cells_)
872 delete pr.second;
873 for (auto &pr : processes)
874 delete pr.second;
875 #ifdef WITH_PYTHON
876 RTLIL::Module::get_all_modules()->erase(hashidx_);
877 #endif
878 }
879
880 #ifdef WITH_PYTHON
881 static std::map<unsigned int, RTLIL::Module*> all_modules;
882 std::map<unsigned int, RTLIL::Module*> *RTLIL::Module::get_all_modules(void)
883 {
884 return &all_modules;
885 }
886 #endif
887
888 void RTLIL::Module::makeblackbox()
889 {
890 pool<RTLIL::Wire*> delwires;
891
892 for (auto it = wires_.begin(); it != wires_.end(); ++it)
893 if (!it->second->port_input && !it->second->port_output)
894 delwires.insert(it->second);
895
896 for (auto it = memories.begin(); it != memories.end(); ++it)
897 delete it->second;
898 memories.clear();
899
900 for (auto it = cells_.begin(); it != cells_.end(); ++it)
901 delete it->second;
902 cells_.clear();
903
904 for (auto it = processes.begin(); it != processes.end(); ++it)
905 delete it->second;
906 processes.clear();
907
908 connections_.clear();
909
910 remove(delwires);
911 set_bool_attribute(ID::blackbox);
912 }
913
914 void RTLIL::Module::reprocess_module(RTLIL::Design *, const dict<RTLIL::IdString, RTLIL::Module *> &)
915 {
916 log_error("Cannot reprocess_module module `%s' !\n", id2cstr(name));
917 }
918
919 RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, const dict<RTLIL::IdString, RTLIL::Const> &, bool mayfail)
920 {
921 if (mayfail)
922 return RTLIL::IdString();
923 log_error("Module `%s' is used with parameters but is not parametric!\n", id2cstr(name));
924 }
925
926
927 RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, const dict<RTLIL::IdString, RTLIL::Const> &, const dict<RTLIL::IdString, RTLIL::Module*> &, const dict<RTLIL::IdString, RTLIL::IdString> &, bool mayfail)
928 {
929 if (mayfail)
930 return RTLIL::IdString();
931 log_error("Module `%s' is used with parameters but is not parametric!\n", id2cstr(name));
932 }
933
934 size_t RTLIL::Module::count_id(RTLIL::IdString id)
935 {
936 return wires_.count(id) + memories.count(id) + cells_.count(id) + processes.count(id);
937 }
938
939 #ifndef NDEBUG
940 namespace {
941 struct InternalCellChecker
942 {
943 RTLIL::Module *module;
944 RTLIL::Cell *cell;
945 pool<RTLIL::IdString> expected_params, expected_ports;
946
947 InternalCellChecker(RTLIL::Module *module, RTLIL::Cell *cell) : module(module), cell(cell) { }
948
949 void error(int linenr)
950 {
951 std::stringstream buf;
952 RTLIL_BACKEND::dump_cell(buf, " ", cell);
953
954 log_error("Found error in internal cell %s%s%s (%s) at %s:%d:\n%s",
955 module ? module->name.c_str() : "", module ? "." : "",
956 cell->name.c_str(), cell->type.c_str(), __FILE__, linenr, buf.str().c_str());
957 }
958
959 int param(RTLIL::IdString name)
960 {
961 auto it = cell->parameters.find(name);
962 if (it == cell->parameters.end())
963 error(__LINE__);
964 expected_params.insert(name);
965 return it->second.as_int();
966 }
967
968 int param_bool(RTLIL::IdString name)
969 {
970 int v = param(name);
971 if (GetSize(cell->parameters.at(name)) > 32)
972 error(__LINE__);
973 if (v != 0 && v != 1)
974 error(__LINE__);
975 return v;
976 }
977
978 int param_bool(RTLIL::IdString name, bool expected)
979 {
980 int v = param_bool(name);
981 if (v != expected)
982 error(__LINE__);
983 return v;
984 }
985
986 void param_bits(RTLIL::IdString name, int width)
987 {
988 param(name);
989 if (GetSize(cell->parameters.at(name).bits) != width)
990 error(__LINE__);
991 }
992
993 void port(RTLIL::IdString name, int width)
994 {
995 auto it = cell->connections_.find(name);
996 if (it == cell->connections_.end())
997 error(__LINE__);
998 if (GetSize(it->second) != width)
999 error(__LINE__);
1000 expected_ports.insert(name);
1001 }
1002
1003 void check_expected(bool check_matched_sign = false)
1004 {
1005 for (auto &para : cell->parameters)
1006 if (expected_params.count(para.first) == 0)
1007 error(__LINE__);
1008 for (auto &conn : cell->connections())
1009 if (expected_ports.count(conn.first) == 0)
1010 error(__LINE__);
1011
1012 if (check_matched_sign) {
1013 log_assert(expected_params.count(ID::A_SIGNED) != 0 && expected_params.count(ID::B_SIGNED) != 0);
1014 bool a_is_signed = cell->parameters.at(ID::A_SIGNED).as_bool();
1015 bool b_is_signed = cell->parameters.at(ID::B_SIGNED).as_bool();
1016 if (a_is_signed != b_is_signed)
1017 error(__LINE__);
1018 }
1019 }
1020
1021 void check()
1022 {
1023 if (!cell->type.begins_with("$") || cell->type.begins_with("$__") || cell->type.begins_with("$paramod") || cell->type.begins_with("$fmcombine") ||
1024 cell->type.begins_with("$verific$") || cell->type.begins_with("$array:") || cell->type.begins_with("$extern:"))
1025 return;
1026
1027 if (cell->type.in(ID($not), ID($pos), ID($neg))) {
1028 param_bool(ID::A_SIGNED);
1029 port(ID::A, param(ID::A_WIDTH));
1030 port(ID::Y, param(ID::Y_WIDTH));
1031 check_expected();
1032 return;
1033 }
1034
1035 if (cell->type.in(ID($and), ID($or), ID($xor), ID($xnor))) {
1036 param_bool(ID::A_SIGNED);
1037 param_bool(ID::B_SIGNED);
1038 port(ID::A, param(ID::A_WIDTH));
1039 port(ID::B, param(ID::B_WIDTH));
1040 port(ID::Y, param(ID::Y_WIDTH));
1041 check_expected(true);
1042 return;
1043 }
1044
1045 if (cell->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor), ID($reduce_bool))) {
1046 param_bool(ID::A_SIGNED);
1047 port(ID::A, param(ID::A_WIDTH));
1048 port(ID::Y, param(ID::Y_WIDTH));
1049 check_expected();
1050 return;
1051 }
1052
1053 if (cell->type.in(ID($shl), ID($shr), ID($sshl), ID($sshr))) {
1054 param_bool(ID::A_SIGNED);
1055 param_bool(ID::B_SIGNED, /*expected=*/false);
1056 port(ID::A, param(ID::A_WIDTH));
1057 port(ID::B, param(ID::B_WIDTH));
1058 port(ID::Y, param(ID::Y_WIDTH));
1059 check_expected(/*check_matched_sign=*/false);
1060 return;
1061 }
1062
1063 if (cell->type.in(ID($shift), ID($shiftx))) {
1064 if (cell->type == ID($shiftx)) {
1065 param_bool(ID::A_SIGNED, /*expected=*/false);
1066 } else {
1067 param_bool(ID::A_SIGNED);
1068 }
1069 param_bool(ID::B_SIGNED);
1070 port(ID::A, param(ID::A_WIDTH));
1071 port(ID::B, param(ID::B_WIDTH));
1072 port(ID::Y, param(ID::Y_WIDTH));
1073 check_expected(/*check_matched_sign=*/false);
1074 return;
1075 }
1076
1077 if (cell->type.in(ID($lt), ID($le), ID($eq), ID($ne), ID($eqx), ID($nex), ID($ge), ID($gt))) {
1078 param_bool(ID::A_SIGNED);
1079 param_bool(ID::B_SIGNED);
1080 port(ID::A, param(ID::A_WIDTH));
1081 port(ID::B, param(ID::B_WIDTH));
1082 port(ID::Y, param(ID::Y_WIDTH));
1083 check_expected(true);
1084 return;
1085 }
1086
1087 if (cell->type.in(ID($add), ID($sub), ID($mul), ID($div), ID($mod), ID($divfloor), ID($modfloor), ID($pow))) {
1088 param_bool(ID::A_SIGNED);
1089 param_bool(ID::B_SIGNED);
1090 port(ID::A, param(ID::A_WIDTH));
1091 port(ID::B, param(ID::B_WIDTH));
1092 port(ID::Y, param(ID::Y_WIDTH));
1093 check_expected(cell->type != ID($pow));
1094 return;
1095 }
1096
1097 if (cell->type == ID($fa)) {
1098 port(ID::A, param(ID::WIDTH));
1099 port(ID::B, param(ID::WIDTH));
1100 port(ID::C, param(ID::WIDTH));
1101 port(ID::X, param(ID::WIDTH));
1102 port(ID::Y, param(ID::WIDTH));
1103 check_expected();
1104 return;
1105 }
1106
1107 if (cell->type == ID($lcu)) {
1108 port(ID::P, param(ID::WIDTH));
1109 port(ID::G, param(ID::WIDTH));
1110 port(ID::CI, 1);
1111 port(ID::CO, param(ID::WIDTH));
1112 check_expected();
1113 return;
1114 }
1115
1116 if (cell->type == ID($alu)) {
1117 param_bool(ID::A_SIGNED);
1118 param_bool(ID::B_SIGNED);
1119 port(ID::A, param(ID::A_WIDTH));
1120 port(ID::B, param(ID::B_WIDTH));
1121 port(ID::CI, 1);
1122 port(ID::BI, 1);
1123 port(ID::X, param(ID::Y_WIDTH));
1124 port(ID::Y, param(ID::Y_WIDTH));
1125 port(ID::CO, param(ID::Y_WIDTH));
1126 check_expected(true);
1127 return;
1128 }
1129
1130 if (cell->type == ID($macc)) {
1131 param(ID::CONFIG);
1132 param(ID::CONFIG_WIDTH);
1133 port(ID::A, param(ID::A_WIDTH));
1134 port(ID::B, param(ID::B_WIDTH));
1135 port(ID::Y, param(ID::Y_WIDTH));
1136 check_expected();
1137 Macc().from_cell(cell);
1138 return;
1139 }
1140
1141 if (cell->type == ID($logic_not)) {
1142 param_bool(ID::A_SIGNED);
1143 port(ID::A, param(ID::A_WIDTH));
1144 port(ID::Y, param(ID::Y_WIDTH));
1145 check_expected();
1146 return;
1147 }
1148
1149 if (cell->type.in(ID($logic_and), ID($logic_or))) {
1150 param_bool(ID::A_SIGNED);
1151 param_bool(ID::B_SIGNED);
1152 port(ID::A, param(ID::A_WIDTH));
1153 port(ID::B, param(ID::B_WIDTH));
1154 port(ID::Y, param(ID::Y_WIDTH));
1155 check_expected(/*check_matched_sign=*/false);
1156 return;
1157 }
1158
1159 if (cell->type == ID($slice)) {
1160 param(ID::OFFSET);
1161 port(ID::A, param(ID::A_WIDTH));
1162 port(ID::Y, param(ID::Y_WIDTH));
1163 if (param(ID::OFFSET) + param(ID::Y_WIDTH) > param(ID::A_WIDTH))
1164 error(__LINE__);
1165 check_expected();
1166 return;
1167 }
1168
1169 if (cell->type == ID($concat)) {
1170 port(ID::A, param(ID::A_WIDTH));
1171 port(ID::B, param(ID::B_WIDTH));
1172 port(ID::Y, param(ID::A_WIDTH) + param(ID::B_WIDTH));
1173 check_expected();
1174 return;
1175 }
1176
1177 if (cell->type == ID($mux)) {
1178 port(ID::A, param(ID::WIDTH));
1179 port(ID::B, param(ID::WIDTH));
1180 port(ID::S, 1);
1181 port(ID::Y, param(ID::WIDTH));
1182 check_expected();
1183 return;
1184 }
1185
1186 if (cell->type == ID($pmux)) {
1187 port(ID::A, param(ID::WIDTH));
1188 port(ID::B, param(ID::WIDTH) * param(ID::S_WIDTH));
1189 port(ID::S, param(ID::S_WIDTH));
1190 port(ID::Y, param(ID::WIDTH));
1191 check_expected();
1192 return;
1193 }
1194
1195 if (cell->type == ID($lut)) {
1196 param(ID::LUT);
1197 port(ID::A, param(ID::WIDTH));
1198 port(ID::Y, 1);
1199 check_expected();
1200 return;
1201 }
1202
1203 if (cell->type == ID($sop)) {
1204 param(ID::DEPTH);
1205 param(ID::TABLE);
1206 port(ID::A, param(ID::WIDTH));
1207 port(ID::Y, 1);
1208 check_expected();
1209 return;
1210 }
1211
1212 if (cell->type == ID($sr)) {
1213 param_bool(ID::SET_POLARITY);
1214 param_bool(ID::CLR_POLARITY);
1215 port(ID::SET, param(ID::WIDTH));
1216 port(ID::CLR, param(ID::WIDTH));
1217 port(ID::Q, param(ID::WIDTH));
1218 check_expected();
1219 return;
1220 }
1221
1222 if (cell->type == ID($ff)) {
1223 port(ID::D, param(ID::WIDTH));
1224 port(ID::Q, param(ID::WIDTH));
1225 check_expected();
1226 return;
1227 }
1228
1229 if (cell->type == ID($dff)) {
1230 param_bool(ID::CLK_POLARITY);
1231 port(ID::CLK, 1);
1232 port(ID::D, param(ID::WIDTH));
1233 port(ID::Q, param(ID::WIDTH));
1234 check_expected();
1235 return;
1236 }
1237
1238 if (cell->type == ID($dffe)) {
1239 param_bool(ID::CLK_POLARITY);
1240 param_bool(ID::EN_POLARITY);
1241 port(ID::CLK, 1);
1242 port(ID::EN, 1);
1243 port(ID::D, param(ID::WIDTH));
1244 port(ID::Q, param(ID::WIDTH));
1245 check_expected();
1246 return;
1247 }
1248
1249 if (cell->type == ID($dffsr)) {
1250 param_bool(ID::CLK_POLARITY);
1251 param_bool(ID::SET_POLARITY);
1252 param_bool(ID::CLR_POLARITY);
1253 port(ID::CLK, 1);
1254 port(ID::SET, param(ID::WIDTH));
1255 port(ID::CLR, param(ID::WIDTH));
1256 port(ID::D, param(ID::WIDTH));
1257 port(ID::Q, param(ID::WIDTH));
1258 check_expected();
1259 return;
1260 }
1261
1262 if (cell->type == ID($dffsre)) {
1263 param_bool(ID::CLK_POLARITY);
1264 param_bool(ID::SET_POLARITY);
1265 param_bool(ID::CLR_POLARITY);
1266 param_bool(ID::EN_POLARITY);
1267 port(ID::CLK, 1);
1268 port(ID::EN, 1);
1269 port(ID::SET, param(ID::WIDTH));
1270 port(ID::CLR, param(ID::WIDTH));
1271 port(ID::D, param(ID::WIDTH));
1272 port(ID::Q, param(ID::WIDTH));
1273 check_expected();
1274 return;
1275 }
1276
1277 if (cell->type == ID($adff)) {
1278 param_bool(ID::CLK_POLARITY);
1279 param_bool(ID::ARST_POLARITY);
1280 param_bits(ID::ARST_VALUE, param(ID::WIDTH));
1281 port(ID::CLK, 1);
1282 port(ID::ARST, 1);
1283 port(ID::D, param(ID::WIDTH));
1284 port(ID::Q, param(ID::WIDTH));
1285 check_expected();
1286 return;
1287 }
1288
1289 if (cell->type == ID($sdff)) {
1290 param_bool(ID::CLK_POLARITY);
1291 param_bool(ID::SRST_POLARITY);
1292 param_bits(ID::SRST_VALUE, param(ID::WIDTH));
1293 port(ID::CLK, 1);
1294 port(ID::SRST, 1);
1295 port(ID::D, param(ID::WIDTH));
1296 port(ID::Q, param(ID::WIDTH));
1297 check_expected();
1298 return;
1299 }
1300
1301 if (cell->type.in(ID($sdffe), ID($sdffce))) {
1302 param_bool(ID::CLK_POLARITY);
1303 param_bool(ID::EN_POLARITY);
1304 param_bool(ID::SRST_POLARITY);
1305 param_bits(ID::SRST_VALUE, param(ID::WIDTH));
1306 port(ID::CLK, 1);
1307 port(ID::EN, 1);
1308 port(ID::SRST, 1);
1309 port(ID::D, param(ID::WIDTH));
1310 port(ID::Q, param(ID::WIDTH));
1311 check_expected();
1312 return;
1313 }
1314
1315 if (cell->type == ID($adffe)) {
1316 param_bool(ID::CLK_POLARITY);
1317 param_bool(ID::EN_POLARITY);
1318 param_bool(ID::ARST_POLARITY);
1319 param_bits(ID::ARST_VALUE, param(ID::WIDTH));
1320 port(ID::CLK, 1);
1321 port(ID::EN, 1);
1322 port(ID::ARST, 1);
1323 port(ID::D, param(ID::WIDTH));
1324 port(ID::Q, param(ID::WIDTH));
1325 check_expected();
1326 return;
1327 }
1328
1329 if (cell->type == ID($dlatch)) {
1330 param_bool(ID::EN_POLARITY);
1331 port(ID::EN, 1);
1332 port(ID::D, param(ID::WIDTH));
1333 port(ID::Q, param(ID::WIDTH));
1334 check_expected();
1335 return;
1336 }
1337
1338 if (cell->type == ID($adlatch)) {
1339 param_bool(ID::EN_POLARITY);
1340 param_bool(ID::ARST_POLARITY);
1341 param_bits(ID::ARST_VALUE, param(ID::WIDTH));
1342 port(ID::EN, 1);
1343 port(ID::ARST, 1);
1344 port(ID::D, param(ID::WIDTH));
1345 port(ID::Q, param(ID::WIDTH));
1346 check_expected();
1347 return;
1348 }
1349
1350 if (cell->type == ID($dlatchsr)) {
1351 param_bool(ID::EN_POLARITY);
1352 param_bool(ID::SET_POLARITY);
1353 param_bool(ID::CLR_POLARITY);
1354 port(ID::EN, 1);
1355 port(ID::SET, param(ID::WIDTH));
1356 port(ID::CLR, param(ID::WIDTH));
1357 port(ID::D, param(ID::WIDTH));
1358 port(ID::Q, param(ID::WIDTH));
1359 check_expected();
1360 return;
1361 }
1362
1363 if (cell->type == ID($fsm)) {
1364 param(ID::NAME);
1365 param_bool(ID::CLK_POLARITY);
1366 param_bool(ID::ARST_POLARITY);
1367 param(ID::STATE_BITS);
1368 param(ID::STATE_NUM);
1369 param(ID::STATE_NUM_LOG2);
1370 param(ID::STATE_RST);
1371 param_bits(ID::STATE_TABLE, param(ID::STATE_BITS) * param(ID::STATE_NUM));
1372 param(ID::TRANS_NUM);
1373 param_bits(ID::TRANS_TABLE, param(ID::TRANS_NUM) * (2*param(ID::STATE_NUM_LOG2) + param(ID::CTRL_IN_WIDTH) + param(ID::CTRL_OUT_WIDTH)));
1374 port(ID::CLK, 1);
1375 port(ID::ARST, 1);
1376 port(ID::CTRL_IN, param(ID::CTRL_IN_WIDTH));
1377 port(ID::CTRL_OUT, param(ID::CTRL_OUT_WIDTH));
1378 check_expected();
1379 return;
1380 }
1381
1382 if (cell->type == ID($memrd)) {
1383 param(ID::MEMID);
1384 param_bool(ID::CLK_ENABLE);
1385 param_bool(ID::CLK_POLARITY);
1386 param_bool(ID::TRANSPARENT);
1387 port(ID::CLK, 1);
1388 port(ID::EN, 1);
1389 port(ID::ADDR, param(ID::ABITS));
1390 port(ID::DATA, param(ID::WIDTH));
1391 check_expected();
1392 return;
1393 }
1394
1395 if (cell->type == ID($memwr)) {
1396 param(ID::MEMID);
1397 param_bool(ID::CLK_ENABLE);
1398 param_bool(ID::CLK_POLARITY);
1399 param(ID::PRIORITY);
1400 port(ID::CLK, 1);
1401 port(ID::EN, param(ID::WIDTH));
1402 port(ID::ADDR, param(ID::ABITS));
1403 port(ID::DATA, param(ID::WIDTH));
1404 check_expected();
1405 return;
1406 }
1407
1408 if (cell->type == ID($meminit)) {
1409 param(ID::MEMID);
1410 param(ID::PRIORITY);
1411 port(ID::ADDR, param(ID::ABITS));
1412 port(ID::DATA, param(ID::WIDTH) * param(ID::WORDS));
1413 check_expected();
1414 return;
1415 }
1416
1417 if (cell->type == ID($mem)) {
1418 param(ID::MEMID);
1419 param(ID::SIZE);
1420 param(ID::OFFSET);
1421 param(ID::INIT);
1422 param_bits(ID::RD_CLK_ENABLE, max(1, param(ID::RD_PORTS)));
1423 param_bits(ID::RD_CLK_POLARITY, max(1, param(ID::RD_PORTS)));
1424 param_bits(ID::RD_TRANSPARENT, max(1, param(ID::RD_PORTS)));
1425 param_bits(ID::WR_CLK_ENABLE, max(1, param(ID::WR_PORTS)));
1426 param_bits(ID::WR_CLK_POLARITY, max(1, param(ID::WR_PORTS)));
1427 port(ID::RD_CLK, param(ID::RD_PORTS));
1428 port(ID::RD_EN, param(ID::RD_PORTS));
1429 port(ID::RD_ADDR, param(ID::RD_PORTS) * param(ID::ABITS));
1430 port(ID::RD_DATA, param(ID::RD_PORTS) * param(ID::WIDTH));
1431 port(ID::WR_CLK, param(ID::WR_PORTS));
1432 port(ID::WR_EN, param(ID::WR_PORTS) * param(ID::WIDTH));
1433 port(ID::WR_ADDR, param(ID::WR_PORTS) * param(ID::ABITS));
1434 port(ID::WR_DATA, param(ID::WR_PORTS) * param(ID::WIDTH));
1435 check_expected();
1436 return;
1437 }
1438
1439 if (cell->type == ID($tribuf)) {
1440 port(ID::A, param(ID::WIDTH));
1441 port(ID::Y, param(ID::WIDTH));
1442 port(ID::EN, 1);
1443 check_expected();
1444 return;
1445 }
1446
1447 if (cell->type.in(ID($assert), ID($assume), ID($live), ID($fair), ID($cover))) {
1448 port(ID::A, 1);
1449 port(ID::EN, 1);
1450 check_expected();
1451 return;
1452 }
1453
1454 if (cell->type == ID($initstate)) {
1455 port(ID::Y, 1);
1456 check_expected();
1457 return;
1458 }
1459
1460 if (cell->type.in(ID($anyconst), ID($anyseq), ID($allconst), ID($allseq))) {
1461 port(ID::Y, param(ID::WIDTH));
1462 check_expected();
1463 return;
1464 }
1465
1466 if (cell->type == ID($equiv)) {
1467 port(ID::A, 1);
1468 port(ID::B, 1);
1469 port(ID::Y, 1);
1470 check_expected();
1471 return;
1472 }
1473
1474 if (cell->type.in(ID($specify2), ID($specify3))) {
1475 param_bool(ID::FULL);
1476 param_bool(ID::SRC_DST_PEN);
1477 param_bool(ID::SRC_DST_POL);
1478 param(ID::T_RISE_MIN);
1479 param(ID::T_RISE_TYP);
1480 param(ID::T_RISE_MAX);
1481 param(ID::T_FALL_MIN);
1482 param(ID::T_FALL_TYP);
1483 param(ID::T_FALL_MAX);
1484 port(ID::EN, 1);
1485 port(ID::SRC, param(ID::SRC_WIDTH));
1486 port(ID::DST, param(ID::DST_WIDTH));
1487 if (cell->type == ID($specify3)) {
1488 param_bool(ID::EDGE_EN);
1489 param_bool(ID::EDGE_POL);
1490 param_bool(ID::DAT_DST_PEN);
1491 param_bool(ID::DAT_DST_POL);
1492 port(ID::DAT, param(ID::DST_WIDTH));
1493 }
1494 check_expected();
1495 return;
1496 }
1497
1498 if (cell->type == ID($specrule)) {
1499 param(ID::TYPE);
1500 param_bool(ID::SRC_PEN);
1501 param_bool(ID::SRC_POL);
1502 param_bool(ID::DST_PEN);
1503 param_bool(ID::DST_POL);
1504 param(ID::T_LIMIT_MIN);
1505 param(ID::T_LIMIT_TYP);
1506 param(ID::T_LIMIT_MAX);
1507 param(ID::T_LIMIT2_MIN);
1508 param(ID::T_LIMIT2_TYP);
1509 param(ID::T_LIMIT2_MAX);
1510 port(ID::SRC_EN, 1);
1511 port(ID::DST_EN, 1);
1512 port(ID::SRC, param(ID::SRC_WIDTH));
1513 port(ID::DST, param(ID::DST_WIDTH));
1514 check_expected();
1515 return;
1516 }
1517
1518 if (cell->type == ID($_BUF_)) { port(ID::A,1); port(ID::Y,1); check_expected(); return; }
1519 if (cell->type == ID($_NOT_)) { port(ID::A,1); port(ID::Y,1); check_expected(); return; }
1520 if (cell->type == ID($_AND_)) { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; }
1521 if (cell->type == ID($_NAND_)) { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; }
1522 if (cell->type == ID($_OR_)) { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; }
1523 if (cell->type == ID($_NOR_)) { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; }
1524 if (cell->type == ID($_XOR_)) { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; }
1525 if (cell->type == ID($_XNOR_)) { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; }
1526 if (cell->type == ID($_ANDNOT_)) { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; }
1527 if (cell->type == ID($_ORNOT_)) { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; }
1528 if (cell->type == ID($_MUX_)) { port(ID::A,1); port(ID::B,1); port(ID::S,1); port(ID::Y,1); check_expected(); return; }
1529 if (cell->type == ID($_NMUX_)) { port(ID::A,1); port(ID::B,1); port(ID::S,1); port(ID::Y,1); check_expected(); return; }
1530 if (cell->type == ID($_AOI3_)) { port(ID::A,1); port(ID::B,1); port(ID::C,1); port(ID::Y,1); check_expected(); return; }
1531 if (cell->type == ID($_OAI3_)) { port(ID::A,1); port(ID::B,1); port(ID::C,1); port(ID::Y,1); check_expected(); return; }
1532 if (cell->type == ID($_AOI4_)) { port(ID::A,1); port(ID::B,1); port(ID::C,1); port(ID::D,1); port(ID::Y,1); check_expected(); return; }
1533 if (cell->type == ID($_OAI4_)) { port(ID::A,1); port(ID::B,1); port(ID::C,1); port(ID::D,1); port(ID::Y,1); check_expected(); return; }
1534
1535 if (cell->type == ID($_TBUF_)) { port(ID::A,1); port(ID::Y,1); port(ID::E,1); check_expected(); return; }
1536
1537 if (cell->type == ID($_MUX4_)) { port(ID::A,1); port(ID::B,1); port(ID::C,1); port(ID::D,1); port(ID::S,1); port(ID::T,1); port(ID::Y,1); check_expected(); return; }
1538 if (cell->type == ID($_MUX8_)) { port(ID::A,1); port(ID::B,1); port(ID::C,1); port(ID::D,1); port(ID::E,1); port(ID::F,1); port(ID::G,1); port(ID::H,1); port(ID::S,1); port(ID::T,1); port(ID::U,1); port(ID::Y,1); check_expected(); return; }
1539 if (cell->type == ID($_MUX16_)) { port(ID::A,1); port(ID::B,1); port(ID::C,1); port(ID::D,1); port(ID::E,1); port(ID::F,1); port(ID::G,1); port(ID::H,1); port(ID::I,1); port(ID::J,1); port(ID::K,1); port(ID::L,1); port(ID::M,1); port(ID::N,1); port(ID::O,1); port(ID::P,1); port(ID::S,1); port(ID::T,1); port(ID::U,1); port(ID::V,1); port(ID::Y,1); check_expected(); return; }
1540
1541 if (cell->type.in(ID($_SR_NN_), ID($_SR_NP_), ID($_SR_PN_), ID($_SR_PP_)))
1542 { port(ID::S,1); port(ID::R,1); port(ID::Q,1); check_expected(); return; }
1543
1544 if (cell->type == ID($_FF_)) { port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1545
1546 if (cell->type.in(ID($_DFF_N_), ID($_DFF_P_)))
1547 { port(ID::D,1); port(ID::Q,1); port(ID::C,1); check_expected(); return; }
1548
1549 if (cell->type.in(ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_)))
1550 { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::E,1); check_expected(); return; }
1551
1552 if (cell->type.in(
1553 ID($_DFF_NN0_), ID($_DFF_NN1_), ID($_DFF_NP0_), ID($_DFF_NP1_),
1554 ID($_DFF_PN0_), ID($_DFF_PN1_), ID($_DFF_PP0_), ID($_DFF_PP1_)))
1555 { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::R,1); check_expected(); return; }
1556
1557 if (cell->type.in(
1558 ID($_DFFE_NN0N_), ID($_DFFE_NN0P_), ID($_DFFE_NN1N_), ID($_DFFE_NN1P_),
1559 ID($_DFFE_NP0N_), ID($_DFFE_NP0P_), ID($_DFFE_NP1N_), ID($_DFFE_NP1P_),
1560 ID($_DFFE_PN0N_), ID($_DFFE_PN0P_), ID($_DFFE_PN1N_), ID($_DFFE_PN1P_),
1561 ID($_DFFE_PP0N_), ID($_DFFE_PP0P_), ID($_DFFE_PP1N_), ID($_DFFE_PP1P_)))
1562 { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::R,1); port(ID::E,1); check_expected(); return; }
1563
1564 if (cell->type.in(
1565 ID($_DFFSR_NNN_), ID($_DFFSR_NNP_), ID($_DFFSR_NPN_), ID($_DFFSR_NPP_),
1566 ID($_DFFSR_PNN_), ID($_DFFSR_PNP_), ID($_DFFSR_PPN_), ID($_DFFSR_PPP_)))
1567 { port(ID::C,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1568
1569 if (cell->type.in(
1570 ID($_DFFSRE_NNNN_), ID($_DFFSRE_NNNP_), ID($_DFFSRE_NNPN_), ID($_DFFSRE_NNPP_),
1571 ID($_DFFSRE_NPNN_), ID($_DFFSRE_NPNP_), ID($_DFFSRE_NPPN_), ID($_DFFSRE_NPPP_),
1572 ID($_DFFSRE_PNNN_), ID($_DFFSRE_PNNP_), ID($_DFFSRE_PNPN_), ID($_DFFSRE_PNPP_),
1573 ID($_DFFSRE_PPNN_), ID($_DFFSRE_PPNP_), ID($_DFFSRE_PPPN_), ID($_DFFSRE_PPPP_)))
1574 { port(ID::C,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::E,1); port(ID::Q,1); check_expected(); return; }
1575
1576 if (cell->type.in(
1577 ID($_SDFF_NN0_), ID($_SDFF_NN1_), ID($_SDFF_NP0_), ID($_SDFF_NP1_),
1578 ID($_SDFF_PN0_), ID($_SDFF_PN1_), ID($_SDFF_PP0_), ID($_SDFF_PP1_)))
1579 { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::R,1); check_expected(); return; }
1580
1581 if (cell->type.in(
1582 ID($_SDFFE_NN0N_), ID($_SDFFE_NN0P_), ID($_SDFFE_NN1N_), ID($_SDFFE_NN1P_),
1583 ID($_SDFFE_NP0N_), ID($_SDFFE_NP0P_), ID($_SDFFE_NP1N_), ID($_SDFFE_NP1P_),
1584 ID($_SDFFE_PN0N_), ID($_SDFFE_PN0P_), ID($_SDFFE_PN1N_), ID($_SDFFE_PN1P_),
1585 ID($_SDFFE_PP0N_), ID($_SDFFE_PP0P_), ID($_SDFFE_PP1N_), ID($_SDFFE_PP1P_),
1586 ID($_SDFFCE_NN0N_), ID($_SDFFCE_NN0P_), ID($_SDFFCE_NN1N_), ID($_SDFFCE_NN1P_),
1587 ID($_SDFFCE_NP0N_), ID($_SDFFCE_NP0P_), ID($_SDFFCE_NP1N_), ID($_SDFFCE_NP1P_),
1588 ID($_SDFFCE_PN0N_), ID($_SDFFCE_PN0P_), ID($_SDFFCE_PN1N_), ID($_SDFFCE_PN1P_),
1589 ID($_SDFFCE_PP0N_), ID($_SDFFCE_PP0P_), ID($_SDFFCE_PP1N_), ID($_SDFFCE_PP1P_)))
1590 { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::R,1); port(ID::E,1); check_expected(); return; }
1591
1592 if (cell->type.in(ID($_DLATCH_N_), ID($_DLATCH_P_)))
1593 { port(ID::E,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1594
1595 if (cell->type.in(
1596 ID($_DLATCH_NN0_), ID($_DLATCH_NN1_), ID($_DLATCH_NP0_), ID($_DLATCH_NP1_),
1597 ID($_DLATCH_PN0_), ID($_DLATCH_PN1_), ID($_DLATCH_PP0_), ID($_DLATCH_PP1_)))
1598 { port(ID::E,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1599
1600 if (cell->type.in(
1601 ID($_DLATCHSR_NNN_), ID($_DLATCHSR_NNP_), ID($_DLATCHSR_NPN_), ID($_DLATCHSR_NPP_),
1602 ID($_DLATCHSR_PNN_), ID($_DLATCHSR_PNP_), ID($_DLATCHSR_PPN_), ID($_DLATCHSR_PPP_)))
1603 { port(ID::E,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1604
1605 error(__LINE__);
1606 }
1607 };
1608 }
1609 #endif
1610
1611 void RTLIL::Module::sort()
1612 {
1613 wires_.sort(sort_by_id_str());
1614 cells_.sort(sort_by_id_str());
1615 parameter_default_values.sort(sort_by_id_str());
1616 memories.sort(sort_by_id_str());
1617 processes.sort(sort_by_id_str());
1618 for (auto &it : cells_)
1619 it.second->sort();
1620 for (auto &it : wires_)
1621 it.second->attributes.sort(sort_by_id_str());
1622 for (auto &it : memories)
1623 it.second->attributes.sort(sort_by_id_str());
1624 }
1625
1626 void RTLIL::Module::check()
1627 {
1628 #ifndef NDEBUG
1629 std::vector<bool> ports_declared;
1630 for (auto &it : wires_) {
1631 log_assert(this == it.second->module);
1632 log_assert(it.first == it.second->name);
1633 log_assert(!it.first.empty());
1634 log_assert(it.second->width >= 0);
1635 log_assert(it.second->port_id >= 0);
1636 for (auto &it2 : it.second->attributes)
1637 log_assert(!it2.first.empty());
1638 if (it.second->port_id) {
1639 log_assert(GetSize(ports) >= it.second->port_id);
1640 log_assert(ports.at(it.second->port_id-1) == it.first);
1641 log_assert(it.second->port_input || it.second->port_output);
1642 if (GetSize(ports_declared) < it.second->port_id)
1643 ports_declared.resize(it.second->port_id);
1644 log_assert(ports_declared[it.second->port_id-1] == false);
1645 ports_declared[it.second->port_id-1] = true;
1646 } else
1647 log_assert(!it.second->port_input && !it.second->port_output);
1648 }
1649 for (auto port_declared : ports_declared)
1650 log_assert(port_declared == true);
1651 log_assert(GetSize(ports) == GetSize(ports_declared));
1652
1653 for (auto &it : memories) {
1654 log_assert(it.first == it.second->name);
1655 log_assert(!it.first.empty());
1656 log_assert(it.second->width >= 0);
1657 log_assert(it.second->size >= 0);
1658 for (auto &it2 : it.second->attributes)
1659 log_assert(!it2.first.empty());
1660 }
1661
1662 for (auto &it : cells_) {
1663 log_assert(this == it.second->module);
1664 log_assert(it.first == it.second->name);
1665 log_assert(!it.first.empty());
1666 log_assert(!it.second->type.empty());
1667 for (auto &it2 : it.second->connections()) {
1668 log_assert(!it2.first.empty());
1669 it2.second.check();
1670 }
1671 for (auto &it2 : it.second->attributes)
1672 log_assert(!it2.first.empty());
1673 for (auto &it2 : it.second->parameters)
1674 log_assert(!it2.first.empty());
1675 InternalCellChecker checker(this, it.second);
1676 checker.check();
1677 }
1678
1679 for (auto &it : processes) {
1680 log_assert(it.first == it.second->name);
1681 log_assert(!it.first.empty());
1682 log_assert(it.second->root_case.compare.empty());
1683 std::vector<CaseRule*> all_cases = {&it.second->root_case};
1684 for (size_t i = 0; i < all_cases.size(); i++) {
1685 for (auto &switch_it : all_cases[i]->switches) {
1686 for (auto &case_it : switch_it->cases) {
1687 for (auto &compare_it : case_it->compare) {
1688 log_assert(switch_it->signal.size() == compare_it.size());
1689 }
1690 all_cases.push_back(case_it);
1691 }
1692 }
1693 }
1694 for (auto &sync_it : it.second->syncs) {
1695 switch (sync_it->type) {
1696 case SyncType::ST0:
1697 case SyncType::ST1:
1698 case SyncType::STp:
1699 case SyncType::STn:
1700 case SyncType::STe:
1701 log_assert(!sync_it->signal.empty());
1702 break;
1703 case SyncType::STa:
1704 case SyncType::STg:
1705 case SyncType::STi:
1706 log_assert(sync_it->signal.empty());
1707 break;
1708 }
1709 }
1710 }
1711
1712 for (auto &it : connections_) {
1713 log_assert(it.first.size() == it.second.size());
1714 log_assert(!it.first.has_const());
1715 it.first.check();
1716 it.second.check();
1717 }
1718
1719 for (auto &it : attributes)
1720 log_assert(!it.first.empty());
1721 #endif
1722 }
1723
1724 void RTLIL::Module::optimize()
1725 {
1726 }
1727
1728 void RTLIL::Module::cloneInto(RTLIL::Module *new_mod) const
1729 {
1730 log_assert(new_mod->refcount_wires_ == 0);
1731 log_assert(new_mod->refcount_cells_ == 0);
1732
1733 new_mod->avail_parameters = avail_parameters;
1734 new_mod->parameter_default_values = parameter_default_values;
1735
1736 for (auto &conn : connections_)
1737 new_mod->connect(conn);
1738
1739 for (auto &attr : attributes)
1740 new_mod->attributes[attr.first] = attr.second;
1741
1742 for (auto &it : wires_)
1743 new_mod->addWire(it.first, it.second);
1744
1745 for (auto &it : memories)
1746 new_mod->addMemory(it.first, it.second);
1747
1748 for (auto &it : cells_)
1749 new_mod->addCell(it.first, it.second);
1750
1751 for (auto &it : processes)
1752 new_mod->addProcess(it.first, it.second);
1753
1754 struct RewriteSigSpecWorker
1755 {
1756 RTLIL::Module *mod;
1757 void operator()(RTLIL::SigSpec &sig)
1758 {
1759 sig.pack();
1760 for (auto &c : sig.chunks_)
1761 if (c.wire != NULL)
1762 c.wire = mod->wires_.at(c.wire->name);
1763 }
1764 };
1765
1766 RewriteSigSpecWorker rewriteSigSpecWorker;
1767 rewriteSigSpecWorker.mod = new_mod;
1768 new_mod->rewrite_sigspecs(rewriteSigSpecWorker);
1769 new_mod->fixup_ports();
1770 }
1771
1772 RTLIL::Module *RTLIL::Module::clone() const
1773 {
1774 RTLIL::Module *new_mod = new RTLIL::Module;
1775 new_mod->name = name;
1776 cloneInto(new_mod);
1777 return new_mod;
1778 }
1779
1780 bool RTLIL::Module::has_memories() const
1781 {
1782 return !memories.empty();
1783 }
1784
1785 bool RTLIL::Module::has_processes() const
1786 {
1787 return !processes.empty();
1788 }
1789
1790 bool RTLIL::Module::has_memories_warn() const
1791 {
1792 if (!memories.empty())
1793 log_warning("Ignoring module %s because it contains memories (run 'memory' command first).\n", log_id(this));
1794 return !memories.empty();
1795 }
1796
1797 bool RTLIL::Module::has_processes_warn() const
1798 {
1799 if (!processes.empty())
1800 log_warning("Ignoring module %s because it contains processes (run 'proc' command first).\n", log_id(this));
1801 return !processes.empty();
1802 }
1803
1804 std::vector<RTLIL::Wire*> RTLIL::Module::selected_wires() const
1805 {
1806 std::vector<RTLIL::Wire*> result;
1807 result.reserve(wires_.size());
1808 for (auto &it : wires_)
1809 if (design->selected(this, it.second))
1810 result.push_back(it.second);
1811 return result;
1812 }
1813
1814 std::vector<RTLIL::Cell*> RTLIL::Module::selected_cells() const
1815 {
1816 std::vector<RTLIL::Cell*> result;
1817 result.reserve(cells_.size());
1818 for (auto &it : cells_)
1819 if (design->selected(this, it.second))
1820 result.push_back(it.second);
1821 return result;
1822 }
1823
1824 void RTLIL::Module::add(RTLIL::Wire *wire)
1825 {
1826 log_assert(!wire->name.empty());
1827 log_assert(count_id(wire->name) == 0);
1828 log_assert(refcount_wires_ == 0);
1829 wires_[wire->name] = wire;
1830 wire->module = this;
1831 }
1832
1833 void RTLIL::Module::add(RTLIL::Cell *cell)
1834 {
1835 log_assert(!cell->name.empty());
1836 log_assert(count_id(cell->name) == 0);
1837 log_assert(refcount_cells_ == 0);
1838 cells_[cell->name] = cell;
1839 cell->module = this;
1840 }
1841
1842 void RTLIL::Module::add(RTLIL::Process *process)
1843 {
1844 log_assert(!process->name.empty());
1845 log_assert(count_id(process->name) == 0);
1846 processes[process->name] = process;
1847 process->module = this;
1848 }
1849
1850 void RTLIL::Module::remove(const pool<RTLIL::Wire*> &wires)
1851 {
1852 log_assert(refcount_wires_ == 0);
1853
1854 struct DeleteWireWorker
1855 {
1856 RTLIL::Module *module;
1857 const pool<RTLIL::Wire*> *wires_p;
1858
1859 void operator()(RTLIL::SigSpec &sig) {
1860 sig.pack();
1861 for (auto &c : sig.chunks_)
1862 if (c.wire != NULL && wires_p->count(c.wire)) {
1863 c.wire = module->addWire(stringf("$delete_wire$%d", autoidx++), c.width);
1864 c.offset = 0;
1865 }
1866 }
1867
1868 void operator()(RTLIL::SigSpec &lhs, RTLIL::SigSpec &rhs) {
1869 log_assert(GetSize(lhs) == GetSize(rhs));
1870 lhs.unpack();
1871 rhs.unpack();
1872 for (int i = 0; i < GetSize(lhs); i++) {
1873 RTLIL::SigBit &lhs_bit = lhs.bits_[i];
1874 RTLIL::SigBit &rhs_bit = rhs.bits_[i];
1875 if ((lhs_bit.wire != nullptr && wires_p->count(lhs_bit.wire)) || (rhs_bit.wire != nullptr && wires_p->count(rhs_bit.wire))) {
1876 lhs_bit = State::Sx;
1877 rhs_bit = State::Sx;
1878 }
1879 }
1880 }
1881 };
1882
1883 DeleteWireWorker delete_wire_worker;
1884 delete_wire_worker.module = this;
1885 delete_wire_worker.wires_p = &wires;
1886 rewrite_sigspecs2(delete_wire_worker);
1887
1888 for (auto &it : wires) {
1889 log_assert(wires_.count(it->name) != 0);
1890 wires_.erase(it->name);
1891 delete it;
1892 }
1893 }
1894
1895 void RTLIL::Module::remove(RTLIL::Cell *cell)
1896 {
1897 while (!cell->connections_.empty())
1898 cell->unsetPort(cell->connections_.begin()->first);
1899
1900 log_assert(cells_.count(cell->name) != 0);
1901 log_assert(refcount_cells_ == 0);
1902 cells_.erase(cell->name);
1903 delete cell;
1904 }
1905
1906 void RTLIL::Module::remove(RTLIL::Process *process)
1907 {
1908 log_assert(processes.count(process->name) != 0);
1909 processes.erase(process->name);
1910 delete process;
1911 }
1912
1913 void RTLIL::Module::rename(RTLIL::Wire *wire, RTLIL::IdString new_name)
1914 {
1915 log_assert(wires_[wire->name] == wire);
1916 log_assert(refcount_wires_ == 0);
1917 wires_.erase(wire->name);
1918 wire->name = new_name;
1919 add(wire);
1920 }
1921
1922 void RTLIL::Module::rename(RTLIL::Cell *cell, RTLIL::IdString new_name)
1923 {
1924 log_assert(cells_[cell->name] == cell);
1925 log_assert(refcount_wires_ == 0);
1926 cells_.erase(cell->name);
1927 cell->name = new_name;
1928 add(cell);
1929 }
1930
1931 void RTLIL::Module::rename(RTLIL::IdString old_name, RTLIL::IdString new_name)
1932 {
1933 log_assert(count_id(old_name) != 0);
1934 if (wires_.count(old_name))
1935 rename(wires_.at(old_name), new_name);
1936 else if (cells_.count(old_name))
1937 rename(cells_.at(old_name), new_name);
1938 else
1939 log_abort();
1940 }
1941
1942 void RTLIL::Module::swap_names(RTLIL::Wire *w1, RTLIL::Wire *w2)
1943 {
1944 log_assert(wires_[w1->name] == w1);
1945 log_assert(wires_[w2->name] == w2);
1946 log_assert(refcount_wires_ == 0);
1947
1948 wires_.erase(w1->name);
1949 wires_.erase(w2->name);
1950
1951 std::swap(w1->name, w2->name);
1952
1953 wires_[w1->name] = w1;
1954 wires_[w2->name] = w2;
1955 }
1956
1957 void RTLIL::Module::swap_names(RTLIL::Cell *c1, RTLIL::Cell *c2)
1958 {
1959 log_assert(cells_[c1->name] == c1);
1960 log_assert(cells_[c2->name] == c2);
1961 log_assert(refcount_cells_ == 0);
1962
1963 cells_.erase(c1->name);
1964 cells_.erase(c2->name);
1965
1966 std::swap(c1->name, c2->name);
1967
1968 cells_[c1->name] = c1;
1969 cells_[c2->name] = c2;
1970 }
1971
1972 RTLIL::IdString RTLIL::Module::uniquify(RTLIL::IdString name)
1973 {
1974 int index = 0;
1975 return uniquify(name, index);
1976 }
1977
1978 RTLIL::IdString RTLIL::Module::uniquify(RTLIL::IdString name, int &index)
1979 {
1980 if (index == 0) {
1981 if (count_id(name) == 0)
1982 return name;
1983 index++;
1984 }
1985
1986 while (1) {
1987 RTLIL::IdString new_name = stringf("%s_%d", name.c_str(), index);
1988 if (count_id(new_name) == 0)
1989 return new_name;
1990 index++;
1991 }
1992 }
1993
1994 static bool fixup_ports_compare(const RTLIL::Wire *a, const RTLIL::Wire *b)
1995 {
1996 if (a->port_id && !b->port_id)
1997 return true;
1998 if (!a->port_id && b->port_id)
1999 return false;
2000
2001 if (a->port_id == b->port_id)
2002 return a->name < b->name;
2003 return a->port_id < b->port_id;
2004 }
2005
2006 void RTLIL::Module::connect(const RTLIL::SigSig &conn)
2007 {
2008 for (auto mon : monitors)
2009 mon->notify_connect(this, conn);
2010
2011 if (design)
2012 for (auto mon : design->monitors)
2013 mon->notify_connect(this, conn);
2014
2015 // ignore all attempts to assign constants to other constants
2016 if (conn.first.has_const()) {
2017 RTLIL::SigSig new_conn;
2018 for (int i = 0; i < GetSize(conn.first); i++)
2019 if (conn.first[i].wire) {
2020 new_conn.first.append(conn.first[i]);
2021 new_conn.second.append(conn.second[i]);
2022 }
2023 if (GetSize(new_conn.first))
2024 connect(new_conn);
2025 return;
2026 }
2027
2028 if (yosys_xtrace) {
2029 log("#X# Connect (SigSig) in %s: %s = %s (%d bits)\n", log_id(this), log_signal(conn.first), log_signal(conn.second), GetSize(conn.first));
2030 log_backtrace("-X- ", yosys_xtrace-1);
2031 }
2032
2033 log_assert(GetSize(conn.first) == GetSize(conn.second));
2034 connections_.push_back(conn);
2035 }
2036
2037 void RTLIL::Module::connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs)
2038 {
2039 connect(RTLIL::SigSig(lhs, rhs));
2040 }
2041
2042 void RTLIL::Module::new_connections(const std::vector<RTLIL::SigSig> &new_conn)
2043 {
2044 for (auto mon : monitors)
2045 mon->notify_connect(this, new_conn);
2046
2047 if (design)
2048 for (auto mon : design->monitors)
2049 mon->notify_connect(this, new_conn);
2050
2051 if (yosys_xtrace) {
2052 log("#X# New connections vector in %s:\n", log_id(this));
2053 for (auto &conn: new_conn)
2054 log("#X# %s = %s (%d bits)\n", log_signal(conn.first), log_signal(conn.second), GetSize(conn.first));
2055 log_backtrace("-X- ", yosys_xtrace-1);
2056 }
2057
2058 connections_ = new_conn;
2059 }
2060
2061 const std::vector<RTLIL::SigSig> &RTLIL::Module::connections() const
2062 {
2063 return connections_;
2064 }
2065
2066 void RTLIL::Module::fixup_ports()
2067 {
2068 std::vector<RTLIL::Wire*> all_ports;
2069
2070 for (auto &w : wires_)
2071 if (w.second->port_input || w.second->port_output)
2072 all_ports.push_back(w.second);
2073 else
2074 w.second->port_id = 0;
2075
2076 std::sort(all_ports.begin(), all_ports.end(), fixup_ports_compare);
2077
2078 ports.clear();
2079 for (size_t i = 0; i < all_ports.size(); i++) {
2080 ports.push_back(all_ports[i]->name);
2081 all_ports[i]->port_id = i+1;
2082 }
2083 }
2084
2085 RTLIL::Wire *RTLIL::Module::addWire(RTLIL::IdString name, int width)
2086 {
2087 RTLIL::Wire *wire = new RTLIL::Wire;
2088 wire->name = name;
2089 wire->width = width;
2090 add(wire);
2091 return wire;
2092 }
2093
2094 RTLIL::Wire *RTLIL::Module::addWire(RTLIL::IdString name, const RTLIL::Wire *other)
2095 {
2096 RTLIL::Wire *wire = addWire(name);
2097 wire->width = other->width;
2098 wire->start_offset = other->start_offset;
2099 wire->port_id = other->port_id;
2100 wire->port_input = other->port_input;
2101 wire->port_output = other->port_output;
2102 wire->upto = other->upto;
2103 wire->is_signed = other->is_signed;
2104 wire->attributes = other->attributes;
2105 return wire;
2106 }
2107
2108 RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, RTLIL::IdString type)
2109 {
2110 RTLIL::Cell *cell = new RTLIL::Cell;
2111 cell->name = name;
2112 cell->type = type;
2113 add(cell);
2114 return cell;
2115 }
2116
2117 RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, const RTLIL::Cell *other)
2118 {
2119 RTLIL::Cell *cell = addCell(name, other->type);
2120 cell->connections_ = other->connections_;
2121 cell->parameters = other->parameters;
2122 cell->attributes = other->attributes;
2123 return cell;
2124 }
2125
2126 RTLIL::Memory *RTLIL::Module::addMemory(RTLIL::IdString name, const RTLIL::Memory *other)
2127 {
2128 RTLIL::Memory *mem = new RTLIL::Memory;
2129 mem->name = name;
2130 mem->width = other->width;
2131 mem->start_offset = other->start_offset;
2132 mem->size = other->size;
2133 mem->attributes = other->attributes;
2134 memories[mem->name] = mem;
2135 return mem;
2136 }
2137
2138 RTLIL::Process *RTLIL::Module::addProcess(RTLIL::IdString name)
2139 {
2140 RTLIL::Process *proc = new RTLIL::Process;
2141 proc->name = name;
2142 add(proc);
2143 return proc;
2144 }
2145
2146 RTLIL::Process *RTLIL::Module::addProcess(RTLIL::IdString name, const RTLIL::Process *other)
2147 {
2148 RTLIL::Process *proc = other->clone();
2149 proc->name = name;
2150 add(proc);
2151 return proc;
2152 }
2153
2154 #define DEF_METHOD(_func, _y_size, _type) \
2155 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed, const std::string &src) { \
2156 RTLIL::Cell *cell = addCell(name, _type); \
2157 cell->parameters[ID::A_SIGNED] = is_signed; \
2158 cell->parameters[ID::A_WIDTH] = sig_a.size(); \
2159 cell->parameters[ID::Y_WIDTH] = sig_y.size(); \
2160 cell->setPort(ID::A, sig_a); \
2161 cell->setPort(ID::Y, sig_y); \
2162 cell->set_src_attribute(src); \
2163 return cell; \
2164 } \
2165 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed, const std::string &src) { \
2166 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
2167 add ## _func(name, sig_a, sig_y, is_signed, src); \
2168 return sig_y; \
2169 }
2170 DEF_METHOD(Not, sig_a.size(), ID($not))
2171 DEF_METHOD(Pos, sig_a.size(), ID($pos))
2172 DEF_METHOD(Neg, sig_a.size(), ID($neg))
2173 DEF_METHOD(ReduceAnd, 1, ID($reduce_and))
2174 DEF_METHOD(ReduceOr, 1, ID($reduce_or))
2175 DEF_METHOD(ReduceXor, 1, ID($reduce_xor))
2176 DEF_METHOD(ReduceXnor, 1, ID($reduce_xnor))
2177 DEF_METHOD(ReduceBool, 1, ID($reduce_bool))
2178 DEF_METHOD(LogicNot, 1, ID($logic_not))
2179 #undef DEF_METHOD
2180
2181 #define DEF_METHOD(_func, _y_size, _type) \
2182 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed, const std::string &src) { \
2183 RTLIL::Cell *cell = addCell(name, _type); \
2184 cell->parameters[ID::A_SIGNED] = is_signed; \
2185 cell->parameters[ID::B_SIGNED] = is_signed; \
2186 cell->parameters[ID::A_WIDTH] = sig_a.size(); \
2187 cell->parameters[ID::B_WIDTH] = sig_b.size(); \
2188 cell->parameters[ID::Y_WIDTH] = sig_y.size(); \
2189 cell->setPort(ID::A, sig_a); \
2190 cell->setPort(ID::B, sig_b); \
2191 cell->setPort(ID::Y, sig_y); \
2192 cell->set_src_attribute(src); \
2193 return cell; \
2194 } \
2195 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed, const std::string &src) { \
2196 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
2197 add ## _func(name, sig_a, sig_b, sig_y, is_signed, src); \
2198 return sig_y; \
2199 }
2200 DEF_METHOD(And, max(sig_a.size(), sig_b.size()), ID($and))
2201 DEF_METHOD(Or, max(sig_a.size(), sig_b.size()), ID($or))
2202 DEF_METHOD(Xor, max(sig_a.size(), sig_b.size()), ID($xor))
2203 DEF_METHOD(Xnor, max(sig_a.size(), sig_b.size()), ID($xnor))
2204 DEF_METHOD(Shift, sig_a.size(), ID($shift))
2205 DEF_METHOD(Shiftx, sig_a.size(), ID($shiftx))
2206 DEF_METHOD(Lt, 1, ID($lt))
2207 DEF_METHOD(Le, 1, ID($le))
2208 DEF_METHOD(Eq, 1, ID($eq))
2209 DEF_METHOD(Ne, 1, ID($ne))
2210 DEF_METHOD(Eqx, 1, ID($eqx))
2211 DEF_METHOD(Nex, 1, ID($nex))
2212 DEF_METHOD(Ge, 1, ID($ge))
2213 DEF_METHOD(Gt, 1, ID($gt))
2214 DEF_METHOD(Add, max(sig_a.size(), sig_b.size()), ID($add))
2215 DEF_METHOD(Sub, max(sig_a.size(), sig_b.size()), ID($sub))
2216 DEF_METHOD(Mul, max(sig_a.size(), sig_b.size()), ID($mul))
2217 DEF_METHOD(Div, max(sig_a.size(), sig_b.size()), ID($div))
2218 DEF_METHOD(Mod, max(sig_a.size(), sig_b.size()), ID($mod))
2219 DEF_METHOD(DivFloor, max(sig_a.size(), sig_b.size()), ID($divfloor))
2220 DEF_METHOD(ModFloor, max(sig_a.size(), sig_b.size()), ID($modfloor))
2221 DEF_METHOD(LogicAnd, 1, ID($logic_and))
2222 DEF_METHOD(LogicOr, 1, ID($logic_or))
2223 #undef DEF_METHOD
2224
2225 #define DEF_METHOD(_func, _y_size, _type) \
2226 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed, const std::string &src) { \
2227 RTLIL::Cell *cell = addCell(name, _type); \
2228 cell->parameters[ID::A_SIGNED] = is_signed; \
2229 cell->parameters[ID::B_SIGNED] = false; \
2230 cell->parameters[ID::A_WIDTH] = sig_a.size(); \
2231 cell->parameters[ID::B_WIDTH] = sig_b.size(); \
2232 cell->parameters[ID::Y_WIDTH] = sig_y.size(); \
2233 cell->setPort(ID::A, sig_a); \
2234 cell->setPort(ID::B, sig_b); \
2235 cell->setPort(ID::Y, sig_y); \
2236 cell->set_src_attribute(src); \
2237 return cell; \
2238 } \
2239 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed, const std::string &src) { \
2240 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
2241 add ## _func(name, sig_a, sig_b, sig_y, is_signed, src); \
2242 return sig_y; \
2243 }
2244 DEF_METHOD(Shl, sig_a.size(), ID($shl))
2245 DEF_METHOD(Shr, sig_a.size(), ID($shr))
2246 DEF_METHOD(Sshl, sig_a.size(), ID($sshl))
2247 DEF_METHOD(Sshr, sig_a.size(), ID($sshr))
2248 #undef DEF_METHOD
2249
2250 #define DEF_METHOD(_func, _type, _pmux) \
2251 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, const std::string &src) { \
2252 RTLIL::Cell *cell = addCell(name, _type); \
2253 cell->parameters[ID::WIDTH] = sig_a.size(); \
2254 if (_pmux) cell->parameters[ID::S_WIDTH] = sig_s.size(); \
2255 cell->setPort(ID::A, sig_a); \
2256 cell->setPort(ID::B, sig_b); \
2257 cell->setPort(ID::S, sig_s); \
2258 cell->setPort(ID::Y, sig_y); \
2259 cell->set_src_attribute(src); \
2260 return cell; \
2261 } \
2262 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const std::string &src) { \
2263 RTLIL::SigSpec sig_y = addWire(NEW_ID, sig_a.size()); \
2264 add ## _func(name, sig_a, sig_b, sig_s, sig_y, src); \
2265 return sig_y; \
2266 }
2267 DEF_METHOD(Mux, ID($mux), 0)
2268 DEF_METHOD(Pmux, ID($pmux), 1)
2269 #undef DEF_METHOD
2270
2271 #define DEF_METHOD_2(_func, _type, _P1, _P2) \
2272 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const std::string &src) { \
2273 RTLIL::Cell *cell = addCell(name, _type); \
2274 cell->setPort("\\" #_P1, sig1); \
2275 cell->setPort("\\" #_P2, sig2); \
2276 cell->set_src_attribute(src); \
2277 return cell; \
2278 } \
2279 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const std::string &src) { \
2280 RTLIL::SigBit sig2 = addWire(NEW_ID); \
2281 add ## _func(name, sig1, sig2, src); \
2282 return sig2; \
2283 }
2284 #define DEF_METHOD_3(_func, _type, _P1, _P2, _P3) \
2285 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const RTLIL::SigBit &sig3, const std::string &src) { \
2286 RTLIL::Cell *cell = addCell(name, _type); \
2287 cell->setPort("\\" #_P1, sig1); \
2288 cell->setPort("\\" #_P2, sig2); \
2289 cell->setPort("\\" #_P3, sig3); \
2290 cell->set_src_attribute(src); \
2291 return cell; \
2292 } \
2293 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const std::string &src) { \
2294 RTLIL::SigBit sig3 = addWire(NEW_ID); \
2295 add ## _func(name, sig1, sig2, sig3, src); \
2296 return sig3; \
2297 }
2298 #define DEF_METHOD_4(_func, _type, _P1, _P2, _P3, _P4) \
2299 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const RTLIL::SigBit &sig3, const RTLIL::SigBit &sig4, const std::string &src) { \
2300 RTLIL::Cell *cell = addCell(name, _type); \
2301 cell->setPort("\\" #_P1, sig1); \
2302 cell->setPort("\\" #_P2, sig2); \
2303 cell->setPort("\\" #_P3, sig3); \
2304 cell->setPort("\\" #_P4, sig4); \
2305 cell->set_src_attribute(src); \
2306 return cell; \
2307 } \
2308 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const RTLIL::SigBit &sig3, const std::string &src) { \
2309 RTLIL::SigBit sig4 = addWire(NEW_ID); \
2310 add ## _func(name, sig1, sig2, sig3, sig4, src); \
2311 return sig4; \
2312 }
2313 #define DEF_METHOD_5(_func, _type, _P1, _P2, _P3, _P4, _P5) \
2314 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const RTLIL::SigBit &sig3, const RTLIL::SigBit &sig4, const RTLIL::SigBit &sig5, const std::string &src) { \
2315 RTLIL::Cell *cell = addCell(name, _type); \
2316 cell->setPort("\\" #_P1, sig1); \
2317 cell->setPort("\\" #_P2, sig2); \
2318 cell->setPort("\\" #_P3, sig3); \
2319 cell->setPort("\\" #_P4, sig4); \
2320 cell->setPort("\\" #_P5, sig5); \
2321 cell->set_src_attribute(src); \
2322 return cell; \
2323 } \
2324 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const RTLIL::SigBit &sig3, const RTLIL::SigBit &sig4, const std::string &src) { \
2325 RTLIL::SigBit sig5 = addWire(NEW_ID); \
2326 add ## _func(name, sig1, sig2, sig3, sig4, sig5, src); \
2327 return sig5; \
2328 }
2329 DEF_METHOD_2(BufGate, ID($_BUF_), A, Y)
2330 DEF_METHOD_2(NotGate, ID($_NOT_), A, Y)
2331 DEF_METHOD_3(AndGate, ID($_AND_), A, B, Y)
2332 DEF_METHOD_3(NandGate, ID($_NAND_), A, B, Y)
2333 DEF_METHOD_3(OrGate, ID($_OR_), A, B, Y)
2334 DEF_METHOD_3(NorGate, ID($_NOR_), A, B, Y)
2335 DEF_METHOD_3(XorGate, ID($_XOR_), A, B, Y)
2336 DEF_METHOD_3(XnorGate, ID($_XNOR_), A, B, Y)
2337 DEF_METHOD_3(AndnotGate, ID($_ANDNOT_), A, B, Y)
2338 DEF_METHOD_3(OrnotGate, ID($_ORNOT_), A, B, Y)
2339 DEF_METHOD_4(MuxGate, ID($_MUX_), A, B, S, Y)
2340 DEF_METHOD_4(NmuxGate, ID($_NMUX_), A, B, S, Y)
2341 DEF_METHOD_4(Aoi3Gate, ID($_AOI3_), A, B, C, Y)
2342 DEF_METHOD_4(Oai3Gate, ID($_OAI3_), A, B, C, Y)
2343 DEF_METHOD_5(Aoi4Gate, ID($_AOI4_), A, B, C, D, Y)
2344 DEF_METHOD_5(Oai4Gate, ID($_OAI4_), A, B, C, D, Y)
2345 #undef DEF_METHOD_2
2346 #undef DEF_METHOD_3
2347 #undef DEF_METHOD_4
2348 #undef DEF_METHOD_5
2349
2350 RTLIL::Cell* RTLIL::Module::addPow(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool a_signed, bool b_signed, const std::string &src)
2351 {
2352 RTLIL::Cell *cell = addCell(name, ID($pow));
2353 cell->parameters[ID::A_SIGNED] = a_signed;
2354 cell->parameters[ID::B_SIGNED] = b_signed;
2355 cell->parameters[ID::A_WIDTH] = sig_a.size();
2356 cell->parameters[ID::B_WIDTH] = sig_b.size();
2357 cell->parameters[ID::Y_WIDTH] = sig_y.size();
2358 cell->setPort(ID::A, sig_a);
2359 cell->setPort(ID::B, sig_b);
2360 cell->setPort(ID::Y, sig_y);
2361 cell->set_src_attribute(src);
2362 return cell;
2363 }
2364
2365 RTLIL::Cell* RTLIL::Module::addSlice(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, RTLIL::Const offset, const std::string &src)
2366 {
2367 RTLIL::Cell *cell = addCell(name, ID($slice));
2368 cell->parameters[ID::A_WIDTH] = sig_a.size();
2369 cell->parameters[ID::Y_WIDTH] = sig_y.size();
2370 cell->parameters[ID::OFFSET] = offset;
2371 cell->setPort(ID::A, sig_a);
2372 cell->setPort(ID::Y, sig_y);
2373 cell->set_src_attribute(src);
2374 return cell;
2375 }
2376
2377 RTLIL::Cell* RTLIL::Module::addConcat(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, const std::string &src)
2378 {
2379 RTLIL::Cell *cell = addCell(name, ID($concat));
2380 cell->parameters[ID::A_WIDTH] = sig_a.size();
2381 cell->parameters[ID::B_WIDTH] = sig_b.size();
2382 cell->setPort(ID::A, sig_a);
2383 cell->setPort(ID::B, sig_b);
2384 cell->setPort(ID::Y, sig_y);
2385 cell->set_src_attribute(src);
2386 return cell;
2387 }
2388
2389 RTLIL::Cell* RTLIL::Module::addLut(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, RTLIL::Const lut, const std::string &src)
2390 {
2391 RTLIL::Cell *cell = addCell(name, ID($lut));
2392 cell->parameters[ID::LUT] = lut;
2393 cell->parameters[ID::WIDTH] = sig_a.size();
2394 cell->setPort(ID::A, sig_a);
2395 cell->setPort(ID::Y, sig_y);
2396 cell->set_src_attribute(src);
2397 return cell;
2398 }
2399
2400 RTLIL::Cell* RTLIL::Module::addTribuf(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_y, const std::string &src)
2401 {
2402 RTLIL::Cell *cell = addCell(name, ID($tribuf));
2403 cell->parameters[ID::WIDTH] = sig_a.size();
2404 cell->setPort(ID::A, sig_a);
2405 cell->setPort(ID::EN, sig_en);
2406 cell->setPort(ID::Y, sig_y);
2407 cell->set_src_attribute(src);
2408 return cell;
2409 }
2410
2411 RTLIL::Cell* RTLIL::Module::addAssert(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src)
2412 {
2413 RTLIL::Cell *cell = addCell(name, ID($assert));
2414 cell->setPort(ID::A, sig_a);
2415 cell->setPort(ID::EN, sig_en);
2416 cell->set_src_attribute(src);
2417 return cell;
2418 }
2419
2420 RTLIL::Cell* RTLIL::Module::addAssume(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src)
2421 {
2422 RTLIL::Cell *cell = addCell(name, ID($assume));
2423 cell->setPort(ID::A, sig_a);
2424 cell->setPort(ID::EN, sig_en);
2425 cell->set_src_attribute(src);
2426 return cell;
2427 }
2428
2429 RTLIL::Cell* RTLIL::Module::addLive(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src)
2430 {
2431 RTLIL::Cell *cell = addCell(name, ID($live));
2432 cell->setPort(ID::A, sig_a);
2433 cell->setPort(ID::EN, sig_en);
2434 cell->set_src_attribute(src);
2435 return cell;
2436 }
2437
2438 RTLIL::Cell* RTLIL::Module::addFair(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src)
2439 {
2440 RTLIL::Cell *cell = addCell(name, ID($fair));
2441 cell->setPort(ID::A, sig_a);
2442 cell->setPort(ID::EN, sig_en);
2443 cell->set_src_attribute(src);
2444 return cell;
2445 }
2446
2447 RTLIL::Cell* RTLIL::Module::addCover(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src)
2448 {
2449 RTLIL::Cell *cell = addCell(name, ID($cover));
2450 cell->setPort(ID::A, sig_a);
2451 cell->setPort(ID::EN, sig_en);
2452 cell->set_src_attribute(src);
2453 return cell;
2454 }
2455
2456 RTLIL::Cell* RTLIL::Module::addEquiv(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, const std::string &src)
2457 {
2458 RTLIL::Cell *cell = addCell(name, ID($equiv));
2459 cell->setPort(ID::A, sig_a);
2460 cell->setPort(ID::B, sig_b);
2461 cell->setPort(ID::Y, sig_y);
2462 cell->set_src_attribute(src);
2463 return cell;
2464 }
2465
2466 RTLIL::Cell* RTLIL::Module::addSr(RTLIL::IdString name, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, const RTLIL::SigSpec &sig_q, bool set_polarity, bool clr_polarity, const std::string &src)
2467 {
2468 RTLIL::Cell *cell = addCell(name, ID($sr));
2469 cell->parameters[ID::SET_POLARITY] = set_polarity;
2470 cell->parameters[ID::CLR_POLARITY] = clr_polarity;
2471 cell->parameters[ID::WIDTH] = sig_q.size();
2472 cell->setPort(ID::SET, sig_set);
2473 cell->setPort(ID::CLR, sig_clr);
2474 cell->setPort(ID::Q, sig_q);
2475 cell->set_src_attribute(src);
2476 return cell;
2477 }
2478
2479 RTLIL::Cell* RTLIL::Module::addFf(RTLIL::IdString name, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const std::string &src)
2480 {
2481 RTLIL::Cell *cell = addCell(name, ID($ff));
2482 cell->parameters[ID::WIDTH] = sig_q.size();
2483 cell->setPort(ID::D, sig_d);
2484 cell->setPort(ID::Q, sig_q);
2485 cell->set_src_attribute(src);
2486 return cell;
2487 }
2488
2489 RTLIL::Cell* RTLIL::Module::addDff(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, const std::string &src)
2490 {
2491 RTLIL::Cell *cell = addCell(name, ID($dff));
2492 cell->parameters[ID::CLK_POLARITY] = clk_polarity;
2493 cell->parameters[ID::WIDTH] = sig_q.size();
2494 cell->setPort(ID::CLK, sig_clk);
2495 cell->setPort(ID::D, sig_d);
2496 cell->setPort(ID::Q, sig_q);
2497 cell->set_src_attribute(src);
2498 return cell;
2499 }
2500
2501 RTLIL::Cell* RTLIL::Module::addDffe(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, bool en_polarity, const std::string &src)
2502 {
2503 RTLIL::Cell *cell = addCell(name, ID($dffe));
2504 cell->parameters[ID::CLK_POLARITY] = clk_polarity;
2505 cell->parameters[ID::EN_POLARITY] = en_polarity;
2506 cell->parameters[ID::WIDTH] = sig_q.size();
2507 cell->setPort(ID::CLK, sig_clk);
2508 cell->setPort(ID::EN, sig_en);
2509 cell->setPort(ID::D, sig_d);
2510 cell->setPort(ID::Q, sig_q);
2511 cell->set_src_attribute(src);
2512 return cell;
2513 }
2514
2515 RTLIL::Cell* RTLIL::Module::addDffsr(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,
2516 RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
2517 {
2518 RTLIL::Cell *cell = addCell(name, ID($dffsr));
2519 cell->parameters[ID::CLK_POLARITY] = clk_polarity;
2520 cell->parameters[ID::SET_POLARITY] = set_polarity;
2521 cell->parameters[ID::CLR_POLARITY] = clr_polarity;
2522 cell->parameters[ID::WIDTH] = sig_q.size();
2523 cell->setPort(ID::CLK, sig_clk);
2524 cell->setPort(ID::SET, sig_set);
2525 cell->setPort(ID::CLR, sig_clr);
2526 cell->setPort(ID::D, sig_d);
2527 cell->setPort(ID::Q, sig_q);
2528 cell->set_src_attribute(src);
2529 return cell;
2530 }
2531
2532 RTLIL::Cell* RTLIL::Module::addDffsre(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,
2533 RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, bool en_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
2534 {
2535 RTLIL::Cell *cell = addCell(name, ID($dffsre));
2536 cell->parameters[ID::CLK_POLARITY] = clk_polarity;
2537 cell->parameters[ID::EN_POLARITY] = en_polarity;
2538 cell->parameters[ID::SET_POLARITY] = set_polarity;
2539 cell->parameters[ID::CLR_POLARITY] = clr_polarity;
2540 cell->parameters[ID::WIDTH] = sig_q.size();
2541 cell->setPort(ID::CLK, sig_clk);
2542 cell->setPort(ID::EN, sig_en);
2543 cell->setPort(ID::SET, sig_set);
2544 cell->setPort(ID::CLR, sig_clr);
2545 cell->setPort(ID::D, sig_d);
2546 cell->setPort(ID::Q, sig_q);
2547 cell->set_src_attribute(src);
2548 return cell;
2549 }
2550
2551 RTLIL::Cell* RTLIL::Module::addAdff(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
2552 RTLIL::Const arst_value, bool clk_polarity, bool arst_polarity, const std::string &src)
2553 {
2554 RTLIL::Cell *cell = addCell(name, ID($adff));
2555 cell->parameters[ID::CLK_POLARITY] = clk_polarity;
2556 cell->parameters[ID::ARST_POLARITY] = arst_polarity;
2557 cell->parameters[ID::ARST_VALUE] = arst_value;
2558 cell->parameters[ID::WIDTH] = sig_q.size();
2559 cell->setPort(ID::CLK, sig_clk);
2560 cell->setPort(ID::ARST, sig_arst);
2561 cell->setPort(ID::D, sig_d);
2562 cell->setPort(ID::Q, sig_q);
2563 cell->set_src_attribute(src);
2564 return cell;
2565 }
2566
2567 RTLIL::Cell* RTLIL::Module::addAdffe(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
2568 RTLIL::Const arst_value, bool clk_polarity, bool en_polarity, bool arst_polarity, const std::string &src)
2569 {
2570 RTLIL::Cell *cell = addCell(name, ID($adffe));
2571 cell->parameters[ID::CLK_POLARITY] = clk_polarity;
2572 cell->parameters[ID::EN_POLARITY] = en_polarity;
2573 cell->parameters[ID::ARST_POLARITY] = arst_polarity;
2574 cell->parameters[ID::ARST_VALUE] = arst_value;
2575 cell->parameters[ID::WIDTH] = sig_q.size();
2576 cell->setPort(ID::CLK, sig_clk);
2577 cell->setPort(ID::EN, sig_en);
2578 cell->setPort(ID::ARST, sig_arst);
2579 cell->setPort(ID::D, sig_d);
2580 cell->setPort(ID::Q, sig_q);
2581 cell->set_src_attribute(src);
2582 return cell;
2583 }
2584
2585 RTLIL::Cell* RTLIL::Module::addSdff(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
2586 RTLIL::Const srst_value, bool clk_polarity, bool srst_polarity, const std::string &src)
2587 {
2588 RTLIL::Cell *cell = addCell(name, ID($sdff));
2589 cell->parameters[ID::CLK_POLARITY] = clk_polarity;
2590 cell->parameters[ID::SRST_POLARITY] = srst_polarity;
2591 cell->parameters[ID::SRST_VALUE] = srst_value;
2592 cell->parameters[ID::WIDTH] = sig_q.size();
2593 cell->setPort(ID::CLK, sig_clk);
2594 cell->setPort(ID::SRST, sig_srst);
2595 cell->setPort(ID::D, sig_d);
2596 cell->setPort(ID::Q, sig_q);
2597 cell->set_src_attribute(src);
2598 return cell;
2599 }
2600
2601 RTLIL::Cell* RTLIL::Module::addSdffe(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
2602 RTLIL::Const srst_value, bool clk_polarity, bool en_polarity, bool srst_polarity, const std::string &src)
2603 {
2604 RTLIL::Cell *cell = addCell(name, ID($sdffe));
2605 cell->parameters[ID::CLK_POLARITY] = clk_polarity;
2606 cell->parameters[ID::EN_POLARITY] = en_polarity;
2607 cell->parameters[ID::SRST_POLARITY] = srst_polarity;
2608 cell->parameters[ID::SRST_VALUE] = srst_value;
2609 cell->parameters[ID::WIDTH] = sig_q.size();
2610 cell->setPort(ID::CLK, sig_clk);
2611 cell->setPort(ID::EN, sig_en);
2612 cell->setPort(ID::SRST, sig_srst);
2613 cell->setPort(ID::D, sig_d);
2614 cell->setPort(ID::Q, sig_q);
2615 cell->set_src_attribute(src);
2616 return cell;
2617 }
2618
2619 RTLIL::Cell* RTLIL::Module::addSdffce(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
2620 RTLIL::Const srst_value, bool clk_polarity, bool en_polarity, bool srst_polarity, const std::string &src)
2621 {
2622 RTLIL::Cell *cell = addCell(name, ID($sdffce));
2623 cell->parameters[ID::CLK_POLARITY] = clk_polarity;
2624 cell->parameters[ID::EN_POLARITY] = en_polarity;
2625 cell->parameters[ID::SRST_POLARITY] = srst_polarity;
2626 cell->parameters[ID::SRST_VALUE] = srst_value;
2627 cell->parameters[ID::WIDTH] = sig_q.size();
2628 cell->setPort(ID::CLK, sig_clk);
2629 cell->setPort(ID::EN, sig_en);
2630 cell->setPort(ID::SRST, sig_srst);
2631 cell->setPort(ID::D, sig_d);
2632 cell->setPort(ID::Q, sig_q);
2633 cell->set_src_attribute(src);
2634 return cell;
2635 }
2636
2637 RTLIL::Cell* RTLIL::Module::addDlatch(RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity, const std::string &src)
2638 {
2639 RTLIL::Cell *cell = addCell(name, ID($dlatch));
2640 cell->parameters[ID::EN_POLARITY] = en_polarity;
2641 cell->parameters[ID::WIDTH] = sig_q.size();
2642 cell->setPort(ID::EN, sig_en);
2643 cell->setPort(ID::D, sig_d);
2644 cell->setPort(ID::Q, sig_q);
2645 cell->set_src_attribute(src);
2646 return cell;
2647 }
2648
2649 RTLIL::Cell* RTLIL::Module::addAdlatch(RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
2650 RTLIL::Const arst_value, bool en_polarity, bool arst_polarity, const std::string &src)
2651 {
2652 RTLIL::Cell *cell = addCell(name, ID($adlatch));
2653 cell->parameters[ID::EN_POLARITY] = en_polarity;
2654 cell->parameters[ID::ARST_POLARITY] = arst_polarity;
2655 cell->parameters[ID::ARST_VALUE] = arst_value;
2656 cell->parameters[ID::WIDTH] = sig_q.size();
2657 cell->setPort(ID::EN, sig_en);
2658 cell->setPort(ID::ARST, sig_arst);
2659 cell->setPort(ID::D, sig_d);
2660 cell->setPort(ID::Q, sig_q);
2661 cell->set_src_attribute(src);
2662 return cell;
2663 }
2664
2665 RTLIL::Cell* RTLIL::Module::addDlatchsr(RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,
2666 RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
2667 {
2668 RTLIL::Cell *cell = addCell(name, ID($dlatchsr));
2669 cell->parameters[ID::EN_POLARITY] = en_polarity;
2670 cell->parameters[ID::SET_POLARITY] = set_polarity;
2671 cell->parameters[ID::CLR_POLARITY] = clr_polarity;
2672 cell->parameters[ID::WIDTH] = sig_q.size();
2673 cell->setPort(ID::EN, sig_en);
2674 cell->setPort(ID::SET, sig_set);
2675 cell->setPort(ID::CLR, sig_clr);
2676 cell->setPort(ID::D, sig_d);
2677 cell->setPort(ID::Q, sig_q);
2678 cell->set_src_attribute(src);
2679 return cell;
2680 }
2681
2682 RTLIL::Cell* RTLIL::Module::addSrGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,
2683 const RTLIL::SigSpec &sig_q, bool set_polarity, bool clr_polarity, const std::string &src)
2684 {
2685 RTLIL::Cell *cell = addCell(name, stringf("$_SR_%c%c_", set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N'));
2686 cell->setPort(ID::S, sig_set);
2687 cell->setPort(ID::R, sig_clr);
2688 cell->setPort(ID::Q, sig_q);
2689 cell->set_src_attribute(src);
2690 return cell;
2691 }
2692
2693 RTLIL::Cell* RTLIL::Module::addFfGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const std::string &src)
2694 {
2695 RTLIL::Cell *cell = addCell(name, ID($_FF_));
2696 cell->setPort(ID::D, sig_d);
2697 cell->setPort(ID::Q, sig_q);
2698 cell->set_src_attribute(src);
2699 return cell;
2700 }
2701
2702 RTLIL::Cell* RTLIL::Module::addDffGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, const std::string &src)
2703 {
2704 RTLIL::Cell *cell = addCell(name, stringf("$_DFF_%c_", clk_polarity ? 'P' : 'N'));
2705 cell->setPort(ID::C, sig_clk);
2706 cell->setPort(ID::D, sig_d);
2707 cell->setPort(ID::Q, sig_q);
2708 cell->set_src_attribute(src);
2709 return cell;
2710 }
2711
2712 RTLIL::Cell* RTLIL::Module::addDffeGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, bool en_polarity, const std::string &src)
2713 {
2714 RTLIL::Cell *cell = addCell(name, stringf("$_DFFE_%c%c_", clk_polarity ? 'P' : 'N', en_polarity ? 'P' : 'N'));
2715 cell->setPort(ID::C, sig_clk);
2716 cell->setPort(ID::E, sig_en);
2717 cell->setPort(ID::D, sig_d);
2718 cell->setPort(ID::Q, sig_q);
2719 cell->set_src_attribute(src);
2720 return cell;
2721 }
2722
2723 RTLIL::Cell* RTLIL::Module::addDffsrGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,
2724 RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
2725 {
2726 RTLIL::Cell *cell = addCell(name, stringf("$_DFFSR_%c%c%c_", clk_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N'));
2727 cell->setPort(ID::C, sig_clk);
2728 cell->setPort(ID::S, sig_set);
2729 cell->setPort(ID::R, sig_clr);
2730 cell->setPort(ID::D, sig_d);
2731 cell->setPort(ID::Q, sig_q);
2732 cell->set_src_attribute(src);
2733 return cell;
2734 }
2735
2736 RTLIL::Cell* RTLIL::Module::addDffsreGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,
2737 RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, bool en_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
2738 {
2739 RTLIL::Cell *cell = addCell(name, stringf("$_DFFSRE_%c%c%c%c_", clk_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N', en_polarity ? 'P' : 'N'));
2740 cell->setPort(ID::C, sig_clk);
2741 cell->setPort(ID::S, sig_set);
2742 cell->setPort(ID::R, sig_clr);
2743 cell->setPort(ID::E, sig_en);
2744 cell->setPort(ID::D, sig_d);
2745 cell->setPort(ID::Q, sig_q);
2746 cell->set_src_attribute(src);
2747 return cell;
2748 }
2749
2750 RTLIL::Cell* RTLIL::Module::addAdffGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
2751 bool arst_value, bool clk_polarity, bool arst_polarity, const std::string &src)
2752 {
2753 RTLIL::Cell *cell = addCell(name, stringf("$_DFF_%c%c%c_", clk_polarity ? 'P' : 'N', arst_polarity ? 'P' : 'N', arst_value ? '1' : '0'));
2754 cell->setPort(ID::C, sig_clk);
2755 cell->setPort(ID::R, sig_arst);
2756 cell->setPort(ID::D, sig_d);
2757 cell->setPort(ID::Q, sig_q);
2758 cell->set_src_attribute(src);
2759 return cell;
2760 }
2761
2762 RTLIL::Cell* RTLIL::Module::addAdffeGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
2763 bool arst_value, bool clk_polarity, bool en_polarity, bool arst_polarity, const std::string &src)
2764 {
2765 RTLIL::Cell *cell = addCell(name, stringf("$_DFFE_%c%c%c%c_", clk_polarity ? 'P' : 'N', arst_polarity ? 'P' : 'N', arst_value ? '1' : '0', en_polarity ? 'P' : 'N'));
2766 cell->setPort(ID::C, sig_clk);
2767 cell->setPort(ID::R, sig_arst);
2768 cell->setPort(ID::E, sig_en);
2769 cell->setPort(ID::D, sig_d);
2770 cell->setPort(ID::Q, sig_q);
2771 cell->set_src_attribute(src);
2772 return cell;
2773 }
2774
2775 RTLIL::Cell* RTLIL::Module::addSdffGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
2776 bool srst_value, bool clk_polarity, bool srst_polarity, const std::string &src)
2777 {
2778 RTLIL::Cell *cell = addCell(name, stringf("$_SDFF_%c%c%c_", clk_polarity ? 'P' : 'N', srst_polarity ? 'P' : 'N', srst_value ? '1' : '0'));
2779 cell->setPort(ID::C, sig_clk);
2780 cell->setPort(ID::R, sig_srst);
2781 cell->setPort(ID::D, sig_d);
2782 cell->setPort(ID::Q, sig_q);
2783 cell->set_src_attribute(src);
2784 return cell;
2785 }
2786
2787 RTLIL::Cell* RTLIL::Module::addSdffeGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
2788 bool srst_value, bool clk_polarity, bool en_polarity, bool srst_polarity, const std::string &src)
2789 {
2790 RTLIL::Cell *cell = addCell(name, stringf("$_SDFFE_%c%c%c%c_", clk_polarity ? 'P' : 'N', srst_polarity ? 'P' : 'N', srst_value ? '1' : '0', en_polarity ? 'P' : 'N'));
2791 cell->setPort(ID::C, sig_clk);
2792 cell->setPort(ID::R, sig_srst);
2793 cell->setPort(ID::E, sig_en);
2794 cell->setPort(ID::D, sig_d);
2795 cell->setPort(ID::Q, sig_q);
2796 cell->set_src_attribute(src);
2797 return cell;
2798 }
2799
2800 RTLIL::Cell* RTLIL::Module::addSdffceGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
2801 bool srst_value, bool clk_polarity, bool en_polarity, bool srst_polarity, const std::string &src)
2802 {
2803 RTLIL::Cell *cell = addCell(name, stringf("$_SDFFCE_%c%c%c%c_", clk_polarity ? 'P' : 'N', srst_polarity ? 'P' : 'N', srst_value ? '1' : '0', en_polarity ? 'P' : 'N'));
2804 cell->setPort(ID::C, sig_clk);
2805 cell->setPort(ID::R, sig_srst);
2806 cell->setPort(ID::E, sig_en);
2807 cell->setPort(ID::D, sig_d);
2808 cell->setPort(ID::Q, sig_q);
2809 cell->set_src_attribute(src);
2810 return cell;
2811 }
2812
2813 RTLIL::Cell* RTLIL::Module::addDlatchGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity, const std::string &src)
2814 {
2815 RTLIL::Cell *cell = addCell(name, stringf("$_DLATCH_%c_", en_polarity ? 'P' : 'N'));
2816 cell->setPort(ID::E, sig_en);
2817 cell->setPort(ID::D, sig_d);
2818 cell->setPort(ID::Q, sig_q);
2819 cell->set_src_attribute(src);
2820 return cell;
2821 }
2822
2823 RTLIL::Cell* RTLIL::Module::addAdlatchGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
2824 bool arst_value, bool en_polarity, bool arst_polarity, const std::string &src)
2825 {
2826 RTLIL::Cell *cell = addCell(name, stringf("$_DLATCH_%c%c%c_", en_polarity ? 'P' : 'N', arst_polarity ? 'P' : 'N', arst_value ? '1' : '0'));
2827 cell->setPort(ID::E, sig_en);
2828 cell->setPort(ID::R, sig_arst);
2829 cell->setPort(ID::D, sig_d);
2830 cell->setPort(ID::Q, sig_q);
2831 cell->set_src_attribute(src);
2832 return cell;
2833 }
2834
2835 RTLIL::Cell* RTLIL::Module::addDlatchsrGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,
2836 RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
2837 {
2838 RTLIL::Cell *cell = addCell(name, stringf("$_DLATCHSR_%c%c%c_", en_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N'));
2839 cell->setPort(ID::E, sig_en);
2840 cell->setPort(ID::S, sig_set);
2841 cell->setPort(ID::R, sig_clr);
2842 cell->setPort(ID::D, sig_d);
2843 cell->setPort(ID::Q, sig_q);
2844 cell->set_src_attribute(src);
2845 return cell;
2846 }
2847
2848 RTLIL::SigSpec RTLIL::Module::Anyconst(RTLIL::IdString name, int width, const std::string &src)
2849 {
2850 RTLIL::SigSpec sig = addWire(NEW_ID, width);
2851 Cell *cell = addCell(name, ID($anyconst));
2852 cell->setParam(ID::WIDTH, width);
2853 cell->setPort(ID::Y, sig);
2854 cell->set_src_attribute(src);
2855 return sig;
2856 }
2857
2858 RTLIL::SigSpec RTLIL::Module::Anyseq(RTLIL::IdString name, int width, const std::string &src)
2859 {
2860 RTLIL::SigSpec sig = addWire(NEW_ID, width);
2861 Cell *cell = addCell(name, ID($anyseq));
2862 cell->setParam(ID::WIDTH, width);
2863 cell->setPort(ID::Y, sig);
2864 cell->set_src_attribute(src);
2865 return sig;
2866 }
2867
2868 RTLIL::SigSpec RTLIL::Module::Allconst(RTLIL::IdString name, int width, const std::string &src)
2869 {
2870 RTLIL::SigSpec sig = addWire(NEW_ID, width);
2871 Cell *cell = addCell(name, ID($allconst));
2872 cell->setParam(ID::WIDTH, width);
2873 cell->setPort(ID::Y, sig);
2874 cell->set_src_attribute(src);
2875 return sig;
2876 }
2877
2878 RTLIL::SigSpec RTLIL::Module::Allseq(RTLIL::IdString name, int width, const std::string &src)
2879 {
2880 RTLIL::SigSpec sig = addWire(NEW_ID, width);
2881 Cell *cell = addCell(name, ID($allseq));
2882 cell->setParam(ID::WIDTH, width);
2883 cell->setPort(ID::Y, sig);
2884 cell->set_src_attribute(src);
2885 return sig;
2886 }
2887
2888 RTLIL::SigSpec RTLIL::Module::Initstate(RTLIL::IdString name, const std::string &src)
2889 {
2890 RTLIL::SigSpec sig = addWire(NEW_ID);
2891 Cell *cell = addCell(name, ID($initstate));
2892 cell->setPort(ID::Y, sig);
2893 cell->set_src_attribute(src);
2894 return sig;
2895 }
2896
2897 RTLIL::Wire::Wire()
2898 {
2899 static unsigned int hashidx_count = 123456789;
2900 hashidx_count = mkhash_xorshift(hashidx_count);
2901 hashidx_ = hashidx_count;
2902
2903 module = nullptr;
2904 width = 1;
2905 start_offset = 0;
2906 port_id = 0;
2907 port_input = false;
2908 port_output = false;
2909 upto = false;
2910 is_signed = false;
2911
2912 #ifdef WITH_PYTHON
2913 RTLIL::Wire::get_all_wires()->insert(std::pair<unsigned int, RTLIL::Wire*>(hashidx_, this));
2914 #endif
2915 }
2916
2917 RTLIL::Wire::~Wire()
2918 {
2919 #ifdef WITH_PYTHON
2920 RTLIL::Wire::get_all_wires()->erase(hashidx_);
2921 #endif
2922 }
2923
2924 #ifdef WITH_PYTHON
2925 static std::map<unsigned int, RTLIL::Wire*> all_wires;
2926 std::map<unsigned int, RTLIL::Wire*> *RTLIL::Wire::get_all_wires(void)
2927 {
2928 return &all_wires;
2929 }
2930 #endif
2931
2932 RTLIL::Memory::Memory()
2933 {
2934 static unsigned int hashidx_count = 123456789;
2935 hashidx_count = mkhash_xorshift(hashidx_count);
2936 hashidx_ = hashidx_count;
2937
2938 width = 1;
2939 start_offset = 0;
2940 size = 0;
2941 #ifdef WITH_PYTHON
2942 RTLIL::Memory::get_all_memorys()->insert(std::pair<unsigned int, RTLIL::Memory*>(hashidx_, this));
2943 #endif
2944 }
2945
2946 RTLIL::Process::Process() : module(nullptr)
2947 {
2948 static unsigned int hashidx_count = 123456789;
2949 hashidx_count = mkhash_xorshift(hashidx_count);
2950 hashidx_ = hashidx_count;
2951 }
2952
2953 RTLIL::Cell::Cell() : module(nullptr)
2954 {
2955 static unsigned int hashidx_count = 123456789;
2956 hashidx_count = mkhash_xorshift(hashidx_count);
2957 hashidx_ = hashidx_count;
2958
2959 // log("#memtrace# %p\n", this);
2960 memhasher();
2961
2962 #ifdef WITH_PYTHON
2963 RTLIL::Cell::get_all_cells()->insert(std::pair<unsigned int, RTLIL::Cell*>(hashidx_, this));
2964 #endif
2965 }
2966
2967 RTLIL::Cell::~Cell()
2968 {
2969 #ifdef WITH_PYTHON
2970 RTLIL::Cell::get_all_cells()->erase(hashidx_);
2971 #endif
2972 }
2973
2974 #ifdef WITH_PYTHON
2975 static std::map<unsigned int, RTLIL::Cell*> all_cells;
2976 std::map<unsigned int, RTLIL::Cell*> *RTLIL::Cell::get_all_cells(void)
2977 {
2978 return &all_cells;
2979 }
2980 #endif
2981
2982 bool RTLIL::Cell::hasPort(RTLIL::IdString portname) const
2983 {
2984 return connections_.count(portname) != 0;
2985 }
2986
2987 void RTLIL::Cell::unsetPort(RTLIL::IdString portname)
2988 {
2989 RTLIL::SigSpec signal;
2990 auto conn_it = connections_.find(portname);
2991
2992 if (conn_it != connections_.end())
2993 {
2994 for (auto mon : module->monitors)
2995 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
2996
2997 if (module->design)
2998 for (auto mon : module->design->monitors)
2999 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
3000
3001 if (yosys_xtrace) {
3002 log("#X# Unconnect %s.%s.%s\n", log_id(this->module), log_id(this), log_id(portname));
3003 log_backtrace("-X- ", yosys_xtrace-1);
3004 }
3005
3006 connections_.erase(conn_it);
3007 }
3008 }
3009
3010 void RTLIL::Cell::setPort(RTLIL::IdString portname, RTLIL::SigSpec signal)
3011 {
3012 auto r = connections_.insert(portname);
3013 auto conn_it = r.first;
3014 if (!r.second && conn_it->second == signal)
3015 return;
3016
3017 for (auto mon : module->monitors)
3018 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
3019
3020 if (module->design)
3021 for (auto mon : module->design->monitors)
3022 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
3023
3024 if (yosys_xtrace) {
3025 log("#X# Connect %s.%s.%s = %s (%d)\n", log_id(this->module), log_id(this), log_id(portname), log_signal(signal), GetSize(signal));
3026 log_backtrace("-X- ", yosys_xtrace-1);
3027 }
3028
3029 conn_it->second = std::move(signal);
3030 }
3031
3032 const RTLIL::SigSpec &RTLIL::Cell::getPort(RTLIL::IdString portname) const
3033 {
3034 return connections_.at(portname);
3035 }
3036
3037 const dict<RTLIL::IdString, RTLIL::SigSpec> &RTLIL::Cell::connections() const
3038 {
3039 return connections_;
3040 }
3041
3042 bool RTLIL::Cell::known() const
3043 {
3044 if (yosys_celltypes.cell_known(type))
3045 return true;
3046 if (module && module->design && module->design->module(type))
3047 return true;
3048 return false;
3049 }
3050
3051 bool RTLIL::Cell::input(RTLIL::IdString portname) const
3052 {
3053 if (yosys_celltypes.cell_known(type))
3054 return yosys_celltypes.cell_input(type, portname);
3055 if (module && module->design) {
3056 RTLIL::Module *m = module->design->module(type);
3057 RTLIL::Wire *w = m ? m->wire(portname) : nullptr;
3058 return w && w->port_input;
3059 }
3060 return false;
3061 }
3062
3063 bool RTLIL::Cell::output(RTLIL::IdString portname) const
3064 {
3065 if (yosys_celltypes.cell_known(type))
3066 return yosys_celltypes.cell_output(type, portname);
3067 if (module && module->design) {
3068 RTLIL::Module *m = module->design->module(type);
3069 RTLIL::Wire *w = m ? m->wire(portname) : nullptr;
3070 return w && w->port_output;
3071 }
3072 return false;
3073 }
3074
3075 bool RTLIL::Cell::hasParam(RTLIL::IdString paramname) const
3076 {
3077 return parameters.count(paramname) != 0;
3078 }
3079
3080 void RTLIL::Cell::unsetParam(RTLIL::IdString paramname)
3081 {
3082 parameters.erase(paramname);
3083 }
3084
3085 void RTLIL::Cell::setParam(RTLIL::IdString paramname, RTLIL::Const value)
3086 {
3087 parameters[paramname] = std::move(value);
3088 }
3089
3090 const RTLIL::Const &RTLIL::Cell::getParam(RTLIL::IdString paramname) const
3091 {
3092 const auto &it = parameters.find(paramname);
3093 if (it != parameters.end())
3094 return it->second;
3095 if (module && module->design) {
3096 RTLIL::Module *m = module->design->module(type);
3097 if (m)
3098 return m->parameter_default_values.at(paramname);
3099 }
3100 throw std::out_of_range("Cell::getParam()");
3101 }
3102
3103 void RTLIL::Cell::sort()
3104 {
3105 connections_.sort(sort_by_id_str());
3106 parameters.sort(sort_by_id_str());
3107 attributes.sort(sort_by_id_str());
3108 }
3109
3110 void RTLIL::Cell::check()
3111 {
3112 #ifndef NDEBUG
3113 InternalCellChecker checker(NULL, this);
3114 checker.check();
3115 #endif
3116 }
3117
3118 void RTLIL::Cell::fixup_parameters(bool set_a_signed, bool set_b_signed)
3119 {
3120 if (!type.begins_with("$") || type.begins_with("$_") || type.begins_with("$paramod") || type.begins_with("$fmcombine") ||
3121 type.begins_with("$verific$") || type.begins_with("$array:") || type.begins_with("$extern:"))
3122 return;
3123
3124 if (type == ID($mux) || type == ID($pmux)) {
3125 parameters[ID::WIDTH] = GetSize(connections_[ID::Y]);
3126 if (type == ID($pmux))
3127 parameters[ID::S_WIDTH] = GetSize(connections_[ID::S]);
3128 check();
3129 return;
3130 }
3131
3132 if (type == ID($lut) || type == ID($sop)) {
3133 parameters[ID::WIDTH] = GetSize(connections_[ID::A]);
3134 return;
3135 }
3136
3137 if (type == ID($fa)) {
3138 parameters[ID::WIDTH] = GetSize(connections_[ID::Y]);
3139 return;
3140 }
3141
3142 if (type == ID($lcu)) {
3143 parameters[ID::WIDTH] = GetSize(connections_[ID::CO]);
3144 return;
3145 }
3146
3147 bool signedness_ab = !type.in(ID($slice), ID($concat), ID($macc));
3148
3149 if (connections_.count(ID::A)) {
3150 if (signedness_ab) {
3151 if (set_a_signed)
3152 parameters[ID::A_SIGNED] = true;
3153 else if (parameters.count(ID::A_SIGNED) == 0)
3154 parameters[ID::A_SIGNED] = false;
3155 }
3156 parameters[ID::A_WIDTH] = GetSize(connections_[ID::A]);
3157 }
3158
3159 if (connections_.count(ID::B)) {
3160 if (signedness_ab) {
3161 if (set_b_signed)
3162 parameters[ID::B_SIGNED] = true;
3163 else if (parameters.count(ID::B_SIGNED) == 0)
3164 parameters[ID::B_SIGNED] = false;
3165 }
3166 parameters[ID::B_WIDTH] = GetSize(connections_[ID::B]);
3167 }
3168
3169 if (connections_.count(ID::Y))
3170 parameters[ID::Y_WIDTH] = GetSize(connections_[ID::Y]);
3171
3172 if (connections_.count(ID::Q))
3173 parameters[ID::WIDTH] = GetSize(connections_[ID::Q]);
3174
3175 check();
3176 }
3177
3178 bool RTLIL::Cell::has_memid() const
3179 {
3180 return type.in(ID($memwr), ID($memrd), ID($meminit));
3181 }
3182
3183 bool RTLIL::Cell::is_mem_cell() const
3184 {
3185 return type == ID($mem) || has_memid();
3186 }
3187
3188 RTLIL::SigChunk::SigChunk()
3189 {
3190 wire = NULL;
3191 width = 0;
3192 offset = 0;
3193 }
3194
3195 RTLIL::SigChunk::SigChunk(const RTLIL::Const &value)
3196 {
3197 wire = NULL;
3198 data = value.bits;
3199 width = GetSize(data);
3200 offset = 0;
3201 }
3202
3203 RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire)
3204 {
3205 log_assert(wire != nullptr);
3206 this->wire = wire;
3207 this->width = wire->width;
3208 this->offset = 0;
3209 }
3210
3211 RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire, int offset, int width)
3212 {
3213 log_assert(wire != nullptr);
3214 this->wire = wire;
3215 this->width = width;
3216 this->offset = offset;
3217 }
3218
3219 RTLIL::SigChunk::SigChunk(const std::string &str)
3220 {
3221 wire = NULL;
3222 data = RTLIL::Const(str).bits;
3223 width = GetSize(data);
3224 offset = 0;
3225 }
3226
3227 RTLIL::SigChunk::SigChunk(int val, int width)
3228 {
3229 wire = NULL;
3230 data = RTLIL::Const(val, width).bits;
3231 this->width = GetSize(data);
3232 offset = 0;
3233 }
3234
3235 RTLIL::SigChunk::SigChunk(RTLIL::State bit, int width)
3236 {
3237 wire = NULL;
3238 data = RTLIL::Const(bit, width).bits;
3239 this->width = GetSize(data);
3240 offset = 0;
3241 }
3242
3243 RTLIL::SigChunk::SigChunk(const RTLIL::SigBit &bit)
3244 {
3245 wire = bit.wire;
3246 offset = 0;
3247 if (wire == NULL)
3248 data = RTLIL::Const(bit.data).bits;
3249 else
3250 offset = bit.offset;
3251 width = 1;
3252 }
3253
3254 RTLIL::SigChunk::SigChunk(const RTLIL::SigChunk &sigchunk)
3255 {
3256 *this = sigchunk;
3257 }
3258
3259 RTLIL::SigChunk RTLIL::SigChunk::extract(int offset, int length) const
3260 {
3261 RTLIL::SigChunk ret;
3262 if (wire) {
3263 ret.wire = wire;
3264 ret.offset = this->offset + offset;
3265 ret.width = length;
3266 } else {
3267 for (int i = 0; i < length; i++)
3268 ret.data.push_back(data[offset+i]);
3269 ret.width = length;
3270 }
3271 return ret;
3272 }
3273
3274 bool RTLIL::SigChunk::operator <(const RTLIL::SigChunk &other) const
3275 {
3276 if (wire && other.wire)
3277 if (wire->name != other.wire->name)
3278 return wire->name < other.wire->name;
3279
3280 if (wire != other.wire)
3281 return wire < other.wire;
3282
3283 if (offset != other.offset)
3284 return offset < other.offset;
3285
3286 if (width != other.width)
3287 return width < other.width;
3288
3289 return data < other.data;
3290 }
3291
3292 bool RTLIL::SigChunk::operator ==(const RTLIL::SigChunk &other) const
3293 {
3294 return wire == other.wire && width == other.width && offset == other.offset && data == other.data;
3295 }
3296
3297 bool RTLIL::SigChunk::operator !=(const RTLIL::SigChunk &other) const
3298 {
3299 if (*this == other)
3300 return false;
3301 return true;
3302 }
3303
3304 RTLIL::SigSpec::SigSpec()
3305 {
3306 width_ = 0;
3307 hash_ = 0;
3308 }
3309
3310 RTLIL::SigSpec::SigSpec(const RTLIL::SigSpec &other)
3311 {
3312 *this = other;
3313 }
3314
3315 RTLIL::SigSpec::SigSpec(std::initializer_list<RTLIL::SigSpec> parts)
3316 {
3317 cover("kernel.rtlil.sigspec.init.list");
3318
3319 width_ = 0;
3320 hash_ = 0;
3321
3322 log_assert(parts.size() > 0);
3323 auto ie = parts.begin();
3324 auto it = ie + parts.size() - 1;
3325 while (it >= ie)
3326 append(*it--);
3327 }
3328
3329 RTLIL::SigSpec &RTLIL::SigSpec::operator=(const RTLIL::SigSpec &other)
3330 {
3331 cover("kernel.rtlil.sigspec.assign");
3332
3333 width_ = other.width_;
3334 hash_ = other.hash_;
3335 chunks_ = other.chunks_;
3336 bits_ = other.bits_;
3337 return *this;
3338 }
3339
3340 RTLIL::SigSpec::SigSpec(const RTLIL::Const &value)
3341 {
3342 cover("kernel.rtlil.sigspec.init.const");
3343
3344 if (GetSize(value) != 0) {
3345 chunks_.emplace_back(value);
3346 width_ = chunks_.back().width;
3347 } else {
3348 width_ = 0;
3349 }
3350 hash_ = 0;
3351 check();
3352 }
3353
3354 RTLIL::SigSpec::SigSpec(const RTLIL::SigChunk &chunk)
3355 {
3356 cover("kernel.rtlil.sigspec.init.chunk");
3357
3358 if (chunk.width != 0) {
3359 chunks_.emplace_back(chunk);
3360 width_ = chunks_.back().width;
3361 } else {
3362 width_ = 0;
3363 }
3364 hash_ = 0;
3365 check();
3366 }
3367
3368 RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire)
3369 {
3370 cover("kernel.rtlil.sigspec.init.wire");
3371
3372 if (wire->width != 0) {
3373 chunks_.emplace_back(wire);
3374 width_ = chunks_.back().width;
3375 } else {
3376 width_ = 0;
3377 }
3378 hash_ = 0;
3379 check();
3380 }
3381
3382 RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire, int offset, int width)
3383 {
3384 cover("kernel.rtlil.sigspec.init.wire_part");
3385
3386 if (width != 0) {
3387 chunks_.emplace_back(wire, offset, width);
3388 width_ = chunks_.back().width;
3389 } else {
3390 width_ = 0;
3391 }
3392 hash_ = 0;
3393 check();
3394 }
3395
3396 RTLIL::SigSpec::SigSpec(const std::string &str)
3397 {
3398 cover("kernel.rtlil.sigspec.init.str");
3399
3400 if (str.size() != 0) {
3401 chunks_.emplace_back(str);
3402 width_ = chunks_.back().width;
3403 } else {
3404 width_ = 0;
3405 }
3406 hash_ = 0;
3407 check();
3408 }
3409
3410 RTLIL::SigSpec::SigSpec(int val, int width)
3411 {
3412 cover("kernel.rtlil.sigspec.init.int");
3413
3414 if (width != 0)
3415 chunks_.emplace_back(val, width);
3416 width_ = width;
3417 hash_ = 0;
3418 check();
3419 }
3420
3421 RTLIL::SigSpec::SigSpec(RTLIL::State bit, int width)
3422 {
3423 cover("kernel.rtlil.sigspec.init.state");
3424
3425 if (width != 0)
3426 chunks_.emplace_back(bit, width);
3427 width_ = width;
3428 hash_ = 0;
3429 check();
3430 }
3431
3432 RTLIL::SigSpec::SigSpec(const RTLIL::SigBit &bit, int width)
3433 {
3434 cover("kernel.rtlil.sigspec.init.bit");
3435
3436 if (width != 0) {
3437 if (bit.wire == NULL)
3438 chunks_.emplace_back(bit.data, width);
3439 else
3440 for (int i = 0; i < width; i++)
3441 chunks_.push_back(bit);
3442 }
3443 width_ = width;
3444 hash_ = 0;
3445 check();
3446 }
3447
3448 RTLIL::SigSpec::SigSpec(const std::vector<RTLIL::SigChunk> &chunks)
3449 {
3450 cover("kernel.rtlil.sigspec.init.stdvec_chunks");
3451
3452 width_ = 0;
3453 hash_ = 0;
3454 for (const auto &c : chunks)
3455 append(c);
3456 check();
3457 }
3458
3459 RTLIL::SigSpec::SigSpec(const std::vector<RTLIL::SigBit> &bits)
3460 {
3461 cover("kernel.rtlil.sigspec.init.stdvec_bits");
3462
3463 width_ = 0;
3464 hash_ = 0;
3465 for (const auto &bit : bits)
3466 append(bit);
3467 check();
3468 }
3469
3470 RTLIL::SigSpec::SigSpec(const pool<RTLIL::SigBit> &bits)
3471 {
3472 cover("kernel.rtlil.sigspec.init.pool_bits");
3473
3474 width_ = 0;
3475 hash_ = 0;
3476 for (const auto &bit : bits)
3477 append(bit);
3478 check();
3479 }
3480
3481 RTLIL::SigSpec::SigSpec(const std::set<RTLIL::SigBit> &bits)
3482 {
3483 cover("kernel.rtlil.sigspec.init.stdset_bits");
3484
3485 width_ = 0;
3486 hash_ = 0;
3487 for (const auto &bit : bits)
3488 append(bit);
3489 check();
3490 }
3491
3492 RTLIL::SigSpec::SigSpec(bool bit)
3493 {
3494 cover("kernel.rtlil.sigspec.init.bool");
3495
3496 width_ = 0;
3497 hash_ = 0;
3498 append(SigBit(bit));
3499 check();
3500 }
3501
3502 void RTLIL::SigSpec::pack() const
3503 {
3504 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
3505
3506 if (that->bits_.empty())
3507 return;
3508
3509 cover("kernel.rtlil.sigspec.convert.pack");
3510 log_assert(that->chunks_.empty());
3511
3512 std::vector<RTLIL::SigBit> old_bits;
3513 old_bits.swap(that->bits_);
3514
3515 RTLIL::SigChunk *last = NULL;
3516 int last_end_offset = 0;
3517
3518 for (auto &bit : old_bits) {
3519 if (last && bit.wire == last->wire) {
3520 if (bit.wire == NULL) {
3521 last->data.push_back(bit.data);
3522 last->width++;
3523 continue;
3524 } else if (last_end_offset == bit.offset) {
3525 last_end_offset++;
3526 last->width++;
3527 continue;
3528 }
3529 }
3530 that->chunks_.push_back(bit);
3531 last = &that->chunks_.back();
3532 last_end_offset = bit.offset + 1;
3533 }
3534
3535 check();
3536 }
3537
3538 void RTLIL::SigSpec::unpack() const
3539 {
3540 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
3541
3542 if (that->chunks_.empty())
3543 return;
3544
3545 cover("kernel.rtlil.sigspec.convert.unpack");
3546 log_assert(that->bits_.empty());
3547
3548 that->bits_.reserve(that->width_);
3549 for (auto &c : that->chunks_)
3550 for (int i = 0; i < c.width; i++)
3551 that->bits_.emplace_back(c, i);
3552
3553 that->chunks_.clear();
3554 that->hash_ = 0;
3555 }
3556
3557 void RTLIL::SigSpec::updhash() const
3558 {
3559 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
3560
3561 if (that->hash_ != 0)
3562 return;
3563
3564 cover("kernel.rtlil.sigspec.hash");
3565 that->pack();
3566
3567 that->hash_ = mkhash_init;
3568 for (auto &c : that->chunks_)
3569 if (c.wire == NULL) {
3570 for (auto &v : c.data)
3571 that->hash_ = mkhash(that->hash_, v);
3572 } else {
3573 that->hash_ = mkhash(that->hash_, c.wire->name.index_);
3574 that->hash_ = mkhash(that->hash_, c.offset);
3575 that->hash_ = mkhash(that->hash_, c.width);
3576 }
3577
3578 if (that->hash_ == 0)
3579 that->hash_ = 1;
3580 }
3581
3582 void RTLIL::SigSpec::sort()
3583 {
3584 unpack();
3585 cover("kernel.rtlil.sigspec.sort");
3586 std::sort(bits_.begin(), bits_.end());
3587 }
3588
3589 void RTLIL::SigSpec::sort_and_unify()
3590 {
3591 unpack();
3592 cover("kernel.rtlil.sigspec.sort_and_unify");
3593
3594 // A copy of the bits vector is used to prevent duplicating the logic from
3595 // SigSpec::SigSpec(std::vector<SigBit>). This incurrs an extra copy but
3596 // that isn't showing up as significant in profiles.
3597 std::vector<SigBit> unique_bits = bits_;
3598 std::sort(unique_bits.begin(), unique_bits.end());
3599 auto last = std::unique(unique_bits.begin(), unique_bits.end());
3600 unique_bits.erase(last, unique_bits.end());
3601
3602 *this = unique_bits;
3603 }
3604
3605 void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with)
3606 {
3607 replace(pattern, with, this);
3608 }
3609
3610 void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with, RTLIL::SigSpec *other) const
3611 {
3612 log_assert(other != NULL);
3613 log_assert(width_ == other->width_);
3614 log_assert(pattern.width_ == with.width_);
3615
3616 pattern.unpack();
3617 with.unpack();
3618 unpack();
3619 other->unpack();
3620
3621 for (int i = 0; i < GetSize(pattern.bits_); i++) {
3622 if (pattern.bits_[i].wire != NULL) {
3623 for (int j = 0; j < GetSize(bits_); j++) {
3624 if (bits_[j] == pattern.bits_[i]) {
3625 other->bits_[j] = with.bits_[i];
3626 }
3627 }
3628 }
3629 }
3630
3631 other->check();
3632 }
3633
3634 void RTLIL::SigSpec::replace(const dict<RTLIL::SigBit, RTLIL::SigBit> &rules)
3635 {
3636 replace(rules, this);
3637 }
3638
3639 void RTLIL::SigSpec::replace(const dict<RTLIL::SigBit, RTLIL::SigBit> &rules, RTLIL::SigSpec *other) const
3640 {
3641 cover("kernel.rtlil.sigspec.replace_dict");
3642
3643 log_assert(other != NULL);
3644 log_assert(width_ == other->width_);
3645
3646 if (rules.empty()) return;
3647 unpack();
3648 other->unpack();
3649
3650 for (int i = 0; i < GetSize(bits_); i++) {
3651 auto it = rules.find(bits_[i]);
3652 if (it != rules.end())
3653 other->bits_[i] = it->second;
3654 }
3655
3656 other->check();
3657 }
3658
3659 void RTLIL::SigSpec::replace(const std::map<RTLIL::SigBit, RTLIL::SigBit> &rules)
3660 {
3661 replace(rules, this);
3662 }
3663
3664 void RTLIL::SigSpec::replace(const std::map<RTLIL::SigBit, RTLIL::SigBit> &rules, RTLIL::SigSpec *other) const
3665 {
3666 cover("kernel.rtlil.sigspec.replace_map");
3667
3668 log_assert(other != NULL);
3669 log_assert(width_ == other->width_);
3670
3671 if (rules.empty()) return;
3672 unpack();
3673 other->unpack();
3674
3675 for (int i = 0; i < GetSize(bits_); i++) {
3676 auto it = rules.find(bits_[i]);
3677 if (it != rules.end())
3678 other->bits_[i] = it->second;
3679 }
3680
3681 other->check();
3682 }
3683
3684 void RTLIL::SigSpec::remove(const RTLIL::SigSpec &pattern)
3685 {
3686 remove2(pattern, NULL);
3687 }
3688
3689 void RTLIL::SigSpec::remove(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other) const
3690 {
3691 RTLIL::SigSpec tmp = *this;
3692 tmp.remove2(pattern, other);
3693 }
3694
3695 void RTLIL::SigSpec::remove2(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other)
3696 {
3697 if (other)
3698 cover("kernel.rtlil.sigspec.remove_other");
3699 else
3700 cover("kernel.rtlil.sigspec.remove");
3701
3702 unpack();
3703 if (other != NULL) {
3704 log_assert(width_ == other->width_);
3705 other->unpack();
3706 }
3707
3708 for (int i = GetSize(bits_) - 1; i >= 0; i--)
3709 {
3710 if (bits_[i].wire == NULL) continue;
3711
3712 for (auto &pattern_chunk : pattern.chunks())
3713 if (bits_[i].wire == pattern_chunk.wire &&
3714 bits_[i].offset >= pattern_chunk.offset &&
3715 bits_[i].offset < pattern_chunk.offset + pattern_chunk.width) {
3716 bits_.erase(bits_.begin() + i);
3717 width_--;
3718 if (other != NULL) {
3719 other->bits_.erase(other->bits_.begin() + i);
3720 other->width_--;
3721 }
3722 break;
3723 }
3724 }
3725
3726 check();
3727 }
3728
3729 void RTLIL::SigSpec::remove(const pool<RTLIL::SigBit> &pattern)
3730 {
3731 remove2(pattern, NULL);
3732 }
3733
3734 void RTLIL::SigSpec::remove(const pool<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other) const
3735 {
3736 RTLIL::SigSpec tmp = *this;
3737 tmp.remove2(pattern, other);
3738 }
3739
3740 void RTLIL::SigSpec::remove2(const pool<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other)
3741 {
3742 if (other)
3743 cover("kernel.rtlil.sigspec.remove_other");
3744 else
3745 cover("kernel.rtlil.sigspec.remove");
3746
3747 unpack();
3748
3749 if (other != NULL) {
3750 log_assert(width_ == other->width_);
3751 other->unpack();
3752 }
3753
3754 for (int i = GetSize(bits_) - 1; i >= 0; i--) {
3755 if (bits_[i].wire != NULL && pattern.count(bits_[i])) {
3756 bits_.erase(bits_.begin() + i);
3757 width_--;
3758 if (other != NULL) {
3759 other->bits_.erase(other->bits_.begin() + i);
3760 other->width_--;
3761 }
3762 }
3763 }
3764
3765 check();
3766 }
3767
3768 void RTLIL::SigSpec::remove2(const std::set<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other)
3769 {
3770 if (other)
3771 cover("kernel.rtlil.sigspec.remove_other");
3772 else
3773 cover("kernel.rtlil.sigspec.remove");
3774
3775 unpack();
3776
3777 if (other != NULL) {
3778 log_assert(width_ == other->width_);
3779 other->unpack();
3780 }
3781
3782 for (int i = GetSize(bits_) - 1; i >= 0; i--) {
3783 if (bits_[i].wire != NULL && pattern.count(bits_[i])) {
3784 bits_.erase(bits_.begin() + i);
3785 width_--;
3786 if (other != NULL) {
3787 other->bits_.erase(other->bits_.begin() + i);
3788 other->width_--;
3789 }
3790 }
3791 }
3792
3793 check();
3794 }
3795
3796 RTLIL::SigSpec RTLIL::SigSpec::extract(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec *other) const
3797 {
3798 if (other)
3799 cover("kernel.rtlil.sigspec.extract_other");
3800 else
3801 cover("kernel.rtlil.sigspec.extract");
3802
3803 log_assert(other == NULL || width_ == other->width_);
3804
3805 RTLIL::SigSpec ret;
3806 std::vector<RTLIL::SigBit> bits_match = to_sigbit_vector();
3807
3808 for (auto& pattern_chunk : pattern.chunks()) {
3809 if (other) {
3810 std::vector<RTLIL::SigBit> bits_other = other->to_sigbit_vector();
3811 for (int i = 0; i < width_; i++)
3812 if (bits_match[i].wire &&
3813 bits_match[i].wire == pattern_chunk.wire &&
3814 bits_match[i].offset >= pattern_chunk.offset &&
3815 bits_match[i].offset < pattern_chunk.offset + pattern_chunk.width)
3816 ret.append(bits_other[i]);
3817 } else {
3818 for (int i = 0; i < width_; i++)
3819 if (bits_match[i].wire &&
3820 bits_match[i].wire == pattern_chunk.wire &&
3821 bits_match[i].offset >= pattern_chunk.offset &&
3822 bits_match[i].offset < pattern_chunk.offset + pattern_chunk.width)
3823 ret.append(bits_match[i]);
3824 }
3825 }
3826
3827 ret.check();
3828 return ret;
3829 }
3830
3831 RTLIL::SigSpec RTLIL::SigSpec::extract(const pool<RTLIL::SigBit> &pattern, const RTLIL::SigSpec *other) const
3832 {
3833 if (other)
3834 cover("kernel.rtlil.sigspec.extract_other");
3835 else
3836 cover("kernel.rtlil.sigspec.extract");
3837
3838 log_assert(other == NULL || width_ == other->width_);
3839
3840 std::vector<RTLIL::SigBit> bits_match = to_sigbit_vector();
3841 RTLIL::SigSpec ret;
3842
3843 if (other) {
3844 std::vector<RTLIL::SigBit> bits_other = other->to_sigbit_vector();
3845 for (int i = 0; i < width_; i++)
3846 if (bits_match[i].wire && pattern.count(bits_match[i]))
3847 ret.append(bits_other[i]);
3848 } else {
3849 for (int i = 0; i < width_; i++)
3850 if (bits_match[i].wire && pattern.count(bits_match[i]))
3851 ret.append(bits_match[i]);
3852 }
3853
3854 ret.check();
3855 return ret;
3856 }
3857
3858 void RTLIL::SigSpec::replace(int offset, const RTLIL::SigSpec &with)
3859 {
3860 cover("kernel.rtlil.sigspec.replace_pos");
3861
3862 unpack();
3863 with.unpack();
3864
3865 log_assert(offset >= 0);
3866 log_assert(with.width_ >= 0);
3867 log_assert(offset+with.width_ <= width_);
3868
3869 for (int i = 0; i < with.width_; i++)
3870 bits_.at(offset + i) = with.bits_.at(i);
3871
3872 check();
3873 }
3874
3875 void RTLIL::SigSpec::remove_const()
3876 {
3877 if (packed())
3878 {
3879 cover("kernel.rtlil.sigspec.remove_const.packed");
3880
3881 std::vector<RTLIL::SigChunk> new_chunks;
3882 new_chunks.reserve(GetSize(chunks_));
3883
3884 width_ = 0;
3885 for (auto &chunk : chunks_)
3886 if (chunk.wire != NULL) {
3887 if (!new_chunks.empty() &&
3888 new_chunks.back().wire == chunk.wire &&
3889 new_chunks.back().offset + new_chunks.back().width == chunk.offset) {
3890 new_chunks.back().width += chunk.width;
3891 } else {
3892 new_chunks.push_back(chunk);
3893 }
3894 width_ += chunk.width;
3895 }
3896
3897 chunks_.swap(new_chunks);
3898 }
3899 else
3900 {
3901 cover("kernel.rtlil.sigspec.remove_const.unpacked");
3902
3903 std::vector<RTLIL::SigBit> new_bits;
3904 new_bits.reserve(width_);
3905
3906 for (auto &bit : bits_)
3907 if (bit.wire != NULL)
3908 new_bits.push_back(bit);
3909
3910 bits_.swap(new_bits);
3911 width_ = bits_.size();
3912 }
3913
3914 check();
3915 }
3916
3917 void RTLIL::SigSpec::remove(int offset, int length)
3918 {
3919 cover("kernel.rtlil.sigspec.remove_pos");
3920
3921 unpack();
3922
3923 log_assert(offset >= 0);
3924 log_assert(length >= 0);
3925 log_assert(offset + length <= width_);
3926
3927 bits_.erase(bits_.begin() + offset, bits_.begin() + offset + length);
3928 width_ = bits_.size();
3929
3930 check();
3931 }
3932
3933 RTLIL::SigSpec RTLIL::SigSpec::extract(int offset, int length) const
3934 {
3935 unpack();
3936 cover("kernel.rtlil.sigspec.extract_pos");
3937 return std::vector<RTLIL::SigBit>(bits_.begin() + offset, bits_.begin() + offset + length);
3938 }
3939
3940 void RTLIL::SigSpec::append(const RTLIL::SigSpec &signal)
3941 {
3942 if (signal.width_ == 0)
3943 return;
3944
3945 if (width_ == 0) {
3946 *this = signal;
3947 return;
3948 }
3949
3950 cover("kernel.rtlil.sigspec.append");
3951
3952 if (packed() != signal.packed()) {
3953 pack();
3954 signal.pack();
3955 }
3956
3957 if (packed())
3958 for (auto &other_c : signal.chunks_)
3959 {
3960 auto &my_last_c = chunks_.back();
3961 if (my_last_c.wire == NULL && other_c.wire == NULL) {
3962 auto &this_data = my_last_c.data;
3963 auto &other_data = other_c.data;
3964 this_data.insert(this_data.end(), other_data.begin(), other_data.end());
3965 my_last_c.width += other_c.width;
3966 } else
3967 if (my_last_c.wire == other_c.wire && my_last_c.offset + my_last_c.width == other_c.offset) {
3968 my_last_c.width += other_c.width;
3969 } else
3970 chunks_.push_back(other_c);
3971 }
3972 else
3973 bits_.insert(bits_.end(), signal.bits_.begin(), signal.bits_.end());
3974
3975 width_ += signal.width_;
3976 check();
3977 }
3978
3979 void RTLIL::SigSpec::append(const RTLIL::SigBit &bit)
3980 {
3981 if (packed())
3982 {
3983 cover("kernel.rtlil.sigspec.append_bit.packed");
3984
3985 if (chunks_.size() == 0)
3986 chunks_.push_back(bit);
3987 else
3988 if (bit.wire == NULL)
3989 if (chunks_.back().wire == NULL) {
3990 chunks_.back().data.push_back(bit.data);
3991 chunks_.back().width++;
3992 } else
3993 chunks_.push_back(bit);
3994 else
3995 if (chunks_.back().wire == bit.wire && chunks_.back().offset + chunks_.back().width == bit.offset)
3996 chunks_.back().width++;
3997 else
3998 chunks_.push_back(bit);
3999 }
4000 else
4001 {
4002 cover("kernel.rtlil.sigspec.append_bit.unpacked");
4003 bits_.push_back(bit);
4004 }
4005
4006 width_++;
4007 check();
4008 }
4009
4010 void RTLIL::SigSpec::extend_u0(int width, bool is_signed)
4011 {
4012 cover("kernel.rtlil.sigspec.extend_u0");
4013
4014 pack();
4015
4016 if (width_ > width)
4017 remove(width, width_ - width);
4018
4019 if (width_ < width) {
4020 RTLIL::SigBit padding = width_ > 0 ? (*this)[width_ - 1] : RTLIL::State::Sx;
4021 if (!is_signed)
4022 padding = RTLIL::State::S0;
4023 while (width_ < width)
4024 append(padding);
4025 }
4026
4027 }
4028
4029 RTLIL::SigSpec RTLIL::SigSpec::repeat(int num) const
4030 {
4031 cover("kernel.rtlil.sigspec.repeat");
4032
4033 RTLIL::SigSpec sig;
4034 for (int i = 0; i < num; i++)
4035 sig.append(*this);
4036 return sig;
4037 }
4038
4039 #ifndef NDEBUG
4040 void RTLIL::SigSpec::check() const
4041 {
4042 if (width_ > 64)
4043 {
4044 cover("kernel.rtlil.sigspec.check.skip");
4045 }
4046 else if (packed())
4047 {
4048 cover("kernel.rtlil.sigspec.check.packed");
4049
4050 int w = 0;
4051 for (size_t i = 0; i < chunks_.size(); i++) {
4052 const RTLIL::SigChunk &chunk = chunks_[i];
4053 log_assert(chunk.width != 0);
4054 if (chunk.wire == NULL) {
4055 if (i > 0)
4056 log_assert(chunks_[i-1].wire != NULL);
4057 log_assert(chunk.offset == 0);
4058 log_assert(chunk.data.size() == (size_t)chunk.width);
4059 } else {
4060 if (i > 0 && chunks_[i-1].wire == chunk.wire)
4061 log_assert(chunk.offset != chunks_[i-1].offset + chunks_[i-1].width);
4062 log_assert(chunk.offset >= 0);
4063 log_assert(chunk.width >= 0);
4064 log_assert(chunk.offset + chunk.width <= chunk.wire->width);
4065 log_assert(chunk.data.size() == 0);
4066 }
4067 w += chunk.width;
4068 }
4069 log_assert(w == width_);
4070 log_assert(bits_.empty());
4071 }
4072 else
4073 {
4074 cover("kernel.rtlil.sigspec.check.unpacked");
4075
4076 log_assert(width_ == GetSize(bits_));
4077 log_assert(chunks_.empty());
4078 }
4079 }
4080 #endif
4081
4082 bool RTLIL::SigSpec::operator <(const RTLIL::SigSpec &other) const
4083 {
4084 cover("kernel.rtlil.sigspec.comp_lt");
4085
4086 if (this == &other)
4087 return false;
4088
4089 if (width_ != other.width_)
4090 return width_ < other.width_;
4091
4092 pack();
4093 other.pack();
4094
4095 if (chunks_.size() != other.chunks_.size())
4096 return chunks_.size() < other.chunks_.size();
4097
4098 updhash();
4099 other.updhash();
4100
4101 if (hash_ != other.hash_)
4102 return hash_ < other.hash_;
4103
4104 for (size_t i = 0; i < chunks_.size(); i++)
4105 if (chunks_[i] != other.chunks_[i]) {
4106 cover("kernel.rtlil.sigspec.comp_lt.hash_collision");
4107 return chunks_[i] < other.chunks_[i];
4108 }
4109
4110 cover("kernel.rtlil.sigspec.comp_lt.equal");
4111 return false;
4112 }
4113
4114 bool RTLIL::SigSpec::operator ==(const RTLIL::SigSpec &other) const
4115 {
4116 cover("kernel.rtlil.sigspec.comp_eq");
4117
4118 if (this == &other)
4119 return true;
4120
4121 if (width_ != other.width_)
4122 return false;
4123
4124 // Without this, SigSpec() == SigSpec(State::S0, 0) will fail
4125 // since the RHS will contain one SigChunk of width 0 causing
4126 // the size check below to fail
4127 if (width_ == 0)
4128 return true;
4129
4130 pack();
4131 other.pack();
4132
4133 if (chunks_.size() != other.chunks_.size())
4134 return false;
4135
4136 updhash();
4137 other.updhash();
4138
4139 if (hash_ != other.hash_)
4140 return false;
4141
4142 for (size_t i = 0; i < chunks_.size(); i++)
4143 if (chunks_[i] != other.chunks_[i]) {
4144 cover("kernel.rtlil.sigspec.comp_eq.hash_collision");
4145 return false;
4146 }
4147
4148 cover("kernel.rtlil.sigspec.comp_eq.equal");
4149 return true;
4150 }
4151
4152 bool RTLIL::SigSpec::is_wire() const
4153 {
4154 cover("kernel.rtlil.sigspec.is_wire");
4155
4156 pack();
4157 return GetSize(chunks_) == 1 && chunks_[0].wire && chunks_[0].wire->width == width_;
4158 }
4159
4160 bool RTLIL::SigSpec::is_chunk() const
4161 {
4162 cover("kernel.rtlil.sigspec.is_chunk");
4163
4164 pack();
4165 return GetSize(chunks_) == 1;
4166 }
4167
4168 bool RTLIL::SigSpec::is_fully_const() const
4169 {
4170 cover("kernel.rtlil.sigspec.is_fully_const");
4171
4172 pack();
4173 for (auto it = chunks_.begin(); it != chunks_.end(); it++)
4174 if (it->width > 0 && it->wire != NULL)
4175 return false;
4176 return true;
4177 }
4178
4179 bool RTLIL::SigSpec::is_fully_zero() const
4180 {
4181 cover("kernel.rtlil.sigspec.is_fully_zero");
4182
4183 pack();
4184 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
4185 if (it->width > 0 && it->wire != NULL)
4186 return false;
4187 for (size_t i = 0; i < it->data.size(); i++)
4188 if (it->data[i] != RTLIL::State::S0)
4189 return false;
4190 }
4191 return true;
4192 }
4193
4194 bool RTLIL::SigSpec::is_fully_ones() const
4195 {
4196 cover("kernel.rtlil.sigspec.is_fully_ones");
4197
4198 pack();
4199 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
4200 if (it->width > 0 && it->wire != NULL)
4201 return false;
4202 for (size_t i = 0; i < it->data.size(); i++)
4203 if (it->data[i] != RTLIL::State::S1)
4204 return false;
4205 }
4206 return true;
4207 }
4208
4209 bool RTLIL::SigSpec::is_fully_def() const
4210 {
4211 cover("kernel.rtlil.sigspec.is_fully_def");
4212
4213 pack();
4214 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
4215 if (it->width > 0 && it->wire != NULL)
4216 return false;
4217 for (size_t i = 0; i < it->data.size(); i++)
4218 if (it->data[i] != RTLIL::State::S0 && it->data[i] != RTLIL::State::S1)
4219 return false;
4220 }
4221 return true;
4222 }
4223
4224 bool RTLIL::SigSpec::is_fully_undef() const
4225 {
4226 cover("kernel.rtlil.sigspec.is_fully_undef");
4227
4228 pack();
4229 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
4230 if (it->width > 0 && it->wire != NULL)
4231 return false;
4232 for (size_t i = 0; i < it->data.size(); i++)
4233 if (it->data[i] != RTLIL::State::Sx && it->data[i] != RTLIL::State::Sz)
4234 return false;
4235 }
4236 return true;
4237 }
4238
4239 bool RTLIL::SigSpec::has_const() const
4240 {
4241 cover("kernel.rtlil.sigspec.has_const");
4242
4243 pack();
4244 for (auto it = chunks_.begin(); it != chunks_.end(); it++)
4245 if (it->width > 0 && it->wire == NULL)
4246 return true;
4247 return false;
4248 }
4249
4250 bool RTLIL::SigSpec::has_marked_bits() const
4251 {
4252 cover("kernel.rtlil.sigspec.has_marked_bits");
4253
4254 pack();
4255 for (auto it = chunks_.begin(); it != chunks_.end(); it++)
4256 if (it->width > 0 && it->wire == NULL) {
4257 for (size_t i = 0; i < it->data.size(); i++)
4258 if (it->data[i] == RTLIL::State::Sm)
4259 return true;
4260 }
4261 return false;
4262 }
4263
4264 bool RTLIL::SigSpec::is_onehot(int *pos) const
4265 {
4266 cover("kernel.rtlil.sigspec.is_onehot");
4267
4268 pack();
4269 if (!is_fully_const())
4270 return false;
4271 log_assert(GetSize(chunks_) <= 1);
4272 if (width_)
4273 return RTLIL::Const(chunks_[0].data).is_onehot(pos);
4274 return false;
4275 }
4276
4277 bool RTLIL::SigSpec::as_bool() const
4278 {
4279 cover("kernel.rtlil.sigspec.as_bool");
4280
4281 pack();
4282 log_assert(is_fully_const() && GetSize(chunks_) <= 1);
4283 if (width_)
4284 return RTLIL::Const(chunks_[0].data).as_bool();
4285 return false;
4286 }
4287
4288 int RTLIL::SigSpec::as_int(bool is_signed) const
4289 {
4290 cover("kernel.rtlil.sigspec.as_int");
4291
4292 pack();
4293 log_assert(is_fully_const() && GetSize(chunks_) <= 1);
4294 if (width_)
4295 return RTLIL::Const(chunks_[0].data).as_int(is_signed);
4296 return 0;
4297 }
4298
4299 std::string RTLIL::SigSpec::as_string() const
4300 {
4301 cover("kernel.rtlil.sigspec.as_string");
4302
4303 pack();
4304 std::string str;
4305 str.reserve(size());
4306 for (size_t i = chunks_.size(); i > 0; i--) {
4307 const RTLIL::SigChunk &chunk = chunks_[i-1];
4308 if (chunk.wire != NULL)
4309 str.append(chunk.width, '?');
4310 else
4311 str += RTLIL::Const(chunk.data).as_string();
4312 }
4313 return str;
4314 }
4315
4316 RTLIL::Const RTLIL::SigSpec::as_const() const
4317 {
4318 cover("kernel.rtlil.sigspec.as_const");
4319
4320 pack();
4321 log_assert(is_fully_const() && GetSize(chunks_) <= 1);
4322 if (width_)
4323 return chunks_[0].data;
4324 return RTLIL::Const();
4325 }
4326
4327 RTLIL::Wire *RTLIL::SigSpec::as_wire() const
4328 {
4329 cover("kernel.rtlil.sigspec.as_wire");
4330
4331 pack();
4332 log_assert(is_wire());
4333 return chunks_[0].wire;
4334 }
4335
4336 RTLIL::SigChunk RTLIL::SigSpec::as_chunk() const
4337 {
4338 cover("kernel.rtlil.sigspec.as_chunk");
4339
4340 pack();
4341 log_assert(is_chunk());
4342 return chunks_[0];
4343 }
4344
4345 RTLIL::SigBit RTLIL::SigSpec::as_bit() const
4346 {
4347 cover("kernel.rtlil.sigspec.as_bit");
4348
4349 log_assert(width_ == 1);
4350 if (packed())
4351 return RTLIL::SigBit(*chunks_.begin());
4352 else
4353 return bits_[0];
4354 }
4355
4356 bool RTLIL::SigSpec::match(const char* pattern) const
4357 {
4358 cover("kernel.rtlil.sigspec.match");
4359
4360 unpack();
4361 log_assert(int(strlen(pattern)) == GetSize(bits_));
4362
4363 for (auto it = bits_.rbegin(); it != bits_.rend(); it++, pattern++) {
4364 if (*pattern == ' ')
4365 continue;
4366 if (*pattern == '*') {
4367 if (*it != State::Sz && *it != State::Sx)
4368 return false;
4369 continue;
4370 }
4371 if (*pattern == '0') {
4372 if (*it != State::S0)
4373 return false;
4374 } else
4375 if (*pattern == '1') {
4376 if (*it != State::S1)
4377 return false;
4378 } else
4379 log_abort();
4380 }
4381
4382 return true;
4383 }
4384
4385 std::set<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_set() const
4386 {
4387 cover("kernel.rtlil.sigspec.to_sigbit_set");
4388
4389 pack();
4390 std::set<RTLIL::SigBit> sigbits;
4391 for (auto &c : chunks_)
4392 for (int i = 0; i < c.width; i++)
4393 sigbits.insert(RTLIL::SigBit(c, i));
4394 return sigbits;
4395 }
4396
4397 pool<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_pool() const
4398 {
4399 cover("kernel.rtlil.sigspec.to_sigbit_pool");
4400
4401 pack();
4402 pool<RTLIL::SigBit> sigbits;
4403 sigbits.reserve(size());
4404 for (auto &c : chunks_)
4405 for (int i = 0; i < c.width; i++)
4406 sigbits.insert(RTLIL::SigBit(c, i));
4407 return sigbits;
4408 }
4409
4410 std::vector<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_vector() const
4411 {
4412 cover("kernel.rtlil.sigspec.to_sigbit_vector");
4413
4414 unpack();
4415 return bits_;
4416 }
4417
4418 std::map<RTLIL::SigBit, RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_map(const RTLIL::SigSpec &other) const
4419 {
4420 cover("kernel.rtlil.sigspec.to_sigbit_map");
4421
4422 unpack();
4423 other.unpack();
4424
4425 log_assert(width_ == other.width_);
4426
4427 std::map<RTLIL::SigBit, RTLIL::SigBit> new_map;
4428 for (int i = 0; i < width_; i++)
4429 new_map[bits_[i]] = other.bits_[i];
4430
4431 return new_map;
4432 }
4433
4434 dict<RTLIL::SigBit, RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_dict(const RTLIL::SigSpec &other) const
4435 {
4436 cover("kernel.rtlil.sigspec.to_sigbit_dict");
4437
4438 unpack();
4439 other.unpack();
4440
4441 log_assert(width_ == other.width_);
4442
4443 dict<RTLIL::SigBit, RTLIL::SigBit> new_map;
4444 new_map.reserve(size());
4445 for (int i = 0; i < width_; i++)
4446 new_map[bits_[i]] = other.bits_[i];
4447
4448 return new_map;
4449 }
4450
4451 static void sigspec_parse_split(std::vector<std::string> &tokens, const std::string &text, char sep)
4452 {
4453 size_t start = 0, end = 0;
4454 while ((end = text.find(sep, start)) != std::string::npos) {
4455 tokens.push_back(text.substr(start, end - start));
4456 start = end + 1;
4457 }
4458 tokens.push_back(text.substr(start));
4459 }
4460
4461 static int sigspec_parse_get_dummy_line_num()
4462 {
4463 return 0;
4464 }
4465
4466 bool RTLIL::SigSpec::parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str)
4467 {
4468 cover("kernel.rtlil.sigspec.parse");
4469
4470 AST::current_filename = "input";
4471
4472 std::vector<std::string> tokens;
4473 sigspec_parse_split(tokens, str, ',');
4474
4475 sig = RTLIL::SigSpec();
4476 for (int tokidx = int(tokens.size())-1; tokidx >= 0; tokidx--)
4477 {
4478 std::string netname = tokens[tokidx];
4479 std::string indices;
4480
4481 if (netname.size() == 0)
4482 continue;
4483
4484 if (('0' <= netname[0] && netname[0] <= '9') || netname[0] == '\'') {
4485 cover("kernel.rtlil.sigspec.parse.const");
4486 AST::get_line_num = sigspec_parse_get_dummy_line_num;
4487 AST::AstNode *ast = VERILOG_FRONTEND::const2ast(netname);
4488 if (ast == NULL)
4489 return false;
4490 sig.append(RTLIL::Const(ast->bits));
4491 delete ast;
4492 continue;
4493 }
4494
4495 if (module == NULL)
4496 return false;
4497
4498 cover("kernel.rtlil.sigspec.parse.net");
4499
4500 if (netname[0] != '$' && netname[0] != '\\')
4501 netname = "\\" + netname;
4502
4503 if (module->wires_.count(netname) == 0) {
4504 size_t indices_pos = netname.size()-1;
4505 if (indices_pos > 2 && netname[indices_pos] == ']')
4506 {
4507 indices_pos--;
4508 while (indices_pos > 0 && ('0' <= netname[indices_pos] && netname[indices_pos] <= '9')) indices_pos--;
4509 if (indices_pos > 0 && netname[indices_pos] == ':') {
4510 indices_pos--;
4511 while (indices_pos > 0 && ('0' <= netname[indices_pos] && netname[indices_pos] <= '9')) indices_pos--;
4512 }
4513 if (indices_pos > 0 && netname[indices_pos] == '[') {
4514 indices = netname.substr(indices_pos);
4515 netname = netname.substr(0, indices_pos);
4516 }
4517 }
4518 }
4519
4520 if (module->wires_.count(netname) == 0)
4521 return false;
4522
4523 RTLIL::Wire *wire = module->wires_.at(netname);
4524 if (!indices.empty()) {
4525 std::vector<std::string> index_tokens;
4526 sigspec_parse_split(index_tokens, indices.substr(1, indices.size()-2), ':');
4527 if (index_tokens.size() == 1) {
4528 cover("kernel.rtlil.sigspec.parse.bit_sel");
4529 int a = atoi(index_tokens.at(0).c_str());
4530 if (a < 0 || a >= wire->width)
4531 return false;
4532 sig.append(RTLIL::SigSpec(wire, a));
4533 } else {
4534 cover("kernel.rtlil.sigspec.parse.part_sel");
4535 int a = atoi(index_tokens.at(0).c_str());
4536 int b = atoi(index_tokens.at(1).c_str());
4537 if (a > b) {
4538 int tmp = a;
4539 a = b, b = tmp;
4540 }
4541 if (a < 0 || a >= wire->width)
4542 return false;
4543 if (b < 0 || b >= wire->width)
4544 return false;
4545 sig.append(RTLIL::SigSpec(wire, a, b-a+1));
4546 }
4547 } else
4548 sig.append(wire);
4549 }
4550
4551 return true;
4552 }
4553
4554 bool RTLIL::SigSpec::parse_sel(RTLIL::SigSpec &sig, RTLIL::Design *design, RTLIL::Module *module, std::string str)
4555 {
4556 if (str.empty() || str[0] != '@')
4557 return parse(sig, module, str);
4558
4559 cover("kernel.rtlil.sigspec.parse.sel");
4560
4561 str = RTLIL::escape_id(str.substr(1));
4562 if (design->selection_vars.count(str) == 0)
4563 return false;
4564
4565 sig = RTLIL::SigSpec();
4566 RTLIL::Selection &sel = design->selection_vars.at(str);
4567 for (auto &it : module->wires_)
4568 if (sel.selected_member(module->name, it.first))
4569 sig.append(it.second);
4570
4571 return true;
4572 }
4573
4574 bool RTLIL::SigSpec::parse_rhs(const RTLIL::SigSpec &lhs, RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str)
4575 {
4576 if (str == "0") {
4577 cover("kernel.rtlil.sigspec.parse.rhs_zeros");
4578 sig = RTLIL::SigSpec(RTLIL::State::S0, lhs.width_);
4579 return true;
4580 }
4581
4582 if (str == "~0") {
4583 cover("kernel.rtlil.sigspec.parse.rhs_ones");
4584 sig = RTLIL::SigSpec(RTLIL::State::S1, lhs.width_);
4585 return true;
4586 }
4587
4588 if (lhs.chunks_.size() == 1) {
4589 char *p = (char*)str.c_str(), *endptr;
4590 long int val = strtol(p, &endptr, 10);
4591 if (endptr && endptr != p && *endptr == 0) {
4592 sig = RTLIL::SigSpec(val, lhs.width_);
4593 cover("kernel.rtlil.sigspec.parse.rhs_dec");
4594 return true;
4595 }
4596 }
4597
4598 return parse(sig, module, str);
4599 }
4600
4601 RTLIL::CaseRule::~CaseRule()
4602 {
4603 for (auto it = switches.begin(); it != switches.end(); it++)
4604 delete *it;
4605 }
4606
4607 bool RTLIL::CaseRule::empty() const
4608 {
4609 return actions.empty() && switches.empty();
4610 }
4611
4612 RTLIL::CaseRule *RTLIL::CaseRule::clone() const
4613 {
4614 RTLIL::CaseRule *new_caserule = new RTLIL::CaseRule;
4615 new_caserule->compare = compare;
4616 new_caserule->actions = actions;
4617 for (auto &it : switches)
4618 new_caserule->switches.push_back(it->clone());
4619 return new_caserule;
4620 }
4621
4622 RTLIL::SwitchRule::~SwitchRule()
4623 {
4624 for (auto it = cases.begin(); it != cases.end(); it++)
4625 delete *it;
4626 }
4627
4628 bool RTLIL::SwitchRule::empty() const
4629 {
4630 return cases.empty();
4631 }
4632
4633 RTLIL::SwitchRule *RTLIL::SwitchRule::clone() const
4634 {
4635 RTLIL::SwitchRule *new_switchrule = new RTLIL::SwitchRule;
4636 new_switchrule->signal = signal;
4637 new_switchrule->attributes = attributes;
4638 for (auto &it : cases)
4639 new_switchrule->cases.push_back(it->clone());
4640 return new_switchrule;
4641
4642 }
4643
4644 RTLIL::SyncRule *RTLIL::SyncRule::clone() const
4645 {
4646 RTLIL::SyncRule *new_syncrule = new RTLIL::SyncRule;
4647 new_syncrule->type = type;
4648 new_syncrule->signal = signal;
4649 new_syncrule->actions = actions;
4650 new_syncrule->mem_write_actions = mem_write_actions;
4651 return new_syncrule;
4652 }
4653
4654 RTLIL::Process::~Process()
4655 {
4656 for (auto it = syncs.begin(); it != syncs.end(); it++)
4657 delete *it;
4658 }
4659
4660 RTLIL::Process *RTLIL::Process::clone() const
4661 {
4662 RTLIL::Process *new_proc = new RTLIL::Process;
4663
4664 new_proc->name = name;
4665 new_proc->attributes = attributes;
4666
4667 RTLIL::CaseRule *rc_ptr = root_case.clone();
4668 new_proc->root_case = *rc_ptr;
4669 rc_ptr->switches.clear();
4670 delete rc_ptr;
4671
4672 for (auto &it : syncs)
4673 new_proc->syncs.push_back(it->clone());
4674
4675 return new_proc;
4676 }
4677
4678 #ifdef WITH_PYTHON
4679 RTLIL::Memory::~Memory()
4680 {
4681 RTLIL::Memory::get_all_memorys()->erase(hashidx_);
4682 }
4683 static std::map<unsigned int, RTLIL::Memory*> all_memorys;
4684 std::map<unsigned int, RTLIL::Memory*> *RTLIL::Memory::get_all_memorys(void)
4685 {
4686 return &all_memorys;
4687 }
4688 #endif
4689 YOSYS_NAMESPACE_END