2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include "kernel/yosys.h"
21 #include "kernel/macc.h"
22 #include "kernel/celltypes.h"
23 #include "frontends/verilog/verilog_frontend.h"
24 #include "backends/ilang/ilang_backend.h"
31 RTLIL::IdString::destruct_guard_t
RTLIL::IdString::destruct_guard
;
32 std::vector
<int> RTLIL::IdString::global_refcount_storage_
;
33 std::vector
<char*> RTLIL::IdString::global_id_storage_
;
34 dict
<char*, int, hash_cstr_ops
> RTLIL::IdString::global_id_index_
;
35 std::vector
<int> RTLIL::IdString::global_free_idx_list_
;
36 int RTLIL::IdString::last_created_idx_
[8];
37 int RTLIL::IdString::last_created_idx_ptr_
;
41 flags
= RTLIL::CONST_FLAG_NONE
;
44 RTLIL::Const::Const(std::string str
)
46 flags
= RTLIL::CONST_FLAG_STRING
;
47 for (int i
= str
.size()-1; i
>= 0; i
--) {
48 unsigned char ch
= str
[i
];
49 for (int j
= 0; j
< 8; j
++) {
50 bits
.push_back((ch
& 1) != 0 ? RTLIL::S1
: RTLIL::S0
);
56 RTLIL::Const::Const(int val
, int width
)
58 flags
= RTLIL::CONST_FLAG_NONE
;
59 for (int i
= 0; i
< width
; i
++) {
60 bits
.push_back((val
& 1) != 0 ? RTLIL::S1
: RTLIL::S0
);
65 RTLIL::Const::Const(RTLIL::State bit
, int width
)
67 flags
= RTLIL::CONST_FLAG_NONE
;
68 for (int i
= 0; i
< width
; i
++)
72 RTLIL::Const::Const(const std::vector
<bool> &bits
)
74 flags
= RTLIL::CONST_FLAG_NONE
;
76 this->bits
.push_back(b
? RTLIL::S1
: RTLIL::S0
);
79 RTLIL::Const::Const(const RTLIL::Const
&c
)
83 this->bits
.push_back(b
);
86 bool RTLIL::Const::operator <(const RTLIL::Const
&other
) const
88 if (bits
.size() != other
.bits
.size())
89 return bits
.size() < other
.bits
.size();
90 for (size_t i
= 0; i
< bits
.size(); i
++)
91 if (bits
[i
] != other
.bits
[i
])
92 return bits
[i
] < other
.bits
[i
];
96 bool RTLIL::Const::operator ==(const RTLIL::Const
&other
) const
98 return bits
== other
.bits
;
101 bool RTLIL::Const::operator !=(const RTLIL::Const
&other
) const
103 return bits
!= other
.bits
;
106 bool RTLIL::Const::as_bool() const
108 for (size_t i
= 0; i
< bits
.size(); i
++)
109 if (bits
[i
] == RTLIL::S1
)
114 int RTLIL::Const::as_int(bool is_signed
) const
117 for (size_t i
= 0; i
< bits
.size() && i
< 32; i
++)
118 if (bits
[i
] == RTLIL::S1
)
120 if (is_signed
&& bits
.back() == RTLIL::S1
)
121 for (size_t i
= bits
.size(); i
< 32; i
++)
126 std::string
RTLIL::Const::as_string() const
129 for (size_t i
= bits
.size(); i
> 0; i
--)
131 case S0
: ret
+= "0"; break;
132 case S1
: ret
+= "1"; break;
133 case Sx
: ret
+= "x"; break;
134 case Sz
: ret
+= "z"; break;
135 case Sa
: ret
+= "-"; break;
136 case Sm
: ret
+= "m"; break;
141 RTLIL::Const
RTLIL::Const::from_string(std::string str
)
144 for (auto it
= str
.rbegin(); it
!= str
.rend(); it
++)
146 case '0': c
.bits
.push_back(State::S0
); break;
147 case '1': c
.bits
.push_back(State::S1
); break;
148 case 'x': c
.bits
.push_back(State::Sx
); break;
149 case 'z': c
.bits
.push_back(State::Sz
); break;
150 case 'm': c
.bits
.push_back(State::Sm
); break;
151 default: c
.bits
.push_back(State::Sa
);
156 std::string
RTLIL::Const::decode_string() const
159 std::vector
<char> string_chars
;
160 for (int i
= 0; i
< int (bits
.size()); i
+= 8) {
162 for (int j
= 0; j
< 8 && i
+ j
< int (bits
.size()); j
++)
163 if (bits
[i
+ j
] == RTLIL::State::S1
)
166 string_chars
.push_back(ch
);
168 for (int i
= int (string_chars
.size()) - 1; i
>= 0; i
--)
169 string
+= string_chars
[i
];
173 bool RTLIL::Const::is_fully_zero() const
175 cover("kernel.rtlil.const.is_fully_zero");
177 for (auto bit
: bits
)
178 if (bit
!= RTLIL::State::S0
)
184 bool RTLIL::Const::is_fully_ones() const
186 cover("kernel.rtlil.const.is_fully_ones");
188 for (auto bit
: bits
)
189 if (bit
!= RTLIL::State::S1
)
195 bool RTLIL::Const::is_fully_def() const
197 cover("kernel.rtlil.const.is_fully_def");
199 for (auto bit
: bits
)
200 if (bit
!= RTLIL::State::S0
&& bit
!= RTLIL::State::S1
)
206 bool RTLIL::Const::is_fully_undef() const
208 cover("kernel.rtlil.const.is_fully_undef");
210 for (auto bit
: bits
)
211 if (bit
!= RTLIL::State::Sx
&& bit
!= RTLIL::State::Sz
)
217 void RTLIL::AttrObject::set_bool_attribute(RTLIL::IdString id
, bool value
)
220 attributes
[id
] = RTLIL::Const(1);
222 const auto it
= attributes
.find(id
);
223 if (it
!= attributes
.end())
224 attributes
.erase(it
);
228 bool RTLIL::AttrObject::get_bool_attribute(RTLIL::IdString id
) const
230 const auto it
= attributes
.find(id
);
231 if (it
== attributes
.end())
233 return it
->second
.as_bool();
236 void RTLIL::AttrObject::set_strpool_attribute(RTLIL::IdString id
, const pool
<string
> &data
)
239 for (auto &s
: data
) {
240 if (!attrval
.empty())
244 attributes
[id
] = RTLIL::Const(attrval
);
247 void RTLIL::AttrObject::add_strpool_attribute(RTLIL::IdString id
, const pool
<string
> &data
)
249 pool
<string
> union_data
= get_strpool_attribute(id
);
250 union_data
.insert(data
.begin(), data
.end());
251 if (!union_data
.empty())
252 set_strpool_attribute(id
, union_data
);
255 pool
<string
> RTLIL::AttrObject::get_strpool_attribute(RTLIL::IdString id
) const
258 if (attributes
.count(id
) != 0)
259 for (auto s
: split_tokens(attributes
.at(id
).decode_string(), "|"))
264 void RTLIL::AttrObject::set_src_attribute(const std::string
&src
)
267 attributes
.erase("\\src");
269 attributes
["\\src"] = src
;
272 std::string
RTLIL::AttrObject::get_src_attribute() const
275 if (attributes
.count("\\src"))
276 src
= attributes
.at("\\src").decode_string();
280 bool RTLIL::Selection::selected_module(RTLIL::IdString mod_name
) const
284 if (selected_modules
.count(mod_name
) > 0)
286 if (selected_members
.count(mod_name
) > 0)
291 bool RTLIL::Selection::selected_whole_module(RTLIL::IdString mod_name
) const
295 if (selected_modules
.count(mod_name
) > 0)
300 bool RTLIL::Selection::selected_member(RTLIL::IdString mod_name
, RTLIL::IdString memb_name
) const
304 if (selected_modules
.count(mod_name
) > 0)
306 if (selected_members
.count(mod_name
) > 0)
307 if (selected_members
.at(mod_name
).count(memb_name
) > 0)
312 void RTLIL::Selection::optimize(RTLIL::Design
*design
)
314 if (full_selection
) {
315 selected_modules
.clear();
316 selected_members
.clear();
320 std::vector
<RTLIL::IdString
> del_list
, add_list
;
323 for (auto mod_name
: selected_modules
) {
324 if (design
->modules_
.count(mod_name
) == 0)
325 del_list
.push_back(mod_name
);
326 selected_members
.erase(mod_name
);
328 for (auto mod_name
: del_list
)
329 selected_modules
.erase(mod_name
);
332 for (auto &it
: selected_members
)
333 if (design
->modules_
.count(it
.first
) == 0)
334 del_list
.push_back(it
.first
);
335 for (auto mod_name
: del_list
)
336 selected_members
.erase(mod_name
);
338 for (auto &it
: selected_members
) {
340 for (auto memb_name
: it
.second
)
341 if (design
->modules_
[it
.first
]->count_id(memb_name
) == 0)
342 del_list
.push_back(memb_name
);
343 for (auto memb_name
: del_list
)
344 it
.second
.erase(memb_name
);
349 for (auto &it
: selected_members
)
350 if (it
.second
.size() == 0)
351 del_list
.push_back(it
.first
);
352 else if (it
.second
.size() == design
->modules_
[it
.first
]->wires_
.size() + design
->modules_
[it
.first
]->memories
.size() +
353 design
->modules_
[it
.first
]->cells_
.size() + design
->modules_
[it
.first
]->processes
.size())
354 add_list
.push_back(it
.first
);
355 for (auto mod_name
: del_list
)
356 selected_members
.erase(mod_name
);
357 for (auto mod_name
: add_list
) {
358 selected_members
.erase(mod_name
);
359 selected_modules
.insert(mod_name
);
362 if (selected_modules
.size() == design
->modules_
.size()) {
363 full_selection
= true;
364 selected_modules
.clear();
365 selected_members
.clear();
369 RTLIL::Design::Design()
371 static unsigned int hashidx_count
= 123456789;
372 hashidx_count
= mkhash_xorshift(hashidx_count
);
373 hashidx_
= hashidx_count
;
375 refcount_modules_
= 0;
376 selection_stack
.push_back(RTLIL::Selection());
379 RTLIL::Design::get_all_designs()->insert(std::pair
<unsigned int, RTLIL::Design
*>(hashidx_
, this));
383 RTLIL::Design::~Design()
385 for (auto it
= modules_
.begin(); it
!= modules_
.end(); ++it
)
387 for (auto n
: verilog_packages
)
389 for (auto n
: verilog_globals
)
392 RTLIL::Design::get_all_designs()->erase(hashidx_
);
397 static std::map
<unsigned int, RTLIL::Design
*> all_designs
;
398 std::map
<unsigned int, RTLIL::Design
*> *RTLIL::Design::get_all_designs(void)
404 RTLIL::ObjRange
<RTLIL::Module
*> RTLIL::Design::modules()
406 return RTLIL::ObjRange
<RTLIL::Module
*>(&modules_
, &refcount_modules_
);
409 RTLIL::Module
*RTLIL::Design::module(RTLIL::IdString name
)
411 return modules_
.count(name
) ? modules_
.at(name
) : NULL
;
414 RTLIL::Module
*RTLIL::Design::top_module()
416 RTLIL::Module
*module
= nullptr;
417 int module_count
= 0;
419 for (auto mod
: selected_modules()) {
420 if (mod
->get_bool_attribute("\\top"))
426 return module_count
== 1 ? module
: nullptr;
429 void RTLIL::Design::add(RTLIL::Module
*module
)
431 log_assert(modules_
.count(module
->name
) == 0);
432 log_assert(refcount_modules_
== 0);
433 modules_
[module
->name
] = module
;
434 module
->design
= this;
436 for (auto mon
: monitors
)
437 mon
->notify_module_add(module
);
440 log("#X# New Module: %s\n", log_id(module
));
441 log_backtrace("-X- ", yosys_xtrace
-1);
445 RTLIL::Module
*RTLIL::Design::addModule(RTLIL::IdString name
)
447 log_assert(modules_
.count(name
) == 0);
448 log_assert(refcount_modules_
== 0);
450 RTLIL::Module
*module
= new RTLIL::Module
;
451 modules_
[name
] = module
;
452 module
->design
= this;
455 for (auto mon
: monitors
)
456 mon
->notify_module_add(module
);
459 log("#X# New Module: %s\n", log_id(module
));
460 log_backtrace("-X- ", yosys_xtrace
-1);
466 void RTLIL::Design::scratchpad_unset(std::string varname
)
468 scratchpad
.erase(varname
);
471 void RTLIL::Design::scratchpad_set_int(std::string varname
, int value
)
473 scratchpad
[varname
] = stringf("%d", value
);
476 void RTLIL::Design::scratchpad_set_bool(std::string varname
, bool value
)
478 scratchpad
[varname
] = value
? "true" : "false";
481 void RTLIL::Design::scratchpad_set_string(std::string varname
, std::string value
)
483 scratchpad
[varname
] = value
;
486 int RTLIL::Design::scratchpad_get_int(std::string varname
, int default_value
) const
488 if (scratchpad
.count(varname
) == 0)
489 return default_value
;
491 std::string str
= scratchpad
.at(varname
);
493 if (str
== "0" || str
== "false")
496 if (str
== "1" || str
== "true")
499 char *endptr
= nullptr;
500 long int parsed_value
= strtol(str
.c_str(), &endptr
, 10);
501 return *endptr
? default_value
: parsed_value
;
504 bool RTLIL::Design::scratchpad_get_bool(std::string varname
, bool default_value
) const
506 if (scratchpad
.count(varname
) == 0)
507 return default_value
;
509 std::string str
= scratchpad
.at(varname
);
511 if (str
== "0" || str
== "false")
514 if (str
== "1" || str
== "true")
517 return default_value
;
520 std::string
RTLIL::Design::scratchpad_get_string(std::string varname
, std::string default_value
) const
522 if (scratchpad
.count(varname
) == 0)
523 return default_value
;
524 return scratchpad
.at(varname
);
527 void RTLIL::Design::remove(RTLIL::Module
*module
)
529 for (auto mon
: monitors
)
530 mon
->notify_module_del(module
);
533 log("#X# Remove Module: %s\n", log_id(module
));
534 log_backtrace("-X- ", yosys_xtrace
-1);
537 log_assert(modules_
.at(module
->name
) == module
);
538 modules_
.erase(module
->name
);
542 void RTLIL::Design::rename(RTLIL::Module
*module
, RTLIL::IdString new_name
)
544 modules_
.erase(module
->name
);
545 module
->name
= new_name
;
549 void RTLIL::Design::sort()
552 modules_
.sort(sort_by_id_str());
553 for (auto &it
: modules_
)
557 void RTLIL::Design::check()
560 for (auto &it
: modules_
) {
561 log_assert(this == it
.second
->design
);
562 log_assert(it
.first
== it
.second
->name
);
563 log_assert(!it
.first
.empty());
569 void RTLIL::Design::optimize()
571 for (auto &it
: modules_
)
572 it
.second
->optimize();
573 for (auto &it
: selection_stack
)
575 for (auto &it
: selection_vars
)
576 it
.second
.optimize(this);
579 bool RTLIL::Design::selected_module(RTLIL::IdString mod_name
) const
581 if (!selected_active_module
.empty() && mod_name
!= selected_active_module
)
583 if (selection_stack
.size() == 0)
585 return selection_stack
.back().selected_module(mod_name
);
588 bool RTLIL::Design::selected_whole_module(RTLIL::IdString mod_name
) const
590 if (!selected_active_module
.empty() && mod_name
!= selected_active_module
)
592 if (selection_stack
.size() == 0)
594 return selection_stack
.back().selected_whole_module(mod_name
);
597 bool RTLIL::Design::selected_member(RTLIL::IdString mod_name
, RTLIL::IdString memb_name
) const
599 if (!selected_active_module
.empty() && mod_name
!= selected_active_module
)
601 if (selection_stack
.size() == 0)
603 return selection_stack
.back().selected_member(mod_name
, memb_name
);
606 bool RTLIL::Design::selected_module(RTLIL::Module
*mod
) const
608 return selected_module(mod
->name
);
611 bool RTLIL::Design::selected_whole_module(RTLIL::Module
*mod
) const
613 return selected_whole_module(mod
->name
);
616 std::vector
<RTLIL::Module
*> RTLIL::Design::selected_modules() const
618 std::vector
<RTLIL::Module
*> result
;
619 result
.reserve(modules_
.size());
620 for (auto &it
: modules_
)
621 if (selected_module(it
.first
) && !it
.second
->get_blackbox_attribute())
622 result
.push_back(it
.second
);
626 std::vector
<RTLIL::Module
*> RTLIL::Design::selected_whole_modules() const
628 std::vector
<RTLIL::Module
*> result
;
629 result
.reserve(modules_
.size());
630 for (auto &it
: modules_
)
631 if (selected_whole_module(it
.first
) && !it
.second
->get_blackbox_attribute())
632 result
.push_back(it
.second
);
636 std::vector
<RTLIL::Module
*> RTLIL::Design::selected_whole_modules_warn() const
638 std::vector
<RTLIL::Module
*> result
;
639 result
.reserve(modules_
.size());
640 for (auto &it
: modules_
)
641 if (it
.second
->get_blackbox_attribute())
643 else if (selected_whole_module(it
.first
))
644 result
.push_back(it
.second
);
645 else if (selected_module(it
.first
))
646 log_warning("Ignoring partially selected module %s.\n", log_id(it
.first
));
650 RTLIL::Module::Module()
652 static unsigned int hashidx_count
= 123456789;
653 hashidx_count
= mkhash_xorshift(hashidx_count
);
654 hashidx_
= hashidx_count
;
661 RTLIL::Module::get_all_modules()->insert(std::pair
<unsigned int, RTLIL::Module
*>(hashidx_
, this));
665 RTLIL::Module::~Module()
667 for (auto it
= wires_
.begin(); it
!= wires_
.end(); ++it
)
669 for (auto it
= memories
.begin(); it
!= memories
.end(); ++it
)
671 for (auto it
= cells_
.begin(); it
!= cells_
.end(); ++it
)
673 for (auto it
= processes
.begin(); it
!= processes
.end(); ++it
)
676 RTLIL::Module::get_all_modules()->erase(hashidx_
);
681 static std::map
<unsigned int, RTLIL::Module
*> all_modules
;
682 std::map
<unsigned int, RTLIL::Module
*> *RTLIL::Module::get_all_modules(void)
688 void RTLIL::Module::makeblackbox()
690 pool
<RTLIL::Wire
*> delwires
;
692 for (auto it
= wires_
.begin(); it
!= wires_
.end(); ++it
)
693 if (!it
->second
->port_input
&& !it
->second
->port_output
)
694 delwires
.insert(it
->second
);
696 for (auto it
= memories
.begin(); it
!= memories
.end(); ++it
)
700 for (auto it
= cells_
.begin(); it
!= cells_
.end(); ++it
)
704 for (auto it
= processes
.begin(); it
!= processes
.end(); ++it
)
709 set_bool_attribute("\\blackbox");
712 void RTLIL::Module::reprocess_module(RTLIL::Design
*, dict
<RTLIL::IdString
, RTLIL::Module
*>)
714 log_error("Cannot reprocess_module module `%s' !\n", id2cstr(name
));
717 RTLIL::IdString
RTLIL::Module::derive(RTLIL::Design
*, dict
<RTLIL::IdString
, RTLIL::Const
>, bool mayfail
)
720 return RTLIL::IdString();
721 log_error("Module `%s' is used with parameters but is not parametric!\n", id2cstr(name
));
725 RTLIL::IdString
RTLIL::Module::derive(RTLIL::Design
*, dict
<RTLIL::IdString
, RTLIL::Const
>, dict
<RTLIL::IdString
, RTLIL::Module
*>, dict
<RTLIL::IdString
, RTLIL::IdString
>, bool mayfail
)
728 return RTLIL::IdString();
729 log_error("Module `%s' is used with parameters but is not parametric!\n", id2cstr(name
));
732 size_t RTLIL::Module::count_id(RTLIL::IdString id
)
734 return wires_
.count(id
) + memories
.count(id
) + cells_
.count(id
) + processes
.count(id
);
739 struct InternalCellChecker
741 RTLIL::Module
*module
;
743 pool
<RTLIL::IdString
> expected_params
, expected_ports
;
745 InternalCellChecker(RTLIL::Module
*module
, RTLIL::Cell
*cell
) : module(module
), cell(cell
) { }
747 void error(int linenr
)
749 std::stringstream buf
;
750 ILANG_BACKEND::dump_cell(buf
, " ", cell
);
752 log_error("Found error in internal cell %s%s%s (%s) at %s:%d:\n%s",
753 module
? module
->name
.c_str() : "", module
? "." : "",
754 cell
->name
.c_str(), cell
->type
.c_str(), __FILE__
, linenr
, buf
.str().c_str());
757 int param(const char *name
)
759 if (cell
->parameters
.count(name
) == 0)
761 expected_params
.insert(name
);
762 return cell
->parameters
.at(name
).as_int();
765 int param_bool(const char *name
)
768 if (cell
->parameters
.at(name
).bits
.size() > 32)
770 if (v
!= 0 && v
!= 1)
775 void param_bits(const char *name
, int width
)
778 if (int(cell
->parameters
.at(name
).bits
.size()) != width
)
782 void port(const char *name
, int width
)
784 if (!cell
->hasPort(name
))
786 if (cell
->getPort(name
).size() != width
)
788 expected_ports
.insert(name
);
791 void check_expected(bool check_matched_sign
= true)
793 for (auto ¶
: cell
->parameters
)
794 if (expected_params
.count(para
.first
) == 0)
796 for (auto &conn
: cell
->connections())
797 if (expected_ports
.count(conn
.first
) == 0)
800 if (expected_params
.count("\\A_SIGNED") != 0 && expected_params
.count("\\B_SIGNED") && check_matched_sign
) {
801 bool a_is_signed
= param("\\A_SIGNED") != 0;
802 bool b_is_signed
= param("\\B_SIGNED") != 0;
803 if (a_is_signed
!= b_is_signed
)
808 void check_gate(const char *ports
)
810 if (cell
->parameters
.size() != 0)
813 for (const char *p
= ports
; *p
; p
++) {
814 char portname
[3] = { '\\', *p
, 0 };
815 if (!cell
->hasPort(portname
))
817 if (cell
->getPort(portname
).size() != 1)
821 for (auto &conn
: cell
->connections()) {
822 if (conn
.first
.size() != 2 || conn
.first
[0] != '\\')
824 if (strchr(ports
, conn
.first
[1]) == NULL
)
831 if (cell
->type
.substr(0, 1) != "$" || cell
->type
.substr(0, 3) == "$__" || cell
->type
.substr(0, 8) == "$paramod" || cell
->type
.substr(0,10) == "$fmcombine" ||
832 cell
->type
.substr(0, 9) == "$verific$" || cell
->type
.substr(0, 7) == "$array:" || cell
->type
.substr(0, 8) == "$extern:")
835 if (cell
->type
.in("$not", "$pos", "$neg")) {
836 param_bool("\\A_SIGNED");
837 port("\\A", param("\\A_WIDTH"));
838 port("\\Y", param("\\Y_WIDTH"));
843 if (cell
->type
.in("$and", "$or", "$xor", "$xnor")) {
844 param_bool("\\A_SIGNED");
845 param_bool("\\B_SIGNED");
846 port("\\A", param("\\A_WIDTH"));
847 port("\\B", param("\\B_WIDTH"));
848 port("\\Y", param("\\Y_WIDTH"));
853 if (cell
->type
.in("$reduce_and", "$reduce_or", "$reduce_xor", "$reduce_xnor", "$reduce_bool")) {
854 param_bool("\\A_SIGNED");
855 port("\\A", param("\\A_WIDTH"));
856 port("\\Y", param("\\Y_WIDTH"));
861 if (cell
->type
.in("$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx")) {
862 param_bool("\\A_SIGNED");
863 param_bool("\\B_SIGNED");
864 port("\\A", param("\\A_WIDTH"));
865 port("\\B", param("\\B_WIDTH"));
866 port("\\Y", param("\\Y_WIDTH"));
867 check_expected(false);
871 if (cell
->type
.in("$lt", "$le", "$eq", "$ne", "$eqx", "$nex", "$ge", "$gt")) {
872 param_bool("\\A_SIGNED");
873 param_bool("\\B_SIGNED");
874 port("\\A", param("\\A_WIDTH"));
875 port("\\B", param("\\B_WIDTH"));
876 port("\\Y", param("\\Y_WIDTH"));
881 if (cell
->type
.in("$add", "$sub", "$mul", "$div", "$mod", "$pow")) {
882 param_bool("\\A_SIGNED");
883 param_bool("\\B_SIGNED");
884 port("\\A", param("\\A_WIDTH"));
885 port("\\B", param("\\B_WIDTH"));
886 port("\\Y", param("\\Y_WIDTH"));
887 check_expected(cell
->type
!= "$pow");
891 if (cell
->type
== "$fa") {
892 port("\\A", param("\\WIDTH"));
893 port("\\B", param("\\WIDTH"));
894 port("\\C", param("\\WIDTH"));
895 port("\\X", param("\\WIDTH"));
896 port("\\Y", param("\\WIDTH"));
901 if (cell
->type
== "$lcu") {
902 port("\\P", param("\\WIDTH"));
903 port("\\G", param("\\WIDTH"));
905 port("\\CO", param("\\WIDTH"));
910 if (cell
->type
== "$alu") {
911 param_bool("\\A_SIGNED");
912 param_bool("\\B_SIGNED");
913 port("\\A", param("\\A_WIDTH"));
914 port("\\B", param("\\B_WIDTH"));
917 port("\\X", param("\\Y_WIDTH"));
918 port("\\Y", param("\\Y_WIDTH"));
919 port("\\CO", param("\\Y_WIDTH"));
924 if (cell
->type
== "$macc") {
926 param("\\CONFIG_WIDTH");
927 port("\\A", param("\\A_WIDTH"));
928 port("\\B", param("\\B_WIDTH"));
929 port("\\Y", param("\\Y_WIDTH"));
931 Macc().from_cell(cell
);
935 if (cell
->type
== "$logic_not") {
936 param_bool("\\A_SIGNED");
937 port("\\A", param("\\A_WIDTH"));
938 port("\\Y", param("\\Y_WIDTH"));
943 if (cell
->type
== "$logic_and" || cell
->type
== "$logic_or") {
944 param_bool("\\A_SIGNED");
945 param_bool("\\B_SIGNED");
946 port("\\A", param("\\A_WIDTH"));
947 port("\\B", param("\\B_WIDTH"));
948 port("\\Y", param("\\Y_WIDTH"));
949 check_expected(false);
953 if (cell
->type
== "$slice") {
955 port("\\A", param("\\A_WIDTH"));
956 port("\\Y", param("\\Y_WIDTH"));
957 if (param("\\OFFSET") + param("\\Y_WIDTH") > param("\\A_WIDTH"))
963 if (cell
->type
== "$concat") {
964 port("\\A", param("\\A_WIDTH"));
965 port("\\B", param("\\B_WIDTH"));
966 port("\\Y", param("\\A_WIDTH") + param("\\B_WIDTH"));
971 if (cell
->type
== "$mux") {
972 port("\\A", param("\\WIDTH"));
973 port("\\B", param("\\WIDTH"));
975 port("\\Y", param("\\WIDTH"));
980 if (cell
->type
== "$pmux") {
981 port("\\A", param("\\WIDTH"));
982 port("\\B", param("\\WIDTH") * param("\\S_WIDTH"));
983 port("\\S", param("\\S_WIDTH"));
984 port("\\Y", param("\\WIDTH"));
989 if (cell
->type
== "$lut") {
991 port("\\A", param("\\WIDTH"));
997 if (cell
->type
== "$sop") {
1000 port("\\A", param("\\WIDTH"));
1006 if (cell
->type
== "$sr") {
1007 param_bool("\\SET_POLARITY");
1008 param_bool("\\CLR_POLARITY");
1009 port("\\SET", param("\\WIDTH"));
1010 port("\\CLR", param("\\WIDTH"));
1011 port("\\Q", param("\\WIDTH"));
1016 if (cell
->type
== "$ff") {
1017 port("\\D", param("\\WIDTH"));
1018 port("\\Q", param("\\WIDTH"));
1023 if (cell
->type
== "$dff") {
1024 param_bool("\\CLK_POLARITY");
1026 port("\\D", param("\\WIDTH"));
1027 port("\\Q", param("\\WIDTH"));
1032 if (cell
->type
== "$dffe") {
1033 param_bool("\\CLK_POLARITY");
1034 param_bool("\\EN_POLARITY");
1037 port("\\D", param("\\WIDTH"));
1038 port("\\Q", param("\\WIDTH"));
1043 if (cell
->type
== "$dffsr") {
1044 param_bool("\\CLK_POLARITY");
1045 param_bool("\\SET_POLARITY");
1046 param_bool("\\CLR_POLARITY");
1048 port("\\SET", param("\\WIDTH"));
1049 port("\\CLR", param("\\WIDTH"));
1050 port("\\D", param("\\WIDTH"));
1051 port("\\Q", param("\\WIDTH"));
1056 if (cell
->type
== "$adff") {
1057 param_bool("\\CLK_POLARITY");
1058 param_bool("\\ARST_POLARITY");
1059 param_bits("\\ARST_VALUE", param("\\WIDTH"));
1062 port("\\D", param("\\WIDTH"));
1063 port("\\Q", param("\\WIDTH"));
1068 if (cell
->type
== "$dlatch") {
1069 param_bool("\\EN_POLARITY");
1071 port("\\D", param("\\WIDTH"));
1072 port("\\Q", param("\\WIDTH"));
1077 if (cell
->type
== "$dlatchsr") {
1078 param_bool("\\EN_POLARITY");
1079 param_bool("\\SET_POLARITY");
1080 param_bool("\\CLR_POLARITY");
1082 port("\\SET", param("\\WIDTH"));
1083 port("\\CLR", param("\\WIDTH"));
1084 port("\\D", param("\\WIDTH"));
1085 port("\\Q", param("\\WIDTH"));
1090 if (cell
->type
== "$fsm") {
1092 param_bool("\\CLK_POLARITY");
1093 param_bool("\\ARST_POLARITY");
1094 param("\\STATE_BITS");
1095 param("\\STATE_NUM");
1096 param("\\STATE_NUM_LOG2");
1097 param("\\STATE_RST");
1098 param_bits("\\STATE_TABLE", param("\\STATE_BITS") * param("\\STATE_NUM"));
1099 param("\\TRANS_NUM");
1100 param_bits("\\TRANS_TABLE", param("\\TRANS_NUM") * (2*param("\\STATE_NUM_LOG2") + param("\\CTRL_IN_WIDTH") + param("\\CTRL_OUT_WIDTH")));
1103 port("\\CTRL_IN", param("\\CTRL_IN_WIDTH"));
1104 port("\\CTRL_OUT", param("\\CTRL_OUT_WIDTH"));
1109 if (cell
->type
== "$memrd") {
1111 param_bool("\\CLK_ENABLE");
1112 param_bool("\\CLK_POLARITY");
1113 param_bool("\\TRANSPARENT");
1116 port("\\ADDR", param("\\ABITS"));
1117 port("\\DATA", param("\\WIDTH"));
1122 if (cell
->type
== "$memwr") {
1124 param_bool("\\CLK_ENABLE");
1125 param_bool("\\CLK_POLARITY");
1126 param("\\PRIORITY");
1128 port("\\EN", param("\\WIDTH"));
1129 port("\\ADDR", param("\\ABITS"));
1130 port("\\DATA", param("\\WIDTH"));
1135 if (cell
->type
== "$meminit") {
1137 param("\\PRIORITY");
1138 port("\\ADDR", param("\\ABITS"));
1139 port("\\DATA", param("\\WIDTH") * param("\\WORDS"));
1144 if (cell
->type
== "$mem") {
1149 param_bits("\\RD_CLK_ENABLE", max(1, param("\\RD_PORTS")));
1150 param_bits("\\RD_CLK_POLARITY", max(1, param("\\RD_PORTS")));
1151 param_bits("\\RD_TRANSPARENT", max(1, param("\\RD_PORTS")));
1152 param_bits("\\WR_CLK_ENABLE", max(1, param("\\WR_PORTS")));
1153 param_bits("\\WR_CLK_POLARITY", max(1, param("\\WR_PORTS")));
1154 port("\\RD_CLK", param("\\RD_PORTS"));
1155 port("\\RD_EN", param("\\RD_PORTS"));
1156 port("\\RD_ADDR", param("\\RD_PORTS") * param("\\ABITS"));
1157 port("\\RD_DATA", param("\\RD_PORTS") * param("\\WIDTH"));
1158 port("\\WR_CLK", param("\\WR_PORTS"));
1159 port("\\WR_EN", param("\\WR_PORTS") * param("\\WIDTH"));
1160 port("\\WR_ADDR", param("\\WR_PORTS") * param("\\ABITS"));
1161 port("\\WR_DATA", param("\\WR_PORTS") * param("\\WIDTH"));
1166 if (cell
->type
== "$tribuf") {
1167 port("\\A", param("\\WIDTH"));
1168 port("\\Y", param("\\WIDTH"));
1174 if (cell
->type
.in("$assert", "$assume", "$live", "$fair", "$cover")) {
1181 if (cell
->type
== "$initstate") {
1187 if (cell
->type
.in("$anyconst", "$anyseq", "$allconst", "$allseq")) {
1188 port("\\Y", param("\\WIDTH"));
1193 if (cell
->type
== "$equiv") {
1201 if (cell
->type
.in("$specify2", "$specify3")) {
1202 param_bool("\\FULL");
1203 param_bool("\\SRC_DST_PEN");
1204 param_bool("\\SRC_DST_POL");
1205 param("\\T_RISE_MIN");
1206 param("\\T_RISE_TYP");
1207 param("\\T_RISE_MAX");
1208 param("\\T_FALL_MIN");
1209 param("\\T_FALL_TYP");
1210 param("\\T_FALL_MAX");
1212 port("\\SRC", param("\\SRC_WIDTH"));
1213 port("\\DST", param("\\DST_WIDTH"));
1214 if (cell
->type
== "$specify3") {
1215 param_bool("\\EDGE_EN");
1216 param_bool("\\EDGE_POL");
1217 param_bool("\\DAT_DST_PEN");
1218 param_bool("\\DAT_DST_POL");
1219 port("\\DAT", param("\\DST_WIDTH"));
1225 if (cell
->type
== "$specrule") {
1227 param_bool("\\SRC_PEN");
1228 param_bool("\\SRC_POL");
1229 param_bool("\\DST_PEN");
1230 param_bool("\\DST_POL");
1232 param("\\T_LIMIT2");
1233 port("\\SRC_EN", 1);
1234 port("\\DST_EN", 1);
1235 port("\\SRC", param("\\SRC_WIDTH"));
1236 port("\\DST", param("\\DST_WIDTH"));
1241 if (cell
->type
== "$_BUF_") { check_gate("AY"); return; }
1242 if (cell
->type
== "$_NOT_") { check_gate("AY"); return; }
1243 if (cell
->type
== "$_AND_") { check_gate("ABY"); return; }
1244 if (cell
->type
== "$_NAND_") { check_gate("ABY"); return; }
1245 if (cell
->type
== "$_OR_") { check_gate("ABY"); return; }
1246 if (cell
->type
== "$_NOR_") { check_gate("ABY"); return; }
1247 if (cell
->type
== "$_XOR_") { check_gate("ABY"); return; }
1248 if (cell
->type
== "$_XNOR_") { check_gate("ABY"); return; }
1249 if (cell
->type
== "$_ANDNOT_") { check_gate("ABY"); return; }
1250 if (cell
->type
== "$_ORNOT_") { check_gate("ABY"); return; }
1251 if (cell
->type
== "$_MUX_") { check_gate("ABSY"); return; }
1252 if (cell
->type
== "$_AOI3_") { check_gate("ABCY"); return; }
1253 if (cell
->type
== "$_OAI3_") { check_gate("ABCY"); return; }
1254 if (cell
->type
== "$_AOI4_") { check_gate("ABCDY"); return; }
1255 if (cell
->type
== "$_OAI4_") { check_gate("ABCDY"); return; }
1257 if (cell
->type
== "$_TBUF_") { check_gate("AYE"); return; }
1259 if (cell
->type
== "$_MUX4_") { check_gate("ABCDSTY"); return; }
1260 if (cell
->type
== "$_MUX8_") { check_gate("ABCDEFGHSTUY"); return; }
1261 if (cell
->type
== "$_MUX16_") { check_gate("ABCDEFGHIJKLMNOPSTUVY"); return; }
1263 if (cell
->type
== "$_SR_NN_") { check_gate("SRQ"); return; }
1264 if (cell
->type
== "$_SR_NP_") { check_gate("SRQ"); return; }
1265 if (cell
->type
== "$_SR_PN_") { check_gate("SRQ"); return; }
1266 if (cell
->type
== "$_SR_PP_") { check_gate("SRQ"); return; }
1268 if (cell
->type
== "$_FF_") { check_gate("DQ"); return; }
1269 if (cell
->type
== "$_DFF_N_") { check_gate("DQC"); return; }
1270 if (cell
->type
== "$_DFF_P_") { check_gate("DQC"); return; }
1272 if (cell
->type
== "$_DFFE_NN_") { check_gate("DQCE"); return; }
1273 if (cell
->type
== "$_DFFE_NP_") { check_gate("DQCE"); return; }
1274 if (cell
->type
== "$_DFFE_PN_") { check_gate("DQCE"); return; }
1275 if (cell
->type
== "$_DFFE_PP_") { check_gate("DQCE"); return; }
1277 if (cell
->type
== "$_DFF_NN0_") { check_gate("DQCR"); return; }
1278 if (cell
->type
== "$_DFF_NN1_") { check_gate("DQCR"); return; }
1279 if (cell
->type
== "$_DFF_NP0_") { check_gate("DQCR"); return; }
1280 if (cell
->type
== "$_DFF_NP1_") { check_gate("DQCR"); return; }
1281 if (cell
->type
== "$_DFF_PN0_") { check_gate("DQCR"); return; }
1282 if (cell
->type
== "$_DFF_PN1_") { check_gate("DQCR"); return; }
1283 if (cell
->type
== "$_DFF_PP0_") { check_gate("DQCR"); return; }
1284 if (cell
->type
== "$_DFF_PP1_") { check_gate("DQCR"); return; }
1286 if (cell
->type
== "$_DFFSR_NNN_") { check_gate("CSRDQ"); return; }
1287 if (cell
->type
== "$_DFFSR_NNP_") { check_gate("CSRDQ"); return; }
1288 if (cell
->type
== "$_DFFSR_NPN_") { check_gate("CSRDQ"); return; }
1289 if (cell
->type
== "$_DFFSR_NPP_") { check_gate("CSRDQ"); return; }
1290 if (cell
->type
== "$_DFFSR_PNN_") { check_gate("CSRDQ"); return; }
1291 if (cell
->type
== "$_DFFSR_PNP_") { check_gate("CSRDQ"); return; }
1292 if (cell
->type
== "$_DFFSR_PPN_") { check_gate("CSRDQ"); return; }
1293 if (cell
->type
== "$_DFFSR_PPP_") { check_gate("CSRDQ"); return; }
1295 if (cell
->type
== "$_DLATCH_N_") { check_gate("EDQ"); return; }
1296 if (cell
->type
== "$_DLATCH_P_") { check_gate("EDQ"); return; }
1298 if (cell
->type
== "$_DLATCHSR_NNN_") { check_gate("ESRDQ"); return; }
1299 if (cell
->type
== "$_DLATCHSR_NNP_") { check_gate("ESRDQ"); return; }
1300 if (cell
->type
== "$_DLATCHSR_NPN_") { check_gate("ESRDQ"); return; }
1301 if (cell
->type
== "$_DLATCHSR_NPP_") { check_gate("ESRDQ"); return; }
1302 if (cell
->type
== "$_DLATCHSR_PNN_") { check_gate("ESRDQ"); return; }
1303 if (cell
->type
== "$_DLATCHSR_PNP_") { check_gate("ESRDQ"); return; }
1304 if (cell
->type
== "$_DLATCHSR_PPN_") { check_gate("ESRDQ"); return; }
1305 if (cell
->type
== "$_DLATCHSR_PPP_") { check_gate("ESRDQ"); return; }
1313 void RTLIL::Module::sort()
1315 wires_
.sort(sort_by_id_str());
1316 cells_
.sort(sort_by_id_str());
1317 avail_parameters
.sort(sort_by_id_str());
1318 memories
.sort(sort_by_id_str());
1319 processes
.sort(sort_by_id_str());
1320 for (auto &it
: cells_
)
1322 for (auto &it
: wires_
)
1323 it
.second
->attributes
.sort(sort_by_id_str());
1324 for (auto &it
: memories
)
1325 it
.second
->attributes
.sort(sort_by_id_str());
1328 void RTLIL::Module::check()
1331 std::vector
<bool> ports_declared
;
1332 for (auto &it
: wires_
) {
1333 log_assert(this == it
.second
->module
);
1334 log_assert(it
.first
== it
.second
->name
);
1335 log_assert(!it
.first
.empty());
1336 log_assert(it
.second
->width
>= 0);
1337 log_assert(it
.second
->port_id
>= 0);
1338 for (auto &it2
: it
.second
->attributes
)
1339 log_assert(!it2
.first
.empty());
1340 if (it
.second
->port_id
) {
1341 log_assert(GetSize(ports
) >= it
.second
->port_id
);
1342 log_assert(ports
.at(it
.second
->port_id
-1) == it
.first
);
1343 log_assert(it
.second
->port_input
|| it
.second
->port_output
);
1344 if (GetSize(ports_declared
) < it
.second
->port_id
)
1345 ports_declared
.resize(it
.second
->port_id
);
1346 log_assert(ports_declared
[it
.second
->port_id
-1] == false);
1347 ports_declared
[it
.second
->port_id
-1] = true;
1349 log_assert(!it
.second
->port_input
&& !it
.second
->port_output
);
1351 for (auto port_declared
: ports_declared
)
1352 log_assert(port_declared
== true);
1353 log_assert(GetSize(ports
) == GetSize(ports_declared
));
1355 for (auto &it
: memories
) {
1356 log_assert(it
.first
== it
.second
->name
);
1357 log_assert(!it
.first
.empty());
1358 log_assert(it
.second
->width
>= 0);
1359 log_assert(it
.second
->size
>= 0);
1360 for (auto &it2
: it
.second
->attributes
)
1361 log_assert(!it2
.first
.empty());
1364 for (auto &it
: cells_
) {
1365 log_assert(this == it
.second
->module
);
1366 log_assert(it
.first
== it
.second
->name
);
1367 log_assert(!it
.first
.empty());
1368 log_assert(!it
.second
->type
.empty());
1369 for (auto &it2
: it
.second
->connections()) {
1370 log_assert(!it2
.first
.empty());
1373 for (auto &it2
: it
.second
->attributes
)
1374 log_assert(!it2
.first
.empty());
1375 for (auto &it2
: it
.second
->parameters
)
1376 log_assert(!it2
.first
.empty());
1377 InternalCellChecker
checker(this, it
.second
);
1381 for (auto &it
: processes
) {
1382 log_assert(it
.first
== it
.second
->name
);
1383 log_assert(!it
.first
.empty());
1384 log_assert(it
.second
->root_case
.compare
.empty());
1385 std::vector
<CaseRule
*> all_cases
= {&it
.second
->root_case
};
1386 for (size_t i
= 0; i
< all_cases
.size(); i
++) {
1387 for (auto &switch_it
: all_cases
[i
]->switches
) {
1388 for (auto &case_it
: switch_it
->cases
) {
1389 for (auto &compare_it
: case_it
->compare
) {
1390 log_assert(switch_it
->signal
.size() == compare_it
.size());
1392 all_cases
.push_back(case_it
);
1396 for (auto &sync_it
: it
.second
->syncs
) {
1397 switch (sync_it
->type
) {
1403 log_assert(!sync_it
->signal
.empty());
1408 log_assert(sync_it
->signal
.empty());
1414 for (auto &it
: connections_
) {
1415 log_assert(it
.first
.size() == it
.second
.size());
1416 log_assert(!it
.first
.has_const());
1421 for (auto &it
: attributes
)
1422 log_assert(!it
.first
.empty());
1426 void RTLIL::Module::optimize()
1430 void RTLIL::Module::cloneInto(RTLIL::Module
*new_mod
) const
1432 log_assert(new_mod
->refcount_wires_
== 0);
1433 log_assert(new_mod
->refcount_cells_
== 0);
1435 new_mod
->avail_parameters
= avail_parameters
;
1437 for (auto &conn
: connections_
)
1438 new_mod
->connect(conn
);
1440 for (auto &attr
: attributes
)
1441 new_mod
->attributes
[attr
.first
] = attr
.second
;
1443 for (auto &it
: wires_
)
1444 new_mod
->addWire(it
.first
, it
.second
);
1446 for (auto &it
: memories
)
1447 new_mod
->memories
[it
.first
] = new RTLIL::Memory(*it
.second
);
1449 for (auto &it
: cells_
)
1450 new_mod
->addCell(it
.first
, it
.second
);
1452 for (auto &it
: processes
)
1453 new_mod
->processes
[it
.first
] = it
.second
->clone();
1455 struct RewriteSigSpecWorker
1458 void operator()(RTLIL::SigSpec
&sig
)
1460 std::vector
<RTLIL::SigChunk
> chunks
= sig
.chunks();
1461 for (auto &c
: chunks
)
1463 c
.wire
= mod
->wires_
.at(c
.wire
->name
);
1468 RewriteSigSpecWorker rewriteSigSpecWorker
;
1469 rewriteSigSpecWorker
.mod
= new_mod
;
1470 new_mod
->rewrite_sigspecs(rewriteSigSpecWorker
);
1471 new_mod
->fixup_ports();
1474 RTLIL::Module
*RTLIL::Module::clone() const
1476 RTLIL::Module
*new_mod
= new RTLIL::Module
;
1477 new_mod
->name
= name
;
1482 bool RTLIL::Module::has_memories() const
1484 return !memories
.empty();
1487 bool RTLIL::Module::has_processes() const
1489 return !processes
.empty();
1492 bool RTLIL::Module::has_memories_warn() const
1494 if (!memories
.empty())
1495 log_warning("Ignoring module %s because it contains memories (run 'memory' command first).\n", log_id(this));
1496 return !memories
.empty();
1499 bool RTLIL::Module::has_processes_warn() const
1501 if (!processes
.empty())
1502 log_warning("Ignoring module %s because it contains processes (run 'proc' command first).\n", log_id(this));
1503 return !processes
.empty();
1506 std::vector
<RTLIL::Wire
*> RTLIL::Module::selected_wires() const
1508 std::vector
<RTLIL::Wire
*> result
;
1509 result
.reserve(wires_
.size());
1510 for (auto &it
: wires_
)
1511 if (design
->selected(this, it
.second
))
1512 result
.push_back(it
.second
);
1516 std::vector
<RTLIL::Cell
*> RTLIL::Module::selected_cells() const
1518 std::vector
<RTLIL::Cell
*> result
;
1519 result
.reserve(wires_
.size());
1520 for (auto &it
: cells_
)
1521 if (design
->selected(this, it
.second
))
1522 result
.push_back(it
.second
);
1526 void RTLIL::Module::add(RTLIL::Wire
*wire
)
1528 log_assert(!wire
->name
.empty());
1529 log_assert(count_id(wire
->name
) == 0);
1530 log_assert(refcount_wires_
== 0);
1531 wires_
[wire
->name
] = wire
;
1532 wire
->module
= this;
1535 void RTLIL::Module::add(RTLIL::Cell
*cell
)
1537 log_assert(!cell
->name
.empty());
1538 log_assert(count_id(cell
->name
) == 0);
1539 log_assert(refcount_cells_
== 0);
1540 cells_
[cell
->name
] = cell
;
1541 cell
->module
= this;
1544 void RTLIL::Module::remove(const pool
<RTLIL::Wire
*> &wires
)
1546 log_assert(refcount_wires_
== 0);
1548 struct DeleteWireWorker
1550 RTLIL::Module
*module
;
1551 const pool
<RTLIL::Wire
*> *wires_p
;
1553 void operator()(RTLIL::SigSpec
&sig
) {
1554 std::vector
<RTLIL::SigChunk
> chunks
= sig
;
1555 for (auto &c
: chunks
)
1556 if (c
.wire
!= NULL
&& wires_p
->count(c
.wire
)) {
1557 c
.wire
= module
->addWire(NEW_ID
, c
.width
);
1563 void operator()(RTLIL::SigSpec
&lhs
, RTLIL::SigSpec
&rhs
) {
1564 log_assert(GetSize(lhs
) == GetSize(rhs
));
1565 RTLIL::SigSpec new_lhs
, new_rhs
;
1566 for (int i
= 0; i
< GetSize(lhs
); i
++) {
1567 RTLIL::SigBit lhs_bit
= lhs
[i
];
1568 if (lhs_bit
.wire
!= nullptr && wires_p
->count(lhs_bit
.wire
))
1570 RTLIL::SigBit rhs_bit
= rhs
[i
];
1571 if (rhs_bit
.wire
!= nullptr && wires_p
->count(rhs_bit
.wire
))
1573 new_lhs
.append(lhs_bit
);
1574 new_rhs
.append(rhs_bit
);
1581 DeleteWireWorker delete_wire_worker
;
1582 delete_wire_worker
.module
= this;
1583 delete_wire_worker
.wires_p
= &wires
;
1584 rewrite_sigspecs2(delete_wire_worker
);
1586 for (auto &it
: wires
) {
1587 log_assert(wires_
.count(it
->name
) != 0);
1588 wires_
.erase(it
->name
);
1593 void RTLIL::Module::remove(RTLIL::Cell
*cell
)
1595 while (!cell
->connections_
.empty())
1596 cell
->unsetPort(cell
->connections_
.begin()->first
);
1598 log_assert(cells_
.count(cell
->name
) != 0);
1599 log_assert(refcount_cells_
== 0);
1600 cells_
.erase(cell
->name
);
1604 void RTLIL::Module::rename(RTLIL::Wire
*wire
, RTLIL::IdString new_name
)
1606 log_assert(wires_
[wire
->name
] == wire
);
1607 log_assert(refcount_wires_
== 0);
1608 wires_
.erase(wire
->name
);
1609 wire
->name
= new_name
;
1613 void RTLIL::Module::rename(RTLIL::Cell
*cell
, RTLIL::IdString new_name
)
1615 log_assert(cells_
[cell
->name
] == cell
);
1616 log_assert(refcount_wires_
== 0);
1617 cells_
.erase(cell
->name
);
1618 cell
->name
= new_name
;
1622 void RTLIL::Module::rename(RTLIL::IdString old_name
, RTLIL::IdString new_name
)
1624 log_assert(count_id(old_name
) != 0);
1625 if (wires_
.count(old_name
))
1626 rename(wires_
.at(old_name
), new_name
);
1627 else if (cells_
.count(old_name
))
1628 rename(cells_
.at(old_name
), new_name
);
1633 void RTLIL::Module::swap_names(RTLIL::Wire
*w1
, RTLIL::Wire
*w2
)
1635 log_assert(wires_
[w1
->name
] == w1
);
1636 log_assert(wires_
[w2
->name
] == w2
);
1637 log_assert(refcount_wires_
== 0);
1639 wires_
.erase(w1
->name
);
1640 wires_
.erase(w2
->name
);
1642 std::swap(w1
->name
, w2
->name
);
1644 wires_
[w1
->name
] = w1
;
1645 wires_
[w2
->name
] = w2
;
1648 void RTLIL::Module::swap_names(RTLIL::Cell
*c1
, RTLIL::Cell
*c2
)
1650 log_assert(cells_
[c1
->name
] == c1
);
1651 log_assert(cells_
[c2
->name
] == c2
);
1652 log_assert(refcount_cells_
== 0);
1654 cells_
.erase(c1
->name
);
1655 cells_
.erase(c2
->name
);
1657 std::swap(c1
->name
, c2
->name
);
1659 cells_
[c1
->name
] = c1
;
1660 cells_
[c2
->name
] = c2
;
1663 RTLIL::IdString
RTLIL::Module::uniquify(RTLIL::IdString name
)
1666 return uniquify(name
, index
);
1669 RTLIL::IdString
RTLIL::Module::uniquify(RTLIL::IdString name
, int &index
)
1672 if (count_id(name
) == 0)
1678 RTLIL::IdString new_name
= stringf("%s_%d", name
.c_str(), index
);
1679 if (count_id(new_name
) == 0)
1685 static bool fixup_ports_compare(const RTLIL::Wire
*a
, const RTLIL::Wire
*b
)
1687 if (a
->port_id
&& !b
->port_id
)
1689 if (!a
->port_id
&& b
->port_id
)
1692 if (a
->port_id
== b
->port_id
)
1693 return a
->name
< b
->name
;
1694 return a
->port_id
< b
->port_id
;
1697 void RTLIL::Module::connect(const RTLIL::SigSig
&conn
)
1699 for (auto mon
: monitors
)
1700 mon
->notify_connect(this, conn
);
1703 for (auto mon
: design
->monitors
)
1704 mon
->notify_connect(this, conn
);
1706 // ignore all attempts to assign constants to other constants
1707 if (conn
.first
.has_const()) {
1708 RTLIL::SigSig new_conn
;
1709 for (int i
= 0; i
< GetSize(conn
.first
); i
++)
1710 if (conn
.first
[i
].wire
) {
1711 new_conn
.first
.append(conn
.first
[i
]);
1712 new_conn
.second
.append(conn
.second
[i
]);
1714 if (GetSize(new_conn
.first
))
1720 log("#X# Connect (SigSig) in %s: %s = %s (%d bits)\n", log_id(this), log_signal(conn
.first
), log_signal(conn
.second
), GetSize(conn
.first
));
1721 log_backtrace("-X- ", yosys_xtrace
-1);
1724 log_assert(GetSize(conn
.first
) == GetSize(conn
.second
));
1725 connections_
.push_back(conn
);
1728 void RTLIL::Module::connect(const RTLIL::SigSpec
&lhs
, const RTLIL::SigSpec
&rhs
)
1730 connect(RTLIL::SigSig(lhs
, rhs
));
1733 void RTLIL::Module::new_connections(const std::vector
<RTLIL::SigSig
> &new_conn
)
1735 for (auto mon
: monitors
)
1736 mon
->notify_connect(this, new_conn
);
1739 for (auto mon
: design
->monitors
)
1740 mon
->notify_connect(this, new_conn
);
1743 log("#X# New connections vector in %s:\n", log_id(this));
1744 for (auto &conn
: new_conn
)
1745 log("#X# %s = %s (%d bits)\n", log_signal(conn
.first
), log_signal(conn
.second
), GetSize(conn
.first
));
1746 log_backtrace("-X- ", yosys_xtrace
-1);
1749 connections_
= new_conn
;
1752 const std::vector
<RTLIL::SigSig
> &RTLIL::Module::connections() const
1754 return connections_
;
1757 void RTLIL::Module::fixup_ports()
1759 std::vector
<RTLIL::Wire
*> all_ports
;
1761 for (auto &w
: wires_
)
1762 if (w
.second
->port_input
|| w
.second
->port_output
)
1763 all_ports
.push_back(w
.second
);
1765 w
.second
->port_id
= 0;
1767 std::sort(all_ports
.begin(), all_ports
.end(), fixup_ports_compare
);
1770 for (size_t i
= 0; i
< all_ports
.size(); i
++) {
1771 ports
.push_back(all_ports
[i
]->name
);
1772 all_ports
[i
]->port_id
= i
+1;
1776 RTLIL::Wire
*RTLIL::Module::addWire(RTLIL::IdString name
, int width
)
1778 RTLIL::Wire
*wire
= new RTLIL::Wire
;
1780 wire
->width
= width
;
1785 RTLIL::Wire
*RTLIL::Module::addWire(RTLIL::IdString name
, const RTLIL::Wire
*other
)
1787 RTLIL::Wire
*wire
= addWire(name
);
1788 wire
->width
= other
->width
;
1789 wire
->start_offset
= other
->start_offset
;
1790 wire
->port_id
= other
->port_id
;
1791 wire
->port_input
= other
->port_input
;
1792 wire
->port_output
= other
->port_output
;
1793 wire
->upto
= other
->upto
;
1794 wire
->attributes
= other
->attributes
;
1798 RTLIL::Cell
*RTLIL::Module::addCell(RTLIL::IdString name
, RTLIL::IdString type
)
1800 RTLIL::Cell
*cell
= new RTLIL::Cell
;
1807 RTLIL::Cell
*RTLIL::Module::addCell(RTLIL::IdString name
, const RTLIL::Cell
*other
)
1809 RTLIL::Cell
*cell
= addCell(name
, other
->type
);
1810 cell
->connections_
= other
->connections_
;
1811 cell
->parameters
= other
->parameters
;
1812 cell
->attributes
= other
->attributes
;
1816 #define DEF_METHOD(_func, _y_size, _type) \
1817 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed, const std::string &src) { \
1818 RTLIL::Cell *cell = addCell(name, _type); \
1819 cell->parameters["\\A_SIGNED"] = is_signed; \
1820 cell->parameters["\\A_WIDTH"] = sig_a.size(); \
1821 cell->parameters["\\Y_WIDTH"] = sig_y.size(); \
1822 cell->setPort("\\A", sig_a); \
1823 cell->setPort("\\Y", sig_y); \
1824 cell->set_src_attribute(src); \
1827 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed, const std::string &src) { \
1828 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
1829 add ## _func(name, sig_a, sig_y, is_signed, src); \
1832 DEF_METHOD(Not
, sig_a
.size(), "$not")
1833 DEF_METHOD(Pos
, sig_a
.size(), "$pos")
1834 DEF_METHOD(Neg
, sig_a
.size(), "$neg")
1835 DEF_METHOD(ReduceAnd
, 1, "$reduce_and")
1836 DEF_METHOD(ReduceOr
, 1, "$reduce_or")
1837 DEF_METHOD(ReduceXor
, 1, "$reduce_xor")
1838 DEF_METHOD(ReduceXnor
, 1, "$reduce_xnor")
1839 DEF_METHOD(ReduceBool
, 1, "$reduce_bool")
1840 DEF_METHOD(LogicNot
, 1, "$logic_not")
1843 #define DEF_METHOD(_func, _y_size, _type) \
1844 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed, const std::string &src) { \
1845 RTLIL::Cell *cell = addCell(name, _type); \
1846 cell->parameters["\\A_SIGNED"] = is_signed; \
1847 cell->parameters["\\B_SIGNED"] = is_signed; \
1848 cell->parameters["\\A_WIDTH"] = sig_a.size(); \
1849 cell->parameters["\\B_WIDTH"] = sig_b.size(); \
1850 cell->parameters["\\Y_WIDTH"] = sig_y.size(); \
1851 cell->setPort("\\A", sig_a); \
1852 cell->setPort("\\B", sig_b); \
1853 cell->setPort("\\Y", sig_y); \
1854 cell->set_src_attribute(src); \
1857 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed, const std::string &src) { \
1858 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
1859 add ## _func(name, sig_a, sig_b, sig_y, is_signed, src); \
1862 DEF_METHOD(And
, max(sig_a
.size(), sig_b
.size()), "$and")
1863 DEF_METHOD(Or
, max(sig_a
.size(), sig_b
.size()), "$or")
1864 DEF_METHOD(Xor
, max(sig_a
.size(), sig_b
.size()), "$xor")
1865 DEF_METHOD(Xnor
, max(sig_a
.size(), sig_b
.size()), "$xnor")
1866 DEF_METHOD(Shl
, sig_a
.size(), "$shl")
1867 DEF_METHOD(Shr
, sig_a
.size(), "$shr")
1868 DEF_METHOD(Sshl
, sig_a
.size(), "$sshl")
1869 DEF_METHOD(Sshr
, sig_a
.size(), "$sshr")
1870 DEF_METHOD(Shift
, sig_a
.size(), "$shift")
1871 DEF_METHOD(Shiftx
, sig_a
.size(), "$shiftx")
1872 DEF_METHOD(Lt
, 1, "$lt")
1873 DEF_METHOD(Le
, 1, "$le")
1874 DEF_METHOD(Eq
, 1, "$eq")
1875 DEF_METHOD(Ne
, 1, "$ne")
1876 DEF_METHOD(Eqx
, 1, "$eqx")
1877 DEF_METHOD(Nex
, 1, "$nex")
1878 DEF_METHOD(Ge
, 1, "$ge")
1879 DEF_METHOD(Gt
, 1, "$gt")
1880 DEF_METHOD(Add
, max(sig_a
.size(), sig_b
.size()), "$add")
1881 DEF_METHOD(Sub
, max(sig_a
.size(), sig_b
.size()), "$sub")
1882 DEF_METHOD(Mul
, max(sig_a
.size(), sig_b
.size()), "$mul")
1883 DEF_METHOD(Div
, max(sig_a
.size(), sig_b
.size()), "$div")
1884 DEF_METHOD(Mod
, max(sig_a
.size(), sig_b
.size()), "$mod")
1885 DEF_METHOD(LogicAnd
, 1, "$logic_and")
1886 DEF_METHOD(LogicOr
, 1, "$logic_or")
1889 #define DEF_METHOD(_func, _type, _pmux) \
1890 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, RTLIL::SigSpec sig_y, const std::string &src) { \
1891 RTLIL::Cell *cell = addCell(name, _type); \
1892 cell->parameters["\\WIDTH"] = sig_a.size(); \
1893 if (_pmux) cell->parameters["\\S_WIDTH"] = sig_s.size(); \
1894 cell->setPort("\\A", sig_a); \
1895 cell->setPort("\\B", sig_b); \
1896 cell->setPort("\\S", sig_s); \
1897 cell->setPort("\\Y", sig_y); \
1898 cell->set_src_attribute(src); \
1901 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, const std::string &src) { \
1902 RTLIL::SigSpec sig_y = addWire(NEW_ID, sig_a.size()); \
1903 add ## _func(name, sig_a, sig_b, sig_s, sig_y, src); \
1906 DEF_METHOD(Mux
, "$mux", 0)
1907 DEF_METHOD(Pmux
, "$pmux", 1)
1910 #define DEF_METHOD_2(_func, _type, _P1, _P2) \
1911 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, const std::string &src) { \
1912 RTLIL::Cell *cell = addCell(name, _type); \
1913 cell->setPort("\\" #_P1, sig1); \
1914 cell->setPort("\\" #_P2, sig2); \
1915 cell->set_src_attribute(src); \
1918 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, const std::string &src) { \
1919 RTLIL::SigBit sig2 = addWire(NEW_ID); \
1920 add ## _func(name, sig1, sig2, src); \
1923 #define DEF_METHOD_3(_func, _type, _P1, _P2, _P3) \
1924 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, const std::string &src) { \
1925 RTLIL::Cell *cell = addCell(name, _type); \
1926 cell->setPort("\\" #_P1, sig1); \
1927 cell->setPort("\\" #_P2, sig2); \
1928 cell->setPort("\\" #_P3, sig3); \
1929 cell->set_src_attribute(src); \
1932 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, const std::string &src) { \
1933 RTLIL::SigBit sig3 = addWire(NEW_ID); \
1934 add ## _func(name, sig1, sig2, sig3, src); \
1937 #define DEF_METHOD_4(_func, _type, _P1, _P2, _P3, _P4) \
1938 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, RTLIL::SigBit sig4, const std::string &src) { \
1939 RTLIL::Cell *cell = addCell(name, _type); \
1940 cell->setPort("\\" #_P1, sig1); \
1941 cell->setPort("\\" #_P2, sig2); \
1942 cell->setPort("\\" #_P3, sig3); \
1943 cell->setPort("\\" #_P4, sig4); \
1944 cell->set_src_attribute(src); \
1947 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, const std::string &src) { \
1948 RTLIL::SigBit sig4 = addWire(NEW_ID); \
1949 add ## _func(name, sig1, sig2, sig3, sig4, src); \
1952 #define DEF_METHOD_5(_func, _type, _P1, _P2, _P3, _P4, _P5) \
1953 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, RTLIL::SigBit sig4, RTLIL::SigBit sig5, const std::string &src) { \
1954 RTLIL::Cell *cell = addCell(name, _type); \
1955 cell->setPort("\\" #_P1, sig1); \
1956 cell->setPort("\\" #_P2, sig2); \
1957 cell->setPort("\\" #_P3, sig3); \
1958 cell->setPort("\\" #_P4, sig4); \
1959 cell->setPort("\\" #_P5, sig5); \
1960 cell->set_src_attribute(src); \
1963 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, RTLIL::SigBit sig4, const std::string &src) { \
1964 RTLIL::SigBit sig5 = addWire(NEW_ID); \
1965 add ## _func(name, sig1, sig2, sig3, sig4, sig5, src); \
1968 DEF_METHOD_2(BufGate
, "$_BUF_", A
, Y
)
1969 DEF_METHOD_2(NotGate
, "$_NOT_", A
, Y
)
1970 DEF_METHOD_3(AndGate
, "$_AND_", A
, B
, Y
)
1971 DEF_METHOD_3(NandGate
, "$_NAND_", A
, B
, Y
)
1972 DEF_METHOD_3(OrGate
, "$_OR_", A
, B
, Y
)
1973 DEF_METHOD_3(NorGate
, "$_NOR_", A
, B
, Y
)
1974 DEF_METHOD_3(XorGate
, "$_XOR_", A
, B
, Y
)
1975 DEF_METHOD_3(XnorGate
, "$_XNOR_", A
, B
, Y
)
1976 DEF_METHOD_3(AndnotGate
, "$_ANDNOT_", A
, B
, Y
)
1977 DEF_METHOD_3(OrnotGate
, "$_ORNOT_", A
, B
, Y
)
1978 DEF_METHOD_4(MuxGate
, "$_MUX_", A
, B
, S
, Y
)
1979 DEF_METHOD_4(Aoi3Gate
, "$_AOI3_", A
, B
, C
, Y
)
1980 DEF_METHOD_4(Oai3Gate
, "$_OAI3_", A
, B
, C
, Y
)
1981 DEF_METHOD_5(Aoi4Gate
, "$_AOI4_", A
, B
, C
, D
, Y
)
1982 DEF_METHOD_5(Oai4Gate
, "$_OAI4_", A
, B
, C
, D
, Y
)
1988 RTLIL::Cell
* RTLIL::Module::addPow(RTLIL::IdString name
, RTLIL::SigSpec sig_a
, RTLIL::SigSpec sig_b
, RTLIL::SigSpec sig_y
, bool a_signed
, bool b_signed
, const std::string
&src
)
1990 RTLIL::Cell
*cell
= addCell(name
, "$pow");
1991 cell
->parameters
["\\A_SIGNED"] = a_signed
;
1992 cell
->parameters
["\\B_SIGNED"] = b_signed
;
1993 cell
->parameters
["\\A_WIDTH"] = sig_a
.size();
1994 cell
->parameters
["\\B_WIDTH"] = sig_b
.size();
1995 cell
->parameters
["\\Y_WIDTH"] = sig_y
.size();
1996 cell
->setPort("\\A", sig_a
);
1997 cell
->setPort("\\B", sig_b
);
1998 cell
->setPort("\\Y", sig_y
);
1999 cell
->set_src_attribute(src
);
2003 RTLIL::Cell
* RTLIL::Module::addSlice(RTLIL::IdString name
, RTLIL::SigSpec sig_a
, RTLIL::SigSpec sig_y
, RTLIL::Const offset
, const std::string
&src
)
2005 RTLIL::Cell
*cell
= addCell(name
, "$slice");
2006 cell
->parameters
["\\A_WIDTH"] = sig_a
.size();
2007 cell
->parameters
["\\Y_WIDTH"] = sig_y
.size();
2008 cell
->parameters
["\\OFFSET"] = offset
;
2009 cell
->setPort("\\A", sig_a
);
2010 cell
->setPort("\\Y", sig_y
);
2011 cell
->set_src_attribute(src
);
2015 RTLIL::Cell
* RTLIL::Module::addConcat(RTLIL::IdString name
, RTLIL::SigSpec sig_a
, RTLIL::SigSpec sig_b
, RTLIL::SigSpec sig_y
, const std::string
&src
)
2017 RTLIL::Cell
*cell
= addCell(name
, "$concat");
2018 cell
->parameters
["\\A_WIDTH"] = sig_a
.size();
2019 cell
->parameters
["\\B_WIDTH"] = sig_b
.size();
2020 cell
->setPort("\\A", sig_a
);
2021 cell
->setPort("\\B", sig_b
);
2022 cell
->setPort("\\Y", sig_y
);
2023 cell
->set_src_attribute(src
);
2027 RTLIL::Cell
* RTLIL::Module::addLut(RTLIL::IdString name
, RTLIL::SigSpec sig_a
, RTLIL::SigSpec sig_y
, RTLIL::Const lut
, const std::string
&src
)
2029 RTLIL::Cell
*cell
= addCell(name
, "$lut");
2030 cell
->parameters
["\\LUT"] = lut
;
2031 cell
->parameters
["\\WIDTH"] = sig_a
.size();
2032 cell
->setPort("\\A", sig_a
);
2033 cell
->setPort("\\Y", sig_y
);
2034 cell
->set_src_attribute(src
);
2038 RTLIL::Cell
* RTLIL::Module::addTribuf(RTLIL::IdString name
, RTLIL::SigSpec sig_a
, RTLIL::SigSpec sig_en
, RTLIL::SigSpec sig_y
, const std::string
&src
)
2040 RTLIL::Cell
*cell
= addCell(name
, "$tribuf");
2041 cell
->parameters
["\\WIDTH"] = sig_a
.size();
2042 cell
->setPort("\\A", sig_a
);
2043 cell
->setPort("\\EN", sig_en
);
2044 cell
->setPort("\\Y", sig_y
);
2045 cell
->set_src_attribute(src
);
2049 RTLIL::Cell
* RTLIL::Module::addAssert(RTLIL::IdString name
, RTLIL::SigSpec sig_a
, RTLIL::SigSpec sig_en
, const std::string
&src
)
2051 RTLIL::Cell
*cell
= addCell(name
, "$assert");
2052 cell
->setPort("\\A", sig_a
);
2053 cell
->setPort("\\EN", sig_en
);
2054 cell
->set_src_attribute(src
);
2058 RTLIL::Cell
* RTLIL::Module::addAssume(RTLIL::IdString name
, RTLIL::SigSpec sig_a
, RTLIL::SigSpec sig_en
, const std::string
&src
)
2060 RTLIL::Cell
*cell
= addCell(name
, "$assume");
2061 cell
->setPort("\\A", sig_a
);
2062 cell
->setPort("\\EN", sig_en
);
2063 cell
->set_src_attribute(src
);
2067 RTLIL::Cell
* RTLIL::Module::addLive(RTLIL::IdString name
, RTLIL::SigSpec sig_a
, RTLIL::SigSpec sig_en
, const std::string
&src
)
2069 RTLIL::Cell
*cell
= addCell(name
, "$live");
2070 cell
->setPort("\\A", sig_a
);
2071 cell
->setPort("\\EN", sig_en
);
2072 cell
->set_src_attribute(src
);
2076 RTLIL::Cell
* RTLIL::Module::addFair(RTLIL::IdString name
, RTLIL::SigSpec sig_a
, RTLIL::SigSpec sig_en
, const std::string
&src
)
2078 RTLIL::Cell
*cell
= addCell(name
, "$fair");
2079 cell
->setPort("\\A", sig_a
);
2080 cell
->setPort("\\EN", sig_en
);
2081 cell
->set_src_attribute(src
);
2085 RTLIL::Cell
* RTLIL::Module::addCover(RTLIL::IdString name
, RTLIL::SigSpec sig_a
, RTLIL::SigSpec sig_en
, const std::string
&src
)
2087 RTLIL::Cell
*cell
= addCell(name
, "$cover");
2088 cell
->setPort("\\A", sig_a
);
2089 cell
->setPort("\\EN", sig_en
);
2090 cell
->set_src_attribute(src
);
2094 RTLIL::Cell
* RTLIL::Module::addEquiv(RTLIL::IdString name
, RTLIL::SigSpec sig_a
, RTLIL::SigSpec sig_b
, RTLIL::SigSpec sig_y
, const std::string
&src
)
2096 RTLIL::Cell
*cell
= addCell(name
, "$equiv");
2097 cell
->setPort("\\A", sig_a
);
2098 cell
->setPort("\\B", sig_b
);
2099 cell
->setPort("\\Y", sig_y
);
2100 cell
->set_src_attribute(src
);
2104 RTLIL::Cell
* RTLIL::Module::addSr(RTLIL::IdString name
, RTLIL::SigSpec sig_set
, RTLIL::SigSpec sig_clr
, RTLIL::SigSpec sig_q
, bool set_polarity
, bool clr_polarity
, const std::string
&src
)
2106 RTLIL::Cell
*cell
= addCell(name
, "$sr");
2107 cell
->parameters
["\\SET_POLARITY"] = set_polarity
;
2108 cell
->parameters
["\\CLR_POLARITY"] = clr_polarity
;
2109 cell
->parameters
["\\WIDTH"] = sig_q
.size();
2110 cell
->setPort("\\SET", sig_set
);
2111 cell
->setPort("\\CLR", sig_clr
);
2112 cell
->setPort("\\Q", sig_q
);
2113 cell
->set_src_attribute(src
);
2117 RTLIL::Cell
* RTLIL::Module::addFf(RTLIL::IdString name
, RTLIL::SigSpec sig_d
, RTLIL::SigSpec sig_q
, const std::string
&src
)
2119 RTLIL::Cell
*cell
= addCell(name
, "$ff");
2120 cell
->parameters
["\\WIDTH"] = sig_q
.size();
2121 cell
->setPort("\\D", sig_d
);
2122 cell
->setPort("\\Q", sig_q
);
2123 cell
->set_src_attribute(src
);
2127 RTLIL::Cell
* RTLIL::Module::addDff(RTLIL::IdString name
, RTLIL::SigSpec sig_clk
, RTLIL::SigSpec sig_d
, RTLIL::SigSpec sig_q
, bool clk_polarity
, const std::string
&src
)
2129 RTLIL::Cell
*cell
= addCell(name
, "$dff");
2130 cell
->parameters
["\\CLK_POLARITY"] = clk_polarity
;
2131 cell
->parameters
["\\WIDTH"] = sig_q
.size();
2132 cell
->setPort("\\CLK", sig_clk
);
2133 cell
->setPort("\\D", sig_d
);
2134 cell
->setPort("\\Q", sig_q
);
2135 cell
->set_src_attribute(src
);
2139 RTLIL::Cell
* RTLIL::Module::addDffe(RTLIL::IdString name
, RTLIL::SigSpec sig_clk
, RTLIL::SigSpec sig_en
, RTLIL::SigSpec sig_d
, RTLIL::SigSpec sig_q
, bool clk_polarity
, bool en_polarity
, const std::string
&src
)
2141 RTLIL::Cell
*cell
= addCell(name
, "$dffe");
2142 cell
->parameters
["\\CLK_POLARITY"] = clk_polarity
;
2143 cell
->parameters
["\\EN_POLARITY"] = en_polarity
;
2144 cell
->parameters
["\\WIDTH"] = sig_q
.size();
2145 cell
->setPort("\\CLK", sig_clk
);
2146 cell
->setPort("\\EN", sig_en
);
2147 cell
->setPort("\\D", sig_d
);
2148 cell
->setPort("\\Q", sig_q
);
2149 cell
->set_src_attribute(src
);
2153 RTLIL::Cell
* RTLIL::Module::addDffsr(RTLIL::IdString name
, RTLIL::SigSpec sig_clk
, RTLIL::SigSpec sig_set
, RTLIL::SigSpec sig_clr
,
2154 RTLIL::SigSpec sig_d
, RTLIL::SigSpec sig_q
, bool clk_polarity
, bool set_polarity
, bool clr_polarity
, const std::string
&src
)
2156 RTLIL::Cell
*cell
= addCell(name
, "$dffsr");
2157 cell
->parameters
["\\CLK_POLARITY"] = clk_polarity
;
2158 cell
->parameters
["\\SET_POLARITY"] = set_polarity
;
2159 cell
->parameters
["\\CLR_POLARITY"] = clr_polarity
;
2160 cell
->parameters
["\\WIDTH"] = sig_q
.size();
2161 cell
->setPort("\\CLK", sig_clk
);
2162 cell
->setPort("\\SET", sig_set
);
2163 cell
->setPort("\\CLR", sig_clr
);
2164 cell
->setPort("\\D", sig_d
);
2165 cell
->setPort("\\Q", sig_q
);
2166 cell
->set_src_attribute(src
);
2170 RTLIL::Cell
* RTLIL::Module::addAdff(RTLIL::IdString name
, RTLIL::SigSpec sig_clk
, RTLIL::SigSpec sig_arst
, RTLIL::SigSpec sig_d
, RTLIL::SigSpec sig_q
,
2171 RTLIL::Const arst_value
, bool clk_polarity
, bool arst_polarity
, const std::string
&src
)
2173 RTLIL::Cell
*cell
= addCell(name
, "$adff");
2174 cell
->parameters
["\\CLK_POLARITY"] = clk_polarity
;
2175 cell
->parameters
["\\ARST_POLARITY"] = arst_polarity
;
2176 cell
->parameters
["\\ARST_VALUE"] = arst_value
;
2177 cell
->parameters
["\\WIDTH"] = sig_q
.size();
2178 cell
->setPort("\\CLK", sig_clk
);
2179 cell
->setPort("\\ARST", sig_arst
);
2180 cell
->setPort("\\D", sig_d
);
2181 cell
->setPort("\\Q", sig_q
);
2182 cell
->set_src_attribute(src
);
2186 RTLIL::Cell
* RTLIL::Module::addDlatch(RTLIL::IdString name
, RTLIL::SigSpec sig_en
, RTLIL::SigSpec sig_d
, RTLIL::SigSpec sig_q
, bool en_polarity
, const std::string
&src
)
2188 RTLIL::Cell
*cell
= addCell(name
, "$dlatch");
2189 cell
->parameters
["\\EN_POLARITY"] = en_polarity
;
2190 cell
->parameters
["\\WIDTH"] = sig_q
.size();
2191 cell
->setPort("\\EN", sig_en
);
2192 cell
->setPort("\\D", sig_d
);
2193 cell
->setPort("\\Q", sig_q
);
2194 cell
->set_src_attribute(src
);
2198 RTLIL::Cell
* RTLIL::Module::addDlatchsr(RTLIL::IdString name
, RTLIL::SigSpec sig_en
, RTLIL::SigSpec sig_set
, RTLIL::SigSpec sig_clr
,
2199 RTLIL::SigSpec sig_d
, RTLIL::SigSpec sig_q
, bool en_polarity
, bool set_polarity
, bool clr_polarity
, const std::string
&src
)
2201 RTLIL::Cell
*cell
= addCell(name
, "$dlatchsr");
2202 cell
->parameters
["\\EN_POLARITY"] = en_polarity
;
2203 cell
->parameters
["\\SET_POLARITY"] = set_polarity
;
2204 cell
->parameters
["\\CLR_POLARITY"] = clr_polarity
;
2205 cell
->parameters
["\\WIDTH"] = sig_q
.size();
2206 cell
->setPort("\\EN", sig_en
);
2207 cell
->setPort("\\SET", sig_set
);
2208 cell
->setPort("\\CLR", sig_clr
);
2209 cell
->setPort("\\D", sig_d
);
2210 cell
->setPort("\\Q", sig_q
);
2211 cell
->set_src_attribute(src
);
2215 RTLIL::Cell
* RTLIL::Module::addFfGate(RTLIL::IdString name
, RTLIL::SigSpec sig_d
, RTLIL::SigSpec sig_q
, const std::string
&src
)
2217 RTLIL::Cell
*cell
= addCell(name
, "$_FF_");
2218 cell
->setPort("\\D", sig_d
);
2219 cell
->setPort("\\Q", sig_q
);
2220 cell
->set_src_attribute(src
);
2224 RTLIL::Cell
* RTLIL::Module::addDffGate(RTLIL::IdString name
, RTLIL::SigSpec sig_clk
, RTLIL::SigSpec sig_d
, RTLIL::SigSpec sig_q
, bool clk_polarity
, const std::string
&src
)
2226 RTLIL::Cell
*cell
= addCell(name
, stringf("$_DFF_%c_", clk_polarity
? 'P' : 'N'));
2227 cell
->setPort("\\C", sig_clk
);
2228 cell
->setPort("\\D", sig_d
);
2229 cell
->setPort("\\Q", sig_q
);
2230 cell
->set_src_attribute(src
);
2234 RTLIL::Cell
* RTLIL::Module::addDffeGate(RTLIL::IdString name
, RTLIL::SigSpec sig_clk
, RTLIL::SigSpec sig_en
, RTLIL::SigSpec sig_d
, RTLIL::SigSpec sig_q
, bool clk_polarity
, bool en_polarity
, const std::string
&src
)
2236 RTLIL::Cell
*cell
= addCell(name
, stringf("$_DFFE_%c%c_", clk_polarity
? 'P' : 'N', en_polarity
? 'P' : 'N'));
2237 cell
->setPort("\\C", sig_clk
);
2238 cell
->setPort("\\E", sig_en
);
2239 cell
->setPort("\\D", sig_d
);
2240 cell
->setPort("\\Q", sig_q
);
2241 cell
->set_src_attribute(src
);
2245 RTLIL::Cell
* RTLIL::Module::addDffsrGate(RTLIL::IdString name
, RTLIL::SigSpec sig_clk
, RTLIL::SigSpec sig_set
, RTLIL::SigSpec sig_clr
,
2246 RTLIL::SigSpec sig_d
, RTLIL::SigSpec sig_q
, bool clk_polarity
, bool set_polarity
, bool clr_polarity
, const std::string
&src
)
2248 RTLIL::Cell
*cell
= addCell(name
, stringf("$_DFFSR_%c%c%c_", clk_polarity
? 'P' : 'N', set_polarity
? 'P' : 'N', clr_polarity
? 'P' : 'N'));
2249 cell
->setPort("\\C", sig_clk
);
2250 cell
->setPort("\\S", sig_set
);
2251 cell
->setPort("\\R", sig_clr
);
2252 cell
->setPort("\\D", sig_d
);
2253 cell
->setPort("\\Q", sig_q
);
2254 cell
->set_src_attribute(src
);
2258 RTLIL::Cell
* RTLIL::Module::addAdffGate(RTLIL::IdString name
, RTLIL::SigSpec sig_clk
, RTLIL::SigSpec sig_arst
, RTLIL::SigSpec sig_d
, RTLIL::SigSpec sig_q
,
2259 bool arst_value
, bool clk_polarity
, bool arst_polarity
, const std::string
&src
)
2261 RTLIL::Cell
*cell
= addCell(name
, stringf("$_DFF_%c%c%c_", clk_polarity
? 'P' : 'N', arst_polarity
? 'P' : 'N', arst_value
? '1' : '0'));
2262 cell
->setPort("\\C", sig_clk
);
2263 cell
->setPort("\\R", sig_arst
);
2264 cell
->setPort("\\D", sig_d
);
2265 cell
->setPort("\\Q", sig_q
);
2266 cell
->set_src_attribute(src
);
2270 RTLIL::Cell
* RTLIL::Module::addDlatchGate(RTLIL::IdString name
, RTLIL::SigSpec sig_en
, RTLIL::SigSpec sig_d
, RTLIL::SigSpec sig_q
, bool en_polarity
, const std::string
&src
)
2272 RTLIL::Cell
*cell
= addCell(name
, stringf("$_DLATCH_%c_", en_polarity
? 'P' : 'N'));
2273 cell
->setPort("\\E", sig_en
);
2274 cell
->setPort("\\D", sig_d
);
2275 cell
->setPort("\\Q", sig_q
);
2276 cell
->set_src_attribute(src
);
2280 RTLIL::Cell
* RTLIL::Module::addDlatchsrGate(RTLIL::IdString name
, RTLIL::SigSpec sig_en
, RTLIL::SigSpec sig_set
, RTLIL::SigSpec sig_clr
,
2281 RTLIL::SigSpec sig_d
, RTLIL::SigSpec sig_q
, bool en_polarity
, bool set_polarity
, bool clr_polarity
, const std::string
&src
)
2283 RTLIL::Cell
*cell
= addCell(name
, stringf("$_DLATCHSR_%c%c%c_", en_polarity
? 'P' : 'N', set_polarity
? 'P' : 'N', clr_polarity
? 'P' : 'N'));
2284 cell
->setPort("\\E", sig_en
);
2285 cell
->setPort("\\S", sig_set
);
2286 cell
->setPort("\\R", sig_clr
);
2287 cell
->setPort("\\D", sig_d
);
2288 cell
->setPort("\\Q", sig_q
);
2289 cell
->set_src_attribute(src
);
2293 RTLIL::SigSpec
RTLIL::Module::Anyconst(RTLIL::IdString name
, int width
, const std::string
&src
)
2295 RTLIL::SigSpec sig
= addWire(NEW_ID
, width
);
2296 Cell
*cell
= addCell(name
, "$anyconst");
2297 cell
->setParam("\\WIDTH", width
);
2298 cell
->setPort("\\Y", sig
);
2299 cell
->set_src_attribute(src
);
2303 RTLIL::SigSpec
RTLIL::Module::Anyseq(RTLIL::IdString name
, int width
, const std::string
&src
)
2305 RTLIL::SigSpec sig
= addWire(NEW_ID
, width
);
2306 Cell
*cell
= addCell(name
, "$anyseq");
2307 cell
->setParam("\\WIDTH", width
);
2308 cell
->setPort("\\Y", sig
);
2309 cell
->set_src_attribute(src
);
2313 RTLIL::SigSpec
RTLIL::Module::Allconst(RTLIL::IdString name
, int width
, const std::string
&src
)
2315 RTLIL::SigSpec sig
= addWire(NEW_ID
, width
);
2316 Cell
*cell
= addCell(name
, "$allconst");
2317 cell
->setParam("\\WIDTH", width
);
2318 cell
->setPort("\\Y", sig
);
2319 cell
->set_src_attribute(src
);
2323 RTLIL::SigSpec
RTLIL::Module::Allseq(RTLIL::IdString name
, int width
, const std::string
&src
)
2325 RTLIL::SigSpec sig
= addWire(NEW_ID
, width
);
2326 Cell
*cell
= addCell(name
, "$allseq");
2327 cell
->setParam("\\WIDTH", width
);
2328 cell
->setPort("\\Y", sig
);
2329 cell
->set_src_attribute(src
);
2333 RTLIL::SigSpec
RTLIL::Module::Initstate(RTLIL::IdString name
, const std::string
&src
)
2335 RTLIL::SigSpec sig
= addWire(NEW_ID
);
2336 Cell
*cell
= addCell(name
, "$initstate");
2337 cell
->setPort("\\Y", sig
);
2338 cell
->set_src_attribute(src
);
2344 static unsigned int hashidx_count
= 123456789;
2345 hashidx_count
= mkhash_xorshift(hashidx_count
);
2346 hashidx_
= hashidx_count
;
2353 port_output
= false;
2357 RTLIL::Wire::get_all_wires()->insert(std::pair
<unsigned int, RTLIL::Wire
*>(hashidx_
, this));
2361 RTLIL::Wire::~Wire()
2364 RTLIL::Wire::get_all_wires()->erase(hashidx_
);
2369 static std::map
<unsigned int, RTLIL::Wire
*> all_wires
;
2370 std::map
<unsigned int, RTLIL::Wire
*> *RTLIL::Wire::get_all_wires(void)
2376 RTLIL::Memory::Memory()
2378 static unsigned int hashidx_count
= 123456789;
2379 hashidx_count
= mkhash_xorshift(hashidx_count
);
2380 hashidx_
= hashidx_count
;
2386 RTLIL::Memory::get_all_memorys()->insert(std::pair
<unsigned int, RTLIL::Memory
*>(hashidx_
, this));
2390 RTLIL::Cell::Cell() : module(nullptr)
2392 static unsigned int hashidx_count
= 123456789;
2393 hashidx_count
= mkhash_xorshift(hashidx_count
);
2394 hashidx_
= hashidx_count
;
2396 // log("#memtrace# %p\n", this);
2400 RTLIL::Cell::get_all_cells()->insert(std::pair
<unsigned int, RTLIL::Cell
*>(hashidx_
, this));
2404 RTLIL::Cell::~Cell()
2407 RTLIL::Cell::get_all_cells()->erase(hashidx_
);
2412 static std::map
<unsigned int, RTLIL::Cell
*> all_cells
;
2413 std::map
<unsigned int, RTLIL::Cell
*> *RTLIL::Cell::get_all_cells(void)
2419 bool RTLIL::Cell::hasPort(RTLIL::IdString portname
) const
2421 return connections_
.count(portname
) != 0;
2424 void RTLIL::Cell::unsetPort(RTLIL::IdString portname
)
2426 RTLIL::SigSpec signal
;
2427 auto conn_it
= connections_
.find(portname
);
2429 if (conn_it
!= connections_
.end())
2431 for (auto mon
: module
->monitors
)
2432 mon
->notify_connect(this, conn_it
->first
, conn_it
->second
, signal
);
2435 for (auto mon
: module
->design
->monitors
)
2436 mon
->notify_connect(this, conn_it
->first
, conn_it
->second
, signal
);
2439 log("#X# Unconnect %s.%s.%s\n", log_id(this->module
), log_id(this), log_id(portname
));
2440 log_backtrace("-X- ", yosys_xtrace
-1);
2443 connections_
.erase(conn_it
);
2447 void RTLIL::Cell::setPort(RTLIL::IdString portname
, RTLIL::SigSpec signal
)
2449 auto conn_it
= connections_
.find(portname
);
2451 if (conn_it
== connections_
.end()) {
2452 connections_
[portname
] = RTLIL::SigSpec();
2453 conn_it
= connections_
.find(portname
);
2454 log_assert(conn_it
!= connections_
.end());
2456 if (conn_it
->second
== signal
)
2459 for (auto mon
: module
->monitors
)
2460 mon
->notify_connect(this, conn_it
->first
, conn_it
->second
, signal
);
2463 for (auto mon
: module
->design
->monitors
)
2464 mon
->notify_connect(this, conn_it
->first
, conn_it
->second
, signal
);
2467 log("#X# Connect %s.%s.%s = %s (%d)\n", log_id(this->module
), log_id(this), log_id(portname
), log_signal(signal
), GetSize(signal
));
2468 log_backtrace("-X- ", yosys_xtrace
-1);
2471 conn_it
->second
= signal
;
2474 const RTLIL::SigSpec
&RTLIL::Cell::getPort(RTLIL::IdString portname
) const
2476 return connections_
.at(portname
);
2479 const dict
<RTLIL::IdString
, RTLIL::SigSpec
> &RTLIL::Cell::connections() const
2481 return connections_
;
2484 bool RTLIL::Cell::known() const
2486 if (yosys_celltypes
.cell_known(type
))
2488 if (module
&& module
->design
&& module
->design
->module(type
))
2493 bool RTLIL::Cell::input(RTLIL::IdString portname
) const
2495 if (yosys_celltypes
.cell_known(type
))
2496 return yosys_celltypes
.cell_input(type
, portname
);
2497 if (module
&& module
->design
) {
2498 RTLIL::Module
*m
= module
->design
->module(type
);
2499 RTLIL::Wire
*w
= m
? m
->wire(portname
) : nullptr;
2500 return w
&& w
->port_input
;
2505 bool RTLIL::Cell::output(RTLIL::IdString portname
) const
2507 if (yosys_celltypes
.cell_known(type
))
2508 return yosys_celltypes
.cell_output(type
, portname
);
2509 if (module
&& module
->design
) {
2510 RTLIL::Module
*m
= module
->design
->module(type
);
2511 RTLIL::Wire
*w
= m
? m
->wire(portname
) : nullptr;
2512 return w
&& w
->port_output
;
2517 bool RTLIL::Cell::hasParam(RTLIL::IdString paramname
) const
2519 return parameters
.count(paramname
) != 0;
2522 void RTLIL::Cell::unsetParam(RTLIL::IdString paramname
)
2524 parameters
.erase(paramname
);
2527 void RTLIL::Cell::setParam(RTLIL::IdString paramname
, RTLIL::Const value
)
2529 parameters
[paramname
] = value
;
2532 const RTLIL::Const
&RTLIL::Cell::getParam(RTLIL::IdString paramname
) const
2534 return parameters
.at(paramname
);
2537 void RTLIL::Cell::sort()
2539 connections_
.sort(sort_by_id_str());
2540 parameters
.sort(sort_by_id_str());
2541 attributes
.sort(sort_by_id_str());
2544 void RTLIL::Cell::check()
2547 InternalCellChecker
checker(NULL
, this);
2552 void RTLIL::Cell::fixup_parameters(bool set_a_signed
, bool set_b_signed
)
2554 if (type
.substr(0, 1) != "$" || type
.substr(0, 2) == "$_" || type
.substr(0, 8) == "$paramod" || type
.substr(0,10) == "$fmcombine" ||
2555 type
.substr(0, 9) == "$verific$" || type
.substr(0, 7) == "$array:" || type
.substr(0, 8) == "$extern:")
2558 if (type
== "$mux" || type
== "$pmux") {
2559 parameters
["\\WIDTH"] = GetSize(connections_
["\\Y"]);
2560 if (type
== "$pmux")
2561 parameters
["\\S_WIDTH"] = GetSize(connections_
["\\S"]);
2566 if (type
== "$lut" || type
== "$sop") {
2567 parameters
["\\WIDTH"] = GetSize(connections_
["\\A"]);
2571 if (type
== "$fa") {
2572 parameters
["\\WIDTH"] = GetSize(connections_
["\\Y"]);
2576 if (type
== "$lcu") {
2577 parameters
["\\WIDTH"] = GetSize(connections_
["\\CO"]);
2581 bool signedness_ab
= !type
.in("$slice", "$concat", "$macc");
2583 if (connections_
.count("\\A")) {
2584 if (signedness_ab
) {
2586 parameters
["\\A_SIGNED"] = true;
2587 else if (parameters
.count("\\A_SIGNED") == 0)
2588 parameters
["\\A_SIGNED"] = false;
2590 parameters
["\\A_WIDTH"] = GetSize(connections_
["\\A"]);
2593 if (connections_
.count("\\B")) {
2594 if (signedness_ab
) {
2596 parameters
["\\B_SIGNED"] = true;
2597 else if (parameters
.count("\\B_SIGNED") == 0)
2598 parameters
["\\B_SIGNED"] = false;
2600 parameters
["\\B_WIDTH"] = GetSize(connections_
["\\B"]);
2603 if (connections_
.count("\\Y"))
2604 parameters
["\\Y_WIDTH"] = GetSize(connections_
["\\Y"]);
2606 if (connections_
.count("\\Q"))
2607 parameters
["\\WIDTH"] = GetSize(connections_
["\\Q"]);
2612 RTLIL::SigChunk::SigChunk()
2619 RTLIL::SigChunk::SigChunk(const RTLIL::Const
&value
)
2623 width
= GetSize(data
);
2627 RTLIL::SigChunk::SigChunk(RTLIL::Wire
*wire
)
2629 log_assert(wire
!= nullptr);
2631 this->width
= wire
->width
;
2635 RTLIL::SigChunk::SigChunk(RTLIL::Wire
*wire
, int offset
, int width
)
2637 log_assert(wire
!= nullptr);
2639 this->width
= width
;
2640 this->offset
= offset
;
2643 RTLIL::SigChunk::SigChunk(const std::string
&str
)
2646 data
= RTLIL::Const(str
).bits
;
2647 width
= GetSize(data
);
2651 RTLIL::SigChunk::SigChunk(int val
, int width
)
2654 data
= RTLIL::Const(val
, width
).bits
;
2655 this->width
= GetSize(data
);
2659 RTLIL::SigChunk::SigChunk(RTLIL::State bit
, int width
)
2662 data
= RTLIL::Const(bit
, width
).bits
;
2663 this->width
= GetSize(data
);
2667 RTLIL::SigChunk::SigChunk(RTLIL::SigBit bit
)
2672 data
= RTLIL::Const(bit
.data
).bits
;
2674 offset
= bit
.offset
;
2678 RTLIL::SigChunk::SigChunk(const RTLIL::SigChunk
&sigchunk
) : data(sigchunk
.data
)
2680 wire
= sigchunk
.wire
;
2681 data
= sigchunk
.data
;
2682 width
= sigchunk
.width
;
2683 offset
= sigchunk
.offset
;
2686 RTLIL::SigChunk
RTLIL::SigChunk::extract(int offset
, int length
) const
2688 RTLIL::SigChunk ret
;
2691 ret
.offset
= this->offset
+ offset
;
2694 for (int i
= 0; i
< length
; i
++)
2695 ret
.data
.push_back(data
[offset
+i
]);
2701 bool RTLIL::SigChunk::operator <(const RTLIL::SigChunk
&other
) const
2703 if (wire
&& other
.wire
)
2704 if (wire
->name
!= other
.wire
->name
)
2705 return wire
->name
< other
.wire
->name
;
2707 if (wire
!= other
.wire
)
2708 return wire
< other
.wire
;
2710 if (offset
!= other
.offset
)
2711 return offset
< other
.offset
;
2713 if (width
!= other
.width
)
2714 return width
< other
.width
;
2716 return data
< other
.data
;
2719 bool RTLIL::SigChunk::operator ==(const RTLIL::SigChunk
&other
) const
2721 return wire
== other
.wire
&& width
== other
.width
&& offset
== other
.offset
&& data
== other
.data
;
2724 bool RTLIL::SigChunk::operator !=(const RTLIL::SigChunk
&other
) const
2731 RTLIL::SigSpec::SigSpec()
2737 RTLIL::SigSpec::SigSpec(const RTLIL::SigSpec
&other
)
2742 RTLIL::SigSpec::SigSpec(std::initializer_list
<RTLIL::SigSpec
> parts
)
2744 cover("kernel.rtlil.sigspec.init.list");
2749 std::vector
<RTLIL::SigSpec
> parts_vec(parts
.begin(), parts
.end());
2750 for (auto it
= parts_vec
.rbegin(); it
!= parts_vec
.rend(); it
++)
2754 const RTLIL::SigSpec
&RTLIL::SigSpec::operator=(const RTLIL::SigSpec
&other
)
2756 cover("kernel.rtlil.sigspec.assign");
2758 width_
= other
.width_
;
2759 hash_
= other
.hash_
;
2760 chunks_
= other
.chunks_
;
2763 if (!other
.bits_
.empty())
2765 RTLIL::SigChunk
*last
= NULL
;
2766 int last_end_offset
= 0;
2768 for (auto &bit
: other
.bits_
) {
2769 if (last
&& bit
.wire
== last
->wire
) {
2770 if (bit
.wire
== NULL
) {
2771 last
->data
.push_back(bit
.data
);
2774 } else if (last_end_offset
== bit
.offset
) {
2780 chunks_
.push_back(bit
);
2781 last
= &chunks_
.back();
2782 last_end_offset
= bit
.offset
+ 1;
2791 RTLIL::SigSpec::SigSpec(const RTLIL::Const
&value
)
2793 cover("kernel.rtlil.sigspec.init.const");
2795 chunks_
.push_back(RTLIL::SigChunk(value
));
2796 width_
= chunks_
.back().width
;
2801 RTLIL::SigSpec::SigSpec(const RTLIL::SigChunk
&chunk
)
2803 cover("kernel.rtlil.sigspec.init.chunk");
2805 chunks_
.push_back(chunk
);
2806 width_
= chunks_
.back().width
;
2811 RTLIL::SigSpec::SigSpec(RTLIL::Wire
*wire
)
2813 cover("kernel.rtlil.sigspec.init.wire");
2815 chunks_
.push_back(RTLIL::SigChunk(wire
));
2816 width_
= chunks_
.back().width
;
2821 RTLIL::SigSpec::SigSpec(RTLIL::Wire
*wire
, int offset
, int width
)
2823 cover("kernel.rtlil.sigspec.init.wire_part");
2825 chunks_
.push_back(RTLIL::SigChunk(wire
, offset
, width
));
2826 width_
= chunks_
.back().width
;
2831 RTLIL::SigSpec::SigSpec(const std::string
&str
)
2833 cover("kernel.rtlil.sigspec.init.str");
2835 chunks_
.push_back(RTLIL::SigChunk(str
));
2836 width_
= chunks_
.back().width
;
2841 RTLIL::SigSpec::SigSpec(int val
, int width
)
2843 cover("kernel.rtlil.sigspec.init.int");
2845 chunks_
.push_back(RTLIL::SigChunk(val
, width
));
2851 RTLIL::SigSpec::SigSpec(RTLIL::State bit
, int width
)
2853 cover("kernel.rtlil.sigspec.init.state");
2855 chunks_
.push_back(RTLIL::SigChunk(bit
, width
));
2861 RTLIL::SigSpec::SigSpec(RTLIL::SigBit bit
, int width
)
2863 cover("kernel.rtlil.sigspec.init.bit");
2865 if (bit
.wire
== NULL
)
2866 chunks_
.push_back(RTLIL::SigChunk(bit
.data
, width
));
2868 for (int i
= 0; i
< width
; i
++)
2869 chunks_
.push_back(bit
);
2875 RTLIL::SigSpec::SigSpec(std::vector
<RTLIL::SigChunk
> chunks
)
2877 cover("kernel.rtlil.sigspec.init.stdvec_chunks");
2881 for (auto &c
: chunks
)
2886 RTLIL::SigSpec::SigSpec(std::vector
<RTLIL::SigBit
> bits
)
2888 cover("kernel.rtlil.sigspec.init.stdvec_bits");
2892 for (auto &bit
: bits
)
2897 RTLIL::SigSpec::SigSpec(pool
<RTLIL::SigBit
> bits
)
2899 cover("kernel.rtlil.sigspec.init.pool_bits");
2903 for (auto &bit
: bits
)
2908 RTLIL::SigSpec::SigSpec(std::set
<RTLIL::SigBit
> bits
)
2910 cover("kernel.rtlil.sigspec.init.stdset_bits");
2914 for (auto &bit
: bits
)
2919 RTLIL::SigSpec::SigSpec(bool bit
)
2921 cover("kernel.rtlil.sigspec.init.bool");
2929 void RTLIL::SigSpec::pack() const
2931 RTLIL::SigSpec
*that
= (RTLIL::SigSpec
*)this;
2933 if (that
->bits_
.empty())
2936 cover("kernel.rtlil.sigspec.convert.pack");
2937 log_assert(that
->chunks_
.empty());
2939 std::vector
<RTLIL::SigBit
> old_bits
;
2940 old_bits
.swap(that
->bits_
);
2942 RTLIL::SigChunk
*last
= NULL
;
2943 int last_end_offset
= 0;
2945 for (auto &bit
: old_bits
) {
2946 if (last
&& bit
.wire
== last
->wire
) {
2947 if (bit
.wire
== NULL
) {
2948 last
->data
.push_back(bit
.data
);
2951 } else if (last_end_offset
== bit
.offset
) {
2957 that
->chunks_
.push_back(bit
);
2958 last
= &that
->chunks_
.back();
2959 last_end_offset
= bit
.offset
+ 1;
2965 void RTLIL::SigSpec::unpack() const
2967 RTLIL::SigSpec
*that
= (RTLIL::SigSpec
*)this;
2969 if (that
->chunks_
.empty())
2972 cover("kernel.rtlil.sigspec.convert.unpack");
2973 log_assert(that
->bits_
.empty());
2975 that
->bits_
.reserve(that
->width_
);
2976 for (auto &c
: that
->chunks_
)
2977 for (int i
= 0; i
< c
.width
; i
++)
2978 that
->bits_
.push_back(RTLIL::SigBit(c
, i
));
2980 that
->chunks_
.clear();
2984 void RTLIL::SigSpec::updhash() const
2986 RTLIL::SigSpec
*that
= (RTLIL::SigSpec
*)this;
2988 if (that
->hash_
!= 0)
2991 cover("kernel.rtlil.sigspec.hash");
2994 that
->hash_
= mkhash_init
;
2995 for (auto &c
: that
->chunks_
)
2996 if (c
.wire
== NULL
) {
2997 for (auto &v
: c
.data
)
2998 that
->hash_
= mkhash(that
->hash_
, v
);
3000 that
->hash_
= mkhash(that
->hash_
, c
.wire
->name
.index_
);
3001 that
->hash_
= mkhash(that
->hash_
, c
.offset
);
3002 that
->hash_
= mkhash(that
->hash_
, c
.width
);
3005 if (that
->hash_
== 0)
3009 void RTLIL::SigSpec::sort()
3012 cover("kernel.rtlil.sigspec.sort");
3013 std::sort(bits_
.begin(), bits_
.end());
3016 void RTLIL::SigSpec::sort_and_unify()
3019 cover("kernel.rtlil.sigspec.sort_and_unify");
3021 // A copy of the bits vector is used to prevent duplicating the logic from
3022 // SigSpec::SigSpec(std::vector<SigBit>). This incurrs an extra copy but
3023 // that isn't showing up as significant in profiles.
3024 std::vector
<SigBit
> unique_bits
= bits_
;
3025 std::sort(unique_bits
.begin(), unique_bits
.end());
3026 auto last
= std::unique(unique_bits
.begin(), unique_bits
.end());
3027 unique_bits
.erase(last
, unique_bits
.end());
3029 *this = unique_bits
;
3032 void RTLIL::SigSpec::replace(const RTLIL::SigSpec
&pattern
, const RTLIL::SigSpec
&with
)
3034 replace(pattern
, with
, this);
3037 void RTLIL::SigSpec::replace(const RTLIL::SigSpec
&pattern
, const RTLIL::SigSpec
&with
, RTLIL::SigSpec
*other
) const
3039 log_assert(other
!= NULL
);
3040 log_assert(width_
== other
->width_
);
3041 log_assert(pattern
.width_
== with
.width_
);
3048 for (int i
= 0; i
< GetSize(pattern
.bits_
); i
++) {
3049 if (pattern
.bits_
[i
].wire
!= NULL
) {
3050 for (int j
= 0; j
< GetSize(bits_
); j
++) {
3051 if (bits_
[j
] == pattern
.bits_
[i
]) {
3052 other
->bits_
[j
] = with
.bits_
[i
];
3061 void RTLIL::SigSpec::replace(const dict
<RTLIL::SigBit
, RTLIL::SigBit
> &rules
)
3063 replace(rules
, this);
3066 void RTLIL::SigSpec::replace(const dict
<RTLIL::SigBit
, RTLIL::SigBit
> &rules
, RTLIL::SigSpec
*other
) const
3068 cover("kernel.rtlil.sigspec.replace_dict");
3070 log_assert(other
!= NULL
);
3071 log_assert(width_
== other
->width_
);
3076 for (int i
= 0; i
< GetSize(bits_
); i
++) {
3077 auto it
= rules
.find(bits_
[i
]);
3078 if (it
!= rules
.end())
3079 other
->bits_
[i
] = it
->second
;
3085 void RTLIL::SigSpec::replace(const std::map
<RTLIL::SigBit
, RTLIL::SigBit
> &rules
)
3087 replace(rules
, this);
3090 void RTLIL::SigSpec::replace(const std::map
<RTLIL::SigBit
, RTLIL::SigBit
> &rules
, RTLIL::SigSpec
*other
) const
3092 cover("kernel.rtlil.sigspec.replace_map");
3094 log_assert(other
!= NULL
);
3095 log_assert(width_
== other
->width_
);
3100 for (int i
= 0; i
< GetSize(bits_
); i
++) {
3101 auto it
= rules
.find(bits_
[i
]);
3102 if (it
!= rules
.end())
3103 other
->bits_
[i
] = it
->second
;
3109 void RTLIL::SigSpec::remove(const RTLIL::SigSpec
&pattern
)
3111 remove2(pattern
, NULL
);
3114 void RTLIL::SigSpec::remove(const RTLIL::SigSpec
&pattern
, RTLIL::SigSpec
*other
) const
3116 RTLIL::SigSpec tmp
= *this;
3117 tmp
.remove2(pattern
, other
);
3120 void RTLIL::SigSpec::remove2(const RTLIL::SigSpec
&pattern
, RTLIL::SigSpec
*other
)
3123 cover("kernel.rtlil.sigspec.remove_other");
3125 cover("kernel.rtlil.sigspec.remove");
3128 if (other
!= NULL
) {
3129 log_assert(width_
== other
->width_
);
3133 for (int i
= GetSize(bits_
) - 1; i
>= 0; i
--)
3135 if (bits_
[i
].wire
== NULL
) continue;
3137 for (auto &pattern_chunk
: pattern
.chunks())
3138 if (bits_
[i
].wire
== pattern_chunk
.wire
&&
3139 bits_
[i
].offset
>= pattern_chunk
.offset
&&
3140 bits_
[i
].offset
< pattern_chunk
.offset
+ pattern_chunk
.width
) {
3141 bits_
.erase(bits_
.begin() + i
);
3143 if (other
!= NULL
) {
3144 other
->bits_
.erase(other
->bits_
.begin() + i
);
3154 void RTLIL::SigSpec::remove(const pool
<RTLIL::SigBit
> &pattern
)
3156 remove2(pattern
, NULL
);
3159 void RTLIL::SigSpec::remove(const pool
<RTLIL::SigBit
> &pattern
, RTLIL::SigSpec
*other
) const
3161 RTLIL::SigSpec tmp
= *this;
3162 tmp
.remove2(pattern
, other
);
3165 void RTLIL::SigSpec::remove2(const pool
<RTLIL::SigBit
> &pattern
, RTLIL::SigSpec
*other
)
3168 cover("kernel.rtlil.sigspec.remove_other");
3170 cover("kernel.rtlil.sigspec.remove");
3174 if (other
!= NULL
) {
3175 log_assert(width_
== other
->width_
);
3179 for (int i
= GetSize(bits_
) - 1; i
>= 0; i
--) {
3180 if (bits_
[i
].wire
!= NULL
&& pattern
.count(bits_
[i
])) {
3181 bits_
.erase(bits_
.begin() + i
);
3183 if (other
!= NULL
) {
3184 other
->bits_
.erase(other
->bits_
.begin() + i
);
3193 void RTLIL::SigSpec::remove2(const std::set
<RTLIL::SigBit
> &pattern
, RTLIL::SigSpec
*other
)
3196 cover("kernel.rtlil.sigspec.remove_other");
3198 cover("kernel.rtlil.sigspec.remove");
3202 if (other
!= NULL
) {
3203 log_assert(width_
== other
->width_
);
3207 for (int i
= GetSize(bits_
) - 1; i
>= 0; i
--) {
3208 if (bits_
[i
].wire
!= NULL
&& pattern
.count(bits_
[i
])) {
3209 bits_
.erase(bits_
.begin() + i
);
3211 if (other
!= NULL
) {
3212 other
->bits_
.erase(other
->bits_
.begin() + i
);
3221 RTLIL::SigSpec
RTLIL::SigSpec::extract(const RTLIL::SigSpec
&pattern
, const RTLIL::SigSpec
*other
) const
3224 cover("kernel.rtlil.sigspec.extract_other");
3226 cover("kernel.rtlil.sigspec.extract");
3228 log_assert(other
== NULL
|| width_
== other
->width_
);
3231 std::vector
<RTLIL::SigBit
> bits_match
= to_sigbit_vector();
3233 for (auto& pattern_chunk
: pattern
.chunks()) {
3235 std::vector
<RTLIL::SigBit
> bits_other
= other
->to_sigbit_vector();
3236 for (int i
= 0; i
< width_
; i
++)
3237 if (bits_match
[i
].wire
&&
3238 bits_match
[i
].wire
== pattern_chunk
.wire
&&
3239 bits_match
[i
].offset
>= pattern_chunk
.offset
&&
3240 bits_match
[i
].offset
< pattern_chunk
.offset
+ pattern_chunk
.width
)
3241 ret
.append_bit(bits_other
[i
]);
3243 for (int i
= 0; i
< width_
; i
++)
3244 if (bits_match
[i
].wire
&&
3245 bits_match
[i
].wire
== pattern_chunk
.wire
&&
3246 bits_match
[i
].offset
>= pattern_chunk
.offset
&&
3247 bits_match
[i
].offset
< pattern_chunk
.offset
+ pattern_chunk
.width
)
3248 ret
.append_bit(bits_match
[i
]);
3256 RTLIL::SigSpec
RTLIL::SigSpec::extract(const pool
<RTLIL::SigBit
> &pattern
, const RTLIL::SigSpec
*other
) const
3259 cover("kernel.rtlil.sigspec.extract_other");
3261 cover("kernel.rtlil.sigspec.extract");
3263 log_assert(other
== NULL
|| width_
== other
->width_
);
3265 std::vector
<RTLIL::SigBit
> bits_match
= to_sigbit_vector();
3269 std::vector
<RTLIL::SigBit
> bits_other
= other
->to_sigbit_vector();
3270 for (int i
= 0; i
< width_
; i
++)
3271 if (bits_match
[i
].wire
&& pattern
.count(bits_match
[i
]))
3272 ret
.append_bit(bits_other
[i
]);
3274 for (int i
= 0; i
< width_
; i
++)
3275 if (bits_match
[i
].wire
&& pattern
.count(bits_match
[i
]))
3276 ret
.append_bit(bits_match
[i
]);
3283 void RTLIL::SigSpec::replace(int offset
, const RTLIL::SigSpec
&with
)
3285 cover("kernel.rtlil.sigspec.replace_pos");
3290 log_assert(offset
>= 0);
3291 log_assert(with
.width_
>= 0);
3292 log_assert(offset
+with
.width_
<= width_
);
3294 for (int i
= 0; i
< with
.width_
; i
++)
3295 bits_
.at(offset
+ i
) = with
.bits_
.at(i
);
3300 void RTLIL::SigSpec::remove_const()
3304 cover("kernel.rtlil.sigspec.remove_const.packed");
3306 std::vector
<RTLIL::SigChunk
> new_chunks
;
3307 new_chunks
.reserve(GetSize(chunks_
));
3310 for (auto &chunk
: chunks_
)
3311 if (chunk
.wire
!= NULL
) {
3312 new_chunks
.push_back(chunk
);
3313 width_
+= chunk
.width
;
3316 chunks_
.swap(new_chunks
);
3320 cover("kernel.rtlil.sigspec.remove_const.unpacked");
3322 std::vector
<RTLIL::SigBit
> new_bits
;
3323 new_bits
.reserve(width_
);
3325 for (auto &bit
: bits_
)
3326 if (bit
.wire
!= NULL
)
3327 new_bits
.push_back(bit
);
3329 bits_
.swap(new_bits
);
3330 width_
= bits_
.size();
3336 void RTLIL::SigSpec::remove(int offset
, int length
)
3338 cover("kernel.rtlil.sigspec.remove_pos");
3342 log_assert(offset
>= 0);
3343 log_assert(length
>= 0);
3344 log_assert(offset
+ length
<= width_
);
3346 bits_
.erase(bits_
.begin() + offset
, bits_
.begin() + offset
+ length
);
3347 width_
= bits_
.size();
3352 RTLIL::SigSpec
RTLIL::SigSpec::extract(int offset
, int length
) const
3355 cover("kernel.rtlil.sigspec.extract_pos");
3356 return std::vector
<RTLIL::SigBit
>(bits_
.begin() + offset
, bits_
.begin() + offset
+ length
);
3359 void RTLIL::SigSpec::append(const RTLIL::SigSpec
&signal
)
3361 if (signal
.width_
== 0)
3369 cover("kernel.rtlil.sigspec.append");
3371 if (packed() != signal
.packed()) {
3377 for (auto &other_c
: signal
.chunks_
)
3379 auto &my_last_c
= chunks_
.back();
3380 if (my_last_c
.wire
== NULL
&& other_c
.wire
== NULL
) {
3381 auto &this_data
= my_last_c
.data
;
3382 auto &other_data
= other_c
.data
;
3383 this_data
.insert(this_data
.end(), other_data
.begin(), other_data
.end());
3384 my_last_c
.width
+= other_c
.width
;
3386 if (my_last_c
.wire
== other_c
.wire
&& my_last_c
.offset
+ my_last_c
.width
== other_c
.offset
) {
3387 my_last_c
.width
+= other_c
.width
;
3389 chunks_
.push_back(other_c
);
3392 bits_
.insert(bits_
.end(), signal
.bits_
.begin(), signal
.bits_
.end());
3394 width_
+= signal
.width_
;
3398 void RTLIL::SigSpec::append_bit(const RTLIL::SigBit
&bit
)
3402 cover("kernel.rtlil.sigspec.append_bit.packed");
3404 if (chunks_
.size() == 0)
3405 chunks_
.push_back(bit
);
3407 if (bit
.wire
== NULL
)
3408 if (chunks_
.back().wire
== NULL
) {
3409 chunks_
.back().data
.push_back(bit
.data
);
3410 chunks_
.back().width
++;
3412 chunks_
.push_back(bit
);
3414 if (chunks_
.back().wire
== bit
.wire
&& chunks_
.back().offset
+ chunks_
.back().width
== bit
.offset
)
3415 chunks_
.back().width
++;
3417 chunks_
.push_back(bit
);
3421 cover("kernel.rtlil.sigspec.append_bit.unpacked");
3422 bits_
.push_back(bit
);
3429 void RTLIL::SigSpec::extend_u0(int width
, bool is_signed
)
3431 cover("kernel.rtlil.sigspec.extend_u0");
3436 remove(width
, width_
- width
);
3438 if (width_
< width
) {
3439 RTLIL::SigBit padding
= width_
> 0 ? (*this)[width_
- 1] : RTLIL::State::Sx
;
3440 if (padding
!= RTLIL::State::Sx
&& !is_signed
)
3441 padding
= RTLIL::State::S0
;
3442 while (width_
< width
)
3448 RTLIL::SigSpec
RTLIL::SigSpec::repeat(int num
) const
3450 cover("kernel.rtlil.sigspec.repeat");
3453 for (int i
= 0; i
< num
; i
++)
3459 void RTLIL::SigSpec::check() const
3463 cover("kernel.rtlil.sigspec.check.skip");
3467 cover("kernel.rtlil.sigspec.check.packed");
3470 for (size_t i
= 0; i
< chunks_
.size(); i
++) {
3471 const RTLIL::SigChunk chunk
= chunks_
[i
];
3472 if (chunk
.wire
== NULL
) {
3474 log_assert(chunks_
[i
-1].wire
!= NULL
);
3475 log_assert(chunk
.offset
== 0);
3476 log_assert(chunk
.data
.size() == (size_t)chunk
.width
);
3478 if (i
> 0 && chunks_
[i
-1].wire
== chunk
.wire
)
3479 log_assert(chunk
.offset
!= chunks_
[i
-1].offset
+ chunks_
[i
-1].width
);
3480 log_assert(chunk
.offset
>= 0);
3481 log_assert(chunk
.width
>= 0);
3482 log_assert(chunk
.offset
+ chunk
.width
<= chunk
.wire
->width
);
3483 log_assert(chunk
.data
.size() == 0);
3487 log_assert(w
== width_
);
3488 log_assert(bits_
.empty());
3492 cover("kernel.rtlil.sigspec.check.unpacked");
3494 log_assert(width_
== GetSize(bits_
));
3495 log_assert(chunks_
.empty());
3500 bool RTLIL::SigSpec::operator <(const RTLIL::SigSpec
&other
) const
3502 cover("kernel.rtlil.sigspec.comp_lt");
3507 if (width_
!= other
.width_
)
3508 return width_
< other
.width_
;
3513 if (chunks_
.size() != other
.chunks_
.size())
3514 return chunks_
.size() < other
.chunks_
.size();
3519 if (hash_
!= other
.hash_
)
3520 return hash_
< other
.hash_
;
3522 for (size_t i
= 0; i
< chunks_
.size(); i
++)
3523 if (chunks_
[i
] != other
.chunks_
[i
]) {
3524 cover("kernel.rtlil.sigspec.comp_lt.hash_collision");
3525 return chunks_
[i
] < other
.chunks_
[i
];
3528 cover("kernel.rtlil.sigspec.comp_lt.equal");
3532 bool RTLIL::SigSpec::operator ==(const RTLIL::SigSpec
&other
) const
3534 cover("kernel.rtlil.sigspec.comp_eq");
3539 if (width_
!= other
.width_
)
3545 if (chunks_
.size() != other
.chunks_
.size())
3551 if (hash_
!= other
.hash_
)
3554 for (size_t i
= 0; i
< chunks_
.size(); i
++)
3555 if (chunks_
[i
] != other
.chunks_
[i
]) {
3556 cover("kernel.rtlil.sigspec.comp_eq.hash_collision");
3560 cover("kernel.rtlil.sigspec.comp_eq.equal");
3564 bool RTLIL::SigSpec::is_wire() const
3566 cover("kernel.rtlil.sigspec.is_wire");
3569 return GetSize(chunks_
) == 1 && chunks_
[0].wire
&& chunks_
[0].wire
->width
== width_
;
3572 bool RTLIL::SigSpec::is_chunk() const
3574 cover("kernel.rtlil.sigspec.is_chunk");
3577 return GetSize(chunks_
) == 1;
3580 bool RTLIL::SigSpec::is_fully_const() const
3582 cover("kernel.rtlil.sigspec.is_fully_const");
3585 for (auto it
= chunks_
.begin(); it
!= chunks_
.end(); it
++)
3586 if (it
->width
> 0 && it
->wire
!= NULL
)
3591 bool RTLIL::SigSpec::is_fully_zero() const
3593 cover("kernel.rtlil.sigspec.is_fully_zero");
3596 for (auto it
= chunks_
.begin(); it
!= chunks_
.end(); it
++) {
3597 if (it
->width
> 0 && it
->wire
!= NULL
)
3599 for (size_t i
= 0; i
< it
->data
.size(); i
++)
3600 if (it
->data
[i
] != RTLIL::State::S0
)
3606 bool RTLIL::SigSpec::is_fully_ones() const
3608 cover("kernel.rtlil.sigspec.is_fully_ones");
3611 for (auto it
= chunks_
.begin(); it
!= chunks_
.end(); it
++) {
3612 if (it
->width
> 0 && it
->wire
!= NULL
)
3614 for (size_t i
= 0; i
< it
->data
.size(); i
++)
3615 if (it
->data
[i
] != RTLIL::State::S1
)
3621 bool RTLIL::SigSpec::is_fully_def() const
3623 cover("kernel.rtlil.sigspec.is_fully_def");
3626 for (auto it
= chunks_
.begin(); it
!= chunks_
.end(); it
++) {
3627 if (it
->width
> 0 && it
->wire
!= NULL
)
3629 for (size_t i
= 0; i
< it
->data
.size(); i
++)
3630 if (it
->data
[i
] != RTLIL::State::S0
&& it
->data
[i
] != RTLIL::State::S1
)
3636 bool RTLIL::SigSpec::is_fully_undef() const
3638 cover("kernel.rtlil.sigspec.is_fully_undef");
3641 for (auto it
= chunks_
.begin(); it
!= chunks_
.end(); it
++) {
3642 if (it
->width
> 0 && it
->wire
!= NULL
)
3644 for (size_t i
= 0; i
< it
->data
.size(); i
++)
3645 if (it
->data
[i
] != RTLIL::State::Sx
&& it
->data
[i
] != RTLIL::State::Sz
)
3651 bool RTLIL::SigSpec::has_const() const
3653 cover("kernel.rtlil.sigspec.has_const");
3656 for (auto it
= chunks_
.begin(); it
!= chunks_
.end(); it
++)
3657 if (it
->width
> 0 && it
->wire
== NULL
)
3662 bool RTLIL::SigSpec::has_marked_bits() const
3664 cover("kernel.rtlil.sigspec.has_marked_bits");
3667 for (auto it
= chunks_
.begin(); it
!= chunks_
.end(); it
++)
3668 if (it
->width
> 0 && it
->wire
== NULL
) {
3669 for (size_t i
= 0; i
< it
->data
.size(); i
++)
3670 if (it
->data
[i
] == RTLIL::State::Sm
)
3676 bool RTLIL::SigSpec::as_bool() const
3678 cover("kernel.rtlil.sigspec.as_bool");
3681 log_assert(is_fully_const() && GetSize(chunks_
) <= 1);
3683 return RTLIL::Const(chunks_
[0].data
).as_bool();
3687 int RTLIL::SigSpec::as_int(bool is_signed
) const
3689 cover("kernel.rtlil.sigspec.as_int");
3692 log_assert(is_fully_const() && GetSize(chunks_
) <= 1);
3694 return RTLIL::Const(chunks_
[0].data
).as_int(is_signed
);
3698 std::string
RTLIL::SigSpec::as_string() const
3700 cover("kernel.rtlil.sigspec.as_string");
3704 for (size_t i
= chunks_
.size(); i
> 0; i
--) {
3705 const RTLIL::SigChunk
&chunk
= chunks_
[i
-1];
3706 if (chunk
.wire
!= NULL
)
3707 for (int j
= 0; j
< chunk
.width
; j
++)
3710 str
+= RTLIL::Const(chunk
.data
).as_string();
3715 RTLIL::Const
RTLIL::SigSpec::as_const() const
3717 cover("kernel.rtlil.sigspec.as_const");
3720 log_assert(is_fully_const() && GetSize(chunks_
) <= 1);
3722 return chunks_
[0].data
;
3723 return RTLIL::Const();
3726 RTLIL::Wire
*RTLIL::SigSpec::as_wire() const
3728 cover("kernel.rtlil.sigspec.as_wire");
3731 log_assert(is_wire());
3732 return chunks_
[0].wire
;
3735 RTLIL::SigChunk
RTLIL::SigSpec::as_chunk() const
3737 cover("kernel.rtlil.sigspec.as_chunk");
3740 log_assert(is_chunk());
3744 RTLIL::SigBit
RTLIL::SigSpec::as_bit() const
3746 cover("kernel.rtlil.sigspec.as_bit");
3748 log_assert(width_
== 1);
3750 return RTLIL::SigBit(*chunks_
.begin());
3755 bool RTLIL::SigSpec::match(std::string pattern
) const
3757 cover("kernel.rtlil.sigspec.match");
3760 std::string str
= as_string();
3761 log_assert(pattern
.size() == str
.size());
3763 for (size_t i
= 0; i
< pattern
.size(); i
++) {
3764 if (pattern
[i
] == ' ')
3766 if (pattern
[i
] == '*') {
3767 if (str
[i
] != 'z' && str
[i
] != 'x')
3771 if (pattern
[i
] != str
[i
])
3778 std::set
<RTLIL::SigBit
> RTLIL::SigSpec::to_sigbit_set() const
3780 cover("kernel.rtlil.sigspec.to_sigbit_set");
3783 std::set
<RTLIL::SigBit
> sigbits
;
3784 for (auto &c
: chunks_
)
3785 for (int i
= 0; i
< c
.width
; i
++)
3786 sigbits
.insert(RTLIL::SigBit(c
, i
));
3790 pool
<RTLIL::SigBit
> RTLIL::SigSpec::to_sigbit_pool() const
3792 cover("kernel.rtlil.sigspec.to_sigbit_pool");
3795 pool
<RTLIL::SigBit
> sigbits
;
3796 for (auto &c
: chunks_
)
3797 for (int i
= 0; i
< c
.width
; i
++)
3798 sigbits
.insert(RTLIL::SigBit(c
, i
));
3802 std::vector
<RTLIL::SigBit
> RTLIL::SigSpec::to_sigbit_vector() const
3804 cover("kernel.rtlil.sigspec.to_sigbit_vector");
3810 std::map
<RTLIL::SigBit
, RTLIL::SigBit
> RTLIL::SigSpec::to_sigbit_map(const RTLIL::SigSpec
&other
) const
3812 cover("kernel.rtlil.sigspec.to_sigbit_map");
3817 log_assert(width_
== other
.width_
);
3819 std::map
<RTLIL::SigBit
, RTLIL::SigBit
> new_map
;
3820 for (int i
= 0; i
< width_
; i
++)
3821 new_map
[bits_
[i
]] = other
.bits_
[i
];
3826 dict
<RTLIL::SigBit
, RTLIL::SigBit
> RTLIL::SigSpec::to_sigbit_dict(const RTLIL::SigSpec
&other
) const
3828 cover("kernel.rtlil.sigspec.to_sigbit_dict");
3833 log_assert(width_
== other
.width_
);
3835 dict
<RTLIL::SigBit
, RTLIL::SigBit
> new_map
;
3836 for (int i
= 0; i
< width_
; i
++)
3837 new_map
[bits_
[i
]] = other
.bits_
[i
];
3842 static void sigspec_parse_split(std::vector
<std::string
> &tokens
, const std::string
&text
, char sep
)
3844 size_t start
= 0, end
= 0;
3845 while ((end
= text
.find(sep
, start
)) != std::string::npos
) {
3846 tokens
.push_back(text
.substr(start
, end
- start
));
3849 tokens
.push_back(text
.substr(start
));
3852 static int sigspec_parse_get_dummy_line_num()
3857 bool RTLIL::SigSpec::parse(RTLIL::SigSpec
&sig
, RTLIL::Module
*module
, std::string str
)
3859 cover("kernel.rtlil.sigspec.parse");
3861 AST::current_filename
= "input";
3862 AST::use_internal_line_num();
3863 AST::set_line_num(0);
3865 std::vector
<std::string
> tokens
;
3866 sigspec_parse_split(tokens
, str
, ',');
3868 sig
= RTLIL::SigSpec();
3869 for (int tokidx
= int(tokens
.size())-1; tokidx
>= 0; tokidx
--)
3871 std::string netname
= tokens
[tokidx
];
3872 std::string indices
;
3874 if (netname
.size() == 0)
3877 if (('0' <= netname
[0] && netname
[0] <= '9') || netname
[0] == '\'') {
3878 cover("kernel.rtlil.sigspec.parse.const");
3879 AST::get_line_num
= sigspec_parse_get_dummy_line_num
;
3880 AST::AstNode
*ast
= VERILOG_FRONTEND::const2ast(netname
);
3883 sig
.append(RTLIL::Const(ast
->bits
));
3891 cover("kernel.rtlil.sigspec.parse.net");
3893 if (netname
[0] != '$' && netname
[0] != '\\')
3894 netname
= "\\" + netname
;
3896 if (module
->wires_
.count(netname
) == 0) {
3897 size_t indices_pos
= netname
.size()-1;
3898 if (indices_pos
> 2 && netname
[indices_pos
] == ']')
3901 while (indices_pos
> 0 && ('0' <= netname
[indices_pos
] && netname
[indices_pos
] <= '9')) indices_pos
--;
3902 if (indices_pos
> 0 && netname
[indices_pos
] == ':') {
3904 while (indices_pos
> 0 && ('0' <= netname
[indices_pos
] && netname
[indices_pos
] <= '9')) indices_pos
--;
3906 if (indices_pos
> 0 && netname
[indices_pos
] == '[') {
3907 indices
= netname
.substr(indices_pos
);
3908 netname
= netname
.substr(0, indices_pos
);
3913 if (module
->wires_
.count(netname
) == 0)
3916 RTLIL::Wire
*wire
= module
->wires_
.at(netname
);
3917 if (!indices
.empty()) {
3918 std::vector
<std::string
> index_tokens
;
3919 sigspec_parse_split(index_tokens
, indices
.substr(1, indices
.size()-2), ':');
3920 if (index_tokens
.size() == 1) {
3921 cover("kernel.rtlil.sigspec.parse.bit_sel");
3922 int a
= atoi(index_tokens
.at(0).c_str());
3923 if (a
< 0 || a
>= wire
->width
)
3925 sig
.append(RTLIL::SigSpec(wire
, a
));
3927 cover("kernel.rtlil.sigspec.parse.part_sel");
3928 int a
= atoi(index_tokens
.at(0).c_str());
3929 int b
= atoi(index_tokens
.at(1).c_str());
3934 if (a
< 0 || a
>= wire
->width
)
3936 if (b
< 0 || b
>= wire
->width
)
3938 sig
.append(RTLIL::SigSpec(wire
, a
, b
-a
+1));
3947 bool RTLIL::SigSpec::parse_sel(RTLIL::SigSpec
&sig
, RTLIL::Design
*design
, RTLIL::Module
*module
, std::string str
)
3949 if (str
.empty() || str
[0] != '@')
3950 return parse(sig
, module
, str
);
3952 cover("kernel.rtlil.sigspec.parse.sel");
3954 str
= RTLIL::escape_id(str
.substr(1));
3955 if (design
->selection_vars
.count(str
) == 0)
3958 sig
= RTLIL::SigSpec();
3959 RTLIL::Selection
&sel
= design
->selection_vars
.at(str
);
3960 for (auto &it
: module
->wires_
)
3961 if (sel
.selected_member(module
->name
, it
.first
))
3962 sig
.append(it
.second
);
3967 bool RTLIL::SigSpec::parse_rhs(const RTLIL::SigSpec
&lhs
, RTLIL::SigSpec
&sig
, RTLIL::Module
*module
, std::string str
)
3970 cover("kernel.rtlil.sigspec.parse.rhs_zeros");
3971 sig
= RTLIL::SigSpec(RTLIL::State::S0
, lhs
.width_
);
3976 cover("kernel.rtlil.sigspec.parse.rhs_ones");
3977 sig
= RTLIL::SigSpec(RTLIL::State::S1
, lhs
.width_
);
3981 if (lhs
.chunks_
.size() == 1) {
3982 char *p
= (char*)str
.c_str(), *endptr
;
3983 long int val
= strtol(p
, &endptr
, 10);
3984 if (endptr
&& endptr
!= p
&& *endptr
== 0) {
3985 sig
= RTLIL::SigSpec(val
, lhs
.width_
);
3986 cover("kernel.rtlil.sigspec.parse.rhs_dec");
3991 return parse(sig
, module
, str
);
3994 RTLIL::CaseRule::~CaseRule()
3996 for (auto it
= switches
.begin(); it
!= switches
.end(); it
++)
4000 bool RTLIL::CaseRule::empty() const
4002 return actions
.empty() && switches
.empty();
4005 RTLIL::CaseRule
*RTLIL::CaseRule::clone() const
4007 RTLIL::CaseRule
*new_caserule
= new RTLIL::CaseRule
;
4008 new_caserule
->compare
= compare
;
4009 new_caserule
->actions
= actions
;
4010 for (auto &it
: switches
)
4011 new_caserule
->switches
.push_back(it
->clone());
4012 return new_caserule
;
4015 RTLIL::SwitchRule::~SwitchRule()
4017 for (auto it
= cases
.begin(); it
!= cases
.end(); it
++)
4021 bool RTLIL::SwitchRule::empty() const
4023 return cases
.empty();
4026 RTLIL::SwitchRule
*RTLIL::SwitchRule::clone() const
4028 RTLIL::SwitchRule
*new_switchrule
= new RTLIL::SwitchRule
;
4029 new_switchrule
->signal
= signal
;
4030 new_switchrule
->attributes
= attributes
;
4031 for (auto &it
: cases
)
4032 new_switchrule
->cases
.push_back(it
->clone());
4033 return new_switchrule
;
4037 RTLIL::SyncRule
*RTLIL::SyncRule::clone() const
4039 RTLIL::SyncRule
*new_syncrule
= new RTLIL::SyncRule
;
4040 new_syncrule
->type
= type
;
4041 new_syncrule
->signal
= signal
;
4042 new_syncrule
->actions
= actions
;
4043 return new_syncrule
;
4046 RTLIL::Process::~Process()
4048 for (auto it
= syncs
.begin(); it
!= syncs
.end(); it
++)
4052 RTLIL::Process
*RTLIL::Process::clone() const
4054 RTLIL::Process
*new_proc
= new RTLIL::Process
;
4056 new_proc
->name
= name
;
4057 new_proc
->attributes
= attributes
;
4059 RTLIL::CaseRule
*rc_ptr
= root_case
.clone();
4060 new_proc
->root_case
= *rc_ptr
;
4061 rc_ptr
->switches
.clear();
4064 for (auto &it
: syncs
)
4065 new_proc
->syncs
.push_back(it
->clone());
4071 RTLIL::Memory::~Memory()
4073 RTLIL::Memory::get_all_memorys()->erase(hashidx_
);
4075 static std::map
<unsigned int, RTLIL::Memory
*> all_memorys
;
4076 std::map
<unsigned int, RTLIL::Memory
*> *RTLIL::Memory::get_all_memorys(void)
4078 return &all_memorys
;