2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include "kernel/yosys.h"
21 #include "kernel/macc.h"
22 #include "kernel/celltypes.h"
23 #include "frontends/verilog/verilog_frontend.h"
24 #include "backends/ilang/ilang_backend.h"
31 RTLIL::IdString::destruct_guard_t
RTLIL::IdString::destruct_guard
;
32 std::vector
<int> RTLIL::IdString::global_refcount_storage_
;
33 std::vector
<char*> RTLIL::IdString::global_id_storage_
;
34 dict
<char*, int, hash_cstr_ops
> RTLIL::IdString::global_id_index_
;
35 std::vector
<int> RTLIL::IdString::global_free_idx_list_
;
36 int RTLIL::IdString::last_created_idx_
[8];
37 int RTLIL::IdString::last_created_idx_ptr_
;
41 flags
= RTLIL::CONST_FLAG_NONE
;
44 RTLIL::Const::Const(std::string str
)
46 flags
= RTLIL::CONST_FLAG_STRING
;
47 for (int i
= str
.size()-1; i
>= 0; i
--) {
48 unsigned char ch
= str
[i
];
49 for (int j
= 0; j
< 8; j
++) {
50 bits
.push_back((ch
& 1) != 0 ? RTLIL::S1
: RTLIL::S0
);
56 RTLIL::Const::Const(int val
, int width
)
58 flags
= RTLIL::CONST_FLAG_NONE
;
59 for (int i
= 0; i
< width
; i
++) {
60 bits
.push_back((val
& 1) != 0 ? RTLIL::S1
: RTLIL::S0
);
65 RTLIL::Const::Const(RTLIL::State bit
, int width
)
67 flags
= RTLIL::CONST_FLAG_NONE
;
68 for (int i
= 0; i
< width
; i
++)
72 RTLIL::Const::Const(const std::vector
<bool> &bits
)
74 flags
= RTLIL::CONST_FLAG_NONE
;
76 this->bits
.push_back(b
? RTLIL::S1
: RTLIL::S0
);
79 bool RTLIL::Const::operator <(const RTLIL::Const
&other
) const
81 if (bits
.size() != other
.bits
.size())
82 return bits
.size() < other
.bits
.size();
83 for (size_t i
= 0; i
< bits
.size(); i
++)
84 if (bits
[i
] != other
.bits
[i
])
85 return bits
[i
] < other
.bits
[i
];
89 bool RTLIL::Const::operator ==(const RTLIL::Const
&other
) const
91 return bits
== other
.bits
;
94 bool RTLIL::Const::operator !=(const RTLIL::Const
&other
) const
96 return bits
!= other
.bits
;
99 bool RTLIL::Const::as_bool() const
101 for (size_t i
= 0; i
< bits
.size(); i
++)
102 if (bits
[i
] == RTLIL::S1
)
107 int RTLIL::Const::as_int(bool is_signed
) const
110 for (size_t i
= 0; i
< bits
.size() && i
< 32; i
++)
111 if (bits
[i
] == RTLIL::S1
)
113 if (is_signed
&& bits
.back() == RTLIL::S1
)
114 for (size_t i
= bits
.size(); i
< 32; i
++)
119 std::string
RTLIL::Const::as_string() const
122 for (size_t i
= bits
.size(); i
> 0; i
--)
124 case S0
: ret
+= "0"; break;
125 case S1
: ret
+= "1"; break;
126 case Sx
: ret
+= "x"; break;
127 case Sz
: ret
+= "z"; break;
128 case Sa
: ret
+= "-"; break;
129 case Sm
: ret
+= "m"; break;
134 RTLIL::Const
RTLIL::Const::from_string(std::string str
)
137 for (auto it
= str
.rbegin(); it
!= str
.rend(); it
++)
139 case '0': c
.bits
.push_back(State::S0
); break;
140 case '1': c
.bits
.push_back(State::S1
); break;
141 case 'x': c
.bits
.push_back(State::Sx
); break;
142 case 'z': c
.bits
.push_back(State::Sz
); break;
143 case 'm': c
.bits
.push_back(State::Sm
); break;
144 default: c
.bits
.push_back(State::Sa
);
149 std::string
RTLIL::Const::decode_string() const
152 std::vector
<char> string_chars
;
153 for (int i
= 0; i
< int (bits
.size()); i
+= 8) {
155 for (int j
= 0; j
< 8 && i
+ j
< int (bits
.size()); j
++)
156 if (bits
[i
+ j
] == RTLIL::State::S1
)
159 string_chars
.push_back(ch
);
161 for (int i
= int (string_chars
.size()) - 1; i
>= 0; i
--)
162 string
+= string_chars
[i
];
166 bool RTLIL::Const::is_fully_zero() const
168 cover("kernel.rtlil.const.is_fully_zero");
170 for (auto bit
: bits
)
171 if (bit
!= RTLIL::State::S0
)
177 bool RTLIL::Const::is_fully_ones() const
179 cover("kernel.rtlil.const.is_fully_ones");
181 for (auto bit
: bits
)
182 if (bit
!= RTLIL::State::S1
)
188 bool RTLIL::Const::is_fully_def() const
190 cover("kernel.rtlil.const.is_fully_def");
192 for (auto bit
: bits
)
193 if (bit
!= RTLIL::State::S0
&& bit
!= RTLIL::State::S1
)
199 bool RTLIL::Const::is_fully_undef() const
201 cover("kernel.rtlil.const.is_fully_undef");
203 for (auto bit
: bits
)
204 if (bit
!= RTLIL::State::Sx
&& bit
!= RTLIL::State::Sz
)
210 void RTLIL::AttrObject::set_bool_attribute(RTLIL::IdString id
)
212 attributes
[id
] = RTLIL::Const(1);
215 bool RTLIL::AttrObject::get_bool_attribute(RTLIL::IdString id
) const
217 if (attributes
.count(id
) == 0)
219 return attributes
.at(id
).as_bool();
222 void RTLIL::AttrObject::set_strpool_attribute(RTLIL::IdString id
, const pool
<string
> &data
)
225 for (auto &s
: data
) {
226 if (!attrval
.empty())
230 attributes
[id
] = RTLIL::Const(attrval
);
233 void RTLIL::AttrObject::add_strpool_attribute(RTLIL::IdString id
, const pool
<string
> &data
)
235 pool
<string
> union_data
= get_strpool_attribute(id
);
236 union_data
.insert(data
.begin(), data
.end());
237 if (!union_data
.empty())
238 set_strpool_attribute(id
, union_data
);
241 pool
<string
> RTLIL::AttrObject::get_strpool_attribute(RTLIL::IdString id
) const
244 if (attributes
.count(id
) != 0)
245 for (auto s
: split_tokens(attributes
.at(id
).decode_string(), "|"))
250 void RTLIL::AttrObject::set_src_attribute(const std::string
&src
)
253 attributes
.erase("\\src");
255 attributes
["\\src"] = src
;
258 std::string
RTLIL::AttrObject::get_src_attribute() const
261 if (attributes
.count("\\src"))
262 src
= attributes
.at("\\src").decode_string();
266 bool RTLIL::Selection::selected_module(RTLIL::IdString mod_name
) const
270 if (selected_modules
.count(mod_name
) > 0)
272 if (selected_members
.count(mod_name
) > 0)
277 bool RTLIL::Selection::selected_whole_module(RTLIL::IdString mod_name
) const
281 if (selected_modules
.count(mod_name
) > 0)
286 bool RTLIL::Selection::selected_member(RTLIL::IdString mod_name
, RTLIL::IdString memb_name
) const
290 if (selected_modules
.count(mod_name
) > 0)
292 if (selected_members
.count(mod_name
) > 0)
293 if (selected_members
.at(mod_name
).count(memb_name
) > 0)
298 void RTLIL::Selection::optimize(RTLIL::Design
*design
)
300 if (full_selection
) {
301 selected_modules
.clear();
302 selected_members
.clear();
306 std::vector
<RTLIL::IdString
> del_list
, add_list
;
309 for (auto mod_name
: selected_modules
) {
310 if (design
->modules_
.count(mod_name
) == 0)
311 del_list
.push_back(mod_name
);
312 selected_members
.erase(mod_name
);
314 for (auto mod_name
: del_list
)
315 selected_modules
.erase(mod_name
);
318 for (auto &it
: selected_members
)
319 if (design
->modules_
.count(it
.first
) == 0)
320 del_list
.push_back(it
.first
);
321 for (auto mod_name
: del_list
)
322 selected_members
.erase(mod_name
);
324 for (auto &it
: selected_members
) {
326 for (auto memb_name
: it
.second
)
327 if (design
->modules_
[it
.first
]->count_id(memb_name
) == 0)
328 del_list
.push_back(memb_name
);
329 for (auto memb_name
: del_list
)
330 it
.second
.erase(memb_name
);
335 for (auto &it
: selected_members
)
336 if (it
.second
.size() == 0)
337 del_list
.push_back(it
.first
);
338 else if (it
.second
.size() == design
->modules_
[it
.first
]->wires_
.size() + design
->modules_
[it
.first
]->memories
.size() +
339 design
->modules_
[it
.first
]->cells_
.size() + design
->modules_
[it
.first
]->processes
.size())
340 add_list
.push_back(it
.first
);
341 for (auto mod_name
: del_list
)
342 selected_members
.erase(mod_name
);
343 for (auto mod_name
: add_list
) {
344 selected_members
.erase(mod_name
);
345 selected_modules
.insert(mod_name
);
348 if (selected_modules
.size() == design
->modules_
.size()) {
349 full_selection
= true;
350 selected_modules
.clear();
351 selected_members
.clear();
355 RTLIL::Design::Design()
357 static unsigned int hashidx_count
= 123456789;
358 hashidx_count
= mkhash_xorshift(hashidx_count
);
359 hashidx_
= hashidx_count
;
361 refcount_modules_
= 0;
362 selection_stack
.push_back(RTLIL::Selection());
365 RTLIL::Design::~Design()
367 for (auto it
= modules_
.begin(); it
!= modules_
.end(); ++it
)
369 for (auto n
: verilog_packages
)
371 for (auto n
: verilog_globals
)
375 RTLIL::ObjRange
<RTLIL::Module
*> RTLIL::Design::modules()
377 return RTLIL::ObjRange
<RTLIL::Module
*>(&modules_
, &refcount_modules_
);
380 RTLIL::Module
*RTLIL::Design::module(RTLIL::IdString name
)
382 return modules_
.count(name
) ? modules_
.at(name
) : NULL
;
385 RTLIL::Module
*RTLIL::Design::top_module()
387 RTLIL::Module
*module
= nullptr;
388 int module_count
= 0;
390 for (auto mod
: selected_modules()) {
391 if (mod
->get_bool_attribute("\\top"))
397 return module_count
== 1 ? module
: nullptr;
400 void RTLIL::Design::add(RTLIL::Module
*module
)
402 log_assert(modules_
.count(module
->name
) == 0);
403 log_assert(refcount_modules_
== 0);
404 modules_
[module
->name
] = module
;
405 module
->design
= this;
407 for (auto mon
: monitors
)
408 mon
->notify_module_add(module
);
411 log("#X# New Module: %s\n", log_id(module
));
412 log_backtrace("-X- ", yosys_xtrace
-1);
416 RTLIL::Module
*RTLIL::Design::addModule(RTLIL::IdString name
)
418 log_assert(modules_
.count(name
) == 0);
419 log_assert(refcount_modules_
== 0);
421 RTLIL::Module
*module
= new RTLIL::Module
;
422 modules_
[name
] = module
;
423 module
->design
= this;
426 for (auto mon
: monitors
)
427 mon
->notify_module_add(module
);
430 log("#X# New Module: %s\n", log_id(module
));
431 log_backtrace("-X- ", yosys_xtrace
-1);
437 void RTLIL::Design::scratchpad_unset(std::string varname
)
439 scratchpad
.erase(varname
);
442 void RTLIL::Design::scratchpad_set_int(std::string varname
, int value
)
444 scratchpad
[varname
] = stringf("%d", value
);
447 void RTLIL::Design::scratchpad_set_bool(std::string varname
, bool value
)
449 scratchpad
[varname
] = value
? "true" : "false";
452 void RTLIL::Design::scratchpad_set_string(std::string varname
, std::string value
)
454 scratchpad
[varname
] = value
;
457 int RTLIL::Design::scratchpad_get_int(std::string varname
, int default_value
) const
459 if (scratchpad
.count(varname
) == 0)
460 return default_value
;
462 std::string str
= scratchpad
.at(varname
);
464 if (str
== "0" || str
== "false")
467 if (str
== "1" || str
== "true")
470 char *endptr
= nullptr;
471 long int parsed_value
= strtol(str
.c_str(), &endptr
, 10);
472 return *endptr
? default_value
: parsed_value
;
475 bool RTLIL::Design::scratchpad_get_bool(std::string varname
, bool default_value
) const
477 if (scratchpad
.count(varname
) == 0)
478 return default_value
;
480 std::string str
= scratchpad
.at(varname
);
482 if (str
== "0" || str
== "false")
485 if (str
== "1" || str
== "true")
488 return default_value
;
491 std::string
RTLIL::Design::scratchpad_get_string(std::string varname
, std::string default_value
) const
493 if (scratchpad
.count(varname
) == 0)
494 return default_value
;
495 return scratchpad
.at(varname
);
498 void RTLIL::Design::remove(RTLIL::Module
*module
)
500 for (auto mon
: monitors
)
501 mon
->notify_module_del(module
);
504 log("#X# Remove Module: %s\n", log_id(module
));
505 log_backtrace("-X- ", yosys_xtrace
-1);
508 log_assert(modules_
.at(module
->name
) == module
);
509 modules_
.erase(module
->name
);
513 void RTLIL::Design::rename(RTLIL::Module
*module
, RTLIL::IdString new_name
)
515 modules_
.erase(module
->name
);
516 module
->name
= new_name
;
520 void RTLIL::Design::sort()
523 modules_
.sort(sort_by_id_str());
524 for (auto &it
: modules_
)
528 void RTLIL::Design::check()
531 for (auto &it
: modules_
) {
532 log_assert(this == it
.second
->design
);
533 log_assert(it
.first
== it
.second
->name
);
534 log_assert(!it
.first
.empty());
540 void RTLIL::Design::optimize()
542 for (auto &it
: modules_
)
543 it
.second
->optimize();
544 for (auto &it
: selection_stack
)
546 for (auto &it
: selection_vars
)
547 it
.second
.optimize(this);
550 bool RTLIL::Design::selected_module(RTLIL::IdString mod_name
) const
552 if (!selected_active_module
.empty() && mod_name
!= selected_active_module
)
554 if (selection_stack
.size() == 0)
556 return selection_stack
.back().selected_module(mod_name
);
559 bool RTLIL::Design::selected_whole_module(RTLIL::IdString mod_name
) const
561 if (!selected_active_module
.empty() && mod_name
!= selected_active_module
)
563 if (selection_stack
.size() == 0)
565 return selection_stack
.back().selected_whole_module(mod_name
);
568 bool RTLIL::Design::selected_member(RTLIL::IdString mod_name
, RTLIL::IdString memb_name
) const
570 if (!selected_active_module
.empty() && mod_name
!= selected_active_module
)
572 if (selection_stack
.size() == 0)
574 return selection_stack
.back().selected_member(mod_name
, memb_name
);
577 bool RTLIL::Design::selected_module(RTLIL::Module
*mod
) const
579 return selected_module(mod
->name
);
582 bool RTLIL::Design::selected_whole_module(RTLIL::Module
*mod
) const
584 return selected_whole_module(mod
->name
);
587 std::vector
<RTLIL::Module
*> RTLIL::Design::selected_modules() const
589 std::vector
<RTLIL::Module
*> result
;
590 result
.reserve(modules_
.size());
591 for (auto &it
: modules_
)
592 if (selected_module(it
.first
) && !it
.second
->get_bool_attribute("\\blackbox"))
593 result
.push_back(it
.second
);
597 std::vector
<RTLIL::Module
*> RTLIL::Design::selected_whole_modules() const
599 std::vector
<RTLIL::Module
*> result
;
600 result
.reserve(modules_
.size());
601 for (auto &it
: modules_
)
602 if (selected_whole_module(it
.first
) && !it
.second
->get_bool_attribute("\\blackbox"))
603 result
.push_back(it
.second
);
607 std::vector
<RTLIL::Module
*> RTLIL::Design::selected_whole_modules_warn() const
609 std::vector
<RTLIL::Module
*> result
;
610 result
.reserve(modules_
.size());
611 for (auto &it
: modules_
)
612 if (it
.second
->get_bool_attribute("\\blackbox"))
614 else if (selected_whole_module(it
.first
))
615 result
.push_back(it
.second
);
616 else if (selected_module(it
.first
))
617 log_warning("Ignoring partially selected module %s.\n", log_id(it
.first
));
621 RTLIL::Module::Module()
623 static unsigned int hashidx_count
= 123456789;
624 hashidx_count
= mkhash_xorshift(hashidx_count
);
625 hashidx_
= hashidx_count
;
632 RTLIL::Module::~Module()
634 for (auto it
= wires_
.begin(); it
!= wires_
.end(); ++it
)
636 for (auto it
= memories
.begin(); it
!= memories
.end(); ++it
)
638 for (auto it
= cells_
.begin(); it
!= cells_
.end(); ++it
)
640 for (auto it
= processes
.begin(); it
!= processes
.end(); ++it
)
644 void RTLIL::Module::reprocess_module(RTLIL::Design
*, dict
<RTLIL::IdString
, RTLIL::Module
*>)
646 log_error("Cannot reprocess_module module `%s' !\n", id2cstr(name
));
649 RTLIL::IdString
RTLIL::Module::derive(RTLIL::Design
*, dict
<RTLIL::IdString
, RTLIL::Const
>, bool mayfail
)
652 return RTLIL::IdString();
653 log_error("Module `%s' is used with parameters but is not parametric!\n", id2cstr(name
));
657 RTLIL::IdString
RTLIL::Module::derive(RTLIL::Design
*, dict
<RTLIL::IdString
, RTLIL::Const
>, dict
<RTLIL::IdString
, RTLIL::Module
*>, dict
<RTLIL::IdString
, RTLIL::IdString
>, bool mayfail
)
660 return RTLIL::IdString();
661 log_error("Module `%s' is used with parameters but is not parametric!\n", id2cstr(name
));
664 size_t RTLIL::Module::count_id(RTLIL::IdString id
)
666 return wires_
.count(id
) + memories
.count(id
) + cells_
.count(id
) + processes
.count(id
);
671 struct InternalCellChecker
673 RTLIL::Module
*module
;
675 pool
<RTLIL::IdString
> expected_params
, expected_ports
;
677 InternalCellChecker(RTLIL::Module
*module
, RTLIL::Cell
*cell
) : module(module
), cell(cell
) { }
679 void error(int linenr
)
681 std::stringstream buf
;
682 ILANG_BACKEND::dump_cell(buf
, " ", cell
);
684 log_error("Found error in internal cell %s%s%s (%s) at %s:%d:\n%s",
685 module
? module
->name
.c_str() : "", module
? "." : "",
686 cell
->name
.c_str(), cell
->type
.c_str(), __FILE__
, linenr
, buf
.str().c_str());
689 int param(const char *name
)
691 if (cell
->parameters
.count(name
) == 0)
693 expected_params
.insert(name
);
694 return cell
->parameters
.at(name
).as_int();
697 int param_bool(const char *name
)
700 if (cell
->parameters
.at(name
).bits
.size() > 32)
702 if (v
!= 0 && v
!= 1)
707 void param_bits(const char *name
, int width
)
710 if (int(cell
->parameters
.at(name
).bits
.size()) != width
)
714 void port(const char *name
, int width
)
716 if (!cell
->hasPort(name
))
718 if (cell
->getPort(name
).size() != width
)
720 expected_ports
.insert(name
);
723 void check_expected(bool check_matched_sign
= true)
725 for (auto ¶
: cell
->parameters
)
726 if (expected_params
.count(para
.first
) == 0)
728 for (auto &conn
: cell
->connections())
729 if (expected_ports
.count(conn
.first
) == 0)
732 if (expected_params
.count("\\A_SIGNED") != 0 && expected_params
.count("\\B_SIGNED") && check_matched_sign
) {
733 bool a_is_signed
= param("\\A_SIGNED") != 0;
734 bool b_is_signed
= param("\\B_SIGNED") != 0;
735 if (a_is_signed
!= b_is_signed
)
740 void check_gate(const char *ports
)
742 if (cell
->parameters
.size() != 0)
745 for (const char *p
= ports
; *p
; p
++) {
746 char portname
[3] = { '\\', *p
, 0 };
747 if (!cell
->hasPort(portname
))
749 if (cell
->getPort(portname
).size() != 1)
753 for (auto &conn
: cell
->connections()) {
754 if (conn
.first
.size() != 2 || conn
.first
[0] != '\\')
756 if (strchr(ports
, conn
.first
[1]) == NULL
)
763 if (cell
->type
.substr(0, 1) != "$" || cell
->type
.substr(0, 3) == "$__" || cell
->type
.substr(0, 8) == "$paramod" || cell
->type
.substr(0,10) == "$fmcombine" ||
764 cell
->type
.substr(0, 9) == "$verific$" || cell
->type
.substr(0, 7) == "$array:" || cell
->type
.substr(0, 8) == "$extern:")
767 if (cell
->type
.in("$not", "$pos", "$neg")) {
768 param_bool("\\A_SIGNED");
769 port("\\A", param("\\A_WIDTH"));
770 port("\\Y", param("\\Y_WIDTH"));
775 if (cell
->type
.in("$and", "$or", "$xor", "$xnor")) {
776 param_bool("\\A_SIGNED");
777 param_bool("\\B_SIGNED");
778 port("\\A", param("\\A_WIDTH"));
779 port("\\B", param("\\B_WIDTH"));
780 port("\\Y", param("\\Y_WIDTH"));
785 if (cell
->type
.in("$reduce_and", "$reduce_or", "$reduce_xor", "$reduce_xnor", "$reduce_bool")) {
786 param_bool("\\A_SIGNED");
787 port("\\A", param("\\A_WIDTH"));
788 port("\\Y", param("\\Y_WIDTH"));
793 if (cell
->type
.in("$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx")) {
794 param_bool("\\A_SIGNED");
795 param_bool("\\B_SIGNED");
796 port("\\A", param("\\A_WIDTH"));
797 port("\\B", param("\\B_WIDTH"));
798 port("\\Y", param("\\Y_WIDTH"));
799 check_expected(false);
803 if (cell
->type
.in("$lt", "$le", "$eq", "$ne", "$eqx", "$nex", "$ge", "$gt")) {
804 param_bool("\\A_SIGNED");
805 param_bool("\\B_SIGNED");
806 port("\\A", param("\\A_WIDTH"));
807 port("\\B", param("\\B_WIDTH"));
808 port("\\Y", param("\\Y_WIDTH"));
813 if (cell
->type
.in("$add", "$sub", "$mul", "$div", "$mod", "$pow")) {
814 param_bool("\\A_SIGNED");
815 param_bool("\\B_SIGNED");
816 port("\\A", param("\\A_WIDTH"));
817 port("\\B", param("\\B_WIDTH"));
818 port("\\Y", param("\\Y_WIDTH"));
819 check_expected(cell
->type
!= "$pow");
823 if (cell
->type
== "$fa") {
824 port("\\A", param("\\WIDTH"));
825 port("\\B", param("\\WIDTH"));
826 port("\\C", param("\\WIDTH"));
827 port("\\X", param("\\WIDTH"));
828 port("\\Y", param("\\WIDTH"));
833 if (cell
->type
== "$lcu") {
834 port("\\P", param("\\WIDTH"));
835 port("\\G", param("\\WIDTH"));
837 port("\\CO", param("\\WIDTH"));
842 if (cell
->type
== "$alu") {
843 param_bool("\\A_SIGNED");
844 param_bool("\\B_SIGNED");
845 port("\\A", param("\\A_WIDTH"));
846 port("\\B", param("\\B_WIDTH"));
849 port("\\X", param("\\Y_WIDTH"));
850 port("\\Y", param("\\Y_WIDTH"));
851 port("\\CO", param("\\Y_WIDTH"));
856 if (cell
->type
== "$macc") {
858 param("\\CONFIG_WIDTH");
859 port("\\A", param("\\A_WIDTH"));
860 port("\\B", param("\\B_WIDTH"));
861 port("\\Y", param("\\Y_WIDTH"));
863 Macc().from_cell(cell
);
867 if (cell
->type
== "$logic_not") {
868 param_bool("\\A_SIGNED");
869 port("\\A", param("\\A_WIDTH"));
870 port("\\Y", param("\\Y_WIDTH"));
875 if (cell
->type
== "$logic_and" || cell
->type
== "$logic_or") {
876 param_bool("\\A_SIGNED");
877 param_bool("\\B_SIGNED");
878 port("\\A", param("\\A_WIDTH"));
879 port("\\B", param("\\B_WIDTH"));
880 port("\\Y", param("\\Y_WIDTH"));
881 check_expected(false);
885 if (cell
->type
== "$slice") {
887 port("\\A", param("\\A_WIDTH"));
888 port("\\Y", param("\\Y_WIDTH"));
889 if (param("\\OFFSET") + param("\\Y_WIDTH") > param("\\A_WIDTH"))
895 if (cell
->type
== "$concat") {
896 port("\\A", param("\\A_WIDTH"));
897 port("\\B", param("\\B_WIDTH"));
898 port("\\Y", param("\\A_WIDTH") + param("\\B_WIDTH"));
903 if (cell
->type
== "$mux") {
904 port("\\A", param("\\WIDTH"));
905 port("\\B", param("\\WIDTH"));
907 port("\\Y", param("\\WIDTH"));
912 if (cell
->type
== "$pmux") {
913 port("\\A", param("\\WIDTH"));
914 port("\\B", param("\\WIDTH") * param("\\S_WIDTH"));
915 port("\\S", param("\\S_WIDTH"));
916 port("\\Y", param("\\WIDTH"));
921 if (cell
->type
== "$lut") {
923 port("\\A", param("\\WIDTH"));
929 if (cell
->type
== "$sop") {
932 port("\\A", param("\\WIDTH"));
938 if (cell
->type
== "$sr") {
939 param_bool("\\SET_POLARITY");
940 param_bool("\\CLR_POLARITY");
941 port("\\SET", param("\\WIDTH"));
942 port("\\CLR", param("\\WIDTH"));
943 port("\\Q", param("\\WIDTH"));
948 if (cell
->type
== "$ff") {
949 port("\\D", param("\\WIDTH"));
950 port("\\Q", param("\\WIDTH"));
955 if (cell
->type
== "$dff") {
956 param_bool("\\CLK_POLARITY");
958 port("\\D", param("\\WIDTH"));
959 port("\\Q", param("\\WIDTH"));
964 if (cell
->type
== "$dffe") {
965 param_bool("\\CLK_POLARITY");
966 param_bool("\\EN_POLARITY");
969 port("\\D", param("\\WIDTH"));
970 port("\\Q", param("\\WIDTH"));
975 if (cell
->type
== "$dffsr") {
976 param_bool("\\CLK_POLARITY");
977 param_bool("\\SET_POLARITY");
978 param_bool("\\CLR_POLARITY");
980 port("\\SET", param("\\WIDTH"));
981 port("\\CLR", param("\\WIDTH"));
982 port("\\D", param("\\WIDTH"));
983 port("\\Q", param("\\WIDTH"));
988 if (cell
->type
== "$adff") {
989 param_bool("\\CLK_POLARITY");
990 param_bool("\\ARST_POLARITY");
991 param_bits("\\ARST_VALUE", param("\\WIDTH"));
994 port("\\D", param("\\WIDTH"));
995 port("\\Q", param("\\WIDTH"));
1000 if (cell
->type
== "$dlatch") {
1001 param_bool("\\EN_POLARITY");
1003 port("\\D", param("\\WIDTH"));
1004 port("\\Q", param("\\WIDTH"));
1009 if (cell
->type
== "$dlatchsr") {
1010 param_bool("\\EN_POLARITY");
1011 param_bool("\\SET_POLARITY");
1012 param_bool("\\CLR_POLARITY");
1014 port("\\SET", param("\\WIDTH"));
1015 port("\\CLR", param("\\WIDTH"));
1016 port("\\D", param("\\WIDTH"));
1017 port("\\Q", param("\\WIDTH"));
1022 if (cell
->type
== "$fsm") {
1024 param_bool("\\CLK_POLARITY");
1025 param_bool("\\ARST_POLARITY");
1026 param("\\STATE_BITS");
1027 param("\\STATE_NUM");
1028 param("\\STATE_NUM_LOG2");
1029 param("\\STATE_RST");
1030 param_bits("\\STATE_TABLE", param("\\STATE_BITS") * param("\\STATE_NUM"));
1031 param("\\TRANS_NUM");
1032 param_bits("\\TRANS_TABLE", param("\\TRANS_NUM") * (2*param("\\STATE_NUM_LOG2") + param("\\CTRL_IN_WIDTH") + param("\\CTRL_OUT_WIDTH")));
1035 port("\\CTRL_IN", param("\\CTRL_IN_WIDTH"));
1036 port("\\CTRL_OUT", param("\\CTRL_OUT_WIDTH"));
1041 if (cell
->type
== "$memrd") {
1043 param_bool("\\CLK_ENABLE");
1044 param_bool("\\CLK_POLARITY");
1045 param_bool("\\TRANSPARENT");
1048 port("\\ADDR", param("\\ABITS"));
1049 port("\\DATA", param("\\WIDTH"));
1054 if (cell
->type
== "$memwr") {
1056 param_bool("\\CLK_ENABLE");
1057 param_bool("\\CLK_POLARITY");
1058 param("\\PRIORITY");
1060 port("\\EN", param("\\WIDTH"));
1061 port("\\ADDR", param("\\ABITS"));
1062 port("\\DATA", param("\\WIDTH"));
1067 if (cell
->type
== "$meminit") {
1069 param("\\PRIORITY");
1070 port("\\ADDR", param("\\ABITS"));
1071 port("\\DATA", param("\\WIDTH") * param("\\WORDS"));
1076 if (cell
->type
== "$mem") {
1081 param_bits("\\RD_CLK_ENABLE", max(1, param("\\RD_PORTS")));
1082 param_bits("\\RD_CLK_POLARITY", max(1, param("\\RD_PORTS")));
1083 param_bits("\\RD_TRANSPARENT", max(1, param("\\RD_PORTS")));
1084 param_bits("\\WR_CLK_ENABLE", max(1, param("\\WR_PORTS")));
1085 param_bits("\\WR_CLK_POLARITY", max(1, param("\\WR_PORTS")));
1086 port("\\RD_CLK", param("\\RD_PORTS"));
1087 port("\\RD_EN", param("\\RD_PORTS"));
1088 port("\\RD_ADDR", param("\\RD_PORTS") * param("\\ABITS"));
1089 port("\\RD_DATA", param("\\RD_PORTS") * param("\\WIDTH"));
1090 port("\\WR_CLK", param("\\WR_PORTS"));
1091 port("\\WR_EN", param("\\WR_PORTS") * param("\\WIDTH"));
1092 port("\\WR_ADDR", param("\\WR_PORTS") * param("\\ABITS"));
1093 port("\\WR_DATA", param("\\WR_PORTS") * param("\\WIDTH"));
1098 if (cell
->type
== "$tribuf") {
1099 port("\\A", param("\\WIDTH"));
1100 port("\\Y", param("\\WIDTH"));
1106 if (cell
->type
.in("$assert", "$assume", "$live", "$fair", "$cover")) {
1113 if (cell
->type
== "$initstate") {
1119 if (cell
->type
.in("$anyconst", "$anyseq", "$allconst", "$allseq")) {
1120 port("\\Y", param("\\WIDTH"));
1125 if (cell
->type
== "$equiv") {
1133 if (cell
->type
== "$_BUF_") { check_gate("AY"); return; }
1134 if (cell
->type
== "$_NOT_") { check_gate("AY"); return; }
1135 if (cell
->type
== "$_AND_") { check_gate("ABY"); return; }
1136 if (cell
->type
== "$_NAND_") { check_gate("ABY"); return; }
1137 if (cell
->type
== "$_OR_") { check_gate("ABY"); return; }
1138 if (cell
->type
== "$_NOR_") { check_gate("ABY"); return; }
1139 if (cell
->type
== "$_XOR_") { check_gate("ABY"); return; }
1140 if (cell
->type
== "$_XNOR_") { check_gate("ABY"); return; }
1141 if (cell
->type
== "$_ANDNOT_") { check_gate("ABY"); return; }
1142 if (cell
->type
== "$_ORNOT_") { check_gate("ABY"); return; }
1143 if (cell
->type
== "$_MUX_") { check_gate("ABSY"); return; }
1144 if (cell
->type
== "$_AOI3_") { check_gate("ABCY"); return; }
1145 if (cell
->type
== "$_OAI3_") { check_gate("ABCY"); return; }
1146 if (cell
->type
== "$_AOI4_") { check_gate("ABCDY"); return; }
1147 if (cell
->type
== "$_OAI4_") { check_gate("ABCDY"); return; }
1149 if (cell
->type
== "$_TBUF_") { check_gate("AYE"); return; }
1151 if (cell
->type
== "$_MUX4_") { check_gate("ABCDSTY"); return; }
1152 if (cell
->type
== "$_MUX8_") { check_gate("ABCDEFGHSTUY"); return; }
1153 if (cell
->type
== "$_MUX16_") { check_gate("ABCDEFGHIJKLMNOPSTUVY"); return; }
1155 if (cell
->type
== "$_SR_NN_") { check_gate("SRQ"); return; }
1156 if (cell
->type
== "$_SR_NP_") { check_gate("SRQ"); return; }
1157 if (cell
->type
== "$_SR_PN_") { check_gate("SRQ"); return; }
1158 if (cell
->type
== "$_SR_PP_") { check_gate("SRQ"); return; }
1160 if (cell
->type
== "$_FF_") { check_gate("DQ"); return; }
1161 if (cell
->type
== "$_DFF_N_") { check_gate("DQC"); return; }
1162 if (cell
->type
== "$_DFF_P_") { check_gate("DQC"); return; }
1164 if (cell
->type
== "$_DFFE_NN_") { check_gate("DQCE"); return; }
1165 if (cell
->type
== "$_DFFE_NP_") { check_gate("DQCE"); return; }
1166 if (cell
->type
== "$_DFFE_PN_") { check_gate("DQCE"); return; }
1167 if (cell
->type
== "$_DFFE_PP_") { check_gate("DQCE"); return; }
1169 if (cell
->type
== "$_DFF_NN0_") { check_gate("DQCR"); return; }
1170 if (cell
->type
== "$_DFF_NN1_") { check_gate("DQCR"); return; }
1171 if (cell
->type
== "$_DFF_NP0_") { check_gate("DQCR"); return; }
1172 if (cell
->type
== "$_DFF_NP1_") { check_gate("DQCR"); return; }
1173 if (cell
->type
== "$_DFF_PN0_") { check_gate("DQCR"); return; }
1174 if (cell
->type
== "$_DFF_PN1_") { check_gate("DQCR"); return; }
1175 if (cell
->type
== "$_DFF_PP0_") { check_gate("DQCR"); return; }
1176 if (cell
->type
== "$_DFF_PP1_") { check_gate("DQCR"); return; }
1178 if (cell
->type
== "$_DFFSR_NNN_") { check_gate("CSRDQ"); return; }
1179 if (cell
->type
== "$_DFFSR_NNP_") { check_gate("CSRDQ"); return; }
1180 if (cell
->type
== "$_DFFSR_NPN_") { check_gate("CSRDQ"); return; }
1181 if (cell
->type
== "$_DFFSR_NPP_") { check_gate("CSRDQ"); return; }
1182 if (cell
->type
== "$_DFFSR_PNN_") { check_gate("CSRDQ"); return; }
1183 if (cell
->type
== "$_DFFSR_PNP_") { check_gate("CSRDQ"); return; }
1184 if (cell
->type
== "$_DFFSR_PPN_") { check_gate("CSRDQ"); return; }
1185 if (cell
->type
== "$_DFFSR_PPP_") { check_gate("CSRDQ"); return; }
1187 if (cell
->type
== "$_DLATCH_N_") { check_gate("EDQ"); return; }
1188 if (cell
->type
== "$_DLATCH_P_") { check_gate("EDQ"); return; }
1190 if (cell
->type
== "$_DLATCHSR_NNN_") { check_gate("ESRDQ"); return; }
1191 if (cell
->type
== "$_DLATCHSR_NNP_") { check_gate("ESRDQ"); return; }
1192 if (cell
->type
== "$_DLATCHSR_NPN_") { check_gate("ESRDQ"); return; }
1193 if (cell
->type
== "$_DLATCHSR_NPP_") { check_gate("ESRDQ"); return; }
1194 if (cell
->type
== "$_DLATCHSR_PNN_") { check_gate("ESRDQ"); return; }
1195 if (cell
->type
== "$_DLATCHSR_PNP_") { check_gate("ESRDQ"); return; }
1196 if (cell
->type
== "$_DLATCHSR_PPN_") { check_gate("ESRDQ"); return; }
1197 if (cell
->type
== "$_DLATCHSR_PPP_") { check_gate("ESRDQ"); return; }
1205 void RTLIL::Module::sort()
1207 wires_
.sort(sort_by_id_str());
1208 cells_
.sort(sort_by_id_str());
1209 avail_parameters
.sort(sort_by_id_str());
1210 memories
.sort(sort_by_id_str());
1211 processes
.sort(sort_by_id_str());
1212 for (auto &it
: cells_
)
1214 for (auto &it
: wires_
)
1215 it
.second
->attributes
.sort(sort_by_id_str());
1216 for (auto &it
: memories
)
1217 it
.second
->attributes
.sort(sort_by_id_str());
1220 void RTLIL::Module::check()
1223 std::vector
<bool> ports_declared
;
1224 for (auto &it
: wires_
) {
1225 log_assert(this == it
.second
->module
);
1226 log_assert(it
.first
== it
.second
->name
);
1227 log_assert(!it
.first
.empty());
1228 log_assert(it
.second
->width
>= 0);
1229 log_assert(it
.second
->port_id
>= 0);
1230 for (auto &it2
: it
.second
->attributes
)
1231 log_assert(!it2
.first
.empty());
1232 if (it
.second
->port_id
) {
1233 log_assert(GetSize(ports
) >= it
.second
->port_id
);
1234 log_assert(ports
.at(it
.second
->port_id
-1) == it
.first
);
1235 log_assert(it
.second
->port_input
|| it
.second
->port_output
);
1236 if (GetSize(ports_declared
) < it
.second
->port_id
)
1237 ports_declared
.resize(it
.second
->port_id
);
1238 log_assert(ports_declared
[it
.second
->port_id
-1] == false);
1239 ports_declared
[it
.second
->port_id
-1] = true;
1241 log_assert(!it
.second
->port_input
&& !it
.second
->port_output
);
1243 for (auto port_declared
: ports_declared
)
1244 log_assert(port_declared
== true);
1245 log_assert(GetSize(ports
) == GetSize(ports_declared
));
1247 for (auto &it
: memories
) {
1248 log_assert(it
.first
== it
.second
->name
);
1249 log_assert(!it
.first
.empty());
1250 log_assert(it
.second
->width
>= 0);
1251 log_assert(it
.second
->size
>= 0);
1252 for (auto &it2
: it
.second
->attributes
)
1253 log_assert(!it2
.first
.empty());
1256 for (auto &it
: cells_
) {
1257 log_assert(this == it
.second
->module
);
1258 log_assert(it
.first
== it
.second
->name
);
1259 log_assert(!it
.first
.empty());
1260 log_assert(!it
.second
->type
.empty());
1261 for (auto &it2
: it
.second
->connections()) {
1262 log_assert(!it2
.first
.empty());
1265 for (auto &it2
: it
.second
->attributes
)
1266 log_assert(!it2
.first
.empty());
1267 for (auto &it2
: it
.second
->parameters
)
1268 log_assert(!it2
.first
.empty());
1269 InternalCellChecker
checker(this, it
.second
);
1273 for (auto &it
: processes
) {
1274 log_assert(it
.first
== it
.second
->name
);
1275 log_assert(!it
.first
.empty());
1276 // FIXME: More checks here..
1279 for (auto &it
: connections_
) {
1280 log_assert(it
.first
.size() == it
.second
.size());
1281 log_assert(!it
.first
.has_const());
1286 for (auto &it
: attributes
)
1287 log_assert(!it
.first
.empty());
1291 void RTLIL::Module::optimize()
1295 void RTLIL::Module::cloneInto(RTLIL::Module
*new_mod
) const
1297 log_assert(new_mod
->refcount_wires_
== 0);
1298 log_assert(new_mod
->refcount_cells_
== 0);
1300 new_mod
->avail_parameters
= avail_parameters
;
1302 for (auto &conn
: connections_
)
1303 new_mod
->connect(conn
);
1305 for (auto &attr
: attributes
)
1306 new_mod
->attributes
[attr
.first
] = attr
.second
;
1308 for (auto &it
: wires_
)
1309 new_mod
->addWire(it
.first
, it
.second
);
1311 for (auto &it
: memories
)
1312 new_mod
->memories
[it
.first
] = new RTLIL::Memory(*it
.second
);
1314 for (auto &it
: cells_
)
1315 new_mod
->addCell(it
.first
, it
.second
);
1317 for (auto &it
: processes
)
1318 new_mod
->processes
[it
.first
] = it
.second
->clone();
1320 struct RewriteSigSpecWorker
1323 void operator()(RTLIL::SigSpec
&sig
)
1325 std::vector
<RTLIL::SigChunk
> chunks
= sig
.chunks();
1326 for (auto &c
: chunks
)
1328 c
.wire
= mod
->wires_
.at(c
.wire
->name
);
1333 RewriteSigSpecWorker rewriteSigSpecWorker
;
1334 rewriteSigSpecWorker
.mod
= new_mod
;
1335 new_mod
->rewrite_sigspecs(rewriteSigSpecWorker
);
1336 new_mod
->fixup_ports();
1339 RTLIL::Module
*RTLIL::Module::clone() const
1341 RTLIL::Module
*new_mod
= new RTLIL::Module
;
1342 new_mod
->name
= name
;
1347 bool RTLIL::Module::has_memories() const
1349 return !memories
.empty();
1352 bool RTLIL::Module::has_processes() const
1354 return !processes
.empty();
1357 bool RTLIL::Module::has_memories_warn() const
1359 if (!memories
.empty())
1360 log_warning("Ignoring module %s because it contains memories (run 'memory' command first).\n", log_id(this));
1361 return !memories
.empty();
1364 bool RTLIL::Module::has_processes_warn() const
1366 if (!processes
.empty())
1367 log_warning("Ignoring module %s because it contains processes (run 'proc' command first).\n", log_id(this));
1368 return !processes
.empty();
1371 std::vector
<RTLIL::Wire
*> RTLIL::Module::selected_wires() const
1373 std::vector
<RTLIL::Wire
*> result
;
1374 result
.reserve(wires_
.size());
1375 for (auto &it
: wires_
)
1376 if (design
->selected(this, it
.second
))
1377 result
.push_back(it
.second
);
1381 std::vector
<RTLIL::Cell
*> RTLIL::Module::selected_cells() const
1383 std::vector
<RTLIL::Cell
*> result
;
1384 result
.reserve(wires_
.size());
1385 for (auto &it
: cells_
)
1386 if (design
->selected(this, it
.second
))
1387 result
.push_back(it
.second
);
1391 void RTLIL::Module::add(RTLIL::Wire
*wire
)
1393 log_assert(!wire
->name
.empty());
1394 log_assert(count_id(wire
->name
) == 0);
1395 log_assert(refcount_wires_
== 0);
1396 wires_
[wire
->name
] = wire
;
1397 wire
->module
= this;
1400 void RTLIL::Module::add(RTLIL::Cell
*cell
)
1402 log_assert(!cell
->name
.empty());
1403 log_assert(count_id(cell
->name
) == 0);
1404 log_assert(refcount_cells_
== 0);
1405 cells_
[cell
->name
] = cell
;
1406 cell
->module
= this;
1410 struct DeleteWireWorker
1412 RTLIL::Module
*module
;
1413 const pool
<RTLIL::Wire
*> *wires_p
;
1415 void operator()(RTLIL::SigSpec
&sig
) {
1416 std::vector
<RTLIL::SigChunk
> chunks
= sig
;
1417 for (auto &c
: chunks
)
1418 if (c
.wire
!= NULL
&& wires_p
->count(c
.wire
)) {
1419 c
.wire
= module
->addWire(NEW_ID
, c
.width
);
1427 void RTLIL::Module::remove(const pool
<RTLIL::Wire
*> &wires
)
1429 log_assert(refcount_wires_
== 0);
1431 DeleteWireWorker delete_wire_worker
;
1432 delete_wire_worker
.module
= this;
1433 delete_wire_worker
.wires_p
= &wires
;
1434 rewrite_sigspecs(delete_wire_worker
);
1436 for (auto &it
: wires
) {
1437 log_assert(wires_
.count(it
->name
) != 0);
1438 wires_
.erase(it
->name
);
1443 void RTLIL::Module::remove(RTLIL::Cell
*cell
)
1445 while (!cell
->connections_
.empty())
1446 cell
->unsetPort(cell
->connections_
.begin()->first
);
1448 log_assert(cells_
.count(cell
->name
) != 0);
1449 log_assert(refcount_cells_
== 0);
1450 cells_
.erase(cell
->name
);
1454 void RTLIL::Module::rename(RTLIL::Wire
*wire
, RTLIL::IdString new_name
)
1456 log_assert(wires_
[wire
->name
] == wire
);
1457 log_assert(refcount_wires_
== 0);
1458 wires_
.erase(wire
->name
);
1459 wire
->name
= new_name
;
1463 void RTLIL::Module::rename(RTLIL::Cell
*cell
, RTLIL::IdString new_name
)
1465 log_assert(cells_
[cell
->name
] == cell
);
1466 log_assert(refcount_wires_
== 0);
1467 cells_
.erase(cell
->name
);
1468 cell
->name
= new_name
;
1472 void RTLIL::Module::rename(RTLIL::IdString old_name
, RTLIL::IdString new_name
)
1474 log_assert(count_id(old_name
) != 0);
1475 if (wires_
.count(old_name
))
1476 rename(wires_
.at(old_name
), new_name
);
1477 else if (cells_
.count(old_name
))
1478 rename(cells_
.at(old_name
), new_name
);
1483 void RTLIL::Module::swap_names(RTLIL::Wire
*w1
, RTLIL::Wire
*w2
)
1485 log_assert(wires_
[w1
->name
] == w1
);
1486 log_assert(wires_
[w2
->name
] == w2
);
1487 log_assert(refcount_wires_
== 0);
1489 wires_
.erase(w1
->name
);
1490 wires_
.erase(w2
->name
);
1492 std::swap(w1
->name
, w2
->name
);
1494 wires_
[w1
->name
] = w1
;
1495 wires_
[w2
->name
] = w2
;
1498 void RTLIL::Module::swap_names(RTLIL::Cell
*c1
, RTLIL::Cell
*c2
)
1500 log_assert(cells_
[c1
->name
] == c1
);
1501 log_assert(cells_
[c2
->name
] == c2
);
1502 log_assert(refcount_cells_
== 0);
1504 cells_
.erase(c1
->name
);
1505 cells_
.erase(c2
->name
);
1507 std::swap(c1
->name
, c2
->name
);
1509 cells_
[c1
->name
] = c1
;
1510 cells_
[c2
->name
] = c2
;
1513 RTLIL::IdString
RTLIL::Module::uniquify(RTLIL::IdString name
)
1516 return uniquify(name
, index
);
1519 RTLIL::IdString
RTLIL::Module::uniquify(RTLIL::IdString name
, int &index
)
1522 if (count_id(name
) == 0)
1528 RTLIL::IdString new_name
= stringf("%s_%d", name
.c_str(), index
);
1529 if (count_id(new_name
) == 0)
1535 static bool fixup_ports_compare(const RTLIL::Wire
*a
, const RTLIL::Wire
*b
)
1537 if (a
->port_id
&& !b
->port_id
)
1539 if (!a
->port_id
&& b
->port_id
)
1542 if (a
->port_id
== b
->port_id
)
1543 return a
->name
< b
->name
;
1544 return a
->port_id
< b
->port_id
;
1547 void RTLIL::Module::connect(const RTLIL::SigSig
&conn
)
1549 for (auto mon
: monitors
)
1550 mon
->notify_connect(this, conn
);
1553 for (auto mon
: design
->monitors
)
1554 mon
->notify_connect(this, conn
);
1556 // ignore all attempts to assign constants to other constants
1557 if (conn
.first
.has_const()) {
1558 RTLIL::SigSig new_conn
;
1559 for (int i
= 0; i
< GetSize(conn
.first
); i
++)
1560 if (conn
.first
[i
].wire
) {
1561 new_conn
.first
.append(conn
.first
[i
]);
1562 new_conn
.second
.append(conn
.second
[i
]);
1564 if (GetSize(new_conn
.first
))
1570 log("#X# Connect (SigSig) in %s: %s = %s (%d bits)\n", log_id(this), log_signal(conn
.first
), log_signal(conn
.second
), GetSize(conn
.first
));
1571 log_backtrace("-X- ", yosys_xtrace
-1);
1574 log_assert(GetSize(conn
.first
) == GetSize(conn
.second
));
1575 connections_
.push_back(conn
);
1578 void RTLIL::Module::connect(const RTLIL::SigSpec
&lhs
, const RTLIL::SigSpec
&rhs
)
1580 connect(RTLIL::SigSig(lhs
, rhs
));
1583 void RTLIL::Module::new_connections(const std::vector
<RTLIL::SigSig
> &new_conn
)
1585 for (auto mon
: monitors
)
1586 mon
->notify_connect(this, new_conn
);
1589 for (auto mon
: design
->monitors
)
1590 mon
->notify_connect(this, new_conn
);
1593 log("#X# New connections vector in %s:\n", log_id(this));
1594 for (auto &conn
: new_conn
)
1595 log("#X# %s = %s (%d bits)\n", log_signal(conn
.first
), log_signal(conn
.second
), GetSize(conn
.first
));
1596 log_backtrace("-X- ", yosys_xtrace
-1);
1599 connections_
= new_conn
;
1602 const std::vector
<RTLIL::SigSig
> &RTLIL::Module::connections() const
1604 return connections_
;
1607 void RTLIL::Module::fixup_ports()
1609 std::vector
<RTLIL::Wire
*> all_ports
;
1611 for (auto &w
: wires_
)
1612 if (w
.second
->port_input
|| w
.second
->port_output
)
1613 all_ports
.push_back(w
.second
);
1615 w
.second
->port_id
= 0;
1617 std::sort(all_ports
.begin(), all_ports
.end(), fixup_ports_compare
);
1620 for (size_t i
= 0; i
< all_ports
.size(); i
++) {
1621 ports
.push_back(all_ports
[i
]->name
);
1622 all_ports
[i
]->port_id
= i
+1;
1626 RTLIL::Wire
*RTLIL::Module::addWire(RTLIL::IdString name
, int width
)
1628 RTLIL::Wire
*wire
= new RTLIL::Wire
;
1630 wire
->width
= width
;
1635 RTLIL::Wire
*RTLIL::Module::addWire(RTLIL::IdString name
, const RTLIL::Wire
*other
)
1637 RTLIL::Wire
*wire
= addWire(name
);
1638 wire
->width
= other
->width
;
1639 wire
->start_offset
= other
->start_offset
;
1640 wire
->port_id
= other
->port_id
;
1641 wire
->port_input
= other
->port_input
;
1642 wire
->port_output
= other
->port_output
;
1643 wire
->upto
= other
->upto
;
1644 wire
->attributes
= other
->attributes
;
1648 RTLIL::Cell
*RTLIL::Module::addCell(RTLIL::IdString name
, RTLIL::IdString type
)
1650 RTLIL::Cell
*cell
= new RTLIL::Cell
;
1657 RTLIL::Cell
*RTLIL::Module::addCell(RTLIL::IdString name
, const RTLIL::Cell
*other
)
1659 RTLIL::Cell
*cell
= addCell(name
, other
->type
);
1660 cell
->connections_
= other
->connections_
;
1661 cell
->parameters
= other
->parameters
;
1662 cell
->attributes
= other
->attributes
;
1666 #define DEF_METHOD(_func, _y_size, _type) \
1667 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed, const std::string &src) { \
1668 RTLIL::Cell *cell = addCell(name, _type); \
1669 cell->parameters["\\A_SIGNED"] = is_signed; \
1670 cell->parameters["\\A_WIDTH"] = sig_a.size(); \
1671 cell->parameters["\\Y_WIDTH"] = sig_y.size(); \
1672 cell->setPort("\\A", sig_a); \
1673 cell->setPort("\\Y", sig_y); \
1674 cell->set_src_attribute(src); \
1677 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed, const std::string &src) { \
1678 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
1679 add ## _func(name, sig_a, sig_y, is_signed, src); \
1682 DEF_METHOD(Not
, sig_a
.size(), "$not")
1683 DEF_METHOD(Pos
, sig_a
.size(), "$pos")
1684 DEF_METHOD(Neg
, sig_a
.size(), "$neg")
1685 DEF_METHOD(ReduceAnd
, 1, "$reduce_and")
1686 DEF_METHOD(ReduceOr
, 1, "$reduce_or")
1687 DEF_METHOD(ReduceXor
, 1, "$reduce_xor")
1688 DEF_METHOD(ReduceXnor
, 1, "$reduce_xnor")
1689 DEF_METHOD(ReduceBool
, 1, "$reduce_bool")
1690 DEF_METHOD(LogicNot
, 1, "$logic_not")
1693 #define DEF_METHOD(_func, _y_size, _type) \
1694 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed, const std::string &src) { \
1695 RTLIL::Cell *cell = addCell(name, _type); \
1696 cell->parameters["\\A_SIGNED"] = is_signed; \
1697 cell->parameters["\\B_SIGNED"] = is_signed; \
1698 cell->parameters["\\A_WIDTH"] = sig_a.size(); \
1699 cell->parameters["\\B_WIDTH"] = sig_b.size(); \
1700 cell->parameters["\\Y_WIDTH"] = sig_y.size(); \
1701 cell->setPort("\\A", sig_a); \
1702 cell->setPort("\\B", sig_b); \
1703 cell->setPort("\\Y", sig_y); \
1704 cell->set_src_attribute(src); \
1707 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed, const std::string &src) { \
1708 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
1709 add ## _func(name, sig_a, sig_b, sig_y, is_signed, src); \
1712 DEF_METHOD(And
, max(sig_a
.size(), sig_b
.size()), "$and")
1713 DEF_METHOD(Or
, max(sig_a
.size(), sig_b
.size()), "$or")
1714 DEF_METHOD(Xor
, max(sig_a
.size(), sig_b
.size()), "$xor")
1715 DEF_METHOD(Xnor
, max(sig_a
.size(), sig_b
.size()), "$xnor")
1716 DEF_METHOD(Shl
, sig_a
.size(), "$shl")
1717 DEF_METHOD(Shr
, sig_a
.size(), "$shr")
1718 DEF_METHOD(Sshl
, sig_a
.size(), "$sshl")
1719 DEF_METHOD(Sshr
, sig_a
.size(), "$sshr")
1720 DEF_METHOD(Shift
, sig_a
.size(), "$shift")
1721 DEF_METHOD(Shiftx
, sig_a
.size(), "$shiftx")
1722 DEF_METHOD(Lt
, 1, "$lt")
1723 DEF_METHOD(Le
, 1, "$le")
1724 DEF_METHOD(Eq
, 1, "$eq")
1725 DEF_METHOD(Ne
, 1, "$ne")
1726 DEF_METHOD(Eqx
, 1, "$eqx")
1727 DEF_METHOD(Nex
, 1, "$nex")
1728 DEF_METHOD(Ge
, 1, "$ge")
1729 DEF_METHOD(Gt
, 1, "$gt")
1730 DEF_METHOD(Add
, max(sig_a
.size(), sig_b
.size()), "$add")
1731 DEF_METHOD(Sub
, max(sig_a
.size(), sig_b
.size()), "$sub")
1732 DEF_METHOD(Mul
, max(sig_a
.size(), sig_b
.size()), "$mul")
1733 DEF_METHOD(Div
, max(sig_a
.size(), sig_b
.size()), "$div")
1734 DEF_METHOD(Mod
, max(sig_a
.size(), sig_b
.size()), "$mod")
1735 DEF_METHOD(LogicAnd
, 1, "$logic_and")
1736 DEF_METHOD(LogicOr
, 1, "$logic_or")
1739 #define DEF_METHOD(_func, _type, _pmux) \
1740 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, RTLIL::SigSpec sig_y, const std::string &src) { \
1741 RTLIL::Cell *cell = addCell(name, _type); \
1742 cell->parameters["\\WIDTH"] = sig_a.size(); \
1743 if (_pmux) cell->parameters["\\S_WIDTH"] = sig_s.size(); \
1744 cell->setPort("\\A", sig_a); \
1745 cell->setPort("\\B", sig_b); \
1746 cell->setPort("\\S", sig_s); \
1747 cell->setPort("\\Y", sig_y); \
1748 cell->set_src_attribute(src); \
1751 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, const std::string &src) { \
1752 RTLIL::SigSpec sig_y = addWire(NEW_ID, sig_a.size()); \
1753 add ## _func(name, sig_a, sig_b, sig_s, sig_y, src); \
1756 DEF_METHOD(Mux
, "$mux", 0)
1757 DEF_METHOD(Pmux
, "$pmux", 1)
1760 #define DEF_METHOD_2(_func, _type, _P1, _P2) \
1761 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, const std::string &src) { \
1762 RTLIL::Cell *cell = addCell(name, _type); \
1763 cell->setPort("\\" #_P1, sig1); \
1764 cell->setPort("\\" #_P2, sig2); \
1765 cell->set_src_attribute(src); \
1768 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, const std::string &src) { \
1769 RTLIL::SigBit sig2 = addWire(NEW_ID); \
1770 add ## _func(name, sig1, sig2, src); \
1773 #define DEF_METHOD_3(_func, _type, _P1, _P2, _P3) \
1774 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, const std::string &src) { \
1775 RTLIL::Cell *cell = addCell(name, _type); \
1776 cell->setPort("\\" #_P1, sig1); \
1777 cell->setPort("\\" #_P2, sig2); \
1778 cell->setPort("\\" #_P3, sig3); \
1779 cell->set_src_attribute(src); \
1782 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, const std::string &src) { \
1783 RTLIL::SigBit sig3 = addWire(NEW_ID); \
1784 add ## _func(name, sig1, sig2, sig3, src); \
1787 #define DEF_METHOD_4(_func, _type, _P1, _P2, _P3, _P4) \
1788 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, RTLIL::SigBit sig4, const std::string &src) { \
1789 RTLIL::Cell *cell = addCell(name, _type); \
1790 cell->setPort("\\" #_P1, sig1); \
1791 cell->setPort("\\" #_P2, sig2); \
1792 cell->setPort("\\" #_P3, sig3); \
1793 cell->setPort("\\" #_P4, sig4); \
1794 cell->set_src_attribute(src); \
1797 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, const std::string &src) { \
1798 RTLIL::SigBit sig4 = addWire(NEW_ID); \
1799 add ## _func(name, sig1, sig2, sig3, sig4, src); \
1802 #define DEF_METHOD_5(_func, _type, _P1, _P2, _P3, _P4, _P5) \
1803 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, RTLIL::SigBit sig4, RTLIL::SigBit sig5, const std::string &src) { \
1804 RTLIL::Cell *cell = addCell(name, _type); \
1805 cell->setPort("\\" #_P1, sig1); \
1806 cell->setPort("\\" #_P2, sig2); \
1807 cell->setPort("\\" #_P3, sig3); \
1808 cell->setPort("\\" #_P4, sig4); \
1809 cell->setPort("\\" #_P5, sig5); \
1810 cell->set_src_attribute(src); \
1813 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, RTLIL::SigBit sig4, const std::string &src) { \
1814 RTLIL::SigBit sig5 = addWire(NEW_ID); \
1815 add ## _func(name, sig1, sig2, sig3, sig4, sig5, src); \
1818 DEF_METHOD_2(BufGate
, "$_BUF_", A
, Y
)
1819 DEF_METHOD_2(NotGate
, "$_NOT_", A
, Y
)
1820 DEF_METHOD_3(AndGate
, "$_AND_", A
, B
, Y
)
1821 DEF_METHOD_3(NandGate
, "$_NAND_", A
, B
, Y
)
1822 DEF_METHOD_3(OrGate
, "$_OR_", A
, B
, Y
)
1823 DEF_METHOD_3(NorGate
, "$_NOR_", A
, B
, Y
)
1824 DEF_METHOD_3(XorGate
, "$_XOR_", A
, B
, Y
)
1825 DEF_METHOD_3(XnorGate
, "$_XNOR_", A
, B
, Y
)
1826 DEF_METHOD_3(AndnotGate
, "$_ANDNOT_", A
, B
, Y
)
1827 DEF_METHOD_3(OrnotGate
, "$_ORNOT_", A
, B
, Y
)
1828 DEF_METHOD_4(MuxGate
, "$_MUX_", A
, B
, S
, Y
)
1829 DEF_METHOD_4(Aoi3Gate
, "$_AOI3_", A
, B
, C
, Y
)
1830 DEF_METHOD_4(Oai3Gate
, "$_OAI3_", A
, B
, C
, Y
)
1831 DEF_METHOD_5(Aoi4Gate
, "$_AOI4_", A
, B
, C
, D
, Y
)
1832 DEF_METHOD_5(Oai4Gate
, "$_OAI4_", A
, B
, C
, D
, Y
)
1838 RTLIL::Cell
* RTLIL::Module::addPow(RTLIL::IdString name
, RTLIL::SigSpec sig_a
, RTLIL::SigSpec sig_b
, RTLIL::SigSpec sig_y
, bool a_signed
, bool b_signed
, const std::string
&src
)
1840 RTLIL::Cell
*cell
= addCell(name
, "$pow");
1841 cell
->parameters
["\\A_SIGNED"] = a_signed
;
1842 cell
->parameters
["\\B_SIGNED"] = b_signed
;
1843 cell
->parameters
["\\A_WIDTH"] = sig_a
.size();
1844 cell
->parameters
["\\B_WIDTH"] = sig_b
.size();
1845 cell
->parameters
["\\Y_WIDTH"] = sig_y
.size();
1846 cell
->setPort("\\A", sig_a
);
1847 cell
->setPort("\\B", sig_b
);
1848 cell
->setPort("\\Y", sig_y
);
1849 cell
->set_src_attribute(src
);
1853 RTLIL::Cell
* RTLIL::Module::addSlice(RTLIL::IdString name
, RTLIL::SigSpec sig_a
, RTLIL::SigSpec sig_y
, RTLIL::Const offset
, const std::string
&src
)
1855 RTLIL::Cell
*cell
= addCell(name
, "$slice");
1856 cell
->parameters
["\\A_WIDTH"] = sig_a
.size();
1857 cell
->parameters
["\\Y_WIDTH"] = sig_y
.size();
1858 cell
->parameters
["\\OFFSET"] = offset
;
1859 cell
->setPort("\\A", sig_a
);
1860 cell
->setPort("\\Y", sig_y
);
1861 cell
->set_src_attribute(src
);
1865 RTLIL::Cell
* RTLIL::Module::addConcat(RTLIL::IdString name
, RTLIL::SigSpec sig_a
, RTLIL::SigSpec sig_b
, RTLIL::SigSpec sig_y
, const std::string
&src
)
1867 RTLIL::Cell
*cell
= addCell(name
, "$concat");
1868 cell
->parameters
["\\A_WIDTH"] = sig_a
.size();
1869 cell
->parameters
["\\B_WIDTH"] = sig_b
.size();
1870 cell
->setPort("\\A", sig_a
);
1871 cell
->setPort("\\B", sig_b
);
1872 cell
->setPort("\\Y", sig_y
);
1873 cell
->set_src_attribute(src
);
1877 RTLIL::Cell
* RTLIL::Module::addLut(RTLIL::IdString name
, RTLIL::SigSpec sig_a
, RTLIL::SigSpec sig_y
, RTLIL::Const lut
, const std::string
&src
)
1879 RTLIL::Cell
*cell
= addCell(name
, "$lut");
1880 cell
->parameters
["\\LUT"] = lut
;
1881 cell
->parameters
["\\WIDTH"] = sig_a
.size();
1882 cell
->setPort("\\A", sig_a
);
1883 cell
->setPort("\\Y", sig_y
);
1884 cell
->set_src_attribute(src
);
1888 RTLIL::Cell
* RTLIL::Module::addTribuf(RTLIL::IdString name
, RTLIL::SigSpec sig_a
, RTLIL::SigSpec sig_en
, RTLIL::SigSpec sig_y
, const std::string
&src
)
1890 RTLIL::Cell
*cell
= addCell(name
, "$tribuf");
1891 cell
->parameters
["\\WIDTH"] = sig_a
.size();
1892 cell
->setPort("\\A", sig_a
);
1893 cell
->setPort("\\EN", sig_en
);
1894 cell
->setPort("\\Y", sig_y
);
1895 cell
->set_src_attribute(src
);
1899 RTLIL::Cell
* RTLIL::Module::addAssert(RTLIL::IdString name
, RTLIL::SigSpec sig_a
, RTLIL::SigSpec sig_en
, const std::string
&src
)
1901 RTLIL::Cell
*cell
= addCell(name
, "$assert");
1902 cell
->setPort("\\A", sig_a
);
1903 cell
->setPort("\\EN", sig_en
);
1904 cell
->set_src_attribute(src
);
1908 RTLIL::Cell
* RTLIL::Module::addAssume(RTLIL::IdString name
, RTLIL::SigSpec sig_a
, RTLIL::SigSpec sig_en
, const std::string
&src
)
1910 RTLIL::Cell
*cell
= addCell(name
, "$assume");
1911 cell
->setPort("\\A", sig_a
);
1912 cell
->setPort("\\EN", sig_en
);
1913 cell
->set_src_attribute(src
);
1917 RTLIL::Cell
* RTLIL::Module::addLive(RTLIL::IdString name
, RTLIL::SigSpec sig_a
, RTLIL::SigSpec sig_en
, const std::string
&src
)
1919 RTLIL::Cell
*cell
= addCell(name
, "$live");
1920 cell
->setPort("\\A", sig_a
);
1921 cell
->setPort("\\EN", sig_en
);
1922 cell
->set_src_attribute(src
);
1926 RTLIL::Cell
* RTLIL::Module::addFair(RTLIL::IdString name
, RTLIL::SigSpec sig_a
, RTLIL::SigSpec sig_en
, const std::string
&src
)
1928 RTLIL::Cell
*cell
= addCell(name
, "$fair");
1929 cell
->setPort("\\A", sig_a
);
1930 cell
->setPort("\\EN", sig_en
);
1931 cell
->set_src_attribute(src
);
1935 RTLIL::Cell
* RTLIL::Module::addCover(RTLIL::IdString name
, RTLIL::SigSpec sig_a
, RTLIL::SigSpec sig_en
, const std::string
&src
)
1937 RTLIL::Cell
*cell
= addCell(name
, "$cover");
1938 cell
->setPort("\\A", sig_a
);
1939 cell
->setPort("\\EN", sig_en
);
1940 cell
->set_src_attribute(src
);
1944 RTLIL::Cell
* RTLIL::Module::addEquiv(RTLIL::IdString name
, RTLIL::SigSpec sig_a
, RTLIL::SigSpec sig_b
, RTLIL::SigSpec sig_y
, const std::string
&src
)
1946 RTLIL::Cell
*cell
= addCell(name
, "$equiv");
1947 cell
->setPort("\\A", sig_a
);
1948 cell
->setPort("\\B", sig_b
);
1949 cell
->setPort("\\Y", sig_y
);
1950 cell
->set_src_attribute(src
);
1954 RTLIL::Cell
* RTLIL::Module::addSr(RTLIL::IdString name
, RTLIL::SigSpec sig_set
, RTLIL::SigSpec sig_clr
, RTLIL::SigSpec sig_q
, bool set_polarity
, bool clr_polarity
, const std::string
&src
)
1956 RTLIL::Cell
*cell
= addCell(name
, "$sr");
1957 cell
->parameters
["\\SET_POLARITY"] = set_polarity
;
1958 cell
->parameters
["\\CLR_POLARITY"] = clr_polarity
;
1959 cell
->parameters
["\\WIDTH"] = sig_q
.size();
1960 cell
->setPort("\\SET", sig_set
);
1961 cell
->setPort("\\CLR", sig_clr
);
1962 cell
->setPort("\\Q", sig_q
);
1963 cell
->set_src_attribute(src
);
1967 RTLIL::Cell
* RTLIL::Module::addFf(RTLIL::IdString name
, RTLIL::SigSpec sig_d
, RTLIL::SigSpec sig_q
, const std::string
&src
)
1969 RTLIL::Cell
*cell
= addCell(name
, "$ff");
1970 cell
->parameters
["\\WIDTH"] = sig_q
.size();
1971 cell
->setPort("\\D", sig_d
);
1972 cell
->setPort("\\Q", sig_q
);
1973 cell
->set_src_attribute(src
);
1977 RTLIL::Cell
* RTLIL::Module::addDff(RTLIL::IdString name
, RTLIL::SigSpec sig_clk
, RTLIL::SigSpec sig_d
, RTLIL::SigSpec sig_q
, bool clk_polarity
, const std::string
&src
)
1979 RTLIL::Cell
*cell
= addCell(name
, "$dff");
1980 cell
->parameters
["\\CLK_POLARITY"] = clk_polarity
;
1981 cell
->parameters
["\\WIDTH"] = sig_q
.size();
1982 cell
->setPort("\\CLK", sig_clk
);
1983 cell
->setPort("\\D", sig_d
);
1984 cell
->setPort("\\Q", sig_q
);
1985 cell
->set_src_attribute(src
);
1989 RTLIL::Cell
* RTLIL::Module::addDffe(RTLIL::IdString name
, RTLIL::SigSpec sig_clk
, RTLIL::SigSpec sig_en
, RTLIL::SigSpec sig_d
, RTLIL::SigSpec sig_q
, bool clk_polarity
, bool en_polarity
, const std::string
&src
)
1991 RTLIL::Cell
*cell
= addCell(name
, "$dffe");
1992 cell
->parameters
["\\CLK_POLARITY"] = clk_polarity
;
1993 cell
->parameters
["\\EN_POLARITY"] = en_polarity
;
1994 cell
->parameters
["\\WIDTH"] = sig_q
.size();
1995 cell
->setPort("\\CLK", sig_clk
);
1996 cell
->setPort("\\EN", sig_en
);
1997 cell
->setPort("\\D", sig_d
);
1998 cell
->setPort("\\Q", sig_q
);
1999 cell
->set_src_attribute(src
);
2003 RTLIL::Cell
* RTLIL::Module::addDffsr(RTLIL::IdString name
, RTLIL::SigSpec sig_clk
, RTLIL::SigSpec sig_set
, RTLIL::SigSpec sig_clr
,
2004 RTLIL::SigSpec sig_d
, RTLIL::SigSpec sig_q
, bool clk_polarity
, bool set_polarity
, bool clr_polarity
, const std::string
&src
)
2006 RTLIL::Cell
*cell
= addCell(name
, "$dffsr");
2007 cell
->parameters
["\\CLK_POLARITY"] = clk_polarity
;
2008 cell
->parameters
["\\SET_POLARITY"] = set_polarity
;
2009 cell
->parameters
["\\CLR_POLARITY"] = clr_polarity
;
2010 cell
->parameters
["\\WIDTH"] = sig_q
.size();
2011 cell
->setPort("\\CLK", sig_clk
);
2012 cell
->setPort("\\SET", sig_set
);
2013 cell
->setPort("\\CLR", sig_clr
);
2014 cell
->setPort("\\D", sig_d
);
2015 cell
->setPort("\\Q", sig_q
);
2016 cell
->set_src_attribute(src
);
2020 RTLIL::Cell
* RTLIL::Module::addAdff(RTLIL::IdString name
, RTLIL::SigSpec sig_clk
, RTLIL::SigSpec sig_arst
, RTLIL::SigSpec sig_d
, RTLIL::SigSpec sig_q
,
2021 RTLIL::Const arst_value
, bool clk_polarity
, bool arst_polarity
, const std::string
&src
)
2023 RTLIL::Cell
*cell
= addCell(name
, "$adff");
2024 cell
->parameters
["\\CLK_POLARITY"] = clk_polarity
;
2025 cell
->parameters
["\\ARST_POLARITY"] = arst_polarity
;
2026 cell
->parameters
["\\ARST_VALUE"] = arst_value
;
2027 cell
->parameters
["\\WIDTH"] = sig_q
.size();
2028 cell
->setPort("\\CLK", sig_clk
);
2029 cell
->setPort("\\ARST", sig_arst
);
2030 cell
->setPort("\\D", sig_d
);
2031 cell
->setPort("\\Q", sig_q
);
2032 cell
->set_src_attribute(src
);
2036 RTLIL::Cell
* RTLIL::Module::addDlatch(RTLIL::IdString name
, RTLIL::SigSpec sig_en
, RTLIL::SigSpec sig_d
, RTLIL::SigSpec sig_q
, bool en_polarity
, const std::string
&src
)
2038 RTLIL::Cell
*cell
= addCell(name
, "$dlatch");
2039 cell
->parameters
["\\EN_POLARITY"] = en_polarity
;
2040 cell
->parameters
["\\WIDTH"] = sig_q
.size();
2041 cell
->setPort("\\EN", sig_en
);
2042 cell
->setPort("\\D", sig_d
);
2043 cell
->setPort("\\Q", sig_q
);
2044 cell
->set_src_attribute(src
);
2048 RTLIL::Cell
* RTLIL::Module::addDlatchsr(RTLIL::IdString name
, RTLIL::SigSpec sig_en
, RTLIL::SigSpec sig_set
, RTLIL::SigSpec sig_clr
,
2049 RTLIL::SigSpec sig_d
, RTLIL::SigSpec sig_q
, bool en_polarity
, bool set_polarity
, bool clr_polarity
, const std::string
&src
)
2051 RTLIL::Cell
*cell
= addCell(name
, "$dlatchsr");
2052 cell
->parameters
["\\EN_POLARITY"] = en_polarity
;
2053 cell
->parameters
["\\SET_POLARITY"] = set_polarity
;
2054 cell
->parameters
["\\CLR_POLARITY"] = clr_polarity
;
2055 cell
->parameters
["\\WIDTH"] = sig_q
.size();
2056 cell
->setPort("\\EN", sig_en
);
2057 cell
->setPort("\\SET", sig_set
);
2058 cell
->setPort("\\CLR", sig_clr
);
2059 cell
->setPort("\\D", sig_d
);
2060 cell
->setPort("\\Q", sig_q
);
2061 cell
->set_src_attribute(src
);
2065 RTLIL::Cell
* RTLIL::Module::addFfGate(RTLIL::IdString name
, RTLIL::SigSpec sig_d
, RTLIL::SigSpec sig_q
, const std::string
&src
)
2067 RTLIL::Cell
*cell
= addCell(name
, "$_FF_");
2068 cell
->setPort("\\D", sig_d
);
2069 cell
->setPort("\\Q", sig_q
);
2070 cell
->set_src_attribute(src
);
2074 RTLIL::Cell
* RTLIL::Module::addDffGate(RTLIL::IdString name
, RTLIL::SigSpec sig_clk
, RTLIL::SigSpec sig_d
, RTLIL::SigSpec sig_q
, bool clk_polarity
, const std::string
&src
)
2076 RTLIL::Cell
*cell
= addCell(name
, stringf("$_DFF_%c_", clk_polarity
? 'P' : 'N'));
2077 cell
->setPort("\\C", sig_clk
);
2078 cell
->setPort("\\D", sig_d
);
2079 cell
->setPort("\\Q", sig_q
);
2080 cell
->set_src_attribute(src
);
2084 RTLIL::Cell
* RTLIL::Module::addDffeGate(RTLIL::IdString name
, RTLIL::SigSpec sig_clk
, RTLIL::SigSpec sig_en
, RTLIL::SigSpec sig_d
, RTLIL::SigSpec sig_q
, bool clk_polarity
, bool en_polarity
, const std::string
&src
)
2086 RTLIL::Cell
*cell
= addCell(name
, stringf("$_DFFE_%c%c_", clk_polarity
? 'P' : 'N', en_polarity
? 'P' : 'N'));
2087 cell
->setPort("\\C", sig_clk
);
2088 cell
->setPort("\\E", sig_en
);
2089 cell
->setPort("\\D", sig_d
);
2090 cell
->setPort("\\Q", sig_q
);
2091 cell
->set_src_attribute(src
);
2095 RTLIL::Cell
* RTLIL::Module::addDffsrGate(RTLIL::IdString name
, RTLIL::SigSpec sig_clk
, RTLIL::SigSpec sig_set
, RTLIL::SigSpec sig_clr
,
2096 RTLIL::SigSpec sig_d
, RTLIL::SigSpec sig_q
, bool clk_polarity
, bool set_polarity
, bool clr_polarity
, const std::string
&src
)
2098 RTLIL::Cell
*cell
= addCell(name
, stringf("$_DFFSR_%c%c%c_", clk_polarity
? 'P' : 'N', set_polarity
? 'P' : 'N', clr_polarity
? 'P' : 'N'));
2099 cell
->setPort("\\C", sig_clk
);
2100 cell
->setPort("\\S", sig_set
);
2101 cell
->setPort("\\R", sig_clr
);
2102 cell
->setPort("\\D", sig_d
);
2103 cell
->setPort("\\Q", sig_q
);
2104 cell
->set_src_attribute(src
);
2108 RTLIL::Cell
* RTLIL::Module::addAdffGate(RTLIL::IdString name
, RTLIL::SigSpec sig_clk
, RTLIL::SigSpec sig_arst
, RTLIL::SigSpec sig_d
, RTLIL::SigSpec sig_q
,
2109 bool arst_value
, bool clk_polarity
, bool arst_polarity
, const std::string
&src
)
2111 RTLIL::Cell
*cell
= addCell(name
, stringf("$_DFF_%c%c%c_", clk_polarity
? 'P' : 'N', arst_polarity
? 'P' : 'N', arst_value
? '1' : '0'));
2112 cell
->setPort("\\C", sig_clk
);
2113 cell
->setPort("\\R", sig_arst
);
2114 cell
->setPort("\\D", sig_d
);
2115 cell
->setPort("\\Q", sig_q
);
2116 cell
->set_src_attribute(src
);
2120 RTLIL::Cell
* RTLIL::Module::addDlatchGate(RTLIL::IdString name
, RTLIL::SigSpec sig_en
, RTLIL::SigSpec sig_d
, RTLIL::SigSpec sig_q
, bool en_polarity
, const std::string
&src
)
2122 RTLIL::Cell
*cell
= addCell(name
, stringf("$_DLATCH_%c_", en_polarity
? 'P' : 'N'));
2123 cell
->setPort("\\E", sig_en
);
2124 cell
->setPort("\\D", sig_d
);
2125 cell
->setPort("\\Q", sig_q
);
2126 cell
->set_src_attribute(src
);
2130 RTLIL::Cell
* RTLIL::Module::addDlatchsrGate(RTLIL::IdString name
, RTLIL::SigSpec sig_en
, RTLIL::SigSpec sig_set
, RTLIL::SigSpec sig_clr
,
2131 RTLIL::SigSpec sig_d
, RTLIL::SigSpec sig_q
, bool en_polarity
, bool set_polarity
, bool clr_polarity
, const std::string
&src
)
2133 RTLIL::Cell
*cell
= addCell(name
, stringf("$_DLATCHSR_%c%c%c_", en_polarity
? 'P' : 'N', set_polarity
? 'P' : 'N', clr_polarity
? 'P' : 'N'));
2134 cell
->setPort("\\E", sig_en
);
2135 cell
->setPort("\\S", sig_set
);
2136 cell
->setPort("\\R", sig_clr
);
2137 cell
->setPort("\\D", sig_d
);
2138 cell
->setPort("\\Q", sig_q
);
2139 cell
->set_src_attribute(src
);
2143 RTLIL::SigSpec
RTLIL::Module::Anyconst(RTLIL::IdString name
, int width
, const std::string
&src
)
2145 RTLIL::SigSpec sig
= addWire(NEW_ID
, width
);
2146 Cell
*cell
= addCell(name
, "$anyconst");
2147 cell
->setParam("\\WIDTH", width
);
2148 cell
->setPort("\\Y", sig
);
2149 cell
->set_src_attribute(src
);
2153 RTLIL::SigSpec
RTLIL::Module::Anyseq(RTLIL::IdString name
, int width
, const std::string
&src
)
2155 RTLIL::SigSpec sig
= addWire(NEW_ID
, width
);
2156 Cell
*cell
= addCell(name
, "$anyseq");
2157 cell
->setParam("\\WIDTH", width
);
2158 cell
->setPort("\\Y", sig
);
2159 cell
->set_src_attribute(src
);
2163 RTLIL::SigSpec
RTLIL::Module::Allconst(RTLIL::IdString name
, int width
, const std::string
&src
)
2165 RTLIL::SigSpec sig
= addWire(NEW_ID
, width
);
2166 Cell
*cell
= addCell(name
, "$allconst");
2167 cell
->setParam("\\WIDTH", width
);
2168 cell
->setPort("\\Y", sig
);
2169 cell
->set_src_attribute(src
);
2173 RTLIL::SigSpec
RTLIL::Module::Allseq(RTLIL::IdString name
, int width
, const std::string
&src
)
2175 RTLIL::SigSpec sig
= addWire(NEW_ID
, width
);
2176 Cell
*cell
= addCell(name
, "$allseq");
2177 cell
->setParam("\\WIDTH", width
);
2178 cell
->setPort("\\Y", sig
);
2179 cell
->set_src_attribute(src
);
2183 RTLIL::SigSpec
RTLIL::Module::Initstate(RTLIL::IdString name
, const std::string
&src
)
2185 RTLIL::SigSpec sig
= addWire(NEW_ID
);
2186 Cell
*cell
= addCell(name
, "$initstate");
2187 cell
->setPort("\\Y", sig
);
2188 cell
->set_src_attribute(src
);
2194 static unsigned int hashidx_count
= 123456789;
2195 hashidx_count
= mkhash_xorshift(hashidx_count
);
2196 hashidx_
= hashidx_count
;
2203 port_output
= false;
2207 RTLIL::Memory::Memory()
2209 static unsigned int hashidx_count
= 123456789;
2210 hashidx_count
= mkhash_xorshift(hashidx_count
);
2211 hashidx_
= hashidx_count
;
2218 RTLIL::Cell::Cell() : module(nullptr)
2220 static unsigned int hashidx_count
= 123456789;
2221 hashidx_count
= mkhash_xorshift(hashidx_count
);
2222 hashidx_
= hashidx_count
;
2224 // log("#memtrace# %p\n", this);
2228 bool RTLIL::Cell::hasPort(RTLIL::IdString portname
) const
2230 return connections_
.count(portname
) != 0;
2233 void RTLIL::Cell::unsetPort(RTLIL::IdString portname
)
2235 RTLIL::SigSpec signal
;
2236 auto conn_it
= connections_
.find(portname
);
2238 if (conn_it
!= connections_
.end())
2240 for (auto mon
: module
->monitors
)
2241 mon
->notify_connect(this, conn_it
->first
, conn_it
->second
, signal
);
2244 for (auto mon
: module
->design
->monitors
)
2245 mon
->notify_connect(this, conn_it
->first
, conn_it
->second
, signal
);
2248 log("#X# Unconnect %s.%s.%s\n", log_id(this->module
), log_id(this), log_id(portname
));
2249 log_backtrace("-X- ", yosys_xtrace
-1);
2252 connections_
.erase(conn_it
);
2256 void RTLIL::Cell::setPort(RTLIL::IdString portname
, RTLIL::SigSpec signal
)
2258 auto conn_it
= connections_
.find(portname
);
2260 if (conn_it
== connections_
.end()) {
2261 connections_
[portname
] = RTLIL::SigSpec();
2262 conn_it
= connections_
.find(portname
);
2263 log_assert(conn_it
!= connections_
.end());
2265 if (conn_it
->second
== signal
)
2268 for (auto mon
: module
->monitors
)
2269 mon
->notify_connect(this, conn_it
->first
, conn_it
->second
, signal
);
2272 for (auto mon
: module
->design
->monitors
)
2273 mon
->notify_connect(this, conn_it
->first
, conn_it
->second
, signal
);
2276 log("#X# Connect %s.%s.%s = %s (%d)\n", log_id(this->module
), log_id(this), log_id(portname
), log_signal(signal
), GetSize(signal
));
2277 log_backtrace("-X- ", yosys_xtrace
-1);
2280 conn_it
->second
= signal
;
2283 const RTLIL::SigSpec
&RTLIL::Cell::getPort(RTLIL::IdString portname
) const
2285 return connections_
.at(portname
);
2288 const dict
<RTLIL::IdString
, RTLIL::SigSpec
> &RTLIL::Cell::connections() const
2290 return connections_
;
2293 bool RTLIL::Cell::known() const
2295 if (yosys_celltypes
.cell_known(type
))
2297 if (module
&& module
->design
&& module
->design
->module(type
))
2302 bool RTLIL::Cell::input(RTLIL::IdString portname
) const
2304 if (yosys_celltypes
.cell_known(type
))
2305 return yosys_celltypes
.cell_input(type
, portname
);
2306 if (module
&& module
->design
) {
2307 RTLIL::Module
*m
= module
->design
->module(type
);
2308 RTLIL::Wire
*w
= m
? m
->wire(portname
) : nullptr;
2309 return w
&& w
->port_input
;
2314 bool RTLIL::Cell::output(RTLIL::IdString portname
) const
2316 if (yosys_celltypes
.cell_known(type
))
2317 return yosys_celltypes
.cell_output(type
, portname
);
2318 if (module
&& module
->design
) {
2319 RTLIL::Module
*m
= module
->design
->module(type
);
2320 RTLIL::Wire
*w
= m
? m
->wire(portname
) : nullptr;
2321 return w
&& w
->port_output
;
2326 bool RTLIL::Cell::hasParam(RTLIL::IdString paramname
) const
2328 return parameters
.count(paramname
) != 0;
2331 void RTLIL::Cell::unsetParam(RTLIL::IdString paramname
)
2333 parameters
.erase(paramname
);
2336 void RTLIL::Cell::setParam(RTLIL::IdString paramname
, RTLIL::Const value
)
2338 parameters
[paramname
] = value
;
2341 const RTLIL::Const
&RTLIL::Cell::getParam(RTLIL::IdString paramname
) const
2343 return parameters
.at(paramname
);
2346 void RTLIL::Cell::sort()
2348 connections_
.sort(sort_by_id_str());
2349 parameters
.sort(sort_by_id_str());
2350 attributes
.sort(sort_by_id_str());
2353 void RTLIL::Cell::check()
2356 InternalCellChecker
checker(NULL
, this);
2361 void RTLIL::Cell::fixup_parameters(bool set_a_signed
, bool set_b_signed
)
2363 if (type
.substr(0, 1) != "$" || type
.substr(0, 2) == "$_" || type
.substr(0, 8) == "$paramod" || type
.substr(0,10) == "$fmcombine" ||
2364 type
.substr(0, 9) == "$verific$" || type
.substr(0, 7) == "$array:" || type
.substr(0, 8) == "$extern:")
2367 if (type
== "$mux" || type
== "$pmux") {
2368 parameters
["\\WIDTH"] = GetSize(connections_
["\\Y"]);
2369 if (type
== "$pmux")
2370 parameters
["\\S_WIDTH"] = GetSize(connections_
["\\S"]);
2375 if (type
== "$lut" || type
== "$sop") {
2376 parameters
["\\WIDTH"] = GetSize(connections_
["\\A"]);
2380 if (type
== "$fa") {
2381 parameters
["\\WIDTH"] = GetSize(connections_
["\\Y"]);
2385 if (type
== "$lcu") {
2386 parameters
["\\WIDTH"] = GetSize(connections_
["\\CO"]);
2390 bool signedness_ab
= !type
.in("$slice", "$concat", "$macc");
2392 if (connections_
.count("\\A")) {
2393 if (signedness_ab
) {
2395 parameters
["\\A_SIGNED"] = true;
2396 else if (parameters
.count("\\A_SIGNED") == 0)
2397 parameters
["\\A_SIGNED"] = false;
2399 parameters
["\\A_WIDTH"] = GetSize(connections_
["\\A"]);
2402 if (connections_
.count("\\B")) {
2403 if (signedness_ab
) {
2405 parameters
["\\B_SIGNED"] = true;
2406 else if (parameters
.count("\\B_SIGNED") == 0)
2407 parameters
["\\B_SIGNED"] = false;
2409 parameters
["\\B_WIDTH"] = GetSize(connections_
["\\B"]);
2412 if (connections_
.count("\\Y"))
2413 parameters
["\\Y_WIDTH"] = GetSize(connections_
["\\Y"]);
2415 if (connections_
.count("\\Q"))
2416 parameters
["\\WIDTH"] = GetSize(connections_
["\\Q"]);
2421 RTLIL::SigChunk::SigChunk()
2428 RTLIL::SigChunk::SigChunk(const RTLIL::Const
&value
)
2432 width
= GetSize(data
);
2436 RTLIL::SigChunk::SigChunk(RTLIL::Wire
*wire
)
2438 log_assert(wire
!= nullptr);
2440 this->width
= wire
->width
;
2444 RTLIL::SigChunk::SigChunk(RTLIL::Wire
*wire
, int offset
, int width
)
2446 log_assert(wire
!= nullptr);
2448 this->width
= width
;
2449 this->offset
= offset
;
2452 RTLIL::SigChunk::SigChunk(const std::string
&str
)
2455 data
= RTLIL::Const(str
).bits
;
2456 width
= GetSize(data
);
2460 RTLIL::SigChunk::SigChunk(int val
, int width
)
2463 data
= RTLIL::Const(val
, width
).bits
;
2464 this->width
= GetSize(data
);
2468 RTLIL::SigChunk::SigChunk(RTLIL::State bit
, int width
)
2471 data
= RTLIL::Const(bit
, width
).bits
;
2472 this->width
= GetSize(data
);
2476 RTLIL::SigChunk::SigChunk(RTLIL::SigBit bit
)
2481 data
= RTLIL::Const(bit
.data
).bits
;
2483 offset
= bit
.offset
;
2487 RTLIL::SigChunk
RTLIL::SigChunk::extract(int offset
, int length
) const
2489 RTLIL::SigChunk ret
;
2492 ret
.offset
= this->offset
+ offset
;
2495 for (int i
= 0; i
< length
; i
++)
2496 ret
.data
.push_back(data
[offset
+i
]);
2502 bool RTLIL::SigChunk::operator <(const RTLIL::SigChunk
&other
) const
2504 if (wire
&& other
.wire
)
2505 if (wire
->name
!= other
.wire
->name
)
2506 return wire
->name
< other
.wire
->name
;
2508 if (wire
!= other
.wire
)
2509 return wire
< other
.wire
;
2511 if (offset
!= other
.offset
)
2512 return offset
< other
.offset
;
2514 if (width
!= other
.width
)
2515 return width
< other
.width
;
2517 return data
< other
.data
;
2520 bool RTLIL::SigChunk::operator ==(const RTLIL::SigChunk
&other
) const
2522 return wire
== other
.wire
&& width
== other
.width
&& offset
== other
.offset
&& data
== other
.data
;
2525 bool RTLIL::SigChunk::operator !=(const RTLIL::SigChunk
&other
) const
2532 RTLIL::SigSpec::SigSpec()
2538 RTLIL::SigSpec::SigSpec(const RTLIL::SigSpec
&other
)
2543 RTLIL::SigSpec::SigSpec(std::initializer_list
<RTLIL::SigSpec
> parts
)
2545 cover("kernel.rtlil.sigspec.init.list");
2550 std::vector
<RTLIL::SigSpec
> parts_vec(parts
.begin(), parts
.end());
2551 for (auto it
= parts_vec
.rbegin(); it
!= parts_vec
.rend(); it
++)
2555 const RTLIL::SigSpec
&RTLIL::SigSpec::operator=(const RTLIL::SigSpec
&other
)
2557 cover("kernel.rtlil.sigspec.assign");
2559 width_
= other
.width_
;
2560 hash_
= other
.hash_
;
2561 chunks_
= other
.chunks_
;
2564 if (!other
.bits_
.empty())
2566 RTLIL::SigChunk
*last
= NULL
;
2567 int last_end_offset
= 0;
2569 for (auto &bit
: other
.bits_
) {
2570 if (last
&& bit
.wire
== last
->wire
) {
2571 if (bit
.wire
== NULL
) {
2572 last
->data
.push_back(bit
.data
);
2575 } else if (last_end_offset
== bit
.offset
) {
2581 chunks_
.push_back(bit
);
2582 last
= &chunks_
.back();
2583 last_end_offset
= bit
.offset
+ 1;
2592 RTLIL::SigSpec::SigSpec(const RTLIL::Const
&value
)
2594 cover("kernel.rtlil.sigspec.init.const");
2596 chunks_
.push_back(RTLIL::SigChunk(value
));
2597 width_
= chunks_
.back().width
;
2602 RTLIL::SigSpec::SigSpec(const RTLIL::SigChunk
&chunk
)
2604 cover("kernel.rtlil.sigspec.init.chunk");
2606 chunks_
.push_back(chunk
);
2607 width_
= chunks_
.back().width
;
2612 RTLIL::SigSpec::SigSpec(RTLIL::Wire
*wire
)
2614 cover("kernel.rtlil.sigspec.init.wire");
2616 chunks_
.push_back(RTLIL::SigChunk(wire
));
2617 width_
= chunks_
.back().width
;
2622 RTLIL::SigSpec::SigSpec(RTLIL::Wire
*wire
, int offset
, int width
)
2624 cover("kernel.rtlil.sigspec.init.wire_part");
2626 chunks_
.push_back(RTLIL::SigChunk(wire
, offset
, width
));
2627 width_
= chunks_
.back().width
;
2632 RTLIL::SigSpec::SigSpec(const std::string
&str
)
2634 cover("kernel.rtlil.sigspec.init.str");
2636 chunks_
.push_back(RTLIL::SigChunk(str
));
2637 width_
= chunks_
.back().width
;
2642 RTLIL::SigSpec::SigSpec(int val
, int width
)
2644 cover("kernel.rtlil.sigspec.init.int");
2646 chunks_
.push_back(RTLIL::SigChunk(val
, width
));
2652 RTLIL::SigSpec::SigSpec(RTLIL::State bit
, int width
)
2654 cover("kernel.rtlil.sigspec.init.state");
2656 chunks_
.push_back(RTLIL::SigChunk(bit
, width
));
2662 RTLIL::SigSpec::SigSpec(RTLIL::SigBit bit
, int width
)
2664 cover("kernel.rtlil.sigspec.init.bit");
2666 if (bit
.wire
== NULL
)
2667 chunks_
.push_back(RTLIL::SigChunk(bit
.data
, width
));
2669 for (int i
= 0; i
< width
; i
++)
2670 chunks_
.push_back(bit
);
2676 RTLIL::SigSpec::SigSpec(std::vector
<RTLIL::SigChunk
> chunks
)
2678 cover("kernel.rtlil.sigspec.init.stdvec_chunks");
2682 for (auto &c
: chunks
)
2687 RTLIL::SigSpec::SigSpec(std::vector
<RTLIL::SigBit
> bits
)
2689 cover("kernel.rtlil.sigspec.init.stdvec_bits");
2693 for (auto &bit
: bits
)
2698 RTLIL::SigSpec::SigSpec(pool
<RTLIL::SigBit
> bits
)
2700 cover("kernel.rtlil.sigspec.init.pool_bits");
2704 for (auto &bit
: bits
)
2709 RTLIL::SigSpec::SigSpec(std::set
<RTLIL::SigBit
> bits
)
2711 cover("kernel.rtlil.sigspec.init.stdset_bits");
2715 for (auto &bit
: bits
)
2720 RTLIL::SigSpec::SigSpec(bool bit
)
2722 cover("kernel.rtlil.sigspec.init.bool");
2730 void RTLIL::SigSpec::pack() const
2732 RTLIL::SigSpec
*that
= (RTLIL::SigSpec
*)this;
2734 if (that
->bits_
.empty())
2737 cover("kernel.rtlil.sigspec.convert.pack");
2738 log_assert(that
->chunks_
.empty());
2740 std::vector
<RTLIL::SigBit
> old_bits
;
2741 old_bits
.swap(that
->bits_
);
2743 RTLIL::SigChunk
*last
= NULL
;
2744 int last_end_offset
= 0;
2746 for (auto &bit
: old_bits
) {
2747 if (last
&& bit
.wire
== last
->wire
) {
2748 if (bit
.wire
== NULL
) {
2749 last
->data
.push_back(bit
.data
);
2752 } else if (last_end_offset
== bit
.offset
) {
2758 that
->chunks_
.push_back(bit
);
2759 last
= &that
->chunks_
.back();
2760 last_end_offset
= bit
.offset
+ 1;
2766 void RTLIL::SigSpec::unpack() const
2768 RTLIL::SigSpec
*that
= (RTLIL::SigSpec
*)this;
2770 if (that
->chunks_
.empty())
2773 cover("kernel.rtlil.sigspec.convert.unpack");
2774 log_assert(that
->bits_
.empty());
2776 that
->bits_
.reserve(that
->width_
);
2777 for (auto &c
: that
->chunks_
)
2778 for (int i
= 0; i
< c
.width
; i
++)
2779 that
->bits_
.push_back(RTLIL::SigBit(c
, i
));
2781 that
->chunks_
.clear();
2785 void RTLIL::SigSpec::updhash() const
2787 RTLIL::SigSpec
*that
= (RTLIL::SigSpec
*)this;
2789 if (that
->hash_
!= 0)
2792 cover("kernel.rtlil.sigspec.hash");
2795 that
->hash_
= mkhash_init
;
2796 for (auto &c
: that
->chunks_
)
2797 if (c
.wire
== NULL
) {
2798 for (auto &v
: c
.data
)
2799 that
->hash_
= mkhash(that
->hash_
, v
);
2801 that
->hash_
= mkhash(that
->hash_
, c
.wire
->name
.index_
);
2802 that
->hash_
= mkhash(that
->hash_
, c
.offset
);
2803 that
->hash_
= mkhash(that
->hash_
, c
.width
);
2806 if (that
->hash_
== 0)
2810 void RTLIL::SigSpec::sort()
2813 cover("kernel.rtlil.sigspec.sort");
2814 std::sort(bits_
.begin(), bits_
.end());
2817 void RTLIL::SigSpec::sort_and_unify()
2820 cover("kernel.rtlil.sigspec.sort_and_unify");
2822 // A copy of the bits vector is used to prevent duplicating the logic from
2823 // SigSpec::SigSpec(std::vector<SigBit>). This incurrs an extra copy but
2824 // that isn't showing up as significant in profiles.
2825 std::vector
<SigBit
> unique_bits
= bits_
;
2826 std::sort(unique_bits
.begin(), unique_bits
.end());
2827 auto last
= std::unique(unique_bits
.begin(), unique_bits
.end());
2828 unique_bits
.erase(last
, unique_bits
.end());
2830 *this = unique_bits
;
2833 void RTLIL::SigSpec::replace(const RTLIL::SigSpec
&pattern
, const RTLIL::SigSpec
&with
)
2835 replace(pattern
, with
, this);
2838 void RTLIL::SigSpec::replace(const RTLIL::SigSpec
&pattern
, const RTLIL::SigSpec
&with
, RTLIL::SigSpec
*other
) const
2840 log_assert(other
!= NULL
);
2841 log_assert(width_
== other
->width_
);
2842 log_assert(pattern
.width_
== with
.width_
);
2849 for (int i
= 0; i
< GetSize(pattern
.bits_
); i
++) {
2850 if (pattern
.bits_
[i
].wire
!= NULL
) {
2851 for (int j
= 0; j
< GetSize(bits_
); j
++) {
2852 if (bits_
[j
] == pattern
.bits_
[i
]) {
2853 other
->bits_
[j
] = with
.bits_
[i
];
2862 void RTLIL::SigSpec::replace(const dict
<RTLIL::SigBit
, RTLIL::SigBit
> &rules
)
2864 replace(rules
, this);
2867 void RTLIL::SigSpec::replace(const dict
<RTLIL::SigBit
, RTLIL::SigBit
> &rules
, RTLIL::SigSpec
*other
) const
2869 cover("kernel.rtlil.sigspec.replace_dict");
2871 log_assert(other
!= NULL
);
2872 log_assert(width_
== other
->width_
);
2877 for (int i
= 0; i
< GetSize(bits_
); i
++) {
2878 auto it
= rules
.find(bits_
[i
]);
2879 if (it
!= rules
.end())
2880 other
->bits_
[i
] = it
->second
;
2886 void RTLIL::SigSpec::replace(const std::map
<RTLIL::SigBit
, RTLIL::SigBit
> &rules
)
2888 replace(rules
, this);
2891 void RTLIL::SigSpec::replace(const std::map
<RTLIL::SigBit
, RTLIL::SigBit
> &rules
, RTLIL::SigSpec
*other
) const
2893 cover("kernel.rtlil.sigspec.replace_map");
2895 log_assert(other
!= NULL
);
2896 log_assert(width_
== other
->width_
);
2901 for (int i
= 0; i
< GetSize(bits_
); i
++) {
2902 auto it
= rules
.find(bits_
[i
]);
2903 if (it
!= rules
.end())
2904 other
->bits_
[i
] = it
->second
;
2910 void RTLIL::SigSpec::remove(const RTLIL::SigSpec
&pattern
)
2912 remove2(pattern
, NULL
);
2915 void RTLIL::SigSpec::remove(const RTLIL::SigSpec
&pattern
, RTLIL::SigSpec
*other
) const
2917 RTLIL::SigSpec tmp
= *this;
2918 tmp
.remove2(pattern
, other
);
2921 void RTLIL::SigSpec::remove2(const RTLIL::SigSpec
&pattern
, RTLIL::SigSpec
*other
)
2924 cover("kernel.rtlil.sigspec.remove_other");
2926 cover("kernel.rtlil.sigspec.remove");
2929 if (other
!= NULL
) {
2930 log_assert(width_
== other
->width_
);
2934 for (int i
= GetSize(bits_
) - 1; i
>= 0; i
--)
2936 if (bits_
[i
].wire
== NULL
) continue;
2938 for (auto &pattern_chunk
: pattern
.chunks())
2939 if (bits_
[i
].wire
== pattern_chunk
.wire
&&
2940 bits_
[i
].offset
>= pattern_chunk
.offset
&&
2941 bits_
[i
].offset
< pattern_chunk
.offset
+ pattern_chunk
.width
) {
2942 bits_
.erase(bits_
.begin() + i
);
2944 if (other
!= NULL
) {
2945 other
->bits_
.erase(other
->bits_
.begin() + i
);
2955 void RTLIL::SigSpec::remove(const pool
<RTLIL::SigBit
> &pattern
)
2957 remove2(pattern
, NULL
);
2960 void RTLIL::SigSpec::remove(const pool
<RTLIL::SigBit
> &pattern
, RTLIL::SigSpec
*other
) const
2962 RTLIL::SigSpec tmp
= *this;
2963 tmp
.remove2(pattern
, other
);
2966 void RTLIL::SigSpec::remove2(const pool
<RTLIL::SigBit
> &pattern
, RTLIL::SigSpec
*other
)
2969 cover("kernel.rtlil.sigspec.remove_other");
2971 cover("kernel.rtlil.sigspec.remove");
2975 if (other
!= NULL
) {
2976 log_assert(width_
== other
->width_
);
2980 for (int i
= GetSize(bits_
) - 1; i
>= 0; i
--) {
2981 if (bits_
[i
].wire
!= NULL
&& pattern
.count(bits_
[i
])) {
2982 bits_
.erase(bits_
.begin() + i
);
2984 if (other
!= NULL
) {
2985 other
->bits_
.erase(other
->bits_
.begin() + i
);
2994 void RTLIL::SigSpec::remove2(const std::set
<RTLIL::SigBit
> &pattern
, RTLIL::SigSpec
*other
)
2997 cover("kernel.rtlil.sigspec.remove_other");
2999 cover("kernel.rtlil.sigspec.remove");
3003 if (other
!= NULL
) {
3004 log_assert(width_
== other
->width_
);
3008 for (int i
= GetSize(bits_
) - 1; i
>= 0; i
--) {
3009 if (bits_
[i
].wire
!= NULL
&& pattern
.count(bits_
[i
])) {
3010 bits_
.erase(bits_
.begin() + i
);
3012 if (other
!= NULL
) {
3013 other
->bits_
.erase(other
->bits_
.begin() + i
);
3022 RTLIL::SigSpec
RTLIL::SigSpec::extract(const RTLIL::SigSpec
&pattern
, const RTLIL::SigSpec
*other
) const
3025 cover("kernel.rtlil.sigspec.extract_other");
3027 cover("kernel.rtlil.sigspec.extract");
3029 log_assert(other
== NULL
|| width_
== other
->width_
);
3032 std::vector
<RTLIL::SigBit
> bits_match
= to_sigbit_vector();
3034 for (auto& pattern_chunk
: pattern
.chunks()) {
3036 std::vector
<RTLIL::SigBit
> bits_other
= other
->to_sigbit_vector();
3037 for (int i
= 0; i
< width_
; i
++)
3038 if (bits_match
[i
].wire
&&
3039 bits_match
[i
].wire
== pattern_chunk
.wire
&&
3040 bits_match
[i
].offset
>= pattern_chunk
.offset
&&
3041 bits_match
[i
].offset
< pattern_chunk
.offset
+ pattern_chunk
.width
)
3042 ret
.append_bit(bits_other
[i
]);
3044 for (int i
= 0; i
< width_
; i
++)
3045 if (bits_match
[i
].wire
&&
3046 bits_match
[i
].wire
== pattern_chunk
.wire
&&
3047 bits_match
[i
].offset
>= pattern_chunk
.offset
&&
3048 bits_match
[i
].offset
< pattern_chunk
.offset
+ pattern_chunk
.width
)
3049 ret
.append_bit(bits_match
[i
]);
3057 RTLIL::SigSpec
RTLIL::SigSpec::extract(const pool
<RTLIL::SigBit
> &pattern
, const RTLIL::SigSpec
*other
) const
3060 cover("kernel.rtlil.sigspec.extract_other");
3062 cover("kernel.rtlil.sigspec.extract");
3064 log_assert(other
== NULL
|| width_
== other
->width_
);
3066 std::vector
<RTLIL::SigBit
> bits_match
= to_sigbit_vector();
3070 std::vector
<RTLIL::SigBit
> bits_other
= other
->to_sigbit_vector();
3071 for (int i
= 0; i
< width_
; i
++)
3072 if (bits_match
[i
].wire
&& pattern
.count(bits_match
[i
]))
3073 ret
.append_bit(bits_other
[i
]);
3075 for (int i
= 0; i
< width_
; i
++)
3076 if (bits_match
[i
].wire
&& pattern
.count(bits_match
[i
]))
3077 ret
.append_bit(bits_match
[i
]);
3084 void RTLIL::SigSpec::replace(int offset
, const RTLIL::SigSpec
&with
)
3086 cover("kernel.rtlil.sigspec.replace_pos");
3091 log_assert(offset
>= 0);
3092 log_assert(with
.width_
>= 0);
3093 log_assert(offset
+with
.width_
<= width_
);
3095 for (int i
= 0; i
< with
.width_
; i
++)
3096 bits_
.at(offset
+ i
) = with
.bits_
.at(i
);
3101 void RTLIL::SigSpec::remove_const()
3105 cover("kernel.rtlil.sigspec.remove_const.packed");
3107 std::vector
<RTLIL::SigChunk
> new_chunks
;
3108 new_chunks
.reserve(GetSize(chunks_
));
3111 for (auto &chunk
: chunks_
)
3112 if (chunk
.wire
!= NULL
) {
3113 new_chunks
.push_back(chunk
);
3114 width_
+= chunk
.width
;
3117 chunks_
.swap(new_chunks
);
3121 cover("kernel.rtlil.sigspec.remove_const.unpacked");
3123 std::vector
<RTLIL::SigBit
> new_bits
;
3124 new_bits
.reserve(width_
);
3126 for (auto &bit
: bits_
)
3127 if (bit
.wire
!= NULL
)
3128 new_bits
.push_back(bit
);
3130 bits_
.swap(new_bits
);
3131 width_
= bits_
.size();
3137 void RTLIL::SigSpec::remove(int offset
, int length
)
3139 cover("kernel.rtlil.sigspec.remove_pos");
3143 log_assert(offset
>= 0);
3144 log_assert(length
>= 0);
3145 log_assert(offset
+ length
<= width_
);
3147 bits_
.erase(bits_
.begin() + offset
, bits_
.begin() + offset
+ length
);
3148 width_
= bits_
.size();
3153 RTLIL::SigSpec
RTLIL::SigSpec::extract(int offset
, int length
) const
3156 cover("kernel.rtlil.sigspec.extract_pos");
3157 return std::vector
<RTLIL::SigBit
>(bits_
.begin() + offset
, bits_
.begin() + offset
+ length
);
3160 void RTLIL::SigSpec::append(const RTLIL::SigSpec
&signal
)
3162 if (signal
.width_
== 0)
3170 cover("kernel.rtlil.sigspec.append");
3172 if (packed() != signal
.packed()) {
3178 for (auto &other_c
: signal
.chunks_
)
3180 auto &my_last_c
= chunks_
.back();
3181 if (my_last_c
.wire
== NULL
&& other_c
.wire
== NULL
) {
3182 auto &this_data
= my_last_c
.data
;
3183 auto &other_data
= other_c
.data
;
3184 this_data
.insert(this_data
.end(), other_data
.begin(), other_data
.end());
3185 my_last_c
.width
+= other_c
.width
;
3187 if (my_last_c
.wire
== other_c
.wire
&& my_last_c
.offset
+ my_last_c
.width
== other_c
.offset
) {
3188 my_last_c
.width
+= other_c
.width
;
3190 chunks_
.push_back(other_c
);
3193 bits_
.insert(bits_
.end(), signal
.bits_
.begin(), signal
.bits_
.end());
3195 width_
+= signal
.width_
;
3199 void RTLIL::SigSpec::append_bit(const RTLIL::SigBit
&bit
)
3203 cover("kernel.rtlil.sigspec.append_bit.packed");
3205 if (chunks_
.size() == 0)
3206 chunks_
.push_back(bit
);
3208 if (bit
.wire
== NULL
)
3209 if (chunks_
.back().wire
== NULL
) {
3210 chunks_
.back().data
.push_back(bit
.data
);
3211 chunks_
.back().width
++;
3213 chunks_
.push_back(bit
);
3215 if (chunks_
.back().wire
== bit
.wire
&& chunks_
.back().offset
+ chunks_
.back().width
== bit
.offset
)
3216 chunks_
.back().width
++;
3218 chunks_
.push_back(bit
);
3222 cover("kernel.rtlil.sigspec.append_bit.unpacked");
3223 bits_
.push_back(bit
);
3230 void RTLIL::SigSpec::extend_u0(int width
, bool is_signed
)
3232 cover("kernel.rtlil.sigspec.extend_u0");
3237 remove(width
, width_
- width
);
3239 if (width_
< width
) {
3240 RTLIL::SigBit padding
= width_
> 0 ? (*this)[width_
- 1] : RTLIL::State::S0
;
3242 padding
= RTLIL::State::S0
;
3243 while (width_
< width
)
3249 RTLIL::SigSpec
RTLIL::SigSpec::repeat(int num
) const
3251 cover("kernel.rtlil.sigspec.repeat");
3254 for (int i
= 0; i
< num
; i
++)
3260 void RTLIL::SigSpec::check() const
3264 cover("kernel.rtlil.sigspec.check.skip");
3268 cover("kernel.rtlil.sigspec.check.packed");
3271 for (size_t i
= 0; i
< chunks_
.size(); i
++) {
3272 const RTLIL::SigChunk chunk
= chunks_
[i
];
3273 if (chunk
.wire
== NULL
) {
3275 log_assert(chunks_
[i
-1].wire
!= NULL
);
3276 log_assert(chunk
.offset
== 0);
3277 log_assert(chunk
.data
.size() == (size_t)chunk
.width
);
3279 if (i
> 0 && chunks_
[i
-1].wire
== chunk
.wire
)
3280 log_assert(chunk
.offset
!= chunks_
[i
-1].offset
+ chunks_
[i
-1].width
);
3281 log_assert(chunk
.offset
>= 0);
3282 log_assert(chunk
.width
>= 0);
3283 log_assert(chunk
.offset
+ chunk
.width
<= chunk
.wire
->width
);
3284 log_assert(chunk
.data
.size() == 0);
3288 log_assert(w
== width_
);
3289 log_assert(bits_
.empty());
3293 cover("kernel.rtlil.sigspec.check.unpacked");
3295 log_assert(width_
== GetSize(bits_
));
3296 log_assert(chunks_
.empty());
3301 bool RTLIL::SigSpec::operator <(const RTLIL::SigSpec
&other
) const
3303 cover("kernel.rtlil.sigspec.comp_lt");
3308 if (width_
!= other
.width_
)
3309 return width_
< other
.width_
;
3314 if (chunks_
.size() != other
.chunks_
.size())
3315 return chunks_
.size() < other
.chunks_
.size();
3320 if (hash_
!= other
.hash_
)
3321 return hash_
< other
.hash_
;
3323 for (size_t i
= 0; i
< chunks_
.size(); i
++)
3324 if (chunks_
[i
] != other
.chunks_
[i
]) {
3325 cover("kernel.rtlil.sigspec.comp_lt.hash_collision");
3326 return chunks_
[i
] < other
.chunks_
[i
];
3329 cover("kernel.rtlil.sigspec.comp_lt.equal");
3333 bool RTLIL::SigSpec::operator ==(const RTLIL::SigSpec
&other
) const
3335 cover("kernel.rtlil.sigspec.comp_eq");
3340 if (width_
!= other
.width_
)
3346 if (chunks_
.size() != chunks_
.size())
3352 if (hash_
!= other
.hash_
)
3355 for (size_t i
= 0; i
< chunks_
.size(); i
++)
3356 if (chunks_
[i
] != other
.chunks_
[i
]) {
3357 cover("kernel.rtlil.sigspec.comp_eq.hash_collision");
3361 cover("kernel.rtlil.sigspec.comp_eq.equal");
3365 bool RTLIL::SigSpec::is_wire() const
3367 cover("kernel.rtlil.sigspec.is_wire");
3370 return GetSize(chunks_
) == 1 && chunks_
[0].wire
&& chunks_
[0].wire
->width
== width_
;
3373 bool RTLIL::SigSpec::is_chunk() const
3375 cover("kernel.rtlil.sigspec.is_chunk");
3378 return GetSize(chunks_
) == 1;
3381 bool RTLIL::SigSpec::is_fully_const() const
3383 cover("kernel.rtlil.sigspec.is_fully_const");
3386 for (auto it
= chunks_
.begin(); it
!= chunks_
.end(); it
++)
3387 if (it
->width
> 0 && it
->wire
!= NULL
)
3392 bool RTLIL::SigSpec::is_fully_zero() const
3394 cover("kernel.rtlil.sigspec.is_fully_zero");
3397 for (auto it
= chunks_
.begin(); it
!= chunks_
.end(); it
++) {
3398 if (it
->width
> 0 && it
->wire
!= NULL
)
3400 for (size_t i
= 0; i
< it
->data
.size(); i
++)
3401 if (it
->data
[i
] != RTLIL::State::S0
)
3407 bool RTLIL::SigSpec::is_fully_ones() const
3409 cover("kernel.rtlil.sigspec.is_fully_ones");
3412 for (auto it
= chunks_
.begin(); it
!= chunks_
.end(); it
++) {
3413 if (it
->width
> 0 && it
->wire
!= NULL
)
3415 for (size_t i
= 0; i
< it
->data
.size(); i
++)
3416 if (it
->data
[i
] != RTLIL::State::S1
)
3422 bool RTLIL::SigSpec::is_fully_def() const
3424 cover("kernel.rtlil.sigspec.is_fully_def");
3427 for (auto it
= chunks_
.begin(); it
!= chunks_
.end(); it
++) {
3428 if (it
->width
> 0 && it
->wire
!= NULL
)
3430 for (size_t i
= 0; i
< it
->data
.size(); i
++)
3431 if (it
->data
[i
] != RTLIL::State::S0
&& it
->data
[i
] != RTLIL::State::S1
)
3437 bool RTLIL::SigSpec::is_fully_undef() const
3439 cover("kernel.rtlil.sigspec.is_fully_undef");
3442 for (auto it
= chunks_
.begin(); it
!= chunks_
.end(); it
++) {
3443 if (it
->width
> 0 && it
->wire
!= NULL
)
3445 for (size_t i
= 0; i
< it
->data
.size(); i
++)
3446 if (it
->data
[i
] != RTLIL::State::Sx
&& it
->data
[i
] != RTLIL::State::Sz
)
3452 bool RTLIL::SigSpec::has_const() const
3454 cover("kernel.rtlil.sigspec.has_const");
3457 for (auto it
= chunks_
.begin(); it
!= chunks_
.end(); it
++)
3458 if (it
->width
> 0 && it
->wire
== NULL
)
3463 bool RTLIL::SigSpec::has_marked_bits() const
3465 cover("kernel.rtlil.sigspec.has_marked_bits");
3468 for (auto it
= chunks_
.begin(); it
!= chunks_
.end(); it
++)
3469 if (it
->width
> 0 && it
->wire
== NULL
) {
3470 for (size_t i
= 0; i
< it
->data
.size(); i
++)
3471 if (it
->data
[i
] == RTLIL::State::Sm
)
3477 bool RTLIL::SigSpec::as_bool() const
3479 cover("kernel.rtlil.sigspec.as_bool");
3482 log_assert(is_fully_const() && GetSize(chunks_
) <= 1);
3484 return RTLIL::Const(chunks_
[0].data
).as_bool();
3488 int RTLIL::SigSpec::as_int(bool is_signed
) const
3490 cover("kernel.rtlil.sigspec.as_int");
3493 log_assert(is_fully_const() && GetSize(chunks_
) <= 1);
3495 return RTLIL::Const(chunks_
[0].data
).as_int(is_signed
);
3499 std::string
RTLIL::SigSpec::as_string() const
3501 cover("kernel.rtlil.sigspec.as_string");
3505 for (size_t i
= chunks_
.size(); i
> 0; i
--) {
3506 const RTLIL::SigChunk
&chunk
= chunks_
[i
-1];
3507 if (chunk
.wire
!= NULL
)
3508 for (int j
= 0; j
< chunk
.width
; j
++)
3511 str
+= RTLIL::Const(chunk
.data
).as_string();
3516 RTLIL::Const
RTLIL::SigSpec::as_const() const
3518 cover("kernel.rtlil.sigspec.as_const");
3521 log_assert(is_fully_const() && GetSize(chunks_
) <= 1);
3523 return chunks_
[0].data
;
3524 return RTLIL::Const();
3527 RTLIL::Wire
*RTLIL::SigSpec::as_wire() const
3529 cover("kernel.rtlil.sigspec.as_wire");
3532 log_assert(is_wire());
3533 return chunks_
[0].wire
;
3536 RTLIL::SigChunk
RTLIL::SigSpec::as_chunk() const
3538 cover("kernel.rtlil.sigspec.as_chunk");
3541 log_assert(is_chunk());
3545 RTLIL::SigBit
RTLIL::SigSpec::as_bit() const
3547 cover("kernel.rtlil.sigspec.as_bit");
3549 log_assert(width_
== 1);
3551 return RTLIL::SigBit(*chunks_
.begin());
3556 bool RTLIL::SigSpec::match(std::string pattern
) const
3558 cover("kernel.rtlil.sigspec.match");
3561 std::string str
= as_string();
3562 log_assert(pattern
.size() == str
.size());
3564 for (size_t i
= 0; i
< pattern
.size(); i
++) {
3565 if (pattern
[i
] == ' ')
3567 if (pattern
[i
] == '*') {
3568 if (str
[i
] != 'z' && str
[i
] != 'x')
3572 if (pattern
[i
] != str
[i
])
3579 std::set
<RTLIL::SigBit
> RTLIL::SigSpec::to_sigbit_set() const
3581 cover("kernel.rtlil.sigspec.to_sigbit_set");
3584 std::set
<RTLIL::SigBit
> sigbits
;
3585 for (auto &c
: chunks_
)
3586 for (int i
= 0; i
< c
.width
; i
++)
3587 sigbits
.insert(RTLIL::SigBit(c
, i
));
3591 pool
<RTLIL::SigBit
> RTLIL::SigSpec::to_sigbit_pool() const
3593 cover("kernel.rtlil.sigspec.to_sigbit_pool");
3596 pool
<RTLIL::SigBit
> sigbits
;
3597 for (auto &c
: chunks_
)
3598 for (int i
= 0; i
< c
.width
; i
++)
3599 sigbits
.insert(RTLIL::SigBit(c
, i
));
3603 std::vector
<RTLIL::SigBit
> RTLIL::SigSpec::to_sigbit_vector() const
3605 cover("kernel.rtlil.sigspec.to_sigbit_vector");
3611 std::map
<RTLIL::SigBit
, RTLIL::SigBit
> RTLIL::SigSpec::to_sigbit_map(const RTLIL::SigSpec
&other
) const
3613 cover("kernel.rtlil.sigspec.to_sigbit_map");
3618 log_assert(width_
== other
.width_
);
3620 std::map
<RTLIL::SigBit
, RTLIL::SigBit
> new_map
;
3621 for (int i
= 0; i
< width_
; i
++)
3622 new_map
[bits_
[i
]] = other
.bits_
[i
];
3627 dict
<RTLIL::SigBit
, RTLIL::SigBit
> RTLIL::SigSpec::to_sigbit_dict(const RTLIL::SigSpec
&other
) const
3629 cover("kernel.rtlil.sigspec.to_sigbit_dict");
3634 log_assert(width_
== other
.width_
);
3636 dict
<RTLIL::SigBit
, RTLIL::SigBit
> new_map
;
3637 for (int i
= 0; i
< width_
; i
++)
3638 new_map
[bits_
[i
]] = other
.bits_
[i
];
3643 static void sigspec_parse_split(std::vector
<std::string
> &tokens
, const std::string
&text
, char sep
)
3645 size_t start
= 0, end
= 0;
3646 while ((end
= text
.find(sep
, start
)) != std::string::npos
) {
3647 tokens
.push_back(text
.substr(start
, end
- start
));
3650 tokens
.push_back(text
.substr(start
));
3653 static int sigspec_parse_get_dummy_line_num()
3658 bool RTLIL::SigSpec::parse(RTLIL::SigSpec
&sig
, RTLIL::Module
*module
, std::string str
)
3660 cover("kernel.rtlil.sigspec.parse");
3662 AST::current_filename
= "input";
3663 AST::use_internal_line_num();
3664 AST::set_line_num(0);
3666 std::vector
<std::string
> tokens
;
3667 sigspec_parse_split(tokens
, str
, ',');
3669 sig
= RTLIL::SigSpec();
3670 for (int tokidx
= int(tokens
.size())-1; tokidx
>= 0; tokidx
--)
3672 std::string netname
= tokens
[tokidx
];
3673 std::string indices
;
3675 if (netname
.size() == 0)
3678 if (('0' <= netname
[0] && netname
[0] <= '9') || netname
[0] == '\'') {
3679 cover("kernel.rtlil.sigspec.parse.const");
3680 AST::get_line_num
= sigspec_parse_get_dummy_line_num
;
3681 AST::AstNode
*ast
= VERILOG_FRONTEND::const2ast(netname
);
3684 sig
.append(RTLIL::Const(ast
->bits
));
3692 cover("kernel.rtlil.sigspec.parse.net");
3694 if (netname
[0] != '$' && netname
[0] != '\\')
3695 netname
= "\\" + netname
;
3697 if (module
->wires_
.count(netname
) == 0) {
3698 size_t indices_pos
= netname
.size()-1;
3699 if (indices_pos
> 2 && netname
[indices_pos
] == ']')
3702 while (indices_pos
> 0 && ('0' <= netname
[indices_pos
] && netname
[indices_pos
] <= '9')) indices_pos
--;
3703 if (indices_pos
> 0 && netname
[indices_pos
] == ':') {
3705 while (indices_pos
> 0 && ('0' <= netname
[indices_pos
] && netname
[indices_pos
] <= '9')) indices_pos
--;
3707 if (indices_pos
> 0 && netname
[indices_pos
] == '[') {
3708 indices
= netname
.substr(indices_pos
);
3709 netname
= netname
.substr(0, indices_pos
);
3714 if (module
->wires_
.count(netname
) == 0)
3717 RTLIL::Wire
*wire
= module
->wires_
.at(netname
);
3718 if (!indices
.empty()) {
3719 std::vector
<std::string
> index_tokens
;
3720 sigspec_parse_split(index_tokens
, indices
.substr(1, indices
.size()-2), ':');
3721 if (index_tokens
.size() == 1) {
3722 cover("kernel.rtlil.sigspec.parse.bit_sel");
3723 int a
= atoi(index_tokens
.at(0).c_str());
3724 if (a
< 0 || a
>= wire
->width
)
3726 sig
.append(RTLIL::SigSpec(wire
, a
));
3728 cover("kernel.rtlil.sigspec.parse.part_sel");
3729 int a
= atoi(index_tokens
.at(0).c_str());
3730 int b
= atoi(index_tokens
.at(1).c_str());
3735 if (a
< 0 || a
>= wire
->width
)
3737 if (b
< 0 || b
>= wire
->width
)
3739 sig
.append(RTLIL::SigSpec(wire
, a
, b
-a
+1));
3748 bool RTLIL::SigSpec::parse_sel(RTLIL::SigSpec
&sig
, RTLIL::Design
*design
, RTLIL::Module
*module
, std::string str
)
3750 if (str
.empty() || str
[0] != '@')
3751 return parse(sig
, module
, str
);
3753 cover("kernel.rtlil.sigspec.parse.sel");
3755 str
= RTLIL::escape_id(str
.substr(1));
3756 if (design
->selection_vars
.count(str
) == 0)
3759 sig
= RTLIL::SigSpec();
3760 RTLIL::Selection
&sel
= design
->selection_vars
.at(str
);
3761 for (auto &it
: module
->wires_
)
3762 if (sel
.selected_member(module
->name
, it
.first
))
3763 sig
.append(it
.second
);
3768 bool RTLIL::SigSpec::parse_rhs(const RTLIL::SigSpec
&lhs
, RTLIL::SigSpec
&sig
, RTLIL::Module
*module
, std::string str
)
3771 cover("kernel.rtlil.sigspec.parse.rhs_zeros");
3772 sig
= RTLIL::SigSpec(RTLIL::State::S0
, lhs
.width_
);
3777 cover("kernel.rtlil.sigspec.parse.rhs_ones");
3778 sig
= RTLIL::SigSpec(RTLIL::State::S1
, lhs
.width_
);
3782 if (lhs
.chunks_
.size() == 1) {
3783 char *p
= (char*)str
.c_str(), *endptr
;
3784 long int val
= strtol(p
, &endptr
, 10);
3785 if (endptr
&& endptr
!= p
&& *endptr
== 0) {
3786 sig
= RTLIL::SigSpec(val
, lhs
.width_
);
3787 cover("kernel.rtlil.sigspec.parse.rhs_dec");
3792 return parse(sig
, module
, str
);
3795 RTLIL::CaseRule::~CaseRule()
3797 for (auto it
= switches
.begin(); it
!= switches
.end(); it
++)
3801 bool RTLIL::CaseRule::empty() const
3803 return actions
.empty() && switches
.empty();
3806 RTLIL::CaseRule
*RTLIL::CaseRule::clone() const
3808 RTLIL::CaseRule
*new_caserule
= new RTLIL::CaseRule
;
3809 new_caserule
->compare
= compare
;
3810 new_caserule
->actions
= actions
;
3811 for (auto &it
: switches
)
3812 new_caserule
->switches
.push_back(it
->clone());
3813 return new_caserule
;
3816 RTLIL::SwitchRule::~SwitchRule()
3818 for (auto it
= cases
.begin(); it
!= cases
.end(); it
++)
3822 bool RTLIL::SwitchRule::empty() const
3824 return cases
.empty();
3827 RTLIL::SwitchRule
*RTLIL::SwitchRule::clone() const
3829 RTLIL::SwitchRule
*new_switchrule
= new RTLIL::SwitchRule
;
3830 new_switchrule
->signal
= signal
;
3831 new_switchrule
->attributes
= attributes
;
3832 for (auto &it
: cases
)
3833 new_switchrule
->cases
.push_back(it
->clone());
3834 return new_switchrule
;
3838 RTLIL::SyncRule
*RTLIL::SyncRule::clone() const
3840 RTLIL::SyncRule
*new_syncrule
= new RTLIL::SyncRule
;
3841 new_syncrule
->type
= type
;
3842 new_syncrule
->signal
= signal
;
3843 new_syncrule
->actions
= actions
;
3844 return new_syncrule
;
3847 RTLIL::Process::~Process()
3849 for (auto it
= syncs
.begin(); it
!= syncs
.end(); it
++)
3853 RTLIL::Process
*RTLIL::Process::clone() const
3855 RTLIL::Process
*new_proc
= new RTLIL::Process
;
3857 new_proc
->name
= name
;
3858 new_proc
->attributes
= attributes
;
3860 RTLIL::CaseRule
*rc_ptr
= root_case
.clone();
3861 new_proc
->root_case
= *rc_ptr
;
3862 rc_ptr
->switches
.clear();
3865 for (auto &it
: syncs
)
3866 new_proc
->syncs
.push_back(it
->clone());