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Merge pull request #941 from Wren6991/sim_lib_io_clke
[yosys.git] / kernel / rtlil.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 #include "kernel/yosys.h"
21 #include "kernel/macc.h"
22 #include "kernel/celltypes.h"
23 #include "frontends/verilog/verilog_frontend.h"
24 #include "backends/ilang/ilang_backend.h"
25
26 #include <string.h>
27 #include <algorithm>
28
29 YOSYS_NAMESPACE_BEGIN
30
31 RTLIL::IdString::destruct_guard_t RTLIL::IdString::destruct_guard;
32 std::vector<int> RTLIL::IdString::global_refcount_storage_;
33 std::vector<char*> RTLIL::IdString::global_id_storage_;
34 dict<char*, int, hash_cstr_ops> RTLIL::IdString::global_id_index_;
35 std::vector<int> RTLIL::IdString::global_free_idx_list_;
36 int RTLIL::IdString::last_created_idx_[8];
37 int RTLIL::IdString::last_created_idx_ptr_;
38
39 RTLIL::Const::Const()
40 {
41 flags = RTLIL::CONST_FLAG_NONE;
42 }
43
44 RTLIL::Const::Const(std::string str)
45 {
46 flags = RTLIL::CONST_FLAG_STRING;
47 for (int i = str.size()-1; i >= 0; i--) {
48 unsigned char ch = str[i];
49 for (int j = 0; j < 8; j++) {
50 bits.push_back((ch & 1) != 0 ? RTLIL::S1 : RTLIL::S0);
51 ch = ch >> 1;
52 }
53 }
54 }
55
56 RTLIL::Const::Const(int val, int width)
57 {
58 flags = RTLIL::CONST_FLAG_NONE;
59 for (int i = 0; i < width; i++) {
60 bits.push_back((val & 1) != 0 ? RTLIL::S1 : RTLIL::S0);
61 val = val >> 1;
62 }
63 }
64
65 RTLIL::Const::Const(RTLIL::State bit, int width)
66 {
67 flags = RTLIL::CONST_FLAG_NONE;
68 for (int i = 0; i < width; i++)
69 bits.push_back(bit);
70 }
71
72 RTLIL::Const::Const(const std::vector<bool> &bits)
73 {
74 flags = RTLIL::CONST_FLAG_NONE;
75 for (auto b : bits)
76 this->bits.push_back(b ? RTLIL::S1 : RTLIL::S0);
77 }
78
79 bool RTLIL::Const::operator <(const RTLIL::Const &other) const
80 {
81 if (bits.size() != other.bits.size())
82 return bits.size() < other.bits.size();
83 for (size_t i = 0; i < bits.size(); i++)
84 if (bits[i] != other.bits[i])
85 return bits[i] < other.bits[i];
86 return false;
87 }
88
89 bool RTLIL::Const::operator ==(const RTLIL::Const &other) const
90 {
91 return bits == other.bits;
92 }
93
94 bool RTLIL::Const::operator !=(const RTLIL::Const &other) const
95 {
96 return bits != other.bits;
97 }
98
99 bool RTLIL::Const::as_bool() const
100 {
101 for (size_t i = 0; i < bits.size(); i++)
102 if (bits[i] == RTLIL::S1)
103 return true;
104 return false;
105 }
106
107 int RTLIL::Const::as_int(bool is_signed) const
108 {
109 int32_t ret = 0;
110 for (size_t i = 0; i < bits.size() && i < 32; i++)
111 if (bits[i] == RTLIL::S1)
112 ret |= 1 << i;
113 if (is_signed && bits.back() == RTLIL::S1)
114 for (size_t i = bits.size(); i < 32; i++)
115 ret |= 1 << i;
116 return ret;
117 }
118
119 std::string RTLIL::Const::as_string() const
120 {
121 std::string ret;
122 for (size_t i = bits.size(); i > 0; i--)
123 switch (bits[i-1]) {
124 case S0: ret += "0"; break;
125 case S1: ret += "1"; break;
126 case Sx: ret += "x"; break;
127 case Sz: ret += "z"; break;
128 case Sa: ret += "-"; break;
129 case Sm: ret += "m"; break;
130 }
131 return ret;
132 }
133
134 RTLIL::Const RTLIL::Const::from_string(std::string str)
135 {
136 Const c;
137 for (auto it = str.rbegin(); it != str.rend(); it++)
138 switch (*it) {
139 case '0': c.bits.push_back(State::S0); break;
140 case '1': c.bits.push_back(State::S1); break;
141 case 'x': c.bits.push_back(State::Sx); break;
142 case 'z': c.bits.push_back(State::Sz); break;
143 case 'm': c.bits.push_back(State::Sm); break;
144 default: c.bits.push_back(State::Sa);
145 }
146 return c;
147 }
148
149 std::string RTLIL::Const::decode_string() const
150 {
151 std::string string;
152 std::vector<char> string_chars;
153 for (int i = 0; i < int (bits.size()); i += 8) {
154 char ch = 0;
155 for (int j = 0; j < 8 && i + j < int (bits.size()); j++)
156 if (bits[i + j] == RTLIL::State::S1)
157 ch |= 1 << j;
158 if (ch != 0)
159 string_chars.push_back(ch);
160 }
161 for (int i = int (string_chars.size()) - 1; i >= 0; i--)
162 string += string_chars[i];
163 return string;
164 }
165
166 bool RTLIL::Const::is_fully_zero() const
167 {
168 cover("kernel.rtlil.const.is_fully_zero");
169
170 for (auto bit : bits)
171 if (bit != RTLIL::State::S0)
172 return false;
173
174 return true;
175 }
176
177 bool RTLIL::Const::is_fully_ones() const
178 {
179 cover("kernel.rtlil.const.is_fully_ones");
180
181 for (auto bit : bits)
182 if (bit != RTLIL::State::S1)
183 return false;
184
185 return true;
186 }
187
188 bool RTLIL::Const::is_fully_def() const
189 {
190 cover("kernel.rtlil.const.is_fully_def");
191
192 for (auto bit : bits)
193 if (bit != RTLIL::State::S0 && bit != RTLIL::State::S1)
194 return false;
195
196 return true;
197 }
198
199 bool RTLIL::Const::is_fully_undef() const
200 {
201 cover("kernel.rtlil.const.is_fully_undef");
202
203 for (auto bit : bits)
204 if (bit != RTLIL::State::Sx && bit != RTLIL::State::Sz)
205 return false;
206
207 return true;
208 }
209
210 void RTLIL::AttrObject::set_bool_attribute(RTLIL::IdString id, bool value)
211 {
212 if (value)
213 attributes[id] = RTLIL::Const(1);
214 else if (attributes.count(id))
215 attributes.erase(id);
216 }
217
218 bool RTLIL::AttrObject::get_bool_attribute(RTLIL::IdString id) const
219 {
220 if (attributes.count(id) == 0)
221 return false;
222 return attributes.at(id).as_bool();
223 }
224
225 void RTLIL::AttrObject::set_strpool_attribute(RTLIL::IdString id, const pool<string> &data)
226 {
227 string attrval;
228 for (auto &s : data) {
229 if (!attrval.empty())
230 attrval += "|";
231 attrval += s;
232 }
233 attributes[id] = RTLIL::Const(attrval);
234 }
235
236 void RTLIL::AttrObject::add_strpool_attribute(RTLIL::IdString id, const pool<string> &data)
237 {
238 pool<string> union_data = get_strpool_attribute(id);
239 union_data.insert(data.begin(), data.end());
240 if (!union_data.empty())
241 set_strpool_attribute(id, union_data);
242 }
243
244 pool<string> RTLIL::AttrObject::get_strpool_attribute(RTLIL::IdString id) const
245 {
246 pool<string> data;
247 if (attributes.count(id) != 0)
248 for (auto s : split_tokens(attributes.at(id).decode_string(), "|"))
249 data.insert(s);
250 return data;
251 }
252
253 void RTLIL::AttrObject::set_src_attribute(const std::string &src)
254 {
255 if (src.empty())
256 attributes.erase("\\src");
257 else
258 attributes["\\src"] = src;
259 }
260
261 std::string RTLIL::AttrObject::get_src_attribute() const
262 {
263 std::string src;
264 if (attributes.count("\\src"))
265 src = attributes.at("\\src").decode_string();
266 return src;
267 }
268
269 bool RTLIL::Selection::selected_module(RTLIL::IdString mod_name) const
270 {
271 if (full_selection)
272 return true;
273 if (selected_modules.count(mod_name) > 0)
274 return true;
275 if (selected_members.count(mod_name) > 0)
276 return true;
277 return false;
278 }
279
280 bool RTLIL::Selection::selected_whole_module(RTLIL::IdString mod_name) const
281 {
282 if (full_selection)
283 return true;
284 if (selected_modules.count(mod_name) > 0)
285 return true;
286 return false;
287 }
288
289 bool RTLIL::Selection::selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const
290 {
291 if (full_selection)
292 return true;
293 if (selected_modules.count(mod_name) > 0)
294 return true;
295 if (selected_members.count(mod_name) > 0)
296 if (selected_members.at(mod_name).count(memb_name) > 0)
297 return true;
298 return false;
299 }
300
301 void RTLIL::Selection::optimize(RTLIL::Design *design)
302 {
303 if (full_selection) {
304 selected_modules.clear();
305 selected_members.clear();
306 return;
307 }
308
309 std::vector<RTLIL::IdString> del_list, add_list;
310
311 del_list.clear();
312 for (auto mod_name : selected_modules) {
313 if (design->modules_.count(mod_name) == 0)
314 del_list.push_back(mod_name);
315 selected_members.erase(mod_name);
316 }
317 for (auto mod_name : del_list)
318 selected_modules.erase(mod_name);
319
320 del_list.clear();
321 for (auto &it : selected_members)
322 if (design->modules_.count(it.first) == 0)
323 del_list.push_back(it.first);
324 for (auto mod_name : del_list)
325 selected_members.erase(mod_name);
326
327 for (auto &it : selected_members) {
328 del_list.clear();
329 for (auto memb_name : it.second)
330 if (design->modules_[it.first]->count_id(memb_name) == 0)
331 del_list.push_back(memb_name);
332 for (auto memb_name : del_list)
333 it.second.erase(memb_name);
334 }
335
336 del_list.clear();
337 add_list.clear();
338 for (auto &it : selected_members)
339 if (it.second.size() == 0)
340 del_list.push_back(it.first);
341 else if (it.second.size() == design->modules_[it.first]->wires_.size() + design->modules_[it.first]->memories.size() +
342 design->modules_[it.first]->cells_.size() + design->modules_[it.first]->processes.size())
343 add_list.push_back(it.first);
344 for (auto mod_name : del_list)
345 selected_members.erase(mod_name);
346 for (auto mod_name : add_list) {
347 selected_members.erase(mod_name);
348 selected_modules.insert(mod_name);
349 }
350
351 if (selected_modules.size() == design->modules_.size()) {
352 full_selection = true;
353 selected_modules.clear();
354 selected_members.clear();
355 }
356 }
357
358 RTLIL::Design::Design()
359 {
360 static unsigned int hashidx_count = 123456789;
361 hashidx_count = mkhash_xorshift(hashidx_count);
362 hashidx_ = hashidx_count;
363
364 refcount_modules_ = 0;
365 selection_stack.push_back(RTLIL::Selection());
366 }
367
368 RTLIL::Design::~Design()
369 {
370 for (auto it = modules_.begin(); it != modules_.end(); ++it)
371 delete it->second;
372 for (auto n : verilog_packages)
373 delete n;
374 for (auto n : verilog_globals)
375 delete n;
376 }
377
378 RTLIL::ObjRange<RTLIL::Module*> RTLIL::Design::modules()
379 {
380 return RTLIL::ObjRange<RTLIL::Module*>(&modules_, &refcount_modules_);
381 }
382
383 RTLIL::Module *RTLIL::Design::module(RTLIL::IdString name)
384 {
385 return modules_.count(name) ? modules_.at(name) : NULL;
386 }
387
388 RTLIL::Module *RTLIL::Design::top_module()
389 {
390 RTLIL::Module *module = nullptr;
391 int module_count = 0;
392
393 for (auto mod : selected_modules()) {
394 if (mod->get_bool_attribute("\\top"))
395 return mod;
396 module_count++;
397 module = mod;
398 }
399
400 return module_count == 1 ? module : nullptr;
401 }
402
403 void RTLIL::Design::add(RTLIL::Module *module)
404 {
405 log_assert(modules_.count(module->name) == 0);
406 log_assert(refcount_modules_ == 0);
407 modules_[module->name] = module;
408 module->design = this;
409
410 for (auto mon : monitors)
411 mon->notify_module_add(module);
412
413 if (yosys_xtrace) {
414 log("#X# New Module: %s\n", log_id(module));
415 log_backtrace("-X- ", yosys_xtrace-1);
416 }
417 }
418
419 RTLIL::Module *RTLIL::Design::addModule(RTLIL::IdString name)
420 {
421 log_assert(modules_.count(name) == 0);
422 log_assert(refcount_modules_ == 0);
423
424 RTLIL::Module *module = new RTLIL::Module;
425 modules_[name] = module;
426 module->design = this;
427 module->name = name;
428
429 for (auto mon : monitors)
430 mon->notify_module_add(module);
431
432 if (yosys_xtrace) {
433 log("#X# New Module: %s\n", log_id(module));
434 log_backtrace("-X- ", yosys_xtrace-1);
435 }
436
437 return module;
438 }
439
440 void RTLIL::Design::scratchpad_unset(std::string varname)
441 {
442 scratchpad.erase(varname);
443 }
444
445 void RTLIL::Design::scratchpad_set_int(std::string varname, int value)
446 {
447 scratchpad[varname] = stringf("%d", value);
448 }
449
450 void RTLIL::Design::scratchpad_set_bool(std::string varname, bool value)
451 {
452 scratchpad[varname] = value ? "true" : "false";
453 }
454
455 void RTLIL::Design::scratchpad_set_string(std::string varname, std::string value)
456 {
457 scratchpad[varname] = value;
458 }
459
460 int RTLIL::Design::scratchpad_get_int(std::string varname, int default_value) const
461 {
462 if (scratchpad.count(varname) == 0)
463 return default_value;
464
465 std::string str = scratchpad.at(varname);
466
467 if (str == "0" || str == "false")
468 return 0;
469
470 if (str == "1" || str == "true")
471 return 1;
472
473 char *endptr = nullptr;
474 long int parsed_value = strtol(str.c_str(), &endptr, 10);
475 return *endptr ? default_value : parsed_value;
476 }
477
478 bool RTLIL::Design::scratchpad_get_bool(std::string varname, bool default_value) const
479 {
480 if (scratchpad.count(varname) == 0)
481 return default_value;
482
483 std::string str = scratchpad.at(varname);
484
485 if (str == "0" || str == "false")
486 return false;
487
488 if (str == "1" || str == "true")
489 return true;
490
491 return default_value;
492 }
493
494 std::string RTLIL::Design::scratchpad_get_string(std::string varname, std::string default_value) const
495 {
496 if (scratchpad.count(varname) == 0)
497 return default_value;
498 return scratchpad.at(varname);
499 }
500
501 void RTLIL::Design::remove(RTLIL::Module *module)
502 {
503 for (auto mon : monitors)
504 mon->notify_module_del(module);
505
506 if (yosys_xtrace) {
507 log("#X# Remove Module: %s\n", log_id(module));
508 log_backtrace("-X- ", yosys_xtrace-1);
509 }
510
511 log_assert(modules_.at(module->name) == module);
512 modules_.erase(module->name);
513 delete module;
514 }
515
516 void RTLIL::Design::rename(RTLIL::Module *module, RTLIL::IdString new_name)
517 {
518 modules_.erase(module->name);
519 module->name = new_name;
520 add(module);
521 }
522
523 void RTLIL::Design::sort()
524 {
525 scratchpad.sort();
526 modules_.sort(sort_by_id_str());
527 for (auto &it : modules_)
528 it.second->sort();
529 }
530
531 void RTLIL::Design::check()
532 {
533 #ifndef NDEBUG
534 for (auto &it : modules_) {
535 log_assert(this == it.second->design);
536 log_assert(it.first == it.second->name);
537 log_assert(!it.first.empty());
538 it.second->check();
539 }
540 #endif
541 }
542
543 void RTLIL::Design::optimize()
544 {
545 for (auto &it : modules_)
546 it.second->optimize();
547 for (auto &it : selection_stack)
548 it.optimize(this);
549 for (auto &it : selection_vars)
550 it.second.optimize(this);
551 }
552
553 bool RTLIL::Design::selected_module(RTLIL::IdString mod_name) const
554 {
555 if (!selected_active_module.empty() && mod_name != selected_active_module)
556 return false;
557 if (selection_stack.size() == 0)
558 return true;
559 return selection_stack.back().selected_module(mod_name);
560 }
561
562 bool RTLIL::Design::selected_whole_module(RTLIL::IdString mod_name) const
563 {
564 if (!selected_active_module.empty() && mod_name != selected_active_module)
565 return false;
566 if (selection_stack.size() == 0)
567 return true;
568 return selection_stack.back().selected_whole_module(mod_name);
569 }
570
571 bool RTLIL::Design::selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const
572 {
573 if (!selected_active_module.empty() && mod_name != selected_active_module)
574 return false;
575 if (selection_stack.size() == 0)
576 return true;
577 return selection_stack.back().selected_member(mod_name, memb_name);
578 }
579
580 bool RTLIL::Design::selected_module(RTLIL::Module *mod) const
581 {
582 return selected_module(mod->name);
583 }
584
585 bool RTLIL::Design::selected_whole_module(RTLIL::Module *mod) const
586 {
587 return selected_whole_module(mod->name);
588 }
589
590 std::vector<RTLIL::Module*> RTLIL::Design::selected_modules() const
591 {
592 std::vector<RTLIL::Module*> result;
593 result.reserve(modules_.size());
594 for (auto &it : modules_)
595 if (selected_module(it.first) && !it.second->get_blackbox_attribute())
596 result.push_back(it.second);
597 return result;
598 }
599
600 std::vector<RTLIL::Module*> RTLIL::Design::selected_whole_modules() const
601 {
602 std::vector<RTLIL::Module*> result;
603 result.reserve(modules_.size());
604 for (auto &it : modules_)
605 if (selected_whole_module(it.first) && !it.second->get_blackbox_attribute())
606 result.push_back(it.second);
607 return result;
608 }
609
610 std::vector<RTLIL::Module*> RTLIL::Design::selected_whole_modules_warn() const
611 {
612 std::vector<RTLIL::Module*> result;
613 result.reserve(modules_.size());
614 for (auto &it : modules_)
615 if (it.second->get_blackbox_attribute())
616 continue;
617 else if (selected_whole_module(it.first))
618 result.push_back(it.second);
619 else if (selected_module(it.first))
620 log_warning("Ignoring partially selected module %s.\n", log_id(it.first));
621 return result;
622 }
623
624 RTLIL::Module::Module()
625 {
626 static unsigned int hashidx_count = 123456789;
627 hashidx_count = mkhash_xorshift(hashidx_count);
628 hashidx_ = hashidx_count;
629
630 design = nullptr;
631 refcount_wires_ = 0;
632 refcount_cells_ = 0;
633 }
634
635 RTLIL::Module::~Module()
636 {
637 for (auto it = wires_.begin(); it != wires_.end(); ++it)
638 delete it->second;
639 for (auto it = memories.begin(); it != memories.end(); ++it)
640 delete it->second;
641 for (auto it = cells_.begin(); it != cells_.end(); ++it)
642 delete it->second;
643 for (auto it = processes.begin(); it != processes.end(); ++it)
644 delete it->second;
645 }
646
647 void RTLIL::Module::makeblackbox()
648 {
649 pool<RTLIL::Wire*> delwires;
650
651 for (auto it = wires_.begin(); it != wires_.end(); ++it)
652 if (!it->second->port_input && !it->second->port_output)
653 delwires.insert(it->second);
654
655 for (auto it = memories.begin(); it != memories.end(); ++it)
656 delete it->second;
657 memories.clear();
658
659 for (auto it = cells_.begin(); it != cells_.end(); ++it)
660 delete it->second;
661 cells_.clear();
662
663 for (auto it = processes.begin(); it != processes.end(); ++it)
664 delete it->second;
665 processes.clear();
666
667 remove(delwires);
668 set_bool_attribute("\\blackbox");
669 }
670
671 void RTLIL::Module::reprocess_module(RTLIL::Design *, dict<RTLIL::IdString, RTLIL::Module *>)
672 {
673 log_error("Cannot reprocess_module module `%s' !\n", id2cstr(name));
674 }
675
676 RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, dict<RTLIL::IdString, RTLIL::Const>, bool mayfail)
677 {
678 if (mayfail)
679 return RTLIL::IdString();
680 log_error("Module `%s' is used with parameters but is not parametric!\n", id2cstr(name));
681 }
682
683
684 RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, dict<RTLIL::IdString, RTLIL::Const>, dict<RTLIL::IdString, RTLIL::Module*>, dict<RTLIL::IdString, RTLIL::IdString>, bool mayfail)
685 {
686 if (mayfail)
687 return RTLIL::IdString();
688 log_error("Module `%s' is used with parameters but is not parametric!\n", id2cstr(name));
689 }
690
691 size_t RTLIL::Module::count_id(RTLIL::IdString id)
692 {
693 return wires_.count(id) + memories.count(id) + cells_.count(id) + processes.count(id);
694 }
695
696 #ifndef NDEBUG
697 namespace {
698 struct InternalCellChecker
699 {
700 RTLIL::Module *module;
701 RTLIL::Cell *cell;
702 pool<RTLIL::IdString> expected_params, expected_ports;
703
704 InternalCellChecker(RTLIL::Module *module, RTLIL::Cell *cell) : module(module), cell(cell) { }
705
706 void error(int linenr)
707 {
708 std::stringstream buf;
709 ILANG_BACKEND::dump_cell(buf, " ", cell);
710
711 log_error("Found error in internal cell %s%s%s (%s) at %s:%d:\n%s",
712 module ? module->name.c_str() : "", module ? "." : "",
713 cell->name.c_str(), cell->type.c_str(), __FILE__, linenr, buf.str().c_str());
714 }
715
716 int param(const char *name)
717 {
718 if (cell->parameters.count(name) == 0)
719 error(__LINE__);
720 expected_params.insert(name);
721 return cell->parameters.at(name).as_int();
722 }
723
724 int param_bool(const char *name)
725 {
726 int v = param(name);
727 if (cell->parameters.at(name).bits.size() > 32)
728 error(__LINE__);
729 if (v != 0 && v != 1)
730 error(__LINE__);
731 return v;
732 }
733
734 void param_bits(const char *name, int width)
735 {
736 param(name);
737 if (int(cell->parameters.at(name).bits.size()) != width)
738 error(__LINE__);
739 }
740
741 void port(const char *name, int width)
742 {
743 if (!cell->hasPort(name))
744 error(__LINE__);
745 if (cell->getPort(name).size() != width)
746 error(__LINE__);
747 expected_ports.insert(name);
748 }
749
750 void check_expected(bool check_matched_sign = true)
751 {
752 for (auto &para : cell->parameters)
753 if (expected_params.count(para.first) == 0)
754 error(__LINE__);
755 for (auto &conn : cell->connections())
756 if (expected_ports.count(conn.first) == 0)
757 error(__LINE__);
758
759 if (expected_params.count("\\A_SIGNED") != 0 && expected_params.count("\\B_SIGNED") && check_matched_sign) {
760 bool a_is_signed = param("\\A_SIGNED") != 0;
761 bool b_is_signed = param("\\B_SIGNED") != 0;
762 if (a_is_signed != b_is_signed)
763 error(__LINE__);
764 }
765 }
766
767 void check_gate(const char *ports)
768 {
769 if (cell->parameters.size() != 0)
770 error(__LINE__);
771
772 for (const char *p = ports; *p; p++) {
773 char portname[3] = { '\\', *p, 0 };
774 if (!cell->hasPort(portname))
775 error(__LINE__);
776 if (cell->getPort(portname).size() != 1)
777 error(__LINE__);
778 }
779
780 for (auto &conn : cell->connections()) {
781 if (conn.first.size() != 2 || conn.first[0] != '\\')
782 error(__LINE__);
783 if (strchr(ports, conn.first[1]) == NULL)
784 error(__LINE__);
785 }
786 }
787
788 void check()
789 {
790 if (cell->type.substr(0, 1) != "$" || cell->type.substr(0, 3) == "$__" || cell->type.substr(0, 8) == "$paramod" || cell->type.substr(0,10) == "$fmcombine" ||
791 cell->type.substr(0, 9) == "$verific$" || cell->type.substr(0, 7) == "$array:" || cell->type.substr(0, 8) == "$extern:")
792 return;
793
794 if (cell->type.in("$not", "$pos", "$neg")) {
795 param_bool("\\A_SIGNED");
796 port("\\A", param("\\A_WIDTH"));
797 port("\\Y", param("\\Y_WIDTH"));
798 check_expected();
799 return;
800 }
801
802 if (cell->type.in("$and", "$or", "$xor", "$xnor")) {
803 param_bool("\\A_SIGNED");
804 param_bool("\\B_SIGNED");
805 port("\\A", param("\\A_WIDTH"));
806 port("\\B", param("\\B_WIDTH"));
807 port("\\Y", param("\\Y_WIDTH"));
808 check_expected();
809 return;
810 }
811
812 if (cell->type.in("$reduce_and", "$reduce_or", "$reduce_xor", "$reduce_xnor", "$reduce_bool")) {
813 param_bool("\\A_SIGNED");
814 port("\\A", param("\\A_WIDTH"));
815 port("\\Y", param("\\Y_WIDTH"));
816 check_expected();
817 return;
818 }
819
820 if (cell->type.in("$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx")) {
821 param_bool("\\A_SIGNED");
822 param_bool("\\B_SIGNED");
823 port("\\A", param("\\A_WIDTH"));
824 port("\\B", param("\\B_WIDTH"));
825 port("\\Y", param("\\Y_WIDTH"));
826 check_expected(false);
827 return;
828 }
829
830 if (cell->type.in("$lt", "$le", "$eq", "$ne", "$eqx", "$nex", "$ge", "$gt")) {
831 param_bool("\\A_SIGNED");
832 param_bool("\\B_SIGNED");
833 port("\\A", param("\\A_WIDTH"));
834 port("\\B", param("\\B_WIDTH"));
835 port("\\Y", param("\\Y_WIDTH"));
836 check_expected();
837 return;
838 }
839
840 if (cell->type.in("$add", "$sub", "$mul", "$div", "$mod", "$pow")) {
841 param_bool("\\A_SIGNED");
842 param_bool("\\B_SIGNED");
843 port("\\A", param("\\A_WIDTH"));
844 port("\\B", param("\\B_WIDTH"));
845 port("\\Y", param("\\Y_WIDTH"));
846 check_expected(cell->type != "$pow");
847 return;
848 }
849
850 if (cell->type == "$fa") {
851 port("\\A", param("\\WIDTH"));
852 port("\\B", param("\\WIDTH"));
853 port("\\C", param("\\WIDTH"));
854 port("\\X", param("\\WIDTH"));
855 port("\\Y", param("\\WIDTH"));
856 check_expected();
857 return;
858 }
859
860 if (cell->type == "$lcu") {
861 port("\\P", param("\\WIDTH"));
862 port("\\G", param("\\WIDTH"));
863 port("\\CI", 1);
864 port("\\CO", param("\\WIDTH"));
865 check_expected();
866 return;
867 }
868
869 if (cell->type == "$alu") {
870 param_bool("\\A_SIGNED");
871 param_bool("\\B_SIGNED");
872 port("\\A", param("\\A_WIDTH"));
873 port("\\B", param("\\B_WIDTH"));
874 port("\\CI", 1);
875 port("\\BI", 1);
876 port("\\X", param("\\Y_WIDTH"));
877 port("\\Y", param("\\Y_WIDTH"));
878 port("\\CO", param("\\Y_WIDTH"));
879 check_expected();
880 return;
881 }
882
883 if (cell->type == "$macc") {
884 param("\\CONFIG");
885 param("\\CONFIG_WIDTH");
886 port("\\A", param("\\A_WIDTH"));
887 port("\\B", param("\\B_WIDTH"));
888 port("\\Y", param("\\Y_WIDTH"));
889 check_expected();
890 Macc().from_cell(cell);
891 return;
892 }
893
894 if (cell->type == "$logic_not") {
895 param_bool("\\A_SIGNED");
896 port("\\A", param("\\A_WIDTH"));
897 port("\\Y", param("\\Y_WIDTH"));
898 check_expected();
899 return;
900 }
901
902 if (cell->type == "$logic_and" || cell->type == "$logic_or") {
903 param_bool("\\A_SIGNED");
904 param_bool("\\B_SIGNED");
905 port("\\A", param("\\A_WIDTH"));
906 port("\\B", param("\\B_WIDTH"));
907 port("\\Y", param("\\Y_WIDTH"));
908 check_expected(false);
909 return;
910 }
911
912 if (cell->type == "$slice") {
913 param("\\OFFSET");
914 port("\\A", param("\\A_WIDTH"));
915 port("\\Y", param("\\Y_WIDTH"));
916 if (param("\\OFFSET") + param("\\Y_WIDTH") > param("\\A_WIDTH"))
917 error(__LINE__);
918 check_expected();
919 return;
920 }
921
922 if (cell->type == "$concat") {
923 port("\\A", param("\\A_WIDTH"));
924 port("\\B", param("\\B_WIDTH"));
925 port("\\Y", param("\\A_WIDTH") + param("\\B_WIDTH"));
926 check_expected();
927 return;
928 }
929
930 if (cell->type == "$mux") {
931 port("\\A", param("\\WIDTH"));
932 port("\\B", param("\\WIDTH"));
933 port("\\S", 1);
934 port("\\Y", param("\\WIDTH"));
935 check_expected();
936 return;
937 }
938
939 if (cell->type == "$pmux") {
940 port("\\A", param("\\WIDTH"));
941 port("\\B", param("\\WIDTH") * param("\\S_WIDTH"));
942 port("\\S", param("\\S_WIDTH"));
943 port("\\Y", param("\\WIDTH"));
944 check_expected();
945 return;
946 }
947
948 if (cell->type == "$lut") {
949 param("\\LUT");
950 port("\\A", param("\\WIDTH"));
951 port("\\Y", 1);
952 check_expected();
953 return;
954 }
955
956 if (cell->type == "$sop") {
957 param("\\DEPTH");
958 param("\\TABLE");
959 port("\\A", param("\\WIDTH"));
960 port("\\Y", 1);
961 check_expected();
962 return;
963 }
964
965 if (cell->type == "$sr") {
966 param_bool("\\SET_POLARITY");
967 param_bool("\\CLR_POLARITY");
968 port("\\SET", param("\\WIDTH"));
969 port("\\CLR", param("\\WIDTH"));
970 port("\\Q", param("\\WIDTH"));
971 check_expected();
972 return;
973 }
974
975 if (cell->type == "$ff") {
976 port("\\D", param("\\WIDTH"));
977 port("\\Q", param("\\WIDTH"));
978 check_expected();
979 return;
980 }
981
982 if (cell->type == "$dff") {
983 param_bool("\\CLK_POLARITY");
984 port("\\CLK", 1);
985 port("\\D", param("\\WIDTH"));
986 port("\\Q", param("\\WIDTH"));
987 check_expected();
988 return;
989 }
990
991 if (cell->type == "$dffe") {
992 param_bool("\\CLK_POLARITY");
993 param_bool("\\EN_POLARITY");
994 port("\\CLK", 1);
995 port("\\EN", 1);
996 port("\\D", param("\\WIDTH"));
997 port("\\Q", param("\\WIDTH"));
998 check_expected();
999 return;
1000 }
1001
1002 if (cell->type == "$dffsr") {
1003 param_bool("\\CLK_POLARITY");
1004 param_bool("\\SET_POLARITY");
1005 param_bool("\\CLR_POLARITY");
1006 port("\\CLK", 1);
1007 port("\\SET", param("\\WIDTH"));
1008 port("\\CLR", param("\\WIDTH"));
1009 port("\\D", param("\\WIDTH"));
1010 port("\\Q", param("\\WIDTH"));
1011 check_expected();
1012 return;
1013 }
1014
1015 if (cell->type == "$adff") {
1016 param_bool("\\CLK_POLARITY");
1017 param_bool("\\ARST_POLARITY");
1018 param_bits("\\ARST_VALUE", param("\\WIDTH"));
1019 port("\\CLK", 1);
1020 port("\\ARST", 1);
1021 port("\\D", param("\\WIDTH"));
1022 port("\\Q", param("\\WIDTH"));
1023 check_expected();
1024 return;
1025 }
1026
1027 if (cell->type == "$dlatch") {
1028 param_bool("\\EN_POLARITY");
1029 port("\\EN", 1);
1030 port("\\D", param("\\WIDTH"));
1031 port("\\Q", param("\\WIDTH"));
1032 check_expected();
1033 return;
1034 }
1035
1036 if (cell->type == "$dlatchsr") {
1037 param_bool("\\EN_POLARITY");
1038 param_bool("\\SET_POLARITY");
1039 param_bool("\\CLR_POLARITY");
1040 port("\\EN", 1);
1041 port("\\SET", param("\\WIDTH"));
1042 port("\\CLR", param("\\WIDTH"));
1043 port("\\D", param("\\WIDTH"));
1044 port("\\Q", param("\\WIDTH"));
1045 check_expected();
1046 return;
1047 }
1048
1049 if (cell->type == "$fsm") {
1050 param("\\NAME");
1051 param_bool("\\CLK_POLARITY");
1052 param_bool("\\ARST_POLARITY");
1053 param("\\STATE_BITS");
1054 param("\\STATE_NUM");
1055 param("\\STATE_NUM_LOG2");
1056 param("\\STATE_RST");
1057 param_bits("\\STATE_TABLE", param("\\STATE_BITS") * param("\\STATE_NUM"));
1058 param("\\TRANS_NUM");
1059 param_bits("\\TRANS_TABLE", param("\\TRANS_NUM") * (2*param("\\STATE_NUM_LOG2") + param("\\CTRL_IN_WIDTH") + param("\\CTRL_OUT_WIDTH")));
1060 port("\\CLK", 1);
1061 port("\\ARST", 1);
1062 port("\\CTRL_IN", param("\\CTRL_IN_WIDTH"));
1063 port("\\CTRL_OUT", param("\\CTRL_OUT_WIDTH"));
1064 check_expected();
1065 return;
1066 }
1067
1068 if (cell->type == "$memrd") {
1069 param("\\MEMID");
1070 param_bool("\\CLK_ENABLE");
1071 param_bool("\\CLK_POLARITY");
1072 param_bool("\\TRANSPARENT");
1073 port("\\CLK", 1);
1074 port("\\EN", 1);
1075 port("\\ADDR", param("\\ABITS"));
1076 port("\\DATA", param("\\WIDTH"));
1077 check_expected();
1078 return;
1079 }
1080
1081 if (cell->type == "$memwr") {
1082 param("\\MEMID");
1083 param_bool("\\CLK_ENABLE");
1084 param_bool("\\CLK_POLARITY");
1085 param("\\PRIORITY");
1086 port("\\CLK", 1);
1087 port("\\EN", param("\\WIDTH"));
1088 port("\\ADDR", param("\\ABITS"));
1089 port("\\DATA", param("\\WIDTH"));
1090 check_expected();
1091 return;
1092 }
1093
1094 if (cell->type == "$meminit") {
1095 param("\\MEMID");
1096 param("\\PRIORITY");
1097 port("\\ADDR", param("\\ABITS"));
1098 port("\\DATA", param("\\WIDTH") * param("\\WORDS"));
1099 check_expected();
1100 return;
1101 }
1102
1103 if (cell->type == "$mem") {
1104 param("\\MEMID");
1105 param("\\SIZE");
1106 param("\\OFFSET");
1107 param("\\INIT");
1108 param_bits("\\RD_CLK_ENABLE", max(1, param("\\RD_PORTS")));
1109 param_bits("\\RD_CLK_POLARITY", max(1, param("\\RD_PORTS")));
1110 param_bits("\\RD_TRANSPARENT", max(1, param("\\RD_PORTS")));
1111 param_bits("\\WR_CLK_ENABLE", max(1, param("\\WR_PORTS")));
1112 param_bits("\\WR_CLK_POLARITY", max(1, param("\\WR_PORTS")));
1113 port("\\RD_CLK", param("\\RD_PORTS"));
1114 port("\\RD_EN", param("\\RD_PORTS"));
1115 port("\\RD_ADDR", param("\\RD_PORTS") * param("\\ABITS"));
1116 port("\\RD_DATA", param("\\RD_PORTS") * param("\\WIDTH"));
1117 port("\\WR_CLK", param("\\WR_PORTS"));
1118 port("\\WR_EN", param("\\WR_PORTS") * param("\\WIDTH"));
1119 port("\\WR_ADDR", param("\\WR_PORTS") * param("\\ABITS"));
1120 port("\\WR_DATA", param("\\WR_PORTS") * param("\\WIDTH"));
1121 check_expected();
1122 return;
1123 }
1124
1125 if (cell->type == "$tribuf") {
1126 port("\\A", param("\\WIDTH"));
1127 port("\\Y", param("\\WIDTH"));
1128 port("\\EN", 1);
1129 check_expected();
1130 return;
1131 }
1132
1133 if (cell->type.in("$assert", "$assume", "$live", "$fair", "$cover")) {
1134 port("\\A", 1);
1135 port("\\EN", 1);
1136 check_expected();
1137 return;
1138 }
1139
1140 if (cell->type == "$initstate") {
1141 port("\\Y", 1);
1142 check_expected();
1143 return;
1144 }
1145
1146 if (cell->type.in("$anyconst", "$anyseq", "$allconst", "$allseq")) {
1147 port("\\Y", param("\\WIDTH"));
1148 check_expected();
1149 return;
1150 }
1151
1152 if (cell->type == "$equiv") {
1153 port("\\A", 1);
1154 port("\\B", 1);
1155 port("\\Y", 1);
1156 check_expected();
1157 return;
1158 }
1159
1160 if (cell->type == "$_BUF_") { check_gate("AY"); return; }
1161 if (cell->type == "$_NOT_") { check_gate("AY"); return; }
1162 if (cell->type == "$_AND_") { check_gate("ABY"); return; }
1163 if (cell->type == "$_NAND_") { check_gate("ABY"); return; }
1164 if (cell->type == "$_OR_") { check_gate("ABY"); return; }
1165 if (cell->type == "$_NOR_") { check_gate("ABY"); return; }
1166 if (cell->type == "$_XOR_") { check_gate("ABY"); return; }
1167 if (cell->type == "$_XNOR_") { check_gate("ABY"); return; }
1168 if (cell->type == "$_ANDNOT_") { check_gate("ABY"); return; }
1169 if (cell->type == "$_ORNOT_") { check_gate("ABY"); return; }
1170 if (cell->type == "$_MUX_") { check_gate("ABSY"); return; }
1171 if (cell->type == "$_AOI3_") { check_gate("ABCY"); return; }
1172 if (cell->type == "$_OAI3_") { check_gate("ABCY"); return; }
1173 if (cell->type == "$_AOI4_") { check_gate("ABCDY"); return; }
1174 if (cell->type == "$_OAI4_") { check_gate("ABCDY"); return; }
1175
1176 if (cell->type == "$_TBUF_") { check_gate("AYE"); return; }
1177
1178 if (cell->type == "$_MUX4_") { check_gate("ABCDSTY"); return; }
1179 if (cell->type == "$_MUX8_") { check_gate("ABCDEFGHSTUY"); return; }
1180 if (cell->type == "$_MUX16_") { check_gate("ABCDEFGHIJKLMNOPSTUVY"); return; }
1181
1182 if (cell->type == "$_SR_NN_") { check_gate("SRQ"); return; }
1183 if (cell->type == "$_SR_NP_") { check_gate("SRQ"); return; }
1184 if (cell->type == "$_SR_PN_") { check_gate("SRQ"); return; }
1185 if (cell->type == "$_SR_PP_") { check_gate("SRQ"); return; }
1186
1187 if (cell->type == "$_FF_") { check_gate("DQ"); return; }
1188 if (cell->type == "$_DFF_N_") { check_gate("DQC"); return; }
1189 if (cell->type == "$_DFF_P_") { check_gate("DQC"); return; }
1190
1191 if (cell->type == "$_DFFE_NN_") { check_gate("DQCE"); return; }
1192 if (cell->type == "$_DFFE_NP_") { check_gate("DQCE"); return; }
1193 if (cell->type == "$_DFFE_PN_") { check_gate("DQCE"); return; }
1194 if (cell->type == "$_DFFE_PP_") { check_gate("DQCE"); return; }
1195
1196 if (cell->type == "$_DFF_NN0_") { check_gate("DQCR"); return; }
1197 if (cell->type == "$_DFF_NN1_") { check_gate("DQCR"); return; }
1198 if (cell->type == "$_DFF_NP0_") { check_gate("DQCR"); return; }
1199 if (cell->type == "$_DFF_NP1_") { check_gate("DQCR"); return; }
1200 if (cell->type == "$_DFF_PN0_") { check_gate("DQCR"); return; }
1201 if (cell->type == "$_DFF_PN1_") { check_gate("DQCR"); return; }
1202 if (cell->type == "$_DFF_PP0_") { check_gate("DQCR"); return; }
1203 if (cell->type == "$_DFF_PP1_") { check_gate("DQCR"); return; }
1204
1205 if (cell->type == "$_DFFSR_NNN_") { check_gate("CSRDQ"); return; }
1206 if (cell->type == "$_DFFSR_NNP_") { check_gate("CSRDQ"); return; }
1207 if (cell->type == "$_DFFSR_NPN_") { check_gate("CSRDQ"); return; }
1208 if (cell->type == "$_DFFSR_NPP_") { check_gate("CSRDQ"); return; }
1209 if (cell->type == "$_DFFSR_PNN_") { check_gate("CSRDQ"); return; }
1210 if (cell->type == "$_DFFSR_PNP_") { check_gate("CSRDQ"); return; }
1211 if (cell->type == "$_DFFSR_PPN_") { check_gate("CSRDQ"); return; }
1212 if (cell->type == "$_DFFSR_PPP_") { check_gate("CSRDQ"); return; }
1213
1214 if (cell->type == "$_DLATCH_N_") { check_gate("EDQ"); return; }
1215 if (cell->type == "$_DLATCH_P_") { check_gate("EDQ"); return; }
1216
1217 if (cell->type == "$_DLATCHSR_NNN_") { check_gate("ESRDQ"); return; }
1218 if (cell->type == "$_DLATCHSR_NNP_") { check_gate("ESRDQ"); return; }
1219 if (cell->type == "$_DLATCHSR_NPN_") { check_gate("ESRDQ"); return; }
1220 if (cell->type == "$_DLATCHSR_NPP_") { check_gate("ESRDQ"); return; }
1221 if (cell->type == "$_DLATCHSR_PNN_") { check_gate("ESRDQ"); return; }
1222 if (cell->type == "$_DLATCHSR_PNP_") { check_gate("ESRDQ"); return; }
1223 if (cell->type == "$_DLATCHSR_PPN_") { check_gate("ESRDQ"); return; }
1224 if (cell->type == "$_DLATCHSR_PPP_") { check_gate("ESRDQ"); return; }
1225
1226 error(__LINE__);
1227 }
1228 };
1229 }
1230 #endif
1231
1232 void RTLIL::Module::sort()
1233 {
1234 wires_.sort(sort_by_id_str());
1235 cells_.sort(sort_by_id_str());
1236 avail_parameters.sort(sort_by_id_str());
1237 memories.sort(sort_by_id_str());
1238 processes.sort(sort_by_id_str());
1239 for (auto &it : cells_)
1240 it.second->sort();
1241 for (auto &it : wires_)
1242 it.second->attributes.sort(sort_by_id_str());
1243 for (auto &it : memories)
1244 it.second->attributes.sort(sort_by_id_str());
1245 }
1246
1247 void RTLIL::Module::check()
1248 {
1249 #ifndef NDEBUG
1250 std::vector<bool> ports_declared;
1251 for (auto &it : wires_) {
1252 log_assert(this == it.second->module);
1253 log_assert(it.first == it.second->name);
1254 log_assert(!it.first.empty());
1255 log_assert(it.second->width >= 0);
1256 log_assert(it.second->port_id >= 0);
1257 for (auto &it2 : it.second->attributes)
1258 log_assert(!it2.first.empty());
1259 if (it.second->port_id) {
1260 log_assert(GetSize(ports) >= it.second->port_id);
1261 log_assert(ports.at(it.second->port_id-1) == it.first);
1262 log_assert(it.second->port_input || it.second->port_output);
1263 if (GetSize(ports_declared) < it.second->port_id)
1264 ports_declared.resize(it.second->port_id);
1265 log_assert(ports_declared[it.second->port_id-1] == false);
1266 ports_declared[it.second->port_id-1] = true;
1267 } else
1268 log_assert(!it.second->port_input && !it.second->port_output);
1269 }
1270 for (auto port_declared : ports_declared)
1271 log_assert(port_declared == true);
1272 log_assert(GetSize(ports) == GetSize(ports_declared));
1273
1274 for (auto &it : memories) {
1275 log_assert(it.first == it.second->name);
1276 log_assert(!it.first.empty());
1277 log_assert(it.second->width >= 0);
1278 log_assert(it.second->size >= 0);
1279 for (auto &it2 : it.second->attributes)
1280 log_assert(!it2.first.empty());
1281 }
1282
1283 for (auto &it : cells_) {
1284 log_assert(this == it.second->module);
1285 log_assert(it.first == it.second->name);
1286 log_assert(!it.first.empty());
1287 log_assert(!it.second->type.empty());
1288 for (auto &it2 : it.second->connections()) {
1289 log_assert(!it2.first.empty());
1290 it2.second.check();
1291 }
1292 for (auto &it2 : it.second->attributes)
1293 log_assert(!it2.first.empty());
1294 for (auto &it2 : it.second->parameters)
1295 log_assert(!it2.first.empty());
1296 InternalCellChecker checker(this, it.second);
1297 checker.check();
1298 }
1299
1300 for (auto &it : processes) {
1301 log_assert(it.first == it.second->name);
1302 log_assert(!it.first.empty());
1303 // FIXME: More checks here..
1304 }
1305
1306 for (auto &it : connections_) {
1307 log_assert(it.first.size() == it.second.size());
1308 log_assert(!it.first.has_const());
1309 it.first.check();
1310 it.second.check();
1311 }
1312
1313 for (auto &it : attributes)
1314 log_assert(!it.first.empty());
1315 #endif
1316 }
1317
1318 void RTLIL::Module::optimize()
1319 {
1320 }
1321
1322 void RTLIL::Module::cloneInto(RTLIL::Module *new_mod) const
1323 {
1324 log_assert(new_mod->refcount_wires_ == 0);
1325 log_assert(new_mod->refcount_cells_ == 0);
1326
1327 new_mod->avail_parameters = avail_parameters;
1328
1329 for (auto &conn : connections_)
1330 new_mod->connect(conn);
1331
1332 for (auto &attr : attributes)
1333 new_mod->attributes[attr.first] = attr.second;
1334
1335 for (auto &it : wires_)
1336 new_mod->addWire(it.first, it.second);
1337
1338 for (auto &it : memories)
1339 new_mod->memories[it.first] = new RTLIL::Memory(*it.second);
1340
1341 for (auto &it : cells_)
1342 new_mod->addCell(it.first, it.second);
1343
1344 for (auto &it : processes)
1345 new_mod->processes[it.first] = it.second->clone();
1346
1347 struct RewriteSigSpecWorker
1348 {
1349 RTLIL::Module *mod;
1350 void operator()(RTLIL::SigSpec &sig)
1351 {
1352 std::vector<RTLIL::SigChunk> chunks = sig.chunks();
1353 for (auto &c : chunks)
1354 if (c.wire != NULL)
1355 c.wire = mod->wires_.at(c.wire->name);
1356 sig = chunks;
1357 }
1358 };
1359
1360 RewriteSigSpecWorker rewriteSigSpecWorker;
1361 rewriteSigSpecWorker.mod = new_mod;
1362 new_mod->rewrite_sigspecs(rewriteSigSpecWorker);
1363 new_mod->fixup_ports();
1364 }
1365
1366 RTLIL::Module *RTLIL::Module::clone() const
1367 {
1368 RTLIL::Module *new_mod = new RTLIL::Module;
1369 new_mod->name = name;
1370 cloneInto(new_mod);
1371 return new_mod;
1372 }
1373
1374 bool RTLIL::Module::has_memories() const
1375 {
1376 return !memories.empty();
1377 }
1378
1379 bool RTLIL::Module::has_processes() const
1380 {
1381 return !processes.empty();
1382 }
1383
1384 bool RTLIL::Module::has_memories_warn() const
1385 {
1386 if (!memories.empty())
1387 log_warning("Ignoring module %s because it contains memories (run 'memory' command first).\n", log_id(this));
1388 return !memories.empty();
1389 }
1390
1391 bool RTLIL::Module::has_processes_warn() const
1392 {
1393 if (!processes.empty())
1394 log_warning("Ignoring module %s because it contains processes (run 'proc' command first).\n", log_id(this));
1395 return !processes.empty();
1396 }
1397
1398 std::vector<RTLIL::Wire*> RTLIL::Module::selected_wires() const
1399 {
1400 std::vector<RTLIL::Wire*> result;
1401 result.reserve(wires_.size());
1402 for (auto &it : wires_)
1403 if (design->selected(this, it.second))
1404 result.push_back(it.second);
1405 return result;
1406 }
1407
1408 std::vector<RTLIL::Cell*> RTLIL::Module::selected_cells() const
1409 {
1410 std::vector<RTLIL::Cell*> result;
1411 result.reserve(wires_.size());
1412 for (auto &it : cells_)
1413 if (design->selected(this, it.second))
1414 result.push_back(it.second);
1415 return result;
1416 }
1417
1418 void RTLIL::Module::add(RTLIL::Wire *wire)
1419 {
1420 log_assert(!wire->name.empty());
1421 log_assert(count_id(wire->name) == 0);
1422 log_assert(refcount_wires_ == 0);
1423 wires_[wire->name] = wire;
1424 wire->module = this;
1425 }
1426
1427 void RTLIL::Module::add(RTLIL::Cell *cell)
1428 {
1429 log_assert(!cell->name.empty());
1430 log_assert(count_id(cell->name) == 0);
1431 log_assert(refcount_cells_ == 0);
1432 cells_[cell->name] = cell;
1433 cell->module = this;
1434 }
1435
1436 namespace {
1437 struct DeleteWireWorker
1438 {
1439 RTLIL::Module *module;
1440 const pool<RTLIL::Wire*> *wires_p;
1441
1442 void operator()(RTLIL::SigSpec &sig) {
1443 std::vector<RTLIL::SigChunk> chunks = sig;
1444 for (auto &c : chunks)
1445 if (c.wire != NULL && wires_p->count(c.wire)) {
1446 c.wire = module->addWire(NEW_ID, c.width);
1447 c.offset = 0;
1448 }
1449 sig = chunks;
1450 }
1451 };
1452 }
1453
1454 void RTLIL::Module::remove(const pool<RTLIL::Wire*> &wires)
1455 {
1456 log_assert(refcount_wires_ == 0);
1457
1458 DeleteWireWorker delete_wire_worker;
1459 delete_wire_worker.module = this;
1460 delete_wire_worker.wires_p = &wires;
1461 rewrite_sigspecs(delete_wire_worker);
1462
1463 for (auto &it : wires) {
1464 log_assert(wires_.count(it->name) != 0);
1465 wires_.erase(it->name);
1466 delete it;
1467 }
1468 }
1469
1470 void RTLIL::Module::remove(RTLIL::Cell *cell)
1471 {
1472 while (!cell->connections_.empty())
1473 cell->unsetPort(cell->connections_.begin()->first);
1474
1475 log_assert(cells_.count(cell->name) != 0);
1476 log_assert(refcount_cells_ == 0);
1477 cells_.erase(cell->name);
1478 delete cell;
1479 }
1480
1481 void RTLIL::Module::rename(RTLIL::Wire *wire, RTLIL::IdString new_name)
1482 {
1483 log_assert(wires_[wire->name] == wire);
1484 log_assert(refcount_wires_ == 0);
1485 wires_.erase(wire->name);
1486 wire->name = new_name;
1487 add(wire);
1488 }
1489
1490 void RTLIL::Module::rename(RTLIL::Cell *cell, RTLIL::IdString new_name)
1491 {
1492 log_assert(cells_[cell->name] == cell);
1493 log_assert(refcount_wires_ == 0);
1494 cells_.erase(cell->name);
1495 cell->name = new_name;
1496 add(cell);
1497 }
1498
1499 void RTLIL::Module::rename(RTLIL::IdString old_name, RTLIL::IdString new_name)
1500 {
1501 log_assert(count_id(old_name) != 0);
1502 if (wires_.count(old_name))
1503 rename(wires_.at(old_name), new_name);
1504 else if (cells_.count(old_name))
1505 rename(cells_.at(old_name), new_name);
1506 else
1507 log_abort();
1508 }
1509
1510 void RTLIL::Module::swap_names(RTLIL::Wire *w1, RTLIL::Wire *w2)
1511 {
1512 log_assert(wires_[w1->name] == w1);
1513 log_assert(wires_[w2->name] == w2);
1514 log_assert(refcount_wires_ == 0);
1515
1516 wires_.erase(w1->name);
1517 wires_.erase(w2->name);
1518
1519 std::swap(w1->name, w2->name);
1520
1521 wires_[w1->name] = w1;
1522 wires_[w2->name] = w2;
1523 }
1524
1525 void RTLIL::Module::swap_names(RTLIL::Cell *c1, RTLIL::Cell *c2)
1526 {
1527 log_assert(cells_[c1->name] == c1);
1528 log_assert(cells_[c2->name] == c2);
1529 log_assert(refcount_cells_ == 0);
1530
1531 cells_.erase(c1->name);
1532 cells_.erase(c2->name);
1533
1534 std::swap(c1->name, c2->name);
1535
1536 cells_[c1->name] = c1;
1537 cells_[c2->name] = c2;
1538 }
1539
1540 RTLIL::IdString RTLIL::Module::uniquify(RTLIL::IdString name)
1541 {
1542 int index = 0;
1543 return uniquify(name, index);
1544 }
1545
1546 RTLIL::IdString RTLIL::Module::uniquify(RTLIL::IdString name, int &index)
1547 {
1548 if (index == 0) {
1549 if (count_id(name) == 0)
1550 return name;
1551 index++;
1552 }
1553
1554 while (1) {
1555 RTLIL::IdString new_name = stringf("%s_%d", name.c_str(), index);
1556 if (count_id(new_name) == 0)
1557 return new_name;
1558 index++;
1559 }
1560 }
1561
1562 static bool fixup_ports_compare(const RTLIL::Wire *a, const RTLIL::Wire *b)
1563 {
1564 if (a->port_id && !b->port_id)
1565 return true;
1566 if (!a->port_id && b->port_id)
1567 return false;
1568
1569 if (a->port_id == b->port_id)
1570 return a->name < b->name;
1571 return a->port_id < b->port_id;
1572 }
1573
1574 void RTLIL::Module::connect(const RTLIL::SigSig &conn)
1575 {
1576 for (auto mon : monitors)
1577 mon->notify_connect(this, conn);
1578
1579 if (design)
1580 for (auto mon : design->monitors)
1581 mon->notify_connect(this, conn);
1582
1583 // ignore all attempts to assign constants to other constants
1584 if (conn.first.has_const()) {
1585 RTLIL::SigSig new_conn;
1586 for (int i = 0; i < GetSize(conn.first); i++)
1587 if (conn.first[i].wire) {
1588 new_conn.first.append(conn.first[i]);
1589 new_conn.second.append(conn.second[i]);
1590 }
1591 if (GetSize(new_conn.first))
1592 connect(new_conn);
1593 return;
1594 }
1595
1596 if (yosys_xtrace) {
1597 log("#X# Connect (SigSig) in %s: %s = %s (%d bits)\n", log_id(this), log_signal(conn.first), log_signal(conn.second), GetSize(conn.first));
1598 log_backtrace("-X- ", yosys_xtrace-1);
1599 }
1600
1601 log_assert(GetSize(conn.first) == GetSize(conn.second));
1602 connections_.push_back(conn);
1603 }
1604
1605 void RTLIL::Module::connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs)
1606 {
1607 connect(RTLIL::SigSig(lhs, rhs));
1608 }
1609
1610 void RTLIL::Module::new_connections(const std::vector<RTLIL::SigSig> &new_conn)
1611 {
1612 for (auto mon : monitors)
1613 mon->notify_connect(this, new_conn);
1614
1615 if (design)
1616 for (auto mon : design->monitors)
1617 mon->notify_connect(this, new_conn);
1618
1619 if (yosys_xtrace) {
1620 log("#X# New connections vector in %s:\n", log_id(this));
1621 for (auto &conn: new_conn)
1622 log("#X# %s = %s (%d bits)\n", log_signal(conn.first), log_signal(conn.second), GetSize(conn.first));
1623 log_backtrace("-X- ", yosys_xtrace-1);
1624 }
1625
1626 connections_ = new_conn;
1627 }
1628
1629 const std::vector<RTLIL::SigSig> &RTLIL::Module::connections() const
1630 {
1631 return connections_;
1632 }
1633
1634 void RTLIL::Module::fixup_ports()
1635 {
1636 std::vector<RTLIL::Wire*> all_ports;
1637
1638 for (auto &w : wires_)
1639 if (w.second->port_input || w.second->port_output)
1640 all_ports.push_back(w.second);
1641 else
1642 w.second->port_id = 0;
1643
1644 std::sort(all_ports.begin(), all_ports.end(), fixup_ports_compare);
1645
1646 ports.clear();
1647 for (size_t i = 0; i < all_ports.size(); i++) {
1648 ports.push_back(all_ports[i]->name);
1649 all_ports[i]->port_id = i+1;
1650 }
1651 }
1652
1653 RTLIL::Wire *RTLIL::Module::addWire(RTLIL::IdString name, int width)
1654 {
1655 RTLIL::Wire *wire = new RTLIL::Wire;
1656 wire->name = name;
1657 wire->width = width;
1658 add(wire);
1659 return wire;
1660 }
1661
1662 RTLIL::Wire *RTLIL::Module::addWire(RTLIL::IdString name, const RTLIL::Wire *other)
1663 {
1664 RTLIL::Wire *wire = addWire(name);
1665 wire->width = other->width;
1666 wire->start_offset = other->start_offset;
1667 wire->port_id = other->port_id;
1668 wire->port_input = other->port_input;
1669 wire->port_output = other->port_output;
1670 wire->upto = other->upto;
1671 wire->attributes = other->attributes;
1672 return wire;
1673 }
1674
1675 RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, RTLIL::IdString type)
1676 {
1677 RTLIL::Cell *cell = new RTLIL::Cell;
1678 cell->name = name;
1679 cell->type = type;
1680 add(cell);
1681 return cell;
1682 }
1683
1684 RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, const RTLIL::Cell *other)
1685 {
1686 RTLIL::Cell *cell = addCell(name, other->type);
1687 cell->connections_ = other->connections_;
1688 cell->parameters = other->parameters;
1689 cell->attributes = other->attributes;
1690 return cell;
1691 }
1692
1693 #define DEF_METHOD(_func, _y_size, _type) \
1694 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed, const std::string &src) { \
1695 RTLIL::Cell *cell = addCell(name, _type); \
1696 cell->parameters["\\A_SIGNED"] = is_signed; \
1697 cell->parameters["\\A_WIDTH"] = sig_a.size(); \
1698 cell->parameters["\\Y_WIDTH"] = sig_y.size(); \
1699 cell->setPort("\\A", sig_a); \
1700 cell->setPort("\\Y", sig_y); \
1701 cell->set_src_attribute(src); \
1702 return cell; \
1703 } \
1704 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed, const std::string &src) { \
1705 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
1706 add ## _func(name, sig_a, sig_y, is_signed, src); \
1707 return sig_y; \
1708 }
1709 DEF_METHOD(Not, sig_a.size(), "$not")
1710 DEF_METHOD(Pos, sig_a.size(), "$pos")
1711 DEF_METHOD(Neg, sig_a.size(), "$neg")
1712 DEF_METHOD(ReduceAnd, 1, "$reduce_and")
1713 DEF_METHOD(ReduceOr, 1, "$reduce_or")
1714 DEF_METHOD(ReduceXor, 1, "$reduce_xor")
1715 DEF_METHOD(ReduceXnor, 1, "$reduce_xnor")
1716 DEF_METHOD(ReduceBool, 1, "$reduce_bool")
1717 DEF_METHOD(LogicNot, 1, "$logic_not")
1718 #undef DEF_METHOD
1719
1720 #define DEF_METHOD(_func, _y_size, _type) \
1721 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed, const std::string &src) { \
1722 RTLIL::Cell *cell = addCell(name, _type); \
1723 cell->parameters["\\A_SIGNED"] = is_signed; \
1724 cell->parameters["\\B_SIGNED"] = is_signed; \
1725 cell->parameters["\\A_WIDTH"] = sig_a.size(); \
1726 cell->parameters["\\B_WIDTH"] = sig_b.size(); \
1727 cell->parameters["\\Y_WIDTH"] = sig_y.size(); \
1728 cell->setPort("\\A", sig_a); \
1729 cell->setPort("\\B", sig_b); \
1730 cell->setPort("\\Y", sig_y); \
1731 cell->set_src_attribute(src); \
1732 return cell; \
1733 } \
1734 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed, const std::string &src) { \
1735 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
1736 add ## _func(name, sig_a, sig_b, sig_y, is_signed, src); \
1737 return sig_y; \
1738 }
1739 DEF_METHOD(And, max(sig_a.size(), sig_b.size()), "$and")
1740 DEF_METHOD(Or, max(sig_a.size(), sig_b.size()), "$or")
1741 DEF_METHOD(Xor, max(sig_a.size(), sig_b.size()), "$xor")
1742 DEF_METHOD(Xnor, max(sig_a.size(), sig_b.size()), "$xnor")
1743 DEF_METHOD(Shl, sig_a.size(), "$shl")
1744 DEF_METHOD(Shr, sig_a.size(), "$shr")
1745 DEF_METHOD(Sshl, sig_a.size(), "$sshl")
1746 DEF_METHOD(Sshr, sig_a.size(), "$sshr")
1747 DEF_METHOD(Shift, sig_a.size(), "$shift")
1748 DEF_METHOD(Shiftx, sig_a.size(), "$shiftx")
1749 DEF_METHOD(Lt, 1, "$lt")
1750 DEF_METHOD(Le, 1, "$le")
1751 DEF_METHOD(Eq, 1, "$eq")
1752 DEF_METHOD(Ne, 1, "$ne")
1753 DEF_METHOD(Eqx, 1, "$eqx")
1754 DEF_METHOD(Nex, 1, "$nex")
1755 DEF_METHOD(Ge, 1, "$ge")
1756 DEF_METHOD(Gt, 1, "$gt")
1757 DEF_METHOD(Add, max(sig_a.size(), sig_b.size()), "$add")
1758 DEF_METHOD(Sub, max(sig_a.size(), sig_b.size()), "$sub")
1759 DEF_METHOD(Mul, max(sig_a.size(), sig_b.size()), "$mul")
1760 DEF_METHOD(Div, max(sig_a.size(), sig_b.size()), "$div")
1761 DEF_METHOD(Mod, max(sig_a.size(), sig_b.size()), "$mod")
1762 DEF_METHOD(LogicAnd, 1, "$logic_and")
1763 DEF_METHOD(LogicOr, 1, "$logic_or")
1764 #undef DEF_METHOD
1765
1766 #define DEF_METHOD(_func, _type, _pmux) \
1767 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, RTLIL::SigSpec sig_y, const std::string &src) { \
1768 RTLIL::Cell *cell = addCell(name, _type); \
1769 cell->parameters["\\WIDTH"] = sig_a.size(); \
1770 if (_pmux) cell->parameters["\\S_WIDTH"] = sig_s.size(); \
1771 cell->setPort("\\A", sig_a); \
1772 cell->setPort("\\B", sig_b); \
1773 cell->setPort("\\S", sig_s); \
1774 cell->setPort("\\Y", sig_y); \
1775 cell->set_src_attribute(src); \
1776 return cell; \
1777 } \
1778 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, const std::string &src) { \
1779 RTLIL::SigSpec sig_y = addWire(NEW_ID, sig_a.size()); \
1780 add ## _func(name, sig_a, sig_b, sig_s, sig_y, src); \
1781 return sig_y; \
1782 }
1783 DEF_METHOD(Mux, "$mux", 0)
1784 DEF_METHOD(Pmux, "$pmux", 1)
1785 #undef DEF_METHOD
1786
1787 #define DEF_METHOD_2(_func, _type, _P1, _P2) \
1788 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, const std::string &src) { \
1789 RTLIL::Cell *cell = addCell(name, _type); \
1790 cell->setPort("\\" #_P1, sig1); \
1791 cell->setPort("\\" #_P2, sig2); \
1792 cell->set_src_attribute(src); \
1793 return cell; \
1794 } \
1795 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, const std::string &src) { \
1796 RTLIL::SigBit sig2 = addWire(NEW_ID); \
1797 add ## _func(name, sig1, sig2, src); \
1798 return sig2; \
1799 }
1800 #define DEF_METHOD_3(_func, _type, _P1, _P2, _P3) \
1801 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, const std::string &src) { \
1802 RTLIL::Cell *cell = addCell(name, _type); \
1803 cell->setPort("\\" #_P1, sig1); \
1804 cell->setPort("\\" #_P2, sig2); \
1805 cell->setPort("\\" #_P3, sig3); \
1806 cell->set_src_attribute(src); \
1807 return cell; \
1808 } \
1809 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, const std::string &src) { \
1810 RTLIL::SigBit sig3 = addWire(NEW_ID); \
1811 add ## _func(name, sig1, sig2, sig3, src); \
1812 return sig3; \
1813 }
1814 #define DEF_METHOD_4(_func, _type, _P1, _P2, _P3, _P4) \
1815 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, RTLIL::SigBit sig4, const std::string &src) { \
1816 RTLIL::Cell *cell = addCell(name, _type); \
1817 cell->setPort("\\" #_P1, sig1); \
1818 cell->setPort("\\" #_P2, sig2); \
1819 cell->setPort("\\" #_P3, sig3); \
1820 cell->setPort("\\" #_P4, sig4); \
1821 cell->set_src_attribute(src); \
1822 return cell; \
1823 } \
1824 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, const std::string &src) { \
1825 RTLIL::SigBit sig4 = addWire(NEW_ID); \
1826 add ## _func(name, sig1, sig2, sig3, sig4, src); \
1827 return sig4; \
1828 }
1829 #define DEF_METHOD_5(_func, _type, _P1, _P2, _P3, _P4, _P5) \
1830 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, RTLIL::SigBit sig4, RTLIL::SigBit sig5, const std::string &src) { \
1831 RTLIL::Cell *cell = addCell(name, _type); \
1832 cell->setPort("\\" #_P1, sig1); \
1833 cell->setPort("\\" #_P2, sig2); \
1834 cell->setPort("\\" #_P3, sig3); \
1835 cell->setPort("\\" #_P4, sig4); \
1836 cell->setPort("\\" #_P5, sig5); \
1837 cell->set_src_attribute(src); \
1838 return cell; \
1839 } \
1840 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, RTLIL::SigBit sig4, const std::string &src) { \
1841 RTLIL::SigBit sig5 = addWire(NEW_ID); \
1842 add ## _func(name, sig1, sig2, sig3, sig4, sig5, src); \
1843 return sig5; \
1844 }
1845 DEF_METHOD_2(BufGate, "$_BUF_", A, Y)
1846 DEF_METHOD_2(NotGate, "$_NOT_", A, Y)
1847 DEF_METHOD_3(AndGate, "$_AND_", A, B, Y)
1848 DEF_METHOD_3(NandGate, "$_NAND_", A, B, Y)
1849 DEF_METHOD_3(OrGate, "$_OR_", A, B, Y)
1850 DEF_METHOD_3(NorGate, "$_NOR_", A, B, Y)
1851 DEF_METHOD_3(XorGate, "$_XOR_", A, B, Y)
1852 DEF_METHOD_3(XnorGate, "$_XNOR_", A, B, Y)
1853 DEF_METHOD_3(AndnotGate, "$_ANDNOT_", A, B, Y)
1854 DEF_METHOD_3(OrnotGate, "$_ORNOT_", A, B, Y)
1855 DEF_METHOD_4(MuxGate, "$_MUX_", A, B, S, Y)
1856 DEF_METHOD_4(Aoi3Gate, "$_AOI3_", A, B, C, Y)
1857 DEF_METHOD_4(Oai3Gate, "$_OAI3_", A, B, C, Y)
1858 DEF_METHOD_5(Aoi4Gate, "$_AOI4_", A, B, C, D, Y)
1859 DEF_METHOD_5(Oai4Gate, "$_OAI4_", A, B, C, D, Y)
1860 #undef DEF_METHOD_2
1861 #undef DEF_METHOD_3
1862 #undef DEF_METHOD_4
1863 #undef DEF_METHOD_5
1864
1865 RTLIL::Cell* RTLIL::Module::addPow(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool a_signed, bool b_signed, const std::string &src)
1866 {
1867 RTLIL::Cell *cell = addCell(name, "$pow");
1868 cell->parameters["\\A_SIGNED"] = a_signed;
1869 cell->parameters["\\B_SIGNED"] = b_signed;
1870 cell->parameters["\\A_WIDTH"] = sig_a.size();
1871 cell->parameters["\\B_WIDTH"] = sig_b.size();
1872 cell->parameters["\\Y_WIDTH"] = sig_y.size();
1873 cell->setPort("\\A", sig_a);
1874 cell->setPort("\\B", sig_b);
1875 cell->setPort("\\Y", sig_y);
1876 cell->set_src_attribute(src);
1877 return cell;
1878 }
1879
1880 RTLIL::Cell* RTLIL::Module::addSlice(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, RTLIL::Const offset, const std::string &src)
1881 {
1882 RTLIL::Cell *cell = addCell(name, "$slice");
1883 cell->parameters["\\A_WIDTH"] = sig_a.size();
1884 cell->parameters["\\Y_WIDTH"] = sig_y.size();
1885 cell->parameters["\\OFFSET"] = offset;
1886 cell->setPort("\\A", sig_a);
1887 cell->setPort("\\Y", sig_y);
1888 cell->set_src_attribute(src);
1889 return cell;
1890 }
1891
1892 RTLIL::Cell* RTLIL::Module::addConcat(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, const std::string &src)
1893 {
1894 RTLIL::Cell *cell = addCell(name, "$concat");
1895 cell->parameters["\\A_WIDTH"] = sig_a.size();
1896 cell->parameters["\\B_WIDTH"] = sig_b.size();
1897 cell->setPort("\\A", sig_a);
1898 cell->setPort("\\B", sig_b);
1899 cell->setPort("\\Y", sig_y);
1900 cell->set_src_attribute(src);
1901 return cell;
1902 }
1903
1904 RTLIL::Cell* RTLIL::Module::addLut(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, RTLIL::Const lut, const std::string &src)
1905 {
1906 RTLIL::Cell *cell = addCell(name, "$lut");
1907 cell->parameters["\\LUT"] = lut;
1908 cell->parameters["\\WIDTH"] = sig_a.size();
1909 cell->setPort("\\A", sig_a);
1910 cell->setPort("\\Y", sig_y);
1911 cell->set_src_attribute(src);
1912 return cell;
1913 }
1914
1915 RTLIL::Cell* RTLIL::Module::addTribuf(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_y, const std::string &src)
1916 {
1917 RTLIL::Cell *cell = addCell(name, "$tribuf");
1918 cell->parameters["\\WIDTH"] = sig_a.size();
1919 cell->setPort("\\A", sig_a);
1920 cell->setPort("\\EN", sig_en);
1921 cell->setPort("\\Y", sig_y);
1922 cell->set_src_attribute(src);
1923 return cell;
1924 }
1925
1926 RTLIL::Cell* RTLIL::Module::addAssert(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src)
1927 {
1928 RTLIL::Cell *cell = addCell(name, "$assert");
1929 cell->setPort("\\A", sig_a);
1930 cell->setPort("\\EN", sig_en);
1931 cell->set_src_attribute(src);
1932 return cell;
1933 }
1934
1935 RTLIL::Cell* RTLIL::Module::addAssume(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src)
1936 {
1937 RTLIL::Cell *cell = addCell(name, "$assume");
1938 cell->setPort("\\A", sig_a);
1939 cell->setPort("\\EN", sig_en);
1940 cell->set_src_attribute(src);
1941 return cell;
1942 }
1943
1944 RTLIL::Cell* RTLIL::Module::addLive(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src)
1945 {
1946 RTLIL::Cell *cell = addCell(name, "$live");
1947 cell->setPort("\\A", sig_a);
1948 cell->setPort("\\EN", sig_en);
1949 cell->set_src_attribute(src);
1950 return cell;
1951 }
1952
1953 RTLIL::Cell* RTLIL::Module::addFair(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src)
1954 {
1955 RTLIL::Cell *cell = addCell(name, "$fair");
1956 cell->setPort("\\A", sig_a);
1957 cell->setPort("\\EN", sig_en);
1958 cell->set_src_attribute(src);
1959 return cell;
1960 }
1961
1962 RTLIL::Cell* RTLIL::Module::addCover(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src)
1963 {
1964 RTLIL::Cell *cell = addCell(name, "$cover");
1965 cell->setPort("\\A", sig_a);
1966 cell->setPort("\\EN", sig_en);
1967 cell->set_src_attribute(src);
1968 return cell;
1969 }
1970
1971 RTLIL::Cell* RTLIL::Module::addEquiv(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, const std::string &src)
1972 {
1973 RTLIL::Cell *cell = addCell(name, "$equiv");
1974 cell->setPort("\\A", sig_a);
1975 cell->setPort("\\B", sig_b);
1976 cell->setPort("\\Y", sig_y);
1977 cell->set_src_attribute(src);
1978 return cell;
1979 }
1980
1981 RTLIL::Cell* RTLIL::Module::addSr(RTLIL::IdString name, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr, RTLIL::SigSpec sig_q, bool set_polarity, bool clr_polarity, const std::string &src)
1982 {
1983 RTLIL::Cell *cell = addCell(name, "$sr");
1984 cell->parameters["\\SET_POLARITY"] = set_polarity;
1985 cell->parameters["\\CLR_POLARITY"] = clr_polarity;
1986 cell->parameters["\\WIDTH"] = sig_q.size();
1987 cell->setPort("\\SET", sig_set);
1988 cell->setPort("\\CLR", sig_clr);
1989 cell->setPort("\\Q", sig_q);
1990 cell->set_src_attribute(src);
1991 return cell;
1992 }
1993
1994 RTLIL::Cell* RTLIL::Module::addFf(RTLIL::IdString name, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, const std::string &src)
1995 {
1996 RTLIL::Cell *cell = addCell(name, "$ff");
1997 cell->parameters["\\WIDTH"] = sig_q.size();
1998 cell->setPort("\\D", sig_d);
1999 cell->setPort("\\Q", sig_q);
2000 cell->set_src_attribute(src);
2001 return cell;
2002 }
2003
2004 RTLIL::Cell* RTLIL::Module::addDff(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, const std::string &src)
2005 {
2006 RTLIL::Cell *cell = addCell(name, "$dff");
2007 cell->parameters["\\CLK_POLARITY"] = clk_polarity;
2008 cell->parameters["\\WIDTH"] = sig_q.size();
2009 cell->setPort("\\CLK", sig_clk);
2010 cell->setPort("\\D", sig_d);
2011 cell->setPort("\\Q", sig_q);
2012 cell->set_src_attribute(src);
2013 return cell;
2014 }
2015
2016 RTLIL::Cell* RTLIL::Module::addDffe(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, bool en_polarity, const std::string &src)
2017 {
2018 RTLIL::Cell *cell = addCell(name, "$dffe");
2019 cell->parameters["\\CLK_POLARITY"] = clk_polarity;
2020 cell->parameters["\\EN_POLARITY"] = en_polarity;
2021 cell->parameters["\\WIDTH"] = sig_q.size();
2022 cell->setPort("\\CLK", sig_clk);
2023 cell->setPort("\\EN", sig_en);
2024 cell->setPort("\\D", sig_d);
2025 cell->setPort("\\Q", sig_q);
2026 cell->set_src_attribute(src);
2027 return cell;
2028 }
2029
2030 RTLIL::Cell* RTLIL::Module::addDffsr(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
2031 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
2032 {
2033 RTLIL::Cell *cell = addCell(name, "$dffsr");
2034 cell->parameters["\\CLK_POLARITY"] = clk_polarity;
2035 cell->parameters["\\SET_POLARITY"] = set_polarity;
2036 cell->parameters["\\CLR_POLARITY"] = clr_polarity;
2037 cell->parameters["\\WIDTH"] = sig_q.size();
2038 cell->setPort("\\CLK", sig_clk);
2039 cell->setPort("\\SET", sig_set);
2040 cell->setPort("\\CLR", sig_clr);
2041 cell->setPort("\\D", sig_d);
2042 cell->setPort("\\Q", sig_q);
2043 cell->set_src_attribute(src);
2044 return cell;
2045 }
2046
2047 RTLIL::Cell* RTLIL::Module::addAdff(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_arst, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q,
2048 RTLIL::Const arst_value, bool clk_polarity, bool arst_polarity, const std::string &src)
2049 {
2050 RTLIL::Cell *cell = addCell(name, "$adff");
2051 cell->parameters["\\CLK_POLARITY"] = clk_polarity;
2052 cell->parameters["\\ARST_POLARITY"] = arst_polarity;
2053 cell->parameters["\\ARST_VALUE"] = arst_value;
2054 cell->parameters["\\WIDTH"] = sig_q.size();
2055 cell->setPort("\\CLK", sig_clk);
2056 cell->setPort("\\ARST", sig_arst);
2057 cell->setPort("\\D", sig_d);
2058 cell->setPort("\\Q", sig_q);
2059 cell->set_src_attribute(src);
2060 return cell;
2061 }
2062
2063 RTLIL::Cell* RTLIL::Module::addDlatch(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity, const std::string &src)
2064 {
2065 RTLIL::Cell *cell = addCell(name, "$dlatch");
2066 cell->parameters["\\EN_POLARITY"] = en_polarity;
2067 cell->parameters["\\WIDTH"] = sig_q.size();
2068 cell->setPort("\\EN", sig_en);
2069 cell->setPort("\\D", sig_d);
2070 cell->setPort("\\Q", sig_q);
2071 cell->set_src_attribute(src);
2072 return cell;
2073 }
2074
2075 RTLIL::Cell* RTLIL::Module::addDlatchsr(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
2076 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
2077 {
2078 RTLIL::Cell *cell = addCell(name, "$dlatchsr");
2079 cell->parameters["\\EN_POLARITY"] = en_polarity;
2080 cell->parameters["\\SET_POLARITY"] = set_polarity;
2081 cell->parameters["\\CLR_POLARITY"] = clr_polarity;
2082 cell->parameters["\\WIDTH"] = sig_q.size();
2083 cell->setPort("\\EN", sig_en);
2084 cell->setPort("\\SET", sig_set);
2085 cell->setPort("\\CLR", sig_clr);
2086 cell->setPort("\\D", sig_d);
2087 cell->setPort("\\Q", sig_q);
2088 cell->set_src_attribute(src);
2089 return cell;
2090 }
2091
2092 RTLIL::Cell* RTLIL::Module::addFfGate(RTLIL::IdString name, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, const std::string &src)
2093 {
2094 RTLIL::Cell *cell = addCell(name, "$_FF_");
2095 cell->setPort("\\D", sig_d);
2096 cell->setPort("\\Q", sig_q);
2097 cell->set_src_attribute(src);
2098 return cell;
2099 }
2100
2101 RTLIL::Cell* RTLIL::Module::addDffGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, const std::string &src)
2102 {
2103 RTLIL::Cell *cell = addCell(name, stringf("$_DFF_%c_", clk_polarity ? 'P' : 'N'));
2104 cell->setPort("\\C", sig_clk);
2105 cell->setPort("\\D", sig_d);
2106 cell->setPort("\\Q", sig_q);
2107 cell->set_src_attribute(src);
2108 return cell;
2109 }
2110
2111 RTLIL::Cell* RTLIL::Module::addDffeGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, bool en_polarity, const std::string &src)
2112 {
2113 RTLIL::Cell *cell = addCell(name, stringf("$_DFFE_%c%c_", clk_polarity ? 'P' : 'N', en_polarity ? 'P' : 'N'));
2114 cell->setPort("\\C", sig_clk);
2115 cell->setPort("\\E", sig_en);
2116 cell->setPort("\\D", sig_d);
2117 cell->setPort("\\Q", sig_q);
2118 cell->set_src_attribute(src);
2119 return cell;
2120 }
2121
2122 RTLIL::Cell* RTLIL::Module::addDffsrGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
2123 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
2124 {
2125 RTLIL::Cell *cell = addCell(name, stringf("$_DFFSR_%c%c%c_", clk_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N'));
2126 cell->setPort("\\C", sig_clk);
2127 cell->setPort("\\S", sig_set);
2128 cell->setPort("\\R", sig_clr);
2129 cell->setPort("\\D", sig_d);
2130 cell->setPort("\\Q", sig_q);
2131 cell->set_src_attribute(src);
2132 return cell;
2133 }
2134
2135 RTLIL::Cell* RTLIL::Module::addAdffGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_arst, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q,
2136 bool arst_value, bool clk_polarity, bool arst_polarity, const std::string &src)
2137 {
2138 RTLIL::Cell *cell = addCell(name, stringf("$_DFF_%c%c%c_", clk_polarity ? 'P' : 'N', arst_polarity ? 'P' : 'N', arst_value ? '1' : '0'));
2139 cell->setPort("\\C", sig_clk);
2140 cell->setPort("\\R", sig_arst);
2141 cell->setPort("\\D", sig_d);
2142 cell->setPort("\\Q", sig_q);
2143 cell->set_src_attribute(src);
2144 return cell;
2145 }
2146
2147 RTLIL::Cell* RTLIL::Module::addDlatchGate(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity, const std::string &src)
2148 {
2149 RTLIL::Cell *cell = addCell(name, stringf("$_DLATCH_%c_", en_polarity ? 'P' : 'N'));
2150 cell->setPort("\\E", sig_en);
2151 cell->setPort("\\D", sig_d);
2152 cell->setPort("\\Q", sig_q);
2153 cell->set_src_attribute(src);
2154 return cell;
2155 }
2156
2157 RTLIL::Cell* RTLIL::Module::addDlatchsrGate(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
2158 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
2159 {
2160 RTLIL::Cell *cell = addCell(name, stringf("$_DLATCHSR_%c%c%c_", en_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N'));
2161 cell->setPort("\\E", sig_en);
2162 cell->setPort("\\S", sig_set);
2163 cell->setPort("\\R", sig_clr);
2164 cell->setPort("\\D", sig_d);
2165 cell->setPort("\\Q", sig_q);
2166 cell->set_src_attribute(src);
2167 return cell;
2168 }
2169
2170 RTLIL::SigSpec RTLIL::Module::Anyconst(RTLIL::IdString name, int width, const std::string &src)
2171 {
2172 RTLIL::SigSpec sig = addWire(NEW_ID, width);
2173 Cell *cell = addCell(name, "$anyconst");
2174 cell->setParam("\\WIDTH", width);
2175 cell->setPort("\\Y", sig);
2176 cell->set_src_attribute(src);
2177 return sig;
2178 }
2179
2180 RTLIL::SigSpec RTLIL::Module::Anyseq(RTLIL::IdString name, int width, const std::string &src)
2181 {
2182 RTLIL::SigSpec sig = addWire(NEW_ID, width);
2183 Cell *cell = addCell(name, "$anyseq");
2184 cell->setParam("\\WIDTH", width);
2185 cell->setPort("\\Y", sig);
2186 cell->set_src_attribute(src);
2187 return sig;
2188 }
2189
2190 RTLIL::SigSpec RTLIL::Module::Allconst(RTLIL::IdString name, int width, const std::string &src)
2191 {
2192 RTLIL::SigSpec sig = addWire(NEW_ID, width);
2193 Cell *cell = addCell(name, "$allconst");
2194 cell->setParam("\\WIDTH", width);
2195 cell->setPort("\\Y", sig);
2196 cell->set_src_attribute(src);
2197 return sig;
2198 }
2199
2200 RTLIL::SigSpec RTLIL::Module::Allseq(RTLIL::IdString name, int width, const std::string &src)
2201 {
2202 RTLIL::SigSpec sig = addWire(NEW_ID, width);
2203 Cell *cell = addCell(name, "$allseq");
2204 cell->setParam("\\WIDTH", width);
2205 cell->setPort("\\Y", sig);
2206 cell->set_src_attribute(src);
2207 return sig;
2208 }
2209
2210 RTLIL::SigSpec RTLIL::Module::Initstate(RTLIL::IdString name, const std::string &src)
2211 {
2212 RTLIL::SigSpec sig = addWire(NEW_ID);
2213 Cell *cell = addCell(name, "$initstate");
2214 cell->setPort("\\Y", sig);
2215 cell->set_src_attribute(src);
2216 return sig;
2217 }
2218
2219 RTLIL::Wire::Wire()
2220 {
2221 static unsigned int hashidx_count = 123456789;
2222 hashidx_count = mkhash_xorshift(hashidx_count);
2223 hashidx_ = hashidx_count;
2224
2225 module = nullptr;
2226 width = 1;
2227 start_offset = 0;
2228 port_id = 0;
2229 port_input = false;
2230 port_output = false;
2231 upto = false;
2232 }
2233
2234 RTLIL::Memory::Memory()
2235 {
2236 static unsigned int hashidx_count = 123456789;
2237 hashidx_count = mkhash_xorshift(hashidx_count);
2238 hashidx_ = hashidx_count;
2239
2240 width = 1;
2241 start_offset = 0;
2242 size = 0;
2243 }
2244
2245 RTLIL::Cell::Cell() : module(nullptr)
2246 {
2247 static unsigned int hashidx_count = 123456789;
2248 hashidx_count = mkhash_xorshift(hashidx_count);
2249 hashidx_ = hashidx_count;
2250
2251 // log("#memtrace# %p\n", this);
2252 memhasher();
2253 }
2254
2255 bool RTLIL::Cell::hasPort(RTLIL::IdString portname) const
2256 {
2257 return connections_.count(portname) != 0;
2258 }
2259
2260 void RTLIL::Cell::unsetPort(RTLIL::IdString portname)
2261 {
2262 RTLIL::SigSpec signal;
2263 auto conn_it = connections_.find(portname);
2264
2265 if (conn_it != connections_.end())
2266 {
2267 for (auto mon : module->monitors)
2268 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
2269
2270 if (module->design)
2271 for (auto mon : module->design->monitors)
2272 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
2273
2274 if (yosys_xtrace) {
2275 log("#X# Unconnect %s.%s.%s\n", log_id(this->module), log_id(this), log_id(portname));
2276 log_backtrace("-X- ", yosys_xtrace-1);
2277 }
2278
2279 connections_.erase(conn_it);
2280 }
2281 }
2282
2283 void RTLIL::Cell::setPort(RTLIL::IdString portname, RTLIL::SigSpec signal)
2284 {
2285 auto conn_it = connections_.find(portname);
2286
2287 if (conn_it == connections_.end()) {
2288 connections_[portname] = RTLIL::SigSpec();
2289 conn_it = connections_.find(portname);
2290 log_assert(conn_it != connections_.end());
2291 } else
2292 if (conn_it->second == signal)
2293 return;
2294
2295 for (auto mon : module->monitors)
2296 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
2297
2298 if (module->design)
2299 for (auto mon : module->design->monitors)
2300 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
2301
2302 if (yosys_xtrace) {
2303 log("#X# Connect %s.%s.%s = %s (%d)\n", log_id(this->module), log_id(this), log_id(portname), log_signal(signal), GetSize(signal));
2304 log_backtrace("-X- ", yosys_xtrace-1);
2305 }
2306
2307 conn_it->second = signal;
2308 }
2309
2310 const RTLIL::SigSpec &RTLIL::Cell::getPort(RTLIL::IdString portname) const
2311 {
2312 return connections_.at(portname);
2313 }
2314
2315 const dict<RTLIL::IdString, RTLIL::SigSpec> &RTLIL::Cell::connections() const
2316 {
2317 return connections_;
2318 }
2319
2320 bool RTLIL::Cell::known() const
2321 {
2322 if (yosys_celltypes.cell_known(type))
2323 return true;
2324 if (module && module->design && module->design->module(type))
2325 return true;
2326 return false;
2327 }
2328
2329 bool RTLIL::Cell::input(RTLIL::IdString portname) const
2330 {
2331 if (yosys_celltypes.cell_known(type))
2332 return yosys_celltypes.cell_input(type, portname);
2333 if (module && module->design) {
2334 RTLIL::Module *m = module->design->module(type);
2335 RTLIL::Wire *w = m ? m->wire(portname) : nullptr;
2336 return w && w->port_input;
2337 }
2338 return false;
2339 }
2340
2341 bool RTLIL::Cell::output(RTLIL::IdString portname) const
2342 {
2343 if (yosys_celltypes.cell_known(type))
2344 return yosys_celltypes.cell_output(type, portname);
2345 if (module && module->design) {
2346 RTLIL::Module *m = module->design->module(type);
2347 RTLIL::Wire *w = m ? m->wire(portname) : nullptr;
2348 return w && w->port_output;
2349 }
2350 return false;
2351 }
2352
2353 bool RTLIL::Cell::hasParam(RTLIL::IdString paramname) const
2354 {
2355 return parameters.count(paramname) != 0;
2356 }
2357
2358 void RTLIL::Cell::unsetParam(RTLIL::IdString paramname)
2359 {
2360 parameters.erase(paramname);
2361 }
2362
2363 void RTLIL::Cell::setParam(RTLIL::IdString paramname, RTLIL::Const value)
2364 {
2365 parameters[paramname] = value;
2366 }
2367
2368 const RTLIL::Const &RTLIL::Cell::getParam(RTLIL::IdString paramname) const
2369 {
2370 return parameters.at(paramname);
2371 }
2372
2373 void RTLIL::Cell::sort()
2374 {
2375 connections_.sort(sort_by_id_str());
2376 parameters.sort(sort_by_id_str());
2377 attributes.sort(sort_by_id_str());
2378 }
2379
2380 void RTLIL::Cell::check()
2381 {
2382 #ifndef NDEBUG
2383 InternalCellChecker checker(NULL, this);
2384 checker.check();
2385 #endif
2386 }
2387
2388 void RTLIL::Cell::fixup_parameters(bool set_a_signed, bool set_b_signed)
2389 {
2390 if (type.substr(0, 1) != "$" || type.substr(0, 2) == "$_" || type.substr(0, 8) == "$paramod" || type.substr(0,10) == "$fmcombine" ||
2391 type.substr(0, 9) == "$verific$" || type.substr(0, 7) == "$array:" || type.substr(0, 8) == "$extern:")
2392 return;
2393
2394 if (type == "$mux" || type == "$pmux") {
2395 parameters["\\WIDTH"] = GetSize(connections_["\\Y"]);
2396 if (type == "$pmux")
2397 parameters["\\S_WIDTH"] = GetSize(connections_["\\S"]);
2398 check();
2399 return;
2400 }
2401
2402 if (type == "$lut" || type == "$sop") {
2403 parameters["\\WIDTH"] = GetSize(connections_["\\A"]);
2404 return;
2405 }
2406
2407 if (type == "$fa") {
2408 parameters["\\WIDTH"] = GetSize(connections_["\\Y"]);
2409 return;
2410 }
2411
2412 if (type == "$lcu") {
2413 parameters["\\WIDTH"] = GetSize(connections_["\\CO"]);
2414 return;
2415 }
2416
2417 bool signedness_ab = !type.in("$slice", "$concat", "$macc");
2418
2419 if (connections_.count("\\A")) {
2420 if (signedness_ab) {
2421 if (set_a_signed)
2422 parameters["\\A_SIGNED"] = true;
2423 else if (parameters.count("\\A_SIGNED") == 0)
2424 parameters["\\A_SIGNED"] = false;
2425 }
2426 parameters["\\A_WIDTH"] = GetSize(connections_["\\A"]);
2427 }
2428
2429 if (connections_.count("\\B")) {
2430 if (signedness_ab) {
2431 if (set_b_signed)
2432 parameters["\\B_SIGNED"] = true;
2433 else if (parameters.count("\\B_SIGNED") == 0)
2434 parameters["\\B_SIGNED"] = false;
2435 }
2436 parameters["\\B_WIDTH"] = GetSize(connections_["\\B"]);
2437 }
2438
2439 if (connections_.count("\\Y"))
2440 parameters["\\Y_WIDTH"] = GetSize(connections_["\\Y"]);
2441
2442 if (connections_.count("\\Q"))
2443 parameters["\\WIDTH"] = GetSize(connections_["\\Q"]);
2444
2445 check();
2446 }
2447
2448 RTLIL::SigChunk::SigChunk()
2449 {
2450 wire = NULL;
2451 width = 0;
2452 offset = 0;
2453 }
2454
2455 RTLIL::SigChunk::SigChunk(const RTLIL::Const &value)
2456 {
2457 wire = NULL;
2458 data = value.bits;
2459 width = GetSize(data);
2460 offset = 0;
2461 }
2462
2463 RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire)
2464 {
2465 log_assert(wire != nullptr);
2466 this->wire = wire;
2467 this->width = wire->width;
2468 this->offset = 0;
2469 }
2470
2471 RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire, int offset, int width)
2472 {
2473 log_assert(wire != nullptr);
2474 this->wire = wire;
2475 this->width = width;
2476 this->offset = offset;
2477 }
2478
2479 RTLIL::SigChunk::SigChunk(const std::string &str)
2480 {
2481 wire = NULL;
2482 data = RTLIL::Const(str).bits;
2483 width = GetSize(data);
2484 offset = 0;
2485 }
2486
2487 RTLIL::SigChunk::SigChunk(int val, int width)
2488 {
2489 wire = NULL;
2490 data = RTLIL::Const(val, width).bits;
2491 this->width = GetSize(data);
2492 offset = 0;
2493 }
2494
2495 RTLIL::SigChunk::SigChunk(RTLIL::State bit, int width)
2496 {
2497 wire = NULL;
2498 data = RTLIL::Const(bit, width).bits;
2499 this->width = GetSize(data);
2500 offset = 0;
2501 }
2502
2503 RTLIL::SigChunk::SigChunk(RTLIL::SigBit bit)
2504 {
2505 wire = bit.wire;
2506 offset = 0;
2507 if (wire == NULL)
2508 data = RTLIL::Const(bit.data).bits;
2509 else
2510 offset = bit.offset;
2511 width = 1;
2512 }
2513
2514 RTLIL::SigChunk RTLIL::SigChunk::extract(int offset, int length) const
2515 {
2516 RTLIL::SigChunk ret;
2517 if (wire) {
2518 ret.wire = wire;
2519 ret.offset = this->offset + offset;
2520 ret.width = length;
2521 } else {
2522 for (int i = 0; i < length; i++)
2523 ret.data.push_back(data[offset+i]);
2524 ret.width = length;
2525 }
2526 return ret;
2527 }
2528
2529 bool RTLIL::SigChunk::operator <(const RTLIL::SigChunk &other) const
2530 {
2531 if (wire && other.wire)
2532 if (wire->name != other.wire->name)
2533 return wire->name < other.wire->name;
2534
2535 if (wire != other.wire)
2536 return wire < other.wire;
2537
2538 if (offset != other.offset)
2539 return offset < other.offset;
2540
2541 if (width != other.width)
2542 return width < other.width;
2543
2544 return data < other.data;
2545 }
2546
2547 bool RTLIL::SigChunk::operator ==(const RTLIL::SigChunk &other) const
2548 {
2549 return wire == other.wire && width == other.width && offset == other.offset && data == other.data;
2550 }
2551
2552 bool RTLIL::SigChunk::operator !=(const RTLIL::SigChunk &other) const
2553 {
2554 if (*this == other)
2555 return false;
2556 return true;
2557 }
2558
2559 RTLIL::SigSpec::SigSpec()
2560 {
2561 width_ = 0;
2562 hash_ = 0;
2563 }
2564
2565 RTLIL::SigSpec::SigSpec(const RTLIL::SigSpec &other)
2566 {
2567 *this = other;
2568 }
2569
2570 RTLIL::SigSpec::SigSpec(std::initializer_list<RTLIL::SigSpec> parts)
2571 {
2572 cover("kernel.rtlil.sigspec.init.list");
2573
2574 width_ = 0;
2575 hash_ = 0;
2576
2577 std::vector<RTLIL::SigSpec> parts_vec(parts.begin(), parts.end());
2578 for (auto it = parts_vec.rbegin(); it != parts_vec.rend(); it++)
2579 append(*it);
2580 }
2581
2582 const RTLIL::SigSpec &RTLIL::SigSpec::operator=(const RTLIL::SigSpec &other)
2583 {
2584 cover("kernel.rtlil.sigspec.assign");
2585
2586 width_ = other.width_;
2587 hash_ = other.hash_;
2588 chunks_ = other.chunks_;
2589 bits_.clear();
2590
2591 if (!other.bits_.empty())
2592 {
2593 RTLIL::SigChunk *last = NULL;
2594 int last_end_offset = 0;
2595
2596 for (auto &bit : other.bits_) {
2597 if (last && bit.wire == last->wire) {
2598 if (bit.wire == NULL) {
2599 last->data.push_back(bit.data);
2600 last->width++;
2601 continue;
2602 } else if (last_end_offset == bit.offset) {
2603 last_end_offset++;
2604 last->width++;
2605 continue;
2606 }
2607 }
2608 chunks_.push_back(bit);
2609 last = &chunks_.back();
2610 last_end_offset = bit.offset + 1;
2611 }
2612
2613 check();
2614 }
2615
2616 return *this;
2617 }
2618
2619 RTLIL::SigSpec::SigSpec(const RTLIL::Const &value)
2620 {
2621 cover("kernel.rtlil.sigspec.init.const");
2622
2623 chunks_.push_back(RTLIL::SigChunk(value));
2624 width_ = chunks_.back().width;
2625 hash_ = 0;
2626 check();
2627 }
2628
2629 RTLIL::SigSpec::SigSpec(const RTLIL::SigChunk &chunk)
2630 {
2631 cover("kernel.rtlil.sigspec.init.chunk");
2632
2633 chunks_.push_back(chunk);
2634 width_ = chunks_.back().width;
2635 hash_ = 0;
2636 check();
2637 }
2638
2639 RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire)
2640 {
2641 cover("kernel.rtlil.sigspec.init.wire");
2642
2643 chunks_.push_back(RTLIL::SigChunk(wire));
2644 width_ = chunks_.back().width;
2645 hash_ = 0;
2646 check();
2647 }
2648
2649 RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire, int offset, int width)
2650 {
2651 cover("kernel.rtlil.sigspec.init.wire_part");
2652
2653 chunks_.push_back(RTLIL::SigChunk(wire, offset, width));
2654 width_ = chunks_.back().width;
2655 hash_ = 0;
2656 check();
2657 }
2658
2659 RTLIL::SigSpec::SigSpec(const std::string &str)
2660 {
2661 cover("kernel.rtlil.sigspec.init.str");
2662
2663 chunks_.push_back(RTLIL::SigChunk(str));
2664 width_ = chunks_.back().width;
2665 hash_ = 0;
2666 check();
2667 }
2668
2669 RTLIL::SigSpec::SigSpec(int val, int width)
2670 {
2671 cover("kernel.rtlil.sigspec.init.int");
2672
2673 chunks_.push_back(RTLIL::SigChunk(val, width));
2674 width_ = width;
2675 hash_ = 0;
2676 check();
2677 }
2678
2679 RTLIL::SigSpec::SigSpec(RTLIL::State bit, int width)
2680 {
2681 cover("kernel.rtlil.sigspec.init.state");
2682
2683 chunks_.push_back(RTLIL::SigChunk(bit, width));
2684 width_ = width;
2685 hash_ = 0;
2686 check();
2687 }
2688
2689 RTLIL::SigSpec::SigSpec(RTLIL::SigBit bit, int width)
2690 {
2691 cover("kernel.rtlil.sigspec.init.bit");
2692
2693 if (bit.wire == NULL)
2694 chunks_.push_back(RTLIL::SigChunk(bit.data, width));
2695 else
2696 for (int i = 0; i < width; i++)
2697 chunks_.push_back(bit);
2698 width_ = width;
2699 hash_ = 0;
2700 check();
2701 }
2702
2703 RTLIL::SigSpec::SigSpec(std::vector<RTLIL::SigChunk> chunks)
2704 {
2705 cover("kernel.rtlil.sigspec.init.stdvec_chunks");
2706
2707 width_ = 0;
2708 hash_ = 0;
2709 for (auto &c : chunks)
2710 append(c);
2711 check();
2712 }
2713
2714 RTLIL::SigSpec::SigSpec(std::vector<RTLIL::SigBit> bits)
2715 {
2716 cover("kernel.rtlil.sigspec.init.stdvec_bits");
2717
2718 width_ = 0;
2719 hash_ = 0;
2720 for (auto &bit : bits)
2721 append_bit(bit);
2722 check();
2723 }
2724
2725 RTLIL::SigSpec::SigSpec(pool<RTLIL::SigBit> bits)
2726 {
2727 cover("kernel.rtlil.sigspec.init.pool_bits");
2728
2729 width_ = 0;
2730 hash_ = 0;
2731 for (auto &bit : bits)
2732 append_bit(bit);
2733 check();
2734 }
2735
2736 RTLIL::SigSpec::SigSpec(std::set<RTLIL::SigBit> bits)
2737 {
2738 cover("kernel.rtlil.sigspec.init.stdset_bits");
2739
2740 width_ = 0;
2741 hash_ = 0;
2742 for (auto &bit : bits)
2743 append_bit(bit);
2744 check();
2745 }
2746
2747 RTLIL::SigSpec::SigSpec(bool bit)
2748 {
2749 cover("kernel.rtlil.sigspec.init.bool");
2750
2751 width_ = 0;
2752 hash_ = 0;
2753 append_bit(bit);
2754 check();
2755 }
2756
2757 void RTLIL::SigSpec::pack() const
2758 {
2759 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
2760
2761 if (that->bits_.empty())
2762 return;
2763
2764 cover("kernel.rtlil.sigspec.convert.pack");
2765 log_assert(that->chunks_.empty());
2766
2767 std::vector<RTLIL::SigBit> old_bits;
2768 old_bits.swap(that->bits_);
2769
2770 RTLIL::SigChunk *last = NULL;
2771 int last_end_offset = 0;
2772
2773 for (auto &bit : old_bits) {
2774 if (last && bit.wire == last->wire) {
2775 if (bit.wire == NULL) {
2776 last->data.push_back(bit.data);
2777 last->width++;
2778 continue;
2779 } else if (last_end_offset == bit.offset) {
2780 last_end_offset++;
2781 last->width++;
2782 continue;
2783 }
2784 }
2785 that->chunks_.push_back(bit);
2786 last = &that->chunks_.back();
2787 last_end_offset = bit.offset + 1;
2788 }
2789
2790 check();
2791 }
2792
2793 void RTLIL::SigSpec::unpack() const
2794 {
2795 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
2796
2797 if (that->chunks_.empty())
2798 return;
2799
2800 cover("kernel.rtlil.sigspec.convert.unpack");
2801 log_assert(that->bits_.empty());
2802
2803 that->bits_.reserve(that->width_);
2804 for (auto &c : that->chunks_)
2805 for (int i = 0; i < c.width; i++)
2806 that->bits_.push_back(RTLIL::SigBit(c, i));
2807
2808 that->chunks_.clear();
2809 that->hash_ = 0;
2810 }
2811
2812 void RTLIL::SigSpec::updhash() const
2813 {
2814 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
2815
2816 if (that->hash_ != 0)
2817 return;
2818
2819 cover("kernel.rtlil.sigspec.hash");
2820 that->pack();
2821
2822 that->hash_ = mkhash_init;
2823 for (auto &c : that->chunks_)
2824 if (c.wire == NULL) {
2825 for (auto &v : c.data)
2826 that->hash_ = mkhash(that->hash_, v);
2827 } else {
2828 that->hash_ = mkhash(that->hash_, c.wire->name.index_);
2829 that->hash_ = mkhash(that->hash_, c.offset);
2830 that->hash_ = mkhash(that->hash_, c.width);
2831 }
2832
2833 if (that->hash_ == 0)
2834 that->hash_ = 1;
2835 }
2836
2837 void RTLIL::SigSpec::sort()
2838 {
2839 unpack();
2840 cover("kernel.rtlil.sigspec.sort");
2841 std::sort(bits_.begin(), bits_.end());
2842 }
2843
2844 void RTLIL::SigSpec::sort_and_unify()
2845 {
2846 unpack();
2847 cover("kernel.rtlil.sigspec.sort_and_unify");
2848
2849 // A copy of the bits vector is used to prevent duplicating the logic from
2850 // SigSpec::SigSpec(std::vector<SigBit>). This incurrs an extra copy but
2851 // that isn't showing up as significant in profiles.
2852 std::vector<SigBit> unique_bits = bits_;
2853 std::sort(unique_bits.begin(), unique_bits.end());
2854 auto last = std::unique(unique_bits.begin(), unique_bits.end());
2855 unique_bits.erase(last, unique_bits.end());
2856
2857 *this = unique_bits;
2858 }
2859
2860 void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with)
2861 {
2862 replace(pattern, with, this);
2863 }
2864
2865 void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with, RTLIL::SigSpec *other) const
2866 {
2867 log_assert(other != NULL);
2868 log_assert(width_ == other->width_);
2869 log_assert(pattern.width_ == with.width_);
2870
2871 pattern.unpack();
2872 with.unpack();
2873 unpack();
2874 other->unpack();
2875
2876 for (int i = 0; i < GetSize(pattern.bits_); i++) {
2877 if (pattern.bits_[i].wire != NULL) {
2878 for (int j = 0; j < GetSize(bits_); j++) {
2879 if (bits_[j] == pattern.bits_[i]) {
2880 other->bits_[j] = with.bits_[i];
2881 }
2882 }
2883 }
2884 }
2885
2886 other->check();
2887 }
2888
2889 void RTLIL::SigSpec::replace(const dict<RTLIL::SigBit, RTLIL::SigBit> &rules)
2890 {
2891 replace(rules, this);
2892 }
2893
2894 void RTLIL::SigSpec::replace(const dict<RTLIL::SigBit, RTLIL::SigBit> &rules, RTLIL::SigSpec *other) const
2895 {
2896 cover("kernel.rtlil.sigspec.replace_dict");
2897
2898 log_assert(other != NULL);
2899 log_assert(width_ == other->width_);
2900
2901 unpack();
2902 other->unpack();
2903
2904 for (int i = 0; i < GetSize(bits_); i++) {
2905 auto it = rules.find(bits_[i]);
2906 if (it != rules.end())
2907 other->bits_[i] = it->second;
2908 }
2909
2910 other->check();
2911 }
2912
2913 void RTLIL::SigSpec::replace(const std::map<RTLIL::SigBit, RTLIL::SigBit> &rules)
2914 {
2915 replace(rules, this);
2916 }
2917
2918 void RTLIL::SigSpec::replace(const std::map<RTLIL::SigBit, RTLIL::SigBit> &rules, RTLIL::SigSpec *other) const
2919 {
2920 cover("kernel.rtlil.sigspec.replace_map");
2921
2922 log_assert(other != NULL);
2923 log_assert(width_ == other->width_);
2924
2925 unpack();
2926 other->unpack();
2927
2928 for (int i = 0; i < GetSize(bits_); i++) {
2929 auto it = rules.find(bits_[i]);
2930 if (it != rules.end())
2931 other->bits_[i] = it->second;
2932 }
2933
2934 other->check();
2935 }
2936
2937 void RTLIL::SigSpec::remove(const RTLIL::SigSpec &pattern)
2938 {
2939 remove2(pattern, NULL);
2940 }
2941
2942 void RTLIL::SigSpec::remove(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other) const
2943 {
2944 RTLIL::SigSpec tmp = *this;
2945 tmp.remove2(pattern, other);
2946 }
2947
2948 void RTLIL::SigSpec::remove2(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other)
2949 {
2950 if (other)
2951 cover("kernel.rtlil.sigspec.remove_other");
2952 else
2953 cover("kernel.rtlil.sigspec.remove");
2954
2955 unpack();
2956 if (other != NULL) {
2957 log_assert(width_ == other->width_);
2958 other->unpack();
2959 }
2960
2961 for (int i = GetSize(bits_) - 1; i >= 0; i--)
2962 {
2963 if (bits_[i].wire == NULL) continue;
2964
2965 for (auto &pattern_chunk : pattern.chunks())
2966 if (bits_[i].wire == pattern_chunk.wire &&
2967 bits_[i].offset >= pattern_chunk.offset &&
2968 bits_[i].offset < pattern_chunk.offset + pattern_chunk.width) {
2969 bits_.erase(bits_.begin() + i);
2970 width_--;
2971 if (other != NULL) {
2972 other->bits_.erase(other->bits_.begin() + i);
2973 other->width_--;
2974 }
2975 break;
2976 }
2977 }
2978
2979 check();
2980 }
2981
2982 void RTLIL::SigSpec::remove(const pool<RTLIL::SigBit> &pattern)
2983 {
2984 remove2(pattern, NULL);
2985 }
2986
2987 void RTLIL::SigSpec::remove(const pool<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other) const
2988 {
2989 RTLIL::SigSpec tmp = *this;
2990 tmp.remove2(pattern, other);
2991 }
2992
2993 void RTLIL::SigSpec::remove2(const pool<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other)
2994 {
2995 if (other)
2996 cover("kernel.rtlil.sigspec.remove_other");
2997 else
2998 cover("kernel.rtlil.sigspec.remove");
2999
3000 unpack();
3001
3002 if (other != NULL) {
3003 log_assert(width_ == other->width_);
3004 other->unpack();
3005 }
3006
3007 for (int i = GetSize(bits_) - 1; i >= 0; i--) {
3008 if (bits_[i].wire != NULL && pattern.count(bits_[i])) {
3009 bits_.erase(bits_.begin() + i);
3010 width_--;
3011 if (other != NULL) {
3012 other->bits_.erase(other->bits_.begin() + i);
3013 other->width_--;
3014 }
3015 }
3016 }
3017
3018 check();
3019 }
3020
3021 void RTLIL::SigSpec::remove2(const std::set<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other)
3022 {
3023 if (other)
3024 cover("kernel.rtlil.sigspec.remove_other");
3025 else
3026 cover("kernel.rtlil.sigspec.remove");
3027
3028 unpack();
3029
3030 if (other != NULL) {
3031 log_assert(width_ == other->width_);
3032 other->unpack();
3033 }
3034
3035 for (int i = GetSize(bits_) - 1; i >= 0; i--) {
3036 if (bits_[i].wire != NULL && pattern.count(bits_[i])) {
3037 bits_.erase(bits_.begin() + i);
3038 width_--;
3039 if (other != NULL) {
3040 other->bits_.erase(other->bits_.begin() + i);
3041 other->width_--;
3042 }
3043 }
3044 }
3045
3046 check();
3047 }
3048
3049 RTLIL::SigSpec RTLIL::SigSpec::extract(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec *other) const
3050 {
3051 if (other)
3052 cover("kernel.rtlil.sigspec.extract_other");
3053 else
3054 cover("kernel.rtlil.sigspec.extract");
3055
3056 log_assert(other == NULL || width_ == other->width_);
3057
3058 RTLIL::SigSpec ret;
3059 std::vector<RTLIL::SigBit> bits_match = to_sigbit_vector();
3060
3061 for (auto& pattern_chunk : pattern.chunks()) {
3062 if (other) {
3063 std::vector<RTLIL::SigBit> bits_other = other->to_sigbit_vector();
3064 for (int i = 0; i < width_; i++)
3065 if (bits_match[i].wire &&
3066 bits_match[i].wire == pattern_chunk.wire &&
3067 bits_match[i].offset >= pattern_chunk.offset &&
3068 bits_match[i].offset < pattern_chunk.offset + pattern_chunk.width)
3069 ret.append_bit(bits_other[i]);
3070 } else {
3071 for (int i = 0; i < width_; i++)
3072 if (bits_match[i].wire &&
3073 bits_match[i].wire == pattern_chunk.wire &&
3074 bits_match[i].offset >= pattern_chunk.offset &&
3075 bits_match[i].offset < pattern_chunk.offset + pattern_chunk.width)
3076 ret.append_bit(bits_match[i]);
3077 }
3078 }
3079
3080 ret.check();
3081 return ret;
3082 }
3083
3084 RTLIL::SigSpec RTLIL::SigSpec::extract(const pool<RTLIL::SigBit> &pattern, const RTLIL::SigSpec *other) const
3085 {
3086 if (other)
3087 cover("kernel.rtlil.sigspec.extract_other");
3088 else
3089 cover("kernel.rtlil.sigspec.extract");
3090
3091 log_assert(other == NULL || width_ == other->width_);
3092
3093 std::vector<RTLIL::SigBit> bits_match = to_sigbit_vector();
3094 RTLIL::SigSpec ret;
3095
3096 if (other) {
3097 std::vector<RTLIL::SigBit> bits_other = other->to_sigbit_vector();
3098 for (int i = 0; i < width_; i++)
3099 if (bits_match[i].wire && pattern.count(bits_match[i]))
3100 ret.append_bit(bits_other[i]);
3101 } else {
3102 for (int i = 0; i < width_; i++)
3103 if (bits_match[i].wire && pattern.count(bits_match[i]))
3104 ret.append_bit(bits_match[i]);
3105 }
3106
3107 ret.check();
3108 return ret;
3109 }
3110
3111 void RTLIL::SigSpec::replace(int offset, const RTLIL::SigSpec &with)
3112 {
3113 cover("kernel.rtlil.sigspec.replace_pos");
3114
3115 unpack();
3116 with.unpack();
3117
3118 log_assert(offset >= 0);
3119 log_assert(with.width_ >= 0);
3120 log_assert(offset+with.width_ <= width_);
3121
3122 for (int i = 0; i < with.width_; i++)
3123 bits_.at(offset + i) = with.bits_.at(i);
3124
3125 check();
3126 }
3127
3128 void RTLIL::SigSpec::remove_const()
3129 {
3130 if (packed())
3131 {
3132 cover("kernel.rtlil.sigspec.remove_const.packed");
3133
3134 std::vector<RTLIL::SigChunk> new_chunks;
3135 new_chunks.reserve(GetSize(chunks_));
3136
3137 width_ = 0;
3138 for (auto &chunk : chunks_)
3139 if (chunk.wire != NULL) {
3140 new_chunks.push_back(chunk);
3141 width_ += chunk.width;
3142 }
3143
3144 chunks_.swap(new_chunks);
3145 }
3146 else
3147 {
3148 cover("kernel.rtlil.sigspec.remove_const.unpacked");
3149
3150 std::vector<RTLIL::SigBit> new_bits;
3151 new_bits.reserve(width_);
3152
3153 for (auto &bit : bits_)
3154 if (bit.wire != NULL)
3155 new_bits.push_back(bit);
3156
3157 bits_.swap(new_bits);
3158 width_ = bits_.size();
3159 }
3160
3161 check();
3162 }
3163
3164 void RTLIL::SigSpec::remove(int offset, int length)
3165 {
3166 cover("kernel.rtlil.sigspec.remove_pos");
3167
3168 unpack();
3169
3170 log_assert(offset >= 0);
3171 log_assert(length >= 0);
3172 log_assert(offset + length <= width_);
3173
3174 bits_.erase(bits_.begin() + offset, bits_.begin() + offset + length);
3175 width_ = bits_.size();
3176
3177 check();
3178 }
3179
3180 RTLIL::SigSpec RTLIL::SigSpec::extract(int offset, int length) const
3181 {
3182 unpack();
3183 cover("kernel.rtlil.sigspec.extract_pos");
3184 return std::vector<RTLIL::SigBit>(bits_.begin() + offset, bits_.begin() + offset + length);
3185 }
3186
3187 void RTLIL::SigSpec::append(const RTLIL::SigSpec &signal)
3188 {
3189 if (signal.width_ == 0)
3190 return;
3191
3192 if (width_ == 0) {
3193 *this = signal;
3194 return;
3195 }
3196
3197 cover("kernel.rtlil.sigspec.append");
3198
3199 if (packed() != signal.packed()) {
3200 pack();
3201 signal.pack();
3202 }
3203
3204 if (packed())
3205 for (auto &other_c : signal.chunks_)
3206 {
3207 auto &my_last_c = chunks_.back();
3208 if (my_last_c.wire == NULL && other_c.wire == NULL) {
3209 auto &this_data = my_last_c.data;
3210 auto &other_data = other_c.data;
3211 this_data.insert(this_data.end(), other_data.begin(), other_data.end());
3212 my_last_c.width += other_c.width;
3213 } else
3214 if (my_last_c.wire == other_c.wire && my_last_c.offset + my_last_c.width == other_c.offset) {
3215 my_last_c.width += other_c.width;
3216 } else
3217 chunks_.push_back(other_c);
3218 }
3219 else
3220 bits_.insert(bits_.end(), signal.bits_.begin(), signal.bits_.end());
3221
3222 width_ += signal.width_;
3223 check();
3224 }
3225
3226 void RTLIL::SigSpec::append_bit(const RTLIL::SigBit &bit)
3227 {
3228 if (packed())
3229 {
3230 cover("kernel.rtlil.sigspec.append_bit.packed");
3231
3232 if (chunks_.size() == 0)
3233 chunks_.push_back(bit);
3234 else
3235 if (bit.wire == NULL)
3236 if (chunks_.back().wire == NULL) {
3237 chunks_.back().data.push_back(bit.data);
3238 chunks_.back().width++;
3239 } else
3240 chunks_.push_back(bit);
3241 else
3242 if (chunks_.back().wire == bit.wire && chunks_.back().offset + chunks_.back().width == bit.offset)
3243 chunks_.back().width++;
3244 else
3245 chunks_.push_back(bit);
3246 }
3247 else
3248 {
3249 cover("kernel.rtlil.sigspec.append_bit.unpacked");
3250 bits_.push_back(bit);
3251 }
3252
3253 width_++;
3254 check();
3255 }
3256
3257 void RTLIL::SigSpec::extend_u0(int width, bool is_signed)
3258 {
3259 cover("kernel.rtlil.sigspec.extend_u0");
3260
3261 pack();
3262
3263 if (width_ > width)
3264 remove(width, width_ - width);
3265
3266 if (width_ < width) {
3267 RTLIL::SigBit padding = width_ > 0 ? (*this)[width_ - 1] : RTLIL::State::Sx;
3268 if (!is_signed)
3269 padding = RTLIL::State::S0;
3270 while (width_ < width)
3271 append(padding);
3272 }
3273
3274 }
3275
3276 RTLIL::SigSpec RTLIL::SigSpec::repeat(int num) const
3277 {
3278 cover("kernel.rtlil.sigspec.repeat");
3279
3280 RTLIL::SigSpec sig;
3281 for (int i = 0; i < num; i++)
3282 sig.append(*this);
3283 return sig;
3284 }
3285
3286 #ifndef NDEBUG
3287 void RTLIL::SigSpec::check() const
3288 {
3289 if (width_ > 64)
3290 {
3291 cover("kernel.rtlil.sigspec.check.skip");
3292 }
3293 else if (packed())
3294 {
3295 cover("kernel.rtlil.sigspec.check.packed");
3296
3297 int w = 0;
3298 for (size_t i = 0; i < chunks_.size(); i++) {
3299 const RTLIL::SigChunk chunk = chunks_[i];
3300 if (chunk.wire == NULL) {
3301 if (i > 0)
3302 log_assert(chunks_[i-1].wire != NULL);
3303 log_assert(chunk.offset == 0);
3304 log_assert(chunk.data.size() == (size_t)chunk.width);
3305 } else {
3306 if (i > 0 && chunks_[i-1].wire == chunk.wire)
3307 log_assert(chunk.offset != chunks_[i-1].offset + chunks_[i-1].width);
3308 log_assert(chunk.offset >= 0);
3309 log_assert(chunk.width >= 0);
3310 log_assert(chunk.offset + chunk.width <= chunk.wire->width);
3311 log_assert(chunk.data.size() == 0);
3312 }
3313 w += chunk.width;
3314 }
3315 log_assert(w == width_);
3316 log_assert(bits_.empty());
3317 }
3318 else
3319 {
3320 cover("kernel.rtlil.sigspec.check.unpacked");
3321
3322 log_assert(width_ == GetSize(bits_));
3323 log_assert(chunks_.empty());
3324 }
3325 }
3326 #endif
3327
3328 bool RTLIL::SigSpec::operator <(const RTLIL::SigSpec &other) const
3329 {
3330 cover("kernel.rtlil.sigspec.comp_lt");
3331
3332 if (this == &other)
3333 return false;
3334
3335 if (width_ != other.width_)
3336 return width_ < other.width_;
3337
3338 pack();
3339 other.pack();
3340
3341 if (chunks_.size() != other.chunks_.size())
3342 return chunks_.size() < other.chunks_.size();
3343
3344 updhash();
3345 other.updhash();
3346
3347 if (hash_ != other.hash_)
3348 return hash_ < other.hash_;
3349
3350 for (size_t i = 0; i < chunks_.size(); i++)
3351 if (chunks_[i] != other.chunks_[i]) {
3352 cover("kernel.rtlil.sigspec.comp_lt.hash_collision");
3353 return chunks_[i] < other.chunks_[i];
3354 }
3355
3356 cover("kernel.rtlil.sigspec.comp_lt.equal");
3357 return false;
3358 }
3359
3360 bool RTLIL::SigSpec::operator ==(const RTLIL::SigSpec &other) const
3361 {
3362 cover("kernel.rtlil.sigspec.comp_eq");
3363
3364 if (this == &other)
3365 return true;
3366
3367 if (width_ != other.width_)
3368 return false;
3369
3370 pack();
3371 other.pack();
3372
3373 if (chunks_.size() != chunks_.size())
3374 return false;
3375
3376 updhash();
3377 other.updhash();
3378
3379 if (hash_ != other.hash_)
3380 return false;
3381
3382 for (size_t i = 0; i < chunks_.size(); i++)
3383 if (chunks_[i] != other.chunks_[i]) {
3384 cover("kernel.rtlil.sigspec.comp_eq.hash_collision");
3385 return false;
3386 }
3387
3388 cover("kernel.rtlil.sigspec.comp_eq.equal");
3389 return true;
3390 }
3391
3392 bool RTLIL::SigSpec::is_wire() const
3393 {
3394 cover("kernel.rtlil.sigspec.is_wire");
3395
3396 pack();
3397 return GetSize(chunks_) == 1 && chunks_[0].wire && chunks_[0].wire->width == width_;
3398 }
3399
3400 bool RTLIL::SigSpec::is_chunk() const
3401 {
3402 cover("kernel.rtlil.sigspec.is_chunk");
3403
3404 pack();
3405 return GetSize(chunks_) == 1;
3406 }
3407
3408 bool RTLIL::SigSpec::is_fully_const() const
3409 {
3410 cover("kernel.rtlil.sigspec.is_fully_const");
3411
3412 pack();
3413 for (auto it = chunks_.begin(); it != chunks_.end(); it++)
3414 if (it->width > 0 && it->wire != NULL)
3415 return false;
3416 return true;
3417 }
3418
3419 bool RTLIL::SigSpec::is_fully_zero() const
3420 {
3421 cover("kernel.rtlil.sigspec.is_fully_zero");
3422
3423 pack();
3424 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
3425 if (it->width > 0 && it->wire != NULL)
3426 return false;
3427 for (size_t i = 0; i < it->data.size(); i++)
3428 if (it->data[i] != RTLIL::State::S0)
3429 return false;
3430 }
3431 return true;
3432 }
3433
3434 bool RTLIL::SigSpec::is_fully_ones() const
3435 {
3436 cover("kernel.rtlil.sigspec.is_fully_ones");
3437
3438 pack();
3439 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
3440 if (it->width > 0 && it->wire != NULL)
3441 return false;
3442 for (size_t i = 0; i < it->data.size(); i++)
3443 if (it->data[i] != RTLIL::State::S1)
3444 return false;
3445 }
3446 return true;
3447 }
3448
3449 bool RTLIL::SigSpec::is_fully_def() const
3450 {
3451 cover("kernel.rtlil.sigspec.is_fully_def");
3452
3453 pack();
3454 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
3455 if (it->width > 0 && it->wire != NULL)
3456 return false;
3457 for (size_t i = 0; i < it->data.size(); i++)
3458 if (it->data[i] != RTLIL::State::S0 && it->data[i] != RTLIL::State::S1)
3459 return false;
3460 }
3461 return true;
3462 }
3463
3464 bool RTLIL::SigSpec::is_fully_undef() const
3465 {
3466 cover("kernel.rtlil.sigspec.is_fully_undef");
3467
3468 pack();
3469 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
3470 if (it->width > 0 && it->wire != NULL)
3471 return false;
3472 for (size_t i = 0; i < it->data.size(); i++)
3473 if (it->data[i] != RTLIL::State::Sx && it->data[i] != RTLIL::State::Sz)
3474 return false;
3475 }
3476 return true;
3477 }
3478
3479 bool RTLIL::SigSpec::has_const() const
3480 {
3481 cover("kernel.rtlil.sigspec.has_const");
3482
3483 pack();
3484 for (auto it = chunks_.begin(); it != chunks_.end(); it++)
3485 if (it->width > 0 && it->wire == NULL)
3486 return true;
3487 return false;
3488 }
3489
3490 bool RTLIL::SigSpec::has_marked_bits() const
3491 {
3492 cover("kernel.rtlil.sigspec.has_marked_bits");
3493
3494 pack();
3495 for (auto it = chunks_.begin(); it != chunks_.end(); it++)
3496 if (it->width > 0 && it->wire == NULL) {
3497 for (size_t i = 0; i < it->data.size(); i++)
3498 if (it->data[i] == RTLIL::State::Sm)
3499 return true;
3500 }
3501 return false;
3502 }
3503
3504 bool RTLIL::SigSpec::as_bool() const
3505 {
3506 cover("kernel.rtlil.sigspec.as_bool");
3507
3508 pack();
3509 log_assert(is_fully_const() && GetSize(chunks_) <= 1);
3510 if (width_)
3511 return RTLIL::Const(chunks_[0].data).as_bool();
3512 return false;
3513 }
3514
3515 int RTLIL::SigSpec::as_int(bool is_signed) const
3516 {
3517 cover("kernel.rtlil.sigspec.as_int");
3518
3519 pack();
3520 log_assert(is_fully_const() && GetSize(chunks_) <= 1);
3521 if (width_)
3522 return RTLIL::Const(chunks_[0].data).as_int(is_signed);
3523 return 0;
3524 }
3525
3526 std::string RTLIL::SigSpec::as_string() const
3527 {
3528 cover("kernel.rtlil.sigspec.as_string");
3529
3530 pack();
3531 std::string str;
3532 for (size_t i = chunks_.size(); i > 0; i--) {
3533 const RTLIL::SigChunk &chunk = chunks_[i-1];
3534 if (chunk.wire != NULL)
3535 for (int j = 0; j < chunk.width; j++)
3536 str += "?";
3537 else
3538 str += RTLIL::Const(chunk.data).as_string();
3539 }
3540 return str;
3541 }
3542
3543 RTLIL::Const RTLIL::SigSpec::as_const() const
3544 {
3545 cover("kernel.rtlil.sigspec.as_const");
3546
3547 pack();
3548 log_assert(is_fully_const() && GetSize(chunks_) <= 1);
3549 if (width_)
3550 return chunks_[0].data;
3551 return RTLIL::Const();
3552 }
3553
3554 RTLIL::Wire *RTLIL::SigSpec::as_wire() const
3555 {
3556 cover("kernel.rtlil.sigspec.as_wire");
3557
3558 pack();
3559 log_assert(is_wire());
3560 return chunks_[0].wire;
3561 }
3562
3563 RTLIL::SigChunk RTLIL::SigSpec::as_chunk() const
3564 {
3565 cover("kernel.rtlil.sigspec.as_chunk");
3566
3567 pack();
3568 log_assert(is_chunk());
3569 return chunks_[0];
3570 }
3571
3572 RTLIL::SigBit RTLIL::SigSpec::as_bit() const
3573 {
3574 cover("kernel.rtlil.sigspec.as_bit");
3575
3576 log_assert(width_ == 1);
3577 if (packed())
3578 return RTLIL::SigBit(*chunks_.begin());
3579 else
3580 return bits_[0];
3581 }
3582
3583 bool RTLIL::SigSpec::match(std::string pattern) const
3584 {
3585 cover("kernel.rtlil.sigspec.match");
3586
3587 pack();
3588 std::string str = as_string();
3589 log_assert(pattern.size() == str.size());
3590
3591 for (size_t i = 0; i < pattern.size(); i++) {
3592 if (pattern[i] == ' ')
3593 continue;
3594 if (pattern[i] == '*') {
3595 if (str[i] != 'z' && str[i] != 'x')
3596 return false;
3597 continue;
3598 }
3599 if (pattern[i] != str[i])
3600 return false;
3601 }
3602
3603 return true;
3604 }
3605
3606 std::set<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_set() const
3607 {
3608 cover("kernel.rtlil.sigspec.to_sigbit_set");
3609
3610 pack();
3611 std::set<RTLIL::SigBit> sigbits;
3612 for (auto &c : chunks_)
3613 for (int i = 0; i < c.width; i++)
3614 sigbits.insert(RTLIL::SigBit(c, i));
3615 return sigbits;
3616 }
3617
3618 pool<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_pool() const
3619 {
3620 cover("kernel.rtlil.sigspec.to_sigbit_pool");
3621
3622 pack();
3623 pool<RTLIL::SigBit> sigbits;
3624 for (auto &c : chunks_)
3625 for (int i = 0; i < c.width; i++)
3626 sigbits.insert(RTLIL::SigBit(c, i));
3627 return sigbits;
3628 }
3629
3630 std::vector<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_vector() const
3631 {
3632 cover("kernel.rtlil.sigspec.to_sigbit_vector");
3633
3634 unpack();
3635 return bits_;
3636 }
3637
3638 std::map<RTLIL::SigBit, RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_map(const RTLIL::SigSpec &other) const
3639 {
3640 cover("kernel.rtlil.sigspec.to_sigbit_map");
3641
3642 unpack();
3643 other.unpack();
3644
3645 log_assert(width_ == other.width_);
3646
3647 std::map<RTLIL::SigBit, RTLIL::SigBit> new_map;
3648 for (int i = 0; i < width_; i++)
3649 new_map[bits_[i]] = other.bits_[i];
3650
3651 return new_map;
3652 }
3653
3654 dict<RTLIL::SigBit, RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_dict(const RTLIL::SigSpec &other) const
3655 {
3656 cover("kernel.rtlil.sigspec.to_sigbit_dict");
3657
3658 unpack();
3659 other.unpack();
3660
3661 log_assert(width_ == other.width_);
3662
3663 dict<RTLIL::SigBit, RTLIL::SigBit> new_map;
3664 for (int i = 0; i < width_; i++)
3665 new_map[bits_[i]] = other.bits_[i];
3666
3667 return new_map;
3668 }
3669
3670 static void sigspec_parse_split(std::vector<std::string> &tokens, const std::string &text, char sep)
3671 {
3672 size_t start = 0, end = 0;
3673 while ((end = text.find(sep, start)) != std::string::npos) {
3674 tokens.push_back(text.substr(start, end - start));
3675 start = end + 1;
3676 }
3677 tokens.push_back(text.substr(start));
3678 }
3679
3680 static int sigspec_parse_get_dummy_line_num()
3681 {
3682 return 0;
3683 }
3684
3685 bool RTLIL::SigSpec::parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str)
3686 {
3687 cover("kernel.rtlil.sigspec.parse");
3688
3689 AST::current_filename = "input";
3690 AST::use_internal_line_num();
3691 AST::set_line_num(0);
3692
3693 std::vector<std::string> tokens;
3694 sigspec_parse_split(tokens, str, ',');
3695
3696 sig = RTLIL::SigSpec();
3697 for (int tokidx = int(tokens.size())-1; tokidx >= 0; tokidx--)
3698 {
3699 std::string netname = tokens[tokidx];
3700 std::string indices;
3701
3702 if (netname.size() == 0)
3703 continue;
3704
3705 if (('0' <= netname[0] && netname[0] <= '9') || netname[0] == '\'') {
3706 cover("kernel.rtlil.sigspec.parse.const");
3707 AST::get_line_num = sigspec_parse_get_dummy_line_num;
3708 AST::AstNode *ast = VERILOG_FRONTEND::const2ast(netname);
3709 if (ast == NULL)
3710 return false;
3711 sig.append(RTLIL::Const(ast->bits));
3712 delete ast;
3713 continue;
3714 }
3715
3716 if (module == NULL)
3717 return false;
3718
3719 cover("kernel.rtlil.sigspec.parse.net");
3720
3721 if (netname[0] != '$' && netname[0] != '\\')
3722 netname = "\\" + netname;
3723
3724 if (module->wires_.count(netname) == 0) {
3725 size_t indices_pos = netname.size()-1;
3726 if (indices_pos > 2 && netname[indices_pos] == ']')
3727 {
3728 indices_pos--;
3729 while (indices_pos > 0 && ('0' <= netname[indices_pos] && netname[indices_pos] <= '9')) indices_pos--;
3730 if (indices_pos > 0 && netname[indices_pos] == ':') {
3731 indices_pos--;
3732 while (indices_pos > 0 && ('0' <= netname[indices_pos] && netname[indices_pos] <= '9')) indices_pos--;
3733 }
3734 if (indices_pos > 0 && netname[indices_pos] == '[') {
3735 indices = netname.substr(indices_pos);
3736 netname = netname.substr(0, indices_pos);
3737 }
3738 }
3739 }
3740
3741 if (module->wires_.count(netname) == 0)
3742 return false;
3743
3744 RTLIL::Wire *wire = module->wires_.at(netname);
3745 if (!indices.empty()) {
3746 std::vector<std::string> index_tokens;
3747 sigspec_parse_split(index_tokens, indices.substr(1, indices.size()-2), ':');
3748 if (index_tokens.size() == 1) {
3749 cover("kernel.rtlil.sigspec.parse.bit_sel");
3750 int a = atoi(index_tokens.at(0).c_str());
3751 if (a < 0 || a >= wire->width)
3752 return false;
3753 sig.append(RTLIL::SigSpec(wire, a));
3754 } else {
3755 cover("kernel.rtlil.sigspec.parse.part_sel");
3756 int a = atoi(index_tokens.at(0).c_str());
3757 int b = atoi(index_tokens.at(1).c_str());
3758 if (a > b) {
3759 int tmp = a;
3760 a = b, b = tmp;
3761 }
3762 if (a < 0 || a >= wire->width)
3763 return false;
3764 if (b < 0 || b >= wire->width)
3765 return false;
3766 sig.append(RTLIL::SigSpec(wire, a, b-a+1));
3767 }
3768 } else
3769 sig.append(wire);
3770 }
3771
3772 return true;
3773 }
3774
3775 bool RTLIL::SigSpec::parse_sel(RTLIL::SigSpec &sig, RTLIL::Design *design, RTLIL::Module *module, std::string str)
3776 {
3777 if (str.empty() || str[0] != '@')
3778 return parse(sig, module, str);
3779
3780 cover("kernel.rtlil.sigspec.parse.sel");
3781
3782 str = RTLIL::escape_id(str.substr(1));
3783 if (design->selection_vars.count(str) == 0)
3784 return false;
3785
3786 sig = RTLIL::SigSpec();
3787 RTLIL::Selection &sel = design->selection_vars.at(str);
3788 for (auto &it : module->wires_)
3789 if (sel.selected_member(module->name, it.first))
3790 sig.append(it.second);
3791
3792 return true;
3793 }
3794
3795 bool RTLIL::SigSpec::parse_rhs(const RTLIL::SigSpec &lhs, RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str)
3796 {
3797 if (str == "0") {
3798 cover("kernel.rtlil.sigspec.parse.rhs_zeros");
3799 sig = RTLIL::SigSpec(RTLIL::State::S0, lhs.width_);
3800 return true;
3801 }
3802
3803 if (str == "~0") {
3804 cover("kernel.rtlil.sigspec.parse.rhs_ones");
3805 sig = RTLIL::SigSpec(RTLIL::State::S1, lhs.width_);
3806 return true;
3807 }
3808
3809 if (lhs.chunks_.size() == 1) {
3810 char *p = (char*)str.c_str(), *endptr;
3811 long int val = strtol(p, &endptr, 10);
3812 if (endptr && endptr != p && *endptr == 0) {
3813 sig = RTLIL::SigSpec(val, lhs.width_);
3814 cover("kernel.rtlil.sigspec.parse.rhs_dec");
3815 return true;
3816 }
3817 }
3818
3819 return parse(sig, module, str);
3820 }
3821
3822 RTLIL::CaseRule::~CaseRule()
3823 {
3824 for (auto it = switches.begin(); it != switches.end(); it++)
3825 delete *it;
3826 }
3827
3828 bool RTLIL::CaseRule::empty() const
3829 {
3830 return actions.empty() && switches.empty();
3831 }
3832
3833 RTLIL::CaseRule *RTLIL::CaseRule::clone() const
3834 {
3835 RTLIL::CaseRule *new_caserule = new RTLIL::CaseRule;
3836 new_caserule->compare = compare;
3837 new_caserule->actions = actions;
3838 for (auto &it : switches)
3839 new_caserule->switches.push_back(it->clone());
3840 return new_caserule;
3841 }
3842
3843 RTLIL::SwitchRule::~SwitchRule()
3844 {
3845 for (auto it = cases.begin(); it != cases.end(); it++)
3846 delete *it;
3847 }
3848
3849 bool RTLIL::SwitchRule::empty() const
3850 {
3851 return cases.empty();
3852 }
3853
3854 RTLIL::SwitchRule *RTLIL::SwitchRule::clone() const
3855 {
3856 RTLIL::SwitchRule *new_switchrule = new RTLIL::SwitchRule;
3857 new_switchrule->signal = signal;
3858 new_switchrule->attributes = attributes;
3859 for (auto &it : cases)
3860 new_switchrule->cases.push_back(it->clone());
3861 return new_switchrule;
3862
3863 }
3864
3865 RTLIL::SyncRule *RTLIL::SyncRule::clone() const
3866 {
3867 RTLIL::SyncRule *new_syncrule = new RTLIL::SyncRule;
3868 new_syncrule->type = type;
3869 new_syncrule->signal = signal;
3870 new_syncrule->actions = actions;
3871 return new_syncrule;
3872 }
3873
3874 RTLIL::Process::~Process()
3875 {
3876 for (auto it = syncs.begin(); it != syncs.end(); it++)
3877 delete *it;
3878 }
3879
3880 RTLIL::Process *RTLIL::Process::clone() const
3881 {
3882 RTLIL::Process *new_proc = new RTLIL::Process;
3883
3884 new_proc->name = name;
3885 new_proc->attributes = attributes;
3886
3887 RTLIL::CaseRule *rc_ptr = root_case.clone();
3888 new_proc->root_case = *rc_ptr;
3889 rc_ptr->switches.clear();
3890 delete rc_ptr;
3891
3892 for (auto &it : syncs)
3893 new_proc->syncs.push_back(it->clone());
3894
3895 return new_proc;
3896 }
3897
3898 YOSYS_NAMESPACE_END
3899