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Merge pull request #1765 from YosysHQ/claire/btor_info
[yosys.git] / kernel / rtlil.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 #include "kernel/yosys.h"
21 #include "kernel/macc.h"
22 #include "kernel/celltypes.h"
23 #include "frontends/verilog/verilog_frontend.h"
24 #include "frontends/verilog/preproc.h"
25 #include "backends/ilang/ilang_backend.h"
26
27 #include <string.h>
28 #include <algorithm>
29
30 YOSYS_NAMESPACE_BEGIN
31
32 RTLIL::IdString::destruct_guard_t RTLIL::IdString::destruct_guard;
33 std::vector<char*> RTLIL::IdString::global_id_storage_;
34 dict<char*, int, hash_cstr_ops> RTLIL::IdString::global_id_index_;
35 #ifndef YOSYS_NO_IDS_REFCNT
36 std::vector<int> RTLIL::IdString::global_refcount_storage_;
37 std::vector<int> RTLIL::IdString::global_free_idx_list_;
38 #endif
39 #ifdef YOSYS_USE_STICKY_IDS
40 int RTLIL::IdString::last_created_idx_[8];
41 int RTLIL::IdString::last_created_idx_ptr_;
42 #endif
43
44 IdString RTLIL::ID::A;
45 IdString RTLIL::ID::B;
46 IdString RTLIL::ID::Y;
47 IdString RTLIL::ID::keep;
48 IdString RTLIL::ID::whitebox;
49 IdString RTLIL::ID::blackbox;
50 dict<std::string, std::string> RTLIL::constpad;
51
52 RTLIL::Const::Const()
53 {
54 flags = RTLIL::CONST_FLAG_NONE;
55 }
56
57 RTLIL::Const::Const(std::string str)
58 {
59 flags = RTLIL::CONST_FLAG_STRING;
60 for (int i = str.size()-1; i >= 0; i--) {
61 unsigned char ch = str[i];
62 for (int j = 0; j < 8; j++) {
63 bits.push_back((ch & 1) != 0 ? State::S1 : State::S0);
64 ch = ch >> 1;
65 }
66 }
67 }
68
69 RTLIL::Const::Const(int val, int width)
70 {
71 flags = RTLIL::CONST_FLAG_NONE;
72 for (int i = 0; i < width; i++) {
73 bits.push_back((val & 1) != 0 ? State::S1 : State::S0);
74 val = val >> 1;
75 }
76 }
77
78 RTLIL::Const::Const(RTLIL::State bit, int width)
79 {
80 flags = RTLIL::CONST_FLAG_NONE;
81 for (int i = 0; i < width; i++)
82 bits.push_back(bit);
83 }
84
85 RTLIL::Const::Const(const std::vector<bool> &bits)
86 {
87 flags = RTLIL::CONST_FLAG_NONE;
88 for (auto b : bits)
89 this->bits.push_back(b ? State::S1 : State::S0);
90 }
91
92 RTLIL::Const::Const(const RTLIL::Const &c)
93 {
94 flags = c.flags;
95 for (auto b : c.bits)
96 this->bits.push_back(b);
97 }
98
99 bool RTLIL::Const::operator <(const RTLIL::Const &other) const
100 {
101 if (bits.size() != other.bits.size())
102 return bits.size() < other.bits.size();
103 for (size_t i = 0; i < bits.size(); i++)
104 if (bits[i] != other.bits[i])
105 return bits[i] < other.bits[i];
106 return false;
107 }
108
109 bool RTLIL::Const::operator ==(const RTLIL::Const &other) const
110 {
111 return bits == other.bits;
112 }
113
114 bool RTLIL::Const::operator !=(const RTLIL::Const &other) const
115 {
116 return bits != other.bits;
117 }
118
119 bool RTLIL::Const::as_bool() const
120 {
121 for (size_t i = 0; i < bits.size(); i++)
122 if (bits[i] == State::S1)
123 return true;
124 return false;
125 }
126
127 int RTLIL::Const::as_int(bool is_signed) const
128 {
129 int32_t ret = 0;
130 for (size_t i = 0; i < bits.size() && i < 32; i++)
131 if (bits[i] == State::S1)
132 ret |= 1 << i;
133 if (is_signed && bits.back() == State::S1)
134 for (size_t i = bits.size(); i < 32; i++)
135 ret |= 1 << i;
136 return ret;
137 }
138
139 std::string RTLIL::Const::as_string() const
140 {
141 std::string ret;
142 for (size_t i = bits.size(); i > 0; i--)
143 switch (bits[i-1]) {
144 case S0: ret += "0"; break;
145 case S1: ret += "1"; break;
146 case Sx: ret += "x"; break;
147 case Sz: ret += "z"; break;
148 case Sa: ret += "-"; break;
149 case Sm: ret += "m"; break;
150 }
151 return ret;
152 }
153
154 RTLIL::Const RTLIL::Const::from_string(std::string str)
155 {
156 Const c;
157 for (auto it = str.rbegin(); it != str.rend(); it++)
158 switch (*it) {
159 case '0': c.bits.push_back(State::S0); break;
160 case '1': c.bits.push_back(State::S1); break;
161 case 'x': c.bits.push_back(State::Sx); break;
162 case 'z': c.bits.push_back(State::Sz); break;
163 case 'm': c.bits.push_back(State::Sm); break;
164 default: c.bits.push_back(State::Sa);
165 }
166 return c;
167 }
168
169 std::string RTLIL::Const::decode_string() const
170 {
171 std::string string;
172 std::vector<char> string_chars;
173 for (int i = 0; i < int (bits.size()); i += 8) {
174 char ch = 0;
175 for (int j = 0; j < 8 && i + j < int (bits.size()); j++)
176 if (bits[i + j] == RTLIL::State::S1)
177 ch |= 1 << j;
178 if (ch != 0)
179 string_chars.push_back(ch);
180 }
181 for (int i = int (string_chars.size()) - 1; i >= 0; i--)
182 string += string_chars[i];
183 return string;
184 }
185
186 bool RTLIL::Const::is_fully_zero() const
187 {
188 cover("kernel.rtlil.const.is_fully_zero");
189
190 for (auto bit : bits)
191 if (bit != RTLIL::State::S0)
192 return false;
193
194 return true;
195 }
196
197 bool RTLIL::Const::is_fully_ones() const
198 {
199 cover("kernel.rtlil.const.is_fully_ones");
200
201 for (auto bit : bits)
202 if (bit != RTLIL::State::S1)
203 return false;
204
205 return true;
206 }
207
208 bool RTLIL::Const::is_fully_def() const
209 {
210 cover("kernel.rtlil.const.is_fully_def");
211
212 for (auto bit : bits)
213 if (bit != RTLIL::State::S0 && bit != RTLIL::State::S1)
214 return false;
215
216 return true;
217 }
218
219 bool RTLIL::Const::is_fully_undef() const
220 {
221 cover("kernel.rtlil.const.is_fully_undef");
222
223 for (auto bit : bits)
224 if (bit != RTLIL::State::Sx && bit != RTLIL::State::Sz)
225 return false;
226
227 return true;
228 }
229
230 void RTLIL::AttrObject::set_bool_attribute(RTLIL::IdString id, bool value)
231 {
232 if (value)
233 attributes[id] = RTLIL::Const(1);
234 else {
235 const auto it = attributes.find(id);
236 if (it != attributes.end())
237 attributes.erase(it);
238 }
239 }
240
241 bool RTLIL::AttrObject::get_bool_attribute(RTLIL::IdString id) const
242 {
243 const auto it = attributes.find(id);
244 if (it == attributes.end())
245 return false;
246 return it->second.as_bool();
247 }
248
249 void RTLIL::AttrObject::set_strpool_attribute(RTLIL::IdString id, const pool<string> &data)
250 {
251 string attrval;
252 for (auto &s : data) {
253 if (!attrval.empty())
254 attrval += "|";
255 attrval += s;
256 }
257 attributes[id] = RTLIL::Const(attrval);
258 }
259
260 void RTLIL::AttrObject::add_strpool_attribute(RTLIL::IdString id, const pool<string> &data)
261 {
262 pool<string> union_data = get_strpool_attribute(id);
263 union_data.insert(data.begin(), data.end());
264 if (!union_data.empty())
265 set_strpool_attribute(id, union_data);
266 }
267
268 pool<string> RTLIL::AttrObject::get_strpool_attribute(RTLIL::IdString id) const
269 {
270 pool<string> data;
271 if (attributes.count(id) != 0)
272 for (auto s : split_tokens(attributes.at(id).decode_string(), "|"))
273 data.insert(s);
274 return data;
275 }
276
277 void RTLIL::AttrObject::set_src_attribute(const std::string &src)
278 {
279 if (src.empty())
280 attributes.erase(ID(src));
281 else
282 attributes[ID(src)] = src;
283 }
284
285 std::string RTLIL::AttrObject::get_src_attribute() const
286 {
287 std::string src;
288 if (attributes.count(ID(src)))
289 src = attributes.at(ID(src)).decode_string();
290 return src;
291 }
292
293 bool RTLIL::Selection::selected_module(RTLIL::IdString mod_name) const
294 {
295 if (full_selection)
296 return true;
297 if (selected_modules.count(mod_name) > 0)
298 return true;
299 if (selected_members.count(mod_name) > 0)
300 return true;
301 return false;
302 }
303
304 bool RTLIL::Selection::selected_whole_module(RTLIL::IdString mod_name) const
305 {
306 if (full_selection)
307 return true;
308 if (selected_modules.count(mod_name) > 0)
309 return true;
310 return false;
311 }
312
313 bool RTLIL::Selection::selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const
314 {
315 if (full_selection)
316 return true;
317 if (selected_modules.count(mod_name) > 0)
318 return true;
319 if (selected_members.count(mod_name) > 0)
320 if (selected_members.at(mod_name).count(memb_name) > 0)
321 return true;
322 return false;
323 }
324
325 void RTLIL::Selection::optimize(RTLIL::Design *design)
326 {
327 if (full_selection) {
328 selected_modules.clear();
329 selected_members.clear();
330 return;
331 }
332
333 std::vector<RTLIL::IdString> del_list, add_list;
334
335 del_list.clear();
336 for (auto mod_name : selected_modules) {
337 if (design->modules_.count(mod_name) == 0)
338 del_list.push_back(mod_name);
339 selected_members.erase(mod_name);
340 }
341 for (auto mod_name : del_list)
342 selected_modules.erase(mod_name);
343
344 del_list.clear();
345 for (auto &it : selected_members)
346 if (design->modules_.count(it.first) == 0)
347 del_list.push_back(it.first);
348 for (auto mod_name : del_list)
349 selected_members.erase(mod_name);
350
351 for (auto &it : selected_members) {
352 del_list.clear();
353 for (auto memb_name : it.second)
354 if (design->modules_[it.first]->count_id(memb_name) == 0)
355 del_list.push_back(memb_name);
356 for (auto memb_name : del_list)
357 it.second.erase(memb_name);
358 }
359
360 del_list.clear();
361 add_list.clear();
362 for (auto &it : selected_members)
363 if (it.second.size() == 0)
364 del_list.push_back(it.first);
365 else if (it.second.size() == design->modules_[it.first]->wires_.size() + design->modules_[it.first]->memories.size() +
366 design->modules_[it.first]->cells_.size() + design->modules_[it.first]->processes.size())
367 add_list.push_back(it.first);
368 for (auto mod_name : del_list)
369 selected_members.erase(mod_name);
370 for (auto mod_name : add_list) {
371 selected_members.erase(mod_name);
372 selected_modules.insert(mod_name);
373 }
374
375 if (selected_modules.size() == design->modules_.size()) {
376 full_selection = true;
377 selected_modules.clear();
378 selected_members.clear();
379 }
380 }
381
382 RTLIL::Design::Design()
383 : verilog_defines (new define_map_t)
384 {
385 static unsigned int hashidx_count = 123456789;
386 hashidx_count = mkhash_xorshift(hashidx_count);
387 hashidx_ = hashidx_count;
388
389 refcount_modules_ = 0;
390 selection_stack.push_back(RTLIL::Selection());
391
392 #ifdef WITH_PYTHON
393 RTLIL::Design::get_all_designs()->insert(std::pair<unsigned int, RTLIL::Design*>(hashidx_, this));
394 #endif
395 }
396
397 RTLIL::Design::~Design()
398 {
399 for (auto it = modules_.begin(); it != modules_.end(); ++it)
400 delete it->second;
401 for (auto n : verilog_packages)
402 delete n;
403 for (auto n : verilog_globals)
404 delete n;
405 #ifdef WITH_PYTHON
406 RTLIL::Design::get_all_designs()->erase(hashidx_);
407 #endif
408 }
409
410 #ifdef WITH_PYTHON
411 static std::map<unsigned int, RTLIL::Design*> all_designs;
412 std::map<unsigned int, RTLIL::Design*> *RTLIL::Design::get_all_designs(void)
413 {
414 return &all_designs;
415 }
416 #endif
417
418 RTLIL::ObjRange<RTLIL::Module*> RTLIL::Design::modules()
419 {
420 return RTLIL::ObjRange<RTLIL::Module*>(&modules_, &refcount_modules_);
421 }
422
423 RTLIL::Module *RTLIL::Design::module(RTLIL::IdString name)
424 {
425 return modules_.count(name) ? modules_.at(name) : NULL;
426 }
427
428 RTLIL::Module *RTLIL::Design::top_module()
429 {
430 RTLIL::Module *module = nullptr;
431 int module_count = 0;
432
433 for (auto mod : selected_modules()) {
434 if (mod->get_bool_attribute(ID(top)))
435 return mod;
436 module_count++;
437 module = mod;
438 }
439
440 return module_count == 1 ? module : nullptr;
441 }
442
443 void RTLIL::Design::add(RTLIL::Module *module)
444 {
445 log_assert(modules_.count(module->name) == 0);
446 log_assert(refcount_modules_ == 0);
447 modules_[module->name] = module;
448 module->design = this;
449
450 for (auto mon : monitors)
451 mon->notify_module_add(module);
452
453 if (yosys_xtrace) {
454 log("#X# New Module: %s\n", log_id(module));
455 log_backtrace("-X- ", yosys_xtrace-1);
456 }
457 }
458
459 RTLIL::Module *RTLIL::Design::addModule(RTLIL::IdString name)
460 {
461 log_assert(modules_.count(name) == 0);
462 log_assert(refcount_modules_ == 0);
463
464 RTLIL::Module *module = new RTLIL::Module;
465 modules_[name] = module;
466 module->design = this;
467 module->name = name;
468
469 for (auto mon : monitors)
470 mon->notify_module_add(module);
471
472 if (yosys_xtrace) {
473 log("#X# New Module: %s\n", log_id(module));
474 log_backtrace("-X- ", yosys_xtrace-1);
475 }
476
477 return module;
478 }
479
480 void RTLIL::Design::scratchpad_unset(std::string varname)
481 {
482 scratchpad.erase(varname);
483 }
484
485 void RTLIL::Design::scratchpad_set_int(std::string varname, int value)
486 {
487 scratchpad[varname] = stringf("%d", value);
488 }
489
490 void RTLIL::Design::scratchpad_set_bool(std::string varname, bool value)
491 {
492 scratchpad[varname] = value ? "true" : "false";
493 }
494
495 void RTLIL::Design::scratchpad_set_string(std::string varname, std::string value)
496 {
497 scratchpad[varname] = value;
498 }
499
500 int RTLIL::Design::scratchpad_get_int(std::string varname, int default_value) const
501 {
502 if (scratchpad.count(varname) == 0)
503 return default_value;
504
505 std::string str = scratchpad.at(varname);
506
507 if (str == "0" || str == "false")
508 return 0;
509
510 if (str == "1" || str == "true")
511 return 1;
512
513 char *endptr = nullptr;
514 long int parsed_value = strtol(str.c_str(), &endptr, 10);
515 return *endptr ? default_value : parsed_value;
516 }
517
518 bool RTLIL::Design::scratchpad_get_bool(std::string varname, bool default_value) const
519 {
520 if (scratchpad.count(varname) == 0)
521 return default_value;
522
523 std::string str = scratchpad.at(varname);
524
525 if (str == "0" || str == "false")
526 return false;
527
528 if (str == "1" || str == "true")
529 return true;
530
531 return default_value;
532 }
533
534 std::string RTLIL::Design::scratchpad_get_string(std::string varname, std::string default_value) const
535 {
536 if (scratchpad.count(varname) == 0)
537 return default_value;
538 return scratchpad.at(varname);
539 }
540
541 void RTLIL::Design::remove(RTLIL::Module *module)
542 {
543 for (auto mon : monitors)
544 mon->notify_module_del(module);
545
546 if (yosys_xtrace) {
547 log("#X# Remove Module: %s\n", log_id(module));
548 log_backtrace("-X- ", yosys_xtrace-1);
549 }
550
551 log_assert(modules_.at(module->name) == module);
552 modules_.erase(module->name);
553 delete module;
554 }
555
556 void RTLIL::Design::rename(RTLIL::Module *module, RTLIL::IdString new_name)
557 {
558 modules_.erase(module->name);
559 module->name = new_name;
560 add(module);
561 }
562
563 void RTLIL::Design::sort()
564 {
565 scratchpad.sort();
566 modules_.sort(sort_by_id_str());
567 for (auto &it : modules_)
568 it.second->sort();
569 }
570
571 void RTLIL::Design::check()
572 {
573 #ifndef NDEBUG
574 for (auto &it : modules_) {
575 log_assert(this == it.second->design);
576 log_assert(it.first == it.second->name);
577 log_assert(!it.first.empty());
578 it.second->check();
579 }
580 #endif
581 }
582
583 void RTLIL::Design::optimize()
584 {
585 for (auto &it : modules_)
586 it.second->optimize();
587 for (auto &it : selection_stack)
588 it.optimize(this);
589 for (auto &it : selection_vars)
590 it.second.optimize(this);
591 }
592
593 bool RTLIL::Design::selected_module(RTLIL::IdString mod_name) const
594 {
595 if (!selected_active_module.empty() && mod_name != selected_active_module)
596 return false;
597 if (selection_stack.size() == 0)
598 return true;
599 return selection_stack.back().selected_module(mod_name);
600 }
601
602 bool RTLIL::Design::selected_whole_module(RTLIL::IdString mod_name) const
603 {
604 if (!selected_active_module.empty() && mod_name != selected_active_module)
605 return false;
606 if (selection_stack.size() == 0)
607 return true;
608 return selection_stack.back().selected_whole_module(mod_name);
609 }
610
611 bool RTLIL::Design::selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const
612 {
613 if (!selected_active_module.empty() && mod_name != selected_active_module)
614 return false;
615 if (selection_stack.size() == 0)
616 return true;
617 return selection_stack.back().selected_member(mod_name, memb_name);
618 }
619
620 bool RTLIL::Design::selected_module(RTLIL::Module *mod) const
621 {
622 return selected_module(mod->name);
623 }
624
625 bool RTLIL::Design::selected_whole_module(RTLIL::Module *mod) const
626 {
627 return selected_whole_module(mod->name);
628 }
629
630 std::vector<RTLIL::Module*> RTLIL::Design::selected_modules() const
631 {
632 std::vector<RTLIL::Module*> result;
633 result.reserve(modules_.size());
634 for (auto &it : modules_)
635 if (selected_module(it.first) && !it.second->get_blackbox_attribute())
636 result.push_back(it.second);
637 return result;
638 }
639
640 std::vector<RTLIL::Module*> RTLIL::Design::selected_whole_modules() const
641 {
642 std::vector<RTLIL::Module*> result;
643 result.reserve(modules_.size());
644 for (auto &it : modules_)
645 if (selected_whole_module(it.first) && !it.second->get_blackbox_attribute())
646 result.push_back(it.second);
647 return result;
648 }
649
650 std::vector<RTLIL::Module*> RTLIL::Design::selected_whole_modules_warn() const
651 {
652 std::vector<RTLIL::Module*> result;
653 result.reserve(modules_.size());
654 for (auto &it : modules_)
655 if (it.second->get_blackbox_attribute())
656 continue;
657 else if (selected_whole_module(it.first))
658 result.push_back(it.second);
659 else if (selected_module(it.first))
660 log_warning("Ignoring partially selected module %s.\n", log_id(it.first));
661 return result;
662 }
663
664 RTLIL::Module::Module()
665 {
666 static unsigned int hashidx_count = 123456789;
667 hashidx_count = mkhash_xorshift(hashidx_count);
668 hashidx_ = hashidx_count;
669
670 design = nullptr;
671 refcount_wires_ = 0;
672 refcount_cells_ = 0;
673
674 #ifdef WITH_PYTHON
675 RTLIL::Module::get_all_modules()->insert(std::pair<unsigned int, RTLIL::Module*>(hashidx_, this));
676 #endif
677 }
678
679 RTLIL::Module::~Module()
680 {
681 for (auto it = wires_.begin(); it != wires_.end(); ++it)
682 delete it->second;
683 for (auto it = memories.begin(); it != memories.end(); ++it)
684 delete it->second;
685 for (auto it = cells_.begin(); it != cells_.end(); ++it)
686 delete it->second;
687 for (auto it = processes.begin(); it != processes.end(); ++it)
688 delete it->second;
689 #ifdef WITH_PYTHON
690 RTLIL::Module::get_all_modules()->erase(hashidx_);
691 #endif
692 }
693
694 #ifdef WITH_PYTHON
695 static std::map<unsigned int, RTLIL::Module*> all_modules;
696 std::map<unsigned int, RTLIL::Module*> *RTLIL::Module::get_all_modules(void)
697 {
698 return &all_modules;
699 }
700 #endif
701
702 void RTLIL::Module::makeblackbox()
703 {
704 pool<RTLIL::Wire*> delwires;
705
706 for (auto it = wires_.begin(); it != wires_.end(); ++it)
707 if (!it->second->port_input && !it->second->port_output)
708 delwires.insert(it->second);
709
710 for (auto it = memories.begin(); it != memories.end(); ++it)
711 delete it->second;
712 memories.clear();
713
714 for (auto it = cells_.begin(); it != cells_.end(); ++it)
715 delete it->second;
716 cells_.clear();
717
718 for (auto it = processes.begin(); it != processes.end(); ++it)
719 delete it->second;
720 processes.clear();
721
722 remove(delwires);
723 set_bool_attribute(ID::blackbox);
724 }
725
726 void RTLIL::Module::reprocess_module(RTLIL::Design *, dict<RTLIL::IdString, RTLIL::Module *>)
727 {
728 log_error("Cannot reprocess_module module `%s' !\n", id2cstr(name));
729 }
730
731 RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, dict<RTLIL::IdString, RTLIL::Const>, bool mayfail)
732 {
733 if (mayfail)
734 return RTLIL::IdString();
735 log_error("Module `%s' is used with parameters but is not parametric!\n", id2cstr(name));
736 }
737
738
739 RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, dict<RTLIL::IdString, RTLIL::Const>, dict<RTLIL::IdString, RTLIL::Module*>, dict<RTLIL::IdString, RTLIL::IdString>, bool mayfail)
740 {
741 if (mayfail)
742 return RTLIL::IdString();
743 log_error("Module `%s' is used with parameters but is not parametric!\n", id2cstr(name));
744 }
745
746 size_t RTLIL::Module::count_id(RTLIL::IdString id)
747 {
748 return wires_.count(id) + memories.count(id) + cells_.count(id) + processes.count(id);
749 }
750
751 #ifndef NDEBUG
752 namespace {
753 struct InternalCellChecker
754 {
755 RTLIL::Module *module;
756 RTLIL::Cell *cell;
757 pool<RTLIL::IdString> expected_params, expected_ports;
758
759 InternalCellChecker(RTLIL::Module *module, RTLIL::Cell *cell) : module(module), cell(cell) { }
760
761 void error(int linenr)
762 {
763 std::stringstream buf;
764 ILANG_BACKEND::dump_cell(buf, " ", cell);
765
766 log_error("Found error in internal cell %s%s%s (%s) at %s:%d:\n%s",
767 module ? module->name.c_str() : "", module ? "." : "",
768 cell->name.c_str(), cell->type.c_str(), __FILE__, linenr, buf.str().c_str());
769 }
770
771 int param(RTLIL::IdString name)
772 {
773 if (cell->parameters.count(name) == 0)
774 error(__LINE__);
775 expected_params.insert(name);
776 return cell->parameters.at(name).as_int();
777 }
778
779 int param_bool(RTLIL::IdString name)
780 {
781 int v = param(name);
782 if (cell->parameters.at(name).bits.size() > 32)
783 error(__LINE__);
784 if (v != 0 && v != 1)
785 error(__LINE__);
786 return v;
787 }
788
789 int param_bool(RTLIL::IdString name, bool expected)
790 {
791 int v = param_bool(name);
792 if (v != expected)
793 error(__LINE__);
794 return v;
795 }
796
797 void param_bits(RTLIL::IdString name, int width)
798 {
799 param(name);
800 if (int(cell->parameters.at(name).bits.size()) != width)
801 error(__LINE__);
802 }
803
804 void port(RTLIL::IdString name, int width)
805 {
806 if (!cell->hasPort(name))
807 error(__LINE__);
808 if (cell->getPort(name).size() != width)
809 error(__LINE__);
810 expected_ports.insert(name);
811 }
812
813 void check_expected(bool check_matched_sign = true)
814 {
815 for (auto &para : cell->parameters)
816 if (expected_params.count(para.first) == 0)
817 error(__LINE__);
818 for (auto &conn : cell->connections())
819 if (expected_ports.count(conn.first) == 0)
820 error(__LINE__);
821
822 if (expected_params.count(ID(A_SIGNED)) != 0 && expected_params.count(ID(B_SIGNED)) && check_matched_sign) {
823 bool a_is_signed = param(ID(A_SIGNED)) != 0;
824 bool b_is_signed = param(ID(B_SIGNED)) != 0;
825 if (a_is_signed != b_is_signed)
826 error(__LINE__);
827 }
828 }
829
830 void check_gate(const char *ports)
831 {
832 if (cell->parameters.size() != 0)
833 error(__LINE__);
834
835 for (const char *p = ports; *p; p++) {
836 char portname[3] = { '\\', *p, 0 };
837 if (!cell->hasPort(portname))
838 error(__LINE__);
839 if (cell->getPort(portname).size() != 1)
840 error(__LINE__);
841 }
842
843 for (auto &conn : cell->connections()) {
844 if (conn.first.size() != 2 || conn.first[0] != '\\')
845 error(__LINE__);
846 if (strchr(ports, conn.first[1]) == NULL)
847 error(__LINE__);
848 }
849 }
850
851 void check()
852 {
853 if (!cell->type.begins_with("$") || cell->type.begins_with("$__") || cell->type.begins_with("$paramod") || cell->type.begins_with("$fmcombine") ||
854 cell->type.begins_with("$verific$") || cell->type.begins_with("$array:") || cell->type.begins_with("$extern:"))
855 return;
856
857 if (cell->type.in(ID($not), ID($pos), ID($neg))) {
858 param_bool(ID(A_SIGNED));
859 port(ID::A, param(ID(A_WIDTH)));
860 port(ID::Y, param(ID(Y_WIDTH)));
861 check_expected();
862 return;
863 }
864
865 if (cell->type.in(ID($and), ID($or), ID($xor), ID($xnor))) {
866 param_bool(ID(A_SIGNED));
867 param_bool(ID(B_SIGNED));
868 port(ID::A, param(ID(A_WIDTH)));
869 port(ID::B, param(ID(B_WIDTH)));
870 port(ID::Y, param(ID(Y_WIDTH)));
871 check_expected();
872 return;
873 }
874
875 if (cell->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor), ID($reduce_bool))) {
876 param_bool(ID(A_SIGNED));
877 port(ID::A, param(ID(A_WIDTH)));
878 port(ID::Y, param(ID(Y_WIDTH)));
879 check_expected();
880 return;
881 }
882
883 if (cell->type.in(ID($shl), ID($shr), ID($sshl), ID($sshr))) {
884 param_bool(ID(A_SIGNED));
885 param_bool(ID(B_SIGNED), /*expected=*/false);
886 port(ID::A, param(ID(A_WIDTH)));
887 port(ID::B, param(ID(B_WIDTH)));
888 port(ID::Y, param(ID(Y_WIDTH)));
889 check_expected(/*check_matched_sign=*/false);
890 return;
891 }
892
893 if (cell->type.in(ID($shift), ID($shiftx))) {
894 param_bool(ID(A_SIGNED));
895 param_bool(ID(B_SIGNED));
896 port(ID::A, param(ID(A_WIDTH)));
897 port(ID::B, param(ID(B_WIDTH)));
898 port(ID::Y, param(ID(Y_WIDTH)));
899 check_expected(/*check_matched_sign=*/false);
900 return;
901 }
902
903 if (cell->type.in(ID($lt), ID($le), ID($eq), ID($ne), ID($eqx), ID($nex), ID($ge), ID($gt))) {
904 param_bool(ID(A_SIGNED));
905 param_bool(ID(B_SIGNED));
906 port(ID::A, param(ID(A_WIDTH)));
907 port(ID::B, param(ID(B_WIDTH)));
908 port(ID::Y, param(ID(Y_WIDTH)));
909 check_expected();
910 return;
911 }
912
913 if (cell->type.in(ID($add), ID($sub), ID($mul), ID($div), ID($mod), ID($pow))) {
914 param_bool(ID(A_SIGNED));
915 param_bool(ID(B_SIGNED));
916 port(ID::A, param(ID(A_WIDTH)));
917 port(ID::B, param(ID(B_WIDTH)));
918 port(ID::Y, param(ID(Y_WIDTH)));
919 check_expected(cell->type != ID($pow));
920 return;
921 }
922
923 if (cell->type == ID($fa)) {
924 port(ID::A, param(ID(WIDTH)));
925 port(ID::B, param(ID(WIDTH)));
926 port(ID(C), param(ID(WIDTH)));
927 port(ID(X), param(ID(WIDTH)));
928 port(ID::Y, param(ID(WIDTH)));
929 check_expected();
930 return;
931 }
932
933 if (cell->type == ID($lcu)) {
934 port(ID(P), param(ID(WIDTH)));
935 port(ID(G), param(ID(WIDTH)));
936 port(ID(CI), 1);
937 port(ID(CO), param(ID(WIDTH)));
938 check_expected();
939 return;
940 }
941
942 if (cell->type == ID($alu)) {
943 param_bool(ID(A_SIGNED));
944 param_bool(ID(B_SIGNED));
945 port(ID::A, param(ID(A_WIDTH)));
946 port(ID::B, param(ID(B_WIDTH)));
947 port(ID(CI), 1);
948 port(ID(BI), 1);
949 port(ID(X), param(ID(Y_WIDTH)));
950 port(ID::Y, param(ID(Y_WIDTH)));
951 port(ID(CO), param(ID(Y_WIDTH)));
952 check_expected();
953 return;
954 }
955
956 if (cell->type == ID($macc)) {
957 param(ID(CONFIG));
958 param(ID(CONFIG_WIDTH));
959 port(ID::A, param(ID(A_WIDTH)));
960 port(ID::B, param(ID(B_WIDTH)));
961 port(ID::Y, param(ID(Y_WIDTH)));
962 check_expected();
963 Macc().from_cell(cell);
964 return;
965 }
966
967 if (cell->type == ID($logic_not)) {
968 param_bool(ID(A_SIGNED));
969 port(ID::A, param(ID(A_WIDTH)));
970 port(ID::Y, param(ID(Y_WIDTH)));
971 check_expected();
972 return;
973 }
974
975 if (cell->type.in(ID($logic_and), ID($logic_or))) {
976 param_bool(ID(A_SIGNED));
977 param_bool(ID(B_SIGNED));
978 port(ID::A, param(ID(A_WIDTH)));
979 port(ID::B, param(ID(B_WIDTH)));
980 port(ID::Y, param(ID(Y_WIDTH)));
981 check_expected(/*check_matched_sign=*/false);
982 return;
983 }
984
985 if (cell->type == ID($slice)) {
986 param(ID(OFFSET));
987 port(ID::A, param(ID(A_WIDTH)));
988 port(ID::Y, param(ID(Y_WIDTH)));
989 if (param(ID(OFFSET)) + param(ID(Y_WIDTH)) > param(ID(A_WIDTH)))
990 error(__LINE__);
991 check_expected();
992 return;
993 }
994
995 if (cell->type == ID($concat)) {
996 port(ID::A, param(ID(A_WIDTH)));
997 port(ID::B, param(ID(B_WIDTH)));
998 port(ID::Y, param(ID(A_WIDTH)) + param(ID(B_WIDTH)));
999 check_expected();
1000 return;
1001 }
1002
1003 if (cell->type == ID($mux)) {
1004 port(ID::A, param(ID(WIDTH)));
1005 port(ID::B, param(ID(WIDTH)));
1006 port(ID(S), 1);
1007 port(ID::Y, param(ID(WIDTH)));
1008 check_expected();
1009 return;
1010 }
1011
1012 if (cell->type == ID($pmux)) {
1013 port(ID::A, param(ID(WIDTH)));
1014 port(ID::B, param(ID(WIDTH)) * param(ID(S_WIDTH)));
1015 port(ID(S), param(ID(S_WIDTH)));
1016 port(ID::Y, param(ID(WIDTH)));
1017 check_expected();
1018 return;
1019 }
1020
1021 if (cell->type == ID($lut)) {
1022 param(ID(LUT));
1023 port(ID::A, param(ID(WIDTH)));
1024 port(ID::Y, 1);
1025 check_expected();
1026 return;
1027 }
1028
1029 if (cell->type == ID($sop)) {
1030 param(ID(DEPTH));
1031 param(ID(TABLE));
1032 port(ID::A, param(ID(WIDTH)));
1033 port(ID::Y, 1);
1034 check_expected();
1035 return;
1036 }
1037
1038 if (cell->type == ID($sr)) {
1039 param_bool(ID(SET_POLARITY));
1040 param_bool(ID(CLR_POLARITY));
1041 port(ID(SET), param(ID(WIDTH)));
1042 port(ID(CLR), param(ID(WIDTH)));
1043 port(ID(Q), param(ID(WIDTH)));
1044 check_expected();
1045 return;
1046 }
1047
1048 if (cell->type == ID($ff)) {
1049 port(ID(D), param(ID(WIDTH)));
1050 port(ID(Q), param(ID(WIDTH)));
1051 check_expected();
1052 return;
1053 }
1054
1055 if (cell->type == ID($dff)) {
1056 param_bool(ID(CLK_POLARITY));
1057 port(ID(CLK), 1);
1058 port(ID(D), param(ID(WIDTH)));
1059 port(ID(Q), param(ID(WIDTH)));
1060 check_expected();
1061 return;
1062 }
1063
1064 if (cell->type == ID($dffe)) {
1065 param_bool(ID(CLK_POLARITY));
1066 param_bool(ID(EN_POLARITY));
1067 port(ID(CLK), 1);
1068 port(ID(EN), 1);
1069 port(ID(D), param(ID(WIDTH)));
1070 port(ID(Q), param(ID(WIDTH)));
1071 check_expected();
1072 return;
1073 }
1074
1075 if (cell->type == ID($dffsr)) {
1076 param_bool(ID(CLK_POLARITY));
1077 param_bool(ID(SET_POLARITY));
1078 param_bool(ID(CLR_POLARITY));
1079 port(ID(CLK), 1);
1080 port(ID(SET), param(ID(WIDTH)));
1081 port(ID(CLR), param(ID(WIDTH)));
1082 port(ID(D), param(ID(WIDTH)));
1083 port(ID(Q), param(ID(WIDTH)));
1084 check_expected();
1085 return;
1086 }
1087
1088 if (cell->type == ID($adff)) {
1089 param_bool(ID(CLK_POLARITY));
1090 param_bool(ID(ARST_POLARITY));
1091 param_bits(ID(ARST_VALUE), param(ID(WIDTH)));
1092 port(ID(CLK), 1);
1093 port(ID(ARST), 1);
1094 port(ID(D), param(ID(WIDTH)));
1095 port(ID(Q), param(ID(WIDTH)));
1096 check_expected();
1097 return;
1098 }
1099
1100 if (cell->type == ID($dlatch)) {
1101 param_bool(ID(EN_POLARITY));
1102 port(ID(EN), 1);
1103 port(ID(D), param(ID(WIDTH)));
1104 port(ID(Q), param(ID(WIDTH)));
1105 check_expected();
1106 return;
1107 }
1108
1109 if (cell->type == ID($dlatchsr)) {
1110 param_bool(ID(EN_POLARITY));
1111 param_bool(ID(SET_POLARITY));
1112 param_bool(ID(CLR_POLARITY));
1113 port(ID(EN), 1);
1114 port(ID(SET), param(ID(WIDTH)));
1115 port(ID(CLR), param(ID(WIDTH)));
1116 port(ID(D), param(ID(WIDTH)));
1117 port(ID(Q), param(ID(WIDTH)));
1118 check_expected();
1119 return;
1120 }
1121
1122 if (cell->type == ID($fsm)) {
1123 param(ID(NAME));
1124 param_bool(ID(CLK_POLARITY));
1125 param_bool(ID(ARST_POLARITY));
1126 param(ID(STATE_BITS));
1127 param(ID(STATE_NUM));
1128 param(ID(STATE_NUM_LOG2));
1129 param(ID(STATE_RST));
1130 param_bits(ID(STATE_TABLE), param(ID(STATE_BITS)) * param(ID(STATE_NUM)));
1131 param(ID(TRANS_NUM));
1132 param_bits(ID(TRANS_TABLE), param(ID(TRANS_NUM)) * (2*param(ID(STATE_NUM_LOG2)) + param(ID(CTRL_IN_WIDTH)) + param(ID(CTRL_OUT_WIDTH))));
1133 port(ID(CLK), 1);
1134 port(ID(ARST), 1);
1135 port(ID(CTRL_IN), param(ID(CTRL_IN_WIDTH)));
1136 port(ID(CTRL_OUT), param(ID(CTRL_OUT_WIDTH)));
1137 check_expected();
1138 return;
1139 }
1140
1141 if (cell->type == ID($memrd)) {
1142 param(ID(MEMID));
1143 param_bool(ID(CLK_ENABLE));
1144 param_bool(ID(CLK_POLARITY));
1145 param_bool(ID(TRANSPARENT));
1146 port(ID(CLK), 1);
1147 port(ID(EN), 1);
1148 port(ID(ADDR), param(ID(ABITS)));
1149 port(ID(DATA), param(ID(WIDTH)));
1150 check_expected();
1151 return;
1152 }
1153
1154 if (cell->type == ID($memwr)) {
1155 param(ID(MEMID));
1156 param_bool(ID(CLK_ENABLE));
1157 param_bool(ID(CLK_POLARITY));
1158 param(ID(PRIORITY));
1159 port(ID(CLK), 1);
1160 port(ID(EN), param(ID(WIDTH)));
1161 port(ID(ADDR), param(ID(ABITS)));
1162 port(ID(DATA), param(ID(WIDTH)));
1163 check_expected();
1164 return;
1165 }
1166
1167 if (cell->type == ID($meminit)) {
1168 param(ID(MEMID));
1169 param(ID(PRIORITY));
1170 port(ID(ADDR), param(ID(ABITS)));
1171 port(ID(DATA), param(ID(WIDTH)) * param(ID(WORDS)));
1172 check_expected();
1173 return;
1174 }
1175
1176 if (cell->type == ID($mem)) {
1177 param(ID(MEMID));
1178 param(ID(SIZE));
1179 param(ID(OFFSET));
1180 param(ID(INIT));
1181 param_bits(ID(RD_CLK_ENABLE), max(1, param(ID(RD_PORTS))));
1182 param_bits(ID(RD_CLK_POLARITY), max(1, param(ID(RD_PORTS))));
1183 param_bits(ID(RD_TRANSPARENT), max(1, param(ID(RD_PORTS))));
1184 param_bits(ID(WR_CLK_ENABLE), max(1, param(ID(WR_PORTS))));
1185 param_bits(ID(WR_CLK_POLARITY), max(1, param(ID(WR_PORTS))));
1186 port(ID(RD_CLK), param(ID(RD_PORTS)));
1187 port(ID(RD_EN), param(ID(RD_PORTS)));
1188 port(ID(RD_ADDR), param(ID(RD_PORTS)) * param(ID(ABITS)));
1189 port(ID(RD_DATA), param(ID(RD_PORTS)) * param(ID(WIDTH)));
1190 port(ID(WR_CLK), param(ID(WR_PORTS)));
1191 port(ID(WR_EN), param(ID(WR_PORTS)) * param(ID(WIDTH)));
1192 port(ID(WR_ADDR), param(ID(WR_PORTS)) * param(ID(ABITS)));
1193 port(ID(WR_DATA), param(ID(WR_PORTS)) * param(ID(WIDTH)));
1194 check_expected();
1195 return;
1196 }
1197
1198 if (cell->type == ID($tribuf)) {
1199 port(ID::A, param(ID(WIDTH)));
1200 port(ID::Y, param(ID(WIDTH)));
1201 port(ID(EN), 1);
1202 check_expected();
1203 return;
1204 }
1205
1206 if (cell->type.in(ID($assert), ID($assume), ID($live), ID($fair), ID($cover))) {
1207 port(ID::A, 1);
1208 port(ID(EN), 1);
1209 check_expected();
1210 return;
1211 }
1212
1213 if (cell->type == ID($initstate)) {
1214 port(ID::Y, 1);
1215 check_expected();
1216 return;
1217 }
1218
1219 if (cell->type.in(ID($anyconst), ID($anyseq), ID($allconst), ID($allseq))) {
1220 port(ID::Y, param(ID(WIDTH)));
1221 check_expected();
1222 return;
1223 }
1224
1225 if (cell->type == ID($equiv)) {
1226 port(ID::A, 1);
1227 port(ID::B, 1);
1228 port(ID::Y, 1);
1229 check_expected();
1230 return;
1231 }
1232
1233 if (cell->type.in(ID($specify2), ID($specify3))) {
1234 param_bool(ID(FULL));
1235 param_bool(ID(SRC_DST_PEN));
1236 param_bool(ID(SRC_DST_POL));
1237 param(ID(T_RISE_MIN));
1238 param(ID(T_RISE_TYP));
1239 param(ID(T_RISE_MAX));
1240 param(ID(T_FALL_MIN));
1241 param(ID(T_FALL_TYP));
1242 param(ID(T_FALL_MAX));
1243 port(ID(EN), 1);
1244 port(ID(SRC), param(ID(SRC_WIDTH)));
1245 port(ID(DST), param(ID(DST_WIDTH)));
1246 if (cell->type == ID($specify3)) {
1247 param_bool(ID(EDGE_EN));
1248 param_bool(ID(EDGE_POL));
1249 param_bool(ID(DAT_DST_PEN));
1250 param_bool(ID(DAT_DST_POL));
1251 port(ID(DAT), param(ID(DST_WIDTH)));
1252 }
1253 check_expected();
1254 return;
1255 }
1256
1257 if (cell->type == ID($specrule)) {
1258 param(ID(TYPE));
1259 param_bool(ID(SRC_PEN));
1260 param_bool(ID(SRC_POL));
1261 param_bool(ID(DST_PEN));
1262 param_bool(ID(DST_POL));
1263 param(ID(T_LIMIT_MIN));
1264 param(ID(T_LIMIT_TYP));
1265 param(ID(T_LIMIT_MAX));
1266 param(ID(T_LIMIT2_MIN));
1267 param(ID(T_LIMIT2_TYP));
1268 param(ID(T_LIMIT2_MAX));
1269 port(ID(SRC_EN), 1);
1270 port(ID(DST_EN), 1);
1271 port(ID(SRC), param(ID(SRC_WIDTH)));
1272 port(ID(DST), param(ID(DST_WIDTH)));
1273 check_expected();
1274 return;
1275 }
1276
1277 if (cell->type == ID($_BUF_)) { check_gate("AY"); return; }
1278 if (cell->type == ID($_NOT_)) { check_gate("AY"); return; }
1279 if (cell->type == ID($_AND_)) { check_gate("ABY"); return; }
1280 if (cell->type == ID($_NAND_)) { check_gate("ABY"); return; }
1281 if (cell->type == ID($_OR_)) { check_gate("ABY"); return; }
1282 if (cell->type == ID($_NOR_)) { check_gate("ABY"); return; }
1283 if (cell->type == ID($_XOR_)) { check_gate("ABY"); return; }
1284 if (cell->type == ID($_XNOR_)) { check_gate("ABY"); return; }
1285 if (cell->type == ID($_ANDNOT_)) { check_gate("ABY"); return; }
1286 if (cell->type == ID($_ORNOT_)) { check_gate("ABY"); return; }
1287 if (cell->type == ID($_MUX_)) { check_gate("ABSY"); return; }
1288 if (cell->type == ID($_NMUX_)) { check_gate("ABSY"); return; }
1289 if (cell->type == ID($_AOI3_)) { check_gate("ABCY"); return; }
1290 if (cell->type == ID($_OAI3_)) { check_gate("ABCY"); return; }
1291 if (cell->type == ID($_AOI4_)) { check_gate("ABCDY"); return; }
1292 if (cell->type == ID($_OAI4_)) { check_gate("ABCDY"); return; }
1293
1294 if (cell->type == ID($_TBUF_)) { check_gate("AYE"); return; }
1295
1296 if (cell->type == ID($_MUX4_)) { check_gate("ABCDSTY"); return; }
1297 if (cell->type == ID($_MUX8_)) { check_gate("ABCDEFGHSTUY"); return; }
1298 if (cell->type == ID($_MUX16_)) { check_gate("ABCDEFGHIJKLMNOPSTUVY"); return; }
1299
1300 if (cell->type == ID($_SR_NN_)) { check_gate("SRQ"); return; }
1301 if (cell->type == ID($_SR_NP_)) { check_gate("SRQ"); return; }
1302 if (cell->type == ID($_SR_PN_)) { check_gate("SRQ"); return; }
1303 if (cell->type == ID($_SR_PP_)) { check_gate("SRQ"); return; }
1304
1305 if (cell->type == ID($_FF_)) { check_gate("DQ"); return; }
1306 if (cell->type == ID($_DFF_N_)) { check_gate("DQC"); return; }
1307 if (cell->type == ID($_DFF_P_)) { check_gate("DQC"); return; }
1308
1309 if (cell->type == ID($_DFFE_NN_)) { check_gate("DQCE"); return; }
1310 if (cell->type == ID($_DFFE_NP_)) { check_gate("DQCE"); return; }
1311 if (cell->type == ID($_DFFE_PN_)) { check_gate("DQCE"); return; }
1312 if (cell->type == ID($_DFFE_PP_)) { check_gate("DQCE"); return; }
1313
1314 if (cell->type == ID($_DFF_NN0_)) { check_gate("DQCR"); return; }
1315 if (cell->type == ID($_DFF_NN1_)) { check_gate("DQCR"); return; }
1316 if (cell->type == ID($_DFF_NP0_)) { check_gate("DQCR"); return; }
1317 if (cell->type == ID($_DFF_NP1_)) { check_gate("DQCR"); return; }
1318 if (cell->type == ID($_DFF_PN0_)) { check_gate("DQCR"); return; }
1319 if (cell->type == ID($_DFF_PN1_)) { check_gate("DQCR"); return; }
1320 if (cell->type == ID($_DFF_PP0_)) { check_gate("DQCR"); return; }
1321 if (cell->type == ID($_DFF_PP1_)) { check_gate("DQCR"); return; }
1322
1323 if (cell->type == ID($_DFFSR_NNN_)) { check_gate("CSRDQ"); return; }
1324 if (cell->type == ID($_DFFSR_NNP_)) { check_gate("CSRDQ"); return; }
1325 if (cell->type == ID($_DFFSR_NPN_)) { check_gate("CSRDQ"); return; }
1326 if (cell->type == ID($_DFFSR_NPP_)) { check_gate("CSRDQ"); return; }
1327 if (cell->type == ID($_DFFSR_PNN_)) { check_gate("CSRDQ"); return; }
1328 if (cell->type == ID($_DFFSR_PNP_)) { check_gate("CSRDQ"); return; }
1329 if (cell->type == ID($_DFFSR_PPN_)) { check_gate("CSRDQ"); return; }
1330 if (cell->type == ID($_DFFSR_PPP_)) { check_gate("CSRDQ"); return; }
1331
1332 if (cell->type == ID($_DLATCH_N_)) { check_gate("EDQ"); return; }
1333 if (cell->type == ID($_DLATCH_P_)) { check_gate("EDQ"); return; }
1334
1335 if (cell->type == ID($_DLATCHSR_NNN_)) { check_gate("ESRDQ"); return; }
1336 if (cell->type == ID($_DLATCHSR_NNP_)) { check_gate("ESRDQ"); return; }
1337 if (cell->type == ID($_DLATCHSR_NPN_)) { check_gate("ESRDQ"); return; }
1338 if (cell->type == ID($_DLATCHSR_NPP_)) { check_gate("ESRDQ"); return; }
1339 if (cell->type == ID($_DLATCHSR_PNN_)) { check_gate("ESRDQ"); return; }
1340 if (cell->type == ID($_DLATCHSR_PNP_)) { check_gate("ESRDQ"); return; }
1341 if (cell->type == ID($_DLATCHSR_PPN_)) { check_gate("ESRDQ"); return; }
1342 if (cell->type == ID($_DLATCHSR_PPP_)) { check_gate("ESRDQ"); return; }
1343
1344 error(__LINE__);
1345 }
1346 };
1347 }
1348 #endif
1349
1350 void RTLIL::Module::sort()
1351 {
1352 wires_.sort(sort_by_id_str());
1353 cells_.sort(sort_by_id_str());
1354 avail_parameters.sort(sort_by_id_str());
1355 memories.sort(sort_by_id_str());
1356 processes.sort(sort_by_id_str());
1357 for (auto &it : cells_)
1358 it.second->sort();
1359 for (auto &it : wires_)
1360 it.second->attributes.sort(sort_by_id_str());
1361 for (auto &it : memories)
1362 it.second->attributes.sort(sort_by_id_str());
1363 }
1364
1365 void RTLIL::Module::check()
1366 {
1367 #ifndef NDEBUG
1368 std::vector<bool> ports_declared;
1369 for (auto &it : wires_) {
1370 log_assert(this == it.second->module);
1371 log_assert(it.first == it.second->name);
1372 log_assert(!it.first.empty());
1373 log_assert(it.second->width >= 0);
1374 log_assert(it.second->port_id >= 0);
1375 for (auto &it2 : it.second->attributes)
1376 log_assert(!it2.first.empty());
1377 if (it.second->port_id) {
1378 log_assert(GetSize(ports) >= it.second->port_id);
1379 log_assert(ports.at(it.second->port_id-1) == it.first);
1380 log_assert(it.second->port_input || it.second->port_output);
1381 if (GetSize(ports_declared) < it.second->port_id)
1382 ports_declared.resize(it.second->port_id);
1383 log_assert(ports_declared[it.second->port_id-1] == false);
1384 ports_declared[it.second->port_id-1] = true;
1385 } else
1386 log_assert(!it.second->port_input && !it.second->port_output);
1387 }
1388 for (auto port_declared : ports_declared)
1389 log_assert(port_declared == true);
1390 log_assert(GetSize(ports) == GetSize(ports_declared));
1391
1392 for (auto &it : memories) {
1393 log_assert(it.first == it.second->name);
1394 log_assert(!it.first.empty());
1395 log_assert(it.second->width >= 0);
1396 log_assert(it.second->size >= 0);
1397 for (auto &it2 : it.second->attributes)
1398 log_assert(!it2.first.empty());
1399 }
1400
1401 for (auto &it : cells_) {
1402 log_assert(this == it.second->module);
1403 log_assert(it.first == it.second->name);
1404 log_assert(!it.first.empty());
1405 log_assert(!it.second->type.empty());
1406 for (auto &it2 : it.second->connections()) {
1407 log_assert(!it2.first.empty());
1408 it2.second.check();
1409 }
1410 for (auto &it2 : it.second->attributes)
1411 log_assert(!it2.first.empty());
1412 for (auto &it2 : it.second->parameters)
1413 log_assert(!it2.first.empty());
1414 InternalCellChecker checker(this, it.second);
1415 checker.check();
1416 }
1417
1418 for (auto &it : processes) {
1419 log_assert(it.first == it.second->name);
1420 log_assert(!it.first.empty());
1421 log_assert(it.second->root_case.compare.empty());
1422 std::vector<CaseRule*> all_cases = {&it.second->root_case};
1423 for (size_t i = 0; i < all_cases.size(); i++) {
1424 for (auto &switch_it : all_cases[i]->switches) {
1425 for (auto &case_it : switch_it->cases) {
1426 for (auto &compare_it : case_it->compare) {
1427 log_assert(switch_it->signal.size() == compare_it.size());
1428 }
1429 all_cases.push_back(case_it);
1430 }
1431 }
1432 }
1433 for (auto &sync_it : it.second->syncs) {
1434 switch (sync_it->type) {
1435 case SyncType::ST0:
1436 case SyncType::ST1:
1437 case SyncType::STp:
1438 case SyncType::STn:
1439 case SyncType::STe:
1440 log_assert(!sync_it->signal.empty());
1441 break;
1442 case SyncType::STa:
1443 case SyncType::STg:
1444 case SyncType::STi:
1445 log_assert(sync_it->signal.empty());
1446 break;
1447 }
1448 }
1449 }
1450
1451 for (auto &it : connections_) {
1452 log_assert(it.first.size() == it.second.size());
1453 log_assert(!it.first.has_const());
1454 it.first.check();
1455 it.second.check();
1456 }
1457
1458 for (auto &it : attributes)
1459 log_assert(!it.first.empty());
1460 #endif
1461 }
1462
1463 void RTLIL::Module::optimize()
1464 {
1465 }
1466
1467 void RTLIL::Module::cloneInto(RTLIL::Module *new_mod) const
1468 {
1469 log_assert(new_mod->refcount_wires_ == 0);
1470 log_assert(new_mod->refcount_cells_ == 0);
1471
1472 new_mod->avail_parameters = avail_parameters;
1473
1474 for (auto &conn : connections_)
1475 new_mod->connect(conn);
1476
1477 for (auto &attr : attributes)
1478 new_mod->attributes[attr.first] = attr.second;
1479
1480 for (auto &it : wires_)
1481 new_mod->addWire(it.first, it.second);
1482
1483 for (auto &it : memories)
1484 new_mod->memories[it.first] = new RTLIL::Memory(*it.second);
1485
1486 for (auto &it : cells_)
1487 new_mod->addCell(it.first, it.second);
1488
1489 for (auto &it : processes)
1490 new_mod->processes[it.first] = it.second->clone();
1491
1492 struct RewriteSigSpecWorker
1493 {
1494 RTLIL::Module *mod;
1495 void operator()(RTLIL::SigSpec &sig)
1496 {
1497 std::vector<RTLIL::SigChunk> chunks = sig.chunks();
1498 for (auto &c : chunks)
1499 if (c.wire != NULL)
1500 c.wire = mod->wires_.at(c.wire->name);
1501 sig = chunks;
1502 }
1503 };
1504
1505 RewriteSigSpecWorker rewriteSigSpecWorker;
1506 rewriteSigSpecWorker.mod = new_mod;
1507 new_mod->rewrite_sigspecs(rewriteSigSpecWorker);
1508 new_mod->fixup_ports();
1509 }
1510
1511 RTLIL::Module *RTLIL::Module::clone() const
1512 {
1513 RTLIL::Module *new_mod = new RTLIL::Module;
1514 new_mod->name = name;
1515 cloneInto(new_mod);
1516 return new_mod;
1517 }
1518
1519 bool RTLIL::Module::has_memories() const
1520 {
1521 return !memories.empty();
1522 }
1523
1524 bool RTLIL::Module::has_processes() const
1525 {
1526 return !processes.empty();
1527 }
1528
1529 bool RTLIL::Module::has_memories_warn() const
1530 {
1531 if (!memories.empty())
1532 log_warning("Ignoring module %s because it contains memories (run 'memory' command first).\n", log_id(this));
1533 return !memories.empty();
1534 }
1535
1536 bool RTLIL::Module::has_processes_warn() const
1537 {
1538 if (!processes.empty())
1539 log_warning("Ignoring module %s because it contains processes (run 'proc' command first).\n", log_id(this));
1540 return !processes.empty();
1541 }
1542
1543 std::vector<RTLIL::Wire*> RTLIL::Module::selected_wires() const
1544 {
1545 std::vector<RTLIL::Wire*> result;
1546 result.reserve(wires_.size());
1547 for (auto &it : wires_)
1548 if (design->selected(this, it.second))
1549 result.push_back(it.second);
1550 return result;
1551 }
1552
1553 std::vector<RTLIL::Cell*> RTLIL::Module::selected_cells() const
1554 {
1555 std::vector<RTLIL::Cell*> result;
1556 result.reserve(cells_.size());
1557 for (auto &it : cells_)
1558 if (design->selected(this, it.second))
1559 result.push_back(it.second);
1560 return result;
1561 }
1562
1563 void RTLIL::Module::add(RTLIL::Wire *wire)
1564 {
1565 log_assert(!wire->name.empty());
1566 log_assert(count_id(wire->name) == 0);
1567 log_assert(refcount_wires_ == 0);
1568 wires_[wire->name] = wire;
1569 wire->module = this;
1570 }
1571
1572 void RTLIL::Module::add(RTLIL::Cell *cell)
1573 {
1574 log_assert(!cell->name.empty());
1575 log_assert(count_id(cell->name) == 0);
1576 log_assert(refcount_cells_ == 0);
1577 cells_[cell->name] = cell;
1578 cell->module = this;
1579 }
1580
1581 void RTLIL::Module::remove(const pool<RTLIL::Wire*> &wires)
1582 {
1583 log_assert(refcount_wires_ == 0);
1584
1585 struct DeleteWireWorker
1586 {
1587 RTLIL::Module *module;
1588 const pool<RTLIL::Wire*> *wires_p;
1589
1590 void operator()(RTLIL::SigSpec &sig) {
1591 std::vector<RTLIL::SigChunk> chunks = sig;
1592 for (auto &c : chunks)
1593 if (c.wire != NULL && wires_p->count(c.wire)) {
1594 c.wire = module->addWire(NEW_ID, c.width);
1595 c.offset = 0;
1596 }
1597 sig = chunks;
1598 }
1599
1600 void operator()(RTLIL::SigSpec &lhs, RTLIL::SigSpec &rhs) {
1601 log_assert(GetSize(lhs) == GetSize(rhs));
1602 RTLIL::SigSpec new_lhs, new_rhs;
1603 for (int i = 0; i < GetSize(lhs); i++) {
1604 RTLIL::SigBit lhs_bit = lhs[i];
1605 if (lhs_bit.wire != nullptr && wires_p->count(lhs_bit.wire))
1606 continue;
1607 RTLIL::SigBit rhs_bit = rhs[i];
1608 if (rhs_bit.wire != nullptr && wires_p->count(rhs_bit.wire))
1609 continue;
1610 new_lhs.append(lhs_bit);
1611 new_rhs.append(rhs_bit);
1612 }
1613 lhs = new_lhs;
1614 rhs = new_rhs;
1615 }
1616 };
1617
1618 DeleteWireWorker delete_wire_worker;
1619 delete_wire_worker.module = this;
1620 delete_wire_worker.wires_p = &wires;
1621 rewrite_sigspecs2(delete_wire_worker);
1622
1623 for (auto &it : wires) {
1624 log_assert(wires_.count(it->name) != 0);
1625 wires_.erase(it->name);
1626 delete it;
1627 }
1628 }
1629
1630 void RTLIL::Module::remove(RTLIL::Cell *cell)
1631 {
1632 while (!cell->connections_.empty())
1633 cell->unsetPort(cell->connections_.begin()->first);
1634
1635 log_assert(cells_.count(cell->name) != 0);
1636 log_assert(refcount_cells_ == 0);
1637 cells_.erase(cell->name);
1638 delete cell;
1639 }
1640
1641 void RTLIL::Module::rename(RTLIL::Wire *wire, RTLIL::IdString new_name)
1642 {
1643 log_assert(wires_[wire->name] == wire);
1644 log_assert(refcount_wires_ == 0);
1645 wires_.erase(wire->name);
1646 wire->name = new_name;
1647 add(wire);
1648 }
1649
1650 void RTLIL::Module::rename(RTLIL::Cell *cell, RTLIL::IdString new_name)
1651 {
1652 log_assert(cells_[cell->name] == cell);
1653 log_assert(refcount_wires_ == 0);
1654 cells_.erase(cell->name);
1655 cell->name = new_name;
1656 add(cell);
1657 }
1658
1659 void RTLIL::Module::rename(RTLIL::IdString old_name, RTLIL::IdString new_name)
1660 {
1661 log_assert(count_id(old_name) != 0);
1662 if (wires_.count(old_name))
1663 rename(wires_.at(old_name), new_name);
1664 else if (cells_.count(old_name))
1665 rename(cells_.at(old_name), new_name);
1666 else
1667 log_abort();
1668 }
1669
1670 void RTLIL::Module::swap_names(RTLIL::Wire *w1, RTLIL::Wire *w2)
1671 {
1672 log_assert(wires_[w1->name] == w1);
1673 log_assert(wires_[w2->name] == w2);
1674 log_assert(refcount_wires_ == 0);
1675
1676 wires_.erase(w1->name);
1677 wires_.erase(w2->name);
1678
1679 std::swap(w1->name, w2->name);
1680
1681 wires_[w1->name] = w1;
1682 wires_[w2->name] = w2;
1683 }
1684
1685 void RTLIL::Module::swap_names(RTLIL::Cell *c1, RTLIL::Cell *c2)
1686 {
1687 log_assert(cells_[c1->name] == c1);
1688 log_assert(cells_[c2->name] == c2);
1689 log_assert(refcount_cells_ == 0);
1690
1691 cells_.erase(c1->name);
1692 cells_.erase(c2->name);
1693
1694 std::swap(c1->name, c2->name);
1695
1696 cells_[c1->name] = c1;
1697 cells_[c2->name] = c2;
1698 }
1699
1700 RTLIL::IdString RTLIL::Module::uniquify(RTLIL::IdString name)
1701 {
1702 int index = 0;
1703 return uniquify(name, index);
1704 }
1705
1706 RTLIL::IdString RTLIL::Module::uniquify(RTLIL::IdString name, int &index)
1707 {
1708 if (index == 0) {
1709 if (count_id(name) == 0)
1710 return name;
1711 index++;
1712 }
1713
1714 while (1) {
1715 RTLIL::IdString new_name = stringf("%s_%d", name.c_str(), index);
1716 if (count_id(new_name) == 0)
1717 return new_name;
1718 index++;
1719 }
1720 }
1721
1722 static bool fixup_ports_compare(const RTLIL::Wire *a, const RTLIL::Wire *b)
1723 {
1724 if (a->port_id && !b->port_id)
1725 return true;
1726 if (!a->port_id && b->port_id)
1727 return false;
1728
1729 if (a->port_id == b->port_id)
1730 return a->name < b->name;
1731 return a->port_id < b->port_id;
1732 }
1733
1734 void RTLIL::Module::connect(const RTLIL::SigSig &conn)
1735 {
1736 for (auto mon : monitors)
1737 mon->notify_connect(this, conn);
1738
1739 if (design)
1740 for (auto mon : design->monitors)
1741 mon->notify_connect(this, conn);
1742
1743 // ignore all attempts to assign constants to other constants
1744 if (conn.first.has_const()) {
1745 RTLIL::SigSig new_conn;
1746 for (int i = 0; i < GetSize(conn.first); i++)
1747 if (conn.first[i].wire) {
1748 new_conn.first.append(conn.first[i]);
1749 new_conn.second.append(conn.second[i]);
1750 }
1751 if (GetSize(new_conn.first))
1752 connect(new_conn);
1753 return;
1754 }
1755
1756 if (yosys_xtrace) {
1757 log("#X# Connect (SigSig) in %s: %s = %s (%d bits)\n", log_id(this), log_signal(conn.first), log_signal(conn.second), GetSize(conn.first));
1758 log_backtrace("-X- ", yosys_xtrace-1);
1759 }
1760
1761 log_assert(GetSize(conn.first) == GetSize(conn.second));
1762 connections_.push_back(conn);
1763 }
1764
1765 void RTLIL::Module::connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs)
1766 {
1767 connect(RTLIL::SigSig(lhs, rhs));
1768 }
1769
1770 void RTLIL::Module::new_connections(const std::vector<RTLIL::SigSig> &new_conn)
1771 {
1772 for (auto mon : monitors)
1773 mon->notify_connect(this, new_conn);
1774
1775 if (design)
1776 for (auto mon : design->monitors)
1777 mon->notify_connect(this, new_conn);
1778
1779 if (yosys_xtrace) {
1780 log("#X# New connections vector in %s:\n", log_id(this));
1781 for (auto &conn: new_conn)
1782 log("#X# %s = %s (%d bits)\n", log_signal(conn.first), log_signal(conn.second), GetSize(conn.first));
1783 log_backtrace("-X- ", yosys_xtrace-1);
1784 }
1785
1786 connections_ = new_conn;
1787 }
1788
1789 const std::vector<RTLIL::SigSig> &RTLIL::Module::connections() const
1790 {
1791 return connections_;
1792 }
1793
1794 void RTLIL::Module::fixup_ports()
1795 {
1796 std::vector<RTLIL::Wire*> all_ports;
1797
1798 for (auto &w : wires_)
1799 if (w.second->port_input || w.second->port_output)
1800 all_ports.push_back(w.second);
1801 else
1802 w.second->port_id = 0;
1803
1804 std::sort(all_ports.begin(), all_ports.end(), fixup_ports_compare);
1805
1806 ports.clear();
1807 for (size_t i = 0; i < all_ports.size(); i++) {
1808 ports.push_back(all_ports[i]->name);
1809 all_ports[i]->port_id = i+1;
1810 }
1811 }
1812
1813 RTLIL::Wire *RTLIL::Module::addWire(RTLIL::IdString name, int width)
1814 {
1815 RTLIL::Wire *wire = new RTLIL::Wire;
1816 wire->name = name;
1817 wire->width = width;
1818 add(wire);
1819 return wire;
1820 }
1821
1822 RTLIL::Wire *RTLIL::Module::addWire(RTLIL::IdString name, const RTLIL::Wire *other)
1823 {
1824 RTLIL::Wire *wire = addWire(name);
1825 wire->width = other->width;
1826 wire->start_offset = other->start_offset;
1827 wire->port_id = other->port_id;
1828 wire->port_input = other->port_input;
1829 wire->port_output = other->port_output;
1830 wire->upto = other->upto;
1831 wire->attributes = other->attributes;
1832 return wire;
1833 }
1834
1835 RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, RTLIL::IdString type)
1836 {
1837 RTLIL::Cell *cell = new RTLIL::Cell;
1838 cell->name = name;
1839 cell->type = type;
1840 add(cell);
1841 return cell;
1842 }
1843
1844 RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, const RTLIL::Cell *other)
1845 {
1846 RTLIL::Cell *cell = addCell(name, other->type);
1847 cell->connections_ = other->connections_;
1848 cell->parameters = other->parameters;
1849 cell->attributes = other->attributes;
1850 return cell;
1851 }
1852
1853 #define DEF_METHOD(_func, _y_size, _type) \
1854 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed, const std::string &src) { \
1855 RTLIL::Cell *cell = addCell(name, _type); \
1856 cell->parameters[ID(A_SIGNED)] = is_signed; \
1857 cell->parameters[ID(A_WIDTH)] = sig_a.size(); \
1858 cell->parameters[ID(Y_WIDTH)] = sig_y.size(); \
1859 cell->setPort(ID::A, sig_a); \
1860 cell->setPort(ID::Y, sig_y); \
1861 cell->set_src_attribute(src); \
1862 return cell; \
1863 } \
1864 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed, const std::string &src) { \
1865 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
1866 add ## _func(name, sig_a, sig_y, is_signed, src); \
1867 return sig_y; \
1868 }
1869 DEF_METHOD(Not, sig_a.size(), ID($not))
1870 DEF_METHOD(Pos, sig_a.size(), ID($pos))
1871 DEF_METHOD(Neg, sig_a.size(), ID($neg))
1872 DEF_METHOD(ReduceAnd, 1, ID($reduce_and))
1873 DEF_METHOD(ReduceOr, 1, ID($reduce_or))
1874 DEF_METHOD(ReduceXor, 1, ID($reduce_xor))
1875 DEF_METHOD(ReduceXnor, 1, ID($reduce_xnor))
1876 DEF_METHOD(ReduceBool, 1, ID($reduce_bool))
1877 DEF_METHOD(LogicNot, 1, ID($logic_not))
1878 #undef DEF_METHOD
1879
1880 #define DEF_METHOD(_func, _y_size, _type) \
1881 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed, const std::string &src) { \
1882 RTLIL::Cell *cell = addCell(name, _type); \
1883 cell->parameters[ID(A_SIGNED)] = is_signed; \
1884 cell->parameters[ID(B_SIGNED)] = is_signed; \
1885 cell->parameters[ID(A_WIDTH)] = sig_a.size(); \
1886 cell->parameters[ID(B_WIDTH)] = sig_b.size(); \
1887 cell->parameters[ID(Y_WIDTH)] = sig_y.size(); \
1888 cell->setPort(ID::A, sig_a); \
1889 cell->setPort(ID::B, sig_b); \
1890 cell->setPort(ID::Y, sig_y); \
1891 cell->set_src_attribute(src); \
1892 return cell; \
1893 } \
1894 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed, const std::string &src) { \
1895 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
1896 add ## _func(name, sig_a, sig_b, sig_y, is_signed, src); \
1897 return sig_y; \
1898 }
1899 DEF_METHOD(And, max(sig_a.size(), sig_b.size()), ID($and))
1900 DEF_METHOD(Or, max(sig_a.size(), sig_b.size()), ID($or))
1901 DEF_METHOD(Xor, max(sig_a.size(), sig_b.size()), ID($xor))
1902 DEF_METHOD(Xnor, max(sig_a.size(), sig_b.size()), ID($xnor))
1903 DEF_METHOD(Shift, sig_a.size(), ID($shift))
1904 DEF_METHOD(Shiftx, sig_a.size(), ID($shiftx))
1905 DEF_METHOD(Lt, 1, ID($lt))
1906 DEF_METHOD(Le, 1, ID($le))
1907 DEF_METHOD(Eq, 1, ID($eq))
1908 DEF_METHOD(Ne, 1, ID($ne))
1909 DEF_METHOD(Eqx, 1, ID($eqx))
1910 DEF_METHOD(Nex, 1, ID($nex))
1911 DEF_METHOD(Ge, 1, ID($ge))
1912 DEF_METHOD(Gt, 1, ID($gt))
1913 DEF_METHOD(Add, max(sig_a.size(), sig_b.size()), ID($add))
1914 DEF_METHOD(Sub, max(sig_a.size(), sig_b.size()), ID($sub))
1915 DEF_METHOD(Mul, max(sig_a.size(), sig_b.size()), ID($mul))
1916 DEF_METHOD(Div, max(sig_a.size(), sig_b.size()), ID($div))
1917 DEF_METHOD(Mod, max(sig_a.size(), sig_b.size()), ID($mod))
1918 DEF_METHOD(LogicAnd, 1, ID($logic_and))
1919 DEF_METHOD(LogicOr, 1, ID($logic_or))
1920 #undef DEF_METHOD
1921
1922 #define DEF_METHOD(_func, _y_size, _type) \
1923 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed, const std::string &src) { \
1924 RTLIL::Cell *cell = addCell(name, _type); \
1925 cell->parameters[ID(A_SIGNED)] = is_signed; \
1926 cell->parameters[ID(B_SIGNED)] = false; \
1927 cell->parameters[ID(A_WIDTH)] = sig_a.size(); \
1928 cell->parameters[ID(B_WIDTH)] = sig_b.size(); \
1929 cell->parameters[ID(Y_WIDTH)] = sig_y.size(); \
1930 cell->setPort(ID::A, sig_a); \
1931 cell->setPort(ID::B, sig_b); \
1932 cell->setPort(ID::Y, sig_y); \
1933 cell->set_src_attribute(src); \
1934 return cell; \
1935 } \
1936 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed, const std::string &src) { \
1937 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
1938 add ## _func(name, sig_a, sig_b, sig_y, is_signed, src); \
1939 return sig_y; \
1940 }
1941 DEF_METHOD(Shl, sig_a.size(), ID($shl))
1942 DEF_METHOD(Shr, sig_a.size(), ID($shr))
1943 DEF_METHOD(Sshl, sig_a.size(), ID($sshl))
1944 DEF_METHOD(Sshr, sig_a.size(), ID($sshr))
1945 #undef DEF_METHOD
1946
1947 #define DEF_METHOD(_func, _type, _pmux) \
1948 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, RTLIL::SigSpec sig_y, const std::string &src) { \
1949 RTLIL::Cell *cell = addCell(name, _type); \
1950 cell->parameters[ID(WIDTH)] = sig_a.size(); \
1951 if (_pmux) cell->parameters[ID(S_WIDTH)] = sig_s.size(); \
1952 cell->setPort(ID::A, sig_a); \
1953 cell->setPort(ID::B, sig_b); \
1954 cell->setPort(ID(S), sig_s); \
1955 cell->setPort(ID::Y, sig_y); \
1956 cell->set_src_attribute(src); \
1957 return cell; \
1958 } \
1959 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, const std::string &src) { \
1960 RTLIL::SigSpec sig_y = addWire(NEW_ID, sig_a.size()); \
1961 add ## _func(name, sig_a, sig_b, sig_s, sig_y, src); \
1962 return sig_y; \
1963 }
1964 DEF_METHOD(Mux, ID($mux), 0)
1965 DEF_METHOD(Pmux, ID($pmux), 1)
1966 #undef DEF_METHOD
1967
1968 #define DEF_METHOD_2(_func, _type, _P1, _P2) \
1969 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, const std::string &src) { \
1970 RTLIL::Cell *cell = addCell(name, _type); \
1971 cell->setPort("\\" #_P1, sig1); \
1972 cell->setPort("\\" #_P2, sig2); \
1973 cell->set_src_attribute(src); \
1974 return cell; \
1975 } \
1976 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, const std::string &src) { \
1977 RTLIL::SigBit sig2 = addWire(NEW_ID); \
1978 add ## _func(name, sig1, sig2, src); \
1979 return sig2; \
1980 }
1981 #define DEF_METHOD_3(_func, _type, _P1, _P2, _P3) \
1982 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, const std::string &src) { \
1983 RTLIL::Cell *cell = addCell(name, _type); \
1984 cell->setPort("\\" #_P1, sig1); \
1985 cell->setPort("\\" #_P2, sig2); \
1986 cell->setPort("\\" #_P3, sig3); \
1987 cell->set_src_attribute(src); \
1988 return cell; \
1989 } \
1990 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, const std::string &src) { \
1991 RTLIL::SigBit sig3 = addWire(NEW_ID); \
1992 add ## _func(name, sig1, sig2, sig3, src); \
1993 return sig3; \
1994 }
1995 #define DEF_METHOD_4(_func, _type, _P1, _P2, _P3, _P4) \
1996 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, RTLIL::SigBit sig4, const std::string &src) { \
1997 RTLIL::Cell *cell = addCell(name, _type); \
1998 cell->setPort("\\" #_P1, sig1); \
1999 cell->setPort("\\" #_P2, sig2); \
2000 cell->setPort("\\" #_P3, sig3); \
2001 cell->setPort("\\" #_P4, sig4); \
2002 cell->set_src_attribute(src); \
2003 return cell; \
2004 } \
2005 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, const std::string &src) { \
2006 RTLIL::SigBit sig4 = addWire(NEW_ID); \
2007 add ## _func(name, sig1, sig2, sig3, sig4, src); \
2008 return sig4; \
2009 }
2010 #define DEF_METHOD_5(_func, _type, _P1, _P2, _P3, _P4, _P5) \
2011 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, RTLIL::SigBit sig4, RTLIL::SigBit sig5, const std::string &src) { \
2012 RTLIL::Cell *cell = addCell(name, _type); \
2013 cell->setPort("\\" #_P1, sig1); \
2014 cell->setPort("\\" #_P2, sig2); \
2015 cell->setPort("\\" #_P3, sig3); \
2016 cell->setPort("\\" #_P4, sig4); \
2017 cell->setPort("\\" #_P5, sig5); \
2018 cell->set_src_attribute(src); \
2019 return cell; \
2020 } \
2021 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, RTLIL::SigBit sig4, const std::string &src) { \
2022 RTLIL::SigBit sig5 = addWire(NEW_ID); \
2023 add ## _func(name, sig1, sig2, sig3, sig4, sig5, src); \
2024 return sig5; \
2025 }
2026 DEF_METHOD_2(BufGate, ID($_BUF_), A, Y)
2027 DEF_METHOD_2(NotGate, ID($_NOT_), A, Y)
2028 DEF_METHOD_3(AndGate, ID($_AND_), A, B, Y)
2029 DEF_METHOD_3(NandGate, ID($_NAND_), A, B, Y)
2030 DEF_METHOD_3(OrGate, ID($_OR_), A, B, Y)
2031 DEF_METHOD_3(NorGate, ID($_NOR_), A, B, Y)
2032 DEF_METHOD_3(XorGate, ID($_XOR_), A, B, Y)
2033 DEF_METHOD_3(XnorGate, ID($_XNOR_), A, B, Y)
2034 DEF_METHOD_3(AndnotGate, ID($_ANDNOT_), A, B, Y)
2035 DEF_METHOD_3(OrnotGate, ID($_ORNOT_), A, B, Y)
2036 DEF_METHOD_4(MuxGate, ID($_MUX_), A, B, S, Y)
2037 DEF_METHOD_4(NmuxGate, ID($_NMUX_), A, B, S, Y)
2038 DEF_METHOD_4(Aoi3Gate, ID($_AOI3_), A, B, C, Y)
2039 DEF_METHOD_4(Oai3Gate, ID($_OAI3_), A, B, C, Y)
2040 DEF_METHOD_5(Aoi4Gate, ID($_AOI4_), A, B, C, D, Y)
2041 DEF_METHOD_5(Oai4Gate, ID($_OAI4_), A, B, C, D, Y)
2042 #undef DEF_METHOD_2
2043 #undef DEF_METHOD_3
2044 #undef DEF_METHOD_4
2045 #undef DEF_METHOD_5
2046
2047 RTLIL::Cell* RTLIL::Module::addPow(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool a_signed, bool b_signed, const std::string &src)
2048 {
2049 RTLIL::Cell *cell = addCell(name, ID($pow));
2050 cell->parameters[ID(A_SIGNED)] = a_signed;
2051 cell->parameters[ID(B_SIGNED)] = b_signed;
2052 cell->parameters[ID(A_WIDTH)] = sig_a.size();
2053 cell->parameters[ID(B_WIDTH)] = sig_b.size();
2054 cell->parameters[ID(Y_WIDTH)] = sig_y.size();
2055 cell->setPort(ID::A, sig_a);
2056 cell->setPort(ID::B, sig_b);
2057 cell->setPort(ID::Y, sig_y);
2058 cell->set_src_attribute(src);
2059 return cell;
2060 }
2061
2062 RTLIL::Cell* RTLIL::Module::addSlice(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, RTLIL::Const offset, const std::string &src)
2063 {
2064 RTLIL::Cell *cell = addCell(name, ID($slice));
2065 cell->parameters[ID(A_WIDTH)] = sig_a.size();
2066 cell->parameters[ID(Y_WIDTH)] = sig_y.size();
2067 cell->parameters[ID(OFFSET)] = offset;
2068 cell->setPort(ID::A, sig_a);
2069 cell->setPort(ID::Y, sig_y);
2070 cell->set_src_attribute(src);
2071 return cell;
2072 }
2073
2074 RTLIL::Cell* RTLIL::Module::addConcat(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, const std::string &src)
2075 {
2076 RTLIL::Cell *cell = addCell(name, ID($concat));
2077 cell->parameters[ID(A_WIDTH)] = sig_a.size();
2078 cell->parameters[ID(B_WIDTH)] = sig_b.size();
2079 cell->setPort(ID::A, sig_a);
2080 cell->setPort(ID::B, sig_b);
2081 cell->setPort(ID::Y, sig_y);
2082 cell->set_src_attribute(src);
2083 return cell;
2084 }
2085
2086 RTLIL::Cell* RTLIL::Module::addLut(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, RTLIL::Const lut, const std::string &src)
2087 {
2088 RTLIL::Cell *cell = addCell(name, ID($lut));
2089 cell->parameters[ID(LUT)] = lut;
2090 cell->parameters[ID(WIDTH)] = sig_a.size();
2091 cell->setPort(ID::A, sig_a);
2092 cell->setPort(ID::Y, sig_y);
2093 cell->set_src_attribute(src);
2094 return cell;
2095 }
2096
2097 RTLIL::Cell* RTLIL::Module::addTribuf(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_y, const std::string &src)
2098 {
2099 RTLIL::Cell *cell = addCell(name, ID($tribuf));
2100 cell->parameters[ID(WIDTH)] = sig_a.size();
2101 cell->setPort(ID::A, sig_a);
2102 cell->setPort(ID(EN), sig_en);
2103 cell->setPort(ID::Y, sig_y);
2104 cell->set_src_attribute(src);
2105 return cell;
2106 }
2107
2108 RTLIL::Cell* RTLIL::Module::addAssert(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src)
2109 {
2110 RTLIL::Cell *cell = addCell(name, ID($assert));
2111 cell->setPort(ID::A, sig_a);
2112 cell->setPort(ID(EN), sig_en);
2113 cell->set_src_attribute(src);
2114 return cell;
2115 }
2116
2117 RTLIL::Cell* RTLIL::Module::addAssume(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src)
2118 {
2119 RTLIL::Cell *cell = addCell(name, ID($assume));
2120 cell->setPort(ID::A, sig_a);
2121 cell->setPort(ID(EN), sig_en);
2122 cell->set_src_attribute(src);
2123 return cell;
2124 }
2125
2126 RTLIL::Cell* RTLIL::Module::addLive(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src)
2127 {
2128 RTLIL::Cell *cell = addCell(name, ID($live));
2129 cell->setPort(ID::A, sig_a);
2130 cell->setPort(ID(EN), sig_en);
2131 cell->set_src_attribute(src);
2132 return cell;
2133 }
2134
2135 RTLIL::Cell* RTLIL::Module::addFair(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src)
2136 {
2137 RTLIL::Cell *cell = addCell(name, ID($fair));
2138 cell->setPort(ID::A, sig_a);
2139 cell->setPort(ID(EN), sig_en);
2140 cell->set_src_attribute(src);
2141 return cell;
2142 }
2143
2144 RTLIL::Cell* RTLIL::Module::addCover(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src)
2145 {
2146 RTLIL::Cell *cell = addCell(name, ID($cover));
2147 cell->setPort(ID::A, sig_a);
2148 cell->setPort(ID(EN), sig_en);
2149 cell->set_src_attribute(src);
2150 return cell;
2151 }
2152
2153 RTLIL::Cell* RTLIL::Module::addEquiv(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, const std::string &src)
2154 {
2155 RTLIL::Cell *cell = addCell(name, ID($equiv));
2156 cell->setPort(ID::A, sig_a);
2157 cell->setPort(ID::B, sig_b);
2158 cell->setPort(ID::Y, sig_y);
2159 cell->set_src_attribute(src);
2160 return cell;
2161 }
2162
2163 RTLIL::Cell* RTLIL::Module::addSr(RTLIL::IdString name, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr, RTLIL::SigSpec sig_q, bool set_polarity, bool clr_polarity, const std::string &src)
2164 {
2165 RTLIL::Cell *cell = addCell(name, ID($sr));
2166 cell->parameters[ID(SET_POLARITY)] = set_polarity;
2167 cell->parameters[ID(CLR_POLARITY)] = clr_polarity;
2168 cell->parameters[ID(WIDTH)] = sig_q.size();
2169 cell->setPort(ID(SET), sig_set);
2170 cell->setPort(ID(CLR), sig_clr);
2171 cell->setPort(ID(Q), sig_q);
2172 cell->set_src_attribute(src);
2173 return cell;
2174 }
2175
2176 RTLIL::Cell* RTLIL::Module::addFf(RTLIL::IdString name, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, const std::string &src)
2177 {
2178 RTLIL::Cell *cell = addCell(name, ID($ff));
2179 cell->parameters[ID(WIDTH)] = sig_q.size();
2180 cell->setPort(ID(D), sig_d);
2181 cell->setPort(ID(Q), sig_q);
2182 cell->set_src_attribute(src);
2183 return cell;
2184 }
2185
2186 RTLIL::Cell* RTLIL::Module::addDff(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, const std::string &src)
2187 {
2188 RTLIL::Cell *cell = addCell(name, ID($dff));
2189 cell->parameters[ID(CLK_POLARITY)] = clk_polarity;
2190 cell->parameters[ID(WIDTH)] = sig_q.size();
2191 cell->setPort(ID(CLK), sig_clk);
2192 cell->setPort(ID(D), sig_d);
2193 cell->setPort(ID(Q), sig_q);
2194 cell->set_src_attribute(src);
2195 return cell;
2196 }
2197
2198 RTLIL::Cell* RTLIL::Module::addDffe(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, bool en_polarity, const std::string &src)
2199 {
2200 RTLIL::Cell *cell = addCell(name, ID($dffe));
2201 cell->parameters[ID(CLK_POLARITY)] = clk_polarity;
2202 cell->parameters[ID(EN_POLARITY)] = en_polarity;
2203 cell->parameters[ID(WIDTH)] = sig_q.size();
2204 cell->setPort(ID(CLK), sig_clk);
2205 cell->setPort(ID(EN), sig_en);
2206 cell->setPort(ID(D), sig_d);
2207 cell->setPort(ID(Q), sig_q);
2208 cell->set_src_attribute(src);
2209 return cell;
2210 }
2211
2212 RTLIL::Cell* RTLIL::Module::addDffsr(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
2213 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
2214 {
2215 RTLIL::Cell *cell = addCell(name, ID($dffsr));
2216 cell->parameters[ID(CLK_POLARITY)] = clk_polarity;
2217 cell->parameters[ID(SET_POLARITY)] = set_polarity;
2218 cell->parameters[ID(CLR_POLARITY)] = clr_polarity;
2219 cell->parameters[ID(WIDTH)] = sig_q.size();
2220 cell->setPort(ID(CLK), sig_clk);
2221 cell->setPort(ID(SET), sig_set);
2222 cell->setPort(ID(CLR), sig_clr);
2223 cell->setPort(ID(D), sig_d);
2224 cell->setPort(ID(Q), sig_q);
2225 cell->set_src_attribute(src);
2226 return cell;
2227 }
2228
2229 RTLIL::Cell* RTLIL::Module::addAdff(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_arst, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q,
2230 RTLIL::Const arst_value, bool clk_polarity, bool arst_polarity, const std::string &src)
2231 {
2232 RTLIL::Cell *cell = addCell(name, ID($adff));
2233 cell->parameters[ID(CLK_POLARITY)] = clk_polarity;
2234 cell->parameters[ID(ARST_POLARITY)] = arst_polarity;
2235 cell->parameters[ID(ARST_VALUE)] = arst_value;
2236 cell->parameters[ID(WIDTH)] = sig_q.size();
2237 cell->setPort(ID(CLK), sig_clk);
2238 cell->setPort(ID(ARST), sig_arst);
2239 cell->setPort(ID(D), sig_d);
2240 cell->setPort(ID(Q), sig_q);
2241 cell->set_src_attribute(src);
2242 return cell;
2243 }
2244
2245 RTLIL::Cell* RTLIL::Module::addDlatch(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity, const std::string &src)
2246 {
2247 RTLIL::Cell *cell = addCell(name, ID($dlatch));
2248 cell->parameters[ID(EN_POLARITY)] = en_polarity;
2249 cell->parameters[ID(WIDTH)] = sig_q.size();
2250 cell->setPort(ID(EN), sig_en);
2251 cell->setPort(ID(D), sig_d);
2252 cell->setPort(ID(Q), sig_q);
2253 cell->set_src_attribute(src);
2254 return cell;
2255 }
2256
2257 RTLIL::Cell* RTLIL::Module::addDlatchsr(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
2258 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
2259 {
2260 RTLIL::Cell *cell = addCell(name, ID($dlatchsr));
2261 cell->parameters[ID(EN_POLARITY)] = en_polarity;
2262 cell->parameters[ID(SET_POLARITY)] = set_polarity;
2263 cell->parameters[ID(CLR_POLARITY)] = clr_polarity;
2264 cell->parameters[ID(WIDTH)] = sig_q.size();
2265 cell->setPort(ID(EN), sig_en);
2266 cell->setPort(ID(SET), sig_set);
2267 cell->setPort(ID(CLR), sig_clr);
2268 cell->setPort(ID(D), sig_d);
2269 cell->setPort(ID(Q), sig_q);
2270 cell->set_src_attribute(src);
2271 return cell;
2272 }
2273
2274 RTLIL::Cell* RTLIL::Module::addFfGate(RTLIL::IdString name, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, const std::string &src)
2275 {
2276 RTLIL::Cell *cell = addCell(name, ID($_FF_));
2277 cell->setPort(ID(D), sig_d);
2278 cell->setPort(ID(Q), sig_q);
2279 cell->set_src_attribute(src);
2280 return cell;
2281 }
2282
2283 RTLIL::Cell* RTLIL::Module::addDffGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, const std::string &src)
2284 {
2285 RTLIL::Cell *cell = addCell(name, stringf("$_DFF_%c_", clk_polarity ? 'P' : 'N'));
2286 cell->setPort(ID(C), sig_clk);
2287 cell->setPort(ID(D), sig_d);
2288 cell->setPort(ID(Q), sig_q);
2289 cell->set_src_attribute(src);
2290 return cell;
2291 }
2292
2293 RTLIL::Cell* RTLIL::Module::addDffeGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, bool en_polarity, const std::string &src)
2294 {
2295 RTLIL::Cell *cell = addCell(name, stringf("$_DFFE_%c%c_", clk_polarity ? 'P' : 'N', en_polarity ? 'P' : 'N'));
2296 cell->setPort(ID(C), sig_clk);
2297 cell->setPort(ID(E), sig_en);
2298 cell->setPort(ID(D), sig_d);
2299 cell->setPort(ID(Q), sig_q);
2300 cell->set_src_attribute(src);
2301 return cell;
2302 }
2303
2304 RTLIL::Cell* RTLIL::Module::addDffsrGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
2305 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
2306 {
2307 RTLIL::Cell *cell = addCell(name, stringf("$_DFFSR_%c%c%c_", clk_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N'));
2308 cell->setPort(ID(C), sig_clk);
2309 cell->setPort(ID(S), sig_set);
2310 cell->setPort(ID(R), sig_clr);
2311 cell->setPort(ID(D), sig_d);
2312 cell->setPort(ID(Q), sig_q);
2313 cell->set_src_attribute(src);
2314 return cell;
2315 }
2316
2317 RTLIL::Cell* RTLIL::Module::addAdffGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_arst, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q,
2318 bool arst_value, bool clk_polarity, bool arst_polarity, const std::string &src)
2319 {
2320 RTLIL::Cell *cell = addCell(name, stringf("$_DFF_%c%c%c_", clk_polarity ? 'P' : 'N', arst_polarity ? 'P' : 'N', arst_value ? '1' : '0'));
2321 cell->setPort(ID(C), sig_clk);
2322 cell->setPort(ID(R), sig_arst);
2323 cell->setPort(ID(D), sig_d);
2324 cell->setPort(ID(Q), sig_q);
2325 cell->set_src_attribute(src);
2326 return cell;
2327 }
2328
2329 RTLIL::Cell* RTLIL::Module::addDlatchGate(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity, const std::string &src)
2330 {
2331 RTLIL::Cell *cell = addCell(name, stringf("$_DLATCH_%c_", en_polarity ? 'P' : 'N'));
2332 cell->setPort(ID(E), sig_en);
2333 cell->setPort(ID(D), sig_d);
2334 cell->setPort(ID(Q), sig_q);
2335 cell->set_src_attribute(src);
2336 return cell;
2337 }
2338
2339 RTLIL::Cell* RTLIL::Module::addDlatchsrGate(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
2340 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
2341 {
2342 RTLIL::Cell *cell = addCell(name, stringf("$_DLATCHSR_%c%c%c_", en_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N'));
2343 cell->setPort(ID(E), sig_en);
2344 cell->setPort(ID(S), sig_set);
2345 cell->setPort(ID(R), sig_clr);
2346 cell->setPort(ID(D), sig_d);
2347 cell->setPort(ID(Q), sig_q);
2348 cell->set_src_attribute(src);
2349 return cell;
2350 }
2351
2352 RTLIL::SigSpec RTLIL::Module::Anyconst(RTLIL::IdString name, int width, const std::string &src)
2353 {
2354 RTLIL::SigSpec sig = addWire(NEW_ID, width);
2355 Cell *cell = addCell(name, ID($anyconst));
2356 cell->setParam(ID(WIDTH), width);
2357 cell->setPort(ID::Y, sig);
2358 cell->set_src_attribute(src);
2359 return sig;
2360 }
2361
2362 RTLIL::SigSpec RTLIL::Module::Anyseq(RTLIL::IdString name, int width, const std::string &src)
2363 {
2364 RTLIL::SigSpec sig = addWire(NEW_ID, width);
2365 Cell *cell = addCell(name, ID($anyseq));
2366 cell->setParam(ID(WIDTH), width);
2367 cell->setPort(ID::Y, sig);
2368 cell->set_src_attribute(src);
2369 return sig;
2370 }
2371
2372 RTLIL::SigSpec RTLIL::Module::Allconst(RTLIL::IdString name, int width, const std::string &src)
2373 {
2374 RTLIL::SigSpec sig = addWire(NEW_ID, width);
2375 Cell *cell = addCell(name, ID($allconst));
2376 cell->setParam(ID(WIDTH), width);
2377 cell->setPort(ID::Y, sig);
2378 cell->set_src_attribute(src);
2379 return sig;
2380 }
2381
2382 RTLIL::SigSpec RTLIL::Module::Allseq(RTLIL::IdString name, int width, const std::string &src)
2383 {
2384 RTLIL::SigSpec sig = addWire(NEW_ID, width);
2385 Cell *cell = addCell(name, ID($allseq));
2386 cell->setParam(ID(WIDTH), width);
2387 cell->setPort(ID::Y, sig);
2388 cell->set_src_attribute(src);
2389 return sig;
2390 }
2391
2392 RTLIL::SigSpec RTLIL::Module::Initstate(RTLIL::IdString name, const std::string &src)
2393 {
2394 RTLIL::SigSpec sig = addWire(NEW_ID);
2395 Cell *cell = addCell(name, ID($initstate));
2396 cell->setPort(ID::Y, sig);
2397 cell->set_src_attribute(src);
2398 return sig;
2399 }
2400
2401 RTLIL::Wire::Wire()
2402 {
2403 static unsigned int hashidx_count = 123456789;
2404 hashidx_count = mkhash_xorshift(hashidx_count);
2405 hashidx_ = hashidx_count;
2406
2407 module = nullptr;
2408 width = 1;
2409 start_offset = 0;
2410 port_id = 0;
2411 port_input = false;
2412 port_output = false;
2413 upto = false;
2414
2415 #ifdef WITH_PYTHON
2416 RTLIL::Wire::get_all_wires()->insert(std::pair<unsigned int, RTLIL::Wire*>(hashidx_, this));
2417 #endif
2418 }
2419
2420 RTLIL::Wire::~Wire()
2421 {
2422 #ifdef WITH_PYTHON
2423 RTLIL::Wire::get_all_wires()->erase(hashidx_);
2424 #endif
2425 }
2426
2427 #ifdef WITH_PYTHON
2428 static std::map<unsigned int, RTLIL::Wire*> all_wires;
2429 std::map<unsigned int, RTLIL::Wire*> *RTLIL::Wire::get_all_wires(void)
2430 {
2431 return &all_wires;
2432 }
2433 #endif
2434
2435 RTLIL::Memory::Memory()
2436 {
2437 static unsigned int hashidx_count = 123456789;
2438 hashidx_count = mkhash_xorshift(hashidx_count);
2439 hashidx_ = hashidx_count;
2440
2441 width = 1;
2442 start_offset = 0;
2443 size = 0;
2444 #ifdef WITH_PYTHON
2445 RTLIL::Memory::get_all_memorys()->insert(std::pair<unsigned int, RTLIL::Memory*>(hashidx_, this));
2446 #endif
2447 }
2448
2449 RTLIL::Cell::Cell() : module(nullptr)
2450 {
2451 static unsigned int hashidx_count = 123456789;
2452 hashidx_count = mkhash_xorshift(hashidx_count);
2453 hashidx_ = hashidx_count;
2454
2455 // log("#memtrace# %p\n", this);
2456 memhasher();
2457
2458 #ifdef WITH_PYTHON
2459 RTLIL::Cell::get_all_cells()->insert(std::pair<unsigned int, RTLIL::Cell*>(hashidx_, this));
2460 #endif
2461 }
2462
2463 RTLIL::Cell::~Cell()
2464 {
2465 #ifdef WITH_PYTHON
2466 RTLIL::Cell::get_all_cells()->erase(hashidx_);
2467 #endif
2468 }
2469
2470 #ifdef WITH_PYTHON
2471 static std::map<unsigned int, RTLIL::Cell*> all_cells;
2472 std::map<unsigned int, RTLIL::Cell*> *RTLIL::Cell::get_all_cells(void)
2473 {
2474 return &all_cells;
2475 }
2476 #endif
2477
2478 bool RTLIL::Cell::hasPort(RTLIL::IdString portname) const
2479 {
2480 return connections_.count(portname) != 0;
2481 }
2482
2483 void RTLIL::Cell::unsetPort(RTLIL::IdString portname)
2484 {
2485 RTLIL::SigSpec signal;
2486 auto conn_it = connections_.find(portname);
2487
2488 if (conn_it != connections_.end())
2489 {
2490 for (auto mon : module->monitors)
2491 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
2492
2493 if (module->design)
2494 for (auto mon : module->design->monitors)
2495 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
2496
2497 if (yosys_xtrace) {
2498 log("#X# Unconnect %s.%s.%s\n", log_id(this->module), log_id(this), log_id(portname));
2499 log_backtrace("-X- ", yosys_xtrace-1);
2500 }
2501
2502 connections_.erase(conn_it);
2503 }
2504 }
2505
2506 void RTLIL::Cell::setPort(RTLIL::IdString portname, RTLIL::SigSpec signal)
2507 {
2508 auto conn_it = connections_.find(portname);
2509
2510 if (conn_it == connections_.end()) {
2511 connections_[portname] = RTLIL::SigSpec();
2512 conn_it = connections_.find(portname);
2513 log_assert(conn_it != connections_.end());
2514 } else
2515 if (conn_it->second == signal)
2516 return;
2517
2518 for (auto mon : module->monitors)
2519 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
2520
2521 if (module->design)
2522 for (auto mon : module->design->monitors)
2523 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
2524
2525 if (yosys_xtrace) {
2526 log("#X# Connect %s.%s.%s = %s (%d)\n", log_id(this->module), log_id(this), log_id(portname), log_signal(signal), GetSize(signal));
2527 log_backtrace("-X- ", yosys_xtrace-1);
2528 }
2529
2530 conn_it->second = signal;
2531 }
2532
2533 const RTLIL::SigSpec &RTLIL::Cell::getPort(RTLIL::IdString portname) const
2534 {
2535 return connections_.at(portname);
2536 }
2537
2538 const dict<RTLIL::IdString, RTLIL::SigSpec> &RTLIL::Cell::connections() const
2539 {
2540 return connections_;
2541 }
2542
2543 bool RTLIL::Cell::known() const
2544 {
2545 if (yosys_celltypes.cell_known(type))
2546 return true;
2547 if (module && module->design && module->design->module(type))
2548 return true;
2549 return false;
2550 }
2551
2552 bool RTLIL::Cell::input(RTLIL::IdString portname) const
2553 {
2554 if (yosys_celltypes.cell_known(type))
2555 return yosys_celltypes.cell_input(type, portname);
2556 if (module && module->design) {
2557 RTLIL::Module *m = module->design->module(type);
2558 RTLIL::Wire *w = m ? m->wire(portname) : nullptr;
2559 return w && w->port_input;
2560 }
2561 return false;
2562 }
2563
2564 bool RTLIL::Cell::output(RTLIL::IdString portname) const
2565 {
2566 if (yosys_celltypes.cell_known(type))
2567 return yosys_celltypes.cell_output(type, portname);
2568 if (module && module->design) {
2569 RTLIL::Module *m = module->design->module(type);
2570 RTLIL::Wire *w = m ? m->wire(portname) : nullptr;
2571 return w && w->port_output;
2572 }
2573 return false;
2574 }
2575
2576 bool RTLIL::Cell::hasParam(RTLIL::IdString paramname) const
2577 {
2578 return parameters.count(paramname) != 0;
2579 }
2580
2581 void RTLIL::Cell::unsetParam(RTLIL::IdString paramname)
2582 {
2583 parameters.erase(paramname);
2584 }
2585
2586 void RTLIL::Cell::setParam(RTLIL::IdString paramname, RTLIL::Const value)
2587 {
2588 parameters[paramname] = value;
2589 }
2590
2591 const RTLIL::Const &RTLIL::Cell::getParam(RTLIL::IdString paramname) const
2592 {
2593 return parameters.at(paramname);
2594 }
2595
2596 void RTLIL::Cell::sort()
2597 {
2598 connections_.sort(sort_by_id_str());
2599 parameters.sort(sort_by_id_str());
2600 attributes.sort(sort_by_id_str());
2601 }
2602
2603 void RTLIL::Cell::check()
2604 {
2605 #ifndef NDEBUG
2606 InternalCellChecker checker(NULL, this);
2607 checker.check();
2608 #endif
2609 }
2610
2611 void RTLIL::Cell::fixup_parameters(bool set_a_signed, bool set_b_signed)
2612 {
2613 if (!type.begins_with("$") || type.begins_with("$_") || type.begins_with("$paramod") || type.begins_with("$fmcombine") ||
2614 type.begins_with("$verific$") || type.begins_with("$array:") || type.begins_with("$extern:"))
2615 return;
2616
2617 if (type == ID($mux) || type == ID($pmux)) {
2618 parameters[ID(WIDTH)] = GetSize(connections_[ID::Y]);
2619 if (type == ID($pmux))
2620 parameters[ID(S_WIDTH)] = GetSize(connections_[ID(S)]);
2621 check();
2622 return;
2623 }
2624
2625 if (type == ID($lut) || type == ID($sop)) {
2626 parameters[ID(WIDTH)] = GetSize(connections_[ID::A]);
2627 return;
2628 }
2629
2630 if (type == ID($fa)) {
2631 parameters[ID(WIDTH)] = GetSize(connections_[ID::Y]);
2632 return;
2633 }
2634
2635 if (type == ID($lcu)) {
2636 parameters[ID(WIDTH)] = GetSize(connections_[ID(CO)]);
2637 return;
2638 }
2639
2640 bool signedness_ab = !type.in(ID($slice), ID($concat), ID($macc));
2641
2642 if (connections_.count(ID::A)) {
2643 if (signedness_ab) {
2644 if (set_a_signed)
2645 parameters[ID(A_SIGNED)] = true;
2646 else if (parameters.count(ID(A_SIGNED)) == 0)
2647 parameters[ID(A_SIGNED)] = false;
2648 }
2649 parameters[ID(A_WIDTH)] = GetSize(connections_[ID::A]);
2650 }
2651
2652 if (connections_.count(ID::B)) {
2653 if (signedness_ab) {
2654 if (set_b_signed)
2655 parameters[ID(B_SIGNED)] = true;
2656 else if (parameters.count(ID(B_SIGNED)) == 0)
2657 parameters[ID(B_SIGNED)] = false;
2658 }
2659 parameters[ID(B_WIDTH)] = GetSize(connections_[ID::B]);
2660 }
2661
2662 if (connections_.count(ID::Y))
2663 parameters[ID(Y_WIDTH)] = GetSize(connections_[ID::Y]);
2664
2665 if (connections_.count(ID(Q)))
2666 parameters[ID(WIDTH)] = GetSize(connections_[ID(Q)]);
2667
2668 check();
2669 }
2670
2671 RTLIL::SigChunk::SigChunk()
2672 {
2673 wire = NULL;
2674 width = 0;
2675 offset = 0;
2676 }
2677
2678 RTLIL::SigChunk::SigChunk(const RTLIL::Const &value)
2679 {
2680 wire = NULL;
2681 data = value.bits;
2682 width = GetSize(data);
2683 offset = 0;
2684 }
2685
2686 RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire)
2687 {
2688 log_assert(wire != nullptr);
2689 this->wire = wire;
2690 this->width = wire->width;
2691 this->offset = 0;
2692 }
2693
2694 RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire, int offset, int width)
2695 {
2696 log_assert(wire != nullptr);
2697 this->wire = wire;
2698 this->width = width;
2699 this->offset = offset;
2700 }
2701
2702 RTLIL::SigChunk::SigChunk(const std::string &str)
2703 {
2704 wire = NULL;
2705 data = RTLIL::Const(str).bits;
2706 width = GetSize(data);
2707 offset = 0;
2708 }
2709
2710 RTLIL::SigChunk::SigChunk(int val, int width)
2711 {
2712 wire = NULL;
2713 data = RTLIL::Const(val, width).bits;
2714 this->width = GetSize(data);
2715 offset = 0;
2716 }
2717
2718 RTLIL::SigChunk::SigChunk(RTLIL::State bit, int width)
2719 {
2720 wire = NULL;
2721 data = RTLIL::Const(bit, width).bits;
2722 this->width = GetSize(data);
2723 offset = 0;
2724 }
2725
2726 RTLIL::SigChunk::SigChunk(RTLIL::SigBit bit)
2727 {
2728 wire = bit.wire;
2729 offset = 0;
2730 if (wire == NULL)
2731 data = RTLIL::Const(bit.data).bits;
2732 else
2733 offset = bit.offset;
2734 width = 1;
2735 }
2736
2737 RTLIL::SigChunk::SigChunk(const RTLIL::SigChunk &sigchunk) : data(sigchunk.data)
2738 {
2739 wire = sigchunk.wire;
2740 data = sigchunk.data;
2741 width = sigchunk.width;
2742 offset = sigchunk.offset;
2743 }
2744
2745 RTLIL::SigChunk RTLIL::SigChunk::extract(int offset, int length) const
2746 {
2747 RTLIL::SigChunk ret;
2748 if (wire) {
2749 ret.wire = wire;
2750 ret.offset = this->offset + offset;
2751 ret.width = length;
2752 } else {
2753 for (int i = 0; i < length; i++)
2754 ret.data.push_back(data[offset+i]);
2755 ret.width = length;
2756 }
2757 return ret;
2758 }
2759
2760 bool RTLIL::SigChunk::operator <(const RTLIL::SigChunk &other) const
2761 {
2762 if (wire && other.wire)
2763 if (wire->name != other.wire->name)
2764 return wire->name < other.wire->name;
2765
2766 if (wire != other.wire)
2767 return wire < other.wire;
2768
2769 if (offset != other.offset)
2770 return offset < other.offset;
2771
2772 if (width != other.width)
2773 return width < other.width;
2774
2775 return data < other.data;
2776 }
2777
2778 bool RTLIL::SigChunk::operator ==(const RTLIL::SigChunk &other) const
2779 {
2780 return wire == other.wire && width == other.width && offset == other.offset && data == other.data;
2781 }
2782
2783 bool RTLIL::SigChunk::operator !=(const RTLIL::SigChunk &other) const
2784 {
2785 if (*this == other)
2786 return false;
2787 return true;
2788 }
2789
2790 RTLIL::SigSpec::SigSpec()
2791 {
2792 width_ = 0;
2793 hash_ = 0;
2794 }
2795
2796 RTLIL::SigSpec::SigSpec(const RTLIL::SigSpec &other)
2797 {
2798 *this = other;
2799 }
2800
2801 RTLIL::SigSpec::SigSpec(std::initializer_list<RTLIL::SigSpec> parts)
2802 {
2803 cover("kernel.rtlil.sigspec.init.list");
2804
2805 width_ = 0;
2806 hash_ = 0;
2807
2808 std::vector<RTLIL::SigSpec> parts_vec(parts.begin(), parts.end());
2809 for (auto it = parts_vec.rbegin(); it != parts_vec.rend(); it++)
2810 append(*it);
2811 }
2812
2813 const RTLIL::SigSpec &RTLIL::SigSpec::operator=(const RTLIL::SigSpec &other)
2814 {
2815 cover("kernel.rtlil.sigspec.assign");
2816
2817 width_ = other.width_;
2818 hash_ = other.hash_;
2819 chunks_ = other.chunks_;
2820 bits_.clear();
2821
2822 if (!other.bits_.empty())
2823 {
2824 RTLIL::SigChunk *last = NULL;
2825 int last_end_offset = 0;
2826
2827 for (auto &bit : other.bits_) {
2828 if (last && bit.wire == last->wire) {
2829 if (bit.wire == NULL) {
2830 last->data.push_back(bit.data);
2831 last->width++;
2832 continue;
2833 } else if (last_end_offset == bit.offset) {
2834 last_end_offset++;
2835 last->width++;
2836 continue;
2837 }
2838 }
2839 chunks_.push_back(bit);
2840 last = &chunks_.back();
2841 last_end_offset = bit.offset + 1;
2842 }
2843
2844 check();
2845 }
2846
2847 return *this;
2848 }
2849
2850 RTLIL::SigSpec::SigSpec(const RTLIL::Const &value)
2851 {
2852 cover("kernel.rtlil.sigspec.init.const");
2853
2854 chunks_.push_back(RTLIL::SigChunk(value));
2855 width_ = chunks_.back().width;
2856 hash_ = 0;
2857 check();
2858 }
2859
2860 RTLIL::SigSpec::SigSpec(const RTLIL::SigChunk &chunk)
2861 {
2862 cover("kernel.rtlil.sigspec.init.chunk");
2863
2864 chunks_.push_back(chunk);
2865 width_ = chunks_.back().width;
2866 hash_ = 0;
2867 check();
2868 }
2869
2870 RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire)
2871 {
2872 cover("kernel.rtlil.sigspec.init.wire");
2873
2874 chunks_.push_back(RTLIL::SigChunk(wire));
2875 width_ = chunks_.back().width;
2876 hash_ = 0;
2877 check();
2878 }
2879
2880 RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire, int offset, int width)
2881 {
2882 cover("kernel.rtlil.sigspec.init.wire_part");
2883
2884 chunks_.push_back(RTLIL::SigChunk(wire, offset, width));
2885 width_ = chunks_.back().width;
2886 hash_ = 0;
2887 check();
2888 }
2889
2890 RTLIL::SigSpec::SigSpec(const std::string &str)
2891 {
2892 cover("kernel.rtlil.sigspec.init.str");
2893
2894 chunks_.push_back(RTLIL::SigChunk(str));
2895 width_ = chunks_.back().width;
2896 hash_ = 0;
2897 check();
2898 }
2899
2900 RTLIL::SigSpec::SigSpec(int val, int width)
2901 {
2902 cover("kernel.rtlil.sigspec.init.int");
2903
2904 chunks_.push_back(RTLIL::SigChunk(val, width));
2905 width_ = width;
2906 hash_ = 0;
2907 check();
2908 }
2909
2910 RTLIL::SigSpec::SigSpec(RTLIL::State bit, int width)
2911 {
2912 cover("kernel.rtlil.sigspec.init.state");
2913
2914 chunks_.push_back(RTLIL::SigChunk(bit, width));
2915 width_ = width;
2916 hash_ = 0;
2917 check();
2918 }
2919
2920 RTLIL::SigSpec::SigSpec(RTLIL::SigBit bit, int width)
2921 {
2922 cover("kernel.rtlil.sigspec.init.bit");
2923
2924 if (bit.wire == NULL)
2925 chunks_.push_back(RTLIL::SigChunk(bit.data, width));
2926 else
2927 for (int i = 0; i < width; i++)
2928 chunks_.push_back(bit);
2929 width_ = width;
2930 hash_ = 0;
2931 check();
2932 }
2933
2934 RTLIL::SigSpec::SigSpec(std::vector<RTLIL::SigChunk> chunks)
2935 {
2936 cover("kernel.rtlil.sigspec.init.stdvec_chunks");
2937
2938 width_ = 0;
2939 hash_ = 0;
2940 for (auto &c : chunks)
2941 append(c);
2942 check();
2943 }
2944
2945 RTLIL::SigSpec::SigSpec(std::vector<RTLIL::SigBit> bits)
2946 {
2947 cover("kernel.rtlil.sigspec.init.stdvec_bits");
2948
2949 width_ = 0;
2950 hash_ = 0;
2951 for (auto &bit : bits)
2952 append_bit(bit);
2953 check();
2954 }
2955
2956 RTLIL::SigSpec::SigSpec(pool<RTLIL::SigBit> bits)
2957 {
2958 cover("kernel.rtlil.sigspec.init.pool_bits");
2959
2960 width_ = 0;
2961 hash_ = 0;
2962 for (auto &bit : bits)
2963 append_bit(bit);
2964 check();
2965 }
2966
2967 RTLIL::SigSpec::SigSpec(std::set<RTLIL::SigBit> bits)
2968 {
2969 cover("kernel.rtlil.sigspec.init.stdset_bits");
2970
2971 width_ = 0;
2972 hash_ = 0;
2973 for (auto &bit : bits)
2974 append_bit(bit);
2975 check();
2976 }
2977
2978 RTLIL::SigSpec::SigSpec(bool bit)
2979 {
2980 cover("kernel.rtlil.sigspec.init.bool");
2981
2982 width_ = 0;
2983 hash_ = 0;
2984 append_bit(bit);
2985 check();
2986 }
2987
2988 void RTLIL::SigSpec::pack() const
2989 {
2990 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
2991
2992 if (that->bits_.empty())
2993 return;
2994
2995 cover("kernel.rtlil.sigspec.convert.pack");
2996 log_assert(that->chunks_.empty());
2997
2998 std::vector<RTLIL::SigBit> old_bits;
2999 old_bits.swap(that->bits_);
3000
3001 RTLIL::SigChunk *last = NULL;
3002 int last_end_offset = 0;
3003
3004 for (auto &bit : old_bits) {
3005 if (last && bit.wire == last->wire) {
3006 if (bit.wire == NULL) {
3007 last->data.push_back(bit.data);
3008 last->width++;
3009 continue;
3010 } else if (last_end_offset == bit.offset) {
3011 last_end_offset++;
3012 last->width++;
3013 continue;
3014 }
3015 }
3016 that->chunks_.push_back(bit);
3017 last = &that->chunks_.back();
3018 last_end_offset = bit.offset + 1;
3019 }
3020
3021 check();
3022 }
3023
3024 void RTLIL::SigSpec::unpack() const
3025 {
3026 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
3027
3028 if (that->chunks_.empty())
3029 return;
3030
3031 cover("kernel.rtlil.sigspec.convert.unpack");
3032 log_assert(that->bits_.empty());
3033
3034 that->bits_.reserve(that->width_);
3035 for (auto &c : that->chunks_)
3036 for (int i = 0; i < c.width; i++)
3037 that->bits_.push_back(RTLIL::SigBit(c, i));
3038
3039 that->chunks_.clear();
3040 that->hash_ = 0;
3041 }
3042
3043 void RTLIL::SigSpec::updhash() const
3044 {
3045 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
3046
3047 if (that->hash_ != 0)
3048 return;
3049
3050 cover("kernel.rtlil.sigspec.hash");
3051 that->pack();
3052
3053 that->hash_ = mkhash_init;
3054 for (auto &c : that->chunks_)
3055 if (c.wire == NULL) {
3056 for (auto &v : c.data)
3057 that->hash_ = mkhash(that->hash_, v);
3058 } else {
3059 that->hash_ = mkhash(that->hash_, c.wire->name.index_);
3060 that->hash_ = mkhash(that->hash_, c.offset);
3061 that->hash_ = mkhash(that->hash_, c.width);
3062 }
3063
3064 if (that->hash_ == 0)
3065 that->hash_ = 1;
3066 }
3067
3068 void RTLIL::SigSpec::sort()
3069 {
3070 unpack();
3071 cover("kernel.rtlil.sigspec.sort");
3072 std::sort(bits_.begin(), bits_.end());
3073 }
3074
3075 void RTLIL::SigSpec::sort_and_unify()
3076 {
3077 unpack();
3078 cover("kernel.rtlil.sigspec.sort_and_unify");
3079
3080 // A copy of the bits vector is used to prevent duplicating the logic from
3081 // SigSpec::SigSpec(std::vector<SigBit>). This incurrs an extra copy but
3082 // that isn't showing up as significant in profiles.
3083 std::vector<SigBit> unique_bits = bits_;
3084 std::sort(unique_bits.begin(), unique_bits.end());
3085 auto last = std::unique(unique_bits.begin(), unique_bits.end());
3086 unique_bits.erase(last, unique_bits.end());
3087
3088 *this = unique_bits;
3089 }
3090
3091 void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with)
3092 {
3093 replace(pattern, with, this);
3094 }
3095
3096 void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with, RTLIL::SigSpec *other) const
3097 {
3098 log_assert(other != NULL);
3099 log_assert(width_ == other->width_);
3100 log_assert(pattern.width_ == with.width_);
3101
3102 pattern.unpack();
3103 with.unpack();
3104 unpack();
3105 other->unpack();
3106
3107 for (int i = 0; i < GetSize(pattern.bits_); i++) {
3108 if (pattern.bits_[i].wire != NULL) {
3109 for (int j = 0; j < GetSize(bits_); j++) {
3110 if (bits_[j] == pattern.bits_[i]) {
3111 other->bits_[j] = with.bits_[i];
3112 }
3113 }
3114 }
3115 }
3116
3117 other->check();
3118 }
3119
3120 void RTLIL::SigSpec::replace(const dict<RTLIL::SigBit, RTLIL::SigBit> &rules)
3121 {
3122 replace(rules, this);
3123 }
3124
3125 void RTLIL::SigSpec::replace(const dict<RTLIL::SigBit, RTLIL::SigBit> &rules, RTLIL::SigSpec *other) const
3126 {
3127 cover("kernel.rtlil.sigspec.replace_dict");
3128
3129 log_assert(other != NULL);
3130 log_assert(width_ == other->width_);
3131
3132 if (rules.empty()) return;
3133 unpack();
3134 other->unpack();
3135
3136 for (int i = 0; i < GetSize(bits_); i++) {
3137 auto it = rules.find(bits_[i]);
3138 if (it != rules.end())
3139 other->bits_[i] = it->second;
3140 }
3141
3142 other->check();
3143 }
3144
3145 void RTLIL::SigSpec::replace(const std::map<RTLIL::SigBit, RTLIL::SigBit> &rules)
3146 {
3147 replace(rules, this);
3148 }
3149
3150 void RTLIL::SigSpec::replace(const std::map<RTLIL::SigBit, RTLIL::SigBit> &rules, RTLIL::SigSpec *other) const
3151 {
3152 cover("kernel.rtlil.sigspec.replace_map");
3153
3154 log_assert(other != NULL);
3155 log_assert(width_ == other->width_);
3156
3157 if (rules.empty()) return;
3158 unpack();
3159 other->unpack();
3160
3161 for (int i = 0; i < GetSize(bits_); i++) {
3162 auto it = rules.find(bits_[i]);
3163 if (it != rules.end())
3164 other->bits_[i] = it->second;
3165 }
3166
3167 other->check();
3168 }
3169
3170 void RTLIL::SigSpec::remove(const RTLIL::SigSpec &pattern)
3171 {
3172 remove2(pattern, NULL);
3173 }
3174
3175 void RTLIL::SigSpec::remove(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other) const
3176 {
3177 RTLIL::SigSpec tmp = *this;
3178 tmp.remove2(pattern, other);
3179 }
3180
3181 void RTLIL::SigSpec::remove2(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other)
3182 {
3183 if (other)
3184 cover("kernel.rtlil.sigspec.remove_other");
3185 else
3186 cover("kernel.rtlil.sigspec.remove");
3187
3188 unpack();
3189 if (other != NULL) {
3190 log_assert(width_ == other->width_);
3191 other->unpack();
3192 }
3193
3194 for (int i = GetSize(bits_) - 1; i >= 0; i--)
3195 {
3196 if (bits_[i].wire == NULL) continue;
3197
3198 for (auto &pattern_chunk : pattern.chunks())
3199 if (bits_[i].wire == pattern_chunk.wire &&
3200 bits_[i].offset >= pattern_chunk.offset &&
3201 bits_[i].offset < pattern_chunk.offset + pattern_chunk.width) {
3202 bits_.erase(bits_.begin() + i);
3203 width_--;
3204 if (other != NULL) {
3205 other->bits_.erase(other->bits_.begin() + i);
3206 other->width_--;
3207 }
3208 break;
3209 }
3210 }
3211
3212 check();
3213 }
3214
3215 void RTLIL::SigSpec::remove(const pool<RTLIL::SigBit> &pattern)
3216 {
3217 remove2(pattern, NULL);
3218 }
3219
3220 void RTLIL::SigSpec::remove(const pool<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other) const
3221 {
3222 RTLIL::SigSpec tmp = *this;
3223 tmp.remove2(pattern, other);
3224 }
3225
3226 void RTLIL::SigSpec::remove2(const pool<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other)
3227 {
3228 if (other)
3229 cover("kernel.rtlil.sigspec.remove_other");
3230 else
3231 cover("kernel.rtlil.sigspec.remove");
3232
3233 unpack();
3234
3235 if (other != NULL) {
3236 log_assert(width_ == other->width_);
3237 other->unpack();
3238 }
3239
3240 for (int i = GetSize(bits_) - 1; i >= 0; i--) {
3241 if (bits_[i].wire != NULL && pattern.count(bits_[i])) {
3242 bits_.erase(bits_.begin() + i);
3243 width_--;
3244 if (other != NULL) {
3245 other->bits_.erase(other->bits_.begin() + i);
3246 other->width_--;
3247 }
3248 }
3249 }
3250
3251 check();
3252 }
3253
3254 void RTLIL::SigSpec::remove2(const std::set<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other)
3255 {
3256 if (other)
3257 cover("kernel.rtlil.sigspec.remove_other");
3258 else
3259 cover("kernel.rtlil.sigspec.remove");
3260
3261 unpack();
3262
3263 if (other != NULL) {
3264 log_assert(width_ == other->width_);
3265 other->unpack();
3266 }
3267
3268 for (int i = GetSize(bits_) - 1; i >= 0; i--) {
3269 if (bits_[i].wire != NULL && pattern.count(bits_[i])) {
3270 bits_.erase(bits_.begin() + i);
3271 width_--;
3272 if (other != NULL) {
3273 other->bits_.erase(other->bits_.begin() + i);
3274 other->width_--;
3275 }
3276 }
3277 }
3278
3279 check();
3280 }
3281
3282 RTLIL::SigSpec RTLIL::SigSpec::extract(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec *other) const
3283 {
3284 if (other)
3285 cover("kernel.rtlil.sigspec.extract_other");
3286 else
3287 cover("kernel.rtlil.sigspec.extract");
3288
3289 log_assert(other == NULL || width_ == other->width_);
3290
3291 RTLIL::SigSpec ret;
3292 std::vector<RTLIL::SigBit> bits_match = to_sigbit_vector();
3293
3294 for (auto& pattern_chunk : pattern.chunks()) {
3295 if (other) {
3296 std::vector<RTLIL::SigBit> bits_other = other->to_sigbit_vector();
3297 for (int i = 0; i < width_; i++)
3298 if (bits_match[i].wire &&
3299 bits_match[i].wire == pattern_chunk.wire &&
3300 bits_match[i].offset >= pattern_chunk.offset &&
3301 bits_match[i].offset < pattern_chunk.offset + pattern_chunk.width)
3302 ret.append_bit(bits_other[i]);
3303 } else {
3304 for (int i = 0; i < width_; i++)
3305 if (bits_match[i].wire &&
3306 bits_match[i].wire == pattern_chunk.wire &&
3307 bits_match[i].offset >= pattern_chunk.offset &&
3308 bits_match[i].offset < pattern_chunk.offset + pattern_chunk.width)
3309 ret.append_bit(bits_match[i]);
3310 }
3311 }
3312
3313 ret.check();
3314 return ret;
3315 }
3316
3317 RTLIL::SigSpec RTLIL::SigSpec::extract(const pool<RTLIL::SigBit> &pattern, const RTLIL::SigSpec *other) const
3318 {
3319 if (other)
3320 cover("kernel.rtlil.sigspec.extract_other");
3321 else
3322 cover("kernel.rtlil.sigspec.extract");
3323
3324 log_assert(other == NULL || width_ == other->width_);
3325
3326 std::vector<RTLIL::SigBit> bits_match = to_sigbit_vector();
3327 RTLIL::SigSpec ret;
3328
3329 if (other) {
3330 std::vector<RTLIL::SigBit> bits_other = other->to_sigbit_vector();
3331 for (int i = 0; i < width_; i++)
3332 if (bits_match[i].wire && pattern.count(bits_match[i]))
3333 ret.append_bit(bits_other[i]);
3334 } else {
3335 for (int i = 0; i < width_; i++)
3336 if (bits_match[i].wire && pattern.count(bits_match[i]))
3337 ret.append_bit(bits_match[i]);
3338 }
3339
3340 ret.check();
3341 return ret;
3342 }
3343
3344 void RTLIL::SigSpec::replace(int offset, const RTLIL::SigSpec &with)
3345 {
3346 cover("kernel.rtlil.sigspec.replace_pos");
3347
3348 unpack();
3349 with.unpack();
3350
3351 log_assert(offset >= 0);
3352 log_assert(with.width_ >= 0);
3353 log_assert(offset+with.width_ <= width_);
3354
3355 for (int i = 0; i < with.width_; i++)
3356 bits_.at(offset + i) = with.bits_.at(i);
3357
3358 check();
3359 }
3360
3361 void RTLIL::SigSpec::remove_const()
3362 {
3363 if (packed())
3364 {
3365 cover("kernel.rtlil.sigspec.remove_const.packed");
3366
3367 std::vector<RTLIL::SigChunk> new_chunks;
3368 new_chunks.reserve(GetSize(chunks_));
3369
3370 width_ = 0;
3371 for (auto &chunk : chunks_)
3372 if (chunk.wire != NULL) {
3373 new_chunks.push_back(chunk);
3374 width_ += chunk.width;
3375 }
3376
3377 chunks_.swap(new_chunks);
3378 }
3379 else
3380 {
3381 cover("kernel.rtlil.sigspec.remove_const.unpacked");
3382
3383 std::vector<RTLIL::SigBit> new_bits;
3384 new_bits.reserve(width_);
3385
3386 for (auto &bit : bits_)
3387 if (bit.wire != NULL)
3388 new_bits.push_back(bit);
3389
3390 bits_.swap(new_bits);
3391 width_ = bits_.size();
3392 }
3393
3394 check();
3395 }
3396
3397 void RTLIL::SigSpec::remove(int offset, int length)
3398 {
3399 cover("kernel.rtlil.sigspec.remove_pos");
3400
3401 unpack();
3402
3403 log_assert(offset >= 0);
3404 log_assert(length >= 0);
3405 log_assert(offset + length <= width_);
3406
3407 bits_.erase(bits_.begin() + offset, bits_.begin() + offset + length);
3408 width_ = bits_.size();
3409
3410 check();
3411 }
3412
3413 RTLIL::SigSpec RTLIL::SigSpec::extract(int offset, int length) const
3414 {
3415 unpack();
3416 cover("kernel.rtlil.sigspec.extract_pos");
3417 return std::vector<RTLIL::SigBit>(bits_.begin() + offset, bits_.begin() + offset + length);
3418 }
3419
3420 void RTLIL::SigSpec::append(const RTLIL::SigSpec &signal)
3421 {
3422 if (signal.width_ == 0)
3423 return;
3424
3425 if (width_ == 0) {
3426 *this = signal;
3427 return;
3428 }
3429
3430 cover("kernel.rtlil.sigspec.append");
3431
3432 if (packed() != signal.packed()) {
3433 pack();
3434 signal.pack();
3435 }
3436
3437 if (packed())
3438 for (auto &other_c : signal.chunks_)
3439 {
3440 auto &my_last_c = chunks_.back();
3441 if (my_last_c.wire == NULL && other_c.wire == NULL) {
3442 auto &this_data = my_last_c.data;
3443 auto &other_data = other_c.data;
3444 this_data.insert(this_data.end(), other_data.begin(), other_data.end());
3445 my_last_c.width += other_c.width;
3446 } else
3447 if (my_last_c.wire == other_c.wire && my_last_c.offset + my_last_c.width == other_c.offset) {
3448 my_last_c.width += other_c.width;
3449 } else
3450 chunks_.push_back(other_c);
3451 }
3452 else
3453 bits_.insert(bits_.end(), signal.bits_.begin(), signal.bits_.end());
3454
3455 width_ += signal.width_;
3456 check();
3457 }
3458
3459 void RTLIL::SigSpec::append_bit(const RTLIL::SigBit &bit)
3460 {
3461 if (packed())
3462 {
3463 cover("kernel.rtlil.sigspec.append_bit.packed");
3464
3465 if (chunks_.size() == 0)
3466 chunks_.push_back(bit);
3467 else
3468 if (bit.wire == NULL)
3469 if (chunks_.back().wire == NULL) {
3470 chunks_.back().data.push_back(bit.data);
3471 chunks_.back().width++;
3472 } else
3473 chunks_.push_back(bit);
3474 else
3475 if (chunks_.back().wire == bit.wire && chunks_.back().offset + chunks_.back().width == bit.offset)
3476 chunks_.back().width++;
3477 else
3478 chunks_.push_back(bit);
3479 }
3480 else
3481 {
3482 cover("kernel.rtlil.sigspec.append_bit.unpacked");
3483 bits_.push_back(bit);
3484 }
3485
3486 width_++;
3487 check();
3488 }
3489
3490 void RTLIL::SigSpec::extend_u0(int width, bool is_signed)
3491 {
3492 cover("kernel.rtlil.sigspec.extend_u0");
3493
3494 pack();
3495
3496 if (width_ > width)
3497 remove(width, width_ - width);
3498
3499 if (width_ < width) {
3500 RTLIL::SigBit padding = width_ > 0 ? (*this)[width_ - 1] : RTLIL::State::Sx;
3501 if (!is_signed)
3502 padding = RTLIL::State::S0;
3503 while (width_ < width)
3504 append(padding);
3505 }
3506
3507 }
3508
3509 RTLIL::SigSpec RTLIL::SigSpec::repeat(int num) const
3510 {
3511 cover("kernel.rtlil.sigspec.repeat");
3512
3513 RTLIL::SigSpec sig;
3514 for (int i = 0; i < num; i++)
3515 sig.append(*this);
3516 return sig;
3517 }
3518
3519 #ifndef NDEBUG
3520 void RTLIL::SigSpec::check() const
3521 {
3522 if (width_ > 64)
3523 {
3524 cover("kernel.rtlil.sigspec.check.skip");
3525 }
3526 else if (packed())
3527 {
3528 cover("kernel.rtlil.sigspec.check.packed");
3529
3530 int w = 0;
3531 for (size_t i = 0; i < chunks_.size(); i++) {
3532 const RTLIL::SigChunk chunk = chunks_[i];
3533 if (chunk.wire == NULL) {
3534 if (i > 0)
3535 log_assert(chunks_[i-1].wire != NULL);
3536 log_assert(chunk.offset == 0);
3537 log_assert(chunk.data.size() == (size_t)chunk.width);
3538 } else {
3539 if (i > 0 && chunks_[i-1].wire == chunk.wire)
3540 log_assert(chunk.offset != chunks_[i-1].offset + chunks_[i-1].width);
3541 log_assert(chunk.offset >= 0);
3542 log_assert(chunk.width >= 0);
3543 log_assert(chunk.offset + chunk.width <= chunk.wire->width);
3544 log_assert(chunk.data.size() == 0);
3545 }
3546 w += chunk.width;
3547 }
3548 log_assert(w == width_);
3549 log_assert(bits_.empty());
3550 }
3551 else
3552 {
3553 cover("kernel.rtlil.sigspec.check.unpacked");
3554
3555 log_assert(width_ == GetSize(bits_));
3556 log_assert(chunks_.empty());
3557 }
3558 }
3559 #endif
3560
3561 bool RTLIL::SigSpec::operator <(const RTLIL::SigSpec &other) const
3562 {
3563 cover("kernel.rtlil.sigspec.comp_lt");
3564
3565 if (this == &other)
3566 return false;
3567
3568 if (width_ != other.width_)
3569 return width_ < other.width_;
3570
3571 pack();
3572 other.pack();
3573
3574 if (chunks_.size() != other.chunks_.size())
3575 return chunks_.size() < other.chunks_.size();
3576
3577 updhash();
3578 other.updhash();
3579
3580 if (hash_ != other.hash_)
3581 return hash_ < other.hash_;
3582
3583 for (size_t i = 0; i < chunks_.size(); i++)
3584 if (chunks_[i] != other.chunks_[i]) {
3585 cover("kernel.rtlil.sigspec.comp_lt.hash_collision");
3586 return chunks_[i] < other.chunks_[i];
3587 }
3588
3589 cover("kernel.rtlil.sigspec.comp_lt.equal");
3590 return false;
3591 }
3592
3593 bool RTLIL::SigSpec::operator ==(const RTLIL::SigSpec &other) const
3594 {
3595 cover("kernel.rtlil.sigspec.comp_eq");
3596
3597 if (this == &other)
3598 return true;
3599
3600 if (width_ != other.width_)
3601 return false;
3602
3603 // Without this, SigSpec() == SigSpec(State::S0, 0) will fail
3604 // since the RHS will contain one SigChunk of width 0 causing
3605 // the size check below to fail
3606 if (width_ == 0)
3607 return true;
3608
3609 pack();
3610 other.pack();
3611
3612 if (chunks_.size() != other.chunks_.size())
3613 return false;
3614
3615 updhash();
3616 other.updhash();
3617
3618 if (hash_ != other.hash_)
3619 return false;
3620
3621 for (size_t i = 0; i < chunks_.size(); i++)
3622 if (chunks_[i] != other.chunks_[i]) {
3623 cover("kernel.rtlil.sigspec.comp_eq.hash_collision");
3624 return false;
3625 }
3626
3627 cover("kernel.rtlil.sigspec.comp_eq.equal");
3628 return true;
3629 }
3630
3631 bool RTLIL::SigSpec::is_wire() const
3632 {
3633 cover("kernel.rtlil.sigspec.is_wire");
3634
3635 pack();
3636 return GetSize(chunks_) == 1 && chunks_[0].wire && chunks_[0].wire->width == width_;
3637 }
3638
3639 bool RTLIL::SigSpec::is_chunk() const
3640 {
3641 cover("kernel.rtlil.sigspec.is_chunk");
3642
3643 pack();
3644 return GetSize(chunks_) == 1;
3645 }
3646
3647 bool RTLIL::SigSpec::is_fully_const() const
3648 {
3649 cover("kernel.rtlil.sigspec.is_fully_const");
3650
3651 pack();
3652 for (auto it = chunks_.begin(); it != chunks_.end(); it++)
3653 if (it->width > 0 && it->wire != NULL)
3654 return false;
3655 return true;
3656 }
3657
3658 bool RTLIL::SigSpec::is_fully_zero() const
3659 {
3660 cover("kernel.rtlil.sigspec.is_fully_zero");
3661
3662 pack();
3663 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
3664 if (it->width > 0 && it->wire != NULL)
3665 return false;
3666 for (size_t i = 0; i < it->data.size(); i++)
3667 if (it->data[i] != RTLIL::State::S0)
3668 return false;
3669 }
3670 return true;
3671 }
3672
3673 bool RTLIL::SigSpec::is_fully_ones() const
3674 {
3675 cover("kernel.rtlil.sigspec.is_fully_ones");
3676
3677 pack();
3678 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
3679 if (it->width > 0 && it->wire != NULL)
3680 return false;
3681 for (size_t i = 0; i < it->data.size(); i++)
3682 if (it->data[i] != RTLIL::State::S1)
3683 return false;
3684 }
3685 return true;
3686 }
3687
3688 bool RTLIL::SigSpec::is_fully_def() const
3689 {
3690 cover("kernel.rtlil.sigspec.is_fully_def");
3691
3692 pack();
3693 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
3694 if (it->width > 0 && it->wire != NULL)
3695 return false;
3696 for (size_t i = 0; i < it->data.size(); i++)
3697 if (it->data[i] != RTLIL::State::S0 && it->data[i] != RTLIL::State::S1)
3698 return false;
3699 }
3700 return true;
3701 }
3702
3703 bool RTLIL::SigSpec::is_fully_undef() const
3704 {
3705 cover("kernel.rtlil.sigspec.is_fully_undef");
3706
3707 pack();
3708 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
3709 if (it->width > 0 && it->wire != NULL)
3710 return false;
3711 for (size_t i = 0; i < it->data.size(); i++)
3712 if (it->data[i] != RTLIL::State::Sx && it->data[i] != RTLIL::State::Sz)
3713 return false;
3714 }
3715 return true;
3716 }
3717
3718 bool RTLIL::SigSpec::has_const() const
3719 {
3720 cover("kernel.rtlil.sigspec.has_const");
3721
3722 pack();
3723 for (auto it = chunks_.begin(); it != chunks_.end(); it++)
3724 if (it->width > 0 && it->wire == NULL)
3725 return true;
3726 return false;
3727 }
3728
3729 bool RTLIL::SigSpec::has_marked_bits() const
3730 {
3731 cover("kernel.rtlil.sigspec.has_marked_bits");
3732
3733 pack();
3734 for (auto it = chunks_.begin(); it != chunks_.end(); it++)
3735 if (it->width > 0 && it->wire == NULL) {
3736 for (size_t i = 0; i < it->data.size(); i++)
3737 if (it->data[i] == RTLIL::State::Sm)
3738 return true;
3739 }
3740 return false;
3741 }
3742
3743 bool RTLIL::SigSpec::as_bool() const
3744 {
3745 cover("kernel.rtlil.sigspec.as_bool");
3746
3747 pack();
3748 log_assert(is_fully_const() && GetSize(chunks_) <= 1);
3749 if (width_)
3750 return RTLIL::Const(chunks_[0].data).as_bool();
3751 return false;
3752 }
3753
3754 int RTLIL::SigSpec::as_int(bool is_signed) const
3755 {
3756 cover("kernel.rtlil.sigspec.as_int");
3757
3758 pack();
3759 log_assert(is_fully_const() && GetSize(chunks_) <= 1);
3760 if (width_)
3761 return RTLIL::Const(chunks_[0].data).as_int(is_signed);
3762 return 0;
3763 }
3764
3765 std::string RTLIL::SigSpec::as_string() const
3766 {
3767 cover("kernel.rtlil.sigspec.as_string");
3768
3769 pack();
3770 std::string str;
3771 for (size_t i = chunks_.size(); i > 0; i--) {
3772 const RTLIL::SigChunk &chunk = chunks_[i-1];
3773 if (chunk.wire != NULL)
3774 for (int j = 0; j < chunk.width; j++)
3775 str += "?";
3776 else
3777 str += RTLIL::Const(chunk.data).as_string();
3778 }
3779 return str;
3780 }
3781
3782 RTLIL::Const RTLIL::SigSpec::as_const() const
3783 {
3784 cover("kernel.rtlil.sigspec.as_const");
3785
3786 pack();
3787 log_assert(is_fully_const() && GetSize(chunks_) <= 1);
3788 if (width_)
3789 return chunks_[0].data;
3790 return RTLIL::Const();
3791 }
3792
3793 RTLIL::Wire *RTLIL::SigSpec::as_wire() const
3794 {
3795 cover("kernel.rtlil.sigspec.as_wire");
3796
3797 pack();
3798 log_assert(is_wire());
3799 return chunks_[0].wire;
3800 }
3801
3802 RTLIL::SigChunk RTLIL::SigSpec::as_chunk() const
3803 {
3804 cover("kernel.rtlil.sigspec.as_chunk");
3805
3806 pack();
3807 log_assert(is_chunk());
3808 return chunks_[0];
3809 }
3810
3811 RTLIL::SigBit RTLIL::SigSpec::as_bit() const
3812 {
3813 cover("kernel.rtlil.sigspec.as_bit");
3814
3815 log_assert(width_ == 1);
3816 if (packed())
3817 return RTLIL::SigBit(*chunks_.begin());
3818 else
3819 return bits_[0];
3820 }
3821
3822 bool RTLIL::SigSpec::match(std::string pattern) const
3823 {
3824 cover("kernel.rtlil.sigspec.match");
3825
3826 pack();
3827 std::string str = as_string();
3828 log_assert(pattern.size() == str.size());
3829
3830 for (size_t i = 0; i < pattern.size(); i++) {
3831 if (pattern[i] == ' ')
3832 continue;
3833 if (pattern[i] == '*') {
3834 if (str[i] != 'z' && str[i] != 'x')
3835 return false;
3836 continue;
3837 }
3838 if (pattern[i] != str[i])
3839 return false;
3840 }
3841
3842 return true;
3843 }
3844
3845 std::set<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_set() const
3846 {
3847 cover("kernel.rtlil.sigspec.to_sigbit_set");
3848
3849 pack();
3850 std::set<RTLIL::SigBit> sigbits;
3851 for (auto &c : chunks_)
3852 for (int i = 0; i < c.width; i++)
3853 sigbits.insert(RTLIL::SigBit(c, i));
3854 return sigbits;
3855 }
3856
3857 pool<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_pool() const
3858 {
3859 cover("kernel.rtlil.sigspec.to_sigbit_pool");
3860
3861 pack();
3862 pool<RTLIL::SigBit> sigbits;
3863 for (auto &c : chunks_)
3864 for (int i = 0; i < c.width; i++)
3865 sigbits.insert(RTLIL::SigBit(c, i));
3866 return sigbits;
3867 }
3868
3869 std::vector<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_vector() const
3870 {
3871 cover("kernel.rtlil.sigspec.to_sigbit_vector");
3872
3873 unpack();
3874 return bits_;
3875 }
3876
3877 std::map<RTLIL::SigBit, RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_map(const RTLIL::SigSpec &other) const
3878 {
3879 cover("kernel.rtlil.sigspec.to_sigbit_map");
3880
3881 unpack();
3882 other.unpack();
3883
3884 log_assert(width_ == other.width_);
3885
3886 std::map<RTLIL::SigBit, RTLIL::SigBit> new_map;
3887 for (int i = 0; i < width_; i++)
3888 new_map[bits_[i]] = other.bits_[i];
3889
3890 return new_map;
3891 }
3892
3893 dict<RTLIL::SigBit, RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_dict(const RTLIL::SigSpec &other) const
3894 {
3895 cover("kernel.rtlil.sigspec.to_sigbit_dict");
3896
3897 unpack();
3898 other.unpack();
3899
3900 log_assert(width_ == other.width_);
3901
3902 dict<RTLIL::SigBit, RTLIL::SigBit> new_map;
3903 for (int i = 0; i < width_; i++)
3904 new_map[bits_[i]] = other.bits_[i];
3905
3906 return new_map;
3907 }
3908
3909 static void sigspec_parse_split(std::vector<std::string> &tokens, const std::string &text, char sep)
3910 {
3911 size_t start = 0, end = 0;
3912 while ((end = text.find(sep, start)) != std::string::npos) {
3913 tokens.push_back(text.substr(start, end - start));
3914 start = end + 1;
3915 }
3916 tokens.push_back(text.substr(start));
3917 }
3918
3919 static int sigspec_parse_get_dummy_line_num()
3920 {
3921 return 0;
3922 }
3923
3924 bool RTLIL::SigSpec::parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str)
3925 {
3926 cover("kernel.rtlil.sigspec.parse");
3927
3928 AST::current_filename = "input";
3929
3930 std::vector<std::string> tokens;
3931 sigspec_parse_split(tokens, str, ',');
3932
3933 sig = RTLIL::SigSpec();
3934 for (int tokidx = int(tokens.size())-1; tokidx >= 0; tokidx--)
3935 {
3936 std::string netname = tokens[tokidx];
3937 std::string indices;
3938
3939 if (netname.size() == 0)
3940 continue;
3941
3942 if (('0' <= netname[0] && netname[0] <= '9') || netname[0] == '\'') {
3943 cover("kernel.rtlil.sigspec.parse.const");
3944 AST::get_line_num = sigspec_parse_get_dummy_line_num;
3945 AST::AstNode *ast = VERILOG_FRONTEND::const2ast(netname);
3946 if (ast == NULL)
3947 return false;
3948 sig.append(RTLIL::Const(ast->bits));
3949 delete ast;
3950 continue;
3951 }
3952
3953 if (module == NULL)
3954 return false;
3955
3956 cover("kernel.rtlil.sigspec.parse.net");
3957
3958 if (netname[0] != '$' && netname[0] != '\\')
3959 netname = "\\" + netname;
3960
3961 if (module->wires_.count(netname) == 0) {
3962 size_t indices_pos = netname.size()-1;
3963 if (indices_pos > 2 && netname[indices_pos] == ']')
3964 {
3965 indices_pos--;
3966 while (indices_pos > 0 && ('0' <= netname[indices_pos] && netname[indices_pos] <= '9')) indices_pos--;
3967 if (indices_pos > 0 && netname[indices_pos] == ':') {
3968 indices_pos--;
3969 while (indices_pos > 0 && ('0' <= netname[indices_pos] && netname[indices_pos] <= '9')) indices_pos--;
3970 }
3971 if (indices_pos > 0 && netname[indices_pos] == '[') {
3972 indices = netname.substr(indices_pos);
3973 netname = netname.substr(0, indices_pos);
3974 }
3975 }
3976 }
3977
3978 if (module->wires_.count(netname) == 0)
3979 return false;
3980
3981 RTLIL::Wire *wire = module->wires_.at(netname);
3982 if (!indices.empty()) {
3983 std::vector<std::string> index_tokens;
3984 sigspec_parse_split(index_tokens, indices.substr(1, indices.size()-2), ':');
3985 if (index_tokens.size() == 1) {
3986 cover("kernel.rtlil.sigspec.parse.bit_sel");
3987 int a = atoi(index_tokens.at(0).c_str());
3988 if (a < 0 || a >= wire->width)
3989 return false;
3990 sig.append(RTLIL::SigSpec(wire, a));
3991 } else {
3992 cover("kernel.rtlil.sigspec.parse.part_sel");
3993 int a = atoi(index_tokens.at(0).c_str());
3994 int b = atoi(index_tokens.at(1).c_str());
3995 if (a > b) {
3996 int tmp = a;
3997 a = b, b = tmp;
3998 }
3999 if (a < 0 || a >= wire->width)
4000 return false;
4001 if (b < 0 || b >= wire->width)
4002 return false;
4003 sig.append(RTLIL::SigSpec(wire, a, b-a+1));
4004 }
4005 } else
4006 sig.append(wire);
4007 }
4008
4009 return true;
4010 }
4011
4012 bool RTLIL::SigSpec::parse_sel(RTLIL::SigSpec &sig, RTLIL::Design *design, RTLIL::Module *module, std::string str)
4013 {
4014 if (str.empty() || str[0] != '@')
4015 return parse(sig, module, str);
4016
4017 cover("kernel.rtlil.sigspec.parse.sel");
4018
4019 str = RTLIL::escape_id(str.substr(1));
4020 if (design->selection_vars.count(str) == 0)
4021 return false;
4022
4023 sig = RTLIL::SigSpec();
4024 RTLIL::Selection &sel = design->selection_vars.at(str);
4025 for (auto &it : module->wires_)
4026 if (sel.selected_member(module->name, it.first))
4027 sig.append(it.second);
4028
4029 return true;
4030 }
4031
4032 bool RTLIL::SigSpec::parse_rhs(const RTLIL::SigSpec &lhs, RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str)
4033 {
4034 if (str == "0") {
4035 cover("kernel.rtlil.sigspec.parse.rhs_zeros");
4036 sig = RTLIL::SigSpec(RTLIL::State::S0, lhs.width_);
4037 return true;
4038 }
4039
4040 if (str == "~0") {
4041 cover("kernel.rtlil.sigspec.parse.rhs_ones");
4042 sig = RTLIL::SigSpec(RTLIL::State::S1, lhs.width_);
4043 return true;
4044 }
4045
4046 if (lhs.chunks_.size() == 1) {
4047 char *p = (char*)str.c_str(), *endptr;
4048 long int val = strtol(p, &endptr, 10);
4049 if (endptr && endptr != p && *endptr == 0) {
4050 sig = RTLIL::SigSpec(val, lhs.width_);
4051 cover("kernel.rtlil.sigspec.parse.rhs_dec");
4052 return true;
4053 }
4054 }
4055
4056 return parse(sig, module, str);
4057 }
4058
4059 RTLIL::CaseRule::~CaseRule()
4060 {
4061 for (auto it = switches.begin(); it != switches.end(); it++)
4062 delete *it;
4063 }
4064
4065 bool RTLIL::CaseRule::empty() const
4066 {
4067 return actions.empty() && switches.empty();
4068 }
4069
4070 RTLIL::CaseRule *RTLIL::CaseRule::clone() const
4071 {
4072 RTLIL::CaseRule *new_caserule = new RTLIL::CaseRule;
4073 new_caserule->compare = compare;
4074 new_caserule->actions = actions;
4075 for (auto &it : switches)
4076 new_caserule->switches.push_back(it->clone());
4077 return new_caserule;
4078 }
4079
4080 RTLIL::SwitchRule::~SwitchRule()
4081 {
4082 for (auto it = cases.begin(); it != cases.end(); it++)
4083 delete *it;
4084 }
4085
4086 bool RTLIL::SwitchRule::empty() const
4087 {
4088 return cases.empty();
4089 }
4090
4091 RTLIL::SwitchRule *RTLIL::SwitchRule::clone() const
4092 {
4093 RTLIL::SwitchRule *new_switchrule = new RTLIL::SwitchRule;
4094 new_switchrule->signal = signal;
4095 new_switchrule->attributes = attributes;
4096 for (auto &it : cases)
4097 new_switchrule->cases.push_back(it->clone());
4098 return new_switchrule;
4099
4100 }
4101
4102 RTLIL::SyncRule *RTLIL::SyncRule::clone() const
4103 {
4104 RTLIL::SyncRule *new_syncrule = new RTLIL::SyncRule;
4105 new_syncrule->type = type;
4106 new_syncrule->signal = signal;
4107 new_syncrule->actions = actions;
4108 return new_syncrule;
4109 }
4110
4111 RTLIL::Process::~Process()
4112 {
4113 for (auto it = syncs.begin(); it != syncs.end(); it++)
4114 delete *it;
4115 }
4116
4117 RTLIL::Process *RTLIL::Process::clone() const
4118 {
4119 RTLIL::Process *new_proc = new RTLIL::Process;
4120
4121 new_proc->name = name;
4122 new_proc->attributes = attributes;
4123
4124 RTLIL::CaseRule *rc_ptr = root_case.clone();
4125 new_proc->root_case = *rc_ptr;
4126 rc_ptr->switches.clear();
4127 delete rc_ptr;
4128
4129 for (auto &it : syncs)
4130 new_proc->syncs.push_back(it->clone());
4131
4132 return new_proc;
4133 }
4134
4135 #ifdef WITH_PYTHON
4136 RTLIL::Memory::~Memory()
4137 {
4138 RTLIL::Memory::get_all_memorys()->erase(hashidx_);
4139 }
4140 static std::map<unsigned int, RTLIL::Memory*> all_memorys;
4141 std::map<unsigned int, RTLIL::Memory*> *RTLIL::Memory::get_all_memorys(void)
4142 {
4143 return &all_memorys;
4144 }
4145 #endif
4146 YOSYS_NAMESPACE_END