projects / yosys.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
RIP $safe_pmux
[yosys.git] / kernel / rtlil.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 #include "kernel/yosys.h"
21 #include "frontends/verilog/verilog_frontend.h"
22 #include "backends/ilang/ilang_backend.h"
23
24 #include <string.h>
25 #include <algorithm>
26
27 YOSYS_NAMESPACE_BEGIN
28
29 std::vector<int> RTLIL::IdString::global_refcount_storage_;
30 std::vector<char*> RTLIL::IdString::global_id_storage_;
31 std::map<char*, int, RTLIL::IdString::char_ptr_cmp> RTLIL::IdString::global_id_index_;
32 std::vector<int> RTLIL::IdString::global_free_idx_list_;
33
34 RTLIL::Const::Const()
35 {
36 flags = RTLIL::CONST_FLAG_NONE;
37 }
38
39 RTLIL::Const::Const(std::string str)
40 {
41 flags = RTLIL::CONST_FLAG_STRING;
42 for (int i = str.size()-1; i >= 0; i--) {
43 unsigned char ch = str[i];
44 for (int j = 0; j < 8; j++) {
45 bits.push_back((ch & 1) != 0 ? RTLIL::S1 : RTLIL::S0);
46 ch = ch >> 1;
47 }
48 }
49 }
50
51 RTLIL::Const::Const(int val, int width)
52 {
53 flags = RTLIL::CONST_FLAG_NONE;
54 for (int i = 0; i < width; i++) {
55 bits.push_back((val & 1) != 0 ? RTLIL::S1 : RTLIL::S0);
56 val = val >> 1;
57 }
58 }
59
60 RTLIL::Const::Const(RTLIL::State bit, int width)
61 {
62 flags = RTLIL::CONST_FLAG_NONE;
63 for (int i = 0; i < width; i++)
64 bits.push_back(bit);
65 }
66
67 bool RTLIL::Const::operator <(const RTLIL::Const &other) const
68 {
69 if (bits.size() != other.bits.size())
70 return bits.size() < other.bits.size();
71 for (size_t i = 0; i < bits.size(); i++)
72 if (bits[i] != other.bits[i])
73 return bits[i] < other.bits[i];
74 return false;
75 }
76
77 bool RTLIL::Const::operator ==(const RTLIL::Const &other) const
78 {
79 return bits == other.bits;
80 }
81
82 bool RTLIL::Const::operator !=(const RTLIL::Const &other) const
83 {
84 return bits != other.bits;
85 }
86
87 bool RTLIL::Const::as_bool() const
88 {
89 for (size_t i = 0; i < bits.size(); i++)
90 if (bits[i] == RTLIL::S1)
91 return true;
92 return false;
93 }
94
95 int RTLIL::Const::as_int() const
96 {
97 int ret = 0;
98 for (size_t i = 0; i < bits.size() && i < 32; i++)
99 if (bits[i] == RTLIL::S1)
100 ret |= 1 << i;
101 return ret;
102 }
103
104 std::string RTLIL::Const::as_string() const
105 {
106 std::string ret;
107 for (size_t i = bits.size(); i > 0; i--)
108 switch (bits[i-1]) {
109 case S0: ret += "0"; break;
110 case S1: ret += "1"; break;
111 case Sx: ret += "x"; break;
112 case Sz: ret += "z"; break;
113 case Sa: ret += "-"; break;
114 case Sm: ret += "m"; break;
115 }
116 return ret;
117 }
118
119 std::string RTLIL::Const::decode_string() const
120 {
121 std::string string;
122 std::vector <char> string_chars;
123 for (int i = 0; i < int (bits.size()); i += 8) {
124 char ch = 0;
125 for (int j = 0; j < 8 && i + j < int (bits.size()); j++)
126 if (bits[i + j] == RTLIL::State::S1)
127 ch |= 1 << j;
128 if (ch != 0)
129 string_chars.push_back(ch);
130 }
131 for (int i = int (string_chars.size()) - 1; i >= 0; i--)
132 string += string_chars[i];
133 return string;
134 }
135
136 bool RTLIL::Selection::selected_module(RTLIL::IdString mod_name) const
137 {
138 if (full_selection)
139 return true;
140 if (selected_modules.count(mod_name) > 0)
141 return true;
142 if (selected_members.count(mod_name) > 0)
143 return true;
144 return false;
145 }
146
147 bool RTLIL::Selection::selected_whole_module(RTLIL::IdString mod_name) const
148 {
149 if (full_selection)
150 return true;
151 if (selected_modules.count(mod_name) > 0)
152 return true;
153 return false;
154 }
155
156 bool RTLIL::Selection::selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const
157 {
158 if (full_selection)
159 return true;
160 if (selected_modules.count(mod_name) > 0)
161 return true;
162 if (selected_members.count(mod_name) > 0)
163 if (selected_members.at(mod_name).count(memb_name) > 0)
164 return true;
165 return false;
166 }
167
168 void RTLIL::Selection::optimize(RTLIL::Design *design)
169 {
170 if (full_selection) {
171 selected_modules.clear();
172 selected_members.clear();
173 return;
174 }
175
176 std::vector<RTLIL::IdString> del_list, add_list;
177
178 del_list.clear();
179 for (auto mod_name : selected_modules) {
180 if (design->modules_.count(mod_name) == 0)
181 del_list.push_back(mod_name);
182 selected_members.erase(mod_name);
183 }
184 for (auto mod_name : del_list)
185 selected_modules.erase(mod_name);
186
187 del_list.clear();
188 for (auto &it : selected_members)
189 if (design->modules_.count(it.first) == 0)
190 del_list.push_back(it.first);
191 for (auto mod_name : del_list)
192 selected_members.erase(mod_name);
193
194 for (auto &it : selected_members) {
195 del_list.clear();
196 for (auto memb_name : it.second)
197 if (design->modules_[it.first]->count_id(memb_name) == 0)
198 del_list.push_back(memb_name);
199 for (auto memb_name : del_list)
200 it.second.erase(memb_name);
201 }
202
203 del_list.clear();
204 add_list.clear();
205 for (auto &it : selected_members)
206 if (it.second.size() == 0)
207 del_list.push_back(it.first);
208 else if (it.second.size() == design->modules_[it.first]->wires_.size() + design->modules_[it.first]->memories.size() +
209 design->modules_[it.first]->cells_.size() + design->modules_[it.first]->processes.size())
210 add_list.push_back(it.first);
211 for (auto mod_name : del_list)
212 selected_members.erase(mod_name);
213 for (auto mod_name : add_list) {
214 selected_members.erase(mod_name);
215 selected_modules.insert(mod_name);
216 }
217
218 if (selected_modules.size() == design->modules_.size()) {
219 full_selection = true;
220 selected_modules.clear();
221 selected_members.clear();
222 }
223 }
224
225 RTLIL::Design::Design()
226 {
227 refcount_modules_ = 0;
228 }
229
230 RTLIL::Design::~Design()
231 {
232 for (auto it = modules_.begin(); it != modules_.end(); it++)
233 delete it->second;
234 }
235
236 RTLIL::ObjRange<RTLIL::Module*> RTLIL::Design::modules()
237 {
238 return RTLIL::ObjRange<RTLIL::Module*>(&modules_, &refcount_modules_);
239 }
240
241 RTLIL::Module *RTLIL::Design::module(RTLIL::IdString name)
242 {
243 return modules_.count(name) ? modules_.at(name) : NULL;
244 }
245
246 void RTLIL::Design::add(RTLIL::Module *module)
247 {
248 log_assert(modules_.count(module->name) == 0);
249 log_assert(refcount_modules_ == 0);
250 modules_[module->name] = module;
251 module->design = this;
252
253 for (auto mon : monitors)
254 mon->notify_module_add(module);
255 }
256
257 RTLIL::Module *RTLIL::Design::addModule(RTLIL::IdString name)
258 {
259 log_assert(modules_.count(name) == 0);
260 log_assert(refcount_modules_ == 0);
261
262 RTLIL::Module *module = new RTLIL::Module;
263 modules_[name] = module;
264 module->design = this;
265 module->name = name;
266
267 for (auto mon : monitors)
268 mon->notify_module_add(module);
269
270 return module;
271 }
272
273 void RTLIL::Design::remove(RTLIL::Module *module)
274 {
275 for (auto mon : monitors)
276 mon->notify_module_del(module);
277
278 log_assert(modules_.at(module->name) == module);
279 modules_.erase(module->name);
280 delete module;
281 }
282
283 void RTLIL::Design::check()
284 {
285 #ifndef NDEBUG
286 for (auto &it : modules_) {
287 log_assert(this == it.second->design);
288 log_assert(it.first == it.second->name);
289 log_assert(!it.first.empty());
290 it.second->check();
291 }
292 #endif
293 }
294
295 void RTLIL::Design::optimize()
296 {
297 for (auto &it : modules_)
298 it.second->optimize();
299 for (auto &it : selection_stack)
300 it.optimize(this);
301 for (auto &it : selection_vars)
302 it.second.optimize(this);
303 }
304
305 bool RTLIL::Design::selected_module(RTLIL::IdString mod_name) const
306 {
307 if (!selected_active_module.empty() && mod_name != selected_active_module)
308 return false;
309 if (selection_stack.size() == 0)
310 return true;
311 return selection_stack.back().selected_module(mod_name);
312 }
313
314 bool RTLIL::Design::selected_whole_module(RTLIL::IdString mod_name) const
315 {
316 if (!selected_active_module.empty() && mod_name != selected_active_module)
317 return false;
318 if (selection_stack.size() == 0)
319 return true;
320 return selection_stack.back().selected_whole_module(mod_name);
321 }
322
323 bool RTLIL::Design::selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const
324 {
325 if (!selected_active_module.empty() && mod_name != selected_active_module)
326 return false;
327 if (selection_stack.size() == 0)
328 return true;
329 return selection_stack.back().selected_member(mod_name, memb_name);
330 }
331
332 bool RTLIL::Design::selected_module(RTLIL::Module *mod) const
333 {
334 return selected_module(mod->name);
335 }
336
337 bool RTLIL::Design::selected_whole_module(RTLIL::Module *mod) const
338 {
339 return selected_whole_module(mod->name);
340 }
341
342 std::vector<RTLIL::Module*> RTLIL::Design::selected_modules() const
343 {
344 std::vector<RTLIL::Module*> result;
345 result.reserve(modules_.size());
346 for (auto &it : modules_)
347 if (selected_module(it.first))
348 result.push_back(it.second);
349 return result;
350 }
351
352 std::vector<RTLIL::Module*> RTLIL::Design::selected_whole_modules() const
353 {
354 std::vector<RTLIL::Module*> result;
355 result.reserve(modules_.size());
356 for (auto &it : modules_)
357 if (selected_whole_module(it.first))
358 result.push_back(it.second);
359 return result;
360 }
361
362 std::vector<RTLIL::Module*> RTLIL::Design::selected_whole_modules_warn() const
363 {
364 std::vector<RTLIL::Module*> result;
365 result.reserve(modules_.size());
366 for (auto &it : modules_)
367 if (selected_whole_module(it.first))
368 result.push_back(it.second);
369 else if (selected_module(it.first))
370 log("Warning: Ignoring partially selected module %s.\n", log_id(it.first));
371 return result;
372 }
373
374 RTLIL::Module::Module()
375 {
376 design = nullptr;
377 refcount_wires_ = 0;
378 refcount_cells_ = 0;
379 }
380
381 RTLIL::Module::~Module()
382 {
383 for (auto it = wires_.begin(); it != wires_.end(); it++)
384 delete it->second;
385 for (auto it = memories.begin(); it != memories.end(); it++)
386 delete it->second;
387 for (auto it = cells_.begin(); it != cells_.end(); it++)
388 delete it->second;
389 for (auto it = processes.begin(); it != processes.end(); it++)
390 delete it->second;
391 }
392
393 RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, std::map<RTLIL::IdString, RTLIL::Const>)
394 {
395 log_error("Module `%s' is used with parameters but is not parametric!\n", id2cstr(name));
396 }
397
398 size_t RTLIL::Module::count_id(RTLIL::IdString id)
399 {
400 return wires_.count(id) + memories.count(id) + cells_.count(id) + processes.count(id);
401 }
402
403 #ifndef NDEBUG
404 namespace {
405 struct InternalCellChecker
406 {
407 RTLIL::Module *module;
408 RTLIL::Cell *cell;
409 std::set<RTLIL::IdString> expected_params, expected_ports;
410
411 InternalCellChecker(RTLIL::Module *module, RTLIL::Cell *cell) : module(module), cell(cell) { }
412
413 void error(int linenr)
414 {
415 char *ptr;
416 size_t size;
417
418 FILE *f = open_memstream(&ptr, &size);
419 ILANG_BACKEND::dump_cell(f, " ", cell);
420 fputc(0, f);
421 fclose(f);
422
423 log_error("Found error in internal cell %s%s%s (%s) at %s:%d:\n%s",
424 module ? module->name.c_str() : "", module ? "." : "",
425 cell->name.c_str(), cell->type.c_str(), __FILE__, linenr, ptr);
426 }
427
428 int param(const char *name)
429 {
430 if (cell->parameters.count(name) == 0)
431 error(__LINE__);
432 expected_params.insert(name);
433 return cell->parameters.at(name).as_int();
434 }
435
436 int param_bool(const char *name)
437 {
438 int v = param(name);
439 if (cell->parameters.at(name).bits.size() > 32)
440 error(__LINE__);
441 if (v != 0 && v != 1)
442 error(__LINE__);
443 return v;
444 }
445
446 void param_bits(const char *name, int width)
447 {
448 param(name);
449 if (int(cell->parameters.at(name).bits.size()) != width)
450 error(__LINE__);
451 }
452
453 void port(const char *name, int width)
454 {
455 if (!cell->hasPort(name))
456 error(__LINE__);
457 if (cell->getPort(name).size() != width)
458 error(__LINE__);
459 expected_ports.insert(name);
460 }
461
462 void check_expected(bool check_matched_sign = true)
463 {
464 for (auto &para : cell->parameters)
465 if (expected_params.count(para.first) == 0)
466 error(__LINE__);
467 for (auto &conn : cell->connections())
468 if (expected_ports.count(conn.first) == 0)
469 error(__LINE__);
470
471 if (expected_params.count("\\A_SIGNED") != 0 && expected_params.count("\\B_SIGNED") && check_matched_sign) {
472 bool a_is_signed = param("\\A_SIGNED") != 0;
473 bool b_is_signed = param("\\B_SIGNED") != 0;
474 if (a_is_signed != b_is_signed)
475 error(__LINE__);
476 }
477 }
478
479 void check_gate(const char *ports)
480 {
481 if (cell->parameters.size() != 0)
482 error(__LINE__);
483
484 for (const char *p = ports; *p; p++) {
485 char portname[3] = { '\\', *p, 0 };
486 if (!cell->hasPort(portname))
487 error(__LINE__);
488 if (cell->getPort(portname).size() != 1)
489 error(__LINE__);
490 }
491
492 for (auto &conn : cell->connections()) {
493 if (conn.first.size() != 2 || conn.first[0] != '\\')
494 error(__LINE__);
495 if (strchr(ports, conn.first[1]) == NULL)
496 error(__LINE__);
497 }
498 }
499
500 void check()
501 {
502 if (cell->type.substr(0, 1) != "$" || cell->type.substr(0, 3) == "$__" || cell->type.substr(0, 8) == "$paramod" ||
503 cell->type.substr(0, 9) == "$verific$" || cell->type.substr(0, 7) == "$array:" || cell->type.substr(0, 8) == "$extern:")
504 return;
505
506 if (cell->type == "$not" || cell->type == "$pos" || cell->type == "$bu0" || cell->type == "$neg") {
507 param_bool("\\A_SIGNED");
508 port("\\A", param("\\A_WIDTH"));
509 port("\\Y", param("\\Y_WIDTH"));
510 check_expected();
511 return;
512 }
513
514 if (cell->type == "$and" || cell->type == "$or" || cell->type == "$xor" || cell->type == "$xnor") {
515 param_bool("\\A_SIGNED");
516 param_bool("\\B_SIGNED");
517 port("\\A", param("\\A_WIDTH"));
518 port("\\B", param("\\B_WIDTH"));
519 port("\\Y", param("\\Y_WIDTH"));
520 check_expected();
521 return;
522 }
523
524 if (cell->type == "$reduce_and" || cell->type == "$reduce_or" || cell->type == "$reduce_xor" ||
525 cell->type == "$reduce_xnor" || cell->type == "$reduce_bool") {
526 param_bool("\\A_SIGNED");
527 port("\\A", param("\\A_WIDTH"));
528 port("\\Y", param("\\Y_WIDTH"));
529 check_expected();
530 return;
531 }
532
533 if (cell->type == "$shl" || cell->type == "$shr" || cell->type == "$sshl" || cell->type == "$sshr" ||
534 cell->type == "$shift" || cell->type == "$shiftx") {
535 param_bool("\\A_SIGNED");
536 param_bool("\\B_SIGNED");
537 port("\\A", param("\\A_WIDTH"));
538 port("\\B", param("\\B_WIDTH"));
539 port("\\Y", param("\\Y_WIDTH"));
540 check_expected(false);
541 return;
542 }
543
544 if (cell->type == "$lt" || cell->type == "$le" || cell->type == "$eq" || cell->type == "$ne" ||
545 cell->type == "$eqx" || cell->type == "$nex" || cell->type == "$ge" || cell->type == "$gt") {
546 param_bool("\\A_SIGNED");
547 param_bool("\\B_SIGNED");
548 port("\\A", param("\\A_WIDTH"));
549 port("\\B", param("\\B_WIDTH"));
550 port("\\Y", param("\\Y_WIDTH"));
551 check_expected();
552 return;
553 }
554
555 if (cell->type == "$add" || cell->type == "$sub" || cell->type == "$mul" || cell->type == "$div" ||
556 cell->type == "$mod" || cell->type == "$pow") {
557 param_bool("\\A_SIGNED");
558 param_bool("\\B_SIGNED");
559 port("\\A", param("\\A_WIDTH"));
560 port("\\B", param("\\B_WIDTH"));
561 port("\\Y", param("\\Y_WIDTH"));
562 check_expected(cell->type != "$pow");
563 return;
564 }
565
566 if (cell->type == "$logic_not") {
567 param_bool("\\A_SIGNED");
568 port("\\A", param("\\A_WIDTH"));
569 port("\\Y", param("\\Y_WIDTH"));
570 check_expected();
571 return;
572 }
573
574 if (cell->type == "$logic_and" || cell->type == "$logic_or") {
575 param_bool("\\A_SIGNED");
576 param_bool("\\B_SIGNED");
577 port("\\A", param("\\A_WIDTH"));
578 port("\\B", param("\\B_WIDTH"));
579 port("\\Y", param("\\Y_WIDTH"));
580 check_expected(false);
581 return;
582 }
583
584 if (cell->type == "$slice") {
585 param("\\OFFSET");
586 port("\\A", param("\\A_WIDTH"));
587 port("\\Y", param("\\Y_WIDTH"));
588 if (param("\\OFFSET") + param("\\Y_WIDTH") > param("\\A_WIDTH"))
589 error(__LINE__);
590 check_expected();
591 return;
592 }
593
594 if (cell->type == "$concat") {
595 port("\\A", param("\\A_WIDTH"));
596 port("\\B", param("\\B_WIDTH"));
597 port("\\Y", param("\\A_WIDTH") + param("\\B_WIDTH"));
598 check_expected();
599 return;
600 }
601
602 if (cell->type == "$mux") {
603 port("\\A", param("\\WIDTH"));
604 port("\\B", param("\\WIDTH"));
605 port("\\S", 1);
606 port("\\Y", param("\\WIDTH"));
607 check_expected();
608 return;
609 }
610
611 if (cell->type == "$pmux") {
612 port("\\A", param("\\WIDTH"));
613 port("\\B", param("\\WIDTH") * param("\\S_WIDTH"));
614 port("\\S", param("\\S_WIDTH"));
615 port("\\Y", param("\\WIDTH"));
616 check_expected();
617 return;
618 }
619
620 if (cell->type == "$lut") {
621 param("\\LUT");
622 port("\\I", param("\\WIDTH"));
623 port("\\O", 1);
624 check_expected();
625 return;
626 }
627
628 if (cell->type == "$sr") {
629 param_bool("\\SET_POLARITY");
630 param_bool("\\CLR_POLARITY");
631 port("\\SET", param("\\WIDTH"));
632 port("\\CLR", param("\\WIDTH"));
633 port("\\Q", param("\\WIDTH"));
634 check_expected();
635 return;
636 }
637
638 if (cell->type == "$dff") {
639 param_bool("\\CLK_POLARITY");
640 port("\\CLK", 1);
641 port("\\D", param("\\WIDTH"));
642 port("\\Q", param("\\WIDTH"));
643 check_expected();
644 return;
645 }
646
647 if (cell->type == "$dffsr") {
648 param_bool("\\CLK_POLARITY");
649 param_bool("\\SET_POLARITY");
650 param_bool("\\CLR_POLARITY");
651 port("\\CLK", 1);
652 port("\\SET", param("\\WIDTH"));
653 port("\\CLR", param("\\WIDTH"));
654 port("\\D", param("\\WIDTH"));
655 port("\\Q", param("\\WIDTH"));
656 check_expected();
657 return;
658 }
659
660 if (cell->type == "$adff") {
661 param_bool("\\CLK_POLARITY");
662 param_bool("\\ARST_POLARITY");
663 param_bits("\\ARST_VALUE", param("\\WIDTH"));
664 port("\\CLK", 1);
665 port("\\ARST", 1);
666 port("\\D", param("\\WIDTH"));
667 port("\\Q", param("\\WIDTH"));
668 check_expected();
669 return;
670 }
671
672 if (cell->type == "$dlatch") {
673 param_bool("\\EN_POLARITY");
674 port("\\EN", 1);
675 port("\\D", param("\\WIDTH"));
676 port("\\Q", param("\\WIDTH"));
677 check_expected();
678 return;
679 }
680
681 if (cell->type == "$dlatchsr") {
682 param_bool("\\EN_POLARITY");
683 param_bool("\\SET_POLARITY");
684 param_bool("\\CLR_POLARITY");
685 port("\\EN", 1);
686 port("\\SET", param("\\WIDTH"));
687 port("\\CLR", param("\\WIDTH"));
688 port("\\D", param("\\WIDTH"));
689 port("\\Q", param("\\WIDTH"));
690 check_expected();
691 return;
692 }
693
694 if (cell->type == "$fsm") {
695 param("\\NAME");
696 param_bool("\\CLK_POLARITY");
697 param_bool("\\ARST_POLARITY");
698 param("\\STATE_BITS");
699 param("\\STATE_NUM");
700 param("\\STATE_NUM_LOG2");
701 param("\\STATE_RST");
702 param_bits("\\STATE_TABLE", param("\\STATE_BITS") * param("\\STATE_NUM"));
703 param("\\TRANS_NUM");
704 param_bits("\\TRANS_TABLE", param("\\TRANS_NUM") * (2*param("\\STATE_NUM_LOG2") + param("\\CTRL_IN_WIDTH") + param("\\CTRL_OUT_WIDTH")));
705 port("\\CLK", 1);
706 port("\\ARST", 1);
707 port("\\CTRL_IN", param("\\CTRL_IN_WIDTH"));
708 port("\\CTRL_OUT", param("\\CTRL_OUT_WIDTH"));
709 check_expected();
710 return;
711 }
712
713 if (cell->type == "$memrd") {
714 param("\\MEMID");
715 param_bool("\\CLK_ENABLE");
716 param_bool("\\CLK_POLARITY");
717 param_bool("\\TRANSPARENT");
718 port("\\CLK", 1);
719 port("\\ADDR", param("\\ABITS"));
720 port("\\DATA", param("\\WIDTH"));
721 check_expected();
722 return;
723 }
724
725 if (cell->type == "$memwr") {
726 param("\\MEMID");
727 param_bool("\\CLK_ENABLE");
728 param_bool("\\CLK_POLARITY");
729 param("\\PRIORITY");
730 port("\\CLK", 1);
731 port("\\EN", param("\\WIDTH"));
732 port("\\ADDR", param("\\ABITS"));
733 port("\\DATA", param("\\WIDTH"));
734 check_expected();
735 return;
736 }
737
738 if (cell->type == "$mem") {
739 param("\\MEMID");
740 param("\\SIZE");
741 param("\\OFFSET");
742 param_bits("\\RD_CLK_ENABLE", param("\\RD_PORTS"));
743 param_bits("\\RD_CLK_POLARITY", param("\\RD_PORTS"));
744 param_bits("\\RD_TRANSPARENT", param("\\RD_PORTS"));
745 param_bits("\\WR_CLK_ENABLE", param("\\WR_PORTS"));
746 param_bits("\\WR_CLK_POLARITY", param("\\WR_PORTS"));
747 port("\\RD_CLK", param("\\RD_PORTS"));
748 port("\\RD_ADDR", param("\\RD_PORTS") * param("\\ABITS"));
749 port("\\RD_DATA", param("\\RD_PORTS") * param("\\WIDTH"));
750 port("\\WR_CLK", param("\\WR_PORTS"));
751 port("\\WR_EN", param("\\WR_PORTS") * param("\\WIDTH"));
752 port("\\WR_ADDR", param("\\WR_PORTS") * param("\\ABITS"));
753 port("\\WR_DATA", param("\\WR_PORTS") * param("\\WIDTH"));
754 check_expected();
755 return;
756 }
757
758 if (cell->type == "$assert") {
759 port("\\A", 1);
760 port("\\EN", 1);
761 check_expected();
762 return;
763 }
764
765 if (cell->type == "$_INV_") { check_gate("AY"); return; }
766 if (cell->type == "$_AND_") { check_gate("ABY"); return; }
767 if (cell->type == "$_OR_") { check_gate("ABY"); return; }
768 if (cell->type == "$_XOR_") { check_gate("ABY"); return; }
769 if (cell->type == "$_MUX_") { check_gate("ABSY"); return; }
770
771 if (cell->type == "$_SR_NN_") { check_gate("SRQ"); return; }
772 if (cell->type == "$_SR_NP_") { check_gate("SRQ"); return; }
773 if (cell->type == "$_SR_PN_") { check_gate("SRQ"); return; }
774 if (cell->type == "$_SR_PP_") { check_gate("SRQ"); return; }
775
776 if (cell->type == "$_DFF_N_") { check_gate("DQC"); return; }
777 if (cell->type == "$_DFF_P_") { check_gate("DQC"); return; }
778
779 if (cell->type == "$_DFF_NN0_") { check_gate("DQCR"); return; }
780 if (cell->type == "$_DFF_NN1_") { check_gate("DQCR"); return; }
781 if (cell->type == "$_DFF_NP0_") { check_gate("DQCR"); return; }
782 if (cell->type == "$_DFF_NP1_") { check_gate("DQCR"); return; }
783 if (cell->type == "$_DFF_PN0_") { check_gate("DQCR"); return; }
784 if (cell->type == "$_DFF_PN1_") { check_gate("DQCR"); return; }
785 if (cell->type == "$_DFF_PP0_") { check_gate("DQCR"); return; }
786 if (cell->type == "$_DFF_PP1_") { check_gate("DQCR"); return; }
787
788 if (cell->type == "$_DFFSR_NNN_") { check_gate("CSRDQ"); return; }
789 if (cell->type == "$_DFFSR_NNP_") { check_gate("CSRDQ"); return; }
790 if (cell->type == "$_DFFSR_NPN_") { check_gate("CSRDQ"); return; }
791 if (cell->type == "$_DFFSR_NPP_") { check_gate("CSRDQ"); return; }
792 if (cell->type == "$_DFFSR_PNN_") { check_gate("CSRDQ"); return; }
793 if (cell->type == "$_DFFSR_PNP_") { check_gate("CSRDQ"); return; }
794 if (cell->type == "$_DFFSR_PPN_") { check_gate("CSRDQ"); return; }
795 if (cell->type == "$_DFFSR_PPP_") { check_gate("CSRDQ"); return; }
796
797 if (cell->type == "$_DLATCH_N_") { check_gate("EDQ"); return; }
798 if (cell->type == "$_DLATCH_P_") { check_gate("EDQ"); return; }
799
800 if (cell->type == "$_DLATCHSR_NNN_") { check_gate("ESRDQ"); return; }
801 if (cell->type == "$_DLATCHSR_NNP_") { check_gate("ESRDQ"); return; }
802 if (cell->type == "$_DLATCHSR_NPN_") { check_gate("ESRDQ"); return; }
803 if (cell->type == "$_DLATCHSR_NPP_") { check_gate("ESRDQ"); return; }
804 if (cell->type == "$_DLATCHSR_PNN_") { check_gate("ESRDQ"); return; }
805 if (cell->type == "$_DLATCHSR_PNP_") { check_gate("ESRDQ"); return; }
806 if (cell->type == "$_DLATCHSR_PPN_") { check_gate("ESRDQ"); return; }
807 if (cell->type == "$_DLATCHSR_PPP_") { check_gate("ESRDQ"); return; }
808
809 error(__LINE__);
810 }
811 };
812 }
813 #endif
814
815 void RTLIL::Module::check()
816 {
817 #ifndef NDEBUG
818 std::vector<bool> ports_declared;
819 for (auto &it : wires_) {
820 log_assert(this == it.second->module);
821 log_assert(it.first == it.second->name);
822 log_assert(!it.first.empty());
823 log_assert(it.second->width >= 0);
824 log_assert(it.second->port_id >= 0);
825 for (auto &it2 : it.second->attributes)
826 log_assert(!it2.first.empty());
827 if (it.second->port_id) {
828 log_assert(it.second->port_input || it.second->port_output);
829 if (SIZE(ports_declared) < it.second->port_id)
830 ports_declared.resize(it.second->port_id);
831 log_assert(ports_declared[it.second->port_id-1] == false);
832 ports_declared[it.second->port_id-1] = true;
833 } else
834 log_assert(!it.second->port_input && !it.second->port_output);
835 }
836 for (auto port_declared : ports_declared)
837 log_assert(port_declared == true);
838
839 for (auto &it : memories) {
840 log_assert(it.first == it.second->name);
841 log_assert(!it.first.empty());
842 log_assert(it.second->width >= 0);
843 log_assert(it.second->size >= 0);
844 for (auto &it2 : it.second->attributes)
845 log_assert(!it2.first.empty());
846 }
847
848 for (auto &it : cells_) {
849 log_assert(this == it.second->module);
850 log_assert(it.first == it.second->name);
851 log_assert(!it.first.empty());
852 log_assert(!it.second->type.empty());
853 for (auto &it2 : it.second->connections()) {
854 log_assert(!it2.first.empty());
855 it2.second.check();
856 }
857 for (auto &it2 : it.second->attributes)
858 log_assert(!it2.first.empty());
859 for (auto &it2 : it.second->parameters)
860 log_assert(!it2.first.empty());
861 InternalCellChecker checker(this, it.second);
862 checker.check();
863 }
864
865 for (auto &it : processes) {
866 log_assert(it.first == it.second->name);
867 log_assert(!it.first.empty());
868 // FIXME: More checks here..
869 }
870
871 for (auto &it : connections_) {
872 log_assert(it.first.size() == it.second.size());
873 it.first.check();
874 it.second.check();
875 }
876
877 for (auto &it : attributes)
878 log_assert(!it.first.empty());
879 #endif
880 }
881
882 void RTLIL::Module::optimize()
883 {
884 }
885
886 void RTLIL::Module::cloneInto(RTLIL::Module *new_mod) const
887 {
888 log_assert(new_mod->refcount_wires_ == 0);
889 log_assert(new_mod->refcount_cells_ == 0);
890
891 new_mod->connections_ = connections_;
892 new_mod->attributes = attributes;
893
894 for (auto &it : wires_)
895 new_mod->addWire(it.first, it.second);
896
897 for (auto &it : memories)
898 new_mod->memories[it.first] = new RTLIL::Memory(*it.second);
899
900 for (auto &it : cells_)
901 new_mod->addCell(it.first, it.second);
902
903 for (auto &it : processes)
904 new_mod->processes[it.first] = it.second->clone();
905
906 struct RewriteSigSpecWorker
907 {
908 RTLIL::Module *mod;
909 void operator()(RTLIL::SigSpec &sig)
910 {
911 std::vector<RTLIL::SigChunk> chunks = sig.chunks();
912 for (auto &c : chunks)
913 if (c.wire != NULL)
914 c.wire = mod->wires_.at(c.wire->name);
915 sig = chunks;
916 }
917 };
918
919 RewriteSigSpecWorker rewriteSigSpecWorker;
920 rewriteSigSpecWorker.mod = new_mod;
921 new_mod->rewrite_sigspecs(rewriteSigSpecWorker);
922 }
923
924 RTLIL::Module *RTLIL::Module::clone() const
925 {
926 RTLIL::Module *new_mod = new RTLIL::Module;
927 new_mod->name = name;
928 cloneInto(new_mod);
929 return new_mod;
930 }
931
932 bool RTLIL::Module::has_memories() const
933 {
934 return !memories.empty();
935 }
936
937 bool RTLIL::Module::has_processes() const
938 {
939 return !processes.empty();
940 }
941
942 bool RTLIL::Module::has_memories_warn() const
943 {
944 if (!memories.empty())
945 log("Warning: Ignoring module %s because it contains memories (run 'memory' command first).\n", log_id(this));
946 return !memories.empty();
947 }
948
949 bool RTLIL::Module::has_processes_warn() const
950 {
951 if (!processes.empty())
952 log("Warning: Ignoring module %s because it contains processes (run 'proc' command first).\n", log_id(this));
953 return !processes.empty();
954 }
955
956 std::vector<RTLIL::Wire*> RTLIL::Module::selected_wires() const
957 {
958 std::vector<RTLIL::Wire*> result;
959 result.reserve(wires_.size());
960 for (auto &it : wires_)
961 if (design->selected(this, it.second))
962 result.push_back(it.second);
963 return result;
964 }
965
966 std::vector<RTLIL::Cell*> RTLIL::Module::selected_cells() const
967 {
968 std::vector<RTLIL::Cell*> result;
969 result.reserve(wires_.size());
970 for (auto &it : cells_)
971 if (design->selected(this, it.second))
972 result.push_back(it.second);
973 return result;
974 }
975
976 void RTLIL::Module::add(RTLIL::Wire *wire)
977 {
978 log_assert(!wire->name.empty());
979 log_assert(count_id(wire->name) == 0);
980 log_assert(refcount_wires_ == 0);
981 wires_[wire->name] = wire;
982 wire->module = this;
983 }
984
985 void RTLIL::Module::add(RTLIL::Cell *cell)
986 {
987 log_assert(!cell->name.empty());
988 log_assert(count_id(cell->name) == 0);
989 log_assert(refcount_cells_ == 0);
990 cells_[cell->name] = cell;
991 cell->module = this;
992 }
993
994 namespace {
995 struct DeleteWireWorker
996 {
997 RTLIL::Module *module;
998 const std::set<RTLIL::Wire*> *wires_p;
999
1000 void operator()(RTLIL::SigSpec &sig) {
1001 std::vector<RTLIL::SigChunk> chunks = sig;
1002 for (auto &c : chunks)
1003 if (c.wire != NULL && wires_p->count(c.wire)) {
1004 c.wire = module->addWire(NEW_ID, c.width);
1005 c.offset = 0;
1006 }
1007 sig = chunks;
1008 }
1009 };
1010 }
1011
1012 #if 0
1013 void RTLIL::Module::remove(RTLIL::Wire *wire)
1014 {
1015 std::setPort<RTLIL::Wire*> wires_;
1016 wires_.insert(wire);
1017 remove(wires_);
1018 }
1019 #endif
1020
1021 void RTLIL::Module::remove(const std::set<RTLIL::Wire*> &wires)
1022 {
1023 log_assert(refcount_wires_ == 0);
1024
1025 DeleteWireWorker delete_wire_worker;
1026 delete_wire_worker.module = this;
1027 delete_wire_worker.wires_p = &wires;
1028 rewrite_sigspecs(delete_wire_worker);
1029
1030 for (auto &it : wires) {
1031 log_assert(wires_.count(it->name) != 0);
1032 wires_.erase(it->name);
1033 delete it;
1034 }
1035 }
1036
1037 void RTLIL::Module::remove(RTLIL::Cell *cell)
1038 {
1039 log_assert(cells_.count(cell->name) != 0);
1040 log_assert(refcount_cells_ == 0);
1041 cells_.erase(cell->name);
1042 delete cell;
1043 }
1044
1045 void RTLIL::Module::rename(RTLIL::Wire *wire, RTLIL::IdString new_name)
1046 {
1047 log_assert(wires_[wire->name] == wire);
1048 log_assert(refcount_wires_ == 0);
1049 wires_.erase(wire->name);
1050 wire->name = new_name;
1051 add(wire);
1052 }
1053
1054 void RTLIL::Module::rename(RTLIL::Cell *cell, RTLIL::IdString new_name)
1055 {
1056 log_assert(cells_[cell->name] == cell);
1057 log_assert(refcount_wires_ == 0);
1058 cells_.erase(cell->name);
1059 cell->name = new_name;
1060 add(cell);
1061 }
1062
1063 void RTLIL::Module::rename(RTLIL::IdString old_name, RTLIL::IdString new_name)
1064 {
1065 log_assert(count_id(old_name) != 0);
1066 if (wires_.count(old_name))
1067 rename(wires_.at(old_name), new_name);
1068 else if (cells_.count(old_name))
1069 rename(cells_.at(old_name), new_name);
1070 else
1071 log_abort();
1072 }
1073
1074 void RTLIL::Module::swap_names(RTLIL::Wire *w1, RTLIL::Wire *w2)
1075 {
1076 log_assert(wires_[w1->name] == w1);
1077 log_assert(wires_[w2->name] == w2);
1078 log_assert(refcount_wires_ == 0);
1079
1080 wires_.erase(w1->name);
1081 wires_.erase(w2->name);
1082
1083 std::swap(w1->name, w2->name);
1084
1085 wires_[w1->name] = w1;
1086 wires_[w2->name] = w2;
1087 }
1088
1089 void RTLIL::Module::swap_names(RTLIL::Cell *c1, RTLIL::Cell *c2)
1090 {
1091 log_assert(cells_[c1->name] == c1);
1092 log_assert(cells_[c2->name] == c2);
1093 log_assert(refcount_cells_ == 0);
1094
1095 cells_.erase(c1->name);
1096 cells_.erase(c2->name);
1097
1098 std::swap(c1->name, c2->name);
1099
1100 cells_[c1->name] = c1;
1101 cells_[c2->name] = c2;
1102 }
1103
1104 static bool fixup_ports_compare(const RTLIL::Wire *a, const RTLIL::Wire *b)
1105 {
1106 if (a->port_id && !b->port_id)
1107 return true;
1108 if (!a->port_id && b->port_id)
1109 return false;
1110
1111 if (a->port_id == b->port_id)
1112 return a->name < b->name;
1113 return a->port_id < b->port_id;
1114 }
1115
1116 void RTLIL::Module::connect(const RTLIL::SigSig &conn)
1117 {
1118 for (auto mon : monitors)
1119 mon->notify_connect(this, conn);
1120
1121 if (design)
1122 for (auto mon : design->monitors)
1123 mon->notify_connect(this, conn);
1124
1125 connections_.push_back(conn);
1126 }
1127
1128 void RTLIL::Module::connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs)
1129 {
1130 connect(RTLIL::SigSig(lhs, rhs));
1131 }
1132
1133 void RTLIL::Module::new_connections(const std::vector<RTLIL::SigSig> &new_conn)
1134 {
1135 for (auto mon : monitors)
1136 mon->notify_connect(this, new_conn);
1137
1138 if (design)
1139 for (auto mon : design->monitors)
1140 mon->notify_connect(this, new_conn);
1141
1142 connections_ = new_conn;
1143 }
1144
1145 const std::vector<RTLIL::SigSig> &RTLIL::Module::connections() const
1146 {
1147 return connections_;
1148 }
1149
1150 void RTLIL::Module::fixup_ports()
1151 {
1152 std::vector<RTLIL::Wire*> all_ports;
1153
1154 for (auto &w : wires_)
1155 if (w.second->port_input || w.second->port_output)
1156 all_ports.push_back(w.second);
1157 else
1158 w.second->port_id = 0;
1159
1160 std::sort(all_ports.begin(), all_ports.end(), fixup_ports_compare);
1161 for (size_t i = 0; i < all_ports.size(); i++)
1162 all_ports[i]->port_id = i+1;
1163 }
1164
1165 RTLIL::Wire *RTLIL::Module::addWire(RTLIL::IdString name, int width)
1166 {
1167 RTLIL::Wire *wire = new RTLIL::Wire;
1168 wire->name = name;
1169 wire->width = width;
1170 add(wire);
1171 return wire;
1172 }
1173
1174 RTLIL::Wire *RTLIL::Module::addWire(RTLIL::IdString name, const RTLIL::Wire *other)
1175 {
1176 RTLIL::Wire *wire = addWire(name);
1177 wire->width = other->width;
1178 wire->start_offset = other->start_offset;
1179 wire->port_id = other->port_id;
1180 wire->port_input = other->port_input;
1181 wire->port_output = other->port_output;
1182 wire->upto = other->upto;
1183 wire->attributes = other->attributes;
1184 return wire;
1185 }
1186
1187 RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, RTLIL::IdString type)
1188 {
1189 RTLIL::Cell *cell = new RTLIL::Cell;
1190 cell->name = name;
1191 cell->type = type;
1192 add(cell);
1193 return cell;
1194 }
1195
1196 RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, const RTLIL::Cell *other)
1197 {
1198 RTLIL::Cell *cell = addCell(name, other->type);
1199 cell->connections_ = other->connections_;
1200 cell->parameters = other->parameters;
1201 cell->attributes = other->attributes;
1202 return cell;
1203 }
1204
1205 #define DEF_METHOD(_func, _y_size, _type) \
1206 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed) { \
1207 RTLIL::Cell *cell = addCell(name, _type); \
1208 cell->parameters["\\A_SIGNED"] = is_signed; \
1209 cell->parameters["\\A_WIDTH"] = sig_a.size(); \
1210 cell->parameters["\\Y_WIDTH"] = sig_y.size(); \
1211 cell->setPort("\\A", sig_a); \
1212 cell->setPort("\\Y", sig_y); \
1213 return cell; \
1214 } \
1215 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed) { \
1216 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
1217 add ## _func(name, sig_a, sig_y, is_signed); \
1218 return sig_y; \
1219 }
1220 DEF_METHOD(Not, sig_a.size(), "$not")
1221 DEF_METHOD(Pos, sig_a.size(), "$pos")
1222 DEF_METHOD(Bu0, sig_a.size(), "$bu0")
1223 DEF_METHOD(Neg, sig_a.size(), "$neg")
1224 DEF_METHOD(ReduceAnd, 1, "$reduce_and")
1225 DEF_METHOD(ReduceOr, 1, "$reduce_or")
1226 DEF_METHOD(ReduceXor, 1, "$reduce_xor")
1227 DEF_METHOD(ReduceXnor, 1, "$reduce_xnor")
1228 DEF_METHOD(ReduceBool, 1, "$reduce_bool")
1229 DEF_METHOD(LogicNot, 1, "$logic_not")
1230 #undef DEF_METHOD
1231
1232 #define DEF_METHOD(_func, _y_size, _type) \
1233 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed) { \
1234 RTLIL::Cell *cell = addCell(name, _type); \
1235 cell->parameters["\\A_SIGNED"] = is_signed; \
1236 cell->parameters["\\B_SIGNED"] = is_signed; \
1237 cell->parameters["\\A_WIDTH"] = sig_a.size(); \
1238 cell->parameters["\\B_WIDTH"] = sig_b.size(); \
1239 cell->parameters["\\Y_WIDTH"] = sig_y.size(); \
1240 cell->setPort("\\A", sig_a); \
1241 cell->setPort("\\B", sig_b); \
1242 cell->setPort("\\Y", sig_y); \
1243 return cell; \
1244 } \
1245 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed) { \
1246 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
1247 add ## _func(name, sig_a, sig_b, sig_y, is_signed); \
1248 return sig_y; \
1249 }
1250 DEF_METHOD(And, std::max(sig_a.size(), sig_b.size()), "$and")
1251 DEF_METHOD(Or, std::max(sig_a.size(), sig_b.size()), "$or")
1252 DEF_METHOD(Xor, std::max(sig_a.size(), sig_b.size()), "$xor")
1253 DEF_METHOD(Xnor, std::max(sig_a.size(), sig_b.size()), "$xnor")
1254 DEF_METHOD(Shl, sig_a.size(), "$shl")
1255 DEF_METHOD(Shr, sig_a.size(), "$shr")
1256 DEF_METHOD(Sshl, sig_a.size(), "$sshl")
1257 DEF_METHOD(Sshr, sig_a.size(), "$sshr")
1258 DEF_METHOD(Shift, sig_a.size(), "$shift")
1259 DEF_METHOD(Shiftx, sig_a.size(), "$shiftx")
1260 DEF_METHOD(Lt, 1, "$lt")
1261 DEF_METHOD(Le, 1, "$le")
1262 DEF_METHOD(Eq, 1, "$eq")
1263 DEF_METHOD(Ne, 1, "$ne")
1264 DEF_METHOD(Eqx, 1, "$eqx")
1265 DEF_METHOD(Nex, 1, "$nex")
1266 DEF_METHOD(Ge, 1, "$ge")
1267 DEF_METHOD(Gt, 1, "$gt")
1268 DEF_METHOD(Add, std::max(sig_a.size(), sig_b.size()), "$add")
1269 DEF_METHOD(Sub, std::max(sig_a.size(), sig_b.size()), "$sub")
1270 DEF_METHOD(Mul, std::max(sig_a.size(), sig_b.size()), "$mul")
1271 DEF_METHOD(Div, std::max(sig_a.size(), sig_b.size()), "$div")
1272 DEF_METHOD(Mod, std::max(sig_a.size(), sig_b.size()), "$mod")
1273 DEF_METHOD(LogicAnd, 1, "$logic_and")
1274 DEF_METHOD(LogicOr, 1, "$logic_or")
1275 #undef DEF_METHOD
1276
1277 #define DEF_METHOD(_func, _type, _pmux) \
1278 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, RTLIL::SigSpec sig_y) { \
1279 RTLIL::Cell *cell = addCell(name, _type); \
1280 cell->parameters["\\WIDTH"] = sig_a.size(); \
1281 cell->parameters["\\WIDTH"] = sig_b.size(); \
1282 if (_pmux) cell->parameters["\\S_WIDTH"] = sig_s.size(); \
1283 cell->setPort("\\A", sig_a); \
1284 cell->setPort("\\B", sig_b); \
1285 cell->setPort("\\S", sig_s); \
1286 cell->setPort("\\Y", sig_y); \
1287 return cell; \
1288 } \
1289 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s) { \
1290 RTLIL::SigSpec sig_y = addWire(NEW_ID, sig_a.size()); \
1291 add ## _func(name, sig_a, sig_b, sig_s, sig_y); \
1292 return sig_y; \
1293 }
1294 DEF_METHOD(Mux, "$mux", 0)
1295 DEF_METHOD(Pmux, "$pmux", 1)
1296 #undef DEF_METHOD
1297
1298 #define DEF_METHOD_2(_func, _type, _P1, _P2) \
1299 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig1, RTLIL::SigSpec sig2) { \
1300 RTLIL::Cell *cell = addCell(name, _type); \
1301 cell->setPort("\\" #_P1, sig1); \
1302 cell->setPort("\\" #_P2, sig2); \
1303 return cell; \
1304 } \
1305 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig1) { \
1306 RTLIL::SigSpec sig2 = addWire(NEW_ID); \
1307 add ## _func(name, sig1, sig2); \
1308 return sig2; \
1309 }
1310 #define DEF_METHOD_3(_func, _type, _P1, _P2, _P3) \
1311 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig1, RTLIL::SigSpec sig2, RTLIL::SigSpec sig3) { \
1312 RTLIL::Cell *cell = addCell(name, _type); \
1313 cell->setPort("\\" #_P1, sig1); \
1314 cell->setPort("\\" #_P2, sig2); \
1315 cell->setPort("\\" #_P3, sig3); \
1316 return cell; \
1317 } \
1318 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig1, RTLIL::SigSpec sig2) { \
1319 RTLIL::SigSpec sig3 = addWire(NEW_ID); \
1320 add ## _func(name, sig1, sig2, sig3); \
1321 return sig3; \
1322 }
1323 #define DEF_METHOD_4(_func, _type, _P1, _P2, _P3, _P4) \
1324 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig1, RTLIL::SigSpec sig2, RTLIL::SigSpec sig3, RTLIL::SigSpec sig4) { \
1325 RTLIL::Cell *cell = addCell(name, _type); \
1326 cell->setPort("\\" #_P1, sig1); \
1327 cell->setPort("\\" #_P2, sig2); \
1328 cell->setPort("\\" #_P3, sig3); \
1329 cell->setPort("\\" #_P4, sig4); \
1330 return cell; \
1331 } \
1332 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig1, RTLIL::SigSpec sig2, RTLIL::SigSpec sig3) { \
1333 RTLIL::SigSpec sig4 = addWire(NEW_ID); \
1334 add ## _func(name, sig1, sig2, sig3, sig4); \
1335 return sig4; \
1336 }
1337 DEF_METHOD_2(InvGate, "$_INV_", A, Y)
1338 DEF_METHOD_3(AndGate, "$_AND_", A, B, Y)
1339 DEF_METHOD_3(OrGate, "$_OR_", A, B, Y)
1340 DEF_METHOD_3(XorGate, "$_XOR_", A, B, Y)
1341 DEF_METHOD_4(MuxGate, "$_MUX_", A, B, S, Y)
1342 #undef DEF_METHOD_2
1343 #undef DEF_METHOD_3
1344 #undef DEF_METHOD_4
1345
1346 RTLIL::Cell* RTLIL::Module::addPow(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool a_signed, bool b_signed)
1347 {
1348 RTLIL::Cell *cell = addCell(name, "$pow");
1349 cell->parameters["\\A_SIGNED"] = a_signed;
1350 cell->parameters["\\B_SIGNED"] = b_signed;
1351 cell->parameters["\\A_WIDTH"] = sig_a.size();
1352 cell->parameters["\\B_WIDTH"] = sig_b.size();
1353 cell->parameters["\\Y_WIDTH"] = sig_y.size();
1354 cell->setPort("\\A", sig_a);
1355 cell->setPort("\\B", sig_b);
1356 cell->setPort("\\Y", sig_y);
1357 return cell;
1358 }
1359
1360 RTLIL::Cell* RTLIL::Module::addSlice(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, RTLIL::Const offset)
1361 {
1362 RTLIL::Cell *cell = addCell(name, "$slice");
1363 cell->parameters["\\A_WIDTH"] = sig_a.size();
1364 cell->parameters["\\Y_WIDTH"] = sig_y.size();
1365 cell->parameters["\\OFFSET"] = offset;
1366 cell->setPort("\\A", sig_a);
1367 cell->setPort("\\Y", sig_y);
1368 return cell;
1369 }
1370
1371 RTLIL::Cell* RTLIL::Module::addConcat(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y)
1372 {
1373 RTLIL::Cell *cell = addCell(name, "$concat");
1374 cell->parameters["\\A_WIDTH"] = sig_a.size();
1375 cell->parameters["\\B_WIDTH"] = sig_b.size();
1376 cell->setPort("\\A", sig_a);
1377 cell->setPort("\\B", sig_b);
1378 cell->setPort("\\Y", sig_y);
1379 return cell;
1380 }
1381
1382 RTLIL::Cell* RTLIL::Module::addLut(RTLIL::IdString name, RTLIL::SigSpec sig_i, RTLIL::SigSpec sig_o, RTLIL::Const lut)
1383 {
1384 RTLIL::Cell *cell = addCell(name, "$lut");
1385 cell->parameters["\\LUT"] = lut;
1386 cell->parameters["\\WIDTH"] = sig_i.size();
1387 cell->setPort("\\I", sig_i);
1388 cell->setPort("\\O", sig_o);
1389 return cell;
1390 }
1391
1392 RTLIL::Cell* RTLIL::Module::addAssert(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en)
1393 {
1394 RTLIL::Cell *cell = addCell(name, "$assert");
1395 cell->setPort("\\A", sig_a);
1396 cell->setPort("\\EN", sig_en);
1397 return cell;
1398 }
1399
1400 RTLIL::Cell* RTLIL::Module::addSr(RTLIL::IdString name, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr, RTLIL::SigSpec sig_q, bool set_polarity, bool clr_polarity)
1401 {
1402 RTLIL::Cell *cell = addCell(name, "$sr");
1403 cell->parameters["\\SET_POLARITY"] = set_polarity;
1404 cell->parameters["\\CLR_POLARITY"] = clr_polarity;
1405 cell->parameters["\\WIDTH"] = sig_q.size();
1406 cell->setPort("\\SET", sig_set);
1407 cell->setPort("\\CLR", sig_clr);
1408 cell->setPort("\\Q", sig_q);
1409 return cell;
1410 }
1411
1412 RTLIL::Cell* RTLIL::Module::addDff(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity)
1413 {
1414 RTLIL::Cell *cell = addCell(name, "$dff");
1415 cell->parameters["\\CLK_POLARITY"] = clk_polarity;
1416 cell->parameters["\\WIDTH"] = sig_q.size();
1417 cell->setPort("\\CLK", sig_clk);
1418 cell->setPort("\\D", sig_d);
1419 cell->setPort("\\Q", sig_q);
1420 return cell;
1421 }
1422
1423 RTLIL::Cell* RTLIL::Module::addDffsr(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
1424 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity)
1425 {
1426 RTLIL::Cell *cell = addCell(name, "$dffsr");
1427 cell->parameters["\\CLK_POLARITY"] = clk_polarity;
1428 cell->parameters["\\SET_POLARITY"] = set_polarity;
1429 cell->parameters["\\CLR_POLARITY"] = clr_polarity;
1430 cell->parameters["\\WIDTH"] = sig_q.size();
1431 cell->setPort("\\CLK", sig_clk);
1432 cell->setPort("\\SET", sig_set);
1433 cell->setPort("\\CLR", sig_clr);
1434 cell->setPort("\\D", sig_d);
1435 cell->setPort("\\Q", sig_q);
1436 return cell;
1437 }
1438
1439 RTLIL::Cell* RTLIL::Module::addAdff(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_arst, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q,
1440 RTLIL::Const arst_value, bool clk_polarity, bool arst_polarity)
1441 {
1442 RTLIL::Cell *cell = addCell(name, "$adff");
1443 cell->parameters["\\CLK_POLARITY"] = clk_polarity;
1444 cell->parameters["\\ARST_POLARITY"] = arst_polarity;
1445 cell->parameters["\\ARST_VALUE"] = arst_value;
1446 cell->parameters["\\WIDTH"] = sig_q.size();
1447 cell->setPort("\\CLK", sig_clk);
1448 cell->setPort("\\ARST", sig_arst);
1449 cell->setPort("\\D", sig_d);
1450 cell->setPort("\\Q", sig_q);
1451 return cell;
1452 }
1453
1454 RTLIL::Cell* RTLIL::Module::addDlatch(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity)
1455 {
1456 RTLIL::Cell *cell = addCell(name, "$dlatch");
1457 cell->parameters["\\EN_POLARITY"] = en_polarity;
1458 cell->parameters["\\WIDTH"] = sig_q.size();
1459 cell->setPort("\\EN", sig_en);
1460 cell->setPort("\\D", sig_d);
1461 cell->setPort("\\Q", sig_q);
1462 return cell;
1463 }
1464
1465 RTLIL::Cell* RTLIL::Module::addDlatchsr(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
1466 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity, bool set_polarity, bool clr_polarity)
1467 {
1468 RTLIL::Cell *cell = addCell(name, "$dlatchsr");
1469 cell->parameters["\\EN_POLARITY"] = en_polarity;
1470 cell->parameters["\\SET_POLARITY"] = set_polarity;
1471 cell->parameters["\\CLR_POLARITY"] = clr_polarity;
1472 cell->parameters["\\WIDTH"] = sig_q.size();
1473 cell->setPort("\\EN", sig_en);
1474 cell->setPort("\\SET", sig_set);
1475 cell->setPort("\\CLR", sig_clr);
1476 cell->setPort("\\D", sig_d);
1477 cell->setPort("\\Q", sig_q);
1478 return cell;
1479 }
1480
1481 RTLIL::Cell* RTLIL::Module::addDffGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity)
1482 {
1483 RTLIL::Cell *cell = addCell(name, stringf("$_DFF_%c_", clk_polarity ? 'P' : 'N'));
1484 cell->setPort("\\C", sig_clk);
1485 cell->setPort("\\D", sig_d);
1486 cell->setPort("\\Q", sig_q);
1487 return cell;
1488 }
1489
1490 RTLIL::Cell* RTLIL::Module::addDffsrGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
1491 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity)
1492 {
1493 RTLIL::Cell *cell = addCell(name, stringf("$_DFFSR_%c%c%c_", clk_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N'));
1494 cell->setPort("\\C", sig_clk);
1495 cell->setPort("\\S", sig_set);
1496 cell->setPort("\\R", sig_clr);
1497 cell->setPort("\\D", sig_d);
1498 cell->setPort("\\Q", sig_q);
1499 return cell;
1500 }
1501
1502 RTLIL::Cell* RTLIL::Module::addAdffGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_arst, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q,
1503 bool arst_value, bool clk_polarity, bool arst_polarity)
1504 {
1505 RTLIL::Cell *cell = addCell(name, stringf("$_DFF_%c%c%c_", clk_polarity ? 'P' : 'N', arst_polarity ? 'P' : 'N', arst_value ? '1' : '0'));
1506 cell->setPort("\\C", sig_clk);
1507 cell->setPort("\\R", sig_arst);
1508 cell->setPort("\\D", sig_d);
1509 cell->setPort("\\Q", sig_q);
1510 return cell;
1511 }
1512
1513 RTLIL::Cell* RTLIL::Module::addDlatchGate(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity)
1514 {
1515 RTLIL::Cell *cell = addCell(name, stringf("$_DLATCH_%c_", en_polarity ? 'P' : 'N'));
1516 cell->setPort("\\E", sig_en);
1517 cell->setPort("\\D", sig_d);
1518 cell->setPort("\\Q", sig_q);
1519 return cell;
1520 }
1521
1522 RTLIL::Cell* RTLIL::Module::addDlatchsrGate(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
1523 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity, bool set_polarity, bool clr_polarity)
1524 {
1525 RTLIL::Cell *cell = addCell(name, stringf("$_DLATCHSR_%c%c%c_", en_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N'));
1526 cell->setPort("\\E", sig_en);
1527 cell->setPort("\\S", sig_set);
1528 cell->setPort("\\R", sig_clr);
1529 cell->setPort("\\D", sig_d);
1530 cell->setPort("\\Q", sig_q);
1531 return cell;
1532 }
1533
1534
1535 RTLIL::Wire::Wire()
1536 {
1537 module = nullptr;
1538 width = 1;
1539 start_offset = 0;
1540 port_id = 0;
1541 port_input = false;
1542 port_output = false;
1543 upto = false;
1544 }
1545
1546 RTLIL::Memory::Memory()
1547 {
1548 width = 1;
1549 size = 0;
1550 }
1551
1552 bool RTLIL::Cell::hasPort(RTLIL::IdString portname) const
1553 {
1554 return connections_.count(portname) != 0;
1555 }
1556
1557 void RTLIL::Cell::unsetPort(RTLIL::IdString portname)
1558 {
1559 RTLIL::SigSpec signal;
1560 auto conn_it = connections_.find(portname);
1561
1562 if (conn_it != connections_.end())
1563 {
1564 for (auto mon : module->monitors)
1565 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
1566
1567 if (module->design)
1568 for (auto mon : module->design->monitors)
1569 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
1570
1571 connections_.erase(conn_it);
1572 }
1573 }
1574
1575 void RTLIL::Cell::setPort(RTLIL::IdString portname, RTLIL::SigSpec signal)
1576 {
1577 auto conn_it = connections_.find(portname);
1578
1579 if (conn_it == connections_.end()) {
1580 connections_[portname] = RTLIL::SigSpec();
1581 conn_it = connections_.find(portname);
1582 log_assert(conn_it != connections_.end());
1583 }
1584
1585 for (auto mon : module->monitors)
1586 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
1587
1588 if (module->design)
1589 for (auto mon : module->design->monitors)
1590 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
1591
1592 conn_it->second = signal;
1593 }
1594
1595 const RTLIL::SigSpec &RTLIL::Cell::getPort(RTLIL::IdString portname) const
1596 {
1597 return connections_.at(portname);
1598 }
1599
1600 const std::map<RTLIL::IdString, RTLIL::SigSpec> &RTLIL::Cell::connections() const
1601 {
1602 return connections_;
1603 }
1604
1605 bool RTLIL::Cell::hasParam(RTLIL::IdString paramname) const
1606 {
1607 return parameters.count(paramname);
1608 }
1609
1610 void RTLIL::Cell::unsetParam(RTLIL::IdString paramname)
1611 {
1612 parameters.erase(paramname);
1613 }
1614
1615 void RTLIL::Cell::setParam(RTLIL::IdString paramname, RTLIL::Const value)
1616 {
1617 parameters[paramname] = value;
1618 }
1619
1620 const RTLIL::Const &RTLIL::Cell::getParam(RTLIL::IdString paramname) const
1621 {
1622 return parameters.at(paramname);
1623 }
1624
1625 void RTLIL::Cell::check()
1626 {
1627 #ifndef NDEBUG
1628 InternalCellChecker checker(NULL, this);
1629 checker.check();
1630 #endif
1631 }
1632
1633 void RTLIL::Cell::fixup_parameters(bool set_a_signed, bool set_b_signed)
1634 {
1635 if (type.substr(0, 1) != "$" || type.substr(0, 2) == "$_" || type.substr(0, 8) == "$paramod" ||
1636 type.substr(0, 9) == "$verific$" || type.substr(0, 7) == "$array:" || type.substr(0, 8) == "$extern:")
1637 return;
1638
1639 if (type == "$mux" || type == "$pmux")
1640 {
1641 parameters["\\WIDTH"] = SIZE(connections_["\\Y"]);
1642 if (type == "$pmux")
1643 parameters["\\S_WIDTH"] = SIZE(connections_["\\S"]);
1644 check();
1645 return;
1646 }
1647
1648 bool signedness_ab = type != "$slice" && type != "$concat";
1649
1650 if (connections_.count("\\A")) {
1651 if (signedness_ab) {
1652 if (set_a_signed)
1653 parameters["\\A_SIGNED"] = true;
1654 else if (parameters.count("\\A_SIGNED") == 0)
1655 parameters["\\A_SIGNED"] = false;
1656 }
1657 parameters["\\A_WIDTH"] = SIZE(connections_["\\A"]);
1658 }
1659
1660 if (connections_.count("\\B")) {
1661 if (signedness_ab) {
1662 if (set_b_signed)
1663 parameters["\\B_SIGNED"] = true;
1664 else if (parameters.count("\\B_SIGNED") == 0)
1665 parameters["\\B_SIGNED"] = false;
1666 }
1667 parameters["\\B_WIDTH"] = SIZE(connections_["\\B"]);
1668 }
1669
1670 if (connections_.count("\\Y"))
1671 parameters["\\Y_WIDTH"] = SIZE(connections_["\\Y"]);
1672
1673 check();
1674 }
1675
1676 RTLIL::SigChunk::SigChunk()
1677 {
1678 wire = NULL;
1679 width = 0;
1680 offset = 0;
1681 }
1682
1683 RTLIL::SigChunk::SigChunk(const RTLIL::Const &value)
1684 {
1685 wire = NULL;
1686 data = value;
1687 width = data.bits.size();
1688 offset = 0;
1689 }
1690
1691 RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire)
1692 {
1693 log_assert(wire != nullptr);
1694 this->wire = wire;
1695 this->width = wire->width;
1696 this->offset = 0;
1697 }
1698
1699 RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire, int offset, int width)
1700 {
1701 log_assert(wire != nullptr);
1702 this->wire = wire;
1703 this->width = width;
1704 this->offset = offset;
1705 }
1706
1707 RTLIL::SigChunk::SigChunk(const std::string &str)
1708 {
1709 wire = NULL;
1710 data = RTLIL::Const(str);
1711 width = data.bits.size();
1712 offset = 0;
1713 }
1714
1715 RTLIL::SigChunk::SigChunk(int val, int width)
1716 {
1717 wire = NULL;
1718 data = RTLIL::Const(val, width);
1719 this->width = data.bits.size();
1720 offset = 0;
1721 }
1722
1723 RTLIL::SigChunk::SigChunk(RTLIL::State bit, int width)
1724 {
1725 wire = NULL;
1726 data = RTLIL::Const(bit, width);
1727 this->width = data.bits.size();
1728 offset = 0;
1729 }
1730
1731 RTLIL::SigChunk::SigChunk(RTLIL::SigBit bit)
1732 {
1733 wire = bit.wire;
1734 offset = 0;
1735 if (wire == NULL)
1736 data = RTLIL::Const(bit.data);
1737 else
1738 offset = bit.offset;
1739 width = 1;
1740 }
1741
1742 RTLIL::SigChunk RTLIL::SigChunk::extract(int offset, int length) const
1743 {
1744 RTLIL::SigChunk ret;
1745 if (wire) {
1746 ret.wire = wire;
1747 ret.offset = this->offset + offset;
1748 ret.width = length;
1749 } else {
1750 for (int i = 0; i < length; i++)
1751 ret.data.bits.push_back(data.bits[offset+i]);
1752 ret.width = length;
1753 }
1754 return ret;
1755 }
1756
1757 bool RTLIL::SigChunk::operator <(const RTLIL::SigChunk &other) const
1758 {
1759 if (wire && other.wire)
1760 if (wire->name != other.wire->name)
1761 return wire->name < other.wire->name;
1762
1763 if (wire != other.wire)
1764 return wire < other.wire;
1765
1766 if (offset != other.offset)
1767 return offset < other.offset;
1768
1769 if (width != other.width)
1770 return width < other.width;
1771
1772 return data.bits < other.data.bits;
1773 }
1774
1775 bool RTLIL::SigChunk::operator ==(const RTLIL::SigChunk &other) const
1776 {
1777 if (wire != other.wire || width != other.width || offset != other.offset)
1778 return false;
1779 if (data.bits != other.data.bits)
1780 return false;
1781 return true;
1782 }
1783
1784 bool RTLIL::SigChunk::operator !=(const RTLIL::SigChunk &other) const
1785 {
1786 if (*this == other)
1787 return false;
1788 return true;
1789 }
1790
1791 RTLIL::SigSpec::SigSpec()
1792 {
1793 width_ = 0;
1794 hash_ = 0;
1795 }
1796
1797 RTLIL::SigSpec::SigSpec(const RTLIL::SigSpec &other)
1798 {
1799 *this = other;
1800 }
1801
1802 RTLIL::SigSpec::SigSpec(std::initializer_list<RTLIL::SigSpec> parts)
1803 {
1804 cover("kernel.rtlil.sigspec.init.list");
1805
1806 width_ = 0;
1807 hash_ = 0;
1808
1809 std::vector<RTLIL::SigSpec> parts_vec(parts.begin(), parts.end());
1810 for (auto it = parts_vec.rbegin(); it != parts_vec.rend(); it++)
1811 append(*it);
1812 }
1813
1814 const RTLIL::SigSpec &RTLIL::SigSpec::operator=(const RTLIL::SigSpec &other)
1815 {
1816 cover("kernel.rtlil.sigspec.assign");
1817
1818 width_ = other.width_;
1819 hash_ = other.hash_;
1820 chunks_ = other.chunks_;
1821 bits_.clear();
1822
1823 if (!other.bits_.empty())
1824 {
1825 RTLIL::SigChunk *last = NULL;
1826 int last_end_offset = 0;
1827
1828 for (auto &bit : other.bits_) {
1829 if (last && bit.wire == last->wire) {
1830 if (bit.wire == NULL) {
1831 last->data.bits.push_back(bit.data);
1832 last->width++;
1833 continue;
1834 } else if (last_end_offset == bit.offset) {
1835 last_end_offset++;
1836 last->width++;
1837 continue;
1838 }
1839 }
1840 chunks_.push_back(bit);
1841 last = &chunks_.back();
1842 last_end_offset = bit.offset + 1;
1843 }
1844
1845 check();
1846 }
1847
1848 return *this;
1849 }
1850
1851 RTLIL::SigSpec::SigSpec(const RTLIL::Const &value)
1852 {
1853 cover("kernel.rtlil.sigspec.init.const");
1854
1855 chunks_.push_back(RTLIL::SigChunk(value));
1856 width_ = chunks_.back().width;
1857 hash_ = 0;
1858 check();
1859 }
1860
1861 RTLIL::SigSpec::SigSpec(const RTLIL::SigChunk &chunk)
1862 {
1863 cover("kernel.rtlil.sigspec.init.chunk");
1864
1865 chunks_.push_back(chunk);
1866 width_ = chunks_.back().width;
1867 hash_ = 0;
1868 check();
1869 }
1870
1871 RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire)
1872 {
1873 cover("kernel.rtlil.sigspec.init.wire");
1874
1875 chunks_.push_back(RTLIL::SigChunk(wire));
1876 width_ = chunks_.back().width;
1877 hash_ = 0;
1878 check();
1879 }
1880
1881 RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire, int offset, int width)
1882 {
1883 cover("kernel.rtlil.sigspec.init.wire_part");
1884
1885 chunks_.push_back(RTLIL::SigChunk(wire, offset, width));
1886 width_ = chunks_.back().width;
1887 hash_ = 0;
1888 check();
1889 }
1890
1891 RTLIL::SigSpec::SigSpec(const std::string &str)
1892 {
1893 cover("kernel.rtlil.sigspec.init.str");
1894
1895 chunks_.push_back(RTLIL::SigChunk(str));
1896 width_ = chunks_.back().width;
1897 hash_ = 0;
1898 check();
1899 }
1900
1901 RTLIL::SigSpec::SigSpec(int val, int width)
1902 {
1903 cover("kernel.rtlil.sigspec.init.int");
1904
1905 chunks_.push_back(RTLIL::SigChunk(val, width));
1906 width_ = width;
1907 hash_ = 0;
1908 check();
1909 }
1910
1911 RTLIL::SigSpec::SigSpec(RTLIL::State bit, int width)
1912 {
1913 cover("kernel.rtlil.sigspec.init.state");
1914
1915 chunks_.push_back(RTLIL::SigChunk(bit, width));
1916 width_ = width;
1917 hash_ = 0;
1918 check();
1919 }
1920
1921 RTLIL::SigSpec::SigSpec(RTLIL::SigBit bit, int width)
1922 {
1923 cover("kernel.rtlil.sigspec.init.bit");
1924
1925 if (bit.wire == NULL)
1926 chunks_.push_back(RTLIL::SigChunk(bit.data, width));
1927 else
1928 for (int i = 0; i < width; i++)
1929 chunks_.push_back(bit);
1930 width_ = width;
1931 hash_ = 0;
1932 check();
1933 }
1934
1935 RTLIL::SigSpec::SigSpec(std::vector<RTLIL::SigChunk> chunks)
1936 {
1937 cover("kernel.rtlil.sigspec.init.stdvec_chunks");
1938
1939 width_ = 0;
1940 hash_ = 0;
1941 for (auto &c : chunks)
1942 append(c);
1943 check();
1944 }
1945
1946 RTLIL::SigSpec::SigSpec(std::vector<RTLIL::SigBit> bits)
1947 {
1948 cover("kernel.rtlil.sigspec.init.stdvec_bits");
1949
1950 width_ = 0;
1951 hash_ = 0;
1952 for (auto &bit : bits)
1953 append_bit(bit);
1954 check();
1955 }
1956
1957 RTLIL::SigSpec::SigSpec(std::set<RTLIL::SigBit> bits)
1958 {
1959 cover("kernel.rtlil.sigspec.init.stdset_bits");
1960
1961 width_ = 0;
1962 hash_ = 0;
1963 for (auto &bit : bits)
1964 append_bit(bit);
1965 check();
1966 }
1967
1968 void RTLIL::SigSpec::pack() const
1969 {
1970 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
1971
1972 if (that->bits_.empty())
1973 return;
1974
1975 cover("kernel.rtlil.sigspec.convert.pack");
1976 log_assert(that->chunks_.empty());
1977
1978 std::vector<RTLIL::SigBit> old_bits;
1979 old_bits.swap(that->bits_);
1980
1981 RTLIL::SigChunk *last = NULL;
1982 int last_end_offset = 0;
1983
1984 for (auto &bit : old_bits) {
1985 if (last && bit.wire == last->wire) {
1986 if (bit.wire == NULL) {
1987 last->data.bits.push_back(bit.data);
1988 last->width++;
1989 continue;
1990 } else if (last_end_offset == bit.offset) {
1991 last_end_offset++;
1992 last->width++;
1993 continue;
1994 }
1995 }
1996 that->chunks_.push_back(bit);
1997 last = &that->chunks_.back();
1998 last_end_offset = bit.offset + 1;
1999 }
2000
2001 check();
2002 }
2003
2004 void RTLIL::SigSpec::unpack() const
2005 {
2006 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
2007
2008 if (that->chunks_.empty())
2009 return;
2010
2011 cover("kernel.rtlil.sigspec.convert.unpack");
2012 log_assert(that->bits_.empty());
2013
2014 that->bits_.reserve(that->width_);
2015 for (auto &c : that->chunks_)
2016 for (int i = 0; i < c.width; i++)
2017 that->bits_.push_back(RTLIL::SigBit(c, i));
2018
2019 that->chunks_.clear();
2020 that->hash_ = 0;
2021 }
2022
2023 #define DJB2(_hash, _value) do { (_hash) = (((_hash) << 5) + (_hash)) + (_value); } while (0)
2024
2025 void RTLIL::SigSpec::hash() const
2026 {
2027 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
2028
2029 if (that->hash_ != 0)
2030 return;
2031
2032 cover("kernel.rtlil.sigspec.hash");
2033 that->pack();
2034
2035 that->hash_ = 5381;
2036 for (auto &c : that->chunks_)
2037 if (c.wire == NULL) {
2038 for (auto &v : c.data.bits)
2039 DJB2(that->hash_, v);
2040 } else {
2041 DJB2(that->hash_, c.wire->name.index_);
2042 DJB2(that->hash_, c.offset);
2043 DJB2(that->hash_, c.width);
2044 }
2045
2046 if (that->hash_ == 0)
2047 that->hash_ = 1;
2048 }
2049
2050 void RTLIL::SigSpec::sort()
2051 {
2052 unpack();
2053 cover("kernel.rtlil.sigspec.sort");
2054 std::sort(bits_.begin(), bits_.end());
2055 }
2056
2057 void RTLIL::SigSpec::sort_and_unify()
2058 {
2059 cover("kernel.rtlil.sigspec.sort_and_unify");
2060 *this = this->to_sigbit_set();
2061 }
2062
2063 void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with)
2064 {
2065 replace(pattern, with, this);
2066 }
2067
2068 void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with, RTLIL::SigSpec *other) const
2069 {
2070 cover("kernel.rtlil.sigspec.replace");
2071
2072 unpack();
2073 pattern.unpack();
2074 with.unpack();
2075
2076 log_assert(other != NULL);
2077 log_assert(width_ == other->width_);
2078 other->unpack();
2079
2080 log_assert(pattern.width_ == with.width_);
2081
2082 std::map<RTLIL::SigBit, RTLIL::SigBit> pattern_map;
2083 for (int i = 0; i < SIZE(pattern.bits_); i++)
2084 if (pattern.bits_[i].wire != NULL)
2085 pattern_map[pattern.bits_[i]] = with.bits_[i];
2086
2087 for (int i = 0; i < SIZE(bits_); i++)
2088 if (pattern_map.count(bits_[i]))
2089 other->bits_[i] = pattern_map.at(bits_[i]);
2090
2091 other->check();
2092 }
2093
2094 void RTLIL::SigSpec::remove(const RTLIL::SigSpec &pattern)
2095 {
2096 remove2(pattern, NULL);
2097 }
2098
2099 void RTLIL::SigSpec::remove(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other) const
2100 {
2101 RTLIL::SigSpec tmp = *this;
2102 tmp.remove2(pattern, other);
2103 }
2104
2105 void RTLIL::SigSpec::remove2(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other)
2106 {
2107 if (other)
2108 cover("kernel.rtlil.sigspec.remove_other");
2109 else
2110 cover("kernel.rtlil.sigspec.remove");
2111
2112 unpack();
2113
2114 if (other != NULL) {
2115 log_assert(width_ == other->width_);
2116 other->unpack();
2117 }
2118
2119 std::set<RTLIL::SigBit> pattern_bits = pattern.to_sigbit_set();
2120 std::vector<RTLIL::SigBit> new_bits, new_other_bits;
2121
2122 for (int i = 0; i < SIZE(bits_); i++) {
2123 if (bits_[i].wire != NULL && pattern_bits.count(bits_[i]))
2124 continue;
2125 if (other != NULL)
2126 new_other_bits.push_back(other->bits_[i]);
2127 new_bits.push_back(bits_[i]);
2128 }
2129
2130 bits_.swap(new_bits);
2131 width_ = SIZE(bits_);
2132
2133 if (other != NULL) {
2134 other->bits_.swap(new_other_bits);
2135 other->width_ = SIZE(other->bits_);
2136 }
2137
2138 check();
2139 }
2140
2141 RTLIL::SigSpec RTLIL::SigSpec::extract(RTLIL::SigSpec pattern, const RTLIL::SigSpec *other) const
2142 {
2143 if (other)
2144 cover("kernel.rtlil.sigspec.extract_other");
2145 else
2146 cover("kernel.rtlil.sigspec.extract");
2147
2148 pack();
2149 pattern.pack();
2150
2151 if (other != NULL)
2152 other->pack();
2153
2154 log_assert(other == NULL || width_ == other->width_);
2155
2156 std::set<RTLIL::SigBit> pat = pattern.to_sigbit_set();
2157 std::vector<RTLIL::SigBit> bits_match = to_sigbit_vector();
2158 RTLIL::SigSpec ret;
2159
2160 if (other) {
2161 std::vector<RTLIL::SigBit> bits_other = other->to_sigbit_vector();
2162 for (int i = 0; i < width_; i++)
2163 if (bits_match[i].wire && pat.count(bits_match[i]))
2164 ret.append_bit(bits_other[i]);
2165 } else {
2166 for (int i = 0; i < width_; i++)
2167 if (bits_match[i].wire && pat.count(bits_match[i]))
2168 ret.append_bit(bits_match[i]);
2169 }
2170
2171 ret.check();
2172 return ret;
2173 }
2174
2175 void RTLIL::SigSpec::replace(int offset, const RTLIL::SigSpec &with)
2176 {
2177 cover("kernel.rtlil.sigspec.replace_pos");
2178
2179 unpack();
2180 with.unpack();
2181
2182 log_assert(offset >= 0);
2183 log_assert(with.width_ >= 0);
2184 log_assert(offset+with.width_ <= width_);
2185
2186 for (int i = 0; i < with.width_; i++)
2187 bits_.at(offset + i) = with.bits_.at(i);
2188
2189 check();
2190 }
2191
2192 void RTLIL::SigSpec::remove_const()
2193 {
2194 if (packed())
2195 {
2196 cover("kernel.rtlil.sigspec.remove_const.packed");
2197
2198 std::vector<RTLIL::SigChunk> new_chunks;
2199 new_chunks.reserve(SIZE(chunks_));
2200
2201 width_ = 0;
2202 for (auto &chunk : chunks_)
2203 if (chunk.wire != NULL) {
2204 new_chunks.push_back(chunk);
2205 width_ += chunk.width;
2206 }
2207
2208 chunks_.swap(new_chunks);
2209 }
2210 else
2211 {
2212 cover("kernel.rtlil.sigspec.remove_const.unpacked");
2213
2214 std::vector<RTLIL::SigBit> new_bits;
2215 new_bits.reserve(width_);
2216
2217 for (auto &bit : bits_)
2218 if (bit.wire != NULL)
2219 new_bits.push_back(bit);
2220
2221 bits_.swap(new_bits);
2222 width_ = bits_.size();
2223 }
2224
2225 check();
2226 }
2227
2228 void RTLIL::SigSpec::remove(int offset, int length)
2229 {
2230 cover("kernel.rtlil.sigspec.remove_pos");
2231
2232 unpack();
2233
2234 log_assert(offset >= 0);
2235 log_assert(length >= 0);
2236 log_assert(offset + length <= width_);
2237
2238 bits_.erase(bits_.begin() + offset, bits_.begin() + offset + length);
2239 width_ = bits_.size();
2240
2241 check();
2242 }
2243
2244 RTLIL::SigSpec RTLIL::SigSpec::extract(int offset, int length) const
2245 {
2246 unpack();
2247 cover("kernel.rtlil.sigspec.extract_pos");
2248 return std::vector<RTLIL::SigBit>(bits_.begin() + offset, bits_.begin() + offset + length);
2249 }
2250
2251 void RTLIL::SigSpec::append(const RTLIL::SigSpec &signal)
2252 {
2253 if (signal.width_ == 0)
2254 return;
2255
2256 if (width_ == 0) {
2257 *this = signal;
2258 return;
2259 }
2260
2261 cover("kernel.rtlil.sigspec.append");
2262
2263 if (packed() != signal.packed()) {
2264 pack();
2265 signal.pack();
2266 }
2267
2268 if (packed())
2269 for (auto &other_c : signal.chunks_)
2270 {
2271 auto &my_last_c = chunks_.back();
2272 if (my_last_c.wire == NULL && other_c.wire == NULL) {
2273 auto &this_data = my_last_c.data.bits;
2274 auto &other_data = other_c.data.bits;
2275 this_data.insert(this_data.end(), other_data.begin(), other_data.end());
2276 my_last_c.width += other_c.width;
2277 } else
2278 if (my_last_c.wire == other_c.wire && my_last_c.offset + my_last_c.width == other_c.offset) {
2279 my_last_c.width += other_c.width;
2280 } else
2281 chunks_.push_back(other_c);
2282 }
2283 else
2284 bits_.insert(bits_.end(), signal.bits_.begin(), signal.bits_.end());
2285
2286 width_ += signal.width_;
2287 check();
2288 }
2289
2290 void RTLIL::SigSpec::append_bit(const RTLIL::SigBit &bit)
2291 {
2292 if (packed())
2293 {
2294 cover("kernel.rtlil.sigspec.append_bit.packed");
2295
2296 if (chunks_.size() == 0)
2297 chunks_.push_back(bit);
2298 else
2299 if (bit.wire == NULL)
2300 if (chunks_.back().wire == NULL) {
2301 chunks_.back().data.bits.push_back(bit.data);
2302 chunks_.back().width++;
2303 } else
2304 chunks_.push_back(bit);
2305 else
2306 if (chunks_.back().wire == bit.wire && chunks_.back().offset + chunks_.back().width == bit.offset)
2307 chunks_.back().width++;
2308 else
2309 chunks_.push_back(bit);
2310 }
2311 else
2312 {
2313 cover("kernel.rtlil.sigspec.append_bit.unpacked");
2314 bits_.push_back(bit);
2315 }
2316
2317 width_++;
2318 check();
2319 }
2320
2321 void RTLIL::SigSpec::extend(int width, bool is_signed)
2322 {
2323 cover("kernel.rtlil.sigspec.extend");
2324
2325 pack();
2326
2327 if (width_ > width)
2328 remove(width, width_ - width);
2329
2330 if (width_ < width) {
2331 RTLIL::SigSpec padding = width_ > 0 ? extract(width_ - 1, 1) : RTLIL::SigSpec(RTLIL::State::S0);
2332 if (!is_signed && padding != RTLIL::SigSpec(RTLIL::State::Sx) && padding != RTLIL::SigSpec(RTLIL::State::Sz) &&
2333 padding != RTLIL::SigSpec(RTLIL::State::Sa) && padding != RTLIL::SigSpec(RTLIL::State::Sm))
2334 padding = RTLIL::SigSpec(RTLIL::State::S0);
2335 while (width_ < width)
2336 append(padding);
2337 }
2338 }
2339
2340 void RTLIL::SigSpec::extend_u0(int width, bool is_signed)
2341 {
2342 cover("kernel.rtlil.sigspec.extend_u0");
2343
2344 pack();
2345
2346 if (width_ > width)
2347 remove(width, width_ - width);
2348
2349 if (width_ < width) {
2350 RTLIL::SigSpec padding = width_ > 0 ? extract(width_ - 1, 1) : RTLIL::SigSpec(RTLIL::State::S0);
2351 if (!is_signed)
2352 padding = RTLIL::SigSpec(RTLIL::State::S0);
2353 while (width_ < width)
2354 append(padding);
2355 }
2356
2357 }
2358
2359 RTLIL::SigSpec RTLIL::SigSpec::repeat(int num) const
2360 {
2361 cover("kernel.rtlil.sigspec.repeat");
2362
2363 RTLIL::SigSpec sig;
2364 for (int i = 0; i < num; i++)
2365 sig.append(*this);
2366 return sig;
2367 }
2368
2369 #ifndef NDEBUG
2370 void RTLIL::SigSpec::check() const
2371 {
2372 if (width_ > 64)
2373 {
2374 cover("kernel.rtlil.sigspec.check.skip");
2375 }
2376 else if (packed())
2377 {
2378 cover("kernel.rtlil.sigspec.check.packed");
2379
2380 int w = 0;
2381 for (size_t i = 0; i < chunks_.size(); i++) {
2382 const RTLIL::SigChunk chunk = chunks_[i];
2383 if (chunk.wire == NULL) {
2384 if (i > 0)
2385 log_assert(chunks_[i-1].wire != NULL);
2386 log_assert(chunk.offset == 0);
2387 log_assert(chunk.data.bits.size() == (size_t)chunk.width);
2388 } else {
2389 if (i > 0 && chunks_[i-1].wire == chunk.wire)
2390 log_assert(chunk.offset != chunks_[i-1].offset + chunks_[i-1].width);
2391 log_assert(chunk.offset >= 0);
2392 log_assert(chunk.width >= 0);
2393 log_assert(chunk.offset + chunk.width <= chunk.wire->width);
2394 log_assert(chunk.data.bits.size() == 0);
2395 }
2396 w += chunk.width;
2397 }
2398 log_assert(w == width_);
2399 log_assert(bits_.empty());
2400 }
2401 else
2402 {
2403 cover("kernel.rtlil.sigspec.check.unpacked");
2404
2405 log_assert(width_ == SIZE(bits_));
2406 log_assert(chunks_.empty());
2407 }
2408 }
2409 #endif
2410
2411 bool RTLIL::SigSpec::operator <(const RTLIL::SigSpec &other) const
2412 {
2413 cover("kernel.rtlil.sigspec.comp_lt");
2414
2415 if (this == &other)
2416 return false;
2417
2418 if (width_ != other.width_)
2419 return width_ < other.width_;
2420
2421 pack();
2422 other.pack();
2423
2424 if (chunks_.size() != other.chunks_.size())
2425 return chunks_.size() < other.chunks_.size();
2426
2427 hash();
2428 other.hash();
2429
2430 if (hash_ != other.hash_)
2431 return hash_ < other.hash_;
2432
2433 for (size_t i = 0; i < chunks_.size(); i++)
2434 if (chunks_[i] != other.chunks_[i]) {
2435 cover("kernel.rtlil.sigspec.comp_lt.hash_collision");
2436 return chunks_[i] < other.chunks_[i];
2437 }
2438
2439 cover("kernel.rtlil.sigspec.comp_lt.equal");
2440 return false;
2441 }
2442
2443 bool RTLIL::SigSpec::operator ==(const RTLIL::SigSpec &other) const
2444 {
2445 cover("kernel.rtlil.sigspec.comp_eq");
2446
2447 if (this == &other)
2448 return true;
2449
2450 if (width_ != other.width_)
2451 return false;
2452
2453 pack();
2454 other.pack();
2455
2456 if (chunks_.size() != chunks_.size())
2457 return false;
2458
2459 hash();
2460 other.hash();
2461
2462 if (hash_ != other.hash_)
2463 return false;
2464
2465 for (size_t i = 0; i < chunks_.size(); i++)
2466 if (chunks_[i] != other.chunks_[i]) {
2467 cover("kernel.rtlil.sigspec.comp_eq.hash_collision");
2468 return false;
2469 }
2470
2471 cover("kernel.rtlil.sigspec.comp_eq.equal");
2472 return true;
2473 }
2474
2475 bool RTLIL::SigSpec::is_wire() const
2476 {
2477 cover("kernel.rtlil.sigspec.is_wire");
2478
2479 pack();
2480 return SIZE(chunks_) == 1 && chunks_[0].wire && chunks_[0].wire->width == width_;
2481 }
2482
2483 bool RTLIL::SigSpec::is_chunk() const
2484 {
2485 cover("kernel.rtlil.sigspec.is_chunk");
2486
2487 pack();
2488 return SIZE(chunks_) == 1;
2489 }
2490
2491 bool RTLIL::SigSpec::is_fully_const() const
2492 {
2493 cover("kernel.rtlil.sigspec.is_fully_const");
2494
2495 pack();
2496 for (auto it = chunks_.begin(); it != chunks_.end(); it++)
2497 if (it->width > 0 && it->wire != NULL)
2498 return false;
2499 return true;
2500 }
2501
2502 bool RTLIL::SigSpec::is_fully_def() const
2503 {
2504 cover("kernel.rtlil.sigspec.is_fully_def");
2505
2506 pack();
2507 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
2508 if (it->width > 0 && it->wire != NULL)
2509 return false;
2510 for (size_t i = 0; i < it->data.bits.size(); i++)
2511 if (it->data.bits[i] != RTLIL::State::S0 && it->data.bits[i] != RTLIL::State::S1)
2512 return false;
2513 }
2514 return true;
2515 }
2516
2517 bool RTLIL::SigSpec::is_fully_undef() const
2518 {
2519 cover("kernel.rtlil.sigspec.is_fully_undef");
2520
2521 pack();
2522 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
2523 if (it->width > 0 && it->wire != NULL)
2524 return false;
2525 for (size_t i = 0; i < it->data.bits.size(); i++)
2526 if (it->data.bits[i] != RTLIL::State::Sx && it->data.bits[i] != RTLIL::State::Sz)
2527 return false;
2528 }
2529 return true;
2530 }
2531
2532 bool RTLIL::SigSpec::has_marked_bits() const
2533 {
2534 cover("kernel.rtlil.sigspec.has_marked_bits");
2535
2536 pack();
2537 for (auto it = chunks_.begin(); it != chunks_.end(); it++)
2538 if (it->width > 0 && it->wire == NULL) {
2539 for (size_t i = 0; i < it->data.bits.size(); i++)
2540 if (it->data.bits[i] == RTLIL::State::Sm)
2541 return true;
2542 }
2543 return false;
2544 }
2545
2546 bool RTLIL::SigSpec::as_bool() const
2547 {
2548 cover("kernel.rtlil.sigspec.as_bool");
2549
2550 pack();
2551 log_assert(is_fully_const() && SIZE(chunks_) <= 1);
2552 if (width_)
2553 return chunks_[0].data.as_bool();
2554 return false;
2555 }
2556
2557 int RTLIL::SigSpec::as_int() const
2558 {
2559 cover("kernel.rtlil.sigspec.as_int");
2560
2561 pack();
2562 log_assert(is_fully_const() && SIZE(chunks_) <= 1);
2563 if (width_)
2564 return chunks_[0].data.as_int();
2565 return 0;
2566 }
2567
2568 std::string RTLIL::SigSpec::as_string() const
2569 {
2570 cover("kernel.rtlil.sigspec.as_string");
2571
2572 pack();
2573 std::string str;
2574 for (size_t i = chunks_.size(); i > 0; i--) {
2575 const RTLIL::SigChunk &chunk = chunks_[i-1];
2576 if (chunk.wire != NULL)
2577 for (int j = 0; j < chunk.width; j++)
2578 str += "?";
2579 else
2580 str += chunk.data.as_string();
2581 }
2582 return str;
2583 }
2584
2585 RTLIL::Const RTLIL::SigSpec::as_const() const
2586 {
2587 cover("kernel.rtlil.sigspec.as_const");
2588
2589 pack();
2590 log_assert(is_fully_const() && SIZE(chunks_) <= 1);
2591 if (width_)
2592 return chunks_[0].data;
2593 return RTLIL::Const();
2594 }
2595
2596 RTLIL::Wire *RTLIL::SigSpec::as_wire() const
2597 {
2598 cover("kernel.rtlil.sigspec.as_wire");
2599
2600 pack();
2601 log_assert(is_wire());
2602 return chunks_[0].wire;
2603 }
2604
2605 RTLIL::SigChunk RTLIL::SigSpec::as_chunk() const
2606 {
2607 cover("kernel.rtlil.sigspec.as_chunk");
2608
2609 pack();
2610 log_assert(is_chunk());
2611 return chunks_[0];
2612 }
2613
2614 bool RTLIL::SigSpec::match(std::string pattern) const
2615 {
2616 cover("kernel.rtlil.sigspec.match");
2617
2618 pack();
2619 std::string str = as_string();
2620 log_assert(pattern.size() == str.size());
2621
2622 for (size_t i = 0; i < pattern.size(); i++) {
2623 if (pattern[i] == ' ')
2624 continue;
2625 if (pattern[i] == '*') {
2626 if (str[i] != 'z' && str[i] != 'x')
2627 return false;
2628 continue;
2629 }
2630 if (pattern[i] != str[i])
2631 return false;
2632 }
2633
2634 return true;
2635 }
2636
2637 std::set<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_set() const
2638 {
2639 cover("kernel.rtlil.sigspec.to_sigbit_set");
2640
2641 pack();
2642 std::set<RTLIL::SigBit> sigbits;
2643 for (auto &c : chunks_)
2644 for (int i = 0; i < c.width; i++)
2645 sigbits.insert(RTLIL::SigBit(c, i));
2646 return sigbits;
2647 }
2648
2649 std::vector<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_vector() const
2650 {
2651 cover("kernel.rtlil.sigspec.to_sigbit_vector");
2652
2653 unpack();
2654 return bits_;
2655 }
2656
2657 RTLIL::SigBit RTLIL::SigSpec::to_single_sigbit() const
2658 {
2659 cover("kernel.rtlil.sigspec.to_single_sigbit");
2660
2661 pack();
2662 log_assert(width_ == 1);
2663 for (auto &c : chunks_)
2664 if (c.width)
2665 return RTLIL::SigBit(c);
2666 log_abort();
2667 }
2668
2669 static void sigspec_parse_split(std::vector<std::string> &tokens, const std::string &text, char sep)
2670 {
2671 size_t start = 0, end = 0;
2672 while ((end = text.find(sep, start)) != std::string::npos) {
2673 tokens.push_back(text.substr(start, end - start));
2674 start = end + 1;
2675 }
2676 tokens.push_back(text.substr(start));
2677 }
2678
2679 static int sigspec_parse_get_dummy_line_num()
2680 {
2681 return 0;
2682 }
2683
2684 bool RTLIL::SigSpec::parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str)
2685 {
2686 cover("kernel.rtlil.sigspec.parse");
2687
2688 std::vector<std::string> tokens;
2689 sigspec_parse_split(tokens, str, ',');
2690
2691 sig = RTLIL::SigSpec();
2692 for (int tokidx = int(tokens.size())-1; tokidx >= 0; tokidx--)
2693 {
2694 std::string netname = tokens[tokidx];
2695 std::string indices;
2696
2697 if (netname.size() == 0)
2698 continue;
2699
2700 if ('0' <= netname[0] && netname[0] <= '9') {
2701 cover("kernel.rtlil.sigspec.parse.const");
2702 AST::get_line_num = sigspec_parse_get_dummy_line_num;
2703 AST::AstNode *ast = VERILOG_FRONTEND::const2ast(netname);
2704 if (ast == NULL)
2705 return false;
2706 sig.append(RTLIL::Const(ast->bits));
2707 delete ast;
2708 continue;
2709 }
2710
2711 if (module == NULL)
2712 return false;
2713
2714 cover("kernel.rtlil.sigspec.parse.net");
2715
2716 if (netname[0] != '$' && netname[0] != '\\')
2717 netname = "\\" + netname;
2718
2719 if (module->wires_.count(netname) == 0) {
2720 size_t indices_pos = netname.size()-1;
2721 if (indices_pos > 2 && netname[indices_pos] == ']')
2722 {
2723 indices_pos--;
2724 while (indices_pos > 0 && ('0' <= netname[indices_pos] && netname[indices_pos] <= '9')) indices_pos--;
2725 if (indices_pos > 0 && netname[indices_pos] == ':') {
2726 indices_pos--;
2727 while (indices_pos > 0 && ('0' <= netname[indices_pos] && netname[indices_pos] <= '9')) indices_pos--;
2728 }
2729 if (indices_pos > 0 && netname[indices_pos] == '[') {
2730 indices = netname.substr(indices_pos);
2731 netname = netname.substr(0, indices_pos);
2732 }
2733 }
2734 }
2735
2736 if (module->wires_.count(netname) == 0)
2737 return false;
2738
2739 RTLIL::Wire *wire = module->wires_.at(netname);
2740 if (!indices.empty()) {
2741 std::vector<std::string> index_tokens;
2742 sigspec_parse_split(index_tokens, indices.substr(1, indices.size()-2), ':');
2743 if (index_tokens.size() == 1) {
2744 cover("kernel.rtlil.sigspec.parse.bit_sel");
2745 sig.append(RTLIL::SigSpec(wire, atoi(index_tokens.at(0).c_str())));
2746 } else {
2747 cover("kernel.rtlil.sigspec.parse.part_sel");
2748 int a = atoi(index_tokens.at(0).c_str());
2749 int b = atoi(index_tokens.at(1).c_str());
2750 if (a > b) {
2751 int tmp = a;
2752 a = b, b = tmp;
2753 }
2754 sig.append(RTLIL::SigSpec(wire, a, b-a+1));
2755 }
2756 } else
2757 sig.append(wire);
2758 }
2759
2760 return true;
2761 }
2762
2763 bool RTLIL::SigSpec::parse_sel(RTLIL::SigSpec &sig, RTLIL::Design *design, RTLIL::Module *module, std::string str)
2764 {
2765 if (str.empty() || str[0] != '@')
2766 return parse(sig, module, str);
2767
2768 cover("kernel.rtlil.sigspec.parse.sel");
2769
2770 str = RTLIL::escape_id(str.substr(1));
2771 if (design->selection_vars.count(str) == 0)
2772 return false;
2773
2774 sig = RTLIL::SigSpec();
2775 RTLIL::Selection &sel = design->selection_vars.at(str);
2776 for (auto &it : module->wires_)
2777 if (sel.selected_member(module->name, it.first))
2778 sig.append(it.second);
2779
2780 return true;
2781 }
2782
2783 bool RTLIL::SigSpec::parse_rhs(const RTLIL::SigSpec &lhs, RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str)
2784 {
2785 if (str == "0") {
2786 cover("kernel.rtlil.sigspec.parse.rhs_zeros");
2787 sig = RTLIL::SigSpec(RTLIL::State::S0, lhs.width_);
2788 return true;
2789 }
2790
2791 if (str == "~0") {
2792 cover("kernel.rtlil.sigspec.parse.rhs_ones");
2793 sig = RTLIL::SigSpec(RTLIL::State::S1, lhs.width_);
2794 return true;
2795 }
2796
2797 if (lhs.chunks_.size() == 1) {
2798 char *p = (char*)str.c_str(), *endptr;
2799 long long int val = strtoll(p, &endptr, 10);
2800 if (endptr && endptr != p && *endptr == 0) {
2801 sig = RTLIL::SigSpec(val, lhs.width_);
2802 cover("kernel.rtlil.sigspec.parse.rhs_dec");
2803 return true;
2804 }
2805 }
2806
2807 return parse(sig, module, str);
2808 }
2809
2810 RTLIL::CaseRule::~CaseRule()
2811 {
2812 for (auto it = switches.begin(); it != switches.end(); it++)
2813 delete *it;
2814 }
2815
2816 RTLIL::CaseRule *RTLIL::CaseRule::clone() const
2817 {
2818 RTLIL::CaseRule *new_caserule = new RTLIL::CaseRule;
2819 new_caserule->compare = compare;
2820 new_caserule->actions = actions;
2821 for (auto &it : switches)
2822 new_caserule->switches.push_back(it->clone());
2823 return new_caserule;
2824 }
2825
2826 RTLIL::SwitchRule::~SwitchRule()
2827 {
2828 for (auto it = cases.begin(); it != cases.end(); it++)
2829 delete *it;
2830 }
2831
2832 RTLIL::SwitchRule *RTLIL::SwitchRule::clone() const
2833 {
2834 RTLIL::SwitchRule *new_switchrule = new RTLIL::SwitchRule;
2835 new_switchrule->signal = signal;
2836 new_switchrule->attributes = attributes;
2837 for (auto &it : cases)
2838 new_switchrule->cases.push_back(it->clone());
2839 return new_switchrule;
2840
2841 }
2842
2843 RTLIL::SyncRule *RTLIL::SyncRule::clone() const
2844 {
2845 RTLIL::SyncRule *new_syncrule = new RTLIL::SyncRule;
2846 new_syncrule->type = type;
2847 new_syncrule->signal = signal;
2848 new_syncrule->actions = actions;
2849 return new_syncrule;
2850 }
2851
2852 RTLIL::Process::~Process()
2853 {
2854 for (auto it = syncs.begin(); it != syncs.end(); it++)
2855 delete *it;
2856 }
2857
2858 RTLIL::Process *RTLIL::Process::clone() const
2859 {
2860 RTLIL::Process *new_proc = new RTLIL::Process;
2861
2862 new_proc->name = name;
2863 new_proc->attributes = attributes;
2864
2865 RTLIL::CaseRule *rc_ptr = root_case.clone();
2866 new_proc->root_case = *rc_ptr;
2867 rc_ptr->switches.clear();
2868 delete rc_ptr;
2869
2870 for (auto &it : syncs)
2871 new_proc->syncs.push_back(it->clone());
2872
2873 return new_proc;
2874 }
2875
2876 YOSYS_NAMESPACE_END
2877