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Improve determinism of IdString DB for similar scripts
[yosys.git] / kernel / rtlil.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 #include "kernel/yosys.h"
21 #include "kernel/macc.h"
22 #include "kernel/celltypes.h"
23 #include "frontends/verilog/verilog_frontend.h"
24 #include "backends/ilang/ilang_backend.h"
25
26 #include <string.h>
27 #include <algorithm>
28
29 YOSYS_NAMESPACE_BEGIN
30
31 RTLIL::IdString::destruct_guard_t RTLIL::IdString::destruct_guard;
32 std::vector<int> RTLIL::IdString::global_refcount_storage_;
33 std::vector<char*> RTLIL::IdString::global_id_storage_;
34 dict<char*, int, hash_cstr_ops> RTLIL::IdString::global_id_index_;
35 std::vector<int> RTLIL::IdString::global_free_idx_list_;
36 int RTLIL::IdString::last_created_idx_[8];
37 int RTLIL::IdString::last_created_idx_ptr_;
38
39 RTLIL::Const::Const()
40 {
41 flags = RTLIL::CONST_FLAG_NONE;
42 }
43
44 RTLIL::Const::Const(std::string str)
45 {
46 flags = RTLIL::CONST_FLAG_STRING;
47 for (int i = str.size()-1; i >= 0; i--) {
48 unsigned char ch = str[i];
49 for (int j = 0; j < 8; j++) {
50 bits.push_back((ch & 1) != 0 ? RTLIL::S1 : RTLIL::S0);
51 ch = ch >> 1;
52 }
53 }
54 }
55
56 RTLIL::Const::Const(int val, int width)
57 {
58 flags = RTLIL::CONST_FLAG_NONE;
59 for (int i = 0; i < width; i++) {
60 bits.push_back((val & 1) != 0 ? RTLIL::S1 : RTLIL::S0);
61 val = val >> 1;
62 }
63 }
64
65 RTLIL::Const::Const(RTLIL::State bit, int width)
66 {
67 flags = RTLIL::CONST_FLAG_NONE;
68 for (int i = 0; i < width; i++)
69 bits.push_back(bit);
70 }
71
72 RTLIL::Const::Const(const std::vector<bool> &bits)
73 {
74 flags = RTLIL::CONST_FLAG_NONE;
75 for (auto b : bits)
76 this->bits.push_back(b ? RTLIL::S1 : RTLIL::S0);
77 }
78
79 bool RTLIL::Const::operator <(const RTLIL::Const &other) const
80 {
81 if (bits.size() != other.bits.size())
82 return bits.size() < other.bits.size();
83 for (size_t i = 0; i < bits.size(); i++)
84 if (bits[i] != other.bits[i])
85 return bits[i] < other.bits[i];
86 return false;
87 }
88
89 bool RTLIL::Const::operator ==(const RTLIL::Const &other) const
90 {
91 return bits == other.bits;
92 }
93
94 bool RTLIL::Const::operator !=(const RTLIL::Const &other) const
95 {
96 return bits != other.bits;
97 }
98
99 bool RTLIL::Const::as_bool() const
100 {
101 for (size_t i = 0; i < bits.size(); i++)
102 if (bits[i] == RTLIL::S1)
103 return true;
104 return false;
105 }
106
107 int RTLIL::Const::as_int(bool is_signed) const
108 {
109 int32_t ret = 0;
110 for (size_t i = 0; i < bits.size() && i < 32; i++)
111 if (bits[i] == RTLIL::S1)
112 ret |= 1 << i;
113 if (is_signed && bits.back() == RTLIL::S1)
114 for (size_t i = bits.size(); i < 32; i++)
115 ret |= 1 << i;
116 return ret;
117 }
118
119 std::string RTLIL::Const::as_string() const
120 {
121 std::string ret;
122 for (size_t i = bits.size(); i > 0; i--)
123 switch (bits[i-1]) {
124 case S0: ret += "0"; break;
125 case S1: ret += "1"; break;
126 case Sx: ret += "x"; break;
127 case Sz: ret += "z"; break;
128 case Sa: ret += "-"; break;
129 case Sm: ret += "m"; break;
130 }
131 return ret;
132 }
133
134 RTLIL::Const RTLIL::Const::from_string(std::string str)
135 {
136 Const c;
137 for (auto it = str.rbegin(); it != str.rend(); it++)
138 switch (*it) {
139 case '0': c.bits.push_back(State::S0); break;
140 case '1': c.bits.push_back(State::S1); break;
141 case 'x': c.bits.push_back(State::Sx); break;
142 case 'z': c.bits.push_back(State::Sz); break;
143 case 'm': c.bits.push_back(State::Sm); break;
144 default: c.bits.push_back(State::Sa);
145 }
146 return c;
147 }
148
149 std::string RTLIL::Const::decode_string() const
150 {
151 std::string string;
152 std::vector<char> string_chars;
153 for (int i = 0; i < int (bits.size()); i += 8) {
154 char ch = 0;
155 for (int j = 0; j < 8 && i + j < int (bits.size()); j++)
156 if (bits[i + j] == RTLIL::State::S1)
157 ch |= 1 << j;
158 if (ch != 0)
159 string_chars.push_back(ch);
160 }
161 for (int i = int (string_chars.size()) - 1; i >= 0; i--)
162 string += string_chars[i];
163 return string;
164 }
165
166 bool RTLIL::Const::is_fully_zero() const
167 {
168 cover("kernel.rtlil.const.is_fully_zero");
169
170 for (auto bit : bits)
171 if (bit != RTLIL::State::S0)
172 return false;
173
174 return true;
175 }
176
177 bool RTLIL::Const::is_fully_ones() const
178 {
179 cover("kernel.rtlil.const.is_fully_ones");
180
181 for (auto bit : bits)
182 if (bit != RTLIL::State::S1)
183 return false;
184
185 return true;
186 }
187
188 bool RTLIL::Const::is_fully_def() const
189 {
190 cover("kernel.rtlil.const.is_fully_def");
191
192 for (auto bit : bits)
193 if (bit != RTLIL::State::S0 && bit != RTLIL::State::S1)
194 return false;
195
196 return true;
197 }
198
199 bool RTLIL::Const::is_fully_undef() const
200 {
201 cover("kernel.rtlil.const.is_fully_undef");
202
203 for (auto bit : bits)
204 if (bit != RTLIL::State::Sx && bit != RTLIL::State::Sz)
205 return false;
206
207 return true;
208 }
209
210 void RTLIL::AttrObject::set_bool_attribute(RTLIL::IdString id)
211 {
212 attributes[id] = RTLIL::Const(1);
213 }
214
215 bool RTLIL::AttrObject::get_bool_attribute(RTLIL::IdString id) const
216 {
217 if (attributes.count(id) == 0)
218 return false;
219 return attributes.at(id).as_bool();
220 }
221
222 void RTLIL::AttrObject::set_strpool_attribute(RTLIL::IdString id, const pool<string> &data)
223 {
224 string attrval;
225 for (auto &s : data) {
226 if (!attrval.empty())
227 attrval += "|";
228 attrval += s;
229 }
230 attributes[id] = RTLIL::Const(attrval);
231 }
232
233 void RTLIL::AttrObject::add_strpool_attribute(RTLIL::IdString id, const pool<string> &data)
234 {
235 pool<string> union_data = get_strpool_attribute(id);
236 union_data.insert(data.begin(), data.end());
237 if (!union_data.empty())
238 set_strpool_attribute(id, union_data);
239 }
240
241 pool<string> RTLIL::AttrObject::get_strpool_attribute(RTLIL::IdString id) const
242 {
243 pool<string> data;
244 if (attributes.count(id) != 0)
245 for (auto s : split_tokens(attributes.at(id).decode_string(), "|"))
246 data.insert(s);
247 return data;
248 }
249
250 void RTLIL::AttrObject::set_src_attribute(const std::string &src)
251 {
252 if (src.empty())
253 attributes.erase("\\src");
254 else
255 attributes["\\src"] = src;
256 }
257
258 std::string RTLIL::AttrObject::get_src_attribute() const
259 {
260 std::string src;
261 if (attributes.count("\\src"))
262 src = attributes.at("\\src").decode_string();
263 return src;
264 }
265
266 bool RTLIL::Selection::selected_module(RTLIL::IdString mod_name) const
267 {
268 if (full_selection)
269 return true;
270 if (selected_modules.count(mod_name) > 0)
271 return true;
272 if (selected_members.count(mod_name) > 0)
273 return true;
274 return false;
275 }
276
277 bool RTLIL::Selection::selected_whole_module(RTLIL::IdString mod_name) const
278 {
279 if (full_selection)
280 return true;
281 if (selected_modules.count(mod_name) > 0)
282 return true;
283 return false;
284 }
285
286 bool RTLIL::Selection::selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const
287 {
288 if (full_selection)
289 return true;
290 if (selected_modules.count(mod_name) > 0)
291 return true;
292 if (selected_members.count(mod_name) > 0)
293 if (selected_members.at(mod_name).count(memb_name) > 0)
294 return true;
295 return false;
296 }
297
298 void RTLIL::Selection::optimize(RTLIL::Design *design)
299 {
300 if (full_selection) {
301 selected_modules.clear();
302 selected_members.clear();
303 return;
304 }
305
306 std::vector<RTLIL::IdString> del_list, add_list;
307
308 del_list.clear();
309 for (auto mod_name : selected_modules) {
310 if (design->modules_.count(mod_name) == 0)
311 del_list.push_back(mod_name);
312 selected_members.erase(mod_name);
313 }
314 for (auto mod_name : del_list)
315 selected_modules.erase(mod_name);
316
317 del_list.clear();
318 for (auto &it : selected_members)
319 if (design->modules_.count(it.first) == 0)
320 del_list.push_back(it.first);
321 for (auto mod_name : del_list)
322 selected_members.erase(mod_name);
323
324 for (auto &it : selected_members) {
325 del_list.clear();
326 for (auto memb_name : it.second)
327 if (design->modules_[it.first]->count_id(memb_name) == 0)
328 del_list.push_back(memb_name);
329 for (auto memb_name : del_list)
330 it.second.erase(memb_name);
331 }
332
333 del_list.clear();
334 add_list.clear();
335 for (auto &it : selected_members)
336 if (it.second.size() == 0)
337 del_list.push_back(it.first);
338 else if (it.second.size() == design->modules_[it.first]->wires_.size() + design->modules_[it.first]->memories.size() +
339 design->modules_[it.first]->cells_.size() + design->modules_[it.first]->processes.size())
340 add_list.push_back(it.first);
341 for (auto mod_name : del_list)
342 selected_members.erase(mod_name);
343 for (auto mod_name : add_list) {
344 selected_members.erase(mod_name);
345 selected_modules.insert(mod_name);
346 }
347
348 if (selected_modules.size() == design->modules_.size()) {
349 full_selection = true;
350 selected_modules.clear();
351 selected_members.clear();
352 }
353 }
354
355 RTLIL::Design::Design()
356 {
357 static unsigned int hashidx_count = 123456789;
358 hashidx_count = mkhash_xorshift(hashidx_count);
359 hashidx_ = hashidx_count;
360
361 refcount_modules_ = 0;
362 selection_stack.push_back(RTLIL::Selection());
363 }
364
365 RTLIL::Design::~Design()
366 {
367 for (auto it = modules_.begin(); it != modules_.end(); ++it)
368 delete it->second;
369 for (auto n : verilog_packages)
370 delete n;
371 for (auto n : verilog_globals)
372 delete n;
373 }
374
375 RTLIL::ObjRange<RTLIL::Module*> RTLIL::Design::modules()
376 {
377 return RTLIL::ObjRange<RTLIL::Module*>(&modules_, &refcount_modules_);
378 }
379
380 RTLIL::Module *RTLIL::Design::module(RTLIL::IdString name)
381 {
382 return modules_.count(name) ? modules_.at(name) : NULL;
383 }
384
385 RTLIL::Module *RTLIL::Design::top_module()
386 {
387 RTLIL::Module *module = nullptr;
388 int module_count = 0;
389
390 for (auto mod : selected_modules()) {
391 if (mod->get_bool_attribute("\\top"))
392 return mod;
393 module_count++;
394 module = mod;
395 }
396
397 return module_count == 1 ? module : nullptr;
398 }
399
400 void RTLIL::Design::add(RTLIL::Module *module)
401 {
402 log_assert(modules_.count(module->name) == 0);
403 log_assert(refcount_modules_ == 0);
404 modules_[module->name] = module;
405 module->design = this;
406
407 for (auto mon : monitors)
408 mon->notify_module_add(module);
409
410 if (yosys_xtrace) {
411 log("#X# New Module: %s\n", log_id(module));
412 log_backtrace("-X- ", yosys_xtrace-1);
413 }
414 }
415
416 RTLIL::Module *RTLIL::Design::addModule(RTLIL::IdString name)
417 {
418 log_assert(modules_.count(name) == 0);
419 log_assert(refcount_modules_ == 0);
420
421 RTLIL::Module *module = new RTLIL::Module;
422 modules_[name] = module;
423 module->design = this;
424 module->name = name;
425
426 for (auto mon : monitors)
427 mon->notify_module_add(module);
428
429 if (yosys_xtrace) {
430 log("#X# New Module: %s\n", log_id(module));
431 log_backtrace("-X- ", yosys_xtrace-1);
432 }
433
434 return module;
435 }
436
437 void RTLIL::Design::scratchpad_unset(std::string varname)
438 {
439 scratchpad.erase(varname);
440 }
441
442 void RTLIL::Design::scratchpad_set_int(std::string varname, int value)
443 {
444 scratchpad[varname] = stringf("%d", value);
445 }
446
447 void RTLIL::Design::scratchpad_set_bool(std::string varname, bool value)
448 {
449 scratchpad[varname] = value ? "true" : "false";
450 }
451
452 void RTLIL::Design::scratchpad_set_string(std::string varname, std::string value)
453 {
454 scratchpad[varname] = value;
455 }
456
457 int RTLIL::Design::scratchpad_get_int(std::string varname, int default_value) const
458 {
459 if (scratchpad.count(varname) == 0)
460 return default_value;
461
462 std::string str = scratchpad.at(varname);
463
464 if (str == "0" || str == "false")
465 return 0;
466
467 if (str == "1" || str == "true")
468 return 1;
469
470 char *endptr = nullptr;
471 long int parsed_value = strtol(str.c_str(), &endptr, 10);
472 return *endptr ? default_value : parsed_value;
473 }
474
475 bool RTLIL::Design::scratchpad_get_bool(std::string varname, bool default_value) const
476 {
477 if (scratchpad.count(varname) == 0)
478 return default_value;
479
480 std::string str = scratchpad.at(varname);
481
482 if (str == "0" || str == "false")
483 return false;
484
485 if (str == "1" || str == "true")
486 return true;
487
488 return default_value;
489 }
490
491 std::string RTLIL::Design::scratchpad_get_string(std::string varname, std::string default_value) const
492 {
493 if (scratchpad.count(varname) == 0)
494 return default_value;
495 return scratchpad.at(varname);
496 }
497
498 void RTLIL::Design::remove(RTLIL::Module *module)
499 {
500 for (auto mon : monitors)
501 mon->notify_module_del(module);
502
503 if (yosys_xtrace) {
504 log("#X# Remove Module: %s\n", log_id(module));
505 log_backtrace("-X- ", yosys_xtrace-1);
506 }
507
508 log_assert(modules_.at(module->name) == module);
509 modules_.erase(module->name);
510 delete module;
511 }
512
513 void RTLIL::Design::rename(RTLIL::Module *module, RTLIL::IdString new_name)
514 {
515 modules_.erase(module->name);
516 module->name = new_name;
517 add(module);
518 }
519
520 void RTLIL::Design::sort()
521 {
522 scratchpad.sort();
523 modules_.sort(sort_by_id_str());
524 for (auto &it : modules_)
525 it.second->sort();
526 }
527
528 void RTLIL::Design::check()
529 {
530 #ifndef NDEBUG
531 for (auto &it : modules_) {
532 log_assert(this == it.second->design);
533 log_assert(it.first == it.second->name);
534 log_assert(!it.first.empty());
535 it.second->check();
536 }
537 #endif
538 }
539
540 void RTLIL::Design::optimize()
541 {
542 for (auto &it : modules_)
543 it.second->optimize();
544 for (auto &it : selection_stack)
545 it.optimize(this);
546 for (auto &it : selection_vars)
547 it.second.optimize(this);
548 }
549
550 bool RTLIL::Design::selected_module(RTLIL::IdString mod_name) const
551 {
552 if (!selected_active_module.empty() && mod_name != selected_active_module)
553 return false;
554 if (selection_stack.size() == 0)
555 return true;
556 return selection_stack.back().selected_module(mod_name);
557 }
558
559 bool RTLIL::Design::selected_whole_module(RTLIL::IdString mod_name) const
560 {
561 if (!selected_active_module.empty() && mod_name != selected_active_module)
562 return false;
563 if (selection_stack.size() == 0)
564 return true;
565 return selection_stack.back().selected_whole_module(mod_name);
566 }
567
568 bool RTLIL::Design::selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const
569 {
570 if (!selected_active_module.empty() && mod_name != selected_active_module)
571 return false;
572 if (selection_stack.size() == 0)
573 return true;
574 return selection_stack.back().selected_member(mod_name, memb_name);
575 }
576
577 bool RTLIL::Design::selected_module(RTLIL::Module *mod) const
578 {
579 return selected_module(mod->name);
580 }
581
582 bool RTLIL::Design::selected_whole_module(RTLIL::Module *mod) const
583 {
584 return selected_whole_module(mod->name);
585 }
586
587 std::vector<RTLIL::Module*> RTLIL::Design::selected_modules() const
588 {
589 std::vector<RTLIL::Module*> result;
590 result.reserve(modules_.size());
591 for (auto &it : modules_)
592 if (selected_module(it.first) && !it.second->get_bool_attribute("\\blackbox"))
593 result.push_back(it.second);
594 return result;
595 }
596
597 std::vector<RTLIL::Module*> RTLIL::Design::selected_whole_modules() const
598 {
599 std::vector<RTLIL::Module*> result;
600 result.reserve(modules_.size());
601 for (auto &it : modules_)
602 if (selected_whole_module(it.first) && !it.second->get_bool_attribute("\\blackbox"))
603 result.push_back(it.second);
604 return result;
605 }
606
607 std::vector<RTLIL::Module*> RTLIL::Design::selected_whole_modules_warn() const
608 {
609 std::vector<RTLIL::Module*> result;
610 result.reserve(modules_.size());
611 for (auto &it : modules_)
612 if (it.second->get_bool_attribute("\\blackbox"))
613 continue;
614 else if (selected_whole_module(it.first))
615 result.push_back(it.second);
616 else if (selected_module(it.first))
617 log_warning("Ignoring partially selected module %s.\n", log_id(it.first));
618 return result;
619 }
620
621 RTLIL::Module::Module()
622 {
623 static unsigned int hashidx_count = 123456789;
624 hashidx_count = mkhash_xorshift(hashidx_count);
625 hashidx_ = hashidx_count;
626
627 design = nullptr;
628 refcount_wires_ = 0;
629 refcount_cells_ = 0;
630 }
631
632 RTLIL::Module::~Module()
633 {
634 for (auto it = wires_.begin(); it != wires_.end(); ++it)
635 delete it->second;
636 for (auto it = memories.begin(); it != memories.end(); ++it)
637 delete it->second;
638 for (auto it = cells_.begin(); it != cells_.end(); ++it)
639 delete it->second;
640 for (auto it = processes.begin(); it != processes.end(); ++it)
641 delete it->second;
642 }
643
644 void RTLIL::Module::reprocess_module(RTLIL::Design *, dict<RTLIL::IdString, RTLIL::Module *>)
645 {
646 log_error("Cannot reprocess_module module `%s' !\n", id2cstr(name));
647 }
648
649 RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, dict<RTLIL::IdString, RTLIL::Const>, bool mayfail)
650 {
651 if (mayfail)
652 return RTLIL::IdString();
653 log_error("Module `%s' is used with parameters but is not parametric!\n", id2cstr(name));
654 }
655
656
657 RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, dict<RTLIL::IdString, RTLIL::Const>, dict<RTLIL::IdString, RTLIL::Module*>, dict<RTLIL::IdString, RTLIL::IdString>, bool mayfail)
658 {
659 if (mayfail)
660 return RTLIL::IdString();
661 log_error("Module `%s' is used with parameters but is not parametric!\n", id2cstr(name));
662 }
663
664 size_t RTLIL::Module::count_id(RTLIL::IdString id)
665 {
666 return wires_.count(id) + memories.count(id) + cells_.count(id) + processes.count(id);
667 }
668
669 #ifndef NDEBUG
670 namespace {
671 struct InternalCellChecker
672 {
673 RTLIL::Module *module;
674 RTLIL::Cell *cell;
675 pool<RTLIL::IdString> expected_params, expected_ports;
676
677 InternalCellChecker(RTLIL::Module *module, RTLIL::Cell *cell) : module(module), cell(cell) { }
678
679 void error(int linenr)
680 {
681 std::stringstream buf;
682 ILANG_BACKEND::dump_cell(buf, " ", cell);
683
684 log_error("Found error in internal cell %s%s%s (%s) at %s:%d:\n%s",
685 module ? module->name.c_str() : "", module ? "." : "",
686 cell->name.c_str(), cell->type.c_str(), __FILE__, linenr, buf.str().c_str());
687 }
688
689 int param(const char *name)
690 {
691 if (cell->parameters.count(name) == 0)
692 error(__LINE__);
693 expected_params.insert(name);
694 return cell->parameters.at(name).as_int();
695 }
696
697 int param_bool(const char *name)
698 {
699 int v = param(name);
700 if (cell->parameters.at(name).bits.size() > 32)
701 error(__LINE__);
702 if (v != 0 && v != 1)
703 error(__LINE__);
704 return v;
705 }
706
707 void param_bits(const char *name, int width)
708 {
709 param(name);
710 if (int(cell->parameters.at(name).bits.size()) != width)
711 error(__LINE__);
712 }
713
714 void port(const char *name, int width)
715 {
716 if (!cell->hasPort(name))
717 error(__LINE__);
718 if (cell->getPort(name).size() != width)
719 error(__LINE__);
720 expected_ports.insert(name);
721 }
722
723 void check_expected(bool check_matched_sign = true)
724 {
725 for (auto &para : cell->parameters)
726 if (expected_params.count(para.first) == 0)
727 error(__LINE__);
728 for (auto &conn : cell->connections())
729 if (expected_ports.count(conn.first) == 0)
730 error(__LINE__);
731
732 if (expected_params.count("\\A_SIGNED") != 0 && expected_params.count("\\B_SIGNED") && check_matched_sign) {
733 bool a_is_signed = param("\\A_SIGNED") != 0;
734 bool b_is_signed = param("\\B_SIGNED") != 0;
735 if (a_is_signed != b_is_signed)
736 error(__LINE__);
737 }
738 }
739
740 void check_gate(const char *ports)
741 {
742 if (cell->parameters.size() != 0)
743 error(__LINE__);
744
745 for (const char *p = ports; *p; p++) {
746 char portname[3] = { '\\', *p, 0 };
747 if (!cell->hasPort(portname))
748 error(__LINE__);
749 if (cell->getPort(portname).size() != 1)
750 error(__LINE__);
751 }
752
753 for (auto &conn : cell->connections()) {
754 if (conn.first.size() != 2 || conn.first[0] != '\\')
755 error(__LINE__);
756 if (strchr(ports, conn.first[1]) == NULL)
757 error(__LINE__);
758 }
759 }
760
761 void check()
762 {
763 if (cell->type.substr(0, 1) != "$" || cell->type.substr(0, 3) == "$__" || cell->type.substr(0, 8) == "$paramod" ||
764 cell->type.substr(0, 9) == "$verific$" || cell->type.substr(0, 7) == "$array:" || cell->type.substr(0, 8) == "$extern:")
765 return;
766
767 if (cell->type.in("$not", "$pos", "$neg")) {
768 param_bool("\\A_SIGNED");
769 port("\\A", param("\\A_WIDTH"));
770 port("\\Y", param("\\Y_WIDTH"));
771 check_expected();
772 return;
773 }
774
775 if (cell->type.in("$and", "$or", "$xor", "$xnor")) {
776 param_bool("\\A_SIGNED");
777 param_bool("\\B_SIGNED");
778 port("\\A", param("\\A_WIDTH"));
779 port("\\B", param("\\B_WIDTH"));
780 port("\\Y", param("\\Y_WIDTH"));
781 check_expected();
782 return;
783 }
784
785 if (cell->type.in("$reduce_and", "$reduce_or", "$reduce_xor", "$reduce_xnor", "$reduce_bool")) {
786 param_bool("\\A_SIGNED");
787 port("\\A", param("\\A_WIDTH"));
788 port("\\Y", param("\\Y_WIDTH"));
789 check_expected();
790 return;
791 }
792
793 if (cell->type.in("$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx")) {
794 param_bool("\\A_SIGNED");
795 param_bool("\\B_SIGNED");
796 port("\\A", param("\\A_WIDTH"));
797 port("\\B", param("\\B_WIDTH"));
798 port("\\Y", param("\\Y_WIDTH"));
799 check_expected(false);
800 return;
801 }
802
803 if (cell->type.in("$lt", "$le", "$eq", "$ne", "$eqx", "$nex", "$ge", "$gt")) {
804 param_bool("\\A_SIGNED");
805 param_bool("\\B_SIGNED");
806 port("\\A", param("\\A_WIDTH"));
807 port("\\B", param("\\B_WIDTH"));
808 port("\\Y", param("\\Y_WIDTH"));
809 check_expected();
810 return;
811 }
812
813 if (cell->type.in("$add", "$sub", "$mul", "$div", "$mod", "$pow")) {
814 param_bool("\\A_SIGNED");
815 param_bool("\\B_SIGNED");
816 port("\\A", param("\\A_WIDTH"));
817 port("\\B", param("\\B_WIDTH"));
818 port("\\Y", param("\\Y_WIDTH"));
819 check_expected(cell->type != "$pow");
820 return;
821 }
822
823 if (cell->type == "$fa") {
824 port("\\A", param("\\WIDTH"));
825 port("\\B", param("\\WIDTH"));
826 port("\\C", param("\\WIDTH"));
827 port("\\X", param("\\WIDTH"));
828 port("\\Y", param("\\WIDTH"));
829 check_expected();
830 return;
831 }
832
833 if (cell->type == "$lcu") {
834 port("\\P", param("\\WIDTH"));
835 port("\\G", param("\\WIDTH"));
836 port("\\CI", 1);
837 port("\\CO", param("\\WIDTH"));
838 check_expected();
839 return;
840 }
841
842 if (cell->type == "$alu") {
843 param_bool("\\A_SIGNED");
844 param_bool("\\B_SIGNED");
845 port("\\A", param("\\A_WIDTH"));
846 port("\\B", param("\\B_WIDTH"));
847 port("\\CI", 1);
848 port("\\BI", 1);
849 port("\\X", param("\\Y_WIDTH"));
850 port("\\Y", param("\\Y_WIDTH"));
851 port("\\CO", param("\\Y_WIDTH"));
852 check_expected();
853 return;
854 }
855
856 if (cell->type == "$macc") {
857 param("\\CONFIG");
858 param("\\CONFIG_WIDTH");
859 port("\\A", param("\\A_WIDTH"));
860 port("\\B", param("\\B_WIDTH"));
861 port("\\Y", param("\\Y_WIDTH"));
862 check_expected();
863 Macc().from_cell(cell);
864 return;
865 }
866
867 if (cell->type == "$logic_not") {
868 param_bool("\\A_SIGNED");
869 port("\\A", param("\\A_WIDTH"));
870 port("\\Y", param("\\Y_WIDTH"));
871 check_expected();
872 return;
873 }
874
875 if (cell->type == "$logic_and" || cell->type == "$logic_or") {
876 param_bool("\\A_SIGNED");
877 param_bool("\\B_SIGNED");
878 port("\\A", param("\\A_WIDTH"));
879 port("\\B", param("\\B_WIDTH"));
880 port("\\Y", param("\\Y_WIDTH"));
881 check_expected(false);
882 return;
883 }
884
885 if (cell->type == "$slice") {
886 param("\\OFFSET");
887 port("\\A", param("\\A_WIDTH"));
888 port("\\Y", param("\\Y_WIDTH"));
889 if (param("\\OFFSET") + param("\\Y_WIDTH") > param("\\A_WIDTH"))
890 error(__LINE__);
891 check_expected();
892 return;
893 }
894
895 if (cell->type == "$concat") {
896 port("\\A", param("\\A_WIDTH"));
897 port("\\B", param("\\B_WIDTH"));
898 port("\\Y", param("\\A_WIDTH") + param("\\B_WIDTH"));
899 check_expected();
900 return;
901 }
902
903 if (cell->type == "$mux") {
904 port("\\A", param("\\WIDTH"));
905 port("\\B", param("\\WIDTH"));
906 port("\\S", 1);
907 port("\\Y", param("\\WIDTH"));
908 check_expected();
909 return;
910 }
911
912 if (cell->type == "$pmux") {
913 port("\\A", param("\\WIDTH"));
914 port("\\B", param("\\WIDTH") * param("\\S_WIDTH"));
915 port("\\S", param("\\S_WIDTH"));
916 port("\\Y", param("\\WIDTH"));
917 check_expected();
918 return;
919 }
920
921 if (cell->type == "$lut") {
922 param("\\LUT");
923 port("\\A", param("\\WIDTH"));
924 port("\\Y", 1);
925 check_expected();
926 return;
927 }
928
929 if (cell->type == "$sop") {
930 param("\\DEPTH");
931 param("\\TABLE");
932 port("\\A", param("\\WIDTH"));
933 port("\\Y", 1);
934 check_expected();
935 return;
936 }
937
938 if (cell->type == "$sr") {
939 param_bool("\\SET_POLARITY");
940 param_bool("\\CLR_POLARITY");
941 port("\\SET", param("\\WIDTH"));
942 port("\\CLR", param("\\WIDTH"));
943 port("\\Q", param("\\WIDTH"));
944 check_expected();
945 return;
946 }
947
948 if (cell->type == "$ff") {
949 port("\\D", param("\\WIDTH"));
950 port("\\Q", param("\\WIDTH"));
951 check_expected();
952 return;
953 }
954
955 if (cell->type == "$dff") {
956 param_bool("\\CLK_POLARITY");
957 port("\\CLK", 1);
958 port("\\D", param("\\WIDTH"));
959 port("\\Q", param("\\WIDTH"));
960 check_expected();
961 return;
962 }
963
964 if (cell->type == "$dffe") {
965 param_bool("\\CLK_POLARITY");
966 param_bool("\\EN_POLARITY");
967 port("\\CLK", 1);
968 port("\\EN", 1);
969 port("\\D", param("\\WIDTH"));
970 port("\\Q", param("\\WIDTH"));
971 check_expected();
972 return;
973 }
974
975 if (cell->type == "$dffsr") {
976 param_bool("\\CLK_POLARITY");
977 param_bool("\\SET_POLARITY");
978 param_bool("\\CLR_POLARITY");
979 port("\\CLK", 1);
980 port("\\SET", param("\\WIDTH"));
981 port("\\CLR", param("\\WIDTH"));
982 port("\\D", param("\\WIDTH"));
983 port("\\Q", param("\\WIDTH"));
984 check_expected();
985 return;
986 }
987
988 if (cell->type == "$adff") {
989 param_bool("\\CLK_POLARITY");
990 param_bool("\\ARST_POLARITY");
991 param_bits("\\ARST_VALUE", param("\\WIDTH"));
992 port("\\CLK", 1);
993 port("\\ARST", 1);
994 port("\\D", param("\\WIDTH"));
995 port("\\Q", param("\\WIDTH"));
996 check_expected();
997 return;
998 }
999
1000 if (cell->type == "$dlatch") {
1001 param_bool("\\EN_POLARITY");
1002 port("\\EN", 1);
1003 port("\\D", param("\\WIDTH"));
1004 port("\\Q", param("\\WIDTH"));
1005 check_expected();
1006 return;
1007 }
1008
1009 if (cell->type == "$dlatchsr") {
1010 param_bool("\\EN_POLARITY");
1011 param_bool("\\SET_POLARITY");
1012 param_bool("\\CLR_POLARITY");
1013 port("\\EN", 1);
1014 port("\\SET", param("\\WIDTH"));
1015 port("\\CLR", param("\\WIDTH"));
1016 port("\\D", param("\\WIDTH"));
1017 port("\\Q", param("\\WIDTH"));
1018 check_expected();
1019 return;
1020 }
1021
1022 if (cell->type == "$fsm") {
1023 param("\\NAME");
1024 param_bool("\\CLK_POLARITY");
1025 param_bool("\\ARST_POLARITY");
1026 param("\\STATE_BITS");
1027 param("\\STATE_NUM");
1028 param("\\STATE_NUM_LOG2");
1029 param("\\STATE_RST");
1030 param_bits("\\STATE_TABLE", param("\\STATE_BITS") * param("\\STATE_NUM"));
1031 param("\\TRANS_NUM");
1032 param_bits("\\TRANS_TABLE", param("\\TRANS_NUM") * (2*param("\\STATE_NUM_LOG2") + param("\\CTRL_IN_WIDTH") + param("\\CTRL_OUT_WIDTH")));
1033 port("\\CLK", 1);
1034 port("\\ARST", 1);
1035 port("\\CTRL_IN", param("\\CTRL_IN_WIDTH"));
1036 port("\\CTRL_OUT", param("\\CTRL_OUT_WIDTH"));
1037 check_expected();
1038 return;
1039 }
1040
1041 if (cell->type == "$memrd") {
1042 param("\\MEMID");
1043 param_bool("\\CLK_ENABLE");
1044 param_bool("\\CLK_POLARITY");
1045 param_bool("\\TRANSPARENT");
1046 port("\\CLK", 1);
1047 port("\\EN", 1);
1048 port("\\ADDR", param("\\ABITS"));
1049 port("\\DATA", param("\\WIDTH"));
1050 check_expected();
1051 return;
1052 }
1053
1054 if (cell->type == "$memwr") {
1055 param("\\MEMID");
1056 param_bool("\\CLK_ENABLE");
1057 param_bool("\\CLK_POLARITY");
1058 param("\\PRIORITY");
1059 port("\\CLK", 1);
1060 port("\\EN", param("\\WIDTH"));
1061 port("\\ADDR", param("\\ABITS"));
1062 port("\\DATA", param("\\WIDTH"));
1063 check_expected();
1064 return;
1065 }
1066
1067 if (cell->type == "$meminit") {
1068 param("\\MEMID");
1069 param("\\PRIORITY");
1070 port("\\ADDR", param("\\ABITS"));
1071 port("\\DATA", param("\\WIDTH") * param("\\WORDS"));
1072 check_expected();
1073 return;
1074 }
1075
1076 if (cell->type == "$mem") {
1077 param("\\MEMID");
1078 param("\\SIZE");
1079 param("\\OFFSET");
1080 param("\\INIT");
1081 param_bits("\\RD_CLK_ENABLE", max(1, param("\\RD_PORTS")));
1082 param_bits("\\RD_CLK_POLARITY", max(1, param("\\RD_PORTS")));
1083 param_bits("\\RD_TRANSPARENT", max(1, param("\\RD_PORTS")));
1084 param_bits("\\WR_CLK_ENABLE", max(1, param("\\WR_PORTS")));
1085 param_bits("\\WR_CLK_POLARITY", max(1, param("\\WR_PORTS")));
1086 port("\\RD_CLK", param("\\RD_PORTS"));
1087 port("\\RD_EN", param("\\RD_PORTS"));
1088 port("\\RD_ADDR", param("\\RD_PORTS") * param("\\ABITS"));
1089 port("\\RD_DATA", param("\\RD_PORTS") * param("\\WIDTH"));
1090 port("\\WR_CLK", param("\\WR_PORTS"));
1091 port("\\WR_EN", param("\\WR_PORTS") * param("\\WIDTH"));
1092 port("\\WR_ADDR", param("\\WR_PORTS") * param("\\ABITS"));
1093 port("\\WR_DATA", param("\\WR_PORTS") * param("\\WIDTH"));
1094 check_expected();
1095 return;
1096 }
1097
1098 if (cell->type == "$tribuf") {
1099 port("\\A", param("\\WIDTH"));
1100 port("\\Y", param("\\WIDTH"));
1101 port("\\EN", 1);
1102 check_expected();
1103 return;
1104 }
1105
1106 if (cell->type.in("$assert", "$assume", "$live", "$fair", "$cover")) {
1107 port("\\A", 1);
1108 port("\\EN", 1);
1109 check_expected();
1110 return;
1111 }
1112
1113 if (cell->type == "$initstate") {
1114 port("\\Y", 1);
1115 check_expected();
1116 return;
1117 }
1118
1119 if (cell->type.in("$anyconst", "$anyseq", "$allconst", "$allseq")) {
1120 port("\\Y", param("\\WIDTH"));
1121 check_expected();
1122 return;
1123 }
1124
1125 if (cell->type == "$equiv") {
1126 port("\\A", 1);
1127 port("\\B", 1);
1128 port("\\Y", 1);
1129 check_expected();
1130 return;
1131 }
1132
1133 if (cell->type == "$_BUF_") { check_gate("AY"); return; }
1134 if (cell->type == "$_NOT_") { check_gate("AY"); return; }
1135 if (cell->type == "$_AND_") { check_gate("ABY"); return; }
1136 if (cell->type == "$_NAND_") { check_gate("ABY"); return; }
1137 if (cell->type == "$_OR_") { check_gate("ABY"); return; }
1138 if (cell->type == "$_NOR_") { check_gate("ABY"); return; }
1139 if (cell->type == "$_XOR_") { check_gate("ABY"); return; }
1140 if (cell->type == "$_XNOR_") { check_gate("ABY"); return; }
1141 if (cell->type == "$_ANDNOT_") { check_gate("ABY"); return; }
1142 if (cell->type == "$_ORNOT_") { check_gate("ABY"); return; }
1143 if (cell->type == "$_MUX_") { check_gate("ABSY"); return; }
1144 if (cell->type == "$_AOI3_") { check_gate("ABCY"); return; }
1145 if (cell->type == "$_OAI3_") { check_gate("ABCY"); return; }
1146 if (cell->type == "$_AOI4_") { check_gate("ABCDY"); return; }
1147 if (cell->type == "$_OAI4_") { check_gate("ABCDY"); return; }
1148
1149 if (cell->type == "$_TBUF_") { check_gate("AYE"); return; }
1150
1151 if (cell->type == "$_MUX4_") { check_gate("ABCDSTY"); return; }
1152 if (cell->type == "$_MUX8_") { check_gate("ABCDEFGHSTUY"); return; }
1153 if (cell->type == "$_MUX16_") { check_gate("ABCDEFGHIJKLMNOPSTUVY"); return; }
1154
1155 if (cell->type == "$_SR_NN_") { check_gate("SRQ"); return; }
1156 if (cell->type == "$_SR_NP_") { check_gate("SRQ"); return; }
1157 if (cell->type == "$_SR_PN_") { check_gate("SRQ"); return; }
1158 if (cell->type == "$_SR_PP_") { check_gate("SRQ"); return; }
1159
1160 if (cell->type == "$_FF_") { check_gate("DQ"); return; }
1161 if (cell->type == "$_DFF_N_") { check_gate("DQC"); return; }
1162 if (cell->type == "$_DFF_P_") { check_gate("DQC"); return; }
1163
1164 if (cell->type == "$_DFFE_NN_") { check_gate("DQCE"); return; }
1165 if (cell->type == "$_DFFE_NP_") { check_gate("DQCE"); return; }
1166 if (cell->type == "$_DFFE_PN_") { check_gate("DQCE"); return; }
1167 if (cell->type == "$_DFFE_PP_") { check_gate("DQCE"); return; }
1168
1169 if (cell->type == "$_DFF_NN0_") { check_gate("DQCR"); return; }
1170 if (cell->type == "$_DFF_NN1_") { check_gate("DQCR"); return; }
1171 if (cell->type == "$_DFF_NP0_") { check_gate("DQCR"); return; }
1172 if (cell->type == "$_DFF_NP1_") { check_gate("DQCR"); return; }
1173 if (cell->type == "$_DFF_PN0_") { check_gate("DQCR"); return; }
1174 if (cell->type == "$_DFF_PN1_") { check_gate("DQCR"); return; }
1175 if (cell->type == "$_DFF_PP0_") { check_gate("DQCR"); return; }
1176 if (cell->type == "$_DFF_PP1_") { check_gate("DQCR"); return; }
1177
1178 if (cell->type == "$_DFFSR_NNN_") { check_gate("CSRDQ"); return; }
1179 if (cell->type == "$_DFFSR_NNP_") { check_gate("CSRDQ"); return; }
1180 if (cell->type == "$_DFFSR_NPN_") { check_gate("CSRDQ"); return; }
1181 if (cell->type == "$_DFFSR_NPP_") { check_gate("CSRDQ"); return; }
1182 if (cell->type == "$_DFFSR_PNN_") { check_gate("CSRDQ"); return; }
1183 if (cell->type == "$_DFFSR_PNP_") { check_gate("CSRDQ"); return; }
1184 if (cell->type == "$_DFFSR_PPN_") { check_gate("CSRDQ"); return; }
1185 if (cell->type == "$_DFFSR_PPP_") { check_gate("CSRDQ"); return; }
1186
1187 if (cell->type == "$_DLATCH_N_") { check_gate("EDQ"); return; }
1188 if (cell->type == "$_DLATCH_P_") { check_gate("EDQ"); return; }
1189
1190 if (cell->type == "$_DLATCHSR_NNN_") { check_gate("ESRDQ"); return; }
1191 if (cell->type == "$_DLATCHSR_NNP_") { check_gate("ESRDQ"); return; }
1192 if (cell->type == "$_DLATCHSR_NPN_") { check_gate("ESRDQ"); return; }
1193 if (cell->type == "$_DLATCHSR_NPP_") { check_gate("ESRDQ"); return; }
1194 if (cell->type == "$_DLATCHSR_PNN_") { check_gate("ESRDQ"); return; }
1195 if (cell->type == "$_DLATCHSR_PNP_") { check_gate("ESRDQ"); return; }
1196 if (cell->type == "$_DLATCHSR_PPN_") { check_gate("ESRDQ"); return; }
1197 if (cell->type == "$_DLATCHSR_PPP_") { check_gate("ESRDQ"); return; }
1198
1199 error(__LINE__);
1200 }
1201 };
1202 }
1203 #endif
1204
1205 void RTLIL::Module::sort()
1206 {
1207 wires_.sort(sort_by_id_str());
1208 cells_.sort(sort_by_id_str());
1209 avail_parameters.sort(sort_by_id_str());
1210 memories.sort(sort_by_id_str());
1211 processes.sort(sort_by_id_str());
1212 for (auto &it : cells_)
1213 it.second->sort();
1214 for (auto &it : wires_)
1215 it.second->attributes.sort(sort_by_id_str());
1216 for (auto &it : memories)
1217 it.second->attributes.sort(sort_by_id_str());
1218 }
1219
1220 void RTLIL::Module::check()
1221 {
1222 #ifndef NDEBUG
1223 std::vector<bool> ports_declared;
1224 for (auto &it : wires_) {
1225 log_assert(this == it.second->module);
1226 log_assert(it.first == it.second->name);
1227 log_assert(!it.first.empty());
1228 log_assert(it.second->width >= 0);
1229 log_assert(it.second->port_id >= 0);
1230 for (auto &it2 : it.second->attributes)
1231 log_assert(!it2.first.empty());
1232 if (it.second->port_id) {
1233 log_assert(GetSize(ports) >= it.second->port_id);
1234 log_assert(ports.at(it.second->port_id-1) == it.first);
1235 log_assert(it.second->port_input || it.second->port_output);
1236 if (GetSize(ports_declared) < it.second->port_id)
1237 ports_declared.resize(it.second->port_id);
1238 log_assert(ports_declared[it.second->port_id-1] == false);
1239 ports_declared[it.second->port_id-1] = true;
1240 } else
1241 log_assert(!it.second->port_input && !it.second->port_output);
1242 }
1243 for (auto port_declared : ports_declared)
1244 log_assert(port_declared == true);
1245 log_assert(GetSize(ports) == GetSize(ports_declared));
1246
1247 for (auto &it : memories) {
1248 log_assert(it.first == it.second->name);
1249 log_assert(!it.first.empty());
1250 log_assert(it.second->width >= 0);
1251 log_assert(it.second->size >= 0);
1252 for (auto &it2 : it.second->attributes)
1253 log_assert(!it2.first.empty());
1254 }
1255
1256 for (auto &it : cells_) {
1257 log_assert(this == it.second->module);
1258 log_assert(it.first == it.second->name);
1259 log_assert(!it.first.empty());
1260 log_assert(!it.second->type.empty());
1261 for (auto &it2 : it.second->connections()) {
1262 log_assert(!it2.first.empty());
1263 it2.second.check();
1264 }
1265 for (auto &it2 : it.second->attributes)
1266 log_assert(!it2.first.empty());
1267 for (auto &it2 : it.second->parameters)
1268 log_assert(!it2.first.empty());
1269 InternalCellChecker checker(this, it.second);
1270 checker.check();
1271 }
1272
1273 for (auto &it : processes) {
1274 log_assert(it.first == it.second->name);
1275 log_assert(!it.first.empty());
1276 // FIXME: More checks here..
1277 }
1278
1279 for (auto &it : connections_) {
1280 log_assert(it.first.size() == it.second.size());
1281 log_assert(!it.first.has_const());
1282 it.first.check();
1283 it.second.check();
1284 }
1285
1286 for (auto &it : attributes)
1287 log_assert(!it.first.empty());
1288 #endif
1289 }
1290
1291 void RTLIL::Module::optimize()
1292 {
1293 }
1294
1295 void RTLIL::Module::cloneInto(RTLIL::Module *new_mod) const
1296 {
1297 log_assert(new_mod->refcount_wires_ == 0);
1298 log_assert(new_mod->refcount_cells_ == 0);
1299
1300 new_mod->avail_parameters = avail_parameters;
1301
1302 for (auto &conn : connections_)
1303 new_mod->connect(conn);
1304
1305 for (auto &attr : attributes)
1306 new_mod->attributes[attr.first] = attr.second;
1307
1308 for (auto &it : wires_)
1309 new_mod->addWire(it.first, it.second);
1310
1311 for (auto &it : memories)
1312 new_mod->memories[it.first] = new RTLIL::Memory(*it.second);
1313
1314 for (auto &it : cells_)
1315 new_mod->addCell(it.first, it.second);
1316
1317 for (auto &it : processes)
1318 new_mod->processes[it.first] = it.second->clone();
1319
1320 struct RewriteSigSpecWorker
1321 {
1322 RTLIL::Module *mod;
1323 void operator()(RTLIL::SigSpec &sig)
1324 {
1325 std::vector<RTLIL::SigChunk> chunks = sig.chunks();
1326 for (auto &c : chunks)
1327 if (c.wire != NULL)
1328 c.wire = mod->wires_.at(c.wire->name);
1329 sig = chunks;
1330 }
1331 };
1332
1333 RewriteSigSpecWorker rewriteSigSpecWorker;
1334 rewriteSigSpecWorker.mod = new_mod;
1335 new_mod->rewrite_sigspecs(rewriteSigSpecWorker);
1336 new_mod->fixup_ports();
1337 }
1338
1339 RTLIL::Module *RTLIL::Module::clone() const
1340 {
1341 RTLIL::Module *new_mod = new RTLIL::Module;
1342 new_mod->name = name;
1343 cloneInto(new_mod);
1344 return new_mod;
1345 }
1346
1347 bool RTLIL::Module::has_memories() const
1348 {
1349 return !memories.empty();
1350 }
1351
1352 bool RTLIL::Module::has_processes() const
1353 {
1354 return !processes.empty();
1355 }
1356
1357 bool RTLIL::Module::has_memories_warn() const
1358 {
1359 if (!memories.empty())
1360 log_warning("Ignoring module %s because it contains memories (run 'memory' command first).\n", log_id(this));
1361 return !memories.empty();
1362 }
1363
1364 bool RTLIL::Module::has_processes_warn() const
1365 {
1366 if (!processes.empty())
1367 log_warning("Ignoring module %s because it contains processes (run 'proc' command first).\n", log_id(this));
1368 return !processes.empty();
1369 }
1370
1371 std::vector<RTLIL::Wire*> RTLIL::Module::selected_wires() const
1372 {
1373 std::vector<RTLIL::Wire*> result;
1374 result.reserve(wires_.size());
1375 for (auto &it : wires_)
1376 if (design->selected(this, it.second))
1377 result.push_back(it.second);
1378 return result;
1379 }
1380
1381 std::vector<RTLIL::Cell*> RTLIL::Module::selected_cells() const
1382 {
1383 std::vector<RTLIL::Cell*> result;
1384 result.reserve(wires_.size());
1385 for (auto &it : cells_)
1386 if (design->selected(this, it.second))
1387 result.push_back(it.second);
1388 return result;
1389 }
1390
1391 void RTLIL::Module::add(RTLIL::Wire *wire)
1392 {
1393 log_assert(!wire->name.empty());
1394 log_assert(count_id(wire->name) == 0);
1395 log_assert(refcount_wires_ == 0);
1396 wires_[wire->name] = wire;
1397 wire->module = this;
1398 }
1399
1400 void RTLIL::Module::add(RTLIL::Cell *cell)
1401 {
1402 log_assert(!cell->name.empty());
1403 log_assert(count_id(cell->name) == 0);
1404 log_assert(refcount_cells_ == 0);
1405 cells_[cell->name] = cell;
1406 cell->module = this;
1407 }
1408
1409 namespace {
1410 struct DeleteWireWorker
1411 {
1412 RTLIL::Module *module;
1413 const pool<RTLIL::Wire*> *wires_p;
1414
1415 void operator()(RTLIL::SigSpec &sig) {
1416 std::vector<RTLIL::SigChunk> chunks = sig;
1417 for (auto &c : chunks)
1418 if (c.wire != NULL && wires_p->count(c.wire)) {
1419 c.wire = module->addWire(NEW_ID, c.width);
1420 c.offset = 0;
1421 }
1422 sig = chunks;
1423 }
1424 };
1425 }
1426
1427 void RTLIL::Module::remove(const pool<RTLIL::Wire*> &wires)
1428 {
1429 log_assert(refcount_wires_ == 0);
1430
1431 DeleteWireWorker delete_wire_worker;
1432 delete_wire_worker.module = this;
1433 delete_wire_worker.wires_p = &wires;
1434 rewrite_sigspecs(delete_wire_worker);
1435
1436 for (auto &it : wires) {
1437 log_assert(wires_.count(it->name) != 0);
1438 wires_.erase(it->name);
1439 delete it;
1440 }
1441 }
1442
1443 void RTLIL::Module::remove(RTLIL::Cell *cell)
1444 {
1445 while (!cell->connections_.empty())
1446 cell->unsetPort(cell->connections_.begin()->first);
1447
1448 log_assert(cells_.count(cell->name) != 0);
1449 log_assert(refcount_cells_ == 0);
1450 cells_.erase(cell->name);
1451 delete cell;
1452 }
1453
1454 void RTLIL::Module::rename(RTLIL::Wire *wire, RTLIL::IdString new_name)
1455 {
1456 log_assert(wires_[wire->name] == wire);
1457 log_assert(refcount_wires_ == 0);
1458 wires_.erase(wire->name);
1459 wire->name = new_name;
1460 add(wire);
1461 }
1462
1463 void RTLIL::Module::rename(RTLIL::Cell *cell, RTLIL::IdString new_name)
1464 {
1465 log_assert(cells_[cell->name] == cell);
1466 log_assert(refcount_wires_ == 0);
1467 cells_.erase(cell->name);
1468 cell->name = new_name;
1469 add(cell);
1470 }
1471
1472 void RTLIL::Module::rename(RTLIL::IdString old_name, RTLIL::IdString new_name)
1473 {
1474 log_assert(count_id(old_name) != 0);
1475 if (wires_.count(old_name))
1476 rename(wires_.at(old_name), new_name);
1477 else if (cells_.count(old_name))
1478 rename(cells_.at(old_name), new_name);
1479 else
1480 log_abort();
1481 }
1482
1483 void RTLIL::Module::swap_names(RTLIL::Wire *w1, RTLIL::Wire *w2)
1484 {
1485 log_assert(wires_[w1->name] == w1);
1486 log_assert(wires_[w2->name] == w2);
1487 log_assert(refcount_wires_ == 0);
1488
1489 wires_.erase(w1->name);
1490 wires_.erase(w2->name);
1491
1492 std::swap(w1->name, w2->name);
1493
1494 wires_[w1->name] = w1;
1495 wires_[w2->name] = w2;
1496 }
1497
1498 void RTLIL::Module::swap_names(RTLIL::Cell *c1, RTLIL::Cell *c2)
1499 {
1500 log_assert(cells_[c1->name] == c1);
1501 log_assert(cells_[c2->name] == c2);
1502 log_assert(refcount_cells_ == 0);
1503
1504 cells_.erase(c1->name);
1505 cells_.erase(c2->name);
1506
1507 std::swap(c1->name, c2->name);
1508
1509 cells_[c1->name] = c1;
1510 cells_[c2->name] = c2;
1511 }
1512
1513 RTLIL::IdString RTLIL::Module::uniquify(RTLIL::IdString name)
1514 {
1515 int index = 0;
1516 return uniquify(name, index);
1517 }
1518
1519 RTLIL::IdString RTLIL::Module::uniquify(RTLIL::IdString name, int &index)
1520 {
1521 if (index == 0) {
1522 if (count_id(name) == 0)
1523 return name;
1524 index++;
1525 }
1526
1527 while (1) {
1528 RTLIL::IdString new_name = stringf("%s_%d", name.c_str(), index);
1529 if (count_id(new_name) == 0)
1530 return new_name;
1531 index++;
1532 }
1533 }
1534
1535 static bool fixup_ports_compare(const RTLIL::Wire *a, const RTLIL::Wire *b)
1536 {
1537 if (a->port_id && !b->port_id)
1538 return true;
1539 if (!a->port_id && b->port_id)
1540 return false;
1541
1542 if (a->port_id == b->port_id)
1543 return a->name < b->name;
1544 return a->port_id < b->port_id;
1545 }
1546
1547 void RTLIL::Module::connect(const RTLIL::SigSig &conn)
1548 {
1549 for (auto mon : monitors)
1550 mon->notify_connect(this, conn);
1551
1552 if (design)
1553 for (auto mon : design->monitors)
1554 mon->notify_connect(this, conn);
1555
1556 // ignore all attempts to assign constants to other constants
1557 if (conn.first.has_const()) {
1558 RTLIL::SigSig new_conn;
1559 for (int i = 0; i < GetSize(conn.first); i++)
1560 if (conn.first[i].wire) {
1561 new_conn.first.append(conn.first[i]);
1562 new_conn.second.append(conn.second[i]);
1563 }
1564 if (GetSize(new_conn.first))
1565 connect(new_conn);
1566 return;
1567 }
1568
1569 if (yosys_xtrace) {
1570 log("#X# Connect (SigSig) in %s: %s = %s (%d bits)\n", log_id(this), log_signal(conn.first), log_signal(conn.second), GetSize(conn.first));
1571 log_backtrace("-X- ", yosys_xtrace-1);
1572 }
1573
1574 log_assert(GetSize(conn.first) == GetSize(conn.second));
1575 connections_.push_back(conn);
1576 }
1577
1578 void RTLIL::Module::connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs)
1579 {
1580 connect(RTLIL::SigSig(lhs, rhs));
1581 }
1582
1583 void RTLIL::Module::new_connections(const std::vector<RTLIL::SigSig> &new_conn)
1584 {
1585 for (auto mon : monitors)
1586 mon->notify_connect(this, new_conn);
1587
1588 if (design)
1589 for (auto mon : design->monitors)
1590 mon->notify_connect(this, new_conn);
1591
1592 if (yosys_xtrace) {
1593 log("#X# New connections vector in %s:\n", log_id(this));
1594 for (auto &conn: new_conn)
1595 log("#X# %s = %s (%d bits)\n", log_signal(conn.first), log_signal(conn.second), GetSize(conn.first));
1596 log_backtrace("-X- ", yosys_xtrace-1);
1597 }
1598
1599 connections_ = new_conn;
1600 }
1601
1602 const std::vector<RTLIL::SigSig> &RTLIL::Module::connections() const
1603 {
1604 return connections_;
1605 }
1606
1607 void RTLIL::Module::fixup_ports()
1608 {
1609 std::vector<RTLIL::Wire*> all_ports;
1610
1611 for (auto &w : wires_)
1612 if (w.second->port_input || w.second->port_output)
1613 all_ports.push_back(w.second);
1614 else
1615 w.second->port_id = 0;
1616
1617 std::sort(all_ports.begin(), all_ports.end(), fixup_ports_compare);
1618
1619 ports.clear();
1620 for (size_t i = 0; i < all_ports.size(); i++) {
1621 ports.push_back(all_ports[i]->name);
1622 all_ports[i]->port_id = i+1;
1623 }
1624 }
1625
1626 RTLIL::Wire *RTLIL::Module::addWire(RTLIL::IdString name, int width)
1627 {
1628 RTLIL::Wire *wire = new RTLIL::Wire;
1629 wire->name = name;
1630 wire->width = width;
1631 add(wire);
1632 return wire;
1633 }
1634
1635 RTLIL::Wire *RTLIL::Module::addWire(RTLIL::IdString name, const RTLIL::Wire *other)
1636 {
1637 RTLIL::Wire *wire = addWire(name);
1638 wire->width = other->width;
1639 wire->start_offset = other->start_offset;
1640 wire->port_id = other->port_id;
1641 wire->port_input = other->port_input;
1642 wire->port_output = other->port_output;
1643 wire->upto = other->upto;
1644 wire->attributes = other->attributes;
1645 return wire;
1646 }
1647
1648 RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, RTLIL::IdString type)
1649 {
1650 RTLIL::Cell *cell = new RTLIL::Cell;
1651 cell->name = name;
1652 cell->type = type;
1653 add(cell);
1654 return cell;
1655 }
1656
1657 RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, const RTLIL::Cell *other)
1658 {
1659 RTLIL::Cell *cell = addCell(name, other->type);
1660 cell->connections_ = other->connections_;
1661 cell->parameters = other->parameters;
1662 cell->attributes = other->attributes;
1663 return cell;
1664 }
1665
1666 #define DEF_METHOD(_func, _y_size, _type) \
1667 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed, const std::string &src) { \
1668 RTLIL::Cell *cell = addCell(name, _type); \
1669 cell->parameters["\\A_SIGNED"] = is_signed; \
1670 cell->parameters["\\A_WIDTH"] = sig_a.size(); \
1671 cell->parameters["\\Y_WIDTH"] = sig_y.size(); \
1672 cell->setPort("\\A", sig_a); \
1673 cell->setPort("\\Y", sig_y); \
1674 cell->set_src_attribute(src); \
1675 return cell; \
1676 } \
1677 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed, const std::string &src) { \
1678 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
1679 add ## _func(name, sig_a, sig_y, is_signed, src); \
1680 return sig_y; \
1681 }
1682 DEF_METHOD(Not, sig_a.size(), "$not")
1683 DEF_METHOD(Pos, sig_a.size(), "$pos")
1684 DEF_METHOD(Neg, sig_a.size(), "$neg")
1685 DEF_METHOD(ReduceAnd, 1, "$reduce_and")
1686 DEF_METHOD(ReduceOr, 1, "$reduce_or")
1687 DEF_METHOD(ReduceXor, 1, "$reduce_xor")
1688 DEF_METHOD(ReduceXnor, 1, "$reduce_xnor")
1689 DEF_METHOD(ReduceBool, 1, "$reduce_bool")
1690 DEF_METHOD(LogicNot, 1, "$logic_not")
1691 #undef DEF_METHOD
1692
1693 #define DEF_METHOD(_func, _y_size, _type) \
1694 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed, const std::string &src) { \
1695 RTLIL::Cell *cell = addCell(name, _type); \
1696 cell->parameters["\\A_SIGNED"] = is_signed; \
1697 cell->parameters["\\B_SIGNED"] = is_signed; \
1698 cell->parameters["\\A_WIDTH"] = sig_a.size(); \
1699 cell->parameters["\\B_WIDTH"] = sig_b.size(); \
1700 cell->parameters["\\Y_WIDTH"] = sig_y.size(); \
1701 cell->setPort("\\A", sig_a); \
1702 cell->setPort("\\B", sig_b); \
1703 cell->setPort("\\Y", sig_y); \
1704 cell->set_src_attribute(src); \
1705 return cell; \
1706 } \
1707 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed, const std::string &src) { \
1708 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
1709 add ## _func(name, sig_a, sig_b, sig_y, is_signed, src); \
1710 return sig_y; \
1711 }
1712 DEF_METHOD(And, max(sig_a.size(), sig_b.size()), "$and")
1713 DEF_METHOD(Or, max(sig_a.size(), sig_b.size()), "$or")
1714 DEF_METHOD(Xor, max(sig_a.size(), sig_b.size()), "$xor")
1715 DEF_METHOD(Xnor, max(sig_a.size(), sig_b.size()), "$xnor")
1716 DEF_METHOD(Shl, sig_a.size(), "$shl")
1717 DEF_METHOD(Shr, sig_a.size(), "$shr")
1718 DEF_METHOD(Sshl, sig_a.size(), "$sshl")
1719 DEF_METHOD(Sshr, sig_a.size(), "$sshr")
1720 DEF_METHOD(Shift, sig_a.size(), "$shift")
1721 DEF_METHOD(Shiftx, sig_a.size(), "$shiftx")
1722 DEF_METHOD(Lt, 1, "$lt")
1723 DEF_METHOD(Le, 1, "$le")
1724 DEF_METHOD(Eq, 1, "$eq")
1725 DEF_METHOD(Ne, 1, "$ne")
1726 DEF_METHOD(Eqx, 1, "$eqx")
1727 DEF_METHOD(Nex, 1, "$nex")
1728 DEF_METHOD(Ge, 1, "$ge")
1729 DEF_METHOD(Gt, 1, "$gt")
1730 DEF_METHOD(Add, max(sig_a.size(), sig_b.size()), "$add")
1731 DEF_METHOD(Sub, max(sig_a.size(), sig_b.size()), "$sub")
1732 DEF_METHOD(Mul, max(sig_a.size(), sig_b.size()), "$mul")
1733 DEF_METHOD(Div, max(sig_a.size(), sig_b.size()), "$div")
1734 DEF_METHOD(Mod, max(sig_a.size(), sig_b.size()), "$mod")
1735 DEF_METHOD(LogicAnd, 1, "$logic_and")
1736 DEF_METHOD(LogicOr, 1, "$logic_or")
1737 #undef DEF_METHOD
1738
1739 #define DEF_METHOD(_func, _type, _pmux) \
1740 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, RTLIL::SigSpec sig_y, const std::string &src) { \
1741 RTLIL::Cell *cell = addCell(name, _type); \
1742 cell->parameters["\\WIDTH"] = sig_a.size(); \
1743 if (_pmux) cell->parameters["\\S_WIDTH"] = sig_s.size(); \
1744 cell->setPort("\\A", sig_a); \
1745 cell->setPort("\\B", sig_b); \
1746 cell->setPort("\\S", sig_s); \
1747 cell->setPort("\\Y", sig_y); \
1748 cell->set_src_attribute(src); \
1749 return cell; \
1750 } \
1751 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, const std::string &src) { \
1752 RTLIL::SigSpec sig_y = addWire(NEW_ID, sig_a.size()); \
1753 add ## _func(name, sig_a, sig_b, sig_s, sig_y, src); \
1754 return sig_y; \
1755 }
1756 DEF_METHOD(Mux, "$mux", 0)
1757 DEF_METHOD(Pmux, "$pmux", 1)
1758 #undef DEF_METHOD
1759
1760 #define DEF_METHOD_2(_func, _type, _P1, _P2) \
1761 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, const std::string &src) { \
1762 RTLIL::Cell *cell = addCell(name, _type); \
1763 cell->setPort("\\" #_P1, sig1); \
1764 cell->setPort("\\" #_P2, sig2); \
1765 cell->set_src_attribute(src); \
1766 return cell; \
1767 } \
1768 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, const std::string &src) { \
1769 RTLIL::SigBit sig2 = addWire(NEW_ID); \
1770 add ## _func(name, sig1, sig2, src); \
1771 return sig2; \
1772 }
1773 #define DEF_METHOD_3(_func, _type, _P1, _P2, _P3) \
1774 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, const std::string &src) { \
1775 RTLIL::Cell *cell = addCell(name, _type); \
1776 cell->setPort("\\" #_P1, sig1); \
1777 cell->setPort("\\" #_P2, sig2); \
1778 cell->setPort("\\" #_P3, sig3); \
1779 cell->set_src_attribute(src); \
1780 return cell; \
1781 } \
1782 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, const std::string &src) { \
1783 RTLIL::SigBit sig3 = addWire(NEW_ID); \
1784 add ## _func(name, sig1, sig2, sig3, src); \
1785 return sig3; \
1786 }
1787 #define DEF_METHOD_4(_func, _type, _P1, _P2, _P3, _P4) \
1788 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, RTLIL::SigBit sig4, const std::string &src) { \
1789 RTLIL::Cell *cell = addCell(name, _type); \
1790 cell->setPort("\\" #_P1, sig1); \
1791 cell->setPort("\\" #_P2, sig2); \
1792 cell->setPort("\\" #_P3, sig3); \
1793 cell->setPort("\\" #_P4, sig4); \
1794 cell->set_src_attribute(src); \
1795 return cell; \
1796 } \
1797 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, const std::string &src) { \
1798 RTLIL::SigBit sig4 = addWire(NEW_ID); \
1799 add ## _func(name, sig1, sig2, sig3, sig4, src); \
1800 return sig4; \
1801 }
1802 #define DEF_METHOD_5(_func, _type, _P1, _P2, _P3, _P4, _P5) \
1803 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, RTLIL::SigBit sig4, RTLIL::SigBit sig5, const std::string &src) { \
1804 RTLIL::Cell *cell = addCell(name, _type); \
1805 cell->setPort("\\" #_P1, sig1); \
1806 cell->setPort("\\" #_P2, sig2); \
1807 cell->setPort("\\" #_P3, sig3); \
1808 cell->setPort("\\" #_P4, sig4); \
1809 cell->setPort("\\" #_P5, sig5); \
1810 cell->set_src_attribute(src); \
1811 return cell; \
1812 } \
1813 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, RTLIL::SigBit sig4, const std::string &src) { \
1814 RTLIL::SigBit sig5 = addWire(NEW_ID); \
1815 add ## _func(name, sig1, sig2, sig3, sig4, sig5, src); \
1816 return sig5; \
1817 }
1818 DEF_METHOD_2(BufGate, "$_BUF_", A, Y)
1819 DEF_METHOD_2(NotGate, "$_NOT_", A, Y)
1820 DEF_METHOD_3(AndGate, "$_AND_", A, B, Y)
1821 DEF_METHOD_3(NandGate, "$_NAND_", A, B, Y)
1822 DEF_METHOD_3(OrGate, "$_OR_", A, B, Y)
1823 DEF_METHOD_3(NorGate, "$_NOR_", A, B, Y)
1824 DEF_METHOD_3(XorGate, "$_XOR_", A, B, Y)
1825 DEF_METHOD_3(XnorGate, "$_XNOR_", A, B, Y)
1826 DEF_METHOD_3(AndnotGate, "$_ANDNOT_", A, B, Y)
1827 DEF_METHOD_3(OrnotGate, "$_ORNOT_", A, B, Y)
1828 DEF_METHOD_4(MuxGate, "$_MUX_", A, B, S, Y)
1829 DEF_METHOD_4(Aoi3Gate, "$_AOI3_", A, B, C, Y)
1830 DEF_METHOD_4(Oai3Gate, "$_OAI3_", A, B, C, Y)
1831 DEF_METHOD_5(Aoi4Gate, "$_AOI4_", A, B, C, D, Y)
1832 DEF_METHOD_5(Oai4Gate, "$_OAI4_", A, B, C, D, Y)
1833 #undef DEF_METHOD_2
1834 #undef DEF_METHOD_3
1835 #undef DEF_METHOD_4
1836 #undef DEF_METHOD_5
1837
1838 RTLIL::Cell* RTLIL::Module::addPow(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool a_signed, bool b_signed, const std::string &src)
1839 {
1840 RTLIL::Cell *cell = addCell(name, "$pow");
1841 cell->parameters["\\A_SIGNED"] = a_signed;
1842 cell->parameters["\\B_SIGNED"] = b_signed;
1843 cell->parameters["\\A_WIDTH"] = sig_a.size();
1844 cell->parameters["\\B_WIDTH"] = sig_b.size();
1845 cell->parameters["\\Y_WIDTH"] = sig_y.size();
1846 cell->setPort("\\A", sig_a);
1847 cell->setPort("\\B", sig_b);
1848 cell->setPort("\\Y", sig_y);
1849 cell->set_src_attribute(src);
1850 return cell;
1851 }
1852
1853 RTLIL::Cell* RTLIL::Module::addSlice(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, RTLIL::Const offset, const std::string &src)
1854 {
1855 RTLIL::Cell *cell = addCell(name, "$slice");
1856 cell->parameters["\\A_WIDTH"] = sig_a.size();
1857 cell->parameters["\\Y_WIDTH"] = sig_y.size();
1858 cell->parameters["\\OFFSET"] = offset;
1859 cell->setPort("\\A", sig_a);
1860 cell->setPort("\\Y", sig_y);
1861 cell->set_src_attribute(src);
1862 return cell;
1863 }
1864
1865 RTLIL::Cell* RTLIL::Module::addConcat(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, const std::string &src)
1866 {
1867 RTLIL::Cell *cell = addCell(name, "$concat");
1868 cell->parameters["\\A_WIDTH"] = sig_a.size();
1869 cell->parameters["\\B_WIDTH"] = sig_b.size();
1870 cell->setPort("\\A", sig_a);
1871 cell->setPort("\\B", sig_b);
1872 cell->setPort("\\Y", sig_y);
1873 cell->set_src_attribute(src);
1874 return cell;
1875 }
1876
1877 RTLIL::Cell* RTLIL::Module::addLut(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, RTLIL::Const lut, const std::string &src)
1878 {
1879 RTLIL::Cell *cell = addCell(name, "$lut");
1880 cell->parameters["\\LUT"] = lut;
1881 cell->parameters["\\WIDTH"] = sig_a.size();
1882 cell->setPort("\\A", sig_a);
1883 cell->setPort("\\Y", sig_y);
1884 cell->set_src_attribute(src);
1885 return cell;
1886 }
1887
1888 RTLIL::Cell* RTLIL::Module::addTribuf(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_y, const std::string &src)
1889 {
1890 RTLIL::Cell *cell = addCell(name, "$tribuf");
1891 cell->parameters["\\WIDTH"] = sig_a.size();
1892 cell->setPort("\\A", sig_a);
1893 cell->setPort("\\EN", sig_en);
1894 cell->setPort("\\Y", sig_y);
1895 cell->set_src_attribute(src);
1896 return cell;
1897 }
1898
1899 RTLIL::Cell* RTLIL::Module::addAssert(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src)
1900 {
1901 RTLIL::Cell *cell = addCell(name, "$assert");
1902 cell->setPort("\\A", sig_a);
1903 cell->setPort("\\EN", sig_en);
1904 cell->set_src_attribute(src);
1905 return cell;
1906 }
1907
1908 RTLIL::Cell* RTLIL::Module::addAssume(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src)
1909 {
1910 RTLIL::Cell *cell = addCell(name, "$assume");
1911 cell->setPort("\\A", sig_a);
1912 cell->setPort("\\EN", sig_en);
1913 cell->set_src_attribute(src);
1914 return cell;
1915 }
1916
1917 RTLIL::Cell* RTLIL::Module::addLive(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src)
1918 {
1919 RTLIL::Cell *cell = addCell(name, "$live");
1920 cell->setPort("\\A", sig_a);
1921 cell->setPort("\\EN", sig_en);
1922 cell->set_src_attribute(src);
1923 return cell;
1924 }
1925
1926 RTLIL::Cell* RTLIL::Module::addFair(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src)
1927 {
1928 RTLIL::Cell *cell = addCell(name, "$fair");
1929 cell->setPort("\\A", sig_a);
1930 cell->setPort("\\EN", sig_en);
1931 cell->set_src_attribute(src);
1932 return cell;
1933 }
1934
1935 RTLIL::Cell* RTLIL::Module::addCover(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src)
1936 {
1937 RTLIL::Cell *cell = addCell(name, "$cover");
1938 cell->setPort("\\A", sig_a);
1939 cell->setPort("\\EN", sig_en);
1940 cell->set_src_attribute(src);
1941 return cell;
1942 }
1943
1944 RTLIL::Cell* RTLIL::Module::addEquiv(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, const std::string &src)
1945 {
1946 RTLIL::Cell *cell = addCell(name, "$equiv");
1947 cell->setPort("\\A", sig_a);
1948 cell->setPort("\\B", sig_b);
1949 cell->setPort("\\Y", sig_y);
1950 cell->set_src_attribute(src);
1951 return cell;
1952 }
1953
1954 RTLIL::Cell* RTLIL::Module::addSr(RTLIL::IdString name, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr, RTLIL::SigSpec sig_q, bool set_polarity, bool clr_polarity, const std::string &src)
1955 {
1956 RTLIL::Cell *cell = addCell(name, "$sr");
1957 cell->parameters["\\SET_POLARITY"] = set_polarity;
1958 cell->parameters["\\CLR_POLARITY"] = clr_polarity;
1959 cell->parameters["\\WIDTH"] = sig_q.size();
1960 cell->setPort("\\SET", sig_set);
1961 cell->setPort("\\CLR", sig_clr);
1962 cell->setPort("\\Q", sig_q);
1963 cell->set_src_attribute(src);
1964 return cell;
1965 }
1966
1967 RTLIL::Cell* RTLIL::Module::addFf(RTLIL::IdString name, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, const std::string &src)
1968 {
1969 RTLIL::Cell *cell = addCell(name, "$ff");
1970 cell->parameters["\\WIDTH"] = sig_q.size();
1971 cell->setPort("\\D", sig_d);
1972 cell->setPort("\\Q", sig_q);
1973 cell->set_src_attribute(src);
1974 return cell;
1975 }
1976
1977 RTLIL::Cell* RTLIL::Module::addDff(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, const std::string &src)
1978 {
1979 RTLIL::Cell *cell = addCell(name, "$dff");
1980 cell->parameters["\\CLK_POLARITY"] = clk_polarity;
1981 cell->parameters["\\WIDTH"] = sig_q.size();
1982 cell->setPort("\\CLK", sig_clk);
1983 cell->setPort("\\D", sig_d);
1984 cell->setPort("\\Q", sig_q);
1985 cell->set_src_attribute(src);
1986 return cell;
1987 }
1988
1989 RTLIL::Cell* RTLIL::Module::addDffe(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, bool en_polarity, const std::string &src)
1990 {
1991 RTLIL::Cell *cell = addCell(name, "$dffe");
1992 cell->parameters["\\CLK_POLARITY"] = clk_polarity;
1993 cell->parameters["\\EN_POLARITY"] = en_polarity;
1994 cell->parameters["\\WIDTH"] = sig_q.size();
1995 cell->setPort("\\CLK", sig_clk);
1996 cell->setPort("\\EN", sig_en);
1997 cell->setPort("\\D", sig_d);
1998 cell->setPort("\\Q", sig_q);
1999 cell->set_src_attribute(src);
2000 return cell;
2001 }
2002
2003 RTLIL::Cell* RTLIL::Module::addDffsr(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
2004 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
2005 {
2006 RTLIL::Cell *cell = addCell(name, "$dffsr");
2007 cell->parameters["\\CLK_POLARITY"] = clk_polarity;
2008 cell->parameters["\\SET_POLARITY"] = set_polarity;
2009 cell->parameters["\\CLR_POLARITY"] = clr_polarity;
2010 cell->parameters["\\WIDTH"] = sig_q.size();
2011 cell->setPort("\\CLK", sig_clk);
2012 cell->setPort("\\SET", sig_set);
2013 cell->setPort("\\CLR", sig_clr);
2014 cell->setPort("\\D", sig_d);
2015 cell->setPort("\\Q", sig_q);
2016 cell->set_src_attribute(src);
2017 return cell;
2018 }
2019
2020 RTLIL::Cell* RTLIL::Module::addAdff(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_arst, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q,
2021 RTLIL::Const arst_value, bool clk_polarity, bool arst_polarity, const std::string &src)
2022 {
2023 RTLIL::Cell *cell = addCell(name, "$adff");
2024 cell->parameters["\\CLK_POLARITY"] = clk_polarity;
2025 cell->parameters["\\ARST_POLARITY"] = arst_polarity;
2026 cell->parameters["\\ARST_VALUE"] = arst_value;
2027 cell->parameters["\\WIDTH"] = sig_q.size();
2028 cell->setPort("\\CLK", sig_clk);
2029 cell->setPort("\\ARST", sig_arst);
2030 cell->setPort("\\D", sig_d);
2031 cell->setPort("\\Q", sig_q);
2032 cell->set_src_attribute(src);
2033 return cell;
2034 }
2035
2036 RTLIL::Cell* RTLIL::Module::addDlatch(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity, const std::string &src)
2037 {
2038 RTLIL::Cell *cell = addCell(name, "$dlatch");
2039 cell->parameters["\\EN_POLARITY"] = en_polarity;
2040 cell->parameters["\\WIDTH"] = sig_q.size();
2041 cell->setPort("\\EN", sig_en);
2042 cell->setPort("\\D", sig_d);
2043 cell->setPort("\\Q", sig_q);
2044 cell->set_src_attribute(src);
2045 return cell;
2046 }
2047
2048 RTLIL::Cell* RTLIL::Module::addDlatchsr(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
2049 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
2050 {
2051 RTLIL::Cell *cell = addCell(name, "$dlatchsr");
2052 cell->parameters["\\EN_POLARITY"] = en_polarity;
2053 cell->parameters["\\SET_POLARITY"] = set_polarity;
2054 cell->parameters["\\CLR_POLARITY"] = clr_polarity;
2055 cell->parameters["\\WIDTH"] = sig_q.size();
2056 cell->setPort("\\EN", sig_en);
2057 cell->setPort("\\SET", sig_set);
2058 cell->setPort("\\CLR", sig_clr);
2059 cell->setPort("\\D", sig_d);
2060 cell->setPort("\\Q", sig_q);
2061 cell->set_src_attribute(src);
2062 return cell;
2063 }
2064
2065 RTLIL::Cell* RTLIL::Module::addFfGate(RTLIL::IdString name, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, const std::string &src)
2066 {
2067 RTLIL::Cell *cell = addCell(name, "$_FF_");
2068 cell->setPort("\\D", sig_d);
2069 cell->setPort("\\Q", sig_q);
2070 cell->set_src_attribute(src);
2071 return cell;
2072 }
2073
2074 RTLIL::Cell* RTLIL::Module::addDffGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, const std::string &src)
2075 {
2076 RTLIL::Cell *cell = addCell(name, stringf("$_DFF_%c_", clk_polarity ? 'P' : 'N'));
2077 cell->setPort("\\C", sig_clk);
2078 cell->setPort("\\D", sig_d);
2079 cell->setPort("\\Q", sig_q);
2080 cell->set_src_attribute(src);
2081 return cell;
2082 }
2083
2084 RTLIL::Cell* RTLIL::Module::addDffeGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, bool en_polarity, const std::string &src)
2085 {
2086 RTLIL::Cell *cell = addCell(name, stringf("$_DFFE_%c%c_", clk_polarity ? 'P' : 'N', en_polarity ? 'P' : 'N'));
2087 cell->setPort("\\C", sig_clk);
2088 cell->setPort("\\E", sig_en);
2089 cell->setPort("\\D", sig_d);
2090 cell->setPort("\\Q", sig_q);
2091 cell->set_src_attribute(src);
2092 return cell;
2093 }
2094
2095 RTLIL::Cell* RTLIL::Module::addDffsrGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
2096 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
2097 {
2098 RTLIL::Cell *cell = addCell(name, stringf("$_DFFSR_%c%c%c_", clk_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N'));
2099 cell->setPort("\\C", sig_clk);
2100 cell->setPort("\\S", sig_set);
2101 cell->setPort("\\R", sig_clr);
2102 cell->setPort("\\D", sig_d);
2103 cell->setPort("\\Q", sig_q);
2104 cell->set_src_attribute(src);
2105 return cell;
2106 }
2107
2108 RTLIL::Cell* RTLIL::Module::addAdffGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_arst, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q,
2109 bool arst_value, bool clk_polarity, bool arst_polarity, const std::string &src)
2110 {
2111 RTLIL::Cell *cell = addCell(name, stringf("$_DFF_%c%c%c_", clk_polarity ? 'P' : 'N', arst_polarity ? 'P' : 'N', arst_value ? '1' : '0'));
2112 cell->setPort("\\C", sig_clk);
2113 cell->setPort("\\R", sig_arst);
2114 cell->setPort("\\D", sig_d);
2115 cell->setPort("\\Q", sig_q);
2116 cell->set_src_attribute(src);
2117 return cell;
2118 }
2119
2120 RTLIL::Cell* RTLIL::Module::addDlatchGate(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity, const std::string &src)
2121 {
2122 RTLIL::Cell *cell = addCell(name, stringf("$_DLATCH_%c_", en_polarity ? 'P' : 'N'));
2123 cell->setPort("\\E", sig_en);
2124 cell->setPort("\\D", sig_d);
2125 cell->setPort("\\Q", sig_q);
2126 cell->set_src_attribute(src);
2127 return cell;
2128 }
2129
2130 RTLIL::Cell* RTLIL::Module::addDlatchsrGate(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
2131 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
2132 {
2133 RTLIL::Cell *cell = addCell(name, stringf("$_DLATCHSR_%c%c%c_", en_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N'));
2134 cell->setPort("\\E", sig_en);
2135 cell->setPort("\\S", sig_set);
2136 cell->setPort("\\R", sig_clr);
2137 cell->setPort("\\D", sig_d);
2138 cell->setPort("\\Q", sig_q);
2139 cell->set_src_attribute(src);
2140 return cell;
2141 }
2142
2143 RTLIL::SigSpec RTLIL::Module::Anyconst(RTLIL::IdString name, int width, const std::string &src)
2144 {
2145 RTLIL::SigSpec sig = addWire(NEW_ID, width);
2146 Cell *cell = addCell(name, "$anyconst");
2147 cell->setParam("\\WIDTH", width);
2148 cell->setPort("\\Y", sig);
2149 cell->set_src_attribute(src);
2150 return sig;
2151 }
2152
2153 RTLIL::SigSpec RTLIL::Module::Anyseq(RTLIL::IdString name, int width, const std::string &src)
2154 {
2155 RTLIL::SigSpec sig = addWire(NEW_ID, width);
2156 Cell *cell = addCell(name, "$anyseq");
2157 cell->setParam("\\WIDTH", width);
2158 cell->setPort("\\Y", sig);
2159 cell->set_src_attribute(src);
2160 return sig;
2161 }
2162
2163 RTLIL::SigSpec RTLIL::Module::Allconst(RTLIL::IdString name, int width, const std::string &src)
2164 {
2165 RTLIL::SigSpec sig = addWire(NEW_ID, width);
2166 Cell *cell = addCell(name, "$allconst");
2167 cell->setParam("\\WIDTH", width);
2168 cell->setPort("\\Y", sig);
2169 cell->set_src_attribute(src);
2170 return sig;
2171 }
2172
2173 RTLIL::SigSpec RTLIL::Module::Allseq(RTLIL::IdString name, int width, const std::string &src)
2174 {
2175 RTLIL::SigSpec sig = addWire(NEW_ID, width);
2176 Cell *cell = addCell(name, "$allseq");
2177 cell->setParam("\\WIDTH", width);
2178 cell->setPort("\\Y", sig);
2179 cell->set_src_attribute(src);
2180 return sig;
2181 }
2182
2183 RTLIL::SigSpec RTLIL::Module::Initstate(RTLIL::IdString name, const std::string &src)
2184 {
2185 RTLIL::SigSpec sig = addWire(NEW_ID);
2186 Cell *cell = addCell(name, "$initstate");
2187 cell->setPort("\\Y", sig);
2188 cell->set_src_attribute(src);
2189 return sig;
2190 }
2191
2192 RTLIL::Wire::Wire()
2193 {
2194 static unsigned int hashidx_count = 123456789;
2195 hashidx_count = mkhash_xorshift(hashidx_count);
2196 hashidx_ = hashidx_count;
2197
2198 module = nullptr;
2199 width = 1;
2200 start_offset = 0;
2201 port_id = 0;
2202 port_input = false;
2203 port_output = false;
2204 upto = false;
2205 }
2206
2207 RTLIL::Memory::Memory()
2208 {
2209 static unsigned int hashidx_count = 123456789;
2210 hashidx_count = mkhash_xorshift(hashidx_count);
2211 hashidx_ = hashidx_count;
2212
2213 width = 1;
2214 start_offset = 0;
2215 size = 0;
2216 }
2217
2218 RTLIL::Cell::Cell() : module(nullptr)
2219 {
2220 static unsigned int hashidx_count = 123456789;
2221 hashidx_count = mkhash_xorshift(hashidx_count);
2222 hashidx_ = hashidx_count;
2223
2224 // log("#memtrace# %p\n", this);
2225 memhasher();
2226 }
2227
2228 bool RTLIL::Cell::hasPort(RTLIL::IdString portname) const
2229 {
2230 return connections_.count(portname) != 0;
2231 }
2232
2233 void RTLIL::Cell::unsetPort(RTLIL::IdString portname)
2234 {
2235 RTLIL::SigSpec signal;
2236 auto conn_it = connections_.find(portname);
2237
2238 if (conn_it != connections_.end())
2239 {
2240 for (auto mon : module->monitors)
2241 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
2242
2243 if (module->design)
2244 for (auto mon : module->design->monitors)
2245 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
2246
2247 if (yosys_xtrace) {
2248 log("#X# Unconnect %s.%s.%s\n", log_id(this->module), log_id(this), log_id(portname));
2249 log_backtrace("-X- ", yosys_xtrace-1);
2250 }
2251
2252 connections_.erase(conn_it);
2253 }
2254 }
2255
2256 void RTLIL::Cell::setPort(RTLIL::IdString portname, RTLIL::SigSpec signal)
2257 {
2258 auto conn_it = connections_.find(portname);
2259
2260 if (conn_it == connections_.end()) {
2261 connections_[portname] = RTLIL::SigSpec();
2262 conn_it = connections_.find(portname);
2263 log_assert(conn_it != connections_.end());
2264 } else
2265 if (conn_it->second == signal)
2266 return;
2267
2268 for (auto mon : module->monitors)
2269 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
2270
2271 if (module->design)
2272 for (auto mon : module->design->monitors)
2273 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
2274
2275 if (yosys_xtrace) {
2276 log("#X# Connect %s.%s.%s = %s (%d)\n", log_id(this->module), log_id(this), log_id(portname), log_signal(signal), GetSize(signal));
2277 log_backtrace("-X- ", yosys_xtrace-1);
2278 }
2279
2280 conn_it->second = signal;
2281 }
2282
2283 const RTLIL::SigSpec &RTLIL::Cell::getPort(RTLIL::IdString portname) const
2284 {
2285 return connections_.at(portname);
2286 }
2287
2288 const dict<RTLIL::IdString, RTLIL::SigSpec> &RTLIL::Cell::connections() const
2289 {
2290 return connections_;
2291 }
2292
2293 bool RTLIL::Cell::known() const
2294 {
2295 if (yosys_celltypes.cell_known(type))
2296 return true;
2297 if (module && module->design && module->design->module(type))
2298 return true;
2299 return false;
2300 }
2301
2302 bool RTLIL::Cell::input(RTLIL::IdString portname) const
2303 {
2304 if (yosys_celltypes.cell_known(type))
2305 return yosys_celltypes.cell_input(type, portname);
2306 if (module && module->design) {
2307 RTLIL::Module *m = module->design->module(type);
2308 RTLIL::Wire *w = m ? m->wire(portname) : nullptr;
2309 return w && w->port_input;
2310 }
2311 return false;
2312 }
2313
2314 bool RTLIL::Cell::output(RTLIL::IdString portname) const
2315 {
2316 if (yosys_celltypes.cell_known(type))
2317 return yosys_celltypes.cell_output(type, portname);
2318 if (module && module->design) {
2319 RTLIL::Module *m = module->design->module(type);
2320 RTLIL::Wire *w = m ? m->wire(portname) : nullptr;
2321 return w && w->port_output;
2322 }
2323 return false;
2324 }
2325
2326 bool RTLIL::Cell::hasParam(RTLIL::IdString paramname) const
2327 {
2328 return parameters.count(paramname) != 0;
2329 }
2330
2331 void RTLIL::Cell::unsetParam(RTLIL::IdString paramname)
2332 {
2333 parameters.erase(paramname);
2334 }
2335
2336 void RTLIL::Cell::setParam(RTLIL::IdString paramname, RTLIL::Const value)
2337 {
2338 parameters[paramname] = value;
2339 }
2340
2341 const RTLIL::Const &RTLIL::Cell::getParam(RTLIL::IdString paramname) const
2342 {
2343 return parameters.at(paramname);
2344 }
2345
2346 void RTLIL::Cell::sort()
2347 {
2348 connections_.sort(sort_by_id_str());
2349 parameters.sort(sort_by_id_str());
2350 attributes.sort(sort_by_id_str());
2351 }
2352
2353 void RTLIL::Cell::check()
2354 {
2355 #ifndef NDEBUG
2356 InternalCellChecker checker(NULL, this);
2357 checker.check();
2358 #endif
2359 }
2360
2361 void RTLIL::Cell::fixup_parameters(bool set_a_signed, bool set_b_signed)
2362 {
2363 if (type.substr(0, 1) != "$" || type.substr(0, 2) == "$_" || type.substr(0, 8) == "$paramod" ||
2364 type.substr(0, 9) == "$verific$" || type.substr(0, 7) == "$array:" || type.substr(0, 8) == "$extern:")
2365 return;
2366
2367 if (type == "$mux" || type == "$pmux") {
2368 parameters["\\WIDTH"] = GetSize(connections_["\\Y"]);
2369 if (type == "$pmux")
2370 parameters["\\S_WIDTH"] = GetSize(connections_["\\S"]);
2371 check();
2372 return;
2373 }
2374
2375 if (type == "$lut" || type == "$sop") {
2376 parameters["\\WIDTH"] = GetSize(connections_["\\A"]);
2377 return;
2378 }
2379
2380 if (type == "$fa") {
2381 parameters["\\WIDTH"] = GetSize(connections_["\\Y"]);
2382 return;
2383 }
2384
2385 if (type == "$lcu") {
2386 parameters["\\WIDTH"] = GetSize(connections_["\\CO"]);
2387 return;
2388 }
2389
2390 bool signedness_ab = !type.in("$slice", "$concat", "$macc");
2391
2392 if (connections_.count("\\A")) {
2393 if (signedness_ab) {
2394 if (set_a_signed)
2395 parameters["\\A_SIGNED"] = true;
2396 else if (parameters.count("\\A_SIGNED") == 0)
2397 parameters["\\A_SIGNED"] = false;
2398 }
2399 parameters["\\A_WIDTH"] = GetSize(connections_["\\A"]);
2400 }
2401
2402 if (connections_.count("\\B")) {
2403 if (signedness_ab) {
2404 if (set_b_signed)
2405 parameters["\\B_SIGNED"] = true;
2406 else if (parameters.count("\\B_SIGNED") == 0)
2407 parameters["\\B_SIGNED"] = false;
2408 }
2409 parameters["\\B_WIDTH"] = GetSize(connections_["\\B"]);
2410 }
2411
2412 if (connections_.count("\\Y"))
2413 parameters["\\Y_WIDTH"] = GetSize(connections_["\\Y"]);
2414
2415 if (connections_.count("\\Q"))
2416 parameters["\\WIDTH"] = GetSize(connections_["\\Q"]);
2417
2418 check();
2419 }
2420
2421 RTLIL::SigChunk::SigChunk()
2422 {
2423 wire = NULL;
2424 width = 0;
2425 offset = 0;
2426 }
2427
2428 RTLIL::SigChunk::SigChunk(const RTLIL::Const &value)
2429 {
2430 wire = NULL;
2431 data = value.bits;
2432 width = GetSize(data);
2433 offset = 0;
2434 }
2435
2436 RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire)
2437 {
2438 log_assert(wire != nullptr);
2439 this->wire = wire;
2440 this->width = wire->width;
2441 this->offset = 0;
2442 }
2443
2444 RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire, int offset, int width)
2445 {
2446 log_assert(wire != nullptr);
2447 this->wire = wire;
2448 this->width = width;
2449 this->offset = offset;
2450 }
2451
2452 RTLIL::SigChunk::SigChunk(const std::string &str)
2453 {
2454 wire = NULL;
2455 data = RTLIL::Const(str).bits;
2456 width = GetSize(data);
2457 offset = 0;
2458 }
2459
2460 RTLIL::SigChunk::SigChunk(int val, int width)
2461 {
2462 wire = NULL;
2463 data = RTLIL::Const(val, width).bits;
2464 this->width = GetSize(data);
2465 offset = 0;
2466 }
2467
2468 RTLIL::SigChunk::SigChunk(RTLIL::State bit, int width)
2469 {
2470 wire = NULL;
2471 data = RTLIL::Const(bit, width).bits;
2472 this->width = GetSize(data);
2473 offset = 0;
2474 }
2475
2476 RTLIL::SigChunk::SigChunk(RTLIL::SigBit bit)
2477 {
2478 wire = bit.wire;
2479 offset = 0;
2480 if (wire == NULL)
2481 data = RTLIL::Const(bit.data).bits;
2482 else
2483 offset = bit.offset;
2484 width = 1;
2485 }
2486
2487 RTLIL::SigChunk RTLIL::SigChunk::extract(int offset, int length) const
2488 {
2489 RTLIL::SigChunk ret;
2490 if (wire) {
2491 ret.wire = wire;
2492 ret.offset = this->offset + offset;
2493 ret.width = length;
2494 } else {
2495 for (int i = 0; i < length; i++)
2496 ret.data.push_back(data[offset+i]);
2497 ret.width = length;
2498 }
2499 return ret;
2500 }
2501
2502 bool RTLIL::SigChunk::operator <(const RTLIL::SigChunk &other) const
2503 {
2504 if (wire && other.wire)
2505 if (wire->name != other.wire->name)
2506 return wire->name < other.wire->name;
2507
2508 if (wire != other.wire)
2509 return wire < other.wire;
2510
2511 if (offset != other.offset)
2512 return offset < other.offset;
2513
2514 if (width != other.width)
2515 return width < other.width;
2516
2517 return data < other.data;
2518 }
2519
2520 bool RTLIL::SigChunk::operator ==(const RTLIL::SigChunk &other) const
2521 {
2522 return wire == other.wire && width == other.width && offset == other.offset && data == other.data;
2523 }
2524
2525 bool RTLIL::SigChunk::operator !=(const RTLIL::SigChunk &other) const
2526 {
2527 if (*this == other)
2528 return false;
2529 return true;
2530 }
2531
2532 RTLIL::SigSpec::SigSpec()
2533 {
2534 width_ = 0;
2535 hash_ = 0;
2536 }
2537
2538 RTLIL::SigSpec::SigSpec(const RTLIL::SigSpec &other)
2539 {
2540 *this = other;
2541 }
2542
2543 RTLIL::SigSpec::SigSpec(std::initializer_list<RTLIL::SigSpec> parts)
2544 {
2545 cover("kernel.rtlil.sigspec.init.list");
2546
2547 width_ = 0;
2548 hash_ = 0;
2549
2550 std::vector<RTLIL::SigSpec> parts_vec(parts.begin(), parts.end());
2551 for (auto it = parts_vec.rbegin(); it != parts_vec.rend(); it++)
2552 append(*it);
2553 }
2554
2555 const RTLIL::SigSpec &RTLIL::SigSpec::operator=(const RTLIL::SigSpec &other)
2556 {
2557 cover("kernel.rtlil.sigspec.assign");
2558
2559 width_ = other.width_;
2560 hash_ = other.hash_;
2561 chunks_ = other.chunks_;
2562 bits_.clear();
2563
2564 if (!other.bits_.empty())
2565 {
2566 RTLIL::SigChunk *last = NULL;
2567 int last_end_offset = 0;
2568
2569 for (auto &bit : other.bits_) {
2570 if (last && bit.wire == last->wire) {
2571 if (bit.wire == NULL) {
2572 last->data.push_back(bit.data);
2573 last->width++;
2574 continue;
2575 } else if (last_end_offset == bit.offset) {
2576 last_end_offset++;
2577 last->width++;
2578 continue;
2579 }
2580 }
2581 chunks_.push_back(bit);
2582 last = &chunks_.back();
2583 last_end_offset = bit.offset + 1;
2584 }
2585
2586 check();
2587 }
2588
2589 return *this;
2590 }
2591
2592 RTLIL::SigSpec::SigSpec(const RTLIL::Const &value)
2593 {
2594 cover("kernel.rtlil.sigspec.init.const");
2595
2596 chunks_.push_back(RTLIL::SigChunk(value));
2597 width_ = chunks_.back().width;
2598 hash_ = 0;
2599 check();
2600 }
2601
2602 RTLIL::SigSpec::SigSpec(const RTLIL::SigChunk &chunk)
2603 {
2604 cover("kernel.rtlil.sigspec.init.chunk");
2605
2606 chunks_.push_back(chunk);
2607 width_ = chunks_.back().width;
2608 hash_ = 0;
2609 check();
2610 }
2611
2612 RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire)
2613 {
2614 cover("kernel.rtlil.sigspec.init.wire");
2615
2616 chunks_.push_back(RTLIL::SigChunk(wire));
2617 width_ = chunks_.back().width;
2618 hash_ = 0;
2619 check();
2620 }
2621
2622 RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire, int offset, int width)
2623 {
2624 cover("kernel.rtlil.sigspec.init.wire_part");
2625
2626 chunks_.push_back(RTLIL::SigChunk(wire, offset, width));
2627 width_ = chunks_.back().width;
2628 hash_ = 0;
2629 check();
2630 }
2631
2632 RTLIL::SigSpec::SigSpec(const std::string &str)
2633 {
2634 cover("kernel.rtlil.sigspec.init.str");
2635
2636 chunks_.push_back(RTLIL::SigChunk(str));
2637 width_ = chunks_.back().width;
2638 hash_ = 0;
2639 check();
2640 }
2641
2642 RTLIL::SigSpec::SigSpec(int val, int width)
2643 {
2644 cover("kernel.rtlil.sigspec.init.int");
2645
2646 chunks_.push_back(RTLIL::SigChunk(val, width));
2647 width_ = width;
2648 hash_ = 0;
2649 check();
2650 }
2651
2652 RTLIL::SigSpec::SigSpec(RTLIL::State bit, int width)
2653 {
2654 cover("kernel.rtlil.sigspec.init.state");
2655
2656 chunks_.push_back(RTLIL::SigChunk(bit, width));
2657 width_ = width;
2658 hash_ = 0;
2659 check();
2660 }
2661
2662 RTLIL::SigSpec::SigSpec(RTLIL::SigBit bit, int width)
2663 {
2664 cover("kernel.rtlil.sigspec.init.bit");
2665
2666 if (bit.wire == NULL)
2667 chunks_.push_back(RTLIL::SigChunk(bit.data, width));
2668 else
2669 for (int i = 0; i < width; i++)
2670 chunks_.push_back(bit);
2671 width_ = width;
2672 hash_ = 0;
2673 check();
2674 }
2675
2676 RTLIL::SigSpec::SigSpec(std::vector<RTLIL::SigChunk> chunks)
2677 {
2678 cover("kernel.rtlil.sigspec.init.stdvec_chunks");
2679
2680 width_ = 0;
2681 hash_ = 0;
2682 for (auto &c : chunks)
2683 append(c);
2684 check();
2685 }
2686
2687 RTLIL::SigSpec::SigSpec(std::vector<RTLIL::SigBit> bits)
2688 {
2689 cover("kernel.rtlil.sigspec.init.stdvec_bits");
2690
2691 width_ = 0;
2692 hash_ = 0;
2693 for (auto &bit : bits)
2694 append_bit(bit);
2695 check();
2696 }
2697
2698 RTLIL::SigSpec::SigSpec(pool<RTLIL::SigBit> bits)
2699 {
2700 cover("kernel.rtlil.sigspec.init.pool_bits");
2701
2702 width_ = 0;
2703 hash_ = 0;
2704 for (auto &bit : bits)
2705 append_bit(bit);
2706 check();
2707 }
2708
2709 RTLIL::SigSpec::SigSpec(std::set<RTLIL::SigBit> bits)
2710 {
2711 cover("kernel.rtlil.sigspec.init.stdset_bits");
2712
2713 width_ = 0;
2714 hash_ = 0;
2715 for (auto &bit : bits)
2716 append_bit(bit);
2717 check();
2718 }
2719
2720 RTLIL::SigSpec::SigSpec(bool bit)
2721 {
2722 cover("kernel.rtlil.sigspec.init.bool");
2723
2724 width_ = 0;
2725 hash_ = 0;
2726 append_bit(bit);
2727 check();
2728 }
2729
2730 void RTLIL::SigSpec::pack() const
2731 {
2732 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
2733
2734 if (that->bits_.empty())
2735 return;
2736
2737 cover("kernel.rtlil.sigspec.convert.pack");
2738 log_assert(that->chunks_.empty());
2739
2740 std::vector<RTLIL::SigBit> old_bits;
2741 old_bits.swap(that->bits_);
2742
2743 RTLIL::SigChunk *last = NULL;
2744 int last_end_offset = 0;
2745
2746 for (auto &bit : old_bits) {
2747 if (last && bit.wire == last->wire) {
2748 if (bit.wire == NULL) {
2749 last->data.push_back(bit.data);
2750 last->width++;
2751 continue;
2752 } else if (last_end_offset == bit.offset) {
2753 last_end_offset++;
2754 last->width++;
2755 continue;
2756 }
2757 }
2758 that->chunks_.push_back(bit);
2759 last = &that->chunks_.back();
2760 last_end_offset = bit.offset + 1;
2761 }
2762
2763 check();
2764 }
2765
2766 void RTLIL::SigSpec::unpack() const
2767 {
2768 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
2769
2770 if (that->chunks_.empty())
2771 return;
2772
2773 cover("kernel.rtlil.sigspec.convert.unpack");
2774 log_assert(that->bits_.empty());
2775
2776 that->bits_.reserve(that->width_);
2777 for (auto &c : that->chunks_)
2778 for (int i = 0; i < c.width; i++)
2779 that->bits_.push_back(RTLIL::SigBit(c, i));
2780
2781 that->chunks_.clear();
2782 that->hash_ = 0;
2783 }
2784
2785 void RTLIL::SigSpec::updhash() const
2786 {
2787 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
2788
2789 if (that->hash_ != 0)
2790 return;
2791
2792 cover("kernel.rtlil.sigspec.hash");
2793 that->pack();
2794
2795 that->hash_ = mkhash_init;
2796 for (auto &c : that->chunks_)
2797 if (c.wire == NULL) {
2798 for (auto &v : c.data)
2799 that->hash_ = mkhash(that->hash_, v);
2800 } else {
2801 that->hash_ = mkhash(that->hash_, c.wire->name.index_);
2802 that->hash_ = mkhash(that->hash_, c.offset);
2803 that->hash_ = mkhash(that->hash_, c.width);
2804 }
2805
2806 if (that->hash_ == 0)
2807 that->hash_ = 1;
2808 }
2809
2810 void RTLIL::SigSpec::sort()
2811 {
2812 unpack();
2813 cover("kernel.rtlil.sigspec.sort");
2814 std::sort(bits_.begin(), bits_.end());
2815 }
2816
2817 void RTLIL::SigSpec::sort_and_unify()
2818 {
2819 unpack();
2820 cover("kernel.rtlil.sigspec.sort_and_unify");
2821
2822 // A copy of the bits vector is used to prevent duplicating the logic from
2823 // SigSpec::SigSpec(std::vector<SigBit>). This incurrs an extra copy but
2824 // that isn't showing up as significant in profiles.
2825 std::vector<SigBit> unique_bits = bits_;
2826 std::sort(unique_bits.begin(), unique_bits.end());
2827 auto last = std::unique(unique_bits.begin(), unique_bits.end());
2828 unique_bits.erase(last, unique_bits.end());
2829
2830 *this = unique_bits;
2831 }
2832
2833 void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with)
2834 {
2835 replace(pattern, with, this);
2836 }
2837
2838 void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with, RTLIL::SigSpec *other) const
2839 {
2840 log_assert(other != NULL);
2841 log_assert(width_ == other->width_);
2842 log_assert(pattern.width_ == with.width_);
2843
2844 pattern.unpack();
2845 with.unpack();
2846 unpack();
2847 other->unpack();
2848
2849 for (int i = 0; i < GetSize(pattern.bits_); i++) {
2850 if (pattern.bits_[i].wire != NULL) {
2851 for (int j = 0; j < GetSize(bits_); j++) {
2852 if (bits_[j] == pattern.bits_[i]) {
2853 other->bits_[j] = with.bits_[i];
2854 }
2855 }
2856 }
2857 }
2858
2859 other->check();
2860 }
2861
2862 void RTLIL::SigSpec::replace(const dict<RTLIL::SigBit, RTLIL::SigBit> &rules)
2863 {
2864 replace(rules, this);
2865 }
2866
2867 void RTLIL::SigSpec::replace(const dict<RTLIL::SigBit, RTLIL::SigBit> &rules, RTLIL::SigSpec *other) const
2868 {
2869 cover("kernel.rtlil.sigspec.replace_dict");
2870
2871 log_assert(other != NULL);
2872 log_assert(width_ == other->width_);
2873
2874 unpack();
2875 other->unpack();
2876
2877 for (int i = 0; i < GetSize(bits_); i++) {
2878 auto it = rules.find(bits_[i]);
2879 if (it != rules.end())
2880 other->bits_[i] = it->second;
2881 }
2882
2883 other->check();
2884 }
2885
2886 void RTLIL::SigSpec::replace(const std::map<RTLIL::SigBit, RTLIL::SigBit> &rules)
2887 {
2888 replace(rules, this);
2889 }
2890
2891 void RTLIL::SigSpec::replace(const std::map<RTLIL::SigBit, RTLIL::SigBit> &rules, RTLIL::SigSpec *other) const
2892 {
2893 cover("kernel.rtlil.sigspec.replace_map");
2894
2895 log_assert(other != NULL);
2896 log_assert(width_ == other->width_);
2897
2898 unpack();
2899 other->unpack();
2900
2901 for (int i = 0; i < GetSize(bits_); i++) {
2902 auto it = rules.find(bits_[i]);
2903 if (it != rules.end())
2904 other->bits_[i] = it->second;
2905 }
2906
2907 other->check();
2908 }
2909
2910 void RTLIL::SigSpec::remove(const RTLIL::SigSpec &pattern)
2911 {
2912 remove2(pattern, NULL);
2913 }
2914
2915 void RTLIL::SigSpec::remove(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other) const
2916 {
2917 RTLIL::SigSpec tmp = *this;
2918 tmp.remove2(pattern, other);
2919 }
2920
2921 void RTLIL::SigSpec::remove2(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other)
2922 {
2923 if (other)
2924 cover("kernel.rtlil.sigspec.remove_other");
2925 else
2926 cover("kernel.rtlil.sigspec.remove");
2927
2928 unpack();
2929 if (other != NULL) {
2930 log_assert(width_ == other->width_);
2931 other->unpack();
2932 }
2933
2934 for (int i = GetSize(bits_) - 1; i >= 0; i--)
2935 {
2936 if (bits_[i].wire == NULL) continue;
2937
2938 for (auto &pattern_chunk : pattern.chunks())
2939 if (bits_[i].wire == pattern_chunk.wire &&
2940 bits_[i].offset >= pattern_chunk.offset &&
2941 bits_[i].offset < pattern_chunk.offset + pattern_chunk.width) {
2942 bits_.erase(bits_.begin() + i);
2943 width_--;
2944 if (other != NULL) {
2945 other->bits_.erase(other->bits_.begin() + i);
2946 other->width_--;
2947 }
2948 break;
2949 }
2950 }
2951
2952 check();
2953 }
2954
2955 void RTLIL::SigSpec::remove(const pool<RTLIL::SigBit> &pattern)
2956 {
2957 remove2(pattern, NULL);
2958 }
2959
2960 void RTLIL::SigSpec::remove(const pool<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other) const
2961 {
2962 RTLIL::SigSpec tmp = *this;
2963 tmp.remove2(pattern, other);
2964 }
2965
2966 void RTLIL::SigSpec::remove2(const pool<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other)
2967 {
2968 if (other)
2969 cover("kernel.rtlil.sigspec.remove_other");
2970 else
2971 cover("kernel.rtlil.sigspec.remove");
2972
2973 unpack();
2974
2975 if (other != NULL) {
2976 log_assert(width_ == other->width_);
2977 other->unpack();
2978 }
2979
2980 for (int i = GetSize(bits_) - 1; i >= 0; i--) {
2981 if (bits_[i].wire != NULL && pattern.count(bits_[i])) {
2982 bits_.erase(bits_.begin() + i);
2983 width_--;
2984 if (other != NULL) {
2985 other->bits_.erase(other->bits_.begin() + i);
2986 other->width_--;
2987 }
2988 }
2989 }
2990
2991 check();
2992 }
2993
2994 void RTLIL::SigSpec::remove2(const std::set<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other)
2995 {
2996 if (other)
2997 cover("kernel.rtlil.sigspec.remove_other");
2998 else
2999 cover("kernel.rtlil.sigspec.remove");
3000
3001 unpack();
3002
3003 if (other != NULL) {
3004 log_assert(width_ == other->width_);
3005 other->unpack();
3006 }
3007
3008 for (int i = GetSize(bits_) - 1; i >= 0; i--) {
3009 if (bits_[i].wire != NULL && pattern.count(bits_[i])) {
3010 bits_.erase(bits_.begin() + i);
3011 width_--;
3012 if (other != NULL) {
3013 other->bits_.erase(other->bits_.begin() + i);
3014 other->width_--;
3015 }
3016 }
3017 }
3018
3019 check();
3020 }
3021
3022 RTLIL::SigSpec RTLIL::SigSpec::extract(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec *other) const
3023 {
3024 if (other)
3025 cover("kernel.rtlil.sigspec.extract_other");
3026 else
3027 cover("kernel.rtlil.sigspec.extract");
3028
3029 log_assert(other == NULL || width_ == other->width_);
3030
3031 RTLIL::SigSpec ret;
3032 std::vector<RTLIL::SigBit> bits_match = to_sigbit_vector();
3033
3034 for (auto& pattern_chunk : pattern.chunks()) {
3035 if (other) {
3036 std::vector<RTLIL::SigBit> bits_other = other->to_sigbit_vector();
3037 for (int i = 0; i < width_; i++)
3038 if (bits_match[i].wire &&
3039 bits_match[i].wire == pattern_chunk.wire &&
3040 bits_match[i].offset >= pattern_chunk.offset &&
3041 bits_match[i].offset < pattern_chunk.offset + pattern_chunk.width)
3042 ret.append_bit(bits_other[i]);
3043 } else {
3044 for (int i = 0; i < width_; i++)
3045 if (bits_match[i].wire &&
3046 bits_match[i].wire == pattern_chunk.wire &&
3047 bits_match[i].offset >= pattern_chunk.offset &&
3048 bits_match[i].offset < pattern_chunk.offset + pattern_chunk.width)
3049 ret.append_bit(bits_match[i]);
3050 }
3051 }
3052
3053 ret.check();
3054 return ret;
3055 }
3056
3057 RTLIL::SigSpec RTLIL::SigSpec::extract(const pool<RTLIL::SigBit> &pattern, const RTLIL::SigSpec *other) const
3058 {
3059 if (other)
3060 cover("kernel.rtlil.sigspec.extract_other");
3061 else
3062 cover("kernel.rtlil.sigspec.extract");
3063
3064 log_assert(other == NULL || width_ == other->width_);
3065
3066 std::vector<RTLIL::SigBit> bits_match = to_sigbit_vector();
3067 RTLIL::SigSpec ret;
3068
3069 if (other) {
3070 std::vector<RTLIL::SigBit> bits_other = other->to_sigbit_vector();
3071 for (int i = 0; i < width_; i++)
3072 if (bits_match[i].wire && pattern.count(bits_match[i]))
3073 ret.append_bit(bits_other[i]);
3074 } else {
3075 for (int i = 0; i < width_; i++)
3076 if (bits_match[i].wire && pattern.count(bits_match[i]))
3077 ret.append_bit(bits_match[i]);
3078 }
3079
3080 ret.check();
3081 return ret;
3082 }
3083
3084 void RTLIL::SigSpec::replace(int offset, const RTLIL::SigSpec &with)
3085 {
3086 cover("kernel.rtlil.sigspec.replace_pos");
3087
3088 unpack();
3089 with.unpack();
3090
3091 log_assert(offset >= 0);
3092 log_assert(with.width_ >= 0);
3093 log_assert(offset+with.width_ <= width_);
3094
3095 for (int i = 0; i < with.width_; i++)
3096 bits_.at(offset + i) = with.bits_.at(i);
3097
3098 check();
3099 }
3100
3101 void RTLIL::SigSpec::remove_const()
3102 {
3103 if (packed())
3104 {
3105 cover("kernel.rtlil.sigspec.remove_const.packed");
3106
3107 std::vector<RTLIL::SigChunk> new_chunks;
3108 new_chunks.reserve(GetSize(chunks_));
3109
3110 width_ = 0;
3111 for (auto &chunk : chunks_)
3112 if (chunk.wire != NULL) {
3113 new_chunks.push_back(chunk);
3114 width_ += chunk.width;
3115 }
3116
3117 chunks_.swap(new_chunks);
3118 }
3119 else
3120 {
3121 cover("kernel.rtlil.sigspec.remove_const.unpacked");
3122
3123 std::vector<RTLIL::SigBit> new_bits;
3124 new_bits.reserve(width_);
3125
3126 for (auto &bit : bits_)
3127 if (bit.wire != NULL)
3128 new_bits.push_back(bit);
3129
3130 bits_.swap(new_bits);
3131 width_ = bits_.size();
3132 }
3133
3134 check();
3135 }
3136
3137 void RTLIL::SigSpec::remove(int offset, int length)
3138 {
3139 cover("kernel.rtlil.sigspec.remove_pos");
3140
3141 unpack();
3142
3143 log_assert(offset >= 0);
3144 log_assert(length >= 0);
3145 log_assert(offset + length <= width_);
3146
3147 bits_.erase(bits_.begin() + offset, bits_.begin() + offset + length);
3148 width_ = bits_.size();
3149
3150 check();
3151 }
3152
3153 RTLIL::SigSpec RTLIL::SigSpec::extract(int offset, int length) const
3154 {
3155 unpack();
3156 cover("kernel.rtlil.sigspec.extract_pos");
3157 return std::vector<RTLIL::SigBit>(bits_.begin() + offset, bits_.begin() + offset + length);
3158 }
3159
3160 void RTLIL::SigSpec::append(const RTLIL::SigSpec &signal)
3161 {
3162 if (signal.width_ == 0)
3163 return;
3164
3165 if (width_ == 0) {
3166 *this = signal;
3167 return;
3168 }
3169
3170 cover("kernel.rtlil.sigspec.append");
3171
3172 if (packed() != signal.packed()) {
3173 pack();
3174 signal.pack();
3175 }
3176
3177 if (packed())
3178 for (auto &other_c : signal.chunks_)
3179 {
3180 auto &my_last_c = chunks_.back();
3181 if (my_last_c.wire == NULL && other_c.wire == NULL) {
3182 auto &this_data = my_last_c.data;
3183 auto &other_data = other_c.data;
3184 this_data.insert(this_data.end(), other_data.begin(), other_data.end());
3185 my_last_c.width += other_c.width;
3186 } else
3187 if (my_last_c.wire == other_c.wire && my_last_c.offset + my_last_c.width == other_c.offset) {
3188 my_last_c.width += other_c.width;
3189 } else
3190 chunks_.push_back(other_c);
3191 }
3192 else
3193 bits_.insert(bits_.end(), signal.bits_.begin(), signal.bits_.end());
3194
3195 width_ += signal.width_;
3196 check();
3197 }
3198
3199 void RTLIL::SigSpec::append_bit(const RTLIL::SigBit &bit)
3200 {
3201 if (packed())
3202 {
3203 cover("kernel.rtlil.sigspec.append_bit.packed");
3204
3205 if (chunks_.size() == 0)
3206 chunks_.push_back(bit);
3207 else
3208 if (bit.wire == NULL)
3209 if (chunks_.back().wire == NULL) {
3210 chunks_.back().data.push_back(bit.data);
3211 chunks_.back().width++;
3212 } else
3213 chunks_.push_back(bit);
3214 else
3215 if (chunks_.back().wire == bit.wire && chunks_.back().offset + chunks_.back().width == bit.offset)
3216 chunks_.back().width++;
3217 else
3218 chunks_.push_back(bit);
3219 }
3220 else
3221 {
3222 cover("kernel.rtlil.sigspec.append_bit.unpacked");
3223 bits_.push_back(bit);
3224 }
3225
3226 width_++;
3227 check();
3228 }
3229
3230 void RTLIL::SigSpec::extend_u0(int width, bool is_signed)
3231 {
3232 cover("kernel.rtlil.sigspec.extend_u0");
3233
3234 pack();
3235
3236 if (width_ > width)
3237 remove(width, width_ - width);
3238
3239 if (width_ < width) {
3240 RTLIL::SigBit padding = width_ > 0 ? (*this)[width_ - 1] : RTLIL::State::S0;
3241 if (!is_signed)
3242 padding = RTLIL::State::S0;
3243 while (width_ < width)
3244 append(padding);
3245 }
3246
3247 }
3248
3249 RTLIL::SigSpec RTLIL::SigSpec::repeat(int num) const
3250 {
3251 cover("kernel.rtlil.sigspec.repeat");
3252
3253 RTLIL::SigSpec sig;
3254 for (int i = 0; i < num; i++)
3255 sig.append(*this);
3256 return sig;
3257 }
3258
3259 #ifndef NDEBUG
3260 void RTLIL::SigSpec::check() const
3261 {
3262 if (width_ > 64)
3263 {
3264 cover("kernel.rtlil.sigspec.check.skip");
3265 }
3266 else if (packed())
3267 {
3268 cover("kernel.rtlil.sigspec.check.packed");
3269
3270 int w = 0;
3271 for (size_t i = 0; i < chunks_.size(); i++) {
3272 const RTLIL::SigChunk chunk = chunks_[i];
3273 if (chunk.wire == NULL) {
3274 if (i > 0)
3275 log_assert(chunks_[i-1].wire != NULL);
3276 log_assert(chunk.offset == 0);
3277 log_assert(chunk.data.size() == (size_t)chunk.width);
3278 } else {
3279 if (i > 0 && chunks_[i-1].wire == chunk.wire)
3280 log_assert(chunk.offset != chunks_[i-1].offset + chunks_[i-1].width);
3281 log_assert(chunk.offset >= 0);
3282 log_assert(chunk.width >= 0);
3283 log_assert(chunk.offset + chunk.width <= chunk.wire->width);
3284 log_assert(chunk.data.size() == 0);
3285 }
3286 w += chunk.width;
3287 }
3288 log_assert(w == width_);
3289 log_assert(bits_.empty());
3290 }
3291 else
3292 {
3293 cover("kernel.rtlil.sigspec.check.unpacked");
3294
3295 log_assert(width_ == GetSize(bits_));
3296 log_assert(chunks_.empty());
3297 }
3298 }
3299 #endif
3300
3301 bool RTLIL::SigSpec::operator <(const RTLIL::SigSpec &other) const
3302 {
3303 cover("kernel.rtlil.sigspec.comp_lt");
3304
3305 if (this == &other)
3306 return false;
3307
3308 if (width_ != other.width_)
3309 return width_ < other.width_;
3310
3311 pack();
3312 other.pack();
3313
3314 if (chunks_.size() != other.chunks_.size())
3315 return chunks_.size() < other.chunks_.size();
3316
3317 updhash();
3318 other.updhash();
3319
3320 if (hash_ != other.hash_)
3321 return hash_ < other.hash_;
3322
3323 for (size_t i = 0; i < chunks_.size(); i++)
3324 if (chunks_[i] != other.chunks_[i]) {
3325 cover("kernel.rtlil.sigspec.comp_lt.hash_collision");
3326 return chunks_[i] < other.chunks_[i];
3327 }
3328
3329 cover("kernel.rtlil.sigspec.comp_lt.equal");
3330 return false;
3331 }
3332
3333 bool RTLIL::SigSpec::operator ==(const RTLIL::SigSpec &other) const
3334 {
3335 cover("kernel.rtlil.sigspec.comp_eq");
3336
3337 if (this == &other)
3338 return true;
3339
3340 if (width_ != other.width_)
3341 return false;
3342
3343 pack();
3344 other.pack();
3345
3346 if (chunks_.size() != chunks_.size())
3347 return false;
3348
3349 updhash();
3350 other.updhash();
3351
3352 if (hash_ != other.hash_)
3353 return false;
3354
3355 for (size_t i = 0; i < chunks_.size(); i++)
3356 if (chunks_[i] != other.chunks_[i]) {
3357 cover("kernel.rtlil.sigspec.comp_eq.hash_collision");
3358 return false;
3359 }
3360
3361 cover("kernel.rtlil.sigspec.comp_eq.equal");
3362 return true;
3363 }
3364
3365 bool RTLIL::SigSpec::is_wire() const
3366 {
3367 cover("kernel.rtlil.sigspec.is_wire");
3368
3369 pack();
3370 return GetSize(chunks_) == 1 && chunks_[0].wire && chunks_[0].wire->width == width_;
3371 }
3372
3373 bool RTLIL::SigSpec::is_chunk() const
3374 {
3375 cover("kernel.rtlil.sigspec.is_chunk");
3376
3377 pack();
3378 return GetSize(chunks_) == 1;
3379 }
3380
3381 bool RTLIL::SigSpec::is_fully_const() const
3382 {
3383 cover("kernel.rtlil.sigspec.is_fully_const");
3384
3385 pack();
3386 for (auto it = chunks_.begin(); it != chunks_.end(); it++)
3387 if (it->width > 0 && it->wire != NULL)
3388 return false;
3389 return true;
3390 }
3391
3392 bool RTLIL::SigSpec::is_fully_zero() const
3393 {
3394 cover("kernel.rtlil.sigspec.is_fully_zero");
3395
3396 pack();
3397 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
3398 if (it->width > 0 && it->wire != NULL)
3399 return false;
3400 for (size_t i = 0; i < it->data.size(); i++)
3401 if (it->data[i] != RTLIL::State::S0)
3402 return false;
3403 }
3404 return true;
3405 }
3406
3407 bool RTLIL::SigSpec::is_fully_ones() const
3408 {
3409 cover("kernel.rtlil.sigspec.is_fully_ones");
3410
3411 pack();
3412 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
3413 if (it->width > 0 && it->wire != NULL)
3414 return false;
3415 for (size_t i = 0; i < it->data.size(); i++)
3416 if (it->data[i] != RTLIL::State::S1)
3417 return false;
3418 }
3419 return true;
3420 }
3421
3422 bool RTLIL::SigSpec::is_fully_def() const
3423 {
3424 cover("kernel.rtlil.sigspec.is_fully_def");
3425
3426 pack();
3427 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
3428 if (it->width > 0 && it->wire != NULL)
3429 return false;
3430 for (size_t i = 0; i < it->data.size(); i++)
3431 if (it->data[i] != RTLIL::State::S0 && it->data[i] != RTLIL::State::S1)
3432 return false;
3433 }
3434 return true;
3435 }
3436
3437 bool RTLIL::SigSpec::is_fully_undef() const
3438 {
3439 cover("kernel.rtlil.sigspec.is_fully_undef");
3440
3441 pack();
3442 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
3443 if (it->width > 0 && it->wire != NULL)
3444 return false;
3445 for (size_t i = 0; i < it->data.size(); i++)
3446 if (it->data[i] != RTLIL::State::Sx && it->data[i] != RTLIL::State::Sz)
3447 return false;
3448 }
3449 return true;
3450 }
3451
3452 bool RTLIL::SigSpec::has_const() const
3453 {
3454 cover("kernel.rtlil.sigspec.has_const");
3455
3456 pack();
3457 for (auto it = chunks_.begin(); it != chunks_.end(); it++)
3458 if (it->width > 0 && it->wire == NULL)
3459 return true;
3460 return false;
3461 }
3462
3463 bool RTLIL::SigSpec::has_marked_bits() const
3464 {
3465 cover("kernel.rtlil.sigspec.has_marked_bits");
3466
3467 pack();
3468 for (auto it = chunks_.begin(); it != chunks_.end(); it++)
3469 if (it->width > 0 && it->wire == NULL) {
3470 for (size_t i = 0; i < it->data.size(); i++)
3471 if (it->data[i] == RTLIL::State::Sm)
3472 return true;
3473 }
3474 return false;
3475 }
3476
3477 bool RTLIL::SigSpec::as_bool() const
3478 {
3479 cover("kernel.rtlil.sigspec.as_bool");
3480
3481 pack();
3482 log_assert(is_fully_const() && GetSize(chunks_) <= 1);
3483 if (width_)
3484 return RTLIL::Const(chunks_[0].data).as_bool();
3485 return false;
3486 }
3487
3488 int RTLIL::SigSpec::as_int(bool is_signed) const
3489 {
3490 cover("kernel.rtlil.sigspec.as_int");
3491
3492 pack();
3493 log_assert(is_fully_const() && GetSize(chunks_) <= 1);
3494 if (width_)
3495 return RTLIL::Const(chunks_[0].data).as_int(is_signed);
3496 return 0;
3497 }
3498
3499 std::string RTLIL::SigSpec::as_string() const
3500 {
3501 cover("kernel.rtlil.sigspec.as_string");
3502
3503 pack();
3504 std::string str;
3505 for (size_t i = chunks_.size(); i > 0; i--) {
3506 const RTLIL::SigChunk &chunk = chunks_[i-1];
3507 if (chunk.wire != NULL)
3508 for (int j = 0; j < chunk.width; j++)
3509 str += "?";
3510 else
3511 str += RTLIL::Const(chunk.data).as_string();
3512 }
3513 return str;
3514 }
3515
3516 RTLIL::Const RTLIL::SigSpec::as_const() const
3517 {
3518 cover("kernel.rtlil.sigspec.as_const");
3519
3520 pack();
3521 log_assert(is_fully_const() && GetSize(chunks_) <= 1);
3522 if (width_)
3523 return chunks_[0].data;
3524 return RTLIL::Const();
3525 }
3526
3527 RTLIL::Wire *RTLIL::SigSpec::as_wire() const
3528 {
3529 cover("kernel.rtlil.sigspec.as_wire");
3530
3531 pack();
3532 log_assert(is_wire());
3533 return chunks_[0].wire;
3534 }
3535
3536 RTLIL::SigChunk RTLIL::SigSpec::as_chunk() const
3537 {
3538 cover("kernel.rtlil.sigspec.as_chunk");
3539
3540 pack();
3541 log_assert(is_chunk());
3542 return chunks_[0];
3543 }
3544
3545 RTLIL::SigBit RTLIL::SigSpec::as_bit() const
3546 {
3547 cover("kernel.rtlil.sigspec.as_bit");
3548
3549 log_assert(width_ == 1);
3550 if (packed())
3551 return RTLIL::SigBit(*chunks_.begin());
3552 else
3553 return bits_[0];
3554 }
3555
3556 bool RTLIL::SigSpec::match(std::string pattern) const
3557 {
3558 cover("kernel.rtlil.sigspec.match");
3559
3560 pack();
3561 std::string str = as_string();
3562 log_assert(pattern.size() == str.size());
3563
3564 for (size_t i = 0; i < pattern.size(); i++) {
3565 if (pattern[i] == ' ')
3566 continue;
3567 if (pattern[i] == '*') {
3568 if (str[i] != 'z' && str[i] != 'x')
3569 return false;
3570 continue;
3571 }
3572 if (pattern[i] != str[i])
3573 return false;
3574 }
3575
3576 return true;
3577 }
3578
3579 std::set<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_set() const
3580 {
3581 cover("kernel.rtlil.sigspec.to_sigbit_set");
3582
3583 pack();
3584 std::set<RTLIL::SigBit> sigbits;
3585 for (auto &c : chunks_)
3586 for (int i = 0; i < c.width; i++)
3587 sigbits.insert(RTLIL::SigBit(c, i));
3588 return sigbits;
3589 }
3590
3591 pool<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_pool() const
3592 {
3593 cover("kernel.rtlil.sigspec.to_sigbit_pool");
3594
3595 pack();
3596 pool<RTLIL::SigBit> sigbits;
3597 for (auto &c : chunks_)
3598 for (int i = 0; i < c.width; i++)
3599 sigbits.insert(RTLIL::SigBit(c, i));
3600 return sigbits;
3601 }
3602
3603 std::vector<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_vector() const
3604 {
3605 cover("kernel.rtlil.sigspec.to_sigbit_vector");
3606
3607 unpack();
3608 return bits_;
3609 }
3610
3611 std::map<RTLIL::SigBit, RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_map(const RTLIL::SigSpec &other) const
3612 {
3613 cover("kernel.rtlil.sigspec.to_sigbit_map");
3614
3615 unpack();
3616 other.unpack();
3617
3618 log_assert(width_ == other.width_);
3619
3620 std::map<RTLIL::SigBit, RTLIL::SigBit> new_map;
3621 for (int i = 0; i < width_; i++)
3622 new_map[bits_[i]] = other.bits_[i];
3623
3624 return new_map;
3625 }
3626
3627 dict<RTLIL::SigBit, RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_dict(const RTLIL::SigSpec &other) const
3628 {
3629 cover("kernel.rtlil.sigspec.to_sigbit_dict");
3630
3631 unpack();
3632 other.unpack();
3633
3634 log_assert(width_ == other.width_);
3635
3636 dict<RTLIL::SigBit, RTLIL::SigBit> new_map;
3637 for (int i = 0; i < width_; i++)
3638 new_map[bits_[i]] = other.bits_[i];
3639
3640 return new_map;
3641 }
3642
3643 static void sigspec_parse_split(std::vector<std::string> &tokens, const std::string &text, char sep)
3644 {
3645 size_t start = 0, end = 0;
3646 while ((end = text.find(sep, start)) != std::string::npos) {
3647 tokens.push_back(text.substr(start, end - start));
3648 start = end + 1;
3649 }
3650 tokens.push_back(text.substr(start));
3651 }
3652
3653 static int sigspec_parse_get_dummy_line_num()
3654 {
3655 return 0;
3656 }
3657
3658 bool RTLIL::SigSpec::parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str)
3659 {
3660 cover("kernel.rtlil.sigspec.parse");
3661
3662 AST::current_filename = "input";
3663 AST::use_internal_line_num();
3664 AST::set_line_num(0);
3665
3666 std::vector<std::string> tokens;
3667 sigspec_parse_split(tokens, str, ',');
3668
3669 sig = RTLIL::SigSpec();
3670 for (int tokidx = int(tokens.size())-1; tokidx >= 0; tokidx--)
3671 {
3672 std::string netname = tokens[tokidx];
3673 std::string indices;
3674
3675 if (netname.size() == 0)
3676 continue;
3677
3678 if (('0' <= netname[0] && netname[0] <= '9') || netname[0] == '\'') {
3679 cover("kernel.rtlil.sigspec.parse.const");
3680 AST::get_line_num = sigspec_parse_get_dummy_line_num;
3681 AST::AstNode *ast = VERILOG_FRONTEND::const2ast(netname);
3682 if (ast == NULL)
3683 return false;
3684 sig.append(RTLIL::Const(ast->bits));
3685 delete ast;
3686 continue;
3687 }
3688
3689 if (module == NULL)
3690 return false;
3691
3692 cover("kernel.rtlil.sigspec.parse.net");
3693
3694 if (netname[0] != '$' && netname[0] != '\\')
3695 netname = "\\" + netname;
3696
3697 if (module->wires_.count(netname) == 0) {
3698 size_t indices_pos = netname.size()-1;
3699 if (indices_pos > 2 && netname[indices_pos] == ']')
3700 {
3701 indices_pos--;
3702 while (indices_pos > 0 && ('0' <= netname[indices_pos] && netname[indices_pos] <= '9')) indices_pos--;
3703 if (indices_pos > 0 && netname[indices_pos] == ':') {
3704 indices_pos--;
3705 while (indices_pos > 0 && ('0' <= netname[indices_pos] && netname[indices_pos] <= '9')) indices_pos--;
3706 }
3707 if (indices_pos > 0 && netname[indices_pos] == '[') {
3708 indices = netname.substr(indices_pos);
3709 netname = netname.substr(0, indices_pos);
3710 }
3711 }
3712 }
3713
3714 if (module->wires_.count(netname) == 0)
3715 return false;
3716
3717 RTLIL::Wire *wire = module->wires_.at(netname);
3718 if (!indices.empty()) {
3719 std::vector<std::string> index_tokens;
3720 sigspec_parse_split(index_tokens, indices.substr(1, indices.size()-2), ':');
3721 if (index_tokens.size() == 1) {
3722 cover("kernel.rtlil.sigspec.parse.bit_sel");
3723 int a = atoi(index_tokens.at(0).c_str());
3724 if (a < 0 || a >= wire->width)
3725 return false;
3726 sig.append(RTLIL::SigSpec(wire, a));
3727 } else {
3728 cover("kernel.rtlil.sigspec.parse.part_sel");
3729 int a = atoi(index_tokens.at(0).c_str());
3730 int b = atoi(index_tokens.at(1).c_str());
3731 if (a > b) {
3732 int tmp = a;
3733 a = b, b = tmp;
3734 }
3735 if (a < 0 || a >= wire->width)
3736 return false;
3737 if (b < 0 || b >= wire->width)
3738 return false;
3739 sig.append(RTLIL::SigSpec(wire, a, b-a+1));
3740 }
3741 } else
3742 sig.append(wire);
3743 }
3744
3745 return true;
3746 }
3747
3748 bool RTLIL::SigSpec::parse_sel(RTLIL::SigSpec &sig, RTLIL::Design *design, RTLIL::Module *module, std::string str)
3749 {
3750 if (str.empty() || str[0] != '@')
3751 return parse(sig, module, str);
3752
3753 cover("kernel.rtlil.sigspec.parse.sel");
3754
3755 str = RTLIL::escape_id(str.substr(1));
3756 if (design->selection_vars.count(str) == 0)
3757 return false;
3758
3759 sig = RTLIL::SigSpec();
3760 RTLIL::Selection &sel = design->selection_vars.at(str);
3761 for (auto &it : module->wires_)
3762 if (sel.selected_member(module->name, it.first))
3763 sig.append(it.second);
3764
3765 return true;
3766 }
3767
3768 bool RTLIL::SigSpec::parse_rhs(const RTLIL::SigSpec &lhs, RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str)
3769 {
3770 if (str == "0") {
3771 cover("kernel.rtlil.sigspec.parse.rhs_zeros");
3772 sig = RTLIL::SigSpec(RTLIL::State::S0, lhs.width_);
3773 return true;
3774 }
3775
3776 if (str == "~0") {
3777 cover("kernel.rtlil.sigspec.parse.rhs_ones");
3778 sig = RTLIL::SigSpec(RTLIL::State::S1, lhs.width_);
3779 return true;
3780 }
3781
3782 if (lhs.chunks_.size() == 1) {
3783 char *p = (char*)str.c_str(), *endptr;
3784 long int val = strtol(p, &endptr, 10);
3785 if (endptr && endptr != p && *endptr == 0) {
3786 sig = RTLIL::SigSpec(val, lhs.width_);
3787 cover("kernel.rtlil.sigspec.parse.rhs_dec");
3788 return true;
3789 }
3790 }
3791
3792 return parse(sig, module, str);
3793 }
3794
3795 RTLIL::CaseRule::~CaseRule()
3796 {
3797 for (auto it = switches.begin(); it != switches.end(); it++)
3798 delete *it;
3799 }
3800
3801 bool RTLIL::CaseRule::empty() const
3802 {
3803 return actions.empty() && switches.empty();
3804 }
3805
3806 RTLIL::CaseRule *RTLIL::CaseRule::clone() const
3807 {
3808 RTLIL::CaseRule *new_caserule = new RTLIL::CaseRule;
3809 new_caserule->compare = compare;
3810 new_caserule->actions = actions;
3811 for (auto &it : switches)
3812 new_caserule->switches.push_back(it->clone());
3813 return new_caserule;
3814 }
3815
3816 RTLIL::SwitchRule::~SwitchRule()
3817 {
3818 for (auto it = cases.begin(); it != cases.end(); it++)
3819 delete *it;
3820 }
3821
3822 bool RTLIL::SwitchRule::empty() const
3823 {
3824 return cases.empty();
3825 }
3826
3827 RTLIL::SwitchRule *RTLIL::SwitchRule::clone() const
3828 {
3829 RTLIL::SwitchRule *new_switchrule = new RTLIL::SwitchRule;
3830 new_switchrule->signal = signal;
3831 new_switchrule->attributes = attributes;
3832 for (auto &it : cases)
3833 new_switchrule->cases.push_back(it->clone());
3834 return new_switchrule;
3835
3836 }
3837
3838 RTLIL::SyncRule *RTLIL::SyncRule::clone() const
3839 {
3840 RTLIL::SyncRule *new_syncrule = new RTLIL::SyncRule;
3841 new_syncrule->type = type;
3842 new_syncrule->signal = signal;
3843 new_syncrule->actions = actions;
3844 return new_syncrule;
3845 }
3846
3847 RTLIL::Process::~Process()
3848 {
3849 for (auto it = syncs.begin(); it != syncs.end(); it++)
3850 delete *it;
3851 }
3852
3853 RTLIL::Process *RTLIL::Process::clone() const
3854 {
3855 RTLIL::Process *new_proc = new RTLIL::Process;
3856
3857 new_proc->name = name;
3858 new_proc->attributes = attributes;
3859
3860 RTLIL::CaseRule *rc_ptr = root_case.clone();
3861 new_proc->root_case = *rc_ptr;
3862 rc_ptr->switches.clear();
3863 delete rc_ptr;
3864
3865 for (auto &it : syncs)
3866 new_proc->syncs.push_back(it->clone());
3867
3868 return new_proc;
3869 }
3870
3871 YOSYS_NAMESPACE_END
3872