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Fixed monitor notifications for removed cell
[yosys.git] / kernel / rtlil.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 #include "kernel/yosys.h"
21 #include "kernel/macc.h"
22 #include "frontends/verilog/verilog_frontend.h"
23 #include "backends/ilang/ilang_backend.h"
24
25 #include <string.h>
26 #include <algorithm>
27
28 YOSYS_NAMESPACE_BEGIN
29
30 std::vector<int> RTLIL::IdString::global_refcount_storage_;
31 std::vector<char*> RTLIL::IdString::global_id_storage_;
32 std::map<char*, int, RTLIL::IdString::char_ptr_cmp> RTLIL::IdString::global_id_index_;
33 std::vector<int> RTLIL::IdString::global_free_idx_list_;
34
35 RTLIL::Const::Const()
36 {
37 flags = RTLIL::CONST_FLAG_NONE;
38 }
39
40 RTLIL::Const::Const(std::string str)
41 {
42 flags = RTLIL::CONST_FLAG_STRING;
43 for (int i = str.size()-1; i >= 0; i--) {
44 unsigned char ch = str[i];
45 for (int j = 0; j < 8; j++) {
46 bits.push_back((ch & 1) != 0 ? RTLIL::S1 : RTLIL::S0);
47 ch = ch >> 1;
48 }
49 }
50 }
51
52 RTLIL::Const::Const(int val, int width)
53 {
54 flags = RTLIL::CONST_FLAG_NONE;
55 for (int i = 0; i < width; i++) {
56 bits.push_back((val & 1) != 0 ? RTLIL::S1 : RTLIL::S0);
57 val = val >> 1;
58 }
59 }
60
61 RTLIL::Const::Const(RTLIL::State bit, int width)
62 {
63 flags = RTLIL::CONST_FLAG_NONE;
64 for (int i = 0; i < width; i++)
65 bits.push_back(bit);
66 }
67
68 bool RTLIL::Const::operator <(const RTLIL::Const &other) const
69 {
70 if (bits.size() != other.bits.size())
71 return bits.size() < other.bits.size();
72 for (size_t i = 0; i < bits.size(); i++)
73 if (bits[i] != other.bits[i])
74 return bits[i] < other.bits[i];
75 return false;
76 }
77
78 bool RTLIL::Const::operator ==(const RTLIL::Const &other) const
79 {
80 return bits == other.bits;
81 }
82
83 bool RTLIL::Const::operator !=(const RTLIL::Const &other) const
84 {
85 return bits != other.bits;
86 }
87
88 bool RTLIL::Const::as_bool() const
89 {
90 for (size_t i = 0; i < bits.size(); i++)
91 if (bits[i] == RTLIL::S1)
92 return true;
93 return false;
94 }
95
96 int RTLIL::Const::as_int(bool is_signed) const
97 {
98 int32_t ret = 0;
99 for (size_t i = 0; i < bits.size() && i < 32; i++)
100 if (bits[i] == RTLIL::S1)
101 ret |= 1 << i;
102 if (is_signed && bits.back() == RTLIL::S1)
103 for (size_t i = bits.size(); i < 32; i++)
104 ret |= 1 << i;
105 return ret;
106 }
107
108 std::string RTLIL::Const::as_string() const
109 {
110 std::string ret;
111 for (size_t i = bits.size(); i > 0; i--)
112 switch (bits[i-1]) {
113 case S0: ret += "0"; break;
114 case S1: ret += "1"; break;
115 case Sx: ret += "x"; break;
116 case Sz: ret += "z"; break;
117 case Sa: ret += "-"; break;
118 case Sm: ret += "m"; break;
119 }
120 return ret;
121 }
122
123 std::string RTLIL::Const::decode_string() const
124 {
125 std::string string;
126 std::vector <char> string_chars;
127 for (int i = 0; i < int (bits.size()); i += 8) {
128 char ch = 0;
129 for (int j = 0; j < 8 && i + j < int (bits.size()); j++)
130 if (bits[i + j] == RTLIL::State::S1)
131 ch |= 1 << j;
132 if (ch != 0)
133 string_chars.push_back(ch);
134 }
135 for (int i = int (string_chars.size()) - 1; i >= 0; i--)
136 string += string_chars[i];
137 return string;
138 }
139
140 bool RTLIL::Selection::selected_module(RTLIL::IdString mod_name) const
141 {
142 if (full_selection)
143 return true;
144 if (selected_modules.count(mod_name) > 0)
145 return true;
146 if (selected_members.count(mod_name) > 0)
147 return true;
148 return false;
149 }
150
151 bool RTLIL::Selection::selected_whole_module(RTLIL::IdString mod_name) const
152 {
153 if (full_selection)
154 return true;
155 if (selected_modules.count(mod_name) > 0)
156 return true;
157 return false;
158 }
159
160 bool RTLIL::Selection::selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const
161 {
162 if (full_selection)
163 return true;
164 if (selected_modules.count(mod_name) > 0)
165 return true;
166 if (selected_members.count(mod_name) > 0)
167 if (selected_members.at(mod_name).count(memb_name) > 0)
168 return true;
169 return false;
170 }
171
172 void RTLIL::Selection::optimize(RTLIL::Design *design)
173 {
174 if (full_selection) {
175 selected_modules.clear();
176 selected_members.clear();
177 return;
178 }
179
180 std::vector<RTLIL::IdString> del_list, add_list;
181
182 del_list.clear();
183 for (auto mod_name : selected_modules) {
184 if (design->modules_.count(mod_name) == 0)
185 del_list.push_back(mod_name);
186 selected_members.erase(mod_name);
187 }
188 for (auto mod_name : del_list)
189 selected_modules.erase(mod_name);
190
191 del_list.clear();
192 for (auto &it : selected_members)
193 if (design->modules_.count(it.first) == 0)
194 del_list.push_back(it.first);
195 for (auto mod_name : del_list)
196 selected_members.erase(mod_name);
197
198 for (auto &it : selected_members) {
199 del_list.clear();
200 for (auto memb_name : it.second)
201 if (design->modules_[it.first]->count_id(memb_name) == 0)
202 del_list.push_back(memb_name);
203 for (auto memb_name : del_list)
204 it.second.erase(memb_name);
205 }
206
207 del_list.clear();
208 add_list.clear();
209 for (auto &it : selected_members)
210 if (it.second.size() == 0)
211 del_list.push_back(it.first);
212 else if (it.second.size() == design->modules_[it.first]->wires_.size() + design->modules_[it.first]->memories.size() +
213 design->modules_[it.first]->cells_.size() + design->modules_[it.first]->processes.size())
214 add_list.push_back(it.first);
215 for (auto mod_name : del_list)
216 selected_members.erase(mod_name);
217 for (auto mod_name : add_list) {
218 selected_members.erase(mod_name);
219 selected_modules.insert(mod_name);
220 }
221
222 if (selected_modules.size() == design->modules_.size()) {
223 full_selection = true;
224 selected_modules.clear();
225 selected_members.clear();
226 }
227 }
228
229 RTLIL::Design::Design()
230 {
231 refcount_modules_ = 0;
232 selection_stack.push_back(RTLIL::Selection());
233 }
234
235 RTLIL::Design::~Design()
236 {
237 for (auto it = modules_.begin(); it != modules_.end(); it++)
238 delete it->second;
239 }
240
241 RTLIL::ObjRange<RTLIL::Module*> RTLIL::Design::modules()
242 {
243 return RTLIL::ObjRange<RTLIL::Module*>(&modules_, &refcount_modules_);
244 }
245
246 RTLIL::Module *RTLIL::Design::module(RTLIL::IdString name)
247 {
248 return modules_.count(name) ? modules_.at(name) : NULL;
249 }
250
251 void RTLIL::Design::add(RTLIL::Module *module)
252 {
253 log_assert(modules_.count(module->name) == 0);
254 log_assert(refcount_modules_ == 0);
255 modules_[module->name] = module;
256 module->design = this;
257
258 for (auto mon : monitors)
259 mon->notify_module_add(module);
260 }
261
262 RTLIL::Module *RTLIL::Design::addModule(RTLIL::IdString name)
263 {
264 log_assert(modules_.count(name) == 0);
265 log_assert(refcount_modules_ == 0);
266
267 RTLIL::Module *module = new RTLIL::Module;
268 modules_[name] = module;
269 module->design = this;
270 module->name = name;
271
272 for (auto mon : monitors)
273 mon->notify_module_add(module);
274
275 return module;
276 }
277
278 void RTLIL::Design::scratchpad_unset(std::string varname)
279 {
280 scratchpad.erase(varname);
281 }
282
283 void RTLIL::Design::scratchpad_set_int(std::string varname, int value)
284 {
285 scratchpad[varname] = stringf("%d", value);
286 }
287
288 void RTLIL::Design::scratchpad_set_bool(std::string varname, bool value)
289 {
290 scratchpad[varname] = value ? "true" : "false";
291 }
292
293 void RTLIL::Design::scratchpad_set_string(std::string varname, std::string value)
294 {
295 scratchpad[varname] = value;
296 }
297
298 int RTLIL::Design::scratchpad_get_int(std::string varname, int default_value) const
299 {
300 if (scratchpad.count(varname) == 0)
301 return default_value;
302
303 std::string str = scratchpad.at(varname);
304
305 if (str == "0" || str == "false")
306 return 0;
307
308 if (str == "1" || str == "true")
309 return 1;
310
311 char *endptr = nullptr;
312 long int parsed_value = strtol(str.c_str(), &endptr, 10);
313 return *endptr ? default_value : parsed_value;
314 }
315
316 bool RTLIL::Design::scratchpad_get_bool(std::string varname, bool default_value) const
317 {
318 if (scratchpad.count(varname) == 0)
319 return default_value;
320
321 std::string str = scratchpad.at(varname);
322
323 if (str == "0" || str == "false")
324 return false;
325
326 if (str == "1" || str == "true")
327 return true;
328
329 return default_value;
330 }
331
332 std::string RTLIL::Design::scratchpad_get_string(std::string varname, std::string default_value) const
333 {
334 if (scratchpad.count(varname) == 0)
335 return default_value;
336 return scratchpad.at(varname);
337 }
338
339 void RTLIL::Design::remove(RTLIL::Module *module)
340 {
341 for (auto mon : monitors)
342 mon->notify_module_del(module);
343
344 log_assert(modules_.at(module->name) == module);
345 modules_.erase(module->name);
346 delete module;
347 }
348
349 void RTLIL::Design::check()
350 {
351 #ifndef NDEBUG
352 for (auto &it : modules_) {
353 log_assert(this == it.second->design);
354 log_assert(it.first == it.second->name);
355 log_assert(!it.first.empty());
356 it.second->check();
357 }
358 #endif
359 }
360
361 void RTLIL::Design::optimize()
362 {
363 for (auto &it : modules_)
364 it.second->optimize();
365 for (auto &it : selection_stack)
366 it.optimize(this);
367 for (auto &it : selection_vars)
368 it.second.optimize(this);
369 }
370
371 bool RTLIL::Design::selected_module(RTLIL::IdString mod_name) const
372 {
373 if (!selected_active_module.empty() && mod_name != selected_active_module)
374 return false;
375 if (selection_stack.size() == 0)
376 return true;
377 return selection_stack.back().selected_module(mod_name);
378 }
379
380 bool RTLIL::Design::selected_whole_module(RTLIL::IdString mod_name) const
381 {
382 if (!selected_active_module.empty() && mod_name != selected_active_module)
383 return false;
384 if (selection_stack.size() == 0)
385 return true;
386 return selection_stack.back().selected_whole_module(mod_name);
387 }
388
389 bool RTLIL::Design::selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const
390 {
391 if (!selected_active_module.empty() && mod_name != selected_active_module)
392 return false;
393 if (selection_stack.size() == 0)
394 return true;
395 return selection_stack.back().selected_member(mod_name, memb_name);
396 }
397
398 bool RTLIL::Design::selected_module(RTLIL::Module *mod) const
399 {
400 return selected_module(mod->name);
401 }
402
403 bool RTLIL::Design::selected_whole_module(RTLIL::Module *mod) const
404 {
405 return selected_whole_module(mod->name);
406 }
407
408 std::vector<RTLIL::Module*> RTLIL::Design::selected_modules() const
409 {
410 std::vector<RTLIL::Module*> result;
411 result.reserve(modules_.size());
412 for (auto &it : modules_)
413 if (selected_module(it.first))
414 result.push_back(it.second);
415 return result;
416 }
417
418 std::vector<RTLIL::Module*> RTLIL::Design::selected_whole_modules() const
419 {
420 std::vector<RTLIL::Module*> result;
421 result.reserve(modules_.size());
422 for (auto &it : modules_)
423 if (selected_whole_module(it.first))
424 result.push_back(it.second);
425 return result;
426 }
427
428 std::vector<RTLIL::Module*> RTLIL::Design::selected_whole_modules_warn() const
429 {
430 std::vector<RTLIL::Module*> result;
431 result.reserve(modules_.size());
432 for (auto &it : modules_)
433 if (selected_whole_module(it.first))
434 result.push_back(it.second);
435 else if (selected_module(it.first))
436 log("Warning: Ignoring partially selected module %s.\n", log_id(it.first));
437 return result;
438 }
439
440 RTLIL::Module::Module()
441 {
442 design = nullptr;
443 refcount_wires_ = 0;
444 refcount_cells_ = 0;
445 }
446
447 RTLIL::Module::~Module()
448 {
449 for (auto it = wires_.begin(); it != wires_.end(); it++)
450 delete it->second;
451 for (auto it = memories.begin(); it != memories.end(); it++)
452 delete it->second;
453 for (auto it = cells_.begin(); it != cells_.end(); it++)
454 delete it->second;
455 for (auto it = processes.begin(); it != processes.end(); it++)
456 delete it->second;
457 }
458
459 RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, std::map<RTLIL::IdString, RTLIL::Const>)
460 {
461 log_error("Module `%s' is used with parameters but is not parametric!\n", id2cstr(name));
462 }
463
464 size_t RTLIL::Module::count_id(RTLIL::IdString id)
465 {
466 return wires_.count(id) + memories.count(id) + cells_.count(id) + processes.count(id);
467 }
468
469 #ifndef NDEBUG
470 namespace {
471 struct InternalCellChecker
472 {
473 RTLIL::Module *module;
474 RTLIL::Cell *cell;
475 std::set<RTLIL::IdString> expected_params, expected_ports;
476
477 InternalCellChecker(RTLIL::Module *module, RTLIL::Cell *cell) : module(module), cell(cell) { }
478
479 void error(int linenr)
480 {
481 std::stringstream buf;
482 ILANG_BACKEND::dump_cell(buf, " ", cell);
483
484 log_error("Found error in internal cell %s%s%s (%s) at %s:%d:\n%s",
485 module ? module->name.c_str() : "", module ? "." : "",
486 cell->name.c_str(), cell->type.c_str(), __FILE__, linenr, buf.str().c_str());
487 }
488
489 int param(const char *name)
490 {
491 if (cell->parameters.count(name) == 0)
492 error(__LINE__);
493 expected_params.insert(name);
494 return cell->parameters.at(name).as_int();
495 }
496
497 int param_bool(const char *name)
498 {
499 int v = param(name);
500 if (cell->parameters.at(name).bits.size() > 32)
501 error(__LINE__);
502 if (v != 0 && v != 1)
503 error(__LINE__);
504 return v;
505 }
506
507 void param_bits(const char *name, int width)
508 {
509 param(name);
510 if (int(cell->parameters.at(name).bits.size()) != width)
511 error(__LINE__);
512 }
513
514 void port(const char *name, int width)
515 {
516 if (!cell->hasPort(name))
517 error(__LINE__);
518 if (cell->getPort(name).size() != width)
519 error(__LINE__);
520 expected_ports.insert(name);
521 }
522
523 void check_expected(bool check_matched_sign = true)
524 {
525 for (auto &para : cell->parameters)
526 if (expected_params.count(para.first) == 0)
527 error(__LINE__);
528 for (auto &conn : cell->connections())
529 if (expected_ports.count(conn.first) == 0)
530 error(__LINE__);
531
532 if (expected_params.count("\\A_SIGNED") != 0 && expected_params.count("\\B_SIGNED") && check_matched_sign) {
533 bool a_is_signed = param("\\A_SIGNED") != 0;
534 bool b_is_signed = param("\\B_SIGNED") != 0;
535 if (a_is_signed != b_is_signed)
536 error(__LINE__);
537 }
538 }
539
540 void check_gate(const char *ports)
541 {
542 if (cell->parameters.size() != 0)
543 error(__LINE__);
544
545 for (const char *p = ports; *p; p++) {
546 char portname[3] = { '\\', *p, 0 };
547 if (!cell->hasPort(portname))
548 error(__LINE__);
549 if (cell->getPort(portname).size() != 1)
550 error(__LINE__);
551 }
552
553 for (auto &conn : cell->connections()) {
554 if (conn.first.size() != 2 || conn.first[0] != '\\')
555 error(__LINE__);
556 if (strchr(ports, conn.first[1]) == NULL)
557 error(__LINE__);
558 }
559 }
560
561 void check()
562 {
563 if (cell->type.substr(0, 1) != "$" || cell->type.substr(0, 3) == "$__" || cell->type.substr(0, 8) == "$paramod" ||
564 cell->type.substr(0, 9) == "$verific$" || cell->type.substr(0, 7) == "$array:" || cell->type.substr(0, 8) == "$extern:")
565 return;
566
567 if (cell->type.in("$not", "$pos", "$neg")) {
568 param_bool("\\A_SIGNED");
569 port("\\A", param("\\A_WIDTH"));
570 port("\\Y", param("\\Y_WIDTH"));
571 check_expected();
572 return;
573 }
574
575 if (cell->type.in("$and", "$or", "$xor", "$xnor")) {
576 param_bool("\\A_SIGNED");
577 param_bool("\\B_SIGNED");
578 port("\\A", param("\\A_WIDTH"));
579 port("\\B", param("\\B_WIDTH"));
580 port("\\Y", param("\\Y_WIDTH"));
581 check_expected();
582 return;
583 }
584
585 if (cell->type.in("$reduce_and", "$reduce_or", "$reduce_xor", "$reduce_xnor", "$reduce_bool")) {
586 param_bool("\\A_SIGNED");
587 port("\\A", param("\\A_WIDTH"));
588 port("\\Y", param("\\Y_WIDTH"));
589 check_expected();
590 return;
591 }
592
593 if (cell->type.in("$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx")) {
594 param_bool("\\A_SIGNED");
595 param_bool("\\B_SIGNED");
596 port("\\A", param("\\A_WIDTH"));
597 port("\\B", param("\\B_WIDTH"));
598 port("\\Y", param("\\Y_WIDTH"));
599 check_expected(false);
600 return;
601 }
602
603 if (cell->type.in("$lt", "$le", "$eq", "$ne", "$eqx", "$nex", "$ge", "$gt")) {
604 param_bool("\\A_SIGNED");
605 param_bool("\\B_SIGNED");
606 port("\\A", param("\\A_WIDTH"));
607 port("\\B", param("\\B_WIDTH"));
608 port("\\Y", param("\\Y_WIDTH"));
609 check_expected();
610 return;
611 }
612
613 if (cell->type.in("$add", "$sub", "$mul", "$div", "$mod", "$pow")) {
614 param_bool("\\A_SIGNED");
615 param_bool("\\B_SIGNED");
616 port("\\A", param("\\A_WIDTH"));
617 port("\\B", param("\\B_WIDTH"));
618 port("\\Y", param("\\Y_WIDTH"));
619 check_expected(cell->type != "$pow");
620 return;
621 }
622
623 if (cell->type == "$fa") {
624 port("\\A", param("\\WIDTH"));
625 port("\\B", param("\\WIDTH"));
626 port("\\C", param("\\WIDTH"));
627 port("\\X", param("\\WIDTH"));
628 port("\\Y", param("\\WIDTH"));
629 check_expected();
630 return;
631 }
632
633 if (cell->type == "$lcu") {
634 port("\\P", param("\\WIDTH"));
635 port("\\G", param("\\WIDTH"));
636 port("\\CI", 1);
637 port("\\CO", param("\\WIDTH"));
638 check_expected();
639 return;
640 }
641
642 if (cell->type == "$alu") {
643 param_bool("\\A_SIGNED");
644 param_bool("\\B_SIGNED");
645 port("\\A", param("\\A_WIDTH"));
646 port("\\B", param("\\B_WIDTH"));
647 port("\\CI", 1);
648 port("\\BI", 1);
649 port("\\X", param("\\Y_WIDTH"));
650 port("\\Y", param("\\Y_WIDTH"));
651 port("\\CO", param("\\Y_WIDTH"));
652 check_expected();
653 return;
654 }
655
656 if (cell->type == "$macc") {
657 param("\\CONFIG");
658 param("\\CONFIG_WIDTH");
659 port("\\A", param("\\A_WIDTH"));
660 port("\\B", param("\\B_WIDTH"));
661 port("\\Y", param("\\Y_WIDTH"));
662 check_expected();
663 Macc().from_cell(cell);
664 return;
665 }
666
667 if (cell->type == "$logic_not") {
668 param_bool("\\A_SIGNED");
669 port("\\A", param("\\A_WIDTH"));
670 port("\\Y", param("\\Y_WIDTH"));
671 check_expected();
672 return;
673 }
674
675 if (cell->type == "$logic_and" || cell->type == "$logic_or") {
676 param_bool("\\A_SIGNED");
677 param_bool("\\B_SIGNED");
678 port("\\A", param("\\A_WIDTH"));
679 port("\\B", param("\\B_WIDTH"));
680 port("\\Y", param("\\Y_WIDTH"));
681 check_expected(false);
682 return;
683 }
684
685 if (cell->type == "$slice") {
686 param("\\OFFSET");
687 port("\\A", param("\\A_WIDTH"));
688 port("\\Y", param("\\Y_WIDTH"));
689 if (param("\\OFFSET") + param("\\Y_WIDTH") > param("\\A_WIDTH"))
690 error(__LINE__);
691 check_expected();
692 return;
693 }
694
695 if (cell->type == "$concat") {
696 port("\\A", param("\\A_WIDTH"));
697 port("\\B", param("\\B_WIDTH"));
698 port("\\Y", param("\\A_WIDTH") + param("\\B_WIDTH"));
699 check_expected();
700 return;
701 }
702
703 if (cell->type == "$mux") {
704 port("\\A", param("\\WIDTH"));
705 port("\\B", param("\\WIDTH"));
706 port("\\S", 1);
707 port("\\Y", param("\\WIDTH"));
708 check_expected();
709 return;
710 }
711
712 if (cell->type == "$pmux") {
713 port("\\A", param("\\WIDTH"));
714 port("\\B", param("\\WIDTH") * param("\\S_WIDTH"));
715 port("\\S", param("\\S_WIDTH"));
716 port("\\Y", param("\\WIDTH"));
717 check_expected();
718 return;
719 }
720
721 if (cell->type == "$lut") {
722 param("\\LUT");
723 port("\\A", param("\\WIDTH"));
724 port("\\Y", 1);
725 check_expected();
726 return;
727 }
728
729 if (cell->type == "$sr") {
730 param_bool("\\SET_POLARITY");
731 param_bool("\\CLR_POLARITY");
732 port("\\SET", param("\\WIDTH"));
733 port("\\CLR", param("\\WIDTH"));
734 port("\\Q", param("\\WIDTH"));
735 check_expected();
736 return;
737 }
738
739 if (cell->type == "$dff") {
740 param_bool("\\CLK_POLARITY");
741 port("\\CLK", 1);
742 port("\\D", param("\\WIDTH"));
743 port("\\Q", param("\\WIDTH"));
744 check_expected();
745 return;
746 }
747
748 if (cell->type == "$dffsr") {
749 param_bool("\\CLK_POLARITY");
750 param_bool("\\SET_POLARITY");
751 param_bool("\\CLR_POLARITY");
752 port("\\CLK", 1);
753 port("\\SET", param("\\WIDTH"));
754 port("\\CLR", param("\\WIDTH"));
755 port("\\D", param("\\WIDTH"));
756 port("\\Q", param("\\WIDTH"));
757 check_expected();
758 return;
759 }
760
761 if (cell->type == "$adff") {
762 param_bool("\\CLK_POLARITY");
763 param_bool("\\ARST_POLARITY");
764 param_bits("\\ARST_VALUE", param("\\WIDTH"));
765 port("\\CLK", 1);
766 port("\\ARST", 1);
767 port("\\D", param("\\WIDTH"));
768 port("\\Q", param("\\WIDTH"));
769 check_expected();
770 return;
771 }
772
773 if (cell->type == "$dlatch") {
774 param_bool("\\EN_POLARITY");
775 port("\\EN", 1);
776 port("\\D", param("\\WIDTH"));
777 port("\\Q", param("\\WIDTH"));
778 check_expected();
779 return;
780 }
781
782 if (cell->type == "$dlatchsr") {
783 param_bool("\\EN_POLARITY");
784 param_bool("\\SET_POLARITY");
785 param_bool("\\CLR_POLARITY");
786 port("\\EN", 1);
787 port("\\SET", param("\\WIDTH"));
788 port("\\CLR", param("\\WIDTH"));
789 port("\\D", param("\\WIDTH"));
790 port("\\Q", param("\\WIDTH"));
791 check_expected();
792 return;
793 }
794
795 if (cell->type == "$fsm") {
796 param("\\NAME");
797 param_bool("\\CLK_POLARITY");
798 param_bool("\\ARST_POLARITY");
799 param("\\STATE_BITS");
800 param("\\STATE_NUM");
801 param("\\STATE_NUM_LOG2");
802 param("\\STATE_RST");
803 param_bits("\\STATE_TABLE", param("\\STATE_BITS") * param("\\STATE_NUM"));
804 param("\\TRANS_NUM");
805 param_bits("\\TRANS_TABLE", param("\\TRANS_NUM") * (2*param("\\STATE_NUM_LOG2") + param("\\CTRL_IN_WIDTH") + param("\\CTRL_OUT_WIDTH")));
806 port("\\CLK", 1);
807 port("\\ARST", 1);
808 port("\\CTRL_IN", param("\\CTRL_IN_WIDTH"));
809 port("\\CTRL_OUT", param("\\CTRL_OUT_WIDTH"));
810 check_expected();
811 return;
812 }
813
814 if (cell->type == "$memrd") {
815 param("\\MEMID");
816 param_bool("\\CLK_ENABLE");
817 param_bool("\\CLK_POLARITY");
818 param_bool("\\TRANSPARENT");
819 port("\\CLK", 1);
820 port("\\ADDR", param("\\ABITS"));
821 port("\\DATA", param("\\WIDTH"));
822 check_expected();
823 return;
824 }
825
826 if (cell->type == "$memwr") {
827 param("\\MEMID");
828 param_bool("\\CLK_ENABLE");
829 param_bool("\\CLK_POLARITY");
830 param("\\PRIORITY");
831 port("\\CLK", 1);
832 port("\\EN", param("\\WIDTH"));
833 port("\\ADDR", param("\\ABITS"));
834 port("\\DATA", param("\\WIDTH"));
835 check_expected();
836 return;
837 }
838
839 if (cell->type == "$mem") {
840 param("\\MEMID");
841 param("\\SIZE");
842 param("\\OFFSET");
843 param_bits("\\RD_CLK_ENABLE", param("\\RD_PORTS"));
844 param_bits("\\RD_CLK_POLARITY", param("\\RD_PORTS"));
845 param_bits("\\RD_TRANSPARENT", param("\\RD_PORTS"));
846 param_bits("\\WR_CLK_ENABLE", param("\\WR_PORTS"));
847 param_bits("\\WR_CLK_POLARITY", param("\\WR_PORTS"));
848 port("\\RD_CLK", param("\\RD_PORTS"));
849 port("\\RD_ADDR", param("\\RD_PORTS") * param("\\ABITS"));
850 port("\\RD_DATA", param("\\RD_PORTS") * param("\\WIDTH"));
851 port("\\WR_CLK", param("\\WR_PORTS"));
852 port("\\WR_EN", param("\\WR_PORTS") * param("\\WIDTH"));
853 port("\\WR_ADDR", param("\\WR_PORTS") * param("\\ABITS"));
854 port("\\WR_DATA", param("\\WR_PORTS") * param("\\WIDTH"));
855 check_expected();
856 return;
857 }
858
859 if (cell->type == "$assert") {
860 port("\\A", 1);
861 port("\\EN", 1);
862 check_expected();
863 return;
864 }
865
866 if (cell->type == "$_NOT_") { check_gate("AY"); return; }
867 if (cell->type == "$_AND_") { check_gate("ABY"); return; }
868 if (cell->type == "$_NAND_") { check_gate("ABY"); return; }
869 if (cell->type == "$_OR_") { check_gate("ABY"); return; }
870 if (cell->type == "$_NOR_") { check_gate("ABY"); return; }
871 if (cell->type == "$_XOR_") { check_gate("ABY"); return; }
872 if (cell->type == "$_XNOR_") { check_gate("ABY"); return; }
873 if (cell->type == "$_MUX_") { check_gate("ABSY"); return; }
874 if (cell->type == "$_AOI3_") { check_gate("ABCY"); return; }
875 if (cell->type == "$_OAI3_") { check_gate("ABCY"); return; }
876 if (cell->type == "$_AOI4_") { check_gate("ABCDY"); return; }
877 if (cell->type == "$_OAI4_") { check_gate("ABCDY"); return; }
878
879 if (cell->type == "$_SR_NN_") { check_gate("SRQ"); return; }
880 if (cell->type == "$_SR_NP_") { check_gate("SRQ"); return; }
881 if (cell->type == "$_SR_PN_") { check_gate("SRQ"); return; }
882 if (cell->type == "$_SR_PP_") { check_gate("SRQ"); return; }
883
884 if (cell->type == "$_DFF_N_") { check_gate("DQC"); return; }
885 if (cell->type == "$_DFF_P_") { check_gate("DQC"); return; }
886
887 if (cell->type == "$_DFF_NN0_") { check_gate("DQCR"); return; }
888 if (cell->type == "$_DFF_NN1_") { check_gate("DQCR"); return; }
889 if (cell->type == "$_DFF_NP0_") { check_gate("DQCR"); return; }
890 if (cell->type == "$_DFF_NP1_") { check_gate("DQCR"); return; }
891 if (cell->type == "$_DFF_PN0_") { check_gate("DQCR"); return; }
892 if (cell->type == "$_DFF_PN1_") { check_gate("DQCR"); return; }
893 if (cell->type == "$_DFF_PP0_") { check_gate("DQCR"); return; }
894 if (cell->type == "$_DFF_PP1_") { check_gate("DQCR"); return; }
895
896 if (cell->type == "$_DFFSR_NNN_") { check_gate("CSRDQ"); return; }
897 if (cell->type == "$_DFFSR_NNP_") { check_gate("CSRDQ"); return; }
898 if (cell->type == "$_DFFSR_NPN_") { check_gate("CSRDQ"); return; }
899 if (cell->type == "$_DFFSR_NPP_") { check_gate("CSRDQ"); return; }
900 if (cell->type == "$_DFFSR_PNN_") { check_gate("CSRDQ"); return; }
901 if (cell->type == "$_DFFSR_PNP_") { check_gate("CSRDQ"); return; }
902 if (cell->type == "$_DFFSR_PPN_") { check_gate("CSRDQ"); return; }
903 if (cell->type == "$_DFFSR_PPP_") { check_gate("CSRDQ"); return; }
904
905 if (cell->type == "$_DLATCH_N_") { check_gate("EDQ"); return; }
906 if (cell->type == "$_DLATCH_P_") { check_gate("EDQ"); return; }
907
908 if (cell->type == "$_DLATCHSR_NNN_") { check_gate("ESRDQ"); return; }
909 if (cell->type == "$_DLATCHSR_NNP_") { check_gate("ESRDQ"); return; }
910 if (cell->type == "$_DLATCHSR_NPN_") { check_gate("ESRDQ"); return; }
911 if (cell->type == "$_DLATCHSR_NPP_") { check_gate("ESRDQ"); return; }
912 if (cell->type == "$_DLATCHSR_PNN_") { check_gate("ESRDQ"); return; }
913 if (cell->type == "$_DLATCHSR_PNP_") { check_gate("ESRDQ"); return; }
914 if (cell->type == "$_DLATCHSR_PPN_") { check_gate("ESRDQ"); return; }
915 if (cell->type == "$_DLATCHSR_PPP_") { check_gate("ESRDQ"); return; }
916
917 error(__LINE__);
918 }
919 };
920 }
921 #endif
922
923 void RTLIL::Module::check()
924 {
925 #ifndef NDEBUG
926 std::vector<bool> ports_declared;
927 for (auto &it : wires_) {
928 log_assert(this == it.second->module);
929 log_assert(it.first == it.second->name);
930 log_assert(!it.first.empty());
931 log_assert(it.second->width >= 0);
932 log_assert(it.second->port_id >= 0);
933 for (auto &it2 : it.second->attributes)
934 log_assert(!it2.first.empty());
935 if (it.second->port_id) {
936 log_assert(SIZE(ports) >= it.second->port_id);
937 log_assert(ports.at(it.second->port_id-1) == it.first);
938 log_assert(it.second->port_input || it.second->port_output);
939 if (SIZE(ports_declared) < it.second->port_id)
940 ports_declared.resize(it.second->port_id);
941 log_assert(ports_declared[it.second->port_id-1] == false);
942 ports_declared[it.second->port_id-1] = true;
943 } else
944 log_assert(!it.second->port_input && !it.second->port_output);
945 }
946 for (auto port_declared : ports_declared)
947 log_assert(port_declared == true);
948 log_assert(SIZE(ports) == SIZE(ports_declared));
949
950 for (auto &it : memories) {
951 log_assert(it.first == it.second->name);
952 log_assert(!it.first.empty());
953 log_assert(it.second->width >= 0);
954 log_assert(it.second->size >= 0);
955 for (auto &it2 : it.second->attributes)
956 log_assert(!it2.first.empty());
957 }
958
959 for (auto &it : cells_) {
960 log_assert(this == it.second->module);
961 log_assert(it.first == it.second->name);
962 log_assert(!it.first.empty());
963 log_assert(!it.second->type.empty());
964 for (auto &it2 : it.second->connections()) {
965 log_assert(!it2.first.empty());
966 it2.second.check();
967 }
968 for (auto &it2 : it.second->attributes)
969 log_assert(!it2.first.empty());
970 for (auto &it2 : it.second->parameters)
971 log_assert(!it2.first.empty());
972 InternalCellChecker checker(this, it.second);
973 checker.check();
974 }
975
976 for (auto &it : processes) {
977 log_assert(it.first == it.second->name);
978 log_assert(!it.first.empty());
979 // FIXME: More checks here..
980 }
981
982 for (auto &it : connections_) {
983 log_assert(it.first.size() == it.second.size());
984 it.first.check();
985 it.second.check();
986 }
987
988 for (auto &it : attributes)
989 log_assert(!it.first.empty());
990 #endif
991 }
992
993 void RTLIL::Module::optimize()
994 {
995 }
996
997 void RTLIL::Module::cloneInto(RTLIL::Module *new_mod) const
998 {
999 log_assert(new_mod->refcount_wires_ == 0);
1000 log_assert(new_mod->refcount_cells_ == 0);
1001
1002 new_mod->connections_ = connections_;
1003 new_mod->attributes = attributes;
1004
1005 for (auto &it : wires_)
1006 new_mod->addWire(it.first, it.second);
1007
1008 for (auto &it : memories)
1009 new_mod->memories[it.first] = new RTLIL::Memory(*it.second);
1010
1011 for (auto &it : cells_)
1012 new_mod->addCell(it.first, it.second);
1013
1014 for (auto &it : processes)
1015 new_mod->processes[it.first] = it.second->clone();
1016
1017 struct RewriteSigSpecWorker
1018 {
1019 RTLIL::Module *mod;
1020 void operator()(RTLIL::SigSpec &sig)
1021 {
1022 std::vector<RTLIL::SigChunk> chunks = sig.chunks();
1023 for (auto &c : chunks)
1024 if (c.wire != NULL)
1025 c.wire = mod->wires_.at(c.wire->name);
1026 sig = chunks;
1027 }
1028 };
1029
1030 RewriteSigSpecWorker rewriteSigSpecWorker;
1031 rewriteSigSpecWorker.mod = new_mod;
1032 new_mod->rewrite_sigspecs(rewriteSigSpecWorker);
1033 new_mod->fixup_ports();
1034 }
1035
1036 RTLIL::Module *RTLIL::Module::clone() const
1037 {
1038 RTLIL::Module *new_mod = new RTLIL::Module;
1039 new_mod->name = name;
1040 cloneInto(new_mod);
1041 return new_mod;
1042 }
1043
1044 bool RTLIL::Module::has_memories() const
1045 {
1046 return !memories.empty();
1047 }
1048
1049 bool RTLIL::Module::has_processes() const
1050 {
1051 return !processes.empty();
1052 }
1053
1054 bool RTLIL::Module::has_memories_warn() const
1055 {
1056 if (!memories.empty())
1057 log("Warning: Ignoring module %s because it contains memories (run 'memory' command first).\n", log_id(this));
1058 return !memories.empty();
1059 }
1060
1061 bool RTLIL::Module::has_processes_warn() const
1062 {
1063 if (!processes.empty())
1064 log("Warning: Ignoring module %s because it contains processes (run 'proc' command first).\n", log_id(this));
1065 return !processes.empty();
1066 }
1067
1068 std::vector<RTLIL::Wire*> RTLIL::Module::selected_wires() const
1069 {
1070 std::vector<RTLIL::Wire*> result;
1071 result.reserve(wires_.size());
1072 for (auto &it : wires_)
1073 if (design->selected(this, it.second))
1074 result.push_back(it.second);
1075 return result;
1076 }
1077
1078 std::vector<RTLIL::Cell*> RTLIL::Module::selected_cells() const
1079 {
1080 std::vector<RTLIL::Cell*> result;
1081 result.reserve(wires_.size());
1082 for (auto &it : cells_)
1083 if (design->selected(this, it.second))
1084 result.push_back(it.second);
1085 return result;
1086 }
1087
1088 void RTLIL::Module::add(RTLIL::Wire *wire)
1089 {
1090 log_assert(!wire->name.empty());
1091 log_assert(count_id(wire->name) == 0);
1092 log_assert(refcount_wires_ == 0);
1093 wires_[wire->name] = wire;
1094 wire->module = this;
1095 }
1096
1097 void RTLIL::Module::add(RTLIL::Cell *cell)
1098 {
1099 log_assert(!cell->name.empty());
1100 log_assert(count_id(cell->name) == 0);
1101 log_assert(refcount_cells_ == 0);
1102 cells_[cell->name] = cell;
1103 cell->module = this;
1104 }
1105
1106 namespace {
1107 struct DeleteWireWorker
1108 {
1109 RTLIL::Module *module;
1110 const std::set<RTLIL::Wire*> *wires_p;
1111
1112 void operator()(RTLIL::SigSpec &sig) {
1113 std::vector<RTLIL::SigChunk> chunks = sig;
1114 for (auto &c : chunks)
1115 if (c.wire != NULL && wires_p->count(c.wire)) {
1116 c.wire = module->addWire(NEW_ID, c.width);
1117 c.offset = 0;
1118 }
1119 sig = chunks;
1120 }
1121 };
1122 }
1123
1124 #if 0
1125 void RTLIL::Module::remove(RTLIL::Wire *wire)
1126 {
1127 std::setPort<RTLIL::Wire*> wires_;
1128 wires_.insert(wire);
1129 remove(wires_);
1130 }
1131 #endif
1132
1133 void RTLIL::Module::remove(const std::set<RTLIL::Wire*> &wires)
1134 {
1135 log_assert(refcount_wires_ == 0);
1136
1137 DeleteWireWorker delete_wire_worker;
1138 delete_wire_worker.module = this;
1139 delete_wire_worker.wires_p = &wires;
1140 rewrite_sigspecs(delete_wire_worker);
1141
1142 for (auto &it : wires) {
1143 log_assert(wires_.count(it->name) != 0);
1144 wires_.erase(it->name);
1145 delete it;
1146 }
1147 }
1148
1149 void RTLIL::Module::remove(RTLIL::Cell *cell)
1150 {
1151 while (!cell->connections_.empty())
1152 cell->unsetPort(cell->connections_.begin()->first);
1153
1154 log_assert(cells_.count(cell->name) != 0);
1155 log_assert(refcount_cells_ == 0);
1156 cells_.erase(cell->name);
1157 delete cell;
1158 }
1159
1160 void RTLIL::Module::rename(RTLIL::Wire *wire, RTLIL::IdString new_name)
1161 {
1162 log_assert(wires_[wire->name] == wire);
1163 log_assert(refcount_wires_ == 0);
1164 wires_.erase(wire->name);
1165 wire->name = new_name;
1166 add(wire);
1167 }
1168
1169 void RTLIL::Module::rename(RTLIL::Cell *cell, RTLIL::IdString new_name)
1170 {
1171 log_assert(cells_[cell->name] == cell);
1172 log_assert(refcount_wires_ == 0);
1173 cells_.erase(cell->name);
1174 cell->name = new_name;
1175 add(cell);
1176 }
1177
1178 void RTLIL::Module::rename(RTLIL::IdString old_name, RTLIL::IdString new_name)
1179 {
1180 log_assert(count_id(old_name) != 0);
1181 if (wires_.count(old_name))
1182 rename(wires_.at(old_name), new_name);
1183 else if (cells_.count(old_name))
1184 rename(cells_.at(old_name), new_name);
1185 else
1186 log_abort();
1187 }
1188
1189 void RTLIL::Module::swap_names(RTLIL::Wire *w1, RTLIL::Wire *w2)
1190 {
1191 log_assert(wires_[w1->name] == w1);
1192 log_assert(wires_[w2->name] == w2);
1193 log_assert(refcount_wires_ == 0);
1194
1195 wires_.erase(w1->name);
1196 wires_.erase(w2->name);
1197
1198 std::swap(w1->name, w2->name);
1199
1200 wires_[w1->name] = w1;
1201 wires_[w2->name] = w2;
1202 }
1203
1204 void RTLIL::Module::swap_names(RTLIL::Cell *c1, RTLIL::Cell *c2)
1205 {
1206 log_assert(cells_[c1->name] == c1);
1207 log_assert(cells_[c2->name] == c2);
1208 log_assert(refcount_cells_ == 0);
1209
1210 cells_.erase(c1->name);
1211 cells_.erase(c2->name);
1212
1213 std::swap(c1->name, c2->name);
1214
1215 cells_[c1->name] = c1;
1216 cells_[c2->name] = c2;
1217 }
1218
1219 RTLIL::IdString RTLIL::Module::uniquify(RTLIL::IdString name)
1220 {
1221 int index = 0;
1222 return uniquify(name, index);
1223 }
1224
1225 RTLIL::IdString RTLIL::Module::uniquify(RTLIL::IdString name, int &index)
1226 {
1227 if (index == 0) {
1228 if (count_id(name) == 0)
1229 return name;
1230 index++;
1231 }
1232
1233 while (1) {
1234 RTLIL::IdString new_name = stringf("%s_%d", name.c_str(), index);
1235 if (count_id(new_name) == 0)
1236 return new_name;
1237 index++;
1238 }
1239 }
1240
1241 static bool fixup_ports_compare(const RTLIL::Wire *a, const RTLIL::Wire *b)
1242 {
1243 if (a->port_id && !b->port_id)
1244 return true;
1245 if (!a->port_id && b->port_id)
1246 return false;
1247
1248 if (a->port_id == b->port_id)
1249 return a->name < b->name;
1250 return a->port_id < b->port_id;
1251 }
1252
1253 void RTLIL::Module::connect(const RTLIL::SigSig &conn)
1254 {
1255 for (auto mon : monitors)
1256 mon->notify_connect(this, conn);
1257
1258 if (design)
1259 for (auto mon : design->monitors)
1260 mon->notify_connect(this, conn);
1261
1262 connections_.push_back(conn);
1263 }
1264
1265 void RTLIL::Module::connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs)
1266 {
1267 connect(RTLIL::SigSig(lhs, rhs));
1268 }
1269
1270 void RTLIL::Module::new_connections(const std::vector<RTLIL::SigSig> &new_conn)
1271 {
1272 for (auto mon : monitors)
1273 mon->notify_connect(this, new_conn);
1274
1275 if (design)
1276 for (auto mon : design->monitors)
1277 mon->notify_connect(this, new_conn);
1278
1279 connections_ = new_conn;
1280 }
1281
1282 const std::vector<RTLIL::SigSig> &RTLIL::Module::connections() const
1283 {
1284 return connections_;
1285 }
1286
1287 void RTLIL::Module::fixup_ports()
1288 {
1289 std::vector<RTLIL::Wire*> all_ports;
1290
1291 for (auto &w : wires_)
1292 if (w.second->port_input || w.second->port_output)
1293 all_ports.push_back(w.second);
1294 else
1295 w.second->port_id = 0;
1296
1297 std::sort(all_ports.begin(), all_ports.end(), fixup_ports_compare);
1298
1299 ports.clear();
1300 for (size_t i = 0; i < all_ports.size(); i++) {
1301 ports.push_back(all_ports[i]->name);
1302 all_ports[i]->port_id = i+1;
1303 }
1304 }
1305
1306 RTLIL::Wire *RTLIL::Module::addWire(RTLIL::IdString name, int width)
1307 {
1308 RTLIL::Wire *wire = new RTLIL::Wire;
1309 wire->name = name;
1310 wire->width = width;
1311 add(wire);
1312 return wire;
1313 }
1314
1315 RTLIL::Wire *RTLIL::Module::addWire(RTLIL::IdString name, const RTLIL::Wire *other)
1316 {
1317 RTLIL::Wire *wire = addWire(name);
1318 wire->width = other->width;
1319 wire->start_offset = other->start_offset;
1320 wire->port_id = other->port_id;
1321 wire->port_input = other->port_input;
1322 wire->port_output = other->port_output;
1323 wire->upto = other->upto;
1324 wire->attributes = other->attributes;
1325 return wire;
1326 }
1327
1328 RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, RTLIL::IdString type)
1329 {
1330 RTLIL::Cell *cell = new RTLIL::Cell;
1331 cell->name = name;
1332 cell->type = type;
1333 add(cell);
1334 return cell;
1335 }
1336
1337 RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, const RTLIL::Cell *other)
1338 {
1339 RTLIL::Cell *cell = addCell(name, other->type);
1340 cell->connections_ = other->connections_;
1341 cell->parameters = other->parameters;
1342 cell->attributes = other->attributes;
1343 return cell;
1344 }
1345
1346 #define DEF_METHOD(_func, _y_size, _type) \
1347 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed) { \
1348 RTLIL::Cell *cell = addCell(name, _type); \
1349 cell->parameters["\\A_SIGNED"] = is_signed; \
1350 cell->parameters["\\A_WIDTH"] = sig_a.size(); \
1351 cell->parameters["\\Y_WIDTH"] = sig_y.size(); \
1352 cell->setPort("\\A", sig_a); \
1353 cell->setPort("\\Y", sig_y); \
1354 return cell; \
1355 } \
1356 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed) { \
1357 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
1358 add ## _func(name, sig_a, sig_y, is_signed); \
1359 return sig_y; \
1360 }
1361 DEF_METHOD(Not, sig_a.size(), "$not")
1362 DEF_METHOD(Pos, sig_a.size(), "$pos")
1363 DEF_METHOD(Neg, sig_a.size(), "$neg")
1364 DEF_METHOD(ReduceAnd, 1, "$reduce_and")
1365 DEF_METHOD(ReduceOr, 1, "$reduce_or")
1366 DEF_METHOD(ReduceXor, 1, "$reduce_xor")
1367 DEF_METHOD(ReduceXnor, 1, "$reduce_xnor")
1368 DEF_METHOD(ReduceBool, 1, "$reduce_bool")
1369 DEF_METHOD(LogicNot, 1, "$logic_not")
1370 #undef DEF_METHOD
1371
1372 #define DEF_METHOD(_func, _y_size, _type) \
1373 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed) { \
1374 RTLIL::Cell *cell = addCell(name, _type); \
1375 cell->parameters["\\A_SIGNED"] = is_signed; \
1376 cell->parameters["\\B_SIGNED"] = is_signed; \
1377 cell->parameters["\\A_WIDTH"] = sig_a.size(); \
1378 cell->parameters["\\B_WIDTH"] = sig_b.size(); \
1379 cell->parameters["\\Y_WIDTH"] = sig_y.size(); \
1380 cell->setPort("\\A", sig_a); \
1381 cell->setPort("\\B", sig_b); \
1382 cell->setPort("\\Y", sig_y); \
1383 return cell; \
1384 } \
1385 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed) { \
1386 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
1387 add ## _func(name, sig_a, sig_b, sig_y, is_signed); \
1388 return sig_y; \
1389 }
1390 DEF_METHOD(And, std::max(sig_a.size(), sig_b.size()), "$and")
1391 DEF_METHOD(Or, std::max(sig_a.size(), sig_b.size()), "$or")
1392 DEF_METHOD(Xor, std::max(sig_a.size(), sig_b.size()), "$xor")
1393 DEF_METHOD(Xnor, std::max(sig_a.size(), sig_b.size()), "$xnor")
1394 DEF_METHOD(Shl, sig_a.size(), "$shl")
1395 DEF_METHOD(Shr, sig_a.size(), "$shr")
1396 DEF_METHOD(Sshl, sig_a.size(), "$sshl")
1397 DEF_METHOD(Sshr, sig_a.size(), "$sshr")
1398 DEF_METHOD(Shift, sig_a.size(), "$shift")
1399 DEF_METHOD(Shiftx, sig_a.size(), "$shiftx")
1400 DEF_METHOD(Lt, 1, "$lt")
1401 DEF_METHOD(Le, 1, "$le")
1402 DEF_METHOD(Eq, 1, "$eq")
1403 DEF_METHOD(Ne, 1, "$ne")
1404 DEF_METHOD(Eqx, 1, "$eqx")
1405 DEF_METHOD(Nex, 1, "$nex")
1406 DEF_METHOD(Ge, 1, "$ge")
1407 DEF_METHOD(Gt, 1, "$gt")
1408 DEF_METHOD(Add, std::max(sig_a.size(), sig_b.size()), "$add")
1409 DEF_METHOD(Sub, std::max(sig_a.size(), sig_b.size()), "$sub")
1410 DEF_METHOD(Mul, std::max(sig_a.size(), sig_b.size()), "$mul")
1411 DEF_METHOD(Div, std::max(sig_a.size(), sig_b.size()), "$div")
1412 DEF_METHOD(Mod, std::max(sig_a.size(), sig_b.size()), "$mod")
1413 DEF_METHOD(LogicAnd, 1, "$logic_and")
1414 DEF_METHOD(LogicOr, 1, "$logic_or")
1415 #undef DEF_METHOD
1416
1417 #define DEF_METHOD(_func, _type, _pmux) \
1418 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, RTLIL::SigSpec sig_y) { \
1419 RTLIL::Cell *cell = addCell(name, _type); \
1420 cell->parameters["\\WIDTH"] = sig_a.size(); \
1421 if (_pmux) cell->parameters["\\S_WIDTH"] = sig_s.size(); \
1422 cell->setPort("\\A", sig_a); \
1423 cell->setPort("\\B", sig_b); \
1424 cell->setPort("\\S", sig_s); \
1425 cell->setPort("\\Y", sig_y); \
1426 return cell; \
1427 } \
1428 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s) { \
1429 RTLIL::SigSpec sig_y = addWire(NEW_ID, sig_a.size()); \
1430 add ## _func(name, sig_a, sig_b, sig_s, sig_y); \
1431 return sig_y; \
1432 }
1433 DEF_METHOD(Mux, "$mux", 0)
1434 DEF_METHOD(Pmux, "$pmux", 1)
1435 #undef DEF_METHOD
1436
1437 #define DEF_METHOD_2(_func, _type, _P1, _P2) \
1438 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2) { \
1439 RTLIL::Cell *cell = addCell(name, _type); \
1440 cell->setPort("\\" #_P1, sig1); \
1441 cell->setPort("\\" #_P2, sig2); \
1442 return cell; \
1443 } \
1444 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1) { \
1445 RTLIL::SigBit sig2 = addWire(NEW_ID); \
1446 add ## _func(name, sig1, sig2); \
1447 return sig2; \
1448 }
1449 #define DEF_METHOD_3(_func, _type, _P1, _P2, _P3) \
1450 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3) { \
1451 RTLIL::Cell *cell = addCell(name, _type); \
1452 cell->setPort("\\" #_P1, sig1); \
1453 cell->setPort("\\" #_P2, sig2); \
1454 cell->setPort("\\" #_P3, sig3); \
1455 return cell; \
1456 } \
1457 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2) { \
1458 RTLIL::SigBit sig3 = addWire(NEW_ID); \
1459 add ## _func(name, sig1, sig2, sig3); \
1460 return sig3; \
1461 }
1462 #define DEF_METHOD_4(_func, _type, _P1, _P2, _P3, _P4) \
1463 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, RTLIL::SigBit sig4) { \
1464 RTLIL::Cell *cell = addCell(name, _type); \
1465 cell->setPort("\\" #_P1, sig1); \
1466 cell->setPort("\\" #_P2, sig2); \
1467 cell->setPort("\\" #_P3, sig3); \
1468 cell->setPort("\\" #_P4, sig4); \
1469 return cell; \
1470 } \
1471 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3) { \
1472 RTLIL::SigBit sig4 = addWire(NEW_ID); \
1473 add ## _func(name, sig1, sig2, sig3, sig4); \
1474 return sig4; \
1475 }
1476 #define DEF_METHOD_5(_func, _type, _P1, _P2, _P3, _P4, _P5) \
1477 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, RTLIL::SigBit sig4, RTLIL::SigBit sig5) { \
1478 RTLIL::Cell *cell = addCell(name, _type); \
1479 cell->setPort("\\" #_P1, sig1); \
1480 cell->setPort("\\" #_P2, sig2); \
1481 cell->setPort("\\" #_P3, sig3); \
1482 cell->setPort("\\" #_P4, sig4); \
1483 cell->setPort("\\" #_P5, sig5); \
1484 return cell; \
1485 } \
1486 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, RTLIL::SigBit sig4) { \
1487 RTLIL::SigBit sig5 = addWire(NEW_ID); \
1488 add ## _func(name, sig1, sig2, sig3, sig4, sig5); \
1489 return sig5; \
1490 }
1491 DEF_METHOD_2(NotGate, "$_NOT_", A, Y)
1492 DEF_METHOD_3(AndGate, "$_AND_", A, B, Y)
1493 DEF_METHOD_3(NandGate, "$_NAND_", A, B, Y)
1494 DEF_METHOD_3(OrGate, "$_OR_", A, B, Y)
1495 DEF_METHOD_3(NorGate, "$_NOR_", A, B, Y)
1496 DEF_METHOD_3(XorGate, "$_XOR_", A, B, Y)
1497 DEF_METHOD_3(XnorGate, "$_XNOR_", A, B, Y)
1498 DEF_METHOD_4(MuxGate, "$_MUX_", A, B, S, Y)
1499 DEF_METHOD_4(Aoi3Gate, "$_AOI3_", A, B, C, Y)
1500 DEF_METHOD_4(Oai3Gate, "$_OAI3_", A, B, C, Y)
1501 DEF_METHOD_5(Aoi4Gate, "$_AOI4_", A, B, C, D, Y)
1502 DEF_METHOD_5(Oai4Gate, "$_OAI4_", A, B, C, D, Y)
1503 #undef DEF_METHOD_2
1504 #undef DEF_METHOD_3
1505 #undef DEF_METHOD_4
1506 #undef DEF_METHOD_5
1507
1508 RTLIL::Cell* RTLIL::Module::addPow(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool a_signed, bool b_signed)
1509 {
1510 RTLIL::Cell *cell = addCell(name, "$pow");
1511 cell->parameters["\\A_SIGNED"] = a_signed;
1512 cell->parameters["\\B_SIGNED"] = b_signed;
1513 cell->parameters["\\A_WIDTH"] = sig_a.size();
1514 cell->parameters["\\B_WIDTH"] = sig_b.size();
1515 cell->parameters["\\Y_WIDTH"] = sig_y.size();
1516 cell->setPort("\\A", sig_a);
1517 cell->setPort("\\B", sig_b);
1518 cell->setPort("\\Y", sig_y);
1519 return cell;
1520 }
1521
1522 RTLIL::Cell* RTLIL::Module::addSlice(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, RTLIL::Const offset)
1523 {
1524 RTLIL::Cell *cell = addCell(name, "$slice");
1525 cell->parameters["\\A_WIDTH"] = sig_a.size();
1526 cell->parameters["\\Y_WIDTH"] = sig_y.size();
1527 cell->parameters["\\OFFSET"] = offset;
1528 cell->setPort("\\A", sig_a);
1529 cell->setPort("\\Y", sig_y);
1530 return cell;
1531 }
1532
1533 RTLIL::Cell* RTLIL::Module::addConcat(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y)
1534 {
1535 RTLIL::Cell *cell = addCell(name, "$concat");
1536 cell->parameters["\\A_WIDTH"] = sig_a.size();
1537 cell->parameters["\\B_WIDTH"] = sig_b.size();
1538 cell->setPort("\\A", sig_a);
1539 cell->setPort("\\B", sig_b);
1540 cell->setPort("\\Y", sig_y);
1541 return cell;
1542 }
1543
1544 RTLIL::Cell* RTLIL::Module::addLut(RTLIL::IdString name, RTLIL::SigSpec sig_i, RTLIL::SigSpec sig_o, RTLIL::Const lut)
1545 {
1546 RTLIL::Cell *cell = addCell(name, "$lut");
1547 cell->parameters["\\LUT"] = lut;
1548 cell->parameters["\\WIDTH"] = sig_i.size();
1549 cell->setPort("\\A", sig_i);
1550 cell->setPort("\\Y", sig_o);
1551 return cell;
1552 }
1553
1554 RTLIL::Cell* RTLIL::Module::addAssert(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en)
1555 {
1556 RTLIL::Cell *cell = addCell(name, "$assert");
1557 cell->setPort("\\A", sig_a);
1558 cell->setPort("\\EN", sig_en);
1559 return cell;
1560 }
1561
1562 RTLIL::Cell* RTLIL::Module::addSr(RTLIL::IdString name, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr, RTLIL::SigSpec sig_q, bool set_polarity, bool clr_polarity)
1563 {
1564 RTLIL::Cell *cell = addCell(name, "$sr");
1565 cell->parameters["\\SET_POLARITY"] = set_polarity;
1566 cell->parameters["\\CLR_POLARITY"] = clr_polarity;
1567 cell->parameters["\\WIDTH"] = sig_q.size();
1568 cell->setPort("\\SET", sig_set);
1569 cell->setPort("\\CLR", sig_clr);
1570 cell->setPort("\\Q", sig_q);
1571 return cell;
1572 }
1573
1574 RTLIL::Cell* RTLIL::Module::addDff(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity)
1575 {
1576 RTLIL::Cell *cell = addCell(name, "$dff");
1577 cell->parameters["\\CLK_POLARITY"] = clk_polarity;
1578 cell->parameters["\\WIDTH"] = sig_q.size();
1579 cell->setPort("\\CLK", sig_clk);
1580 cell->setPort("\\D", sig_d);
1581 cell->setPort("\\Q", sig_q);
1582 return cell;
1583 }
1584
1585 RTLIL::Cell* RTLIL::Module::addDffsr(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
1586 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity)
1587 {
1588 RTLIL::Cell *cell = addCell(name, "$dffsr");
1589 cell->parameters["\\CLK_POLARITY"] = clk_polarity;
1590 cell->parameters["\\SET_POLARITY"] = set_polarity;
1591 cell->parameters["\\CLR_POLARITY"] = clr_polarity;
1592 cell->parameters["\\WIDTH"] = sig_q.size();
1593 cell->setPort("\\CLK", sig_clk);
1594 cell->setPort("\\SET", sig_set);
1595 cell->setPort("\\CLR", sig_clr);
1596 cell->setPort("\\D", sig_d);
1597 cell->setPort("\\Q", sig_q);
1598 return cell;
1599 }
1600
1601 RTLIL::Cell* RTLIL::Module::addAdff(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_arst, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q,
1602 RTLIL::Const arst_value, bool clk_polarity, bool arst_polarity)
1603 {
1604 RTLIL::Cell *cell = addCell(name, "$adff");
1605 cell->parameters["\\CLK_POLARITY"] = clk_polarity;
1606 cell->parameters["\\ARST_POLARITY"] = arst_polarity;
1607 cell->parameters["\\ARST_VALUE"] = arst_value;
1608 cell->parameters["\\WIDTH"] = sig_q.size();
1609 cell->setPort("\\CLK", sig_clk);
1610 cell->setPort("\\ARST", sig_arst);
1611 cell->setPort("\\D", sig_d);
1612 cell->setPort("\\Q", sig_q);
1613 return cell;
1614 }
1615
1616 RTLIL::Cell* RTLIL::Module::addDlatch(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity)
1617 {
1618 RTLIL::Cell *cell = addCell(name, "$dlatch");
1619 cell->parameters["\\EN_POLARITY"] = en_polarity;
1620 cell->parameters["\\WIDTH"] = sig_q.size();
1621 cell->setPort("\\EN", sig_en);
1622 cell->setPort("\\D", sig_d);
1623 cell->setPort("\\Q", sig_q);
1624 return cell;
1625 }
1626
1627 RTLIL::Cell* RTLIL::Module::addDlatchsr(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
1628 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity, bool set_polarity, bool clr_polarity)
1629 {
1630 RTLIL::Cell *cell = addCell(name, "$dlatchsr");
1631 cell->parameters["\\EN_POLARITY"] = en_polarity;
1632 cell->parameters["\\SET_POLARITY"] = set_polarity;
1633 cell->parameters["\\CLR_POLARITY"] = clr_polarity;
1634 cell->parameters["\\WIDTH"] = sig_q.size();
1635 cell->setPort("\\EN", sig_en);
1636 cell->setPort("\\SET", sig_set);
1637 cell->setPort("\\CLR", sig_clr);
1638 cell->setPort("\\D", sig_d);
1639 cell->setPort("\\Q", sig_q);
1640 return cell;
1641 }
1642
1643 RTLIL::Cell* RTLIL::Module::addDffGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity)
1644 {
1645 RTLIL::Cell *cell = addCell(name, stringf("$_DFF_%c_", clk_polarity ? 'P' : 'N'));
1646 cell->setPort("\\C", sig_clk);
1647 cell->setPort("\\D", sig_d);
1648 cell->setPort("\\Q", sig_q);
1649 return cell;
1650 }
1651
1652 RTLIL::Cell* RTLIL::Module::addDffsrGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
1653 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity)
1654 {
1655 RTLIL::Cell *cell = addCell(name, stringf("$_DFFSR_%c%c%c_", clk_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N'));
1656 cell->setPort("\\C", sig_clk);
1657 cell->setPort("\\S", sig_set);
1658 cell->setPort("\\R", sig_clr);
1659 cell->setPort("\\D", sig_d);
1660 cell->setPort("\\Q", sig_q);
1661 return cell;
1662 }
1663
1664 RTLIL::Cell* RTLIL::Module::addAdffGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_arst, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q,
1665 bool arst_value, bool clk_polarity, bool arst_polarity)
1666 {
1667 RTLIL::Cell *cell = addCell(name, stringf("$_DFF_%c%c%c_", clk_polarity ? 'P' : 'N', arst_polarity ? 'P' : 'N', arst_value ? '1' : '0'));
1668 cell->setPort("\\C", sig_clk);
1669 cell->setPort("\\R", sig_arst);
1670 cell->setPort("\\D", sig_d);
1671 cell->setPort("\\Q", sig_q);
1672 return cell;
1673 }
1674
1675 RTLIL::Cell* RTLIL::Module::addDlatchGate(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity)
1676 {
1677 RTLIL::Cell *cell = addCell(name, stringf("$_DLATCH_%c_", en_polarity ? 'P' : 'N'));
1678 cell->setPort("\\E", sig_en);
1679 cell->setPort("\\D", sig_d);
1680 cell->setPort("\\Q", sig_q);
1681 return cell;
1682 }
1683
1684 RTLIL::Cell* RTLIL::Module::addDlatchsrGate(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
1685 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity, bool set_polarity, bool clr_polarity)
1686 {
1687 RTLIL::Cell *cell = addCell(name, stringf("$_DLATCHSR_%c%c%c_", en_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N'));
1688 cell->setPort("\\E", sig_en);
1689 cell->setPort("\\S", sig_set);
1690 cell->setPort("\\R", sig_clr);
1691 cell->setPort("\\D", sig_d);
1692 cell->setPort("\\Q", sig_q);
1693 return cell;
1694 }
1695
1696
1697 RTLIL::Wire::Wire()
1698 {
1699 module = nullptr;
1700 width = 1;
1701 start_offset = 0;
1702 port_id = 0;
1703 port_input = false;
1704 port_output = false;
1705 upto = false;
1706 }
1707
1708 RTLIL::Memory::Memory()
1709 {
1710 width = 1;
1711 size = 0;
1712 }
1713
1714 RTLIL::Cell::Cell() : module(nullptr)
1715 {
1716 }
1717
1718 bool RTLIL::Cell::hasPort(RTLIL::IdString portname) const
1719 {
1720 return connections_.count(portname) != 0;
1721 }
1722
1723 void RTLIL::Cell::unsetPort(RTLIL::IdString portname)
1724 {
1725 RTLIL::SigSpec signal;
1726 auto conn_it = connections_.find(portname);
1727
1728 if (conn_it != connections_.end())
1729 {
1730 for (auto mon : module->monitors)
1731 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
1732
1733 if (module->design)
1734 for (auto mon : module->design->monitors)
1735 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
1736
1737 connections_.erase(conn_it);
1738 }
1739 }
1740
1741 void RTLIL::Cell::setPort(RTLIL::IdString portname, RTLIL::SigSpec signal)
1742 {
1743 auto conn_it = connections_.find(portname);
1744
1745 if (conn_it == connections_.end()) {
1746 connections_[portname] = RTLIL::SigSpec();
1747 conn_it = connections_.find(portname);
1748 log_assert(conn_it != connections_.end());
1749 }
1750
1751 for (auto mon : module->monitors)
1752 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
1753
1754 if (module->design)
1755 for (auto mon : module->design->monitors)
1756 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
1757
1758 conn_it->second = signal;
1759 }
1760
1761 const RTLIL::SigSpec &RTLIL::Cell::getPort(RTLIL::IdString portname) const
1762 {
1763 return connections_.at(portname);
1764 }
1765
1766 const std::map<RTLIL::IdString, RTLIL::SigSpec> &RTLIL::Cell::connections() const
1767 {
1768 return connections_;
1769 }
1770
1771 bool RTLIL::Cell::hasParam(RTLIL::IdString paramname) const
1772 {
1773 return parameters.count(paramname);
1774 }
1775
1776 void RTLIL::Cell::unsetParam(RTLIL::IdString paramname)
1777 {
1778 parameters.erase(paramname);
1779 }
1780
1781 void RTLIL::Cell::setParam(RTLIL::IdString paramname, RTLIL::Const value)
1782 {
1783 parameters[paramname] = value;
1784 }
1785
1786 const RTLIL::Const &RTLIL::Cell::getParam(RTLIL::IdString paramname) const
1787 {
1788 return parameters.at(paramname);
1789 }
1790
1791 void RTLIL::Cell::check()
1792 {
1793 #ifndef NDEBUG
1794 InternalCellChecker checker(NULL, this);
1795 checker.check();
1796 #endif
1797 }
1798
1799 void RTLIL::Cell::fixup_parameters(bool set_a_signed, bool set_b_signed)
1800 {
1801 if (type.substr(0, 1) != "$" || type.substr(0, 2) == "$_" || type.substr(0, 8) == "$paramod" ||
1802 type.substr(0, 9) == "$verific$" || type.substr(0, 7) == "$array:" || type.substr(0, 8) == "$extern:")
1803 return;
1804
1805 if (type == "$mux" || type == "$pmux") {
1806 parameters["\\WIDTH"] = SIZE(connections_["\\Y"]);
1807 if (type == "$pmux")
1808 parameters["\\S_WIDTH"] = SIZE(connections_["\\S"]);
1809 check();
1810 return;
1811 }
1812
1813 if (type == "$lut") {
1814 parameters["\\WIDTH"] = SIZE(connections_["\\A"]);
1815 return;
1816 }
1817
1818 if (type == "$fa") {
1819 parameters["\\WIDTH"] = SIZE(connections_["\\Y"]);
1820 return;
1821 }
1822
1823 if (type == "$lcu") {
1824 parameters["\\WIDTH"] = SIZE(connections_["\\CO"]);
1825 return;
1826 }
1827
1828 bool signedness_ab = !type.in("$slice", "$concat", "$macc");
1829
1830 if (connections_.count("\\A")) {
1831 if (signedness_ab) {
1832 if (set_a_signed)
1833 parameters["\\A_SIGNED"] = true;
1834 else if (parameters.count("\\A_SIGNED") == 0)
1835 parameters["\\A_SIGNED"] = false;
1836 }
1837 parameters["\\A_WIDTH"] = SIZE(connections_["\\A"]);
1838 }
1839
1840 if (connections_.count("\\B")) {
1841 if (signedness_ab) {
1842 if (set_b_signed)
1843 parameters["\\B_SIGNED"] = true;
1844 else if (parameters.count("\\B_SIGNED") == 0)
1845 parameters["\\B_SIGNED"] = false;
1846 }
1847 parameters["\\B_WIDTH"] = SIZE(connections_["\\B"]);
1848 }
1849
1850 if (connections_.count("\\Y"))
1851 parameters["\\Y_WIDTH"] = SIZE(connections_["\\Y"]);
1852
1853 check();
1854 }
1855
1856 RTLIL::SigChunk::SigChunk()
1857 {
1858 wire = NULL;
1859 width = 0;
1860 offset = 0;
1861 }
1862
1863 RTLIL::SigChunk::SigChunk(const RTLIL::Const &value)
1864 {
1865 wire = NULL;
1866 data = value.bits;
1867 width = SIZE(data);
1868 offset = 0;
1869 }
1870
1871 RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire)
1872 {
1873 log_assert(wire != nullptr);
1874 this->wire = wire;
1875 this->width = wire->width;
1876 this->offset = 0;
1877 }
1878
1879 RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire, int offset, int width)
1880 {
1881 log_assert(wire != nullptr);
1882 this->wire = wire;
1883 this->width = width;
1884 this->offset = offset;
1885 }
1886
1887 RTLIL::SigChunk::SigChunk(const std::string &str)
1888 {
1889 wire = NULL;
1890 data = RTLIL::Const(str).bits;
1891 width = SIZE(data);
1892 offset = 0;
1893 }
1894
1895 RTLIL::SigChunk::SigChunk(int val, int width)
1896 {
1897 wire = NULL;
1898 data = RTLIL::Const(val, width).bits;
1899 this->width = SIZE(data);
1900 offset = 0;
1901 }
1902
1903 RTLIL::SigChunk::SigChunk(RTLIL::State bit, int width)
1904 {
1905 wire = NULL;
1906 data = RTLIL::Const(bit, width).bits;
1907 this->width = SIZE(data);
1908 offset = 0;
1909 }
1910
1911 RTLIL::SigChunk::SigChunk(RTLIL::SigBit bit)
1912 {
1913 wire = bit.wire;
1914 offset = 0;
1915 if (wire == NULL)
1916 data = RTLIL::Const(bit.data).bits;
1917 else
1918 offset = bit.offset;
1919 width = 1;
1920 }
1921
1922 RTLIL::SigChunk RTLIL::SigChunk::extract(int offset, int length) const
1923 {
1924 RTLIL::SigChunk ret;
1925 if (wire) {
1926 ret.wire = wire;
1927 ret.offset = this->offset + offset;
1928 ret.width = length;
1929 } else {
1930 for (int i = 0; i < length; i++)
1931 ret.data.push_back(data[offset+i]);
1932 ret.width = length;
1933 }
1934 return ret;
1935 }
1936
1937 bool RTLIL::SigChunk::operator <(const RTLIL::SigChunk &other) const
1938 {
1939 if (wire && other.wire)
1940 if (wire->name != other.wire->name)
1941 return wire->name < other.wire->name;
1942
1943 if (wire != other.wire)
1944 return wire < other.wire;
1945
1946 if (offset != other.offset)
1947 return offset < other.offset;
1948
1949 if (width != other.width)
1950 return width < other.width;
1951
1952 return data < other.data;
1953 }
1954
1955 bool RTLIL::SigChunk::operator ==(const RTLIL::SigChunk &other) const
1956 {
1957 return wire == other.wire && width == other.width && offset == other.offset && data == other.data;
1958 }
1959
1960 bool RTLIL::SigChunk::operator !=(const RTLIL::SigChunk &other) const
1961 {
1962 if (*this == other)
1963 return false;
1964 return true;
1965 }
1966
1967 RTLIL::SigSpec::SigSpec()
1968 {
1969 width_ = 0;
1970 hash_ = 0;
1971 }
1972
1973 RTLIL::SigSpec::SigSpec(const RTLIL::SigSpec &other)
1974 {
1975 *this = other;
1976 }
1977
1978 RTLIL::SigSpec::SigSpec(std::initializer_list<RTLIL::SigSpec> parts)
1979 {
1980 cover("kernel.rtlil.sigspec.init.list");
1981
1982 width_ = 0;
1983 hash_ = 0;
1984
1985 std::vector<RTLIL::SigSpec> parts_vec(parts.begin(), parts.end());
1986 for (auto it = parts_vec.rbegin(); it != parts_vec.rend(); it++)
1987 append(*it);
1988 }
1989
1990 const RTLIL::SigSpec &RTLIL::SigSpec::operator=(const RTLIL::SigSpec &other)
1991 {
1992 cover("kernel.rtlil.sigspec.assign");
1993
1994 width_ = other.width_;
1995 hash_ = other.hash_;
1996 chunks_ = other.chunks_;
1997 bits_.clear();
1998
1999 if (!other.bits_.empty())
2000 {
2001 RTLIL::SigChunk *last = NULL;
2002 int last_end_offset = 0;
2003
2004 for (auto &bit : other.bits_) {
2005 if (last && bit.wire == last->wire) {
2006 if (bit.wire == NULL) {
2007 last->data.push_back(bit.data);
2008 last->width++;
2009 continue;
2010 } else if (last_end_offset == bit.offset) {
2011 last_end_offset++;
2012 last->width++;
2013 continue;
2014 }
2015 }
2016 chunks_.push_back(bit);
2017 last = &chunks_.back();
2018 last_end_offset = bit.offset + 1;
2019 }
2020
2021 check();
2022 }
2023
2024 return *this;
2025 }
2026
2027 RTLIL::SigSpec::SigSpec(const RTLIL::Const &value)
2028 {
2029 cover("kernel.rtlil.sigspec.init.const");
2030
2031 chunks_.push_back(RTLIL::SigChunk(value));
2032 width_ = chunks_.back().width;
2033 hash_ = 0;
2034 check();
2035 }
2036
2037 RTLIL::SigSpec::SigSpec(const RTLIL::SigChunk &chunk)
2038 {
2039 cover("kernel.rtlil.sigspec.init.chunk");
2040
2041 chunks_.push_back(chunk);
2042 width_ = chunks_.back().width;
2043 hash_ = 0;
2044 check();
2045 }
2046
2047 RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire)
2048 {
2049 cover("kernel.rtlil.sigspec.init.wire");
2050
2051 chunks_.push_back(RTLIL::SigChunk(wire));
2052 width_ = chunks_.back().width;
2053 hash_ = 0;
2054 check();
2055 }
2056
2057 RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire, int offset, int width)
2058 {
2059 cover("kernel.rtlil.sigspec.init.wire_part");
2060
2061 chunks_.push_back(RTLIL::SigChunk(wire, offset, width));
2062 width_ = chunks_.back().width;
2063 hash_ = 0;
2064 check();
2065 }
2066
2067 RTLIL::SigSpec::SigSpec(const std::string &str)
2068 {
2069 cover("kernel.rtlil.sigspec.init.str");
2070
2071 chunks_.push_back(RTLIL::SigChunk(str));
2072 width_ = chunks_.back().width;
2073 hash_ = 0;
2074 check();
2075 }
2076
2077 RTLIL::SigSpec::SigSpec(int val, int width)
2078 {
2079 cover("kernel.rtlil.sigspec.init.int");
2080
2081 chunks_.push_back(RTLIL::SigChunk(val, width));
2082 width_ = width;
2083 hash_ = 0;
2084 check();
2085 }
2086
2087 RTLIL::SigSpec::SigSpec(RTLIL::State bit, int width)
2088 {
2089 cover("kernel.rtlil.sigspec.init.state");
2090
2091 chunks_.push_back(RTLIL::SigChunk(bit, width));
2092 width_ = width;
2093 hash_ = 0;
2094 check();
2095 }
2096
2097 RTLIL::SigSpec::SigSpec(RTLIL::SigBit bit, int width)
2098 {
2099 cover("kernel.rtlil.sigspec.init.bit");
2100
2101 if (bit.wire == NULL)
2102 chunks_.push_back(RTLIL::SigChunk(bit.data, width));
2103 else
2104 for (int i = 0; i < width; i++)
2105 chunks_.push_back(bit);
2106 width_ = width;
2107 hash_ = 0;
2108 check();
2109 }
2110
2111 RTLIL::SigSpec::SigSpec(std::vector<RTLIL::SigChunk> chunks)
2112 {
2113 cover("kernel.rtlil.sigspec.init.stdvec_chunks");
2114
2115 width_ = 0;
2116 hash_ = 0;
2117 for (auto &c : chunks)
2118 append(c);
2119 check();
2120 }
2121
2122 RTLIL::SigSpec::SigSpec(std::vector<RTLIL::SigBit> bits)
2123 {
2124 cover("kernel.rtlil.sigspec.init.stdvec_bits");
2125
2126 width_ = 0;
2127 hash_ = 0;
2128 for (auto &bit : bits)
2129 append_bit(bit);
2130 check();
2131 }
2132
2133 RTLIL::SigSpec::SigSpec(std::set<RTLIL::SigBit> bits)
2134 {
2135 cover("kernel.rtlil.sigspec.init.stdset_bits");
2136
2137 width_ = 0;
2138 hash_ = 0;
2139 for (auto &bit : bits)
2140 append_bit(bit);
2141 check();
2142 }
2143
2144 void RTLIL::SigSpec::pack() const
2145 {
2146 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
2147
2148 if (that->bits_.empty())
2149 return;
2150
2151 cover("kernel.rtlil.sigspec.convert.pack");
2152 log_assert(that->chunks_.empty());
2153
2154 std::vector<RTLIL::SigBit> old_bits;
2155 old_bits.swap(that->bits_);
2156
2157 RTLIL::SigChunk *last = NULL;
2158 int last_end_offset = 0;
2159
2160 for (auto &bit : old_bits) {
2161 if (last && bit.wire == last->wire) {
2162 if (bit.wire == NULL) {
2163 last->data.push_back(bit.data);
2164 last->width++;
2165 continue;
2166 } else if (last_end_offset == bit.offset) {
2167 last_end_offset++;
2168 last->width++;
2169 continue;
2170 }
2171 }
2172 that->chunks_.push_back(bit);
2173 last = &that->chunks_.back();
2174 last_end_offset = bit.offset + 1;
2175 }
2176
2177 check();
2178 }
2179
2180 void RTLIL::SigSpec::unpack() const
2181 {
2182 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
2183
2184 if (that->chunks_.empty())
2185 return;
2186
2187 cover("kernel.rtlil.sigspec.convert.unpack");
2188 log_assert(that->bits_.empty());
2189
2190 that->bits_.reserve(that->width_);
2191 for (auto &c : that->chunks_)
2192 for (int i = 0; i < c.width; i++)
2193 that->bits_.push_back(RTLIL::SigBit(c, i));
2194
2195 that->chunks_.clear();
2196 that->hash_ = 0;
2197 }
2198
2199 #define DJB2(_hash, _value) do { (_hash) = (((_hash) << 5) + (_hash)) + (_value); } while (0)
2200
2201 void RTLIL::SigSpec::hash() const
2202 {
2203 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
2204
2205 if (that->hash_ != 0)
2206 return;
2207
2208 cover("kernel.rtlil.sigspec.hash");
2209 that->pack();
2210
2211 that->hash_ = 5381;
2212 for (auto &c : that->chunks_)
2213 if (c.wire == NULL) {
2214 for (auto &v : c.data)
2215 DJB2(that->hash_, v);
2216 } else {
2217 DJB2(that->hash_, c.wire->name.index_);
2218 DJB2(that->hash_, c.offset);
2219 DJB2(that->hash_, c.width);
2220 }
2221
2222 if (that->hash_ == 0)
2223 that->hash_ = 1;
2224 }
2225
2226 void RTLIL::SigSpec::sort()
2227 {
2228 unpack();
2229 cover("kernel.rtlil.sigspec.sort");
2230 std::sort(bits_.begin(), bits_.end());
2231 }
2232
2233 void RTLIL::SigSpec::sort_and_unify()
2234 {
2235 cover("kernel.rtlil.sigspec.sort_and_unify");
2236 *this = this->to_sigbit_set();
2237 }
2238
2239 void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with)
2240 {
2241 replace(pattern, with, this);
2242 }
2243
2244 void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with, RTLIL::SigSpec *other) const
2245 {
2246 log_assert(pattern.width_ == with.width_);
2247
2248 pattern.unpack();
2249 with.unpack();
2250
2251 std::map<RTLIL::SigBit, RTLIL::SigBit> rules;
2252
2253 for (int i = 0; i < SIZE(pattern.bits_); i++)
2254 if (pattern.bits_[i].wire != NULL)
2255 rules[pattern.bits_[i]] = with.bits_[i];
2256
2257 replace(rules, other);
2258 }
2259
2260 void RTLIL::SigSpec::replace(const std::map<RTLIL::SigBit, RTLIL::SigBit> &rules)
2261 {
2262 replace(rules, this);
2263 }
2264
2265 void RTLIL::SigSpec::replace(const std::map<RTLIL::SigBit, RTLIL::SigBit> &rules, RTLIL::SigSpec *other) const
2266 {
2267 cover("kernel.rtlil.sigspec.replace");
2268
2269 log_assert(other != NULL);
2270 log_assert(width_ == other->width_);
2271
2272 unpack();
2273 other->unpack();
2274
2275 for (int i = 0; i < SIZE(bits_); i++) {
2276 auto it = rules.find(bits_[i]);
2277 if (it != rules.end())
2278 other->bits_[i] = it->second;
2279 }
2280
2281 other->check();
2282 }
2283
2284 void RTLIL::SigSpec::remove(const RTLIL::SigSpec &pattern)
2285 {
2286 remove2(pattern, NULL);
2287 }
2288
2289 void RTLIL::SigSpec::remove(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other) const
2290 {
2291 RTLIL::SigSpec tmp = *this;
2292 tmp.remove2(pattern, other);
2293 }
2294
2295 void RTLIL::SigSpec::remove2(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other)
2296 {
2297 std::set<RTLIL::SigBit> pattern_bits = pattern.to_sigbit_set();
2298 remove2(pattern_bits, other);
2299 }
2300
2301 void RTLIL::SigSpec::remove(const std::set<RTLIL::SigBit> &pattern)
2302 {
2303 remove2(pattern, NULL);
2304 }
2305
2306 void RTLIL::SigSpec::remove(const std::set<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other) const
2307 {
2308 RTLIL::SigSpec tmp = *this;
2309 tmp.remove2(pattern, other);
2310 }
2311
2312 void RTLIL::SigSpec::remove2(const std::set<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other)
2313 {
2314 if (other)
2315 cover("kernel.rtlil.sigspec.remove_other");
2316 else
2317 cover("kernel.rtlil.sigspec.remove");
2318
2319 unpack();
2320
2321 if (other != NULL) {
2322 log_assert(width_ == other->width_);
2323 other->unpack();
2324 }
2325
2326 std::vector<RTLIL::SigBit> new_bits, new_other_bits;
2327
2328 new_bits.resize(SIZE(bits_));
2329 if (other != NULL)
2330 new_other_bits.resize(SIZE(bits_));
2331
2332 int k = 0;
2333 for (int i = 0; i < SIZE(bits_); i++) {
2334 if (bits_[i].wire != NULL && pattern.count(bits_[i]))
2335 continue;
2336 if (other != NULL)
2337 new_other_bits[k] = other->bits_[i];
2338 new_bits[k++] = bits_[i];
2339 }
2340
2341 new_bits.resize(k);
2342 if (other != NULL)
2343 new_other_bits.resize(k);
2344
2345 bits_.swap(new_bits);
2346 width_ = SIZE(bits_);
2347
2348 if (other != NULL) {
2349 other->bits_.swap(new_other_bits);
2350 other->width_ = SIZE(other->bits_);
2351 }
2352
2353 check();
2354 }
2355
2356 RTLIL::SigSpec RTLIL::SigSpec::extract(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec *other) const
2357 {
2358 std::set<RTLIL::SigBit> pattern_bits = pattern.to_sigbit_set();
2359 return extract(pattern_bits, other);
2360 }
2361
2362 RTLIL::SigSpec RTLIL::SigSpec::extract(const std::set<RTLIL::SigBit> &pattern, const RTLIL::SigSpec *other) const
2363 {
2364 if (other)
2365 cover("kernel.rtlil.sigspec.extract_other");
2366 else
2367 cover("kernel.rtlil.sigspec.extract");
2368
2369 log_assert(other == NULL || width_ == other->width_);
2370
2371 std::vector<RTLIL::SigBit> bits_match = to_sigbit_vector();
2372 RTLIL::SigSpec ret;
2373
2374 if (other) {
2375 std::vector<RTLIL::SigBit> bits_other = other->to_sigbit_vector();
2376 for (int i = 0; i < width_; i++)
2377 if (bits_match[i].wire && pattern.count(bits_match[i]))
2378 ret.append_bit(bits_other[i]);
2379 } else {
2380 for (int i = 0; i < width_; i++)
2381 if (bits_match[i].wire && pattern.count(bits_match[i]))
2382 ret.append_bit(bits_match[i]);
2383 }
2384
2385 ret.check();
2386 return ret;
2387 }
2388
2389 void RTLIL::SigSpec::replace(int offset, const RTLIL::SigSpec &with)
2390 {
2391 cover("kernel.rtlil.sigspec.replace_pos");
2392
2393 unpack();
2394 with.unpack();
2395
2396 log_assert(offset >= 0);
2397 log_assert(with.width_ >= 0);
2398 log_assert(offset+with.width_ <= width_);
2399
2400 for (int i = 0; i < with.width_; i++)
2401 bits_.at(offset + i) = with.bits_.at(i);
2402
2403 check();
2404 }
2405
2406 void RTLIL::SigSpec::remove_const()
2407 {
2408 if (packed())
2409 {
2410 cover("kernel.rtlil.sigspec.remove_const.packed");
2411
2412 std::vector<RTLIL::SigChunk> new_chunks;
2413 new_chunks.reserve(SIZE(chunks_));
2414
2415 width_ = 0;
2416 for (auto &chunk : chunks_)
2417 if (chunk.wire != NULL) {
2418 new_chunks.push_back(chunk);
2419 width_ += chunk.width;
2420 }
2421
2422 chunks_.swap(new_chunks);
2423 }
2424 else
2425 {
2426 cover("kernel.rtlil.sigspec.remove_const.unpacked");
2427
2428 std::vector<RTLIL::SigBit> new_bits;
2429 new_bits.reserve(width_);
2430
2431 for (auto &bit : bits_)
2432 if (bit.wire != NULL)
2433 new_bits.push_back(bit);
2434
2435 bits_.swap(new_bits);
2436 width_ = bits_.size();
2437 }
2438
2439 check();
2440 }
2441
2442 void RTLIL::SigSpec::remove(int offset, int length)
2443 {
2444 cover("kernel.rtlil.sigspec.remove_pos");
2445
2446 unpack();
2447
2448 log_assert(offset >= 0);
2449 log_assert(length >= 0);
2450 log_assert(offset + length <= width_);
2451
2452 bits_.erase(bits_.begin() + offset, bits_.begin() + offset + length);
2453 width_ = bits_.size();
2454
2455 check();
2456 }
2457
2458 RTLIL::SigSpec RTLIL::SigSpec::extract(int offset, int length) const
2459 {
2460 unpack();
2461 cover("kernel.rtlil.sigspec.extract_pos");
2462 return std::vector<RTLIL::SigBit>(bits_.begin() + offset, bits_.begin() + offset + length);
2463 }
2464
2465 void RTLIL::SigSpec::append(const RTLIL::SigSpec &signal)
2466 {
2467 if (signal.width_ == 0)
2468 return;
2469
2470 if (width_ == 0) {
2471 *this = signal;
2472 return;
2473 }
2474
2475 cover("kernel.rtlil.sigspec.append");
2476
2477 if (packed() != signal.packed()) {
2478 pack();
2479 signal.pack();
2480 }
2481
2482 if (packed())
2483 for (auto &other_c : signal.chunks_)
2484 {
2485 auto &my_last_c = chunks_.back();
2486 if (my_last_c.wire == NULL && other_c.wire == NULL) {
2487 auto &this_data = my_last_c.data;
2488 auto &other_data = other_c.data;
2489 this_data.insert(this_data.end(), other_data.begin(), other_data.end());
2490 my_last_c.width += other_c.width;
2491 } else
2492 if (my_last_c.wire == other_c.wire && my_last_c.offset + my_last_c.width == other_c.offset) {
2493 my_last_c.width += other_c.width;
2494 } else
2495 chunks_.push_back(other_c);
2496 }
2497 else
2498 bits_.insert(bits_.end(), signal.bits_.begin(), signal.bits_.end());
2499
2500 width_ += signal.width_;
2501 check();
2502 }
2503
2504 void RTLIL::SigSpec::append_bit(const RTLIL::SigBit &bit)
2505 {
2506 if (packed())
2507 {
2508 cover("kernel.rtlil.sigspec.append_bit.packed");
2509
2510 if (chunks_.size() == 0)
2511 chunks_.push_back(bit);
2512 else
2513 if (bit.wire == NULL)
2514 if (chunks_.back().wire == NULL) {
2515 chunks_.back().data.push_back(bit.data);
2516 chunks_.back().width++;
2517 } else
2518 chunks_.push_back(bit);
2519 else
2520 if (chunks_.back().wire == bit.wire && chunks_.back().offset + chunks_.back().width == bit.offset)
2521 chunks_.back().width++;
2522 else
2523 chunks_.push_back(bit);
2524 }
2525 else
2526 {
2527 cover("kernel.rtlil.sigspec.append_bit.unpacked");
2528 bits_.push_back(bit);
2529 }
2530
2531 width_++;
2532 check();
2533 }
2534
2535 void RTLIL::SigSpec::extend(int width, bool is_signed)
2536 {
2537 cover("kernel.rtlil.sigspec.extend");
2538
2539 pack();
2540
2541 if (width_ > width)
2542 remove(width, width_ - width);
2543
2544 if (width_ < width) {
2545 RTLIL::SigSpec padding = width_ > 0 ? extract(width_ - 1, 1) : RTLIL::SigSpec(RTLIL::State::S0);
2546 if (!is_signed && padding != RTLIL::SigSpec(RTLIL::State::Sx) && padding != RTLIL::SigSpec(RTLIL::State::Sz) &&
2547 padding != RTLIL::SigSpec(RTLIL::State::Sa) && padding != RTLIL::SigSpec(RTLIL::State::Sm))
2548 padding = RTLIL::SigSpec(RTLIL::State::S0);
2549 while (width_ < width)
2550 append(padding);
2551 }
2552 }
2553
2554 void RTLIL::SigSpec::extend_u0(int width, bool is_signed)
2555 {
2556 cover("kernel.rtlil.sigspec.extend_u0");
2557
2558 pack();
2559
2560 if (width_ > width)
2561 remove(width, width_ - width);
2562
2563 if (width_ < width) {
2564 RTLIL::SigSpec padding = width_ > 0 ? extract(width_ - 1, 1) : RTLIL::SigSpec(RTLIL::State::S0);
2565 if (!is_signed)
2566 padding = RTLIL::SigSpec(RTLIL::State::S0);
2567 while (width_ < width)
2568 append(padding);
2569 }
2570
2571 }
2572
2573 RTLIL::SigSpec RTLIL::SigSpec::repeat(int num) const
2574 {
2575 cover("kernel.rtlil.sigspec.repeat");
2576
2577 RTLIL::SigSpec sig;
2578 for (int i = 0; i < num; i++)
2579 sig.append(*this);
2580 return sig;
2581 }
2582
2583 #ifndef NDEBUG
2584 void RTLIL::SigSpec::check() const
2585 {
2586 if (width_ > 64)
2587 {
2588 cover("kernel.rtlil.sigspec.check.skip");
2589 }
2590 else if (packed())
2591 {
2592 cover("kernel.rtlil.sigspec.check.packed");
2593
2594 int w = 0;
2595 for (size_t i = 0; i < chunks_.size(); i++) {
2596 const RTLIL::SigChunk chunk = chunks_[i];
2597 if (chunk.wire == NULL) {
2598 if (i > 0)
2599 log_assert(chunks_[i-1].wire != NULL);
2600 log_assert(chunk.offset == 0);
2601 log_assert(chunk.data.size() == (size_t)chunk.width);
2602 } else {
2603 if (i > 0 && chunks_[i-1].wire == chunk.wire)
2604 log_assert(chunk.offset != chunks_[i-1].offset + chunks_[i-1].width);
2605 log_assert(chunk.offset >= 0);
2606 log_assert(chunk.width >= 0);
2607 log_assert(chunk.offset + chunk.width <= chunk.wire->width);
2608 log_assert(chunk.data.size() == 0);
2609 }
2610 w += chunk.width;
2611 }
2612 log_assert(w == width_);
2613 log_assert(bits_.empty());
2614 }
2615 else
2616 {
2617 cover("kernel.rtlil.sigspec.check.unpacked");
2618
2619 log_assert(width_ == SIZE(bits_));
2620 log_assert(chunks_.empty());
2621 }
2622 }
2623 #endif
2624
2625 bool RTLIL::SigSpec::operator <(const RTLIL::SigSpec &other) const
2626 {
2627 cover("kernel.rtlil.sigspec.comp_lt");
2628
2629 if (this == &other)
2630 return false;
2631
2632 if (width_ != other.width_)
2633 return width_ < other.width_;
2634
2635 pack();
2636 other.pack();
2637
2638 if (chunks_.size() != other.chunks_.size())
2639 return chunks_.size() < other.chunks_.size();
2640
2641 hash();
2642 other.hash();
2643
2644 if (hash_ != other.hash_)
2645 return hash_ < other.hash_;
2646
2647 for (size_t i = 0; i < chunks_.size(); i++)
2648 if (chunks_[i] != other.chunks_[i]) {
2649 cover("kernel.rtlil.sigspec.comp_lt.hash_collision");
2650 return chunks_[i] < other.chunks_[i];
2651 }
2652
2653 cover("kernel.rtlil.sigspec.comp_lt.equal");
2654 return false;
2655 }
2656
2657 bool RTLIL::SigSpec::operator ==(const RTLIL::SigSpec &other) const
2658 {
2659 cover("kernel.rtlil.sigspec.comp_eq");
2660
2661 if (this == &other)
2662 return true;
2663
2664 if (width_ != other.width_)
2665 return false;
2666
2667 pack();
2668 other.pack();
2669
2670 if (chunks_.size() != chunks_.size())
2671 return false;
2672
2673 hash();
2674 other.hash();
2675
2676 if (hash_ != other.hash_)
2677 return false;
2678
2679 for (size_t i = 0; i < chunks_.size(); i++)
2680 if (chunks_[i] != other.chunks_[i]) {
2681 cover("kernel.rtlil.sigspec.comp_eq.hash_collision");
2682 return false;
2683 }
2684
2685 cover("kernel.rtlil.sigspec.comp_eq.equal");
2686 return true;
2687 }
2688
2689 bool RTLIL::SigSpec::is_wire() const
2690 {
2691 cover("kernel.rtlil.sigspec.is_wire");
2692
2693 pack();
2694 return SIZE(chunks_) == 1 && chunks_[0].wire && chunks_[0].wire->width == width_;
2695 }
2696
2697 bool RTLIL::SigSpec::is_chunk() const
2698 {
2699 cover("kernel.rtlil.sigspec.is_chunk");
2700
2701 pack();
2702 return SIZE(chunks_) == 1;
2703 }
2704
2705 bool RTLIL::SigSpec::is_fully_const() const
2706 {
2707 cover("kernel.rtlil.sigspec.is_fully_const");
2708
2709 pack();
2710 for (auto it = chunks_.begin(); it != chunks_.end(); it++)
2711 if (it->width > 0 && it->wire != NULL)
2712 return false;
2713 return true;
2714 }
2715
2716 bool RTLIL::SigSpec::is_fully_def() const
2717 {
2718 cover("kernel.rtlil.sigspec.is_fully_def");
2719
2720 pack();
2721 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
2722 if (it->width > 0 && it->wire != NULL)
2723 return false;
2724 for (size_t i = 0; i < it->data.size(); i++)
2725 if (it->data[i] != RTLIL::State::S0 && it->data[i] != RTLIL::State::S1)
2726 return false;
2727 }
2728 return true;
2729 }
2730
2731 bool RTLIL::SigSpec::is_fully_undef() const
2732 {
2733 cover("kernel.rtlil.sigspec.is_fully_undef");
2734
2735 pack();
2736 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
2737 if (it->width > 0 && it->wire != NULL)
2738 return false;
2739 for (size_t i = 0; i < it->data.size(); i++)
2740 if (it->data[i] != RTLIL::State::Sx && it->data[i] != RTLIL::State::Sz)
2741 return false;
2742 }
2743 return true;
2744 }
2745
2746 bool RTLIL::SigSpec::has_marked_bits() const
2747 {
2748 cover("kernel.rtlil.sigspec.has_marked_bits");
2749
2750 pack();
2751 for (auto it = chunks_.begin(); it != chunks_.end(); it++)
2752 if (it->width > 0 && it->wire == NULL) {
2753 for (size_t i = 0; i < it->data.size(); i++)
2754 if (it->data[i] == RTLIL::State::Sm)
2755 return true;
2756 }
2757 return false;
2758 }
2759
2760 bool RTLIL::SigSpec::as_bool() const
2761 {
2762 cover("kernel.rtlil.sigspec.as_bool");
2763
2764 pack();
2765 log_assert(is_fully_const() && SIZE(chunks_) <= 1);
2766 if (width_)
2767 return RTLIL::Const(chunks_[0].data).as_bool();
2768 return false;
2769 }
2770
2771 int RTLIL::SigSpec::as_int(bool is_signed) const
2772 {
2773 cover("kernel.rtlil.sigspec.as_int");
2774
2775 pack();
2776 log_assert(is_fully_const() && SIZE(chunks_) <= 1);
2777 if (width_)
2778 return RTLIL::Const(chunks_[0].data).as_int(is_signed);
2779 return 0;
2780 }
2781
2782 std::string RTLIL::SigSpec::as_string() const
2783 {
2784 cover("kernel.rtlil.sigspec.as_string");
2785
2786 pack();
2787 std::string str;
2788 for (size_t i = chunks_.size(); i > 0; i--) {
2789 const RTLIL::SigChunk &chunk = chunks_[i-1];
2790 if (chunk.wire != NULL)
2791 for (int j = 0; j < chunk.width; j++)
2792 str += "?";
2793 else
2794 str += RTLIL::Const(chunk.data).as_string();
2795 }
2796 return str;
2797 }
2798
2799 RTLIL::Const RTLIL::SigSpec::as_const() const
2800 {
2801 cover("kernel.rtlil.sigspec.as_const");
2802
2803 pack();
2804 log_assert(is_fully_const() && SIZE(chunks_) <= 1);
2805 if (width_)
2806 return chunks_[0].data;
2807 return RTLIL::Const();
2808 }
2809
2810 RTLIL::Wire *RTLIL::SigSpec::as_wire() const
2811 {
2812 cover("kernel.rtlil.sigspec.as_wire");
2813
2814 pack();
2815 log_assert(is_wire());
2816 return chunks_[0].wire;
2817 }
2818
2819 RTLIL::SigChunk RTLIL::SigSpec::as_chunk() const
2820 {
2821 cover("kernel.rtlil.sigspec.as_chunk");
2822
2823 pack();
2824 log_assert(is_chunk());
2825 return chunks_[0];
2826 }
2827
2828 bool RTLIL::SigSpec::match(std::string pattern) const
2829 {
2830 cover("kernel.rtlil.sigspec.match");
2831
2832 pack();
2833 std::string str = as_string();
2834 log_assert(pattern.size() == str.size());
2835
2836 for (size_t i = 0; i < pattern.size(); i++) {
2837 if (pattern[i] == ' ')
2838 continue;
2839 if (pattern[i] == '*') {
2840 if (str[i] != 'z' && str[i] != 'x')
2841 return false;
2842 continue;
2843 }
2844 if (pattern[i] != str[i])
2845 return false;
2846 }
2847
2848 return true;
2849 }
2850
2851 std::set<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_set() const
2852 {
2853 cover("kernel.rtlil.sigspec.to_sigbit_set");
2854
2855 pack();
2856 std::set<RTLIL::SigBit> sigbits;
2857 for (auto &c : chunks_)
2858 for (int i = 0; i < c.width; i++)
2859 sigbits.insert(RTLIL::SigBit(c, i));
2860 return sigbits;
2861 }
2862
2863 std::vector<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_vector() const
2864 {
2865 cover("kernel.rtlil.sigspec.to_sigbit_vector");
2866
2867 unpack();
2868 return bits_;
2869 }
2870
2871 std::map<RTLIL::SigBit, RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_map(const RTLIL::SigSpec &other) const
2872 {
2873 cover("kernel.rtlil.sigspec.to_sigbit_map");
2874
2875 unpack();
2876 other.unpack();
2877
2878 log_assert(width_ == other.width_);
2879
2880 std::map<RTLIL::SigBit, RTLIL::SigBit> new_map;
2881 for (int i = 0; i < width_; i++)
2882 new_map[bits_[i]] = other.bits_[i];
2883
2884 return new_map;
2885 }
2886
2887 RTLIL::SigBit RTLIL::SigSpec::to_single_sigbit() const
2888 {
2889 cover("kernel.rtlil.sigspec.to_single_sigbit");
2890
2891 pack();
2892 log_assert(width_ == 1);
2893 for (auto &c : chunks_)
2894 if (c.width)
2895 return RTLIL::SigBit(c);
2896 log_abort();
2897 }
2898
2899 static void sigspec_parse_split(std::vector<std::string> &tokens, const std::string &text, char sep)
2900 {
2901 size_t start = 0, end = 0;
2902 while ((end = text.find(sep, start)) != std::string::npos) {
2903 tokens.push_back(text.substr(start, end - start));
2904 start = end + 1;
2905 }
2906 tokens.push_back(text.substr(start));
2907 }
2908
2909 static int sigspec_parse_get_dummy_line_num()
2910 {
2911 return 0;
2912 }
2913
2914 bool RTLIL::SigSpec::parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str)
2915 {
2916 cover("kernel.rtlil.sigspec.parse");
2917
2918 std::vector<std::string> tokens;
2919 sigspec_parse_split(tokens, str, ',');
2920
2921 sig = RTLIL::SigSpec();
2922 for (int tokidx = int(tokens.size())-1; tokidx >= 0; tokidx--)
2923 {
2924 std::string netname = tokens[tokidx];
2925 std::string indices;
2926
2927 if (netname.size() == 0)
2928 continue;
2929
2930 if ('0' <= netname[0] && netname[0] <= '9') {
2931 cover("kernel.rtlil.sigspec.parse.const");
2932 AST::get_line_num = sigspec_parse_get_dummy_line_num;
2933 AST::AstNode *ast = VERILOG_FRONTEND::const2ast(netname);
2934 if (ast == NULL)
2935 return false;
2936 sig.append(RTLIL::Const(ast->bits));
2937 delete ast;
2938 continue;
2939 }
2940
2941 if (module == NULL)
2942 return false;
2943
2944 cover("kernel.rtlil.sigspec.parse.net");
2945
2946 if (netname[0] != '$' && netname[0] != '\\')
2947 netname = "\\" + netname;
2948
2949 if (module->wires_.count(netname) == 0) {
2950 size_t indices_pos = netname.size()-1;
2951 if (indices_pos > 2 && netname[indices_pos] == ']')
2952 {
2953 indices_pos--;
2954 while (indices_pos > 0 && ('0' <= netname[indices_pos] && netname[indices_pos] <= '9')) indices_pos--;
2955 if (indices_pos > 0 && netname[indices_pos] == ':') {
2956 indices_pos--;
2957 while (indices_pos > 0 && ('0' <= netname[indices_pos] && netname[indices_pos] <= '9')) indices_pos--;
2958 }
2959 if (indices_pos > 0 && netname[indices_pos] == '[') {
2960 indices = netname.substr(indices_pos);
2961 netname = netname.substr(0, indices_pos);
2962 }
2963 }
2964 }
2965
2966 if (module->wires_.count(netname) == 0)
2967 return false;
2968
2969 RTLIL::Wire *wire = module->wires_.at(netname);
2970 if (!indices.empty()) {
2971 std::vector<std::string> index_tokens;
2972 sigspec_parse_split(index_tokens, indices.substr(1, indices.size()-2), ':');
2973 if (index_tokens.size() == 1) {
2974 cover("kernel.rtlil.sigspec.parse.bit_sel");
2975 sig.append(RTLIL::SigSpec(wire, atoi(index_tokens.at(0).c_str())));
2976 } else {
2977 cover("kernel.rtlil.sigspec.parse.part_sel");
2978 int a = atoi(index_tokens.at(0).c_str());
2979 int b = atoi(index_tokens.at(1).c_str());
2980 if (a > b) {
2981 int tmp = a;
2982 a = b, b = tmp;
2983 }
2984 sig.append(RTLIL::SigSpec(wire, a, b-a+1));
2985 }
2986 } else
2987 sig.append(wire);
2988 }
2989
2990 return true;
2991 }
2992
2993 bool RTLIL::SigSpec::parse_sel(RTLIL::SigSpec &sig, RTLIL::Design *design, RTLIL::Module *module, std::string str)
2994 {
2995 if (str.empty() || str[0] != '@')
2996 return parse(sig, module, str);
2997
2998 cover("kernel.rtlil.sigspec.parse.sel");
2999
3000 str = RTLIL::escape_id(str.substr(1));
3001 if (design->selection_vars.count(str) == 0)
3002 return false;
3003
3004 sig = RTLIL::SigSpec();
3005 RTLIL::Selection &sel = design->selection_vars.at(str);
3006 for (auto &it : module->wires_)
3007 if (sel.selected_member(module->name, it.first))
3008 sig.append(it.second);
3009
3010 return true;
3011 }
3012
3013 bool RTLIL::SigSpec::parse_rhs(const RTLIL::SigSpec &lhs, RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str)
3014 {
3015 if (str == "0") {
3016 cover("kernel.rtlil.sigspec.parse.rhs_zeros");
3017 sig = RTLIL::SigSpec(RTLIL::State::S0, lhs.width_);
3018 return true;
3019 }
3020
3021 if (str == "~0") {
3022 cover("kernel.rtlil.sigspec.parse.rhs_ones");
3023 sig = RTLIL::SigSpec(RTLIL::State::S1, lhs.width_);
3024 return true;
3025 }
3026
3027 if (lhs.chunks_.size() == 1) {
3028 char *p = (char*)str.c_str(), *endptr;
3029 long long int val = strtoll(p, &endptr, 10);
3030 if (endptr && endptr != p && *endptr == 0) {
3031 sig = RTLIL::SigSpec(val, lhs.width_);
3032 cover("kernel.rtlil.sigspec.parse.rhs_dec");
3033 return true;
3034 }
3035 }
3036
3037 return parse(sig, module, str);
3038 }
3039
3040 RTLIL::CaseRule::~CaseRule()
3041 {
3042 for (auto it = switches.begin(); it != switches.end(); it++)
3043 delete *it;
3044 }
3045
3046 RTLIL::CaseRule *RTLIL::CaseRule::clone() const
3047 {
3048 RTLIL::CaseRule *new_caserule = new RTLIL::CaseRule;
3049 new_caserule->compare = compare;
3050 new_caserule->actions = actions;
3051 for (auto &it : switches)
3052 new_caserule->switches.push_back(it->clone());
3053 return new_caserule;
3054 }
3055
3056 RTLIL::SwitchRule::~SwitchRule()
3057 {
3058 for (auto it = cases.begin(); it != cases.end(); it++)
3059 delete *it;
3060 }
3061
3062 RTLIL::SwitchRule *RTLIL::SwitchRule::clone() const
3063 {
3064 RTLIL::SwitchRule *new_switchrule = new RTLIL::SwitchRule;
3065 new_switchrule->signal = signal;
3066 new_switchrule->attributes = attributes;
3067 for (auto &it : cases)
3068 new_switchrule->cases.push_back(it->clone());
3069 return new_switchrule;
3070
3071 }
3072
3073 RTLIL::SyncRule *RTLIL::SyncRule::clone() const
3074 {
3075 RTLIL::SyncRule *new_syncrule = new RTLIL::SyncRule;
3076 new_syncrule->type = type;
3077 new_syncrule->signal = signal;
3078 new_syncrule->actions = actions;
3079 return new_syncrule;
3080 }
3081
3082 RTLIL::Process::~Process()
3083 {
3084 for (auto it = syncs.begin(); it != syncs.end(); it++)
3085 delete *it;
3086 }
3087
3088 RTLIL::Process *RTLIL::Process::clone() const
3089 {
3090 RTLIL::Process *new_proc = new RTLIL::Process;
3091
3092 new_proc->name = name;
3093 new_proc->attributes = attributes;
3094
3095 RTLIL::CaseRule *rc_ptr = root_case.clone();
3096 new_proc->root_case = *rc_ptr;
3097 rc_ptr->switches.clear();
3098 delete rc_ptr;
3099
3100 for (auto &it : syncs)
3101 new_proc->syncs.push_back(it->clone());
3102
3103 return new_proc;
3104 }
3105
3106 YOSYS_NAMESPACE_END
3107