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Merge pull request #820 from YosysHQ/clifford/fix810
[yosys.git] / kernel / rtlil.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 #include "kernel/yosys.h"
21 #include "kernel/macc.h"
22 #include "kernel/celltypes.h"
23 #include "frontends/verilog/verilog_frontend.h"
24 #include "backends/ilang/ilang_backend.h"
25
26 #include <string.h>
27 #include <algorithm>
28
29 YOSYS_NAMESPACE_BEGIN
30
31 RTLIL::IdString::destruct_guard_t RTLIL::IdString::destruct_guard;
32 std::vector<int> RTLIL::IdString::global_refcount_storage_;
33 std::vector<char*> RTLIL::IdString::global_id_storage_;
34 dict<char*, int, hash_cstr_ops> RTLIL::IdString::global_id_index_;
35 std::vector<int> RTLIL::IdString::global_free_idx_list_;
36
37 RTLIL::Const::Const()
38 {
39 flags = RTLIL::CONST_FLAG_NONE;
40 }
41
42 RTLIL::Const::Const(std::string str)
43 {
44 flags = RTLIL::CONST_FLAG_STRING;
45 for (int i = str.size()-1; i >= 0; i--) {
46 unsigned char ch = str[i];
47 for (int j = 0; j < 8; j++) {
48 bits.push_back((ch & 1) != 0 ? RTLIL::S1 : RTLIL::S0);
49 ch = ch >> 1;
50 }
51 }
52 }
53
54 RTLIL::Const::Const(int val, int width)
55 {
56 flags = RTLIL::CONST_FLAG_NONE;
57 for (int i = 0; i < width; i++) {
58 bits.push_back((val & 1) != 0 ? RTLIL::S1 : RTLIL::S0);
59 val = val >> 1;
60 }
61 }
62
63 RTLIL::Const::Const(RTLIL::State bit, int width)
64 {
65 flags = RTLIL::CONST_FLAG_NONE;
66 for (int i = 0; i < width; i++)
67 bits.push_back(bit);
68 }
69
70 RTLIL::Const::Const(const std::vector<bool> &bits)
71 {
72 flags = RTLIL::CONST_FLAG_NONE;
73 for (auto b : bits)
74 this->bits.push_back(b ? RTLIL::S1 : RTLIL::S0);
75 }
76
77 bool RTLIL::Const::operator <(const RTLIL::Const &other) const
78 {
79 if (bits.size() != other.bits.size())
80 return bits.size() < other.bits.size();
81 for (size_t i = 0; i < bits.size(); i++)
82 if (bits[i] != other.bits[i])
83 return bits[i] < other.bits[i];
84 return false;
85 }
86
87 bool RTLIL::Const::operator ==(const RTLIL::Const &other) const
88 {
89 return bits == other.bits;
90 }
91
92 bool RTLIL::Const::operator !=(const RTLIL::Const &other) const
93 {
94 return bits != other.bits;
95 }
96
97 bool RTLIL::Const::as_bool() const
98 {
99 for (size_t i = 0; i < bits.size(); i++)
100 if (bits[i] == RTLIL::S1)
101 return true;
102 return false;
103 }
104
105 int RTLIL::Const::as_int(bool is_signed) const
106 {
107 int32_t ret = 0;
108 for (size_t i = 0; i < bits.size() && i < 32; i++)
109 if (bits[i] == RTLIL::S1)
110 ret |= 1 << i;
111 if (is_signed && bits.back() == RTLIL::S1)
112 for (size_t i = bits.size(); i < 32; i++)
113 ret |= 1 << i;
114 return ret;
115 }
116
117 std::string RTLIL::Const::as_string() const
118 {
119 std::string ret;
120 for (size_t i = bits.size(); i > 0; i--)
121 switch (bits[i-1]) {
122 case S0: ret += "0"; break;
123 case S1: ret += "1"; break;
124 case Sx: ret += "x"; break;
125 case Sz: ret += "z"; break;
126 case Sa: ret += "-"; break;
127 case Sm: ret += "m"; break;
128 }
129 return ret;
130 }
131
132 RTLIL::Const RTLIL::Const::from_string(std::string str)
133 {
134 Const c;
135 for (auto it = str.rbegin(); it != str.rend(); it++)
136 switch (*it) {
137 case '0': c.bits.push_back(State::S0); break;
138 case '1': c.bits.push_back(State::S1); break;
139 case 'x': c.bits.push_back(State::Sx); break;
140 case 'z': c.bits.push_back(State::Sz); break;
141 case 'm': c.bits.push_back(State::Sm); break;
142 default: c.bits.push_back(State::Sa);
143 }
144 return c;
145 }
146
147 std::string RTLIL::Const::decode_string() const
148 {
149 std::string string;
150 std::vector<char> string_chars;
151 for (int i = 0; i < int (bits.size()); i += 8) {
152 char ch = 0;
153 for (int j = 0; j < 8 && i + j < int (bits.size()); j++)
154 if (bits[i + j] == RTLIL::State::S1)
155 ch |= 1 << j;
156 if (ch != 0)
157 string_chars.push_back(ch);
158 }
159 for (int i = int (string_chars.size()) - 1; i >= 0; i--)
160 string += string_chars[i];
161 return string;
162 }
163
164 bool RTLIL::Const::is_fully_zero() const
165 {
166 cover("kernel.rtlil.const.is_fully_zero");
167
168 for (auto bit : bits)
169 if (bit != RTLIL::State::S0)
170 return false;
171
172 return true;
173 }
174
175 bool RTLIL::Const::is_fully_ones() const
176 {
177 cover("kernel.rtlil.const.is_fully_ones");
178
179 for (auto bit : bits)
180 if (bit != RTLIL::State::S1)
181 return false;
182
183 return true;
184 }
185
186 bool RTLIL::Const::is_fully_def() const
187 {
188 cover("kernel.rtlil.const.is_fully_def");
189
190 for (auto bit : bits)
191 if (bit != RTLIL::State::S0 && bit != RTLIL::State::S1)
192 return false;
193
194 return true;
195 }
196
197 bool RTLIL::Const::is_fully_undef() const
198 {
199 cover("kernel.rtlil.const.is_fully_undef");
200
201 for (auto bit : bits)
202 if (bit != RTLIL::State::Sx && bit != RTLIL::State::Sz)
203 return false;
204
205 return true;
206 }
207
208 void RTLIL::AttrObject::set_bool_attribute(RTLIL::IdString id)
209 {
210 attributes[id] = RTLIL::Const(1);
211 }
212
213 bool RTLIL::AttrObject::get_bool_attribute(RTLIL::IdString id) const
214 {
215 if (attributes.count(id) == 0)
216 return false;
217 return attributes.at(id).as_bool();
218 }
219
220 void RTLIL::AttrObject::set_strpool_attribute(RTLIL::IdString id, const pool<string> &data)
221 {
222 string attrval;
223 for (auto &s : data) {
224 if (!attrval.empty())
225 attrval += "|";
226 attrval += s;
227 }
228 attributes[id] = RTLIL::Const(attrval);
229 }
230
231 void RTLIL::AttrObject::add_strpool_attribute(RTLIL::IdString id, const pool<string> &data)
232 {
233 pool<string> union_data = get_strpool_attribute(id);
234 union_data.insert(data.begin(), data.end());
235 if (!union_data.empty())
236 set_strpool_attribute(id, union_data);
237 }
238
239 pool<string> RTLIL::AttrObject::get_strpool_attribute(RTLIL::IdString id) const
240 {
241 pool<string> data;
242 if (attributes.count(id) != 0)
243 for (auto s : split_tokens(attributes.at(id).decode_string(), "|"))
244 data.insert(s);
245 return data;
246 }
247
248 void RTLIL::AttrObject::set_src_attribute(const std::string &src)
249 {
250 if (src.empty())
251 attributes.erase("\\src");
252 else
253 attributes["\\src"] = src;
254 }
255
256 std::string RTLIL::AttrObject::get_src_attribute() const
257 {
258 std::string src;
259 if (attributes.count("\\src"))
260 src = attributes.at("\\src").decode_string();
261 return src;
262 }
263
264 bool RTLIL::Selection::selected_module(RTLIL::IdString mod_name) const
265 {
266 if (full_selection)
267 return true;
268 if (selected_modules.count(mod_name) > 0)
269 return true;
270 if (selected_members.count(mod_name) > 0)
271 return true;
272 return false;
273 }
274
275 bool RTLIL::Selection::selected_whole_module(RTLIL::IdString mod_name) const
276 {
277 if (full_selection)
278 return true;
279 if (selected_modules.count(mod_name) > 0)
280 return true;
281 return false;
282 }
283
284 bool RTLIL::Selection::selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const
285 {
286 if (full_selection)
287 return true;
288 if (selected_modules.count(mod_name) > 0)
289 return true;
290 if (selected_members.count(mod_name) > 0)
291 if (selected_members.at(mod_name).count(memb_name) > 0)
292 return true;
293 return false;
294 }
295
296 void RTLIL::Selection::optimize(RTLIL::Design *design)
297 {
298 if (full_selection) {
299 selected_modules.clear();
300 selected_members.clear();
301 return;
302 }
303
304 std::vector<RTLIL::IdString> del_list, add_list;
305
306 del_list.clear();
307 for (auto mod_name : selected_modules) {
308 if (design->modules_.count(mod_name) == 0)
309 del_list.push_back(mod_name);
310 selected_members.erase(mod_name);
311 }
312 for (auto mod_name : del_list)
313 selected_modules.erase(mod_name);
314
315 del_list.clear();
316 for (auto &it : selected_members)
317 if (design->modules_.count(it.first) == 0)
318 del_list.push_back(it.first);
319 for (auto mod_name : del_list)
320 selected_members.erase(mod_name);
321
322 for (auto &it : selected_members) {
323 del_list.clear();
324 for (auto memb_name : it.second)
325 if (design->modules_[it.first]->count_id(memb_name) == 0)
326 del_list.push_back(memb_name);
327 for (auto memb_name : del_list)
328 it.second.erase(memb_name);
329 }
330
331 del_list.clear();
332 add_list.clear();
333 for (auto &it : selected_members)
334 if (it.second.size() == 0)
335 del_list.push_back(it.first);
336 else if (it.second.size() == design->modules_[it.first]->wires_.size() + design->modules_[it.first]->memories.size() +
337 design->modules_[it.first]->cells_.size() + design->modules_[it.first]->processes.size())
338 add_list.push_back(it.first);
339 for (auto mod_name : del_list)
340 selected_members.erase(mod_name);
341 for (auto mod_name : add_list) {
342 selected_members.erase(mod_name);
343 selected_modules.insert(mod_name);
344 }
345
346 if (selected_modules.size() == design->modules_.size()) {
347 full_selection = true;
348 selected_modules.clear();
349 selected_members.clear();
350 }
351 }
352
353 RTLIL::Design::Design()
354 {
355 static unsigned int hashidx_count = 123456789;
356 hashidx_count = mkhash_xorshift(hashidx_count);
357 hashidx_ = hashidx_count;
358
359 refcount_modules_ = 0;
360 selection_stack.push_back(RTLIL::Selection());
361 }
362
363 RTLIL::Design::~Design()
364 {
365 for (auto it = modules_.begin(); it != modules_.end(); ++it)
366 delete it->second;
367 for (auto n : verilog_packages)
368 delete n;
369 for (auto n : verilog_globals)
370 delete n;
371 }
372
373 RTLIL::ObjRange<RTLIL::Module*> RTLIL::Design::modules()
374 {
375 return RTLIL::ObjRange<RTLIL::Module*>(&modules_, &refcount_modules_);
376 }
377
378 RTLIL::Module *RTLIL::Design::module(RTLIL::IdString name)
379 {
380 return modules_.count(name) ? modules_.at(name) : NULL;
381 }
382
383 RTLIL::Module *RTLIL::Design::top_module()
384 {
385 RTLIL::Module *module = nullptr;
386 int module_count = 0;
387
388 for (auto mod : selected_modules()) {
389 if (mod->get_bool_attribute("\\top"))
390 return mod;
391 module_count++;
392 module = mod;
393 }
394
395 return module_count == 1 ? module : nullptr;
396 }
397
398 void RTLIL::Design::add(RTLIL::Module *module)
399 {
400 log_assert(modules_.count(module->name) == 0);
401 log_assert(refcount_modules_ == 0);
402 modules_[module->name] = module;
403 module->design = this;
404
405 for (auto mon : monitors)
406 mon->notify_module_add(module);
407
408 if (yosys_xtrace) {
409 log("#X# New Module: %s\n", log_id(module));
410 log_backtrace("-X- ", yosys_xtrace-1);
411 }
412 }
413
414 RTLIL::Module *RTLIL::Design::addModule(RTLIL::IdString name)
415 {
416 log_assert(modules_.count(name) == 0);
417 log_assert(refcount_modules_ == 0);
418
419 RTLIL::Module *module = new RTLIL::Module;
420 modules_[name] = module;
421 module->design = this;
422 module->name = name;
423
424 for (auto mon : monitors)
425 mon->notify_module_add(module);
426
427 if (yosys_xtrace) {
428 log("#X# New Module: %s\n", log_id(module));
429 log_backtrace("-X- ", yosys_xtrace-1);
430 }
431
432 return module;
433 }
434
435 void RTLIL::Design::scratchpad_unset(std::string varname)
436 {
437 scratchpad.erase(varname);
438 }
439
440 void RTLIL::Design::scratchpad_set_int(std::string varname, int value)
441 {
442 scratchpad[varname] = stringf("%d", value);
443 }
444
445 void RTLIL::Design::scratchpad_set_bool(std::string varname, bool value)
446 {
447 scratchpad[varname] = value ? "true" : "false";
448 }
449
450 void RTLIL::Design::scratchpad_set_string(std::string varname, std::string value)
451 {
452 scratchpad[varname] = value;
453 }
454
455 int RTLIL::Design::scratchpad_get_int(std::string varname, int default_value) const
456 {
457 if (scratchpad.count(varname) == 0)
458 return default_value;
459
460 std::string str = scratchpad.at(varname);
461
462 if (str == "0" || str == "false")
463 return 0;
464
465 if (str == "1" || str == "true")
466 return 1;
467
468 char *endptr = nullptr;
469 long int parsed_value = strtol(str.c_str(), &endptr, 10);
470 return *endptr ? default_value : parsed_value;
471 }
472
473 bool RTLIL::Design::scratchpad_get_bool(std::string varname, bool default_value) const
474 {
475 if (scratchpad.count(varname) == 0)
476 return default_value;
477
478 std::string str = scratchpad.at(varname);
479
480 if (str == "0" || str == "false")
481 return false;
482
483 if (str == "1" || str == "true")
484 return true;
485
486 return default_value;
487 }
488
489 std::string RTLIL::Design::scratchpad_get_string(std::string varname, std::string default_value) const
490 {
491 if (scratchpad.count(varname) == 0)
492 return default_value;
493 return scratchpad.at(varname);
494 }
495
496 void RTLIL::Design::remove(RTLIL::Module *module)
497 {
498 for (auto mon : monitors)
499 mon->notify_module_del(module);
500
501 if (yosys_xtrace) {
502 log("#X# Remove Module: %s\n", log_id(module));
503 log_backtrace("-X- ", yosys_xtrace-1);
504 }
505
506 log_assert(modules_.at(module->name) == module);
507 modules_.erase(module->name);
508 delete module;
509 }
510
511 void RTLIL::Design::rename(RTLIL::Module *module, RTLIL::IdString new_name)
512 {
513 modules_.erase(module->name);
514 module->name = new_name;
515 add(module);
516 }
517
518 void RTLIL::Design::sort()
519 {
520 scratchpad.sort();
521 modules_.sort(sort_by_id_str());
522 for (auto &it : modules_)
523 it.second->sort();
524 }
525
526 void RTLIL::Design::check()
527 {
528 #ifndef NDEBUG
529 for (auto &it : modules_) {
530 log_assert(this == it.second->design);
531 log_assert(it.first == it.second->name);
532 log_assert(!it.first.empty());
533 it.second->check();
534 }
535 #endif
536 }
537
538 void RTLIL::Design::optimize()
539 {
540 for (auto &it : modules_)
541 it.second->optimize();
542 for (auto &it : selection_stack)
543 it.optimize(this);
544 for (auto &it : selection_vars)
545 it.second.optimize(this);
546 }
547
548 bool RTLIL::Design::selected_module(RTLIL::IdString mod_name) const
549 {
550 if (!selected_active_module.empty() && mod_name != selected_active_module)
551 return false;
552 if (selection_stack.size() == 0)
553 return true;
554 return selection_stack.back().selected_module(mod_name);
555 }
556
557 bool RTLIL::Design::selected_whole_module(RTLIL::IdString mod_name) const
558 {
559 if (!selected_active_module.empty() && mod_name != selected_active_module)
560 return false;
561 if (selection_stack.size() == 0)
562 return true;
563 return selection_stack.back().selected_whole_module(mod_name);
564 }
565
566 bool RTLIL::Design::selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const
567 {
568 if (!selected_active_module.empty() && mod_name != selected_active_module)
569 return false;
570 if (selection_stack.size() == 0)
571 return true;
572 return selection_stack.back().selected_member(mod_name, memb_name);
573 }
574
575 bool RTLIL::Design::selected_module(RTLIL::Module *mod) const
576 {
577 return selected_module(mod->name);
578 }
579
580 bool RTLIL::Design::selected_whole_module(RTLIL::Module *mod) const
581 {
582 return selected_whole_module(mod->name);
583 }
584
585 std::vector<RTLIL::Module*> RTLIL::Design::selected_modules() const
586 {
587 std::vector<RTLIL::Module*> result;
588 result.reserve(modules_.size());
589 for (auto &it : modules_)
590 if (selected_module(it.first) && !it.second->get_bool_attribute("\\blackbox"))
591 result.push_back(it.second);
592 return result;
593 }
594
595 std::vector<RTLIL::Module*> RTLIL::Design::selected_whole_modules() const
596 {
597 std::vector<RTLIL::Module*> result;
598 result.reserve(modules_.size());
599 for (auto &it : modules_)
600 if (selected_whole_module(it.first) && !it.second->get_bool_attribute("\\blackbox"))
601 result.push_back(it.second);
602 return result;
603 }
604
605 std::vector<RTLIL::Module*> RTLIL::Design::selected_whole_modules_warn() const
606 {
607 std::vector<RTLIL::Module*> result;
608 result.reserve(modules_.size());
609 for (auto &it : modules_)
610 if (it.second->get_bool_attribute("\\blackbox"))
611 continue;
612 else if (selected_whole_module(it.first))
613 result.push_back(it.second);
614 else if (selected_module(it.first))
615 log_warning("Ignoring partially selected module %s.\n", log_id(it.first));
616 return result;
617 }
618
619 RTLIL::Module::Module()
620 {
621 static unsigned int hashidx_count = 123456789;
622 hashidx_count = mkhash_xorshift(hashidx_count);
623 hashidx_ = hashidx_count;
624
625 design = nullptr;
626 refcount_wires_ = 0;
627 refcount_cells_ = 0;
628 }
629
630 RTLIL::Module::~Module()
631 {
632 for (auto it = wires_.begin(); it != wires_.end(); ++it)
633 delete it->second;
634 for (auto it = memories.begin(); it != memories.end(); ++it)
635 delete it->second;
636 for (auto it = cells_.begin(); it != cells_.end(); ++it)
637 delete it->second;
638 for (auto it = processes.begin(); it != processes.end(); ++it)
639 delete it->second;
640 }
641
642 void RTLIL::Module::reprocess_module(RTLIL::Design *, dict<RTLIL::IdString, RTLIL::Module *>)
643 {
644 log_error("Cannot reprocess_module module `%s' !\n", id2cstr(name));
645 }
646
647 RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, dict<RTLIL::IdString, RTLIL::Const>, bool mayfail)
648 {
649 if (mayfail)
650 return RTLIL::IdString();
651 log_error("Module `%s' is used with parameters but is not parametric!\n", id2cstr(name));
652 }
653
654
655 RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, dict<RTLIL::IdString, RTLIL::Const>, dict<RTLIL::IdString, RTLIL::Module*>, dict<RTLIL::IdString, RTLIL::IdString>, bool mayfail)
656 {
657 if (mayfail)
658 return RTLIL::IdString();
659 log_error("Module `%s' is used with parameters but is not parametric!\n", id2cstr(name));
660 }
661
662 size_t RTLIL::Module::count_id(RTLIL::IdString id)
663 {
664 return wires_.count(id) + memories.count(id) + cells_.count(id) + processes.count(id);
665 }
666
667 #ifndef NDEBUG
668 namespace {
669 struct InternalCellChecker
670 {
671 RTLIL::Module *module;
672 RTLIL::Cell *cell;
673 pool<RTLIL::IdString> expected_params, expected_ports;
674
675 InternalCellChecker(RTLIL::Module *module, RTLIL::Cell *cell) : module(module), cell(cell) { }
676
677 void error(int linenr)
678 {
679 std::stringstream buf;
680 ILANG_BACKEND::dump_cell(buf, " ", cell);
681
682 log_error("Found error in internal cell %s%s%s (%s) at %s:%d:\n%s",
683 module ? module->name.c_str() : "", module ? "." : "",
684 cell->name.c_str(), cell->type.c_str(), __FILE__, linenr, buf.str().c_str());
685 }
686
687 int param(const char *name)
688 {
689 if (cell->parameters.count(name) == 0)
690 error(__LINE__);
691 expected_params.insert(name);
692 return cell->parameters.at(name).as_int();
693 }
694
695 int param_bool(const char *name)
696 {
697 int v = param(name);
698 if (cell->parameters.at(name).bits.size() > 32)
699 error(__LINE__);
700 if (v != 0 && v != 1)
701 error(__LINE__);
702 return v;
703 }
704
705 void param_bits(const char *name, int width)
706 {
707 param(name);
708 if (int(cell->parameters.at(name).bits.size()) != width)
709 error(__LINE__);
710 }
711
712 void port(const char *name, int width)
713 {
714 if (!cell->hasPort(name))
715 error(__LINE__);
716 if (cell->getPort(name).size() != width)
717 error(__LINE__);
718 expected_ports.insert(name);
719 }
720
721 void check_expected(bool check_matched_sign = true)
722 {
723 for (auto &para : cell->parameters)
724 if (expected_params.count(para.first) == 0)
725 error(__LINE__);
726 for (auto &conn : cell->connections())
727 if (expected_ports.count(conn.first) == 0)
728 error(__LINE__);
729
730 if (expected_params.count("\\A_SIGNED") != 0 && expected_params.count("\\B_SIGNED") && check_matched_sign) {
731 bool a_is_signed = param("\\A_SIGNED") != 0;
732 bool b_is_signed = param("\\B_SIGNED") != 0;
733 if (a_is_signed != b_is_signed)
734 error(__LINE__);
735 }
736 }
737
738 void check_gate(const char *ports)
739 {
740 if (cell->parameters.size() != 0)
741 error(__LINE__);
742
743 for (const char *p = ports; *p; p++) {
744 char portname[3] = { '\\', *p, 0 };
745 if (!cell->hasPort(portname))
746 error(__LINE__);
747 if (cell->getPort(portname).size() != 1)
748 error(__LINE__);
749 }
750
751 for (auto &conn : cell->connections()) {
752 if (conn.first.size() != 2 || conn.first[0] != '\\')
753 error(__LINE__);
754 if (strchr(ports, conn.first[1]) == NULL)
755 error(__LINE__);
756 }
757 }
758
759 void check()
760 {
761 if (cell->type.substr(0, 1) != "$" || cell->type.substr(0, 3) == "$__" || cell->type.substr(0, 8) == "$paramod" ||
762 cell->type.substr(0, 9) == "$verific$" || cell->type.substr(0, 7) == "$array:" || cell->type.substr(0, 8) == "$extern:")
763 return;
764
765 if (cell->type.in("$not", "$pos", "$neg")) {
766 param_bool("\\A_SIGNED");
767 port("\\A", param("\\A_WIDTH"));
768 port("\\Y", param("\\Y_WIDTH"));
769 check_expected();
770 return;
771 }
772
773 if (cell->type.in("$and", "$or", "$xor", "$xnor")) {
774 param_bool("\\A_SIGNED");
775 param_bool("\\B_SIGNED");
776 port("\\A", param("\\A_WIDTH"));
777 port("\\B", param("\\B_WIDTH"));
778 port("\\Y", param("\\Y_WIDTH"));
779 check_expected();
780 return;
781 }
782
783 if (cell->type.in("$reduce_and", "$reduce_or", "$reduce_xor", "$reduce_xnor", "$reduce_bool")) {
784 param_bool("\\A_SIGNED");
785 port("\\A", param("\\A_WIDTH"));
786 port("\\Y", param("\\Y_WIDTH"));
787 check_expected();
788 return;
789 }
790
791 if (cell->type.in("$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx")) {
792 param_bool("\\A_SIGNED");
793 param_bool("\\B_SIGNED");
794 port("\\A", param("\\A_WIDTH"));
795 port("\\B", param("\\B_WIDTH"));
796 port("\\Y", param("\\Y_WIDTH"));
797 check_expected(false);
798 return;
799 }
800
801 if (cell->type.in("$lt", "$le", "$eq", "$ne", "$eqx", "$nex", "$ge", "$gt")) {
802 param_bool("\\A_SIGNED");
803 param_bool("\\B_SIGNED");
804 port("\\A", param("\\A_WIDTH"));
805 port("\\B", param("\\B_WIDTH"));
806 port("\\Y", param("\\Y_WIDTH"));
807 check_expected();
808 return;
809 }
810
811 if (cell->type.in("$add", "$sub", "$mul", "$div", "$mod", "$pow")) {
812 param_bool("\\A_SIGNED");
813 param_bool("\\B_SIGNED");
814 port("\\A", param("\\A_WIDTH"));
815 port("\\B", param("\\B_WIDTH"));
816 port("\\Y", param("\\Y_WIDTH"));
817 check_expected(cell->type != "$pow");
818 return;
819 }
820
821 if (cell->type == "$fa") {
822 port("\\A", param("\\WIDTH"));
823 port("\\B", param("\\WIDTH"));
824 port("\\C", param("\\WIDTH"));
825 port("\\X", param("\\WIDTH"));
826 port("\\Y", param("\\WIDTH"));
827 check_expected();
828 return;
829 }
830
831 if (cell->type == "$lcu") {
832 port("\\P", param("\\WIDTH"));
833 port("\\G", param("\\WIDTH"));
834 port("\\CI", 1);
835 port("\\CO", param("\\WIDTH"));
836 check_expected();
837 return;
838 }
839
840 if (cell->type == "$alu") {
841 param_bool("\\A_SIGNED");
842 param_bool("\\B_SIGNED");
843 port("\\A", param("\\A_WIDTH"));
844 port("\\B", param("\\B_WIDTH"));
845 port("\\CI", 1);
846 port("\\BI", 1);
847 port("\\X", param("\\Y_WIDTH"));
848 port("\\Y", param("\\Y_WIDTH"));
849 port("\\CO", param("\\Y_WIDTH"));
850 check_expected();
851 return;
852 }
853
854 if (cell->type == "$macc") {
855 param("\\CONFIG");
856 param("\\CONFIG_WIDTH");
857 port("\\A", param("\\A_WIDTH"));
858 port("\\B", param("\\B_WIDTH"));
859 port("\\Y", param("\\Y_WIDTH"));
860 check_expected();
861 Macc().from_cell(cell);
862 return;
863 }
864
865 if (cell->type == "$logic_not") {
866 param_bool("\\A_SIGNED");
867 port("\\A", param("\\A_WIDTH"));
868 port("\\Y", param("\\Y_WIDTH"));
869 check_expected();
870 return;
871 }
872
873 if (cell->type == "$logic_and" || cell->type == "$logic_or") {
874 param_bool("\\A_SIGNED");
875 param_bool("\\B_SIGNED");
876 port("\\A", param("\\A_WIDTH"));
877 port("\\B", param("\\B_WIDTH"));
878 port("\\Y", param("\\Y_WIDTH"));
879 check_expected(false);
880 return;
881 }
882
883 if (cell->type == "$slice") {
884 param("\\OFFSET");
885 port("\\A", param("\\A_WIDTH"));
886 port("\\Y", param("\\Y_WIDTH"));
887 if (param("\\OFFSET") + param("\\Y_WIDTH") > param("\\A_WIDTH"))
888 error(__LINE__);
889 check_expected();
890 return;
891 }
892
893 if (cell->type == "$concat") {
894 port("\\A", param("\\A_WIDTH"));
895 port("\\B", param("\\B_WIDTH"));
896 port("\\Y", param("\\A_WIDTH") + param("\\B_WIDTH"));
897 check_expected();
898 return;
899 }
900
901 if (cell->type == "$mux") {
902 port("\\A", param("\\WIDTH"));
903 port("\\B", param("\\WIDTH"));
904 port("\\S", 1);
905 port("\\Y", param("\\WIDTH"));
906 check_expected();
907 return;
908 }
909
910 if (cell->type == "$pmux") {
911 port("\\A", param("\\WIDTH"));
912 port("\\B", param("\\WIDTH") * param("\\S_WIDTH"));
913 port("\\S", param("\\S_WIDTH"));
914 port("\\Y", param("\\WIDTH"));
915 check_expected();
916 return;
917 }
918
919 if (cell->type == "$lut") {
920 param("\\LUT");
921 port("\\A", param("\\WIDTH"));
922 port("\\Y", 1);
923 check_expected();
924 return;
925 }
926
927 if (cell->type == "$sop") {
928 param("\\DEPTH");
929 param("\\TABLE");
930 port("\\A", param("\\WIDTH"));
931 port("\\Y", 1);
932 check_expected();
933 return;
934 }
935
936 if (cell->type == "$sr") {
937 param_bool("\\SET_POLARITY");
938 param_bool("\\CLR_POLARITY");
939 port("\\SET", param("\\WIDTH"));
940 port("\\CLR", param("\\WIDTH"));
941 port("\\Q", param("\\WIDTH"));
942 check_expected();
943 return;
944 }
945
946 if (cell->type == "$ff") {
947 port("\\D", param("\\WIDTH"));
948 port("\\Q", param("\\WIDTH"));
949 check_expected();
950 return;
951 }
952
953 if (cell->type == "$dff") {
954 param_bool("\\CLK_POLARITY");
955 port("\\CLK", 1);
956 port("\\D", param("\\WIDTH"));
957 port("\\Q", param("\\WIDTH"));
958 check_expected();
959 return;
960 }
961
962 if (cell->type == "$dffe") {
963 param_bool("\\CLK_POLARITY");
964 param_bool("\\EN_POLARITY");
965 port("\\CLK", 1);
966 port("\\EN", 1);
967 port("\\D", param("\\WIDTH"));
968 port("\\Q", param("\\WIDTH"));
969 check_expected();
970 return;
971 }
972
973 if (cell->type == "$dffsr") {
974 param_bool("\\CLK_POLARITY");
975 param_bool("\\SET_POLARITY");
976 param_bool("\\CLR_POLARITY");
977 port("\\CLK", 1);
978 port("\\SET", param("\\WIDTH"));
979 port("\\CLR", param("\\WIDTH"));
980 port("\\D", param("\\WIDTH"));
981 port("\\Q", param("\\WIDTH"));
982 check_expected();
983 return;
984 }
985
986 if (cell->type == "$adff") {
987 param_bool("\\CLK_POLARITY");
988 param_bool("\\ARST_POLARITY");
989 param_bits("\\ARST_VALUE", param("\\WIDTH"));
990 port("\\CLK", 1);
991 port("\\ARST", 1);
992 port("\\D", param("\\WIDTH"));
993 port("\\Q", param("\\WIDTH"));
994 check_expected();
995 return;
996 }
997
998 if (cell->type == "$dlatch") {
999 param_bool("\\EN_POLARITY");
1000 port("\\EN", 1);
1001 port("\\D", param("\\WIDTH"));
1002 port("\\Q", param("\\WIDTH"));
1003 check_expected();
1004 return;
1005 }
1006
1007 if (cell->type == "$dlatchsr") {
1008 param_bool("\\EN_POLARITY");
1009 param_bool("\\SET_POLARITY");
1010 param_bool("\\CLR_POLARITY");
1011 port("\\EN", 1);
1012 port("\\SET", param("\\WIDTH"));
1013 port("\\CLR", param("\\WIDTH"));
1014 port("\\D", param("\\WIDTH"));
1015 port("\\Q", param("\\WIDTH"));
1016 check_expected();
1017 return;
1018 }
1019
1020 if (cell->type == "$fsm") {
1021 param("\\NAME");
1022 param_bool("\\CLK_POLARITY");
1023 param_bool("\\ARST_POLARITY");
1024 param("\\STATE_BITS");
1025 param("\\STATE_NUM");
1026 param("\\STATE_NUM_LOG2");
1027 param("\\STATE_RST");
1028 param_bits("\\STATE_TABLE", param("\\STATE_BITS") * param("\\STATE_NUM"));
1029 param("\\TRANS_NUM");
1030 param_bits("\\TRANS_TABLE", param("\\TRANS_NUM") * (2*param("\\STATE_NUM_LOG2") + param("\\CTRL_IN_WIDTH") + param("\\CTRL_OUT_WIDTH")));
1031 port("\\CLK", 1);
1032 port("\\ARST", 1);
1033 port("\\CTRL_IN", param("\\CTRL_IN_WIDTH"));
1034 port("\\CTRL_OUT", param("\\CTRL_OUT_WIDTH"));
1035 check_expected();
1036 return;
1037 }
1038
1039 if (cell->type == "$memrd") {
1040 param("\\MEMID");
1041 param_bool("\\CLK_ENABLE");
1042 param_bool("\\CLK_POLARITY");
1043 param_bool("\\TRANSPARENT");
1044 port("\\CLK", 1);
1045 port("\\EN", 1);
1046 port("\\ADDR", param("\\ABITS"));
1047 port("\\DATA", param("\\WIDTH"));
1048 check_expected();
1049 return;
1050 }
1051
1052 if (cell->type == "$memwr") {
1053 param("\\MEMID");
1054 param_bool("\\CLK_ENABLE");
1055 param_bool("\\CLK_POLARITY");
1056 param("\\PRIORITY");
1057 port("\\CLK", 1);
1058 port("\\EN", param("\\WIDTH"));
1059 port("\\ADDR", param("\\ABITS"));
1060 port("\\DATA", param("\\WIDTH"));
1061 check_expected();
1062 return;
1063 }
1064
1065 if (cell->type == "$meminit") {
1066 param("\\MEMID");
1067 param("\\PRIORITY");
1068 port("\\ADDR", param("\\ABITS"));
1069 port("\\DATA", param("\\WIDTH") * param("\\WORDS"));
1070 check_expected();
1071 return;
1072 }
1073
1074 if (cell->type == "$mem") {
1075 param("\\MEMID");
1076 param("\\SIZE");
1077 param("\\OFFSET");
1078 param("\\INIT");
1079 param_bits("\\RD_CLK_ENABLE", max(1, param("\\RD_PORTS")));
1080 param_bits("\\RD_CLK_POLARITY", max(1, param("\\RD_PORTS")));
1081 param_bits("\\RD_TRANSPARENT", max(1, param("\\RD_PORTS")));
1082 param_bits("\\WR_CLK_ENABLE", max(1, param("\\WR_PORTS")));
1083 param_bits("\\WR_CLK_POLARITY", max(1, param("\\WR_PORTS")));
1084 port("\\RD_CLK", param("\\RD_PORTS"));
1085 port("\\RD_EN", param("\\RD_PORTS"));
1086 port("\\RD_ADDR", param("\\RD_PORTS") * param("\\ABITS"));
1087 port("\\RD_DATA", param("\\RD_PORTS") * param("\\WIDTH"));
1088 port("\\WR_CLK", param("\\WR_PORTS"));
1089 port("\\WR_EN", param("\\WR_PORTS") * param("\\WIDTH"));
1090 port("\\WR_ADDR", param("\\WR_PORTS") * param("\\ABITS"));
1091 port("\\WR_DATA", param("\\WR_PORTS") * param("\\WIDTH"));
1092 check_expected();
1093 return;
1094 }
1095
1096 if (cell->type == "$tribuf") {
1097 port("\\A", param("\\WIDTH"));
1098 port("\\Y", param("\\WIDTH"));
1099 port("\\EN", 1);
1100 check_expected();
1101 return;
1102 }
1103
1104 if (cell->type.in("$assert", "$assume", "$live", "$fair", "$cover")) {
1105 port("\\A", 1);
1106 port("\\EN", 1);
1107 check_expected();
1108 return;
1109 }
1110
1111 if (cell->type == "$initstate") {
1112 port("\\Y", 1);
1113 check_expected();
1114 return;
1115 }
1116
1117 if (cell->type.in("$anyconst", "$anyseq", "$allconst", "$allseq")) {
1118 port("\\Y", param("\\WIDTH"));
1119 check_expected();
1120 return;
1121 }
1122
1123 if (cell->type == "$equiv") {
1124 port("\\A", 1);
1125 port("\\B", 1);
1126 port("\\Y", 1);
1127 check_expected();
1128 return;
1129 }
1130
1131 if (cell->type == "$_BUF_") { check_gate("AY"); return; }
1132 if (cell->type == "$_NOT_") { check_gate("AY"); return; }
1133 if (cell->type == "$_AND_") { check_gate("ABY"); return; }
1134 if (cell->type == "$_NAND_") { check_gate("ABY"); return; }
1135 if (cell->type == "$_OR_") { check_gate("ABY"); return; }
1136 if (cell->type == "$_NOR_") { check_gate("ABY"); return; }
1137 if (cell->type == "$_XOR_") { check_gate("ABY"); return; }
1138 if (cell->type == "$_XNOR_") { check_gate("ABY"); return; }
1139 if (cell->type == "$_ANDNOT_") { check_gate("ABY"); return; }
1140 if (cell->type == "$_ORNOT_") { check_gate("ABY"); return; }
1141 if (cell->type == "$_MUX_") { check_gate("ABSY"); return; }
1142 if (cell->type == "$_AOI3_") { check_gate("ABCY"); return; }
1143 if (cell->type == "$_OAI3_") { check_gate("ABCY"); return; }
1144 if (cell->type == "$_AOI4_") { check_gate("ABCDY"); return; }
1145 if (cell->type == "$_OAI4_") { check_gate("ABCDY"); return; }
1146
1147 if (cell->type == "$_TBUF_") { check_gate("AYE"); return; }
1148
1149 if (cell->type == "$_MUX4_") { check_gate("ABCDSTY"); return; }
1150 if (cell->type == "$_MUX8_") { check_gate("ABCDEFGHSTUY"); return; }
1151 if (cell->type == "$_MUX16_") { check_gate("ABCDEFGHIJKLMNOPSTUVY"); return; }
1152
1153 if (cell->type == "$_SR_NN_") { check_gate("SRQ"); return; }
1154 if (cell->type == "$_SR_NP_") { check_gate("SRQ"); return; }
1155 if (cell->type == "$_SR_PN_") { check_gate("SRQ"); return; }
1156 if (cell->type == "$_SR_PP_") { check_gate("SRQ"); return; }
1157
1158 if (cell->type == "$_FF_") { check_gate("DQ"); return; }
1159 if (cell->type == "$_DFF_N_") { check_gate("DQC"); return; }
1160 if (cell->type == "$_DFF_P_") { check_gate("DQC"); return; }
1161
1162 if (cell->type == "$_DFFE_NN_") { check_gate("DQCE"); return; }
1163 if (cell->type == "$_DFFE_NP_") { check_gate("DQCE"); return; }
1164 if (cell->type == "$_DFFE_PN_") { check_gate("DQCE"); return; }
1165 if (cell->type == "$_DFFE_PP_") { check_gate("DQCE"); return; }
1166
1167 if (cell->type == "$_DFF_NN0_") { check_gate("DQCR"); return; }
1168 if (cell->type == "$_DFF_NN1_") { check_gate("DQCR"); return; }
1169 if (cell->type == "$_DFF_NP0_") { check_gate("DQCR"); return; }
1170 if (cell->type == "$_DFF_NP1_") { check_gate("DQCR"); return; }
1171 if (cell->type == "$_DFF_PN0_") { check_gate("DQCR"); return; }
1172 if (cell->type == "$_DFF_PN1_") { check_gate("DQCR"); return; }
1173 if (cell->type == "$_DFF_PP0_") { check_gate("DQCR"); return; }
1174 if (cell->type == "$_DFF_PP1_") { check_gate("DQCR"); return; }
1175
1176 if (cell->type == "$_DFFSR_NNN_") { check_gate("CSRDQ"); return; }
1177 if (cell->type == "$_DFFSR_NNP_") { check_gate("CSRDQ"); return; }
1178 if (cell->type == "$_DFFSR_NPN_") { check_gate("CSRDQ"); return; }
1179 if (cell->type == "$_DFFSR_NPP_") { check_gate("CSRDQ"); return; }
1180 if (cell->type == "$_DFFSR_PNN_") { check_gate("CSRDQ"); return; }
1181 if (cell->type == "$_DFFSR_PNP_") { check_gate("CSRDQ"); return; }
1182 if (cell->type == "$_DFFSR_PPN_") { check_gate("CSRDQ"); return; }
1183 if (cell->type == "$_DFFSR_PPP_") { check_gate("CSRDQ"); return; }
1184
1185 if (cell->type == "$_DLATCH_N_") { check_gate("EDQ"); return; }
1186 if (cell->type == "$_DLATCH_P_") { check_gate("EDQ"); return; }
1187
1188 if (cell->type == "$_DLATCHSR_NNN_") { check_gate("ESRDQ"); return; }
1189 if (cell->type == "$_DLATCHSR_NNP_") { check_gate("ESRDQ"); return; }
1190 if (cell->type == "$_DLATCHSR_NPN_") { check_gate("ESRDQ"); return; }
1191 if (cell->type == "$_DLATCHSR_NPP_") { check_gate("ESRDQ"); return; }
1192 if (cell->type == "$_DLATCHSR_PNN_") { check_gate("ESRDQ"); return; }
1193 if (cell->type == "$_DLATCHSR_PNP_") { check_gate("ESRDQ"); return; }
1194 if (cell->type == "$_DLATCHSR_PPN_") { check_gate("ESRDQ"); return; }
1195 if (cell->type == "$_DLATCHSR_PPP_") { check_gate("ESRDQ"); return; }
1196
1197 error(__LINE__);
1198 }
1199 };
1200 }
1201 #endif
1202
1203 void RTLIL::Module::sort()
1204 {
1205 wires_.sort(sort_by_id_str());
1206 cells_.sort(sort_by_id_str());
1207 avail_parameters.sort(sort_by_id_str());
1208 memories.sort(sort_by_id_str());
1209 processes.sort(sort_by_id_str());
1210 for (auto &it : cells_)
1211 it.second->sort();
1212 for (auto &it : wires_)
1213 it.second->attributes.sort(sort_by_id_str());
1214 for (auto &it : memories)
1215 it.second->attributes.sort(sort_by_id_str());
1216 }
1217
1218 void RTLIL::Module::check()
1219 {
1220 #ifndef NDEBUG
1221 std::vector<bool> ports_declared;
1222 for (auto &it : wires_) {
1223 log_assert(this == it.second->module);
1224 log_assert(it.first == it.second->name);
1225 log_assert(!it.first.empty());
1226 log_assert(it.second->width >= 0);
1227 log_assert(it.second->port_id >= 0);
1228 for (auto &it2 : it.second->attributes)
1229 log_assert(!it2.first.empty());
1230 if (it.second->port_id) {
1231 log_assert(GetSize(ports) >= it.second->port_id);
1232 log_assert(ports.at(it.second->port_id-1) == it.first);
1233 log_assert(it.second->port_input || it.second->port_output);
1234 if (GetSize(ports_declared) < it.second->port_id)
1235 ports_declared.resize(it.second->port_id);
1236 log_assert(ports_declared[it.second->port_id-1] == false);
1237 ports_declared[it.second->port_id-1] = true;
1238 } else
1239 log_assert(!it.second->port_input && !it.second->port_output);
1240 }
1241 for (auto port_declared : ports_declared)
1242 log_assert(port_declared == true);
1243 log_assert(GetSize(ports) == GetSize(ports_declared));
1244
1245 for (auto &it : memories) {
1246 log_assert(it.first == it.second->name);
1247 log_assert(!it.first.empty());
1248 log_assert(it.second->width >= 0);
1249 log_assert(it.second->size >= 0);
1250 for (auto &it2 : it.second->attributes)
1251 log_assert(!it2.first.empty());
1252 }
1253
1254 for (auto &it : cells_) {
1255 log_assert(this == it.second->module);
1256 log_assert(it.first == it.second->name);
1257 log_assert(!it.first.empty());
1258 log_assert(!it.second->type.empty());
1259 for (auto &it2 : it.second->connections()) {
1260 log_assert(!it2.first.empty());
1261 it2.second.check();
1262 }
1263 for (auto &it2 : it.second->attributes)
1264 log_assert(!it2.first.empty());
1265 for (auto &it2 : it.second->parameters)
1266 log_assert(!it2.first.empty());
1267 InternalCellChecker checker(this, it.second);
1268 checker.check();
1269 }
1270
1271 for (auto &it : processes) {
1272 log_assert(it.first == it.second->name);
1273 log_assert(!it.first.empty());
1274 // FIXME: More checks here..
1275 }
1276
1277 for (auto &it : connections_) {
1278 log_assert(it.first.size() == it.second.size());
1279 log_assert(!it.first.has_const());
1280 it.first.check();
1281 it.second.check();
1282 }
1283
1284 for (auto &it : attributes)
1285 log_assert(!it.first.empty());
1286 #endif
1287 }
1288
1289 void RTLIL::Module::optimize()
1290 {
1291 }
1292
1293 void RTLIL::Module::cloneInto(RTLIL::Module *new_mod) const
1294 {
1295 log_assert(new_mod->refcount_wires_ == 0);
1296 log_assert(new_mod->refcount_cells_ == 0);
1297
1298 new_mod->avail_parameters = avail_parameters;
1299
1300 for (auto &conn : connections_)
1301 new_mod->connect(conn);
1302
1303 for (auto &attr : attributes)
1304 new_mod->attributes[attr.first] = attr.second;
1305
1306 for (auto &it : wires_)
1307 new_mod->addWire(it.first, it.second);
1308
1309 for (auto &it : memories)
1310 new_mod->memories[it.first] = new RTLIL::Memory(*it.second);
1311
1312 for (auto &it : cells_)
1313 new_mod->addCell(it.first, it.second);
1314
1315 for (auto &it : processes)
1316 new_mod->processes[it.first] = it.second->clone();
1317
1318 struct RewriteSigSpecWorker
1319 {
1320 RTLIL::Module *mod;
1321 void operator()(RTLIL::SigSpec &sig)
1322 {
1323 std::vector<RTLIL::SigChunk> chunks = sig.chunks();
1324 for (auto &c : chunks)
1325 if (c.wire != NULL)
1326 c.wire = mod->wires_.at(c.wire->name);
1327 sig = chunks;
1328 }
1329 };
1330
1331 RewriteSigSpecWorker rewriteSigSpecWorker;
1332 rewriteSigSpecWorker.mod = new_mod;
1333 new_mod->rewrite_sigspecs(rewriteSigSpecWorker);
1334 new_mod->fixup_ports();
1335 }
1336
1337 RTLIL::Module *RTLIL::Module::clone() const
1338 {
1339 RTLIL::Module *new_mod = new RTLIL::Module;
1340 new_mod->name = name;
1341 cloneInto(new_mod);
1342 return new_mod;
1343 }
1344
1345 bool RTLIL::Module::has_memories() const
1346 {
1347 return !memories.empty();
1348 }
1349
1350 bool RTLIL::Module::has_processes() const
1351 {
1352 return !processes.empty();
1353 }
1354
1355 bool RTLIL::Module::has_memories_warn() const
1356 {
1357 if (!memories.empty())
1358 log_warning("Ignoring module %s because it contains memories (run 'memory' command first).\n", log_id(this));
1359 return !memories.empty();
1360 }
1361
1362 bool RTLIL::Module::has_processes_warn() const
1363 {
1364 if (!processes.empty())
1365 log_warning("Ignoring module %s because it contains processes (run 'proc' command first).\n", log_id(this));
1366 return !processes.empty();
1367 }
1368
1369 std::vector<RTLIL::Wire*> RTLIL::Module::selected_wires() const
1370 {
1371 std::vector<RTLIL::Wire*> result;
1372 result.reserve(wires_.size());
1373 for (auto &it : wires_)
1374 if (design->selected(this, it.second))
1375 result.push_back(it.second);
1376 return result;
1377 }
1378
1379 std::vector<RTLIL::Cell*> RTLIL::Module::selected_cells() const
1380 {
1381 std::vector<RTLIL::Cell*> result;
1382 result.reserve(wires_.size());
1383 for (auto &it : cells_)
1384 if (design->selected(this, it.second))
1385 result.push_back(it.second);
1386 return result;
1387 }
1388
1389 void RTLIL::Module::add(RTLIL::Wire *wire)
1390 {
1391 log_assert(!wire->name.empty());
1392 log_assert(count_id(wire->name) == 0);
1393 log_assert(refcount_wires_ == 0);
1394 wires_[wire->name] = wire;
1395 wire->module = this;
1396 }
1397
1398 void RTLIL::Module::add(RTLIL::Cell *cell)
1399 {
1400 log_assert(!cell->name.empty());
1401 log_assert(count_id(cell->name) == 0);
1402 log_assert(refcount_cells_ == 0);
1403 cells_[cell->name] = cell;
1404 cell->module = this;
1405 }
1406
1407 namespace {
1408 struct DeleteWireWorker
1409 {
1410 RTLIL::Module *module;
1411 const pool<RTLIL::Wire*> *wires_p;
1412
1413 void operator()(RTLIL::SigSpec &sig) {
1414 std::vector<RTLIL::SigChunk> chunks = sig;
1415 for (auto &c : chunks)
1416 if (c.wire != NULL && wires_p->count(c.wire)) {
1417 c.wire = module->addWire(NEW_ID, c.width);
1418 c.offset = 0;
1419 }
1420 sig = chunks;
1421 }
1422 };
1423 }
1424
1425 void RTLIL::Module::remove(const pool<RTLIL::Wire*> &wires)
1426 {
1427 log_assert(refcount_wires_ == 0);
1428
1429 DeleteWireWorker delete_wire_worker;
1430 delete_wire_worker.module = this;
1431 delete_wire_worker.wires_p = &wires;
1432 rewrite_sigspecs(delete_wire_worker);
1433
1434 for (auto &it : wires) {
1435 log_assert(wires_.count(it->name) != 0);
1436 wires_.erase(it->name);
1437 delete it;
1438 }
1439 }
1440
1441 void RTLIL::Module::remove(RTLIL::Cell *cell)
1442 {
1443 while (!cell->connections_.empty())
1444 cell->unsetPort(cell->connections_.begin()->first);
1445
1446 log_assert(cells_.count(cell->name) != 0);
1447 log_assert(refcount_cells_ == 0);
1448 cells_.erase(cell->name);
1449 delete cell;
1450 }
1451
1452 void RTLIL::Module::rename(RTLIL::Wire *wire, RTLIL::IdString new_name)
1453 {
1454 log_assert(wires_[wire->name] == wire);
1455 log_assert(refcount_wires_ == 0);
1456 wires_.erase(wire->name);
1457 wire->name = new_name;
1458 add(wire);
1459 }
1460
1461 void RTLIL::Module::rename(RTLIL::Cell *cell, RTLIL::IdString new_name)
1462 {
1463 log_assert(cells_[cell->name] == cell);
1464 log_assert(refcount_wires_ == 0);
1465 cells_.erase(cell->name);
1466 cell->name = new_name;
1467 add(cell);
1468 }
1469
1470 void RTLIL::Module::rename(RTLIL::IdString old_name, RTLIL::IdString new_name)
1471 {
1472 log_assert(count_id(old_name) != 0);
1473 if (wires_.count(old_name))
1474 rename(wires_.at(old_name), new_name);
1475 else if (cells_.count(old_name))
1476 rename(cells_.at(old_name), new_name);
1477 else
1478 log_abort();
1479 }
1480
1481 void RTLIL::Module::swap_names(RTLIL::Wire *w1, RTLIL::Wire *w2)
1482 {
1483 log_assert(wires_[w1->name] == w1);
1484 log_assert(wires_[w2->name] == w2);
1485 log_assert(refcount_wires_ == 0);
1486
1487 wires_.erase(w1->name);
1488 wires_.erase(w2->name);
1489
1490 std::swap(w1->name, w2->name);
1491
1492 wires_[w1->name] = w1;
1493 wires_[w2->name] = w2;
1494 }
1495
1496 void RTLIL::Module::swap_names(RTLIL::Cell *c1, RTLIL::Cell *c2)
1497 {
1498 log_assert(cells_[c1->name] == c1);
1499 log_assert(cells_[c2->name] == c2);
1500 log_assert(refcount_cells_ == 0);
1501
1502 cells_.erase(c1->name);
1503 cells_.erase(c2->name);
1504
1505 std::swap(c1->name, c2->name);
1506
1507 cells_[c1->name] = c1;
1508 cells_[c2->name] = c2;
1509 }
1510
1511 RTLIL::IdString RTLIL::Module::uniquify(RTLIL::IdString name)
1512 {
1513 int index = 0;
1514 return uniquify(name, index);
1515 }
1516
1517 RTLIL::IdString RTLIL::Module::uniquify(RTLIL::IdString name, int &index)
1518 {
1519 if (index == 0) {
1520 if (count_id(name) == 0)
1521 return name;
1522 index++;
1523 }
1524
1525 while (1) {
1526 RTLIL::IdString new_name = stringf("%s_%d", name.c_str(), index);
1527 if (count_id(new_name) == 0)
1528 return new_name;
1529 index++;
1530 }
1531 }
1532
1533 static bool fixup_ports_compare(const RTLIL::Wire *a, const RTLIL::Wire *b)
1534 {
1535 if (a->port_id && !b->port_id)
1536 return true;
1537 if (!a->port_id && b->port_id)
1538 return false;
1539
1540 if (a->port_id == b->port_id)
1541 return a->name < b->name;
1542 return a->port_id < b->port_id;
1543 }
1544
1545 void RTLIL::Module::connect(const RTLIL::SigSig &conn)
1546 {
1547 for (auto mon : monitors)
1548 mon->notify_connect(this, conn);
1549
1550 if (design)
1551 for (auto mon : design->monitors)
1552 mon->notify_connect(this, conn);
1553
1554 // ignore all attempts to assign constants to other constants
1555 if (conn.first.has_const()) {
1556 RTLIL::SigSig new_conn;
1557 for (int i = 0; i < GetSize(conn.first); i++)
1558 if (conn.first[i].wire) {
1559 new_conn.first.append(conn.first[i]);
1560 new_conn.second.append(conn.second[i]);
1561 }
1562 if (GetSize(new_conn.first))
1563 connect(new_conn);
1564 return;
1565 }
1566
1567 if (yosys_xtrace) {
1568 log("#X# Connect (SigSig) in %s: %s = %s (%d bits)\n", log_id(this), log_signal(conn.first), log_signal(conn.second), GetSize(conn.first));
1569 log_backtrace("-X- ", yosys_xtrace-1);
1570 }
1571
1572 log_assert(GetSize(conn.first) == GetSize(conn.second));
1573 connections_.push_back(conn);
1574 }
1575
1576 void RTLIL::Module::connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs)
1577 {
1578 connect(RTLIL::SigSig(lhs, rhs));
1579 }
1580
1581 void RTLIL::Module::new_connections(const std::vector<RTLIL::SigSig> &new_conn)
1582 {
1583 for (auto mon : monitors)
1584 mon->notify_connect(this, new_conn);
1585
1586 if (design)
1587 for (auto mon : design->monitors)
1588 mon->notify_connect(this, new_conn);
1589
1590 if (yosys_xtrace) {
1591 log("#X# New connections vector in %s:\n", log_id(this));
1592 for (auto &conn: new_conn)
1593 log("#X# %s = %s (%d bits)\n", log_signal(conn.first), log_signal(conn.second), GetSize(conn.first));
1594 log_backtrace("-X- ", yosys_xtrace-1);
1595 }
1596
1597 connections_ = new_conn;
1598 }
1599
1600 const std::vector<RTLIL::SigSig> &RTLIL::Module::connections() const
1601 {
1602 return connections_;
1603 }
1604
1605 void RTLIL::Module::fixup_ports()
1606 {
1607 std::vector<RTLIL::Wire*> all_ports;
1608
1609 for (auto &w : wires_)
1610 if (w.second->port_input || w.second->port_output)
1611 all_ports.push_back(w.second);
1612 else
1613 w.second->port_id = 0;
1614
1615 std::sort(all_ports.begin(), all_ports.end(), fixup_ports_compare);
1616
1617 ports.clear();
1618 for (size_t i = 0; i < all_ports.size(); i++) {
1619 ports.push_back(all_ports[i]->name);
1620 all_ports[i]->port_id = i+1;
1621 }
1622 }
1623
1624 RTLIL::Wire *RTLIL::Module::addWire(RTLIL::IdString name, int width)
1625 {
1626 RTLIL::Wire *wire = new RTLIL::Wire;
1627 wire->name = name;
1628 wire->width = width;
1629 add(wire);
1630 return wire;
1631 }
1632
1633 RTLIL::Wire *RTLIL::Module::addWire(RTLIL::IdString name, const RTLIL::Wire *other)
1634 {
1635 RTLIL::Wire *wire = addWire(name);
1636 wire->width = other->width;
1637 wire->start_offset = other->start_offset;
1638 wire->port_id = other->port_id;
1639 wire->port_input = other->port_input;
1640 wire->port_output = other->port_output;
1641 wire->upto = other->upto;
1642 wire->attributes = other->attributes;
1643 return wire;
1644 }
1645
1646 RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, RTLIL::IdString type)
1647 {
1648 RTLIL::Cell *cell = new RTLIL::Cell;
1649 cell->name = name;
1650 cell->type = type;
1651 add(cell);
1652 return cell;
1653 }
1654
1655 RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, const RTLIL::Cell *other)
1656 {
1657 RTLIL::Cell *cell = addCell(name, other->type);
1658 cell->connections_ = other->connections_;
1659 cell->parameters = other->parameters;
1660 cell->attributes = other->attributes;
1661 return cell;
1662 }
1663
1664 #define DEF_METHOD(_func, _y_size, _type) \
1665 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed, const std::string &src) { \
1666 RTLIL::Cell *cell = addCell(name, _type); \
1667 cell->parameters["\\A_SIGNED"] = is_signed; \
1668 cell->parameters["\\A_WIDTH"] = sig_a.size(); \
1669 cell->parameters["\\Y_WIDTH"] = sig_y.size(); \
1670 cell->setPort("\\A", sig_a); \
1671 cell->setPort("\\Y", sig_y); \
1672 cell->set_src_attribute(src); \
1673 return cell; \
1674 } \
1675 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed, const std::string &src) { \
1676 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
1677 add ## _func(name, sig_a, sig_y, is_signed, src); \
1678 return sig_y; \
1679 }
1680 DEF_METHOD(Not, sig_a.size(), "$not")
1681 DEF_METHOD(Pos, sig_a.size(), "$pos")
1682 DEF_METHOD(Neg, sig_a.size(), "$neg")
1683 DEF_METHOD(ReduceAnd, 1, "$reduce_and")
1684 DEF_METHOD(ReduceOr, 1, "$reduce_or")
1685 DEF_METHOD(ReduceXor, 1, "$reduce_xor")
1686 DEF_METHOD(ReduceXnor, 1, "$reduce_xnor")
1687 DEF_METHOD(ReduceBool, 1, "$reduce_bool")
1688 DEF_METHOD(LogicNot, 1, "$logic_not")
1689 #undef DEF_METHOD
1690
1691 #define DEF_METHOD(_func, _y_size, _type) \
1692 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed, const std::string &src) { \
1693 RTLIL::Cell *cell = addCell(name, _type); \
1694 cell->parameters["\\A_SIGNED"] = is_signed; \
1695 cell->parameters["\\B_SIGNED"] = is_signed; \
1696 cell->parameters["\\A_WIDTH"] = sig_a.size(); \
1697 cell->parameters["\\B_WIDTH"] = sig_b.size(); \
1698 cell->parameters["\\Y_WIDTH"] = sig_y.size(); \
1699 cell->setPort("\\A", sig_a); \
1700 cell->setPort("\\B", sig_b); \
1701 cell->setPort("\\Y", sig_y); \
1702 cell->set_src_attribute(src); \
1703 return cell; \
1704 } \
1705 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed, const std::string &src) { \
1706 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
1707 add ## _func(name, sig_a, sig_b, sig_y, is_signed, src); \
1708 return sig_y; \
1709 }
1710 DEF_METHOD(And, max(sig_a.size(), sig_b.size()), "$and")
1711 DEF_METHOD(Or, max(sig_a.size(), sig_b.size()), "$or")
1712 DEF_METHOD(Xor, max(sig_a.size(), sig_b.size()), "$xor")
1713 DEF_METHOD(Xnor, max(sig_a.size(), sig_b.size()), "$xnor")
1714 DEF_METHOD(Shl, sig_a.size(), "$shl")
1715 DEF_METHOD(Shr, sig_a.size(), "$shr")
1716 DEF_METHOD(Sshl, sig_a.size(), "$sshl")
1717 DEF_METHOD(Sshr, sig_a.size(), "$sshr")
1718 DEF_METHOD(Shift, sig_a.size(), "$shift")
1719 DEF_METHOD(Shiftx, sig_a.size(), "$shiftx")
1720 DEF_METHOD(Lt, 1, "$lt")
1721 DEF_METHOD(Le, 1, "$le")
1722 DEF_METHOD(Eq, 1, "$eq")
1723 DEF_METHOD(Ne, 1, "$ne")
1724 DEF_METHOD(Eqx, 1, "$eqx")
1725 DEF_METHOD(Nex, 1, "$nex")
1726 DEF_METHOD(Ge, 1, "$ge")
1727 DEF_METHOD(Gt, 1, "$gt")
1728 DEF_METHOD(Add, max(sig_a.size(), sig_b.size()), "$add")
1729 DEF_METHOD(Sub, max(sig_a.size(), sig_b.size()), "$sub")
1730 DEF_METHOD(Mul, max(sig_a.size(), sig_b.size()), "$mul")
1731 DEF_METHOD(Div, max(sig_a.size(), sig_b.size()), "$div")
1732 DEF_METHOD(Mod, max(sig_a.size(), sig_b.size()), "$mod")
1733 DEF_METHOD(LogicAnd, 1, "$logic_and")
1734 DEF_METHOD(LogicOr, 1, "$logic_or")
1735 #undef DEF_METHOD
1736
1737 #define DEF_METHOD(_func, _type, _pmux) \
1738 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, RTLIL::SigSpec sig_y, const std::string &src) { \
1739 RTLIL::Cell *cell = addCell(name, _type); \
1740 cell->parameters["\\WIDTH"] = sig_a.size(); \
1741 if (_pmux) cell->parameters["\\S_WIDTH"] = sig_s.size(); \
1742 cell->setPort("\\A", sig_a); \
1743 cell->setPort("\\B", sig_b); \
1744 cell->setPort("\\S", sig_s); \
1745 cell->setPort("\\Y", sig_y); \
1746 cell->set_src_attribute(src); \
1747 return cell; \
1748 } \
1749 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, const std::string &src) { \
1750 RTLIL::SigSpec sig_y = addWire(NEW_ID, sig_a.size()); \
1751 add ## _func(name, sig_a, sig_b, sig_s, sig_y, src); \
1752 return sig_y; \
1753 }
1754 DEF_METHOD(Mux, "$mux", 0)
1755 DEF_METHOD(Pmux, "$pmux", 1)
1756 #undef DEF_METHOD
1757
1758 #define DEF_METHOD_2(_func, _type, _P1, _P2) \
1759 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, const std::string &src) { \
1760 RTLIL::Cell *cell = addCell(name, _type); \
1761 cell->setPort("\\" #_P1, sig1); \
1762 cell->setPort("\\" #_P2, sig2); \
1763 cell->set_src_attribute(src); \
1764 return cell; \
1765 } \
1766 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, const std::string &src) { \
1767 RTLIL::SigBit sig2 = addWire(NEW_ID); \
1768 add ## _func(name, sig1, sig2, src); \
1769 return sig2; \
1770 }
1771 #define DEF_METHOD_3(_func, _type, _P1, _P2, _P3) \
1772 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, const std::string &src) { \
1773 RTLIL::Cell *cell = addCell(name, _type); \
1774 cell->setPort("\\" #_P1, sig1); \
1775 cell->setPort("\\" #_P2, sig2); \
1776 cell->setPort("\\" #_P3, sig3); \
1777 cell->set_src_attribute(src); \
1778 return cell; \
1779 } \
1780 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, const std::string &src) { \
1781 RTLIL::SigBit sig3 = addWire(NEW_ID); \
1782 add ## _func(name, sig1, sig2, sig3, src); \
1783 return sig3; \
1784 }
1785 #define DEF_METHOD_4(_func, _type, _P1, _P2, _P3, _P4) \
1786 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, RTLIL::SigBit sig4, const std::string &src) { \
1787 RTLIL::Cell *cell = addCell(name, _type); \
1788 cell->setPort("\\" #_P1, sig1); \
1789 cell->setPort("\\" #_P2, sig2); \
1790 cell->setPort("\\" #_P3, sig3); \
1791 cell->setPort("\\" #_P4, sig4); \
1792 cell->set_src_attribute(src); \
1793 return cell; \
1794 } \
1795 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, const std::string &src) { \
1796 RTLIL::SigBit sig4 = addWire(NEW_ID); \
1797 add ## _func(name, sig1, sig2, sig3, sig4, src); \
1798 return sig4; \
1799 }
1800 #define DEF_METHOD_5(_func, _type, _P1, _P2, _P3, _P4, _P5) \
1801 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, RTLIL::SigBit sig4, RTLIL::SigBit sig5, const std::string &src) { \
1802 RTLIL::Cell *cell = addCell(name, _type); \
1803 cell->setPort("\\" #_P1, sig1); \
1804 cell->setPort("\\" #_P2, sig2); \
1805 cell->setPort("\\" #_P3, sig3); \
1806 cell->setPort("\\" #_P4, sig4); \
1807 cell->setPort("\\" #_P5, sig5); \
1808 cell->set_src_attribute(src); \
1809 return cell; \
1810 } \
1811 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, RTLIL::SigBit sig4, const std::string &src) { \
1812 RTLIL::SigBit sig5 = addWire(NEW_ID); \
1813 add ## _func(name, sig1, sig2, sig3, sig4, sig5, src); \
1814 return sig5; \
1815 }
1816 DEF_METHOD_2(BufGate, "$_BUF_", A, Y)
1817 DEF_METHOD_2(NotGate, "$_NOT_", A, Y)
1818 DEF_METHOD_3(AndGate, "$_AND_", A, B, Y)
1819 DEF_METHOD_3(NandGate, "$_NAND_", A, B, Y)
1820 DEF_METHOD_3(OrGate, "$_OR_", A, B, Y)
1821 DEF_METHOD_3(NorGate, "$_NOR_", A, B, Y)
1822 DEF_METHOD_3(XorGate, "$_XOR_", A, B, Y)
1823 DEF_METHOD_3(XnorGate, "$_XNOR_", A, B, Y)
1824 DEF_METHOD_3(AndnotGate, "$_ANDNOT_", A, B, Y)
1825 DEF_METHOD_3(OrnotGate, "$_ORNOT_", A, B, Y)
1826 DEF_METHOD_4(MuxGate, "$_MUX_", A, B, S, Y)
1827 DEF_METHOD_4(Aoi3Gate, "$_AOI3_", A, B, C, Y)
1828 DEF_METHOD_4(Oai3Gate, "$_OAI3_", A, B, C, Y)
1829 DEF_METHOD_5(Aoi4Gate, "$_AOI4_", A, B, C, D, Y)
1830 DEF_METHOD_5(Oai4Gate, "$_OAI4_", A, B, C, D, Y)
1831 #undef DEF_METHOD_2
1832 #undef DEF_METHOD_3
1833 #undef DEF_METHOD_4
1834 #undef DEF_METHOD_5
1835
1836 RTLIL::Cell* RTLIL::Module::addPow(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool a_signed, bool b_signed, const std::string &src)
1837 {
1838 RTLIL::Cell *cell = addCell(name, "$pow");
1839 cell->parameters["\\A_SIGNED"] = a_signed;
1840 cell->parameters["\\B_SIGNED"] = b_signed;
1841 cell->parameters["\\A_WIDTH"] = sig_a.size();
1842 cell->parameters["\\B_WIDTH"] = sig_b.size();
1843 cell->parameters["\\Y_WIDTH"] = sig_y.size();
1844 cell->setPort("\\A", sig_a);
1845 cell->setPort("\\B", sig_b);
1846 cell->setPort("\\Y", sig_y);
1847 cell->set_src_attribute(src);
1848 return cell;
1849 }
1850
1851 RTLIL::Cell* RTLIL::Module::addSlice(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, RTLIL::Const offset, const std::string &src)
1852 {
1853 RTLIL::Cell *cell = addCell(name, "$slice");
1854 cell->parameters["\\A_WIDTH"] = sig_a.size();
1855 cell->parameters["\\Y_WIDTH"] = sig_y.size();
1856 cell->parameters["\\OFFSET"] = offset;
1857 cell->setPort("\\A", sig_a);
1858 cell->setPort("\\Y", sig_y);
1859 cell->set_src_attribute(src);
1860 return cell;
1861 }
1862
1863 RTLIL::Cell* RTLIL::Module::addConcat(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, const std::string &src)
1864 {
1865 RTLIL::Cell *cell = addCell(name, "$concat");
1866 cell->parameters["\\A_WIDTH"] = sig_a.size();
1867 cell->parameters["\\B_WIDTH"] = sig_b.size();
1868 cell->setPort("\\A", sig_a);
1869 cell->setPort("\\B", sig_b);
1870 cell->setPort("\\Y", sig_y);
1871 cell->set_src_attribute(src);
1872 return cell;
1873 }
1874
1875 RTLIL::Cell* RTLIL::Module::addLut(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, RTLIL::Const lut, const std::string &src)
1876 {
1877 RTLIL::Cell *cell = addCell(name, "$lut");
1878 cell->parameters["\\LUT"] = lut;
1879 cell->parameters["\\WIDTH"] = sig_a.size();
1880 cell->setPort("\\A", sig_a);
1881 cell->setPort("\\Y", sig_y);
1882 cell->set_src_attribute(src);
1883 return cell;
1884 }
1885
1886 RTLIL::Cell* RTLIL::Module::addTribuf(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_y, const std::string &src)
1887 {
1888 RTLIL::Cell *cell = addCell(name, "$tribuf");
1889 cell->parameters["\\WIDTH"] = sig_a.size();
1890 cell->setPort("\\A", sig_a);
1891 cell->setPort("\\EN", sig_en);
1892 cell->setPort("\\Y", sig_y);
1893 cell->set_src_attribute(src);
1894 return cell;
1895 }
1896
1897 RTLIL::Cell* RTLIL::Module::addAssert(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src)
1898 {
1899 RTLIL::Cell *cell = addCell(name, "$assert");
1900 cell->setPort("\\A", sig_a);
1901 cell->setPort("\\EN", sig_en);
1902 cell->set_src_attribute(src);
1903 return cell;
1904 }
1905
1906 RTLIL::Cell* RTLIL::Module::addAssume(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src)
1907 {
1908 RTLIL::Cell *cell = addCell(name, "$assume");
1909 cell->setPort("\\A", sig_a);
1910 cell->setPort("\\EN", sig_en);
1911 cell->set_src_attribute(src);
1912 return cell;
1913 }
1914
1915 RTLIL::Cell* RTLIL::Module::addLive(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src)
1916 {
1917 RTLIL::Cell *cell = addCell(name, "$live");
1918 cell->setPort("\\A", sig_a);
1919 cell->setPort("\\EN", sig_en);
1920 cell->set_src_attribute(src);
1921 return cell;
1922 }
1923
1924 RTLIL::Cell* RTLIL::Module::addFair(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src)
1925 {
1926 RTLIL::Cell *cell = addCell(name, "$fair");
1927 cell->setPort("\\A", sig_a);
1928 cell->setPort("\\EN", sig_en);
1929 cell->set_src_attribute(src);
1930 return cell;
1931 }
1932
1933 RTLIL::Cell* RTLIL::Module::addCover(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src)
1934 {
1935 RTLIL::Cell *cell = addCell(name, "$cover");
1936 cell->setPort("\\A", sig_a);
1937 cell->setPort("\\EN", sig_en);
1938 cell->set_src_attribute(src);
1939 return cell;
1940 }
1941
1942 RTLIL::Cell* RTLIL::Module::addEquiv(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, const std::string &src)
1943 {
1944 RTLIL::Cell *cell = addCell(name, "$equiv");
1945 cell->setPort("\\A", sig_a);
1946 cell->setPort("\\B", sig_b);
1947 cell->setPort("\\Y", sig_y);
1948 cell->set_src_attribute(src);
1949 return cell;
1950 }
1951
1952 RTLIL::Cell* RTLIL::Module::addSr(RTLIL::IdString name, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr, RTLIL::SigSpec sig_q, bool set_polarity, bool clr_polarity, const std::string &src)
1953 {
1954 RTLIL::Cell *cell = addCell(name, "$sr");
1955 cell->parameters["\\SET_POLARITY"] = set_polarity;
1956 cell->parameters["\\CLR_POLARITY"] = clr_polarity;
1957 cell->parameters["\\WIDTH"] = sig_q.size();
1958 cell->setPort("\\SET", sig_set);
1959 cell->setPort("\\CLR", sig_clr);
1960 cell->setPort("\\Q", sig_q);
1961 cell->set_src_attribute(src);
1962 return cell;
1963 }
1964
1965 RTLIL::Cell* RTLIL::Module::addFf(RTLIL::IdString name, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, const std::string &src)
1966 {
1967 RTLIL::Cell *cell = addCell(name, "$ff");
1968 cell->parameters["\\WIDTH"] = sig_q.size();
1969 cell->setPort("\\D", sig_d);
1970 cell->setPort("\\Q", sig_q);
1971 cell->set_src_attribute(src);
1972 return cell;
1973 }
1974
1975 RTLIL::Cell* RTLIL::Module::addDff(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, const std::string &src)
1976 {
1977 RTLIL::Cell *cell = addCell(name, "$dff");
1978 cell->parameters["\\CLK_POLARITY"] = clk_polarity;
1979 cell->parameters["\\WIDTH"] = sig_q.size();
1980 cell->setPort("\\CLK", sig_clk);
1981 cell->setPort("\\D", sig_d);
1982 cell->setPort("\\Q", sig_q);
1983 cell->set_src_attribute(src);
1984 return cell;
1985 }
1986
1987 RTLIL::Cell* RTLIL::Module::addDffe(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, bool en_polarity, const std::string &src)
1988 {
1989 RTLIL::Cell *cell = addCell(name, "$dffe");
1990 cell->parameters["\\CLK_POLARITY"] = clk_polarity;
1991 cell->parameters["\\EN_POLARITY"] = en_polarity;
1992 cell->parameters["\\WIDTH"] = sig_q.size();
1993 cell->setPort("\\CLK", sig_clk);
1994 cell->setPort("\\EN", sig_en);
1995 cell->setPort("\\D", sig_d);
1996 cell->setPort("\\Q", sig_q);
1997 cell->set_src_attribute(src);
1998 return cell;
1999 }
2000
2001 RTLIL::Cell* RTLIL::Module::addDffsr(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
2002 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
2003 {
2004 RTLIL::Cell *cell = addCell(name, "$dffsr");
2005 cell->parameters["\\CLK_POLARITY"] = clk_polarity;
2006 cell->parameters["\\SET_POLARITY"] = set_polarity;
2007 cell->parameters["\\CLR_POLARITY"] = clr_polarity;
2008 cell->parameters["\\WIDTH"] = sig_q.size();
2009 cell->setPort("\\CLK", sig_clk);
2010 cell->setPort("\\SET", sig_set);
2011 cell->setPort("\\CLR", sig_clr);
2012 cell->setPort("\\D", sig_d);
2013 cell->setPort("\\Q", sig_q);
2014 cell->set_src_attribute(src);
2015 return cell;
2016 }
2017
2018 RTLIL::Cell* RTLIL::Module::addAdff(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_arst, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q,
2019 RTLIL::Const arst_value, bool clk_polarity, bool arst_polarity, const std::string &src)
2020 {
2021 RTLIL::Cell *cell = addCell(name, "$adff");
2022 cell->parameters["\\CLK_POLARITY"] = clk_polarity;
2023 cell->parameters["\\ARST_POLARITY"] = arst_polarity;
2024 cell->parameters["\\ARST_VALUE"] = arst_value;
2025 cell->parameters["\\WIDTH"] = sig_q.size();
2026 cell->setPort("\\CLK", sig_clk);
2027 cell->setPort("\\ARST", sig_arst);
2028 cell->setPort("\\D", sig_d);
2029 cell->setPort("\\Q", sig_q);
2030 cell->set_src_attribute(src);
2031 return cell;
2032 }
2033
2034 RTLIL::Cell* RTLIL::Module::addDlatch(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity, const std::string &src)
2035 {
2036 RTLIL::Cell *cell = addCell(name, "$dlatch");
2037 cell->parameters["\\EN_POLARITY"] = en_polarity;
2038 cell->parameters["\\WIDTH"] = sig_q.size();
2039 cell->setPort("\\EN", sig_en);
2040 cell->setPort("\\D", sig_d);
2041 cell->setPort("\\Q", sig_q);
2042 cell->set_src_attribute(src);
2043 return cell;
2044 }
2045
2046 RTLIL::Cell* RTLIL::Module::addDlatchsr(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
2047 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
2048 {
2049 RTLIL::Cell *cell = addCell(name, "$dlatchsr");
2050 cell->parameters["\\EN_POLARITY"] = en_polarity;
2051 cell->parameters["\\SET_POLARITY"] = set_polarity;
2052 cell->parameters["\\CLR_POLARITY"] = clr_polarity;
2053 cell->parameters["\\WIDTH"] = sig_q.size();
2054 cell->setPort("\\EN", sig_en);
2055 cell->setPort("\\SET", sig_set);
2056 cell->setPort("\\CLR", sig_clr);
2057 cell->setPort("\\D", sig_d);
2058 cell->setPort("\\Q", sig_q);
2059 cell->set_src_attribute(src);
2060 return cell;
2061 }
2062
2063 RTLIL::Cell* RTLIL::Module::addFfGate(RTLIL::IdString name, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, const std::string &src)
2064 {
2065 RTLIL::Cell *cell = addCell(name, "$_FF_");
2066 cell->setPort("\\D", sig_d);
2067 cell->setPort("\\Q", sig_q);
2068 cell->set_src_attribute(src);
2069 return cell;
2070 }
2071
2072 RTLIL::Cell* RTLIL::Module::addDffGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, const std::string &src)
2073 {
2074 RTLIL::Cell *cell = addCell(name, stringf("$_DFF_%c_", clk_polarity ? 'P' : 'N'));
2075 cell->setPort("\\C", sig_clk);
2076 cell->setPort("\\D", sig_d);
2077 cell->setPort("\\Q", sig_q);
2078 cell->set_src_attribute(src);
2079 return cell;
2080 }
2081
2082 RTLIL::Cell* RTLIL::Module::addDffeGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, bool en_polarity, const std::string &src)
2083 {
2084 RTLIL::Cell *cell = addCell(name, stringf("$_DFFE_%c%c_", clk_polarity ? 'P' : 'N', en_polarity ? 'P' : 'N'));
2085 cell->setPort("\\C", sig_clk);
2086 cell->setPort("\\E", sig_en);
2087 cell->setPort("\\D", sig_d);
2088 cell->setPort("\\Q", sig_q);
2089 cell->set_src_attribute(src);
2090 return cell;
2091 }
2092
2093 RTLIL::Cell* RTLIL::Module::addDffsrGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
2094 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
2095 {
2096 RTLIL::Cell *cell = addCell(name, stringf("$_DFFSR_%c%c%c_", clk_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N'));
2097 cell->setPort("\\C", sig_clk);
2098 cell->setPort("\\S", sig_set);
2099 cell->setPort("\\R", sig_clr);
2100 cell->setPort("\\D", sig_d);
2101 cell->setPort("\\Q", sig_q);
2102 cell->set_src_attribute(src);
2103 return cell;
2104 }
2105
2106 RTLIL::Cell* RTLIL::Module::addAdffGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_arst, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q,
2107 bool arst_value, bool clk_polarity, bool arst_polarity, const std::string &src)
2108 {
2109 RTLIL::Cell *cell = addCell(name, stringf("$_DFF_%c%c%c_", clk_polarity ? 'P' : 'N', arst_polarity ? 'P' : 'N', arst_value ? '1' : '0'));
2110 cell->setPort("\\C", sig_clk);
2111 cell->setPort("\\R", sig_arst);
2112 cell->setPort("\\D", sig_d);
2113 cell->setPort("\\Q", sig_q);
2114 cell->set_src_attribute(src);
2115 return cell;
2116 }
2117
2118 RTLIL::Cell* RTLIL::Module::addDlatchGate(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity, const std::string &src)
2119 {
2120 RTLIL::Cell *cell = addCell(name, stringf("$_DLATCH_%c_", en_polarity ? 'P' : 'N'));
2121 cell->setPort("\\E", sig_en);
2122 cell->setPort("\\D", sig_d);
2123 cell->setPort("\\Q", sig_q);
2124 cell->set_src_attribute(src);
2125 return cell;
2126 }
2127
2128 RTLIL::Cell* RTLIL::Module::addDlatchsrGate(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
2129 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
2130 {
2131 RTLIL::Cell *cell = addCell(name, stringf("$_DLATCHSR_%c%c%c_", en_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N'));
2132 cell->setPort("\\E", sig_en);
2133 cell->setPort("\\S", sig_set);
2134 cell->setPort("\\R", sig_clr);
2135 cell->setPort("\\D", sig_d);
2136 cell->setPort("\\Q", sig_q);
2137 cell->set_src_attribute(src);
2138 return cell;
2139 }
2140
2141 RTLIL::SigSpec RTLIL::Module::Anyconst(RTLIL::IdString name, int width, const std::string &src)
2142 {
2143 RTLIL::SigSpec sig = addWire(NEW_ID, width);
2144 Cell *cell = addCell(name, "$anyconst");
2145 cell->setParam("\\WIDTH", width);
2146 cell->setPort("\\Y", sig);
2147 cell->set_src_attribute(src);
2148 return sig;
2149 }
2150
2151 RTLIL::SigSpec RTLIL::Module::Anyseq(RTLIL::IdString name, int width, const std::string &src)
2152 {
2153 RTLIL::SigSpec sig = addWire(NEW_ID, width);
2154 Cell *cell = addCell(name, "$anyseq");
2155 cell->setParam("\\WIDTH", width);
2156 cell->setPort("\\Y", sig);
2157 cell->set_src_attribute(src);
2158 return sig;
2159 }
2160
2161 RTLIL::SigSpec RTLIL::Module::Allconst(RTLIL::IdString name, int width, const std::string &src)
2162 {
2163 RTLIL::SigSpec sig = addWire(NEW_ID, width);
2164 Cell *cell = addCell(name, "$allconst");
2165 cell->setParam("\\WIDTH", width);
2166 cell->setPort("\\Y", sig);
2167 cell->set_src_attribute(src);
2168 return sig;
2169 }
2170
2171 RTLIL::SigSpec RTLIL::Module::Allseq(RTLIL::IdString name, int width, const std::string &src)
2172 {
2173 RTLIL::SigSpec sig = addWire(NEW_ID, width);
2174 Cell *cell = addCell(name, "$allseq");
2175 cell->setParam("\\WIDTH", width);
2176 cell->setPort("\\Y", sig);
2177 cell->set_src_attribute(src);
2178 return sig;
2179 }
2180
2181 RTLIL::SigSpec RTLIL::Module::Initstate(RTLIL::IdString name, const std::string &src)
2182 {
2183 RTLIL::SigSpec sig = addWire(NEW_ID);
2184 Cell *cell = addCell(name, "$initstate");
2185 cell->setPort("\\Y", sig);
2186 cell->set_src_attribute(src);
2187 return sig;
2188 }
2189
2190 RTLIL::Wire::Wire()
2191 {
2192 static unsigned int hashidx_count = 123456789;
2193 hashidx_count = mkhash_xorshift(hashidx_count);
2194 hashidx_ = hashidx_count;
2195
2196 module = nullptr;
2197 width = 1;
2198 start_offset = 0;
2199 port_id = 0;
2200 port_input = false;
2201 port_output = false;
2202 upto = false;
2203 }
2204
2205 RTLIL::Memory::Memory()
2206 {
2207 static unsigned int hashidx_count = 123456789;
2208 hashidx_count = mkhash_xorshift(hashidx_count);
2209 hashidx_ = hashidx_count;
2210
2211 width = 1;
2212 start_offset = 0;
2213 size = 0;
2214 }
2215
2216 RTLIL::Cell::Cell() : module(nullptr)
2217 {
2218 static unsigned int hashidx_count = 123456789;
2219 hashidx_count = mkhash_xorshift(hashidx_count);
2220 hashidx_ = hashidx_count;
2221
2222 // log("#memtrace# %p\n", this);
2223 memhasher();
2224 }
2225
2226 bool RTLIL::Cell::hasPort(RTLIL::IdString portname) const
2227 {
2228 return connections_.count(portname) != 0;
2229 }
2230
2231 void RTLIL::Cell::unsetPort(RTLIL::IdString portname)
2232 {
2233 RTLIL::SigSpec signal;
2234 auto conn_it = connections_.find(portname);
2235
2236 if (conn_it != connections_.end())
2237 {
2238 for (auto mon : module->monitors)
2239 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
2240
2241 if (module->design)
2242 for (auto mon : module->design->monitors)
2243 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
2244
2245 if (yosys_xtrace) {
2246 log("#X# Unconnect %s.%s.%s\n", log_id(this->module), log_id(this), log_id(portname));
2247 log_backtrace("-X- ", yosys_xtrace-1);
2248 }
2249
2250 connections_.erase(conn_it);
2251 }
2252 }
2253
2254 void RTLIL::Cell::setPort(RTLIL::IdString portname, RTLIL::SigSpec signal)
2255 {
2256 auto conn_it = connections_.find(portname);
2257
2258 if (conn_it == connections_.end()) {
2259 connections_[portname] = RTLIL::SigSpec();
2260 conn_it = connections_.find(portname);
2261 log_assert(conn_it != connections_.end());
2262 } else
2263 if (conn_it->second == signal)
2264 return;
2265
2266 for (auto mon : module->monitors)
2267 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
2268
2269 if (module->design)
2270 for (auto mon : module->design->monitors)
2271 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
2272
2273 if (yosys_xtrace) {
2274 log("#X# Connect %s.%s.%s = %s (%d)\n", log_id(this->module), log_id(this), log_id(portname), log_signal(signal), GetSize(signal));
2275 log_backtrace("-X- ", yosys_xtrace-1);
2276 }
2277
2278 conn_it->second = signal;
2279 }
2280
2281 const RTLIL::SigSpec &RTLIL::Cell::getPort(RTLIL::IdString portname) const
2282 {
2283 return connections_.at(portname);
2284 }
2285
2286 const dict<RTLIL::IdString, RTLIL::SigSpec> &RTLIL::Cell::connections() const
2287 {
2288 return connections_;
2289 }
2290
2291 bool RTLIL::Cell::known() const
2292 {
2293 if (yosys_celltypes.cell_known(type))
2294 return true;
2295 if (module && module->design && module->design->module(type))
2296 return true;
2297 return false;
2298 }
2299
2300 bool RTLIL::Cell::input(RTLIL::IdString portname) const
2301 {
2302 if (yosys_celltypes.cell_known(type))
2303 return yosys_celltypes.cell_input(type, portname);
2304 if (module && module->design) {
2305 RTLIL::Module *m = module->design->module(type);
2306 RTLIL::Wire *w = m ? m->wire(portname) : nullptr;
2307 return w && w->port_input;
2308 }
2309 return false;
2310 }
2311
2312 bool RTLIL::Cell::output(RTLIL::IdString portname) const
2313 {
2314 if (yosys_celltypes.cell_known(type))
2315 return yosys_celltypes.cell_output(type, portname);
2316 if (module && module->design) {
2317 RTLIL::Module *m = module->design->module(type);
2318 RTLIL::Wire *w = m ? m->wire(portname) : nullptr;
2319 return w && w->port_output;
2320 }
2321 return false;
2322 }
2323
2324 bool RTLIL::Cell::hasParam(RTLIL::IdString paramname) const
2325 {
2326 return parameters.count(paramname) != 0;
2327 }
2328
2329 void RTLIL::Cell::unsetParam(RTLIL::IdString paramname)
2330 {
2331 parameters.erase(paramname);
2332 }
2333
2334 void RTLIL::Cell::setParam(RTLIL::IdString paramname, RTLIL::Const value)
2335 {
2336 parameters[paramname] = value;
2337 }
2338
2339 const RTLIL::Const &RTLIL::Cell::getParam(RTLIL::IdString paramname) const
2340 {
2341 return parameters.at(paramname);
2342 }
2343
2344 void RTLIL::Cell::sort()
2345 {
2346 connections_.sort(sort_by_id_str());
2347 parameters.sort(sort_by_id_str());
2348 attributes.sort(sort_by_id_str());
2349 }
2350
2351 void RTLIL::Cell::check()
2352 {
2353 #ifndef NDEBUG
2354 InternalCellChecker checker(NULL, this);
2355 checker.check();
2356 #endif
2357 }
2358
2359 void RTLIL::Cell::fixup_parameters(bool set_a_signed, bool set_b_signed)
2360 {
2361 if (type.substr(0, 1) != "$" || type.substr(0, 2) == "$_" || type.substr(0, 8) == "$paramod" ||
2362 type.substr(0, 9) == "$verific$" || type.substr(0, 7) == "$array:" || type.substr(0, 8) == "$extern:")
2363 return;
2364
2365 if (type == "$mux" || type == "$pmux") {
2366 parameters["\\WIDTH"] = GetSize(connections_["\\Y"]);
2367 if (type == "$pmux")
2368 parameters["\\S_WIDTH"] = GetSize(connections_["\\S"]);
2369 check();
2370 return;
2371 }
2372
2373 if (type == "$lut" || type == "$sop") {
2374 parameters["\\WIDTH"] = GetSize(connections_["\\A"]);
2375 return;
2376 }
2377
2378 if (type == "$fa") {
2379 parameters["\\WIDTH"] = GetSize(connections_["\\Y"]);
2380 return;
2381 }
2382
2383 if (type == "$lcu") {
2384 parameters["\\WIDTH"] = GetSize(connections_["\\CO"]);
2385 return;
2386 }
2387
2388 bool signedness_ab = !type.in("$slice", "$concat", "$macc");
2389
2390 if (connections_.count("\\A")) {
2391 if (signedness_ab) {
2392 if (set_a_signed)
2393 parameters["\\A_SIGNED"] = true;
2394 else if (parameters.count("\\A_SIGNED") == 0)
2395 parameters["\\A_SIGNED"] = false;
2396 }
2397 parameters["\\A_WIDTH"] = GetSize(connections_["\\A"]);
2398 }
2399
2400 if (connections_.count("\\B")) {
2401 if (signedness_ab) {
2402 if (set_b_signed)
2403 parameters["\\B_SIGNED"] = true;
2404 else if (parameters.count("\\B_SIGNED") == 0)
2405 parameters["\\B_SIGNED"] = false;
2406 }
2407 parameters["\\B_WIDTH"] = GetSize(connections_["\\B"]);
2408 }
2409
2410 if (connections_.count("\\Y"))
2411 parameters["\\Y_WIDTH"] = GetSize(connections_["\\Y"]);
2412
2413 if (connections_.count("\\Q"))
2414 parameters["\\WIDTH"] = GetSize(connections_["\\Q"]);
2415
2416 check();
2417 }
2418
2419 RTLIL::SigChunk::SigChunk()
2420 {
2421 wire = NULL;
2422 width = 0;
2423 offset = 0;
2424 }
2425
2426 RTLIL::SigChunk::SigChunk(const RTLIL::Const &value)
2427 {
2428 wire = NULL;
2429 data = value.bits;
2430 width = GetSize(data);
2431 offset = 0;
2432 }
2433
2434 RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire)
2435 {
2436 log_assert(wire != nullptr);
2437 this->wire = wire;
2438 this->width = wire->width;
2439 this->offset = 0;
2440 }
2441
2442 RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire, int offset, int width)
2443 {
2444 log_assert(wire != nullptr);
2445 this->wire = wire;
2446 this->width = width;
2447 this->offset = offset;
2448 }
2449
2450 RTLIL::SigChunk::SigChunk(const std::string &str)
2451 {
2452 wire = NULL;
2453 data = RTLIL::Const(str).bits;
2454 width = GetSize(data);
2455 offset = 0;
2456 }
2457
2458 RTLIL::SigChunk::SigChunk(int val, int width)
2459 {
2460 wire = NULL;
2461 data = RTLIL::Const(val, width).bits;
2462 this->width = GetSize(data);
2463 offset = 0;
2464 }
2465
2466 RTLIL::SigChunk::SigChunk(RTLIL::State bit, int width)
2467 {
2468 wire = NULL;
2469 data = RTLIL::Const(bit, width).bits;
2470 this->width = GetSize(data);
2471 offset = 0;
2472 }
2473
2474 RTLIL::SigChunk::SigChunk(RTLIL::SigBit bit)
2475 {
2476 wire = bit.wire;
2477 offset = 0;
2478 if (wire == NULL)
2479 data = RTLIL::Const(bit.data).bits;
2480 else
2481 offset = bit.offset;
2482 width = 1;
2483 }
2484
2485 RTLIL::SigChunk RTLIL::SigChunk::extract(int offset, int length) const
2486 {
2487 RTLIL::SigChunk ret;
2488 if (wire) {
2489 ret.wire = wire;
2490 ret.offset = this->offset + offset;
2491 ret.width = length;
2492 } else {
2493 for (int i = 0; i < length; i++)
2494 ret.data.push_back(data[offset+i]);
2495 ret.width = length;
2496 }
2497 return ret;
2498 }
2499
2500 bool RTLIL::SigChunk::operator <(const RTLIL::SigChunk &other) const
2501 {
2502 if (wire && other.wire)
2503 if (wire->name != other.wire->name)
2504 return wire->name < other.wire->name;
2505
2506 if (wire != other.wire)
2507 return wire < other.wire;
2508
2509 if (offset != other.offset)
2510 return offset < other.offset;
2511
2512 if (width != other.width)
2513 return width < other.width;
2514
2515 return data < other.data;
2516 }
2517
2518 bool RTLIL::SigChunk::operator ==(const RTLIL::SigChunk &other) const
2519 {
2520 return wire == other.wire && width == other.width && offset == other.offset && data == other.data;
2521 }
2522
2523 bool RTLIL::SigChunk::operator !=(const RTLIL::SigChunk &other) const
2524 {
2525 if (*this == other)
2526 return false;
2527 return true;
2528 }
2529
2530 RTLIL::SigSpec::SigSpec()
2531 {
2532 width_ = 0;
2533 hash_ = 0;
2534 }
2535
2536 RTLIL::SigSpec::SigSpec(const RTLIL::SigSpec &other)
2537 {
2538 *this = other;
2539 }
2540
2541 RTLIL::SigSpec::SigSpec(std::initializer_list<RTLIL::SigSpec> parts)
2542 {
2543 cover("kernel.rtlil.sigspec.init.list");
2544
2545 width_ = 0;
2546 hash_ = 0;
2547
2548 std::vector<RTLIL::SigSpec> parts_vec(parts.begin(), parts.end());
2549 for (auto it = parts_vec.rbegin(); it != parts_vec.rend(); it++)
2550 append(*it);
2551 }
2552
2553 const RTLIL::SigSpec &RTLIL::SigSpec::operator=(const RTLIL::SigSpec &other)
2554 {
2555 cover("kernel.rtlil.sigspec.assign");
2556
2557 width_ = other.width_;
2558 hash_ = other.hash_;
2559 chunks_ = other.chunks_;
2560 bits_.clear();
2561
2562 if (!other.bits_.empty())
2563 {
2564 RTLIL::SigChunk *last = NULL;
2565 int last_end_offset = 0;
2566
2567 for (auto &bit : other.bits_) {
2568 if (last && bit.wire == last->wire) {
2569 if (bit.wire == NULL) {
2570 last->data.push_back(bit.data);
2571 last->width++;
2572 continue;
2573 } else if (last_end_offset == bit.offset) {
2574 last_end_offset++;
2575 last->width++;
2576 continue;
2577 }
2578 }
2579 chunks_.push_back(bit);
2580 last = &chunks_.back();
2581 last_end_offset = bit.offset + 1;
2582 }
2583
2584 check();
2585 }
2586
2587 return *this;
2588 }
2589
2590 RTLIL::SigSpec::SigSpec(const RTLIL::Const &value)
2591 {
2592 cover("kernel.rtlil.sigspec.init.const");
2593
2594 chunks_.push_back(RTLIL::SigChunk(value));
2595 width_ = chunks_.back().width;
2596 hash_ = 0;
2597 check();
2598 }
2599
2600 RTLIL::SigSpec::SigSpec(const RTLIL::SigChunk &chunk)
2601 {
2602 cover("kernel.rtlil.sigspec.init.chunk");
2603
2604 chunks_.push_back(chunk);
2605 width_ = chunks_.back().width;
2606 hash_ = 0;
2607 check();
2608 }
2609
2610 RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire)
2611 {
2612 cover("kernel.rtlil.sigspec.init.wire");
2613
2614 chunks_.push_back(RTLIL::SigChunk(wire));
2615 width_ = chunks_.back().width;
2616 hash_ = 0;
2617 check();
2618 }
2619
2620 RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire, int offset, int width)
2621 {
2622 cover("kernel.rtlil.sigspec.init.wire_part");
2623
2624 chunks_.push_back(RTLIL::SigChunk(wire, offset, width));
2625 width_ = chunks_.back().width;
2626 hash_ = 0;
2627 check();
2628 }
2629
2630 RTLIL::SigSpec::SigSpec(const std::string &str)
2631 {
2632 cover("kernel.rtlil.sigspec.init.str");
2633
2634 chunks_.push_back(RTLIL::SigChunk(str));
2635 width_ = chunks_.back().width;
2636 hash_ = 0;
2637 check();
2638 }
2639
2640 RTLIL::SigSpec::SigSpec(int val, int width)
2641 {
2642 cover("kernel.rtlil.sigspec.init.int");
2643
2644 chunks_.push_back(RTLIL::SigChunk(val, width));
2645 width_ = width;
2646 hash_ = 0;
2647 check();
2648 }
2649
2650 RTLIL::SigSpec::SigSpec(RTLIL::State bit, int width)
2651 {
2652 cover("kernel.rtlil.sigspec.init.state");
2653
2654 chunks_.push_back(RTLIL::SigChunk(bit, width));
2655 width_ = width;
2656 hash_ = 0;
2657 check();
2658 }
2659
2660 RTLIL::SigSpec::SigSpec(RTLIL::SigBit bit, int width)
2661 {
2662 cover("kernel.rtlil.sigspec.init.bit");
2663
2664 if (bit.wire == NULL)
2665 chunks_.push_back(RTLIL::SigChunk(bit.data, width));
2666 else
2667 for (int i = 0; i < width; i++)
2668 chunks_.push_back(bit);
2669 width_ = width;
2670 hash_ = 0;
2671 check();
2672 }
2673
2674 RTLIL::SigSpec::SigSpec(std::vector<RTLIL::SigChunk> chunks)
2675 {
2676 cover("kernel.rtlil.sigspec.init.stdvec_chunks");
2677
2678 width_ = 0;
2679 hash_ = 0;
2680 for (auto &c : chunks)
2681 append(c);
2682 check();
2683 }
2684
2685 RTLIL::SigSpec::SigSpec(std::vector<RTLIL::SigBit> bits)
2686 {
2687 cover("kernel.rtlil.sigspec.init.stdvec_bits");
2688
2689 width_ = 0;
2690 hash_ = 0;
2691 for (auto &bit : bits)
2692 append_bit(bit);
2693 check();
2694 }
2695
2696 RTLIL::SigSpec::SigSpec(pool<RTLIL::SigBit> bits)
2697 {
2698 cover("kernel.rtlil.sigspec.init.pool_bits");
2699
2700 width_ = 0;
2701 hash_ = 0;
2702 for (auto &bit : bits)
2703 append_bit(bit);
2704 check();
2705 }
2706
2707 RTLIL::SigSpec::SigSpec(std::set<RTLIL::SigBit> bits)
2708 {
2709 cover("kernel.rtlil.sigspec.init.stdset_bits");
2710
2711 width_ = 0;
2712 hash_ = 0;
2713 for (auto &bit : bits)
2714 append_bit(bit);
2715 check();
2716 }
2717
2718 RTLIL::SigSpec::SigSpec(bool bit)
2719 {
2720 cover("kernel.rtlil.sigspec.init.bool");
2721
2722 width_ = 0;
2723 hash_ = 0;
2724 append_bit(bit);
2725 check();
2726 }
2727
2728 void RTLIL::SigSpec::pack() const
2729 {
2730 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
2731
2732 if (that->bits_.empty())
2733 return;
2734
2735 cover("kernel.rtlil.sigspec.convert.pack");
2736 log_assert(that->chunks_.empty());
2737
2738 std::vector<RTLIL::SigBit> old_bits;
2739 old_bits.swap(that->bits_);
2740
2741 RTLIL::SigChunk *last = NULL;
2742 int last_end_offset = 0;
2743
2744 for (auto &bit : old_bits) {
2745 if (last && bit.wire == last->wire) {
2746 if (bit.wire == NULL) {
2747 last->data.push_back(bit.data);
2748 last->width++;
2749 continue;
2750 } else if (last_end_offset == bit.offset) {
2751 last_end_offset++;
2752 last->width++;
2753 continue;
2754 }
2755 }
2756 that->chunks_.push_back(bit);
2757 last = &that->chunks_.back();
2758 last_end_offset = bit.offset + 1;
2759 }
2760
2761 check();
2762 }
2763
2764 void RTLIL::SigSpec::unpack() const
2765 {
2766 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
2767
2768 if (that->chunks_.empty())
2769 return;
2770
2771 cover("kernel.rtlil.sigspec.convert.unpack");
2772 log_assert(that->bits_.empty());
2773
2774 that->bits_.reserve(that->width_);
2775 for (auto &c : that->chunks_)
2776 for (int i = 0; i < c.width; i++)
2777 that->bits_.push_back(RTLIL::SigBit(c, i));
2778
2779 that->chunks_.clear();
2780 that->hash_ = 0;
2781 }
2782
2783 void RTLIL::SigSpec::updhash() const
2784 {
2785 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
2786
2787 if (that->hash_ != 0)
2788 return;
2789
2790 cover("kernel.rtlil.sigspec.hash");
2791 that->pack();
2792
2793 that->hash_ = mkhash_init;
2794 for (auto &c : that->chunks_)
2795 if (c.wire == NULL) {
2796 for (auto &v : c.data)
2797 that->hash_ = mkhash(that->hash_, v);
2798 } else {
2799 that->hash_ = mkhash(that->hash_, c.wire->name.index_);
2800 that->hash_ = mkhash(that->hash_, c.offset);
2801 that->hash_ = mkhash(that->hash_, c.width);
2802 }
2803
2804 if (that->hash_ == 0)
2805 that->hash_ = 1;
2806 }
2807
2808 void RTLIL::SigSpec::sort()
2809 {
2810 unpack();
2811 cover("kernel.rtlil.sigspec.sort");
2812 std::sort(bits_.begin(), bits_.end());
2813 }
2814
2815 void RTLIL::SigSpec::sort_and_unify()
2816 {
2817 unpack();
2818 cover("kernel.rtlil.sigspec.sort_and_unify");
2819
2820 // A copy of the bits vector is used to prevent duplicating the logic from
2821 // SigSpec::SigSpec(std::vector<SigBit>). This incurrs an extra copy but
2822 // that isn't showing up as significant in profiles.
2823 std::vector<SigBit> unique_bits = bits_;
2824 std::sort(unique_bits.begin(), unique_bits.end());
2825 auto last = std::unique(unique_bits.begin(), unique_bits.end());
2826 unique_bits.erase(last, unique_bits.end());
2827
2828 *this = unique_bits;
2829 }
2830
2831 void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with)
2832 {
2833 replace(pattern, with, this);
2834 }
2835
2836 void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with, RTLIL::SigSpec *other) const
2837 {
2838 log_assert(other != NULL);
2839 log_assert(width_ == other->width_);
2840 log_assert(pattern.width_ == with.width_);
2841
2842 pattern.unpack();
2843 with.unpack();
2844 unpack();
2845 other->unpack();
2846
2847 for (int i = 0; i < GetSize(pattern.bits_); i++) {
2848 if (pattern.bits_[i].wire != NULL) {
2849 for (int j = 0; j < GetSize(bits_); j++) {
2850 if (bits_[j] == pattern.bits_[i]) {
2851 other->bits_[j] = with.bits_[i];
2852 }
2853 }
2854 }
2855 }
2856
2857 other->check();
2858 }
2859
2860 void RTLIL::SigSpec::replace(const dict<RTLIL::SigBit, RTLIL::SigBit> &rules)
2861 {
2862 replace(rules, this);
2863 }
2864
2865 void RTLIL::SigSpec::replace(const dict<RTLIL::SigBit, RTLIL::SigBit> &rules, RTLIL::SigSpec *other) const
2866 {
2867 cover("kernel.rtlil.sigspec.replace_dict");
2868
2869 log_assert(other != NULL);
2870 log_assert(width_ == other->width_);
2871
2872 unpack();
2873 other->unpack();
2874
2875 for (int i = 0; i < GetSize(bits_); i++) {
2876 auto it = rules.find(bits_[i]);
2877 if (it != rules.end())
2878 other->bits_[i] = it->second;
2879 }
2880
2881 other->check();
2882 }
2883
2884 void RTLIL::SigSpec::replace(const std::map<RTLIL::SigBit, RTLIL::SigBit> &rules)
2885 {
2886 replace(rules, this);
2887 }
2888
2889 void RTLIL::SigSpec::replace(const std::map<RTLIL::SigBit, RTLIL::SigBit> &rules, RTLIL::SigSpec *other) const
2890 {
2891 cover("kernel.rtlil.sigspec.replace_map");
2892
2893 log_assert(other != NULL);
2894 log_assert(width_ == other->width_);
2895
2896 unpack();
2897 other->unpack();
2898
2899 for (int i = 0; i < GetSize(bits_); i++) {
2900 auto it = rules.find(bits_[i]);
2901 if (it != rules.end())
2902 other->bits_[i] = it->second;
2903 }
2904
2905 other->check();
2906 }
2907
2908 void RTLIL::SigSpec::remove(const RTLIL::SigSpec &pattern)
2909 {
2910 remove2(pattern, NULL);
2911 }
2912
2913 void RTLIL::SigSpec::remove(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other) const
2914 {
2915 RTLIL::SigSpec tmp = *this;
2916 tmp.remove2(pattern, other);
2917 }
2918
2919 void RTLIL::SigSpec::remove2(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other)
2920 {
2921 if (other)
2922 cover("kernel.rtlil.sigspec.remove_other");
2923 else
2924 cover("kernel.rtlil.sigspec.remove");
2925
2926 unpack();
2927 if (other != NULL) {
2928 log_assert(width_ == other->width_);
2929 other->unpack();
2930 }
2931
2932 for (int i = GetSize(bits_) - 1; i >= 0; i--)
2933 {
2934 if (bits_[i].wire == NULL) continue;
2935
2936 for (auto &pattern_chunk : pattern.chunks())
2937 if (bits_[i].wire == pattern_chunk.wire &&
2938 bits_[i].offset >= pattern_chunk.offset &&
2939 bits_[i].offset < pattern_chunk.offset + pattern_chunk.width) {
2940 bits_.erase(bits_.begin() + i);
2941 width_--;
2942 if (other != NULL) {
2943 other->bits_.erase(other->bits_.begin() + i);
2944 other->width_--;
2945 }
2946 break;
2947 }
2948 }
2949
2950 check();
2951 }
2952
2953 void RTLIL::SigSpec::remove(const pool<RTLIL::SigBit> &pattern)
2954 {
2955 remove2(pattern, NULL);
2956 }
2957
2958 void RTLIL::SigSpec::remove(const pool<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other) const
2959 {
2960 RTLIL::SigSpec tmp = *this;
2961 tmp.remove2(pattern, other);
2962 }
2963
2964 void RTLIL::SigSpec::remove2(const pool<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other)
2965 {
2966 if (other)
2967 cover("kernel.rtlil.sigspec.remove_other");
2968 else
2969 cover("kernel.rtlil.sigspec.remove");
2970
2971 unpack();
2972
2973 if (other != NULL) {
2974 log_assert(width_ == other->width_);
2975 other->unpack();
2976 }
2977
2978 for (int i = GetSize(bits_) - 1; i >= 0; i--) {
2979 if (bits_[i].wire != NULL && pattern.count(bits_[i])) {
2980 bits_.erase(bits_.begin() + i);
2981 width_--;
2982 if (other != NULL) {
2983 other->bits_.erase(other->bits_.begin() + i);
2984 other->width_--;
2985 }
2986 }
2987 }
2988
2989 check();
2990 }
2991
2992 void RTLIL::SigSpec::remove2(const std::set<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other)
2993 {
2994 if (other)
2995 cover("kernel.rtlil.sigspec.remove_other");
2996 else
2997 cover("kernel.rtlil.sigspec.remove");
2998
2999 unpack();
3000
3001 if (other != NULL) {
3002 log_assert(width_ == other->width_);
3003 other->unpack();
3004 }
3005
3006 for (int i = GetSize(bits_) - 1; i >= 0; i--) {
3007 if (bits_[i].wire != NULL && pattern.count(bits_[i])) {
3008 bits_.erase(bits_.begin() + i);
3009 width_--;
3010 if (other != NULL) {
3011 other->bits_.erase(other->bits_.begin() + i);
3012 other->width_--;
3013 }
3014 }
3015 }
3016
3017 check();
3018 }
3019
3020 RTLIL::SigSpec RTLIL::SigSpec::extract(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec *other) const
3021 {
3022 if (other)
3023 cover("kernel.rtlil.sigspec.extract_other");
3024 else
3025 cover("kernel.rtlil.sigspec.extract");
3026
3027 log_assert(other == NULL || width_ == other->width_);
3028
3029 RTLIL::SigSpec ret;
3030 std::vector<RTLIL::SigBit> bits_match = to_sigbit_vector();
3031
3032 for (auto& pattern_chunk : pattern.chunks()) {
3033 if (other) {
3034 std::vector<RTLIL::SigBit> bits_other = other->to_sigbit_vector();
3035 for (int i = 0; i < width_; i++)
3036 if (bits_match[i].wire &&
3037 bits_match[i].wire == pattern_chunk.wire &&
3038 bits_match[i].offset >= pattern_chunk.offset &&
3039 bits_match[i].offset < pattern_chunk.offset + pattern_chunk.width)
3040 ret.append_bit(bits_other[i]);
3041 } else {
3042 for (int i = 0; i < width_; i++)
3043 if (bits_match[i].wire &&
3044 bits_match[i].wire == pattern_chunk.wire &&
3045 bits_match[i].offset >= pattern_chunk.offset &&
3046 bits_match[i].offset < pattern_chunk.offset + pattern_chunk.width)
3047 ret.append_bit(bits_match[i]);
3048 }
3049 }
3050
3051 ret.check();
3052 return ret;
3053 }
3054
3055 RTLIL::SigSpec RTLIL::SigSpec::extract(const pool<RTLIL::SigBit> &pattern, const RTLIL::SigSpec *other) const
3056 {
3057 if (other)
3058 cover("kernel.rtlil.sigspec.extract_other");
3059 else
3060 cover("kernel.rtlil.sigspec.extract");
3061
3062 log_assert(other == NULL || width_ == other->width_);
3063
3064 std::vector<RTLIL::SigBit> bits_match = to_sigbit_vector();
3065 RTLIL::SigSpec ret;
3066
3067 if (other) {
3068 std::vector<RTLIL::SigBit> bits_other = other->to_sigbit_vector();
3069 for (int i = 0; i < width_; i++)
3070 if (bits_match[i].wire && pattern.count(bits_match[i]))
3071 ret.append_bit(bits_other[i]);
3072 } else {
3073 for (int i = 0; i < width_; i++)
3074 if (bits_match[i].wire && pattern.count(bits_match[i]))
3075 ret.append_bit(bits_match[i]);
3076 }
3077
3078 ret.check();
3079 return ret;
3080 }
3081
3082 void RTLIL::SigSpec::replace(int offset, const RTLIL::SigSpec &with)
3083 {
3084 cover("kernel.rtlil.sigspec.replace_pos");
3085
3086 unpack();
3087 with.unpack();
3088
3089 log_assert(offset >= 0);
3090 log_assert(with.width_ >= 0);
3091 log_assert(offset+with.width_ <= width_);
3092
3093 for (int i = 0; i < with.width_; i++)
3094 bits_.at(offset + i) = with.bits_.at(i);
3095
3096 check();
3097 }
3098
3099 void RTLIL::SigSpec::remove_const()
3100 {
3101 if (packed())
3102 {
3103 cover("kernel.rtlil.sigspec.remove_const.packed");
3104
3105 std::vector<RTLIL::SigChunk> new_chunks;
3106 new_chunks.reserve(GetSize(chunks_));
3107
3108 width_ = 0;
3109 for (auto &chunk : chunks_)
3110 if (chunk.wire != NULL) {
3111 new_chunks.push_back(chunk);
3112 width_ += chunk.width;
3113 }
3114
3115 chunks_.swap(new_chunks);
3116 }
3117 else
3118 {
3119 cover("kernel.rtlil.sigspec.remove_const.unpacked");
3120
3121 std::vector<RTLIL::SigBit> new_bits;
3122 new_bits.reserve(width_);
3123
3124 for (auto &bit : bits_)
3125 if (bit.wire != NULL)
3126 new_bits.push_back(bit);
3127
3128 bits_.swap(new_bits);
3129 width_ = bits_.size();
3130 }
3131
3132 check();
3133 }
3134
3135 void RTLIL::SigSpec::remove(int offset, int length)
3136 {
3137 cover("kernel.rtlil.sigspec.remove_pos");
3138
3139 unpack();
3140
3141 log_assert(offset >= 0);
3142 log_assert(length >= 0);
3143 log_assert(offset + length <= width_);
3144
3145 bits_.erase(bits_.begin() + offset, bits_.begin() + offset + length);
3146 width_ = bits_.size();
3147
3148 check();
3149 }
3150
3151 RTLIL::SigSpec RTLIL::SigSpec::extract(int offset, int length) const
3152 {
3153 unpack();
3154 cover("kernel.rtlil.sigspec.extract_pos");
3155 return std::vector<RTLIL::SigBit>(bits_.begin() + offset, bits_.begin() + offset + length);
3156 }
3157
3158 void RTLIL::SigSpec::append(const RTLIL::SigSpec &signal)
3159 {
3160 if (signal.width_ == 0)
3161 return;
3162
3163 if (width_ == 0) {
3164 *this = signal;
3165 return;
3166 }
3167
3168 cover("kernel.rtlil.sigspec.append");
3169
3170 if (packed() != signal.packed()) {
3171 pack();
3172 signal.pack();
3173 }
3174
3175 if (packed())
3176 for (auto &other_c : signal.chunks_)
3177 {
3178 auto &my_last_c = chunks_.back();
3179 if (my_last_c.wire == NULL && other_c.wire == NULL) {
3180 auto &this_data = my_last_c.data;
3181 auto &other_data = other_c.data;
3182 this_data.insert(this_data.end(), other_data.begin(), other_data.end());
3183 my_last_c.width += other_c.width;
3184 } else
3185 if (my_last_c.wire == other_c.wire && my_last_c.offset + my_last_c.width == other_c.offset) {
3186 my_last_c.width += other_c.width;
3187 } else
3188 chunks_.push_back(other_c);
3189 }
3190 else
3191 bits_.insert(bits_.end(), signal.bits_.begin(), signal.bits_.end());
3192
3193 width_ += signal.width_;
3194 check();
3195 }
3196
3197 void RTLIL::SigSpec::append_bit(const RTLIL::SigBit &bit)
3198 {
3199 if (packed())
3200 {
3201 cover("kernel.rtlil.sigspec.append_bit.packed");
3202
3203 if (chunks_.size() == 0)
3204 chunks_.push_back(bit);
3205 else
3206 if (bit.wire == NULL)
3207 if (chunks_.back().wire == NULL) {
3208 chunks_.back().data.push_back(bit.data);
3209 chunks_.back().width++;
3210 } else
3211 chunks_.push_back(bit);
3212 else
3213 if (chunks_.back().wire == bit.wire && chunks_.back().offset + chunks_.back().width == bit.offset)
3214 chunks_.back().width++;
3215 else
3216 chunks_.push_back(bit);
3217 }
3218 else
3219 {
3220 cover("kernel.rtlil.sigspec.append_bit.unpacked");
3221 bits_.push_back(bit);
3222 }
3223
3224 width_++;
3225 check();
3226 }
3227
3228 void RTLIL::SigSpec::extend_u0(int width, bool is_signed)
3229 {
3230 cover("kernel.rtlil.sigspec.extend_u0");
3231
3232 pack();
3233
3234 if (width_ > width)
3235 remove(width, width_ - width);
3236
3237 if (width_ < width) {
3238 RTLIL::SigBit padding = width_ > 0 ? (*this)[width_ - 1] : RTLIL::State::S0;
3239 if (!is_signed)
3240 padding = RTLIL::State::S0;
3241 while (width_ < width)
3242 append(padding);
3243 }
3244
3245 }
3246
3247 RTLIL::SigSpec RTLIL::SigSpec::repeat(int num) const
3248 {
3249 cover("kernel.rtlil.sigspec.repeat");
3250
3251 RTLIL::SigSpec sig;
3252 for (int i = 0; i < num; i++)
3253 sig.append(*this);
3254 return sig;
3255 }
3256
3257 #ifndef NDEBUG
3258 void RTLIL::SigSpec::check() const
3259 {
3260 if (width_ > 64)
3261 {
3262 cover("kernel.rtlil.sigspec.check.skip");
3263 }
3264 else if (packed())
3265 {
3266 cover("kernel.rtlil.sigspec.check.packed");
3267
3268 int w = 0;
3269 for (size_t i = 0; i < chunks_.size(); i++) {
3270 const RTLIL::SigChunk chunk = chunks_[i];
3271 if (chunk.wire == NULL) {
3272 if (i > 0)
3273 log_assert(chunks_[i-1].wire != NULL);
3274 log_assert(chunk.offset == 0);
3275 log_assert(chunk.data.size() == (size_t)chunk.width);
3276 } else {
3277 if (i > 0 && chunks_[i-1].wire == chunk.wire)
3278 log_assert(chunk.offset != chunks_[i-1].offset + chunks_[i-1].width);
3279 log_assert(chunk.offset >= 0);
3280 log_assert(chunk.width >= 0);
3281 log_assert(chunk.offset + chunk.width <= chunk.wire->width);
3282 log_assert(chunk.data.size() == 0);
3283 }
3284 w += chunk.width;
3285 }
3286 log_assert(w == width_);
3287 log_assert(bits_.empty());
3288 }
3289 else
3290 {
3291 cover("kernel.rtlil.sigspec.check.unpacked");
3292
3293 log_assert(width_ == GetSize(bits_));
3294 log_assert(chunks_.empty());
3295 }
3296 }
3297 #endif
3298
3299 bool RTLIL::SigSpec::operator <(const RTLIL::SigSpec &other) const
3300 {
3301 cover("kernel.rtlil.sigspec.comp_lt");
3302
3303 if (this == &other)
3304 return false;
3305
3306 if (width_ != other.width_)
3307 return width_ < other.width_;
3308
3309 pack();
3310 other.pack();
3311
3312 if (chunks_.size() != other.chunks_.size())
3313 return chunks_.size() < other.chunks_.size();
3314
3315 updhash();
3316 other.updhash();
3317
3318 if (hash_ != other.hash_)
3319 return hash_ < other.hash_;
3320
3321 for (size_t i = 0; i < chunks_.size(); i++)
3322 if (chunks_[i] != other.chunks_[i]) {
3323 cover("kernel.rtlil.sigspec.comp_lt.hash_collision");
3324 return chunks_[i] < other.chunks_[i];
3325 }
3326
3327 cover("kernel.rtlil.sigspec.comp_lt.equal");
3328 return false;
3329 }
3330
3331 bool RTLIL::SigSpec::operator ==(const RTLIL::SigSpec &other) const
3332 {
3333 cover("kernel.rtlil.sigspec.comp_eq");
3334
3335 if (this == &other)
3336 return true;
3337
3338 if (width_ != other.width_)
3339 return false;
3340
3341 pack();
3342 other.pack();
3343
3344 if (chunks_.size() != chunks_.size())
3345 return false;
3346
3347 updhash();
3348 other.updhash();
3349
3350 if (hash_ != other.hash_)
3351 return false;
3352
3353 for (size_t i = 0; i < chunks_.size(); i++)
3354 if (chunks_[i] != other.chunks_[i]) {
3355 cover("kernel.rtlil.sigspec.comp_eq.hash_collision");
3356 return false;
3357 }
3358
3359 cover("kernel.rtlil.sigspec.comp_eq.equal");
3360 return true;
3361 }
3362
3363 bool RTLIL::SigSpec::is_wire() const
3364 {
3365 cover("kernel.rtlil.sigspec.is_wire");
3366
3367 pack();
3368 return GetSize(chunks_) == 1 && chunks_[0].wire && chunks_[0].wire->width == width_;
3369 }
3370
3371 bool RTLIL::SigSpec::is_chunk() const
3372 {
3373 cover("kernel.rtlil.sigspec.is_chunk");
3374
3375 pack();
3376 return GetSize(chunks_) == 1;
3377 }
3378
3379 bool RTLIL::SigSpec::is_fully_const() const
3380 {
3381 cover("kernel.rtlil.sigspec.is_fully_const");
3382
3383 pack();
3384 for (auto it = chunks_.begin(); it != chunks_.end(); it++)
3385 if (it->width > 0 && it->wire != NULL)
3386 return false;
3387 return true;
3388 }
3389
3390 bool RTLIL::SigSpec::is_fully_zero() const
3391 {
3392 cover("kernel.rtlil.sigspec.is_fully_zero");
3393
3394 pack();
3395 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
3396 if (it->width > 0 && it->wire != NULL)
3397 return false;
3398 for (size_t i = 0; i < it->data.size(); i++)
3399 if (it->data[i] != RTLIL::State::S0)
3400 return false;
3401 }
3402 return true;
3403 }
3404
3405 bool RTLIL::SigSpec::is_fully_ones() const
3406 {
3407 cover("kernel.rtlil.sigspec.is_fully_ones");
3408
3409 pack();
3410 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
3411 if (it->width > 0 && it->wire != NULL)
3412 return false;
3413 for (size_t i = 0; i < it->data.size(); i++)
3414 if (it->data[i] != RTLIL::State::S1)
3415 return false;
3416 }
3417 return true;
3418 }
3419
3420 bool RTLIL::SigSpec::is_fully_def() const
3421 {
3422 cover("kernel.rtlil.sigspec.is_fully_def");
3423
3424 pack();
3425 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
3426 if (it->width > 0 && it->wire != NULL)
3427 return false;
3428 for (size_t i = 0; i < it->data.size(); i++)
3429 if (it->data[i] != RTLIL::State::S0 && it->data[i] != RTLIL::State::S1)
3430 return false;
3431 }
3432 return true;
3433 }
3434
3435 bool RTLIL::SigSpec::is_fully_undef() const
3436 {
3437 cover("kernel.rtlil.sigspec.is_fully_undef");
3438
3439 pack();
3440 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
3441 if (it->width > 0 && it->wire != NULL)
3442 return false;
3443 for (size_t i = 0; i < it->data.size(); i++)
3444 if (it->data[i] != RTLIL::State::Sx && it->data[i] != RTLIL::State::Sz)
3445 return false;
3446 }
3447 return true;
3448 }
3449
3450 bool RTLIL::SigSpec::has_const() const
3451 {
3452 cover("kernel.rtlil.sigspec.has_const");
3453
3454 pack();
3455 for (auto it = chunks_.begin(); it != chunks_.end(); it++)
3456 if (it->width > 0 && it->wire == NULL)
3457 return true;
3458 return false;
3459 }
3460
3461 bool RTLIL::SigSpec::has_marked_bits() const
3462 {
3463 cover("kernel.rtlil.sigspec.has_marked_bits");
3464
3465 pack();
3466 for (auto it = chunks_.begin(); it != chunks_.end(); it++)
3467 if (it->width > 0 && it->wire == NULL) {
3468 for (size_t i = 0; i < it->data.size(); i++)
3469 if (it->data[i] == RTLIL::State::Sm)
3470 return true;
3471 }
3472 return false;
3473 }
3474
3475 bool RTLIL::SigSpec::as_bool() const
3476 {
3477 cover("kernel.rtlil.sigspec.as_bool");
3478
3479 pack();
3480 log_assert(is_fully_const() && GetSize(chunks_) <= 1);
3481 if (width_)
3482 return RTLIL::Const(chunks_[0].data).as_bool();
3483 return false;
3484 }
3485
3486 int RTLIL::SigSpec::as_int(bool is_signed) const
3487 {
3488 cover("kernel.rtlil.sigspec.as_int");
3489
3490 pack();
3491 log_assert(is_fully_const() && GetSize(chunks_) <= 1);
3492 if (width_)
3493 return RTLIL::Const(chunks_[0].data).as_int(is_signed);
3494 return 0;
3495 }
3496
3497 std::string RTLIL::SigSpec::as_string() const
3498 {
3499 cover("kernel.rtlil.sigspec.as_string");
3500
3501 pack();
3502 std::string str;
3503 for (size_t i = chunks_.size(); i > 0; i--) {
3504 const RTLIL::SigChunk &chunk = chunks_[i-1];
3505 if (chunk.wire != NULL)
3506 for (int j = 0; j < chunk.width; j++)
3507 str += "?";
3508 else
3509 str += RTLIL::Const(chunk.data).as_string();
3510 }
3511 return str;
3512 }
3513
3514 RTLIL::Const RTLIL::SigSpec::as_const() const
3515 {
3516 cover("kernel.rtlil.sigspec.as_const");
3517
3518 pack();
3519 log_assert(is_fully_const() && GetSize(chunks_) <= 1);
3520 if (width_)
3521 return chunks_[0].data;
3522 return RTLIL::Const();
3523 }
3524
3525 RTLIL::Wire *RTLIL::SigSpec::as_wire() const
3526 {
3527 cover("kernel.rtlil.sigspec.as_wire");
3528
3529 pack();
3530 log_assert(is_wire());
3531 return chunks_[0].wire;
3532 }
3533
3534 RTLIL::SigChunk RTLIL::SigSpec::as_chunk() const
3535 {
3536 cover("kernel.rtlil.sigspec.as_chunk");
3537
3538 pack();
3539 log_assert(is_chunk());
3540 return chunks_[0];
3541 }
3542
3543 RTLIL::SigBit RTLIL::SigSpec::as_bit() const
3544 {
3545 cover("kernel.rtlil.sigspec.as_bit");
3546
3547 log_assert(width_ == 1);
3548 if (packed())
3549 return RTLIL::SigBit(*chunks_.begin());
3550 else
3551 return bits_[0];
3552 }
3553
3554 bool RTLIL::SigSpec::match(std::string pattern) const
3555 {
3556 cover("kernel.rtlil.sigspec.match");
3557
3558 pack();
3559 std::string str = as_string();
3560 log_assert(pattern.size() == str.size());
3561
3562 for (size_t i = 0; i < pattern.size(); i++) {
3563 if (pattern[i] == ' ')
3564 continue;
3565 if (pattern[i] == '*') {
3566 if (str[i] != 'z' && str[i] != 'x')
3567 return false;
3568 continue;
3569 }
3570 if (pattern[i] != str[i])
3571 return false;
3572 }
3573
3574 return true;
3575 }
3576
3577 std::set<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_set() const
3578 {
3579 cover("kernel.rtlil.sigspec.to_sigbit_set");
3580
3581 pack();
3582 std::set<RTLIL::SigBit> sigbits;
3583 for (auto &c : chunks_)
3584 for (int i = 0; i < c.width; i++)
3585 sigbits.insert(RTLIL::SigBit(c, i));
3586 return sigbits;
3587 }
3588
3589 pool<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_pool() const
3590 {
3591 cover("kernel.rtlil.sigspec.to_sigbit_pool");
3592
3593 pack();
3594 pool<RTLIL::SigBit> sigbits;
3595 for (auto &c : chunks_)
3596 for (int i = 0; i < c.width; i++)
3597 sigbits.insert(RTLIL::SigBit(c, i));
3598 return sigbits;
3599 }
3600
3601 std::vector<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_vector() const
3602 {
3603 cover("kernel.rtlil.sigspec.to_sigbit_vector");
3604
3605 unpack();
3606 return bits_;
3607 }
3608
3609 std::map<RTLIL::SigBit, RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_map(const RTLIL::SigSpec &other) const
3610 {
3611 cover("kernel.rtlil.sigspec.to_sigbit_map");
3612
3613 unpack();
3614 other.unpack();
3615
3616 log_assert(width_ == other.width_);
3617
3618 std::map<RTLIL::SigBit, RTLIL::SigBit> new_map;
3619 for (int i = 0; i < width_; i++)
3620 new_map[bits_[i]] = other.bits_[i];
3621
3622 return new_map;
3623 }
3624
3625 dict<RTLIL::SigBit, RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_dict(const RTLIL::SigSpec &other) const
3626 {
3627 cover("kernel.rtlil.sigspec.to_sigbit_dict");
3628
3629 unpack();
3630 other.unpack();
3631
3632 log_assert(width_ == other.width_);
3633
3634 dict<RTLIL::SigBit, RTLIL::SigBit> new_map;
3635 for (int i = 0; i < width_; i++)
3636 new_map[bits_[i]] = other.bits_[i];
3637
3638 return new_map;
3639 }
3640
3641 static void sigspec_parse_split(std::vector<std::string> &tokens, const std::string &text, char sep)
3642 {
3643 size_t start = 0, end = 0;
3644 while ((end = text.find(sep, start)) != std::string::npos) {
3645 tokens.push_back(text.substr(start, end - start));
3646 start = end + 1;
3647 }
3648 tokens.push_back(text.substr(start));
3649 }
3650
3651 static int sigspec_parse_get_dummy_line_num()
3652 {
3653 return 0;
3654 }
3655
3656 bool RTLIL::SigSpec::parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str)
3657 {
3658 cover("kernel.rtlil.sigspec.parse");
3659
3660 AST::current_filename = "input";
3661 AST::use_internal_line_num();
3662 AST::set_line_num(0);
3663
3664 std::vector<std::string> tokens;
3665 sigspec_parse_split(tokens, str, ',');
3666
3667 sig = RTLIL::SigSpec();
3668 for (int tokidx = int(tokens.size())-1; tokidx >= 0; tokidx--)
3669 {
3670 std::string netname = tokens[tokidx];
3671 std::string indices;
3672
3673 if (netname.size() == 0)
3674 continue;
3675
3676 if (('0' <= netname[0] && netname[0] <= '9') || netname[0] == '\'') {
3677 cover("kernel.rtlil.sigspec.parse.const");
3678 AST::get_line_num = sigspec_parse_get_dummy_line_num;
3679 AST::AstNode *ast = VERILOG_FRONTEND::const2ast(netname);
3680 if (ast == NULL)
3681 return false;
3682 sig.append(RTLIL::Const(ast->bits));
3683 delete ast;
3684 continue;
3685 }
3686
3687 if (module == NULL)
3688 return false;
3689
3690 cover("kernel.rtlil.sigspec.parse.net");
3691
3692 if (netname[0] != '$' && netname[0] != '\\')
3693 netname = "\\" + netname;
3694
3695 if (module->wires_.count(netname) == 0) {
3696 size_t indices_pos = netname.size()-1;
3697 if (indices_pos > 2 && netname[indices_pos] == ']')
3698 {
3699 indices_pos--;
3700 while (indices_pos > 0 && ('0' <= netname[indices_pos] && netname[indices_pos] <= '9')) indices_pos--;
3701 if (indices_pos > 0 && netname[indices_pos] == ':') {
3702 indices_pos--;
3703 while (indices_pos > 0 && ('0' <= netname[indices_pos] && netname[indices_pos] <= '9')) indices_pos--;
3704 }
3705 if (indices_pos > 0 && netname[indices_pos] == '[') {
3706 indices = netname.substr(indices_pos);
3707 netname = netname.substr(0, indices_pos);
3708 }
3709 }
3710 }
3711
3712 if (module->wires_.count(netname) == 0)
3713 return false;
3714
3715 RTLIL::Wire *wire = module->wires_.at(netname);
3716 if (!indices.empty()) {
3717 std::vector<std::string> index_tokens;
3718 sigspec_parse_split(index_tokens, indices.substr(1, indices.size()-2), ':');
3719 if (index_tokens.size() == 1) {
3720 cover("kernel.rtlil.sigspec.parse.bit_sel");
3721 int a = atoi(index_tokens.at(0).c_str());
3722 if (a < 0 || a >= wire->width)
3723 return false;
3724 sig.append(RTLIL::SigSpec(wire, a));
3725 } else {
3726 cover("kernel.rtlil.sigspec.parse.part_sel");
3727 int a = atoi(index_tokens.at(0).c_str());
3728 int b = atoi(index_tokens.at(1).c_str());
3729 if (a > b) {
3730 int tmp = a;
3731 a = b, b = tmp;
3732 }
3733 if (a < 0 || a >= wire->width)
3734 return false;
3735 if (b < 0 || b >= wire->width)
3736 return false;
3737 sig.append(RTLIL::SigSpec(wire, a, b-a+1));
3738 }
3739 } else
3740 sig.append(wire);
3741 }
3742
3743 return true;
3744 }
3745
3746 bool RTLIL::SigSpec::parse_sel(RTLIL::SigSpec &sig, RTLIL::Design *design, RTLIL::Module *module, std::string str)
3747 {
3748 if (str.empty() || str[0] != '@')
3749 return parse(sig, module, str);
3750
3751 cover("kernel.rtlil.sigspec.parse.sel");
3752
3753 str = RTLIL::escape_id(str.substr(1));
3754 if (design->selection_vars.count(str) == 0)
3755 return false;
3756
3757 sig = RTLIL::SigSpec();
3758 RTLIL::Selection &sel = design->selection_vars.at(str);
3759 for (auto &it : module->wires_)
3760 if (sel.selected_member(module->name, it.first))
3761 sig.append(it.second);
3762
3763 return true;
3764 }
3765
3766 bool RTLIL::SigSpec::parse_rhs(const RTLIL::SigSpec &lhs, RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str)
3767 {
3768 if (str == "0") {
3769 cover("kernel.rtlil.sigspec.parse.rhs_zeros");
3770 sig = RTLIL::SigSpec(RTLIL::State::S0, lhs.width_);
3771 return true;
3772 }
3773
3774 if (str == "~0") {
3775 cover("kernel.rtlil.sigspec.parse.rhs_ones");
3776 sig = RTLIL::SigSpec(RTLIL::State::S1, lhs.width_);
3777 return true;
3778 }
3779
3780 if (lhs.chunks_.size() == 1) {
3781 char *p = (char*)str.c_str(), *endptr;
3782 long int val = strtol(p, &endptr, 10);
3783 if (endptr && endptr != p && *endptr == 0) {
3784 sig = RTLIL::SigSpec(val, lhs.width_);
3785 cover("kernel.rtlil.sigspec.parse.rhs_dec");
3786 return true;
3787 }
3788 }
3789
3790 return parse(sig, module, str);
3791 }
3792
3793 RTLIL::CaseRule::~CaseRule()
3794 {
3795 for (auto it = switches.begin(); it != switches.end(); it++)
3796 delete *it;
3797 }
3798
3799 bool RTLIL::CaseRule::empty() const
3800 {
3801 return actions.empty() && switches.empty();
3802 }
3803
3804 RTLIL::CaseRule *RTLIL::CaseRule::clone() const
3805 {
3806 RTLIL::CaseRule *new_caserule = new RTLIL::CaseRule;
3807 new_caserule->compare = compare;
3808 new_caserule->actions = actions;
3809 for (auto &it : switches)
3810 new_caserule->switches.push_back(it->clone());
3811 return new_caserule;
3812 }
3813
3814 RTLIL::SwitchRule::~SwitchRule()
3815 {
3816 for (auto it = cases.begin(); it != cases.end(); it++)
3817 delete *it;
3818 }
3819
3820 bool RTLIL::SwitchRule::empty() const
3821 {
3822 return cases.empty();
3823 }
3824
3825 RTLIL::SwitchRule *RTLIL::SwitchRule::clone() const
3826 {
3827 RTLIL::SwitchRule *new_switchrule = new RTLIL::SwitchRule;
3828 new_switchrule->signal = signal;
3829 new_switchrule->attributes = attributes;
3830 for (auto &it : cases)
3831 new_switchrule->cases.push_back(it->clone());
3832 return new_switchrule;
3833
3834 }
3835
3836 RTLIL::SyncRule *RTLIL::SyncRule::clone() const
3837 {
3838 RTLIL::SyncRule *new_syncrule = new RTLIL::SyncRule;
3839 new_syncrule->type = type;
3840 new_syncrule->signal = signal;
3841 new_syncrule->actions = actions;
3842 return new_syncrule;
3843 }
3844
3845 RTLIL::Process::~Process()
3846 {
3847 for (auto it = syncs.begin(); it != syncs.end(); it++)
3848 delete *it;
3849 }
3850
3851 RTLIL::Process *RTLIL::Process::clone() const
3852 {
3853 RTLIL::Process *new_proc = new RTLIL::Process;
3854
3855 new_proc->name = name;
3856 new_proc->attributes = attributes;
3857
3858 RTLIL::CaseRule *rc_ptr = root_case.clone();
3859 new_proc->root_case = *rc_ptr;
3860 rc_ptr->switches.clear();
3861 delete rc_ptr;
3862
3863 for (auto &it : syncs)
3864 new_proc->syncs.push_back(it->clone());
3865
3866 return new_proc;
3867 }
3868
3869 YOSYS_NAMESPACE_END
3870