2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include "kernel/yosys.h"
21 #include "kernel/macc.h"
22 #include "kernel/celltypes.h"
23 #include "frontends/verilog/verilog_frontend.h"
24 #include "backends/ilang/ilang_backend.h"
31 RTLIL::IdString::destruct_guard_t
RTLIL::IdString::destruct_guard
;
32 std::vector
<int> RTLIL::IdString::global_refcount_storage_
;
33 std::vector
<char*> RTLIL::IdString::global_id_storage_
;
34 dict
<char*, int, hash_cstr_ops
> RTLIL::IdString::global_id_index_
;
35 std::vector
<int> RTLIL::IdString::global_free_idx_list_
;
36 int RTLIL::IdString::last_created_idx_
[8];
37 int RTLIL::IdString::last_created_idx_ptr_
;
41 flags
= RTLIL::CONST_FLAG_NONE
;
44 RTLIL::Const::Const(std::string str
)
46 flags
= RTLIL::CONST_FLAG_STRING
;
47 for (int i
= str
.size()-1; i
>= 0; i
--) {
48 unsigned char ch
= str
[i
];
49 for (int j
= 0; j
< 8; j
++) {
50 bits
.push_back((ch
& 1) != 0 ? RTLIL::S1
: RTLIL::S0
);
56 RTLIL::Const::Const(int val
, int width
)
58 flags
= RTLIL::CONST_FLAG_NONE
;
59 for (int i
= 0; i
< width
; i
++) {
60 bits
.push_back((val
& 1) != 0 ? RTLIL::S1
: RTLIL::S0
);
65 RTLIL::Const::Const(RTLIL::State bit
, int width
)
67 flags
= RTLIL::CONST_FLAG_NONE
;
68 for (int i
= 0; i
< width
; i
++)
72 RTLIL::Const::Const(const std::vector
<bool> &bits
)
74 flags
= RTLIL::CONST_FLAG_NONE
;
76 this->bits
.push_back(b
? RTLIL::S1
: RTLIL::S0
);
79 bool RTLIL::Const::operator <(const RTLIL::Const
&other
) const
81 if (bits
.size() != other
.bits
.size())
82 return bits
.size() < other
.bits
.size();
83 for (size_t i
= 0; i
< bits
.size(); i
++)
84 if (bits
[i
] != other
.bits
[i
])
85 return bits
[i
] < other
.bits
[i
];
89 bool RTLIL::Const::operator ==(const RTLIL::Const
&other
) const
91 return bits
== other
.bits
;
94 bool RTLIL::Const::operator !=(const RTLIL::Const
&other
) const
96 return bits
!= other
.bits
;
99 bool RTLIL::Const::as_bool() const
101 for (size_t i
= 0; i
< bits
.size(); i
++)
102 if (bits
[i
] == RTLIL::S1
)
107 int RTLIL::Const::as_int(bool is_signed
) const
110 for (size_t i
= 0; i
< bits
.size() && i
< 32; i
++)
111 if (bits
[i
] == RTLIL::S1
)
113 if (is_signed
&& bits
.back() == RTLIL::S1
)
114 for (size_t i
= bits
.size(); i
< 32; i
++)
119 std::string
RTLIL::Const::as_string() const
122 for (size_t i
= bits
.size(); i
> 0; i
--)
124 case S0
: ret
+= "0"; break;
125 case S1
: ret
+= "1"; break;
126 case Sx
: ret
+= "x"; break;
127 case Sz
: ret
+= "z"; break;
128 case Sa
: ret
+= "-"; break;
129 case Sm
: ret
+= "m"; break;
134 RTLIL::Const
RTLIL::Const::from_string(std::string str
)
137 for (auto it
= str
.rbegin(); it
!= str
.rend(); it
++)
139 case '0': c
.bits
.push_back(State::S0
); break;
140 case '1': c
.bits
.push_back(State::S1
); break;
141 case 'x': c
.bits
.push_back(State::Sx
); break;
142 case 'z': c
.bits
.push_back(State::Sz
); break;
143 case 'm': c
.bits
.push_back(State::Sm
); break;
144 default: c
.bits
.push_back(State::Sa
);
149 std::string
RTLIL::Const::decode_string() const
152 std::vector
<char> string_chars
;
153 for (int i
= 0; i
< int (bits
.size()); i
+= 8) {
155 for (int j
= 0; j
< 8 && i
+ j
< int (bits
.size()); j
++)
156 if (bits
[i
+ j
] == RTLIL::State::S1
)
159 string_chars
.push_back(ch
);
161 for (int i
= int (string_chars
.size()) - 1; i
>= 0; i
--)
162 string
+= string_chars
[i
];
166 bool RTLIL::Const::is_fully_zero() const
168 cover("kernel.rtlil.const.is_fully_zero");
170 for (auto bit
: bits
)
171 if (bit
!= RTLIL::State::S0
)
177 bool RTLIL::Const::is_fully_ones() const
179 cover("kernel.rtlil.const.is_fully_ones");
181 for (auto bit
: bits
)
182 if (bit
!= RTLIL::State::S1
)
188 bool RTLIL::Const::is_fully_def() const
190 cover("kernel.rtlil.const.is_fully_def");
192 for (auto bit
: bits
)
193 if (bit
!= RTLIL::State::S0
&& bit
!= RTLIL::State::S1
)
199 bool RTLIL::Const::is_fully_undef() const
201 cover("kernel.rtlil.const.is_fully_undef");
203 for (auto bit
: bits
)
204 if (bit
!= RTLIL::State::Sx
&& bit
!= RTLIL::State::Sz
)
210 void RTLIL::AttrObject::set_bool_attribute(RTLIL::IdString id
)
212 attributes
[id
] = RTLIL::Const(1);
215 bool RTLIL::AttrObject::get_bool_attribute(RTLIL::IdString id
) const
217 if (attributes
.count(id
) == 0)
219 return attributes
.at(id
).as_bool();
222 void RTLIL::AttrObject::set_strpool_attribute(RTLIL::IdString id
, const pool
<string
> &data
)
225 for (auto &s
: data
) {
226 if (!attrval
.empty())
230 attributes
[id
] = RTLIL::Const(attrval
);
233 void RTLIL::AttrObject::add_strpool_attribute(RTLIL::IdString id
, const pool
<string
> &data
)
235 pool
<string
> union_data
= get_strpool_attribute(id
);
236 union_data
.insert(data
.begin(), data
.end());
237 if (!union_data
.empty())
238 set_strpool_attribute(id
, union_data
);
241 pool
<string
> RTLIL::AttrObject::get_strpool_attribute(RTLIL::IdString id
) const
244 if (attributes
.count(id
) != 0)
245 for (auto s
: split_tokens(attributes
.at(id
).decode_string(), "|"))
250 void RTLIL::AttrObject::set_src_attribute(const std::string
&src
)
253 attributes
.erase("\\src");
255 attributes
["\\src"] = src
;
258 std::string
RTLIL::AttrObject::get_src_attribute() const
261 if (attributes
.count("\\src"))
262 src
= attributes
.at("\\src").decode_string();
266 bool RTLIL::Selection::selected_module(RTLIL::IdString mod_name
) const
270 if (selected_modules
.count(mod_name
) > 0)
272 if (selected_members
.count(mod_name
) > 0)
277 bool RTLIL::Selection::selected_whole_module(RTLIL::IdString mod_name
) const
281 if (selected_modules
.count(mod_name
) > 0)
286 bool RTLIL::Selection::selected_member(RTLIL::IdString mod_name
, RTLIL::IdString memb_name
) const
290 if (selected_modules
.count(mod_name
) > 0)
292 if (selected_members
.count(mod_name
) > 0)
293 if (selected_members
.at(mod_name
).count(memb_name
) > 0)
298 void RTLIL::Selection::optimize(RTLIL::Design
*design
)
300 if (full_selection
) {
301 selected_modules
.clear();
302 selected_members
.clear();
306 std::vector
<RTLIL::IdString
> del_list
, add_list
;
309 for (auto mod_name
: selected_modules
) {
310 if (design
->modules_
.count(mod_name
) == 0)
311 del_list
.push_back(mod_name
);
312 selected_members
.erase(mod_name
);
314 for (auto mod_name
: del_list
)
315 selected_modules
.erase(mod_name
);
318 for (auto &it
: selected_members
)
319 if (design
->modules_
.count(it
.first
) == 0)
320 del_list
.push_back(it
.first
);
321 for (auto mod_name
: del_list
)
322 selected_members
.erase(mod_name
);
324 for (auto &it
: selected_members
) {
326 for (auto memb_name
: it
.second
)
327 if (design
->modules_
[it
.first
]->count_id(memb_name
) == 0)
328 del_list
.push_back(memb_name
);
329 for (auto memb_name
: del_list
)
330 it
.second
.erase(memb_name
);
335 for (auto &it
: selected_members
)
336 if (it
.second
.size() == 0)
337 del_list
.push_back(it
.first
);
338 else if (it
.second
.size() == design
->modules_
[it
.first
]->wires_
.size() + design
->modules_
[it
.first
]->memories
.size() +
339 design
->modules_
[it
.first
]->cells_
.size() + design
->modules_
[it
.first
]->processes
.size())
340 add_list
.push_back(it
.first
);
341 for (auto mod_name
: del_list
)
342 selected_members
.erase(mod_name
);
343 for (auto mod_name
: add_list
) {
344 selected_members
.erase(mod_name
);
345 selected_modules
.insert(mod_name
);
348 if (selected_modules
.size() == design
->modules_
.size()) {
349 full_selection
= true;
350 selected_modules
.clear();
351 selected_members
.clear();
355 RTLIL::Design::Design()
357 static unsigned int hashidx_count
= 123456789;
358 hashidx_count
= mkhash_xorshift(hashidx_count
);
359 hashidx_
= hashidx_count
;
361 refcount_modules_
= 0;
362 selection_stack
.push_back(RTLIL::Selection());
365 RTLIL::Design::~Design()
367 for (auto it
= modules_
.begin(); it
!= modules_
.end(); ++it
)
369 for (auto n
: verilog_packages
)
371 for (auto n
: verilog_globals
)
375 RTLIL::ObjRange
<RTLIL::Module
*> RTLIL::Design::modules()
377 return RTLIL::ObjRange
<RTLIL::Module
*>(&modules_
, &refcount_modules_
);
380 RTLIL::Module
*RTLIL::Design::module(RTLIL::IdString name
)
382 return modules_
.count(name
) ? modules_
.at(name
) : NULL
;
385 RTLIL::Module
*RTLIL::Design::top_module()
387 RTLIL::Module
*module
= nullptr;
388 int module_count
= 0;
390 for (auto mod
: selected_modules()) {
391 if (mod
->get_bool_attribute("\\top"))
397 return module_count
== 1 ? module
: nullptr;
400 void RTLIL::Design::add(RTLIL::Module
*module
)
402 log_assert(modules_
.count(module
->name
) == 0);
403 log_assert(refcount_modules_
== 0);
404 modules_
[module
->name
] = module
;
405 module
->design
= this;
407 for (auto mon
: monitors
)
408 mon
->notify_module_add(module
);
411 log("#X# New Module: %s\n", log_id(module
));
412 log_backtrace("-X- ", yosys_xtrace
-1);
416 RTLIL::Module
*RTLIL::Design::addModule(RTLIL::IdString name
)
418 log_assert(modules_
.count(name
) == 0);
419 log_assert(refcount_modules_
== 0);
421 RTLIL::Module
*module
= new RTLIL::Module
;
422 modules_
[name
] = module
;
423 module
->design
= this;
426 for (auto mon
: monitors
)
427 mon
->notify_module_add(module
);
430 log("#X# New Module: %s\n", log_id(module
));
431 log_backtrace("-X- ", yosys_xtrace
-1);
437 void RTLIL::Design::scratchpad_unset(std::string varname
)
439 scratchpad
.erase(varname
);
442 void RTLIL::Design::scratchpad_set_int(std::string varname
, int value
)
444 scratchpad
[varname
] = stringf("%d", value
);
447 void RTLIL::Design::scratchpad_set_bool(std::string varname
, bool value
)
449 scratchpad
[varname
] = value
? "true" : "false";
452 void RTLIL::Design::scratchpad_set_string(std::string varname
, std::string value
)
454 scratchpad
[varname
] = value
;
457 int RTLIL::Design::scratchpad_get_int(std::string varname
, int default_value
) const
459 if (scratchpad
.count(varname
) == 0)
460 return default_value
;
462 std::string str
= scratchpad
.at(varname
);
464 if (str
== "0" || str
== "false")
467 if (str
== "1" || str
== "true")
470 char *endptr
= nullptr;
471 long int parsed_value
= strtol(str
.c_str(), &endptr
, 10);
472 return *endptr
? default_value
: parsed_value
;
475 bool RTLIL::Design::scratchpad_get_bool(std::string varname
, bool default_value
) const
477 if (scratchpad
.count(varname
) == 0)
478 return default_value
;
480 std::string str
= scratchpad
.at(varname
);
482 if (str
== "0" || str
== "false")
485 if (str
== "1" || str
== "true")
488 return default_value
;
491 std::string
RTLIL::Design::scratchpad_get_string(std::string varname
, std::string default_value
) const
493 if (scratchpad
.count(varname
) == 0)
494 return default_value
;
495 return scratchpad
.at(varname
);
498 void RTLIL::Design::remove(RTLIL::Module
*module
)
500 for (auto mon
: monitors
)
501 mon
->notify_module_del(module
);
504 log("#X# Remove Module: %s\n", log_id(module
));
505 log_backtrace("-X- ", yosys_xtrace
-1);
508 log_assert(modules_
.at(module
->name
) == module
);
509 modules_
.erase(module
->name
);
513 void RTLIL::Design::rename(RTLIL::Module
*module
, RTLIL::IdString new_name
)
515 modules_
.erase(module
->name
);
516 module
->name
= new_name
;
520 void RTLIL::Design::sort()
523 modules_
.sort(sort_by_id_str());
524 for (auto &it
: modules_
)
528 void RTLIL::Design::check()
531 for (auto &it
: modules_
) {
532 log_assert(this == it
.second
->design
);
533 log_assert(it
.first
== it
.second
->name
);
534 log_assert(!it
.first
.empty());
540 void RTLIL::Design::optimize()
542 for (auto &it
: modules_
)
543 it
.second
->optimize();
544 for (auto &it
: selection_stack
)
546 for (auto &it
: selection_vars
)
547 it
.second
.optimize(this);
550 bool RTLIL::Design::selected_module(RTLIL::IdString mod_name
) const
552 if (!selected_active_module
.empty() && mod_name
!= selected_active_module
)
554 if (selection_stack
.size() == 0)
556 return selection_stack
.back().selected_module(mod_name
);
559 bool RTLIL::Design::selected_whole_module(RTLIL::IdString mod_name
) const
561 if (!selected_active_module
.empty() && mod_name
!= selected_active_module
)
563 if (selection_stack
.size() == 0)
565 return selection_stack
.back().selected_whole_module(mod_name
);
568 bool RTLIL::Design::selected_member(RTLIL::IdString mod_name
, RTLIL::IdString memb_name
) const
570 if (!selected_active_module
.empty() && mod_name
!= selected_active_module
)
572 if (selection_stack
.size() == 0)
574 return selection_stack
.back().selected_member(mod_name
, memb_name
);
577 bool RTLIL::Design::selected_module(RTLIL::Module
*mod
) const
579 return selected_module(mod
->name
);
582 bool RTLIL::Design::selected_whole_module(RTLIL::Module
*mod
) const
584 return selected_whole_module(mod
->name
);
587 std::vector
<RTLIL::Module
*> RTLIL::Design::selected_modules() const
589 std::vector
<RTLIL::Module
*> result
;
590 result
.reserve(modules_
.size());
591 for (auto &it
: modules_
)
592 if (selected_module(it
.first
) && !it
.second
->get_bool_attribute("\\blackbox"))
593 result
.push_back(it
.second
);
597 std::vector
<RTLIL::Module
*> RTLIL::Design::selected_whole_modules() const
599 std::vector
<RTLIL::Module
*> result
;
600 result
.reserve(modules_
.size());
601 for (auto &it
: modules_
)
602 if (selected_whole_module(it
.first
) && !it
.second
->get_bool_attribute("\\blackbox"))
603 result
.push_back(it
.second
);
607 std::vector
<RTLIL::Module
*> RTLIL::Design::selected_whole_modules_warn() const
609 std::vector
<RTLIL::Module
*> result
;
610 result
.reserve(modules_
.size());
611 for (auto &it
: modules_
)
612 if (it
.second
->get_bool_attribute("\\blackbox"))
614 else if (selected_whole_module(it
.first
))
615 result
.push_back(it
.second
);
616 else if (selected_module(it
.first
))
617 log_warning("Ignoring partially selected module %s.\n", log_id(it
.first
));
621 RTLIL::Module::Module()
623 static unsigned int hashidx_count
= 123456789;
624 hashidx_count
= mkhash_xorshift(hashidx_count
);
625 hashidx_
= hashidx_count
;
632 RTLIL::Module::~Module()
634 for (auto it
= wires_
.begin(); it
!= wires_
.end(); ++it
)
636 for (auto it
= memories
.begin(); it
!= memories
.end(); ++it
)
638 for (auto it
= cells_
.begin(); it
!= cells_
.end(); ++it
)
640 for (auto it
= processes
.begin(); it
!= processes
.end(); ++it
)
644 void RTLIL::Module::makeblackbox()
646 pool
<RTLIL::Wire
*> delwires
;
648 for (auto it
= wires_
.begin(); it
!= wires_
.end(); ++it
)
649 if (!it
->second
->port_input
&& !it
->second
->port_output
)
650 delwires
.insert(it
->second
);
652 for (auto it
= memories
.begin(); it
!= memories
.end(); ++it
)
656 for (auto it
= cells_
.begin(); it
!= cells_
.end(); ++it
)
660 for (auto it
= processes
.begin(); it
!= processes
.end(); ++it
)
665 set_bool_attribute("\\blackbox");
668 void RTLIL::Module::reprocess_module(RTLIL::Design
*, dict
<RTLIL::IdString
, RTLIL::Module
*>)
670 log_error("Cannot reprocess_module module `%s' !\n", id2cstr(name
));
673 RTLIL::IdString
RTLIL::Module::derive(RTLIL::Design
*, dict
<RTLIL::IdString
, RTLIL::Const
>, bool mayfail
)
676 return RTLIL::IdString();
677 log_error("Module `%s' is used with parameters but is not parametric!\n", id2cstr(name
));
681 RTLIL::IdString
RTLIL::Module::derive(RTLIL::Design
*, dict
<RTLIL::IdString
, RTLIL::Const
>, dict
<RTLIL::IdString
, RTLIL::Module
*>, dict
<RTLIL::IdString
, RTLIL::IdString
>, bool mayfail
)
684 return RTLIL::IdString();
685 log_error("Module `%s' is used with parameters but is not parametric!\n", id2cstr(name
));
688 size_t RTLIL::Module::count_id(RTLIL::IdString id
)
690 return wires_
.count(id
) + memories
.count(id
) + cells_
.count(id
) + processes
.count(id
);
695 struct InternalCellChecker
697 RTLIL::Module
*module
;
699 pool
<RTLIL::IdString
> expected_params
, expected_ports
;
701 InternalCellChecker(RTLIL::Module
*module
, RTLIL::Cell
*cell
) : module(module
), cell(cell
) { }
703 void error(int linenr
)
705 std::stringstream buf
;
706 ILANG_BACKEND::dump_cell(buf
, " ", cell
);
708 log_error("Found error in internal cell %s%s%s (%s) at %s:%d:\n%s",
709 module
? module
->name
.c_str() : "", module
? "." : "",
710 cell
->name
.c_str(), cell
->type
.c_str(), __FILE__
, linenr
, buf
.str().c_str());
713 int param(const char *name
)
715 if (cell
->parameters
.count(name
) == 0)
717 expected_params
.insert(name
);
718 return cell
->parameters
.at(name
).as_int();
721 int param_bool(const char *name
)
724 if (cell
->parameters
.at(name
).bits
.size() > 32)
726 if (v
!= 0 && v
!= 1)
731 void param_bits(const char *name
, int width
)
734 if (int(cell
->parameters
.at(name
).bits
.size()) != width
)
738 void port(const char *name
, int width
)
740 if (!cell
->hasPort(name
))
742 if (cell
->getPort(name
).size() != width
)
744 expected_ports
.insert(name
);
747 void check_expected(bool check_matched_sign
= true)
749 for (auto ¶
: cell
->parameters
)
750 if (expected_params
.count(para
.first
) == 0)
752 for (auto &conn
: cell
->connections())
753 if (expected_ports
.count(conn
.first
) == 0)
756 if (expected_params
.count("\\A_SIGNED") != 0 && expected_params
.count("\\B_SIGNED") && check_matched_sign
) {
757 bool a_is_signed
= param("\\A_SIGNED") != 0;
758 bool b_is_signed
= param("\\B_SIGNED") != 0;
759 if (a_is_signed
!= b_is_signed
)
764 void check_gate(const char *ports
)
766 if (cell
->parameters
.size() != 0)
769 for (const char *p
= ports
; *p
; p
++) {
770 char portname
[3] = { '\\', *p
, 0 };
771 if (!cell
->hasPort(portname
))
773 if (cell
->getPort(portname
).size() != 1)
777 for (auto &conn
: cell
->connections()) {
778 if (conn
.first
.size() != 2 || conn
.first
[0] != '\\')
780 if (strchr(ports
, conn
.first
[1]) == NULL
)
787 if (cell
->type
.substr(0, 1) != "$" || cell
->type
.substr(0, 3) == "$__" || cell
->type
.substr(0, 8) == "$paramod" || cell
->type
.substr(0,10) == "$fmcombine" ||
788 cell
->type
.substr(0, 9) == "$verific$" || cell
->type
.substr(0, 7) == "$array:" || cell
->type
.substr(0, 8) == "$extern:")
791 if (cell
->type
.in("$not", "$pos", "$neg")) {
792 param_bool("\\A_SIGNED");
793 port("\\A", param("\\A_WIDTH"));
794 port("\\Y", param("\\Y_WIDTH"));
799 if (cell
->type
.in("$and", "$or", "$xor", "$xnor")) {
800 param_bool("\\A_SIGNED");
801 param_bool("\\B_SIGNED");
802 port("\\A", param("\\A_WIDTH"));
803 port("\\B", param("\\B_WIDTH"));
804 port("\\Y", param("\\Y_WIDTH"));
809 if (cell
->type
.in("$reduce_and", "$reduce_or", "$reduce_xor", "$reduce_xnor", "$reduce_bool")) {
810 param_bool("\\A_SIGNED");
811 port("\\A", param("\\A_WIDTH"));
812 port("\\Y", param("\\Y_WIDTH"));
817 if (cell
->type
.in("$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx")) {
818 param_bool("\\A_SIGNED");
819 param_bool("\\B_SIGNED");
820 port("\\A", param("\\A_WIDTH"));
821 port("\\B", param("\\B_WIDTH"));
822 port("\\Y", param("\\Y_WIDTH"));
823 check_expected(false);
827 if (cell
->type
.in("$lt", "$le", "$eq", "$ne", "$eqx", "$nex", "$ge", "$gt")) {
828 param_bool("\\A_SIGNED");
829 param_bool("\\B_SIGNED");
830 port("\\A", param("\\A_WIDTH"));
831 port("\\B", param("\\B_WIDTH"));
832 port("\\Y", param("\\Y_WIDTH"));
837 if (cell
->type
.in("$add", "$sub", "$mul", "$div", "$mod", "$pow")) {
838 param_bool("\\A_SIGNED");
839 param_bool("\\B_SIGNED");
840 port("\\A", param("\\A_WIDTH"));
841 port("\\B", param("\\B_WIDTH"));
842 port("\\Y", param("\\Y_WIDTH"));
843 check_expected(cell
->type
!= "$pow");
847 if (cell
->type
== "$fa") {
848 port("\\A", param("\\WIDTH"));
849 port("\\B", param("\\WIDTH"));
850 port("\\C", param("\\WIDTH"));
851 port("\\X", param("\\WIDTH"));
852 port("\\Y", param("\\WIDTH"));
857 if (cell
->type
== "$lcu") {
858 port("\\P", param("\\WIDTH"));
859 port("\\G", param("\\WIDTH"));
861 port("\\CO", param("\\WIDTH"));
866 if (cell
->type
== "$alu") {
867 param_bool("\\A_SIGNED");
868 param_bool("\\B_SIGNED");
869 port("\\A", param("\\A_WIDTH"));
870 port("\\B", param("\\B_WIDTH"));
873 port("\\X", param("\\Y_WIDTH"));
874 port("\\Y", param("\\Y_WIDTH"));
875 port("\\CO", param("\\Y_WIDTH"));
880 if (cell
->type
== "$macc") {
882 param("\\CONFIG_WIDTH");
883 port("\\A", param("\\A_WIDTH"));
884 port("\\B", param("\\B_WIDTH"));
885 port("\\Y", param("\\Y_WIDTH"));
887 Macc().from_cell(cell
);
891 if (cell
->type
== "$logic_not") {
892 param_bool("\\A_SIGNED");
893 port("\\A", param("\\A_WIDTH"));
894 port("\\Y", param("\\Y_WIDTH"));
899 if (cell
->type
== "$logic_and" || cell
->type
== "$logic_or") {
900 param_bool("\\A_SIGNED");
901 param_bool("\\B_SIGNED");
902 port("\\A", param("\\A_WIDTH"));
903 port("\\B", param("\\B_WIDTH"));
904 port("\\Y", param("\\Y_WIDTH"));
905 check_expected(false);
909 if (cell
->type
== "$slice") {
911 port("\\A", param("\\A_WIDTH"));
912 port("\\Y", param("\\Y_WIDTH"));
913 if (param("\\OFFSET") + param("\\Y_WIDTH") > param("\\A_WIDTH"))
919 if (cell
->type
== "$concat") {
920 port("\\A", param("\\A_WIDTH"));
921 port("\\B", param("\\B_WIDTH"));
922 port("\\Y", param("\\A_WIDTH") + param("\\B_WIDTH"));
927 if (cell
->type
== "$mux") {
928 port("\\A", param("\\WIDTH"));
929 port("\\B", param("\\WIDTH"));
931 port("\\Y", param("\\WIDTH"));
936 if (cell
->type
== "$pmux") {
937 port("\\A", param("\\WIDTH"));
938 port("\\B", param("\\WIDTH") * param("\\S_WIDTH"));
939 port("\\S", param("\\S_WIDTH"));
940 port("\\Y", param("\\WIDTH"));
945 if (cell
->type
== "$lut") {
947 port("\\A", param("\\WIDTH"));
953 if (cell
->type
== "$sop") {
956 port("\\A", param("\\WIDTH"));
962 if (cell
->type
== "$sr") {
963 param_bool("\\SET_POLARITY");
964 param_bool("\\CLR_POLARITY");
965 port("\\SET", param("\\WIDTH"));
966 port("\\CLR", param("\\WIDTH"));
967 port("\\Q", param("\\WIDTH"));
972 if (cell
->type
== "$ff") {
973 port("\\D", param("\\WIDTH"));
974 port("\\Q", param("\\WIDTH"));
979 if (cell
->type
== "$dff") {
980 param_bool("\\CLK_POLARITY");
982 port("\\D", param("\\WIDTH"));
983 port("\\Q", param("\\WIDTH"));
988 if (cell
->type
== "$dffe") {
989 param_bool("\\CLK_POLARITY");
990 param_bool("\\EN_POLARITY");
993 port("\\D", param("\\WIDTH"));
994 port("\\Q", param("\\WIDTH"));
999 if (cell
->type
== "$dffsr") {
1000 param_bool("\\CLK_POLARITY");
1001 param_bool("\\SET_POLARITY");
1002 param_bool("\\CLR_POLARITY");
1004 port("\\SET", param("\\WIDTH"));
1005 port("\\CLR", param("\\WIDTH"));
1006 port("\\D", param("\\WIDTH"));
1007 port("\\Q", param("\\WIDTH"));
1012 if (cell
->type
== "$adff") {
1013 param_bool("\\CLK_POLARITY");
1014 param_bool("\\ARST_POLARITY");
1015 param_bits("\\ARST_VALUE", param("\\WIDTH"));
1018 port("\\D", param("\\WIDTH"));
1019 port("\\Q", param("\\WIDTH"));
1024 if (cell
->type
== "$dlatch") {
1025 param_bool("\\EN_POLARITY");
1027 port("\\D", param("\\WIDTH"));
1028 port("\\Q", param("\\WIDTH"));
1033 if (cell
->type
== "$dlatchsr") {
1034 param_bool("\\EN_POLARITY");
1035 param_bool("\\SET_POLARITY");
1036 param_bool("\\CLR_POLARITY");
1038 port("\\SET", param("\\WIDTH"));
1039 port("\\CLR", param("\\WIDTH"));
1040 port("\\D", param("\\WIDTH"));
1041 port("\\Q", param("\\WIDTH"));
1046 if (cell
->type
== "$fsm") {
1048 param_bool("\\CLK_POLARITY");
1049 param_bool("\\ARST_POLARITY");
1050 param("\\STATE_BITS");
1051 param("\\STATE_NUM");
1052 param("\\STATE_NUM_LOG2");
1053 param("\\STATE_RST");
1054 param_bits("\\STATE_TABLE", param("\\STATE_BITS") * param("\\STATE_NUM"));
1055 param("\\TRANS_NUM");
1056 param_bits("\\TRANS_TABLE", param("\\TRANS_NUM") * (2*param("\\STATE_NUM_LOG2") + param("\\CTRL_IN_WIDTH") + param("\\CTRL_OUT_WIDTH")));
1059 port("\\CTRL_IN", param("\\CTRL_IN_WIDTH"));
1060 port("\\CTRL_OUT", param("\\CTRL_OUT_WIDTH"));
1065 if (cell
->type
== "$memrd") {
1067 param_bool("\\CLK_ENABLE");
1068 param_bool("\\CLK_POLARITY");
1069 param_bool("\\TRANSPARENT");
1072 port("\\ADDR", param("\\ABITS"));
1073 port("\\DATA", param("\\WIDTH"));
1078 if (cell
->type
== "$memwr") {
1080 param_bool("\\CLK_ENABLE");
1081 param_bool("\\CLK_POLARITY");
1082 param("\\PRIORITY");
1084 port("\\EN", param("\\WIDTH"));
1085 port("\\ADDR", param("\\ABITS"));
1086 port("\\DATA", param("\\WIDTH"));
1091 if (cell
->type
== "$meminit") {
1093 param("\\PRIORITY");
1094 port("\\ADDR", param("\\ABITS"));
1095 port("\\DATA", param("\\WIDTH") * param("\\WORDS"));
1100 if (cell
->type
== "$mem") {
1105 param_bits("\\RD_CLK_ENABLE", max(1, param("\\RD_PORTS")));
1106 param_bits("\\RD_CLK_POLARITY", max(1, param("\\RD_PORTS")));
1107 param_bits("\\RD_TRANSPARENT", max(1, param("\\RD_PORTS")));
1108 param_bits("\\WR_CLK_ENABLE", max(1, param("\\WR_PORTS")));
1109 param_bits("\\WR_CLK_POLARITY", max(1, param("\\WR_PORTS")));
1110 port("\\RD_CLK", param("\\RD_PORTS"));
1111 port("\\RD_EN", param("\\RD_PORTS"));
1112 port("\\RD_ADDR", param("\\RD_PORTS") * param("\\ABITS"));
1113 port("\\RD_DATA", param("\\RD_PORTS") * param("\\WIDTH"));
1114 port("\\WR_CLK", param("\\WR_PORTS"));
1115 port("\\WR_EN", param("\\WR_PORTS") * param("\\WIDTH"));
1116 port("\\WR_ADDR", param("\\WR_PORTS") * param("\\ABITS"));
1117 port("\\WR_DATA", param("\\WR_PORTS") * param("\\WIDTH"));
1122 if (cell
->type
== "$tribuf") {
1123 port("\\A", param("\\WIDTH"));
1124 port("\\Y", param("\\WIDTH"));
1130 if (cell
->type
.in("$assert", "$assume", "$live", "$fair", "$cover")) {
1137 if (cell
->type
== "$initstate") {
1143 if (cell
->type
.in("$anyconst", "$anyseq", "$allconst", "$allseq")) {
1144 port("\\Y", param("\\WIDTH"));
1149 if (cell
->type
== "$equiv") {
1157 if (cell
->type
== "$_BUF_") { check_gate("AY"); return; }
1158 if (cell
->type
== "$_NOT_") { check_gate("AY"); return; }
1159 if (cell
->type
== "$_AND_") { check_gate("ABY"); return; }
1160 if (cell
->type
== "$_NAND_") { check_gate("ABY"); return; }
1161 if (cell
->type
== "$_OR_") { check_gate("ABY"); return; }
1162 if (cell
->type
== "$_NOR_") { check_gate("ABY"); return; }
1163 if (cell
->type
== "$_XOR_") { check_gate("ABY"); return; }
1164 if (cell
->type
== "$_XNOR_") { check_gate("ABY"); return; }
1165 if (cell
->type
== "$_ANDNOT_") { check_gate("ABY"); return; }
1166 if (cell
->type
== "$_ORNOT_") { check_gate("ABY"); return; }
1167 if (cell
->type
== "$_MUX_") { check_gate("ABSY"); return; }
1168 if (cell
->type
== "$_AOI3_") { check_gate("ABCY"); return; }
1169 if (cell
->type
== "$_OAI3_") { check_gate("ABCY"); return; }
1170 if (cell
->type
== "$_AOI4_") { check_gate("ABCDY"); return; }
1171 if (cell
->type
== "$_OAI4_") { check_gate("ABCDY"); return; }
1173 if (cell
->type
== "$_TBUF_") { check_gate("AYE"); return; }
1175 if (cell
->type
== "$_MUX4_") { check_gate("ABCDSTY"); return; }
1176 if (cell
->type
== "$_MUX8_") { check_gate("ABCDEFGHSTUY"); return; }
1177 if (cell
->type
== "$_MUX16_") { check_gate("ABCDEFGHIJKLMNOPSTUVY"); return; }
1179 if (cell
->type
== "$_SR_NN_") { check_gate("SRQ"); return; }
1180 if (cell
->type
== "$_SR_NP_") { check_gate("SRQ"); return; }
1181 if (cell
->type
== "$_SR_PN_") { check_gate("SRQ"); return; }
1182 if (cell
->type
== "$_SR_PP_") { check_gate("SRQ"); return; }
1184 if (cell
->type
== "$_FF_") { check_gate("DQ"); return; }
1185 if (cell
->type
== "$_DFF_N_") { check_gate("DQC"); return; }
1186 if (cell
->type
== "$_DFF_P_") { check_gate("DQC"); return; }
1188 if (cell
->type
== "$_DFFE_NN_") { check_gate("DQCE"); return; }
1189 if (cell
->type
== "$_DFFE_NP_") { check_gate("DQCE"); return; }
1190 if (cell
->type
== "$_DFFE_PN_") { check_gate("DQCE"); return; }
1191 if (cell
->type
== "$_DFFE_PP_") { check_gate("DQCE"); return; }
1193 if (cell
->type
== "$_DFF_NN0_") { check_gate("DQCR"); return; }
1194 if (cell
->type
== "$_DFF_NN1_") { check_gate("DQCR"); return; }
1195 if (cell
->type
== "$_DFF_NP0_") { check_gate("DQCR"); return; }
1196 if (cell
->type
== "$_DFF_NP1_") { check_gate("DQCR"); return; }
1197 if (cell
->type
== "$_DFF_PN0_") { check_gate("DQCR"); return; }
1198 if (cell
->type
== "$_DFF_PN1_") { check_gate("DQCR"); return; }
1199 if (cell
->type
== "$_DFF_PP0_") { check_gate("DQCR"); return; }
1200 if (cell
->type
== "$_DFF_PP1_") { check_gate("DQCR"); return; }
1202 if (cell
->type
== "$_DFFSR_NNN_") { check_gate("CSRDQ"); return; }
1203 if (cell
->type
== "$_DFFSR_NNP_") { check_gate("CSRDQ"); return; }
1204 if (cell
->type
== "$_DFFSR_NPN_") { check_gate("CSRDQ"); return; }
1205 if (cell
->type
== "$_DFFSR_NPP_") { check_gate("CSRDQ"); return; }
1206 if (cell
->type
== "$_DFFSR_PNN_") { check_gate("CSRDQ"); return; }
1207 if (cell
->type
== "$_DFFSR_PNP_") { check_gate("CSRDQ"); return; }
1208 if (cell
->type
== "$_DFFSR_PPN_") { check_gate("CSRDQ"); return; }
1209 if (cell
->type
== "$_DFFSR_PPP_") { check_gate("CSRDQ"); return; }
1211 if (cell
->type
== "$_DLATCH_N_") { check_gate("EDQ"); return; }
1212 if (cell
->type
== "$_DLATCH_P_") { check_gate("EDQ"); return; }
1214 if (cell
->type
== "$_DLATCHSR_NNN_") { check_gate("ESRDQ"); return; }
1215 if (cell
->type
== "$_DLATCHSR_NNP_") { check_gate("ESRDQ"); return; }
1216 if (cell
->type
== "$_DLATCHSR_NPN_") { check_gate("ESRDQ"); return; }
1217 if (cell
->type
== "$_DLATCHSR_NPP_") { check_gate("ESRDQ"); return; }
1218 if (cell
->type
== "$_DLATCHSR_PNN_") { check_gate("ESRDQ"); return; }
1219 if (cell
->type
== "$_DLATCHSR_PNP_") { check_gate("ESRDQ"); return; }
1220 if (cell
->type
== "$_DLATCHSR_PPN_") { check_gate("ESRDQ"); return; }
1221 if (cell
->type
== "$_DLATCHSR_PPP_") { check_gate("ESRDQ"); return; }
1229 void RTLIL::Module::sort()
1231 wires_
.sort(sort_by_id_str());
1232 cells_
.sort(sort_by_id_str());
1233 avail_parameters
.sort(sort_by_id_str());
1234 memories
.sort(sort_by_id_str());
1235 processes
.sort(sort_by_id_str());
1236 for (auto &it
: cells_
)
1238 for (auto &it
: wires_
)
1239 it
.second
->attributes
.sort(sort_by_id_str());
1240 for (auto &it
: memories
)
1241 it
.second
->attributes
.sort(sort_by_id_str());
1244 void RTLIL::Module::check()
1247 std::vector
<bool> ports_declared
;
1248 for (auto &it
: wires_
) {
1249 log_assert(this == it
.second
->module
);
1250 log_assert(it
.first
== it
.second
->name
);
1251 log_assert(!it
.first
.empty());
1252 log_assert(it
.second
->width
>= 0);
1253 log_assert(it
.second
->port_id
>= 0);
1254 for (auto &it2
: it
.second
->attributes
)
1255 log_assert(!it2
.first
.empty());
1256 if (it
.second
->port_id
) {
1257 log_assert(GetSize(ports
) >= it
.second
->port_id
);
1258 log_assert(ports
.at(it
.second
->port_id
-1) == it
.first
);
1259 log_assert(it
.second
->port_input
|| it
.second
->port_output
);
1260 if (GetSize(ports_declared
) < it
.second
->port_id
)
1261 ports_declared
.resize(it
.second
->port_id
);
1262 log_assert(ports_declared
[it
.second
->port_id
-1] == false);
1263 ports_declared
[it
.second
->port_id
-1] = true;
1265 log_assert(!it
.second
->port_input
&& !it
.second
->port_output
);
1267 for (auto port_declared
: ports_declared
)
1268 log_assert(port_declared
== true);
1269 log_assert(GetSize(ports
) == GetSize(ports_declared
));
1271 for (auto &it
: memories
) {
1272 log_assert(it
.first
== it
.second
->name
);
1273 log_assert(!it
.first
.empty());
1274 log_assert(it
.second
->width
>= 0);
1275 log_assert(it
.second
->size
>= 0);
1276 for (auto &it2
: it
.second
->attributes
)
1277 log_assert(!it2
.first
.empty());
1280 for (auto &it
: cells_
) {
1281 log_assert(this == it
.second
->module
);
1282 log_assert(it
.first
== it
.second
->name
);
1283 log_assert(!it
.first
.empty());
1284 log_assert(!it
.second
->type
.empty());
1285 for (auto &it2
: it
.second
->connections()) {
1286 log_assert(!it2
.first
.empty());
1289 for (auto &it2
: it
.second
->attributes
)
1290 log_assert(!it2
.first
.empty());
1291 for (auto &it2
: it
.second
->parameters
)
1292 log_assert(!it2
.first
.empty());
1293 InternalCellChecker
checker(this, it
.second
);
1297 for (auto &it
: processes
) {
1298 log_assert(it
.first
== it
.second
->name
);
1299 log_assert(!it
.first
.empty());
1300 // FIXME: More checks here..
1303 for (auto &it
: connections_
) {
1304 log_assert(it
.first
.size() == it
.second
.size());
1305 log_assert(!it
.first
.has_const());
1310 for (auto &it
: attributes
)
1311 log_assert(!it
.first
.empty());
1315 void RTLIL::Module::optimize()
1319 void RTLIL::Module::cloneInto(RTLIL::Module
*new_mod
) const
1321 log_assert(new_mod
->refcount_wires_
== 0);
1322 log_assert(new_mod
->refcount_cells_
== 0);
1324 new_mod
->avail_parameters
= avail_parameters
;
1326 for (auto &conn
: connections_
)
1327 new_mod
->connect(conn
);
1329 for (auto &attr
: attributes
)
1330 new_mod
->attributes
[attr
.first
] = attr
.second
;
1332 for (auto &it
: wires_
)
1333 new_mod
->addWire(it
.first
, it
.second
);
1335 for (auto &it
: memories
)
1336 new_mod
->memories
[it
.first
] = new RTLIL::Memory(*it
.second
);
1338 for (auto &it
: cells_
)
1339 new_mod
->addCell(it
.first
, it
.second
);
1341 for (auto &it
: processes
)
1342 new_mod
->processes
[it
.first
] = it
.second
->clone();
1344 struct RewriteSigSpecWorker
1347 void operator()(RTLIL::SigSpec
&sig
)
1349 std::vector
<RTLIL::SigChunk
> chunks
= sig
.chunks();
1350 for (auto &c
: chunks
)
1352 c
.wire
= mod
->wires_
.at(c
.wire
->name
);
1357 RewriteSigSpecWorker rewriteSigSpecWorker
;
1358 rewriteSigSpecWorker
.mod
= new_mod
;
1359 new_mod
->rewrite_sigspecs(rewriteSigSpecWorker
);
1360 new_mod
->fixup_ports();
1363 RTLIL::Module
*RTLIL::Module::clone() const
1365 RTLIL::Module
*new_mod
= new RTLIL::Module
;
1366 new_mod
->name
= name
;
1371 bool RTLIL::Module::has_memories() const
1373 return !memories
.empty();
1376 bool RTLIL::Module::has_processes() const
1378 return !processes
.empty();
1381 bool RTLIL::Module::has_memories_warn() const
1383 if (!memories
.empty())
1384 log_warning("Ignoring module %s because it contains memories (run 'memory' command first).\n", log_id(this));
1385 return !memories
.empty();
1388 bool RTLIL::Module::has_processes_warn() const
1390 if (!processes
.empty())
1391 log_warning("Ignoring module %s because it contains processes (run 'proc' command first).\n", log_id(this));
1392 return !processes
.empty();
1395 std::vector
<RTLIL::Wire
*> RTLIL::Module::selected_wires() const
1397 std::vector
<RTLIL::Wire
*> result
;
1398 result
.reserve(wires_
.size());
1399 for (auto &it
: wires_
)
1400 if (design
->selected(this, it
.second
))
1401 result
.push_back(it
.second
);
1405 std::vector
<RTLIL::Cell
*> RTLIL::Module::selected_cells() const
1407 std::vector
<RTLIL::Cell
*> result
;
1408 result
.reserve(wires_
.size());
1409 for (auto &it
: cells_
)
1410 if (design
->selected(this, it
.second
))
1411 result
.push_back(it
.second
);
1415 void RTLIL::Module::add(RTLIL::Wire
*wire
)
1417 log_assert(!wire
->name
.empty());
1418 log_assert(count_id(wire
->name
) == 0);
1419 log_assert(refcount_wires_
== 0);
1420 wires_
[wire
->name
] = wire
;
1421 wire
->module
= this;
1424 void RTLIL::Module::add(RTLIL::Cell
*cell
)
1426 log_assert(!cell
->name
.empty());
1427 log_assert(count_id(cell
->name
) == 0);
1428 log_assert(refcount_cells_
== 0);
1429 cells_
[cell
->name
] = cell
;
1430 cell
->module
= this;
1434 struct DeleteWireWorker
1436 RTLIL::Module
*module
;
1437 const pool
<RTLIL::Wire
*> *wires_p
;
1439 void operator()(RTLIL::SigSpec
&sig
) {
1440 std::vector
<RTLIL::SigChunk
> chunks
= sig
;
1441 for (auto &c
: chunks
)
1442 if (c
.wire
!= NULL
&& wires_p
->count(c
.wire
)) {
1443 c
.wire
= module
->addWire(NEW_ID
, c
.width
);
1451 void RTLIL::Module::remove(const pool
<RTLIL::Wire
*> &wires
)
1453 log_assert(refcount_wires_
== 0);
1455 DeleteWireWorker delete_wire_worker
;
1456 delete_wire_worker
.module
= this;
1457 delete_wire_worker
.wires_p
= &wires
;
1458 rewrite_sigspecs(delete_wire_worker
);
1460 for (auto &it
: wires
) {
1461 log_assert(wires_
.count(it
->name
) != 0);
1462 wires_
.erase(it
->name
);
1467 void RTLIL::Module::remove(RTLIL::Cell
*cell
)
1469 while (!cell
->connections_
.empty())
1470 cell
->unsetPort(cell
->connections_
.begin()->first
);
1472 log_assert(cells_
.count(cell
->name
) != 0);
1473 log_assert(refcount_cells_
== 0);
1474 cells_
.erase(cell
->name
);
1478 void RTLIL::Module::rename(RTLIL::Wire
*wire
, RTLIL::IdString new_name
)
1480 log_assert(wires_
[wire
->name
] == wire
);
1481 log_assert(refcount_wires_
== 0);
1482 wires_
.erase(wire
->name
);
1483 wire
->name
= new_name
;
1487 void RTLIL::Module::rename(RTLIL::Cell
*cell
, RTLIL::IdString new_name
)
1489 log_assert(cells_
[cell
->name
] == cell
);
1490 log_assert(refcount_wires_
== 0);
1491 cells_
.erase(cell
->name
);
1492 cell
->name
= new_name
;
1496 void RTLIL::Module::rename(RTLIL::IdString old_name
, RTLIL::IdString new_name
)
1498 log_assert(count_id(old_name
) != 0);
1499 if (wires_
.count(old_name
))
1500 rename(wires_
.at(old_name
), new_name
);
1501 else if (cells_
.count(old_name
))
1502 rename(cells_
.at(old_name
), new_name
);
1507 void RTLIL::Module::swap_names(RTLIL::Wire
*w1
, RTLIL::Wire
*w2
)
1509 log_assert(wires_
[w1
->name
] == w1
);
1510 log_assert(wires_
[w2
->name
] == w2
);
1511 log_assert(refcount_wires_
== 0);
1513 wires_
.erase(w1
->name
);
1514 wires_
.erase(w2
->name
);
1516 std::swap(w1
->name
, w2
->name
);
1518 wires_
[w1
->name
] = w1
;
1519 wires_
[w2
->name
] = w2
;
1522 void RTLIL::Module::swap_names(RTLIL::Cell
*c1
, RTLIL::Cell
*c2
)
1524 log_assert(cells_
[c1
->name
] == c1
);
1525 log_assert(cells_
[c2
->name
] == c2
);
1526 log_assert(refcount_cells_
== 0);
1528 cells_
.erase(c1
->name
);
1529 cells_
.erase(c2
->name
);
1531 std::swap(c1
->name
, c2
->name
);
1533 cells_
[c1
->name
] = c1
;
1534 cells_
[c2
->name
] = c2
;
1537 RTLIL::IdString
RTLIL::Module::uniquify(RTLIL::IdString name
)
1540 return uniquify(name
, index
);
1543 RTLIL::IdString
RTLIL::Module::uniquify(RTLIL::IdString name
, int &index
)
1546 if (count_id(name
) == 0)
1552 RTLIL::IdString new_name
= stringf("%s_%d", name
.c_str(), index
);
1553 if (count_id(new_name
) == 0)
1559 static bool fixup_ports_compare(const RTLIL::Wire
*a
, const RTLIL::Wire
*b
)
1561 if (a
->port_id
&& !b
->port_id
)
1563 if (!a
->port_id
&& b
->port_id
)
1566 if (a
->port_id
== b
->port_id
)
1567 return a
->name
< b
->name
;
1568 return a
->port_id
< b
->port_id
;
1571 void RTLIL::Module::connect(const RTLIL::SigSig
&conn
)
1573 for (auto mon
: monitors
)
1574 mon
->notify_connect(this, conn
);
1577 for (auto mon
: design
->monitors
)
1578 mon
->notify_connect(this, conn
);
1580 // ignore all attempts to assign constants to other constants
1581 if (conn
.first
.has_const()) {
1582 RTLIL::SigSig new_conn
;
1583 for (int i
= 0; i
< GetSize(conn
.first
); i
++)
1584 if (conn
.first
[i
].wire
) {
1585 new_conn
.first
.append(conn
.first
[i
]);
1586 new_conn
.second
.append(conn
.second
[i
]);
1588 if (GetSize(new_conn
.first
))
1594 log("#X# Connect (SigSig) in %s: %s = %s (%d bits)\n", log_id(this), log_signal(conn
.first
), log_signal(conn
.second
), GetSize(conn
.first
));
1595 log_backtrace("-X- ", yosys_xtrace
-1);
1598 log_assert(GetSize(conn
.first
) == GetSize(conn
.second
));
1599 connections_
.push_back(conn
);
1602 void RTLIL::Module::connect(const RTLIL::SigSpec
&lhs
, const RTLIL::SigSpec
&rhs
)
1604 connect(RTLIL::SigSig(lhs
, rhs
));
1607 void RTLIL::Module::new_connections(const std::vector
<RTLIL::SigSig
> &new_conn
)
1609 for (auto mon
: monitors
)
1610 mon
->notify_connect(this, new_conn
);
1613 for (auto mon
: design
->monitors
)
1614 mon
->notify_connect(this, new_conn
);
1617 log("#X# New connections vector in %s:\n", log_id(this));
1618 for (auto &conn
: new_conn
)
1619 log("#X# %s = %s (%d bits)\n", log_signal(conn
.first
), log_signal(conn
.second
), GetSize(conn
.first
));
1620 log_backtrace("-X- ", yosys_xtrace
-1);
1623 connections_
= new_conn
;
1626 const std::vector
<RTLIL::SigSig
> &RTLIL::Module::connections() const
1628 return connections_
;
1631 void RTLIL::Module::fixup_ports()
1633 std::vector
<RTLIL::Wire
*> all_ports
;
1635 for (auto &w
: wires_
)
1636 if (w
.second
->port_input
|| w
.second
->port_output
)
1637 all_ports
.push_back(w
.second
);
1639 w
.second
->port_id
= 0;
1641 std::sort(all_ports
.begin(), all_ports
.end(), fixup_ports_compare
);
1644 for (size_t i
= 0; i
< all_ports
.size(); i
++) {
1645 ports
.push_back(all_ports
[i
]->name
);
1646 all_ports
[i
]->port_id
= i
+1;
1650 RTLIL::Wire
*RTLIL::Module::addWire(RTLIL::IdString name
, int width
)
1652 RTLIL::Wire
*wire
= new RTLIL::Wire
;
1654 wire
->width
= width
;
1659 RTLIL::Wire
*RTLIL::Module::addWire(RTLIL::IdString name
, const RTLIL::Wire
*other
)
1661 RTLIL::Wire
*wire
= addWire(name
);
1662 wire
->width
= other
->width
;
1663 wire
->start_offset
= other
->start_offset
;
1664 wire
->port_id
= other
->port_id
;
1665 wire
->port_input
= other
->port_input
;
1666 wire
->port_output
= other
->port_output
;
1667 wire
->upto
= other
->upto
;
1668 wire
->attributes
= other
->attributes
;
1672 RTLIL::Cell
*RTLIL::Module::addCell(RTLIL::IdString name
, RTLIL::IdString type
)
1674 RTLIL::Cell
*cell
= new RTLIL::Cell
;
1681 RTLIL::Cell
*RTLIL::Module::addCell(RTLIL::IdString name
, const RTLIL::Cell
*other
)
1683 RTLIL::Cell
*cell
= addCell(name
, other
->type
);
1684 cell
->connections_
= other
->connections_
;
1685 cell
->parameters
= other
->parameters
;
1686 cell
->attributes
= other
->attributes
;
1690 #define DEF_METHOD(_func, _y_size, _type) \
1691 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed, const std::string &src) { \
1692 RTLIL::Cell *cell = addCell(name, _type); \
1693 cell->parameters["\\A_SIGNED"] = is_signed; \
1694 cell->parameters["\\A_WIDTH"] = sig_a.size(); \
1695 cell->parameters["\\Y_WIDTH"] = sig_y.size(); \
1696 cell->setPort("\\A", sig_a); \
1697 cell->setPort("\\Y", sig_y); \
1698 cell->set_src_attribute(src); \
1701 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed, const std::string &src) { \
1702 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
1703 add ## _func(name, sig_a, sig_y, is_signed, src); \
1706 DEF_METHOD(Not
, sig_a
.size(), "$not")
1707 DEF_METHOD(Pos
, sig_a
.size(), "$pos")
1708 DEF_METHOD(Neg
, sig_a
.size(), "$neg")
1709 DEF_METHOD(ReduceAnd
, 1, "$reduce_and")
1710 DEF_METHOD(ReduceOr
, 1, "$reduce_or")
1711 DEF_METHOD(ReduceXor
, 1, "$reduce_xor")
1712 DEF_METHOD(ReduceXnor
, 1, "$reduce_xnor")
1713 DEF_METHOD(ReduceBool
, 1, "$reduce_bool")
1714 DEF_METHOD(LogicNot
, 1, "$logic_not")
1717 #define DEF_METHOD(_func, _y_size, _type) \
1718 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed, const std::string &src) { \
1719 RTLIL::Cell *cell = addCell(name, _type); \
1720 cell->parameters["\\A_SIGNED"] = is_signed; \
1721 cell->parameters["\\B_SIGNED"] = is_signed; \
1722 cell->parameters["\\A_WIDTH"] = sig_a.size(); \
1723 cell->parameters["\\B_WIDTH"] = sig_b.size(); \
1724 cell->parameters["\\Y_WIDTH"] = sig_y.size(); \
1725 cell->setPort("\\A", sig_a); \
1726 cell->setPort("\\B", sig_b); \
1727 cell->setPort("\\Y", sig_y); \
1728 cell->set_src_attribute(src); \
1731 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed, const std::string &src) { \
1732 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
1733 add ## _func(name, sig_a, sig_b, sig_y, is_signed, src); \
1736 DEF_METHOD(And
, max(sig_a
.size(), sig_b
.size()), "$and")
1737 DEF_METHOD(Or
, max(sig_a
.size(), sig_b
.size()), "$or")
1738 DEF_METHOD(Xor
, max(sig_a
.size(), sig_b
.size()), "$xor")
1739 DEF_METHOD(Xnor
, max(sig_a
.size(), sig_b
.size()), "$xnor")
1740 DEF_METHOD(Shl
, sig_a
.size(), "$shl")
1741 DEF_METHOD(Shr
, sig_a
.size(), "$shr")
1742 DEF_METHOD(Sshl
, sig_a
.size(), "$sshl")
1743 DEF_METHOD(Sshr
, sig_a
.size(), "$sshr")
1744 DEF_METHOD(Shift
, sig_a
.size(), "$shift")
1745 DEF_METHOD(Shiftx
, sig_a
.size(), "$shiftx")
1746 DEF_METHOD(Lt
, 1, "$lt")
1747 DEF_METHOD(Le
, 1, "$le")
1748 DEF_METHOD(Eq
, 1, "$eq")
1749 DEF_METHOD(Ne
, 1, "$ne")
1750 DEF_METHOD(Eqx
, 1, "$eqx")
1751 DEF_METHOD(Nex
, 1, "$nex")
1752 DEF_METHOD(Ge
, 1, "$ge")
1753 DEF_METHOD(Gt
, 1, "$gt")
1754 DEF_METHOD(Add
, max(sig_a
.size(), sig_b
.size()), "$add")
1755 DEF_METHOD(Sub
, max(sig_a
.size(), sig_b
.size()), "$sub")
1756 DEF_METHOD(Mul
, max(sig_a
.size(), sig_b
.size()), "$mul")
1757 DEF_METHOD(Div
, max(sig_a
.size(), sig_b
.size()), "$div")
1758 DEF_METHOD(Mod
, max(sig_a
.size(), sig_b
.size()), "$mod")
1759 DEF_METHOD(LogicAnd
, 1, "$logic_and")
1760 DEF_METHOD(LogicOr
, 1, "$logic_or")
1763 #define DEF_METHOD(_func, _type, _pmux) \
1764 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, RTLIL::SigSpec sig_y, const std::string &src) { \
1765 RTLIL::Cell *cell = addCell(name, _type); \
1766 cell->parameters["\\WIDTH"] = sig_a.size(); \
1767 if (_pmux) cell->parameters["\\S_WIDTH"] = sig_s.size(); \
1768 cell->setPort("\\A", sig_a); \
1769 cell->setPort("\\B", sig_b); \
1770 cell->setPort("\\S", sig_s); \
1771 cell->setPort("\\Y", sig_y); \
1772 cell->set_src_attribute(src); \
1775 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, const std::string &src) { \
1776 RTLIL::SigSpec sig_y = addWire(NEW_ID, sig_a.size()); \
1777 add ## _func(name, sig_a, sig_b, sig_s, sig_y, src); \
1780 DEF_METHOD(Mux
, "$mux", 0)
1781 DEF_METHOD(Pmux
, "$pmux", 1)
1784 #define DEF_METHOD_2(_func, _type, _P1, _P2) \
1785 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, const std::string &src) { \
1786 RTLIL::Cell *cell = addCell(name, _type); \
1787 cell->setPort("\\" #_P1, sig1); \
1788 cell->setPort("\\" #_P2, sig2); \
1789 cell->set_src_attribute(src); \
1792 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, const std::string &src) { \
1793 RTLIL::SigBit sig2 = addWire(NEW_ID); \
1794 add ## _func(name, sig1, sig2, src); \
1797 #define DEF_METHOD_3(_func, _type, _P1, _P2, _P3) \
1798 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, const std::string &src) { \
1799 RTLIL::Cell *cell = addCell(name, _type); \
1800 cell->setPort("\\" #_P1, sig1); \
1801 cell->setPort("\\" #_P2, sig2); \
1802 cell->setPort("\\" #_P3, sig3); \
1803 cell->set_src_attribute(src); \
1806 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, const std::string &src) { \
1807 RTLIL::SigBit sig3 = addWire(NEW_ID); \
1808 add ## _func(name, sig1, sig2, sig3, src); \
1811 #define DEF_METHOD_4(_func, _type, _P1, _P2, _P3, _P4) \
1812 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, RTLIL::SigBit sig4, const std::string &src) { \
1813 RTLIL::Cell *cell = addCell(name, _type); \
1814 cell->setPort("\\" #_P1, sig1); \
1815 cell->setPort("\\" #_P2, sig2); \
1816 cell->setPort("\\" #_P3, sig3); \
1817 cell->setPort("\\" #_P4, sig4); \
1818 cell->set_src_attribute(src); \
1821 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, const std::string &src) { \
1822 RTLIL::SigBit sig4 = addWire(NEW_ID); \
1823 add ## _func(name, sig1, sig2, sig3, sig4, src); \
1826 #define DEF_METHOD_5(_func, _type, _P1, _P2, _P3, _P4, _P5) \
1827 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, RTLIL::SigBit sig4, RTLIL::SigBit sig5, const std::string &src) { \
1828 RTLIL::Cell *cell = addCell(name, _type); \
1829 cell->setPort("\\" #_P1, sig1); \
1830 cell->setPort("\\" #_P2, sig2); \
1831 cell->setPort("\\" #_P3, sig3); \
1832 cell->setPort("\\" #_P4, sig4); \
1833 cell->setPort("\\" #_P5, sig5); \
1834 cell->set_src_attribute(src); \
1837 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, RTLIL::SigBit sig4, const std::string &src) { \
1838 RTLIL::SigBit sig5 = addWire(NEW_ID); \
1839 add ## _func(name, sig1, sig2, sig3, sig4, sig5, src); \
1842 DEF_METHOD_2(BufGate
, "$_BUF_", A
, Y
)
1843 DEF_METHOD_2(NotGate
, "$_NOT_", A
, Y
)
1844 DEF_METHOD_3(AndGate
, "$_AND_", A
, B
, Y
)
1845 DEF_METHOD_3(NandGate
, "$_NAND_", A
, B
, Y
)
1846 DEF_METHOD_3(OrGate
, "$_OR_", A
, B
, Y
)
1847 DEF_METHOD_3(NorGate
, "$_NOR_", A
, B
, Y
)
1848 DEF_METHOD_3(XorGate
, "$_XOR_", A
, B
, Y
)
1849 DEF_METHOD_3(XnorGate
, "$_XNOR_", A
, B
, Y
)
1850 DEF_METHOD_3(AndnotGate
, "$_ANDNOT_", A
, B
, Y
)
1851 DEF_METHOD_3(OrnotGate
, "$_ORNOT_", A
, B
, Y
)
1852 DEF_METHOD_4(MuxGate
, "$_MUX_", A
, B
, S
, Y
)
1853 DEF_METHOD_4(Aoi3Gate
, "$_AOI3_", A
, B
, C
, Y
)
1854 DEF_METHOD_4(Oai3Gate
, "$_OAI3_", A
, B
, C
, Y
)
1855 DEF_METHOD_5(Aoi4Gate
, "$_AOI4_", A
, B
, C
, D
, Y
)
1856 DEF_METHOD_5(Oai4Gate
, "$_OAI4_", A
, B
, C
, D
, Y
)
1862 RTLIL::Cell
* RTLIL::Module::addPow(RTLIL::IdString name
, RTLIL::SigSpec sig_a
, RTLIL::SigSpec sig_b
, RTLIL::SigSpec sig_y
, bool a_signed
, bool b_signed
, const std::string
&src
)
1864 RTLIL::Cell
*cell
= addCell(name
, "$pow");
1865 cell
->parameters
["\\A_SIGNED"] = a_signed
;
1866 cell
->parameters
["\\B_SIGNED"] = b_signed
;
1867 cell
->parameters
["\\A_WIDTH"] = sig_a
.size();
1868 cell
->parameters
["\\B_WIDTH"] = sig_b
.size();
1869 cell
->parameters
["\\Y_WIDTH"] = sig_y
.size();
1870 cell
->setPort("\\A", sig_a
);
1871 cell
->setPort("\\B", sig_b
);
1872 cell
->setPort("\\Y", sig_y
);
1873 cell
->set_src_attribute(src
);
1877 RTLIL::Cell
* RTLIL::Module::addSlice(RTLIL::IdString name
, RTLIL::SigSpec sig_a
, RTLIL::SigSpec sig_y
, RTLIL::Const offset
, const std::string
&src
)
1879 RTLIL::Cell
*cell
= addCell(name
, "$slice");
1880 cell
->parameters
["\\A_WIDTH"] = sig_a
.size();
1881 cell
->parameters
["\\Y_WIDTH"] = sig_y
.size();
1882 cell
->parameters
["\\OFFSET"] = offset
;
1883 cell
->setPort("\\A", sig_a
);
1884 cell
->setPort("\\Y", sig_y
);
1885 cell
->set_src_attribute(src
);
1889 RTLIL::Cell
* RTLIL::Module::addConcat(RTLIL::IdString name
, RTLIL::SigSpec sig_a
, RTLIL::SigSpec sig_b
, RTLIL::SigSpec sig_y
, const std::string
&src
)
1891 RTLIL::Cell
*cell
= addCell(name
, "$concat");
1892 cell
->parameters
["\\A_WIDTH"] = sig_a
.size();
1893 cell
->parameters
["\\B_WIDTH"] = sig_b
.size();
1894 cell
->setPort("\\A", sig_a
);
1895 cell
->setPort("\\B", sig_b
);
1896 cell
->setPort("\\Y", sig_y
);
1897 cell
->set_src_attribute(src
);
1901 RTLIL::Cell
* RTLIL::Module::addLut(RTLIL::IdString name
, RTLIL::SigSpec sig_a
, RTLIL::SigSpec sig_y
, RTLIL::Const lut
, const std::string
&src
)
1903 RTLIL::Cell
*cell
= addCell(name
, "$lut");
1904 cell
->parameters
["\\LUT"] = lut
;
1905 cell
->parameters
["\\WIDTH"] = sig_a
.size();
1906 cell
->setPort("\\A", sig_a
);
1907 cell
->setPort("\\Y", sig_y
);
1908 cell
->set_src_attribute(src
);
1912 RTLIL::Cell
* RTLIL::Module::addTribuf(RTLIL::IdString name
, RTLIL::SigSpec sig_a
, RTLIL::SigSpec sig_en
, RTLIL::SigSpec sig_y
, const std::string
&src
)
1914 RTLIL::Cell
*cell
= addCell(name
, "$tribuf");
1915 cell
->parameters
["\\WIDTH"] = sig_a
.size();
1916 cell
->setPort("\\A", sig_a
);
1917 cell
->setPort("\\EN", sig_en
);
1918 cell
->setPort("\\Y", sig_y
);
1919 cell
->set_src_attribute(src
);
1923 RTLIL::Cell
* RTLIL::Module::addAssert(RTLIL::IdString name
, RTLIL::SigSpec sig_a
, RTLIL::SigSpec sig_en
, const std::string
&src
)
1925 RTLIL::Cell
*cell
= addCell(name
, "$assert");
1926 cell
->setPort("\\A", sig_a
);
1927 cell
->setPort("\\EN", sig_en
);
1928 cell
->set_src_attribute(src
);
1932 RTLIL::Cell
* RTLIL::Module::addAssume(RTLIL::IdString name
, RTLIL::SigSpec sig_a
, RTLIL::SigSpec sig_en
, const std::string
&src
)
1934 RTLIL::Cell
*cell
= addCell(name
, "$assume");
1935 cell
->setPort("\\A", sig_a
);
1936 cell
->setPort("\\EN", sig_en
);
1937 cell
->set_src_attribute(src
);
1941 RTLIL::Cell
* RTLIL::Module::addLive(RTLIL::IdString name
, RTLIL::SigSpec sig_a
, RTLIL::SigSpec sig_en
, const std::string
&src
)
1943 RTLIL::Cell
*cell
= addCell(name
, "$live");
1944 cell
->setPort("\\A", sig_a
);
1945 cell
->setPort("\\EN", sig_en
);
1946 cell
->set_src_attribute(src
);
1950 RTLIL::Cell
* RTLIL::Module::addFair(RTLIL::IdString name
, RTLIL::SigSpec sig_a
, RTLIL::SigSpec sig_en
, const std::string
&src
)
1952 RTLIL::Cell
*cell
= addCell(name
, "$fair");
1953 cell
->setPort("\\A", sig_a
);
1954 cell
->setPort("\\EN", sig_en
);
1955 cell
->set_src_attribute(src
);
1959 RTLIL::Cell
* RTLIL::Module::addCover(RTLIL::IdString name
, RTLIL::SigSpec sig_a
, RTLIL::SigSpec sig_en
, const std::string
&src
)
1961 RTLIL::Cell
*cell
= addCell(name
, "$cover");
1962 cell
->setPort("\\A", sig_a
);
1963 cell
->setPort("\\EN", sig_en
);
1964 cell
->set_src_attribute(src
);
1968 RTLIL::Cell
* RTLIL::Module::addEquiv(RTLIL::IdString name
, RTLIL::SigSpec sig_a
, RTLIL::SigSpec sig_b
, RTLIL::SigSpec sig_y
, const std::string
&src
)
1970 RTLIL::Cell
*cell
= addCell(name
, "$equiv");
1971 cell
->setPort("\\A", sig_a
);
1972 cell
->setPort("\\B", sig_b
);
1973 cell
->setPort("\\Y", sig_y
);
1974 cell
->set_src_attribute(src
);
1978 RTLIL::Cell
* RTLIL::Module::addSr(RTLIL::IdString name
, RTLIL::SigSpec sig_set
, RTLIL::SigSpec sig_clr
, RTLIL::SigSpec sig_q
, bool set_polarity
, bool clr_polarity
, const std::string
&src
)
1980 RTLIL::Cell
*cell
= addCell(name
, "$sr");
1981 cell
->parameters
["\\SET_POLARITY"] = set_polarity
;
1982 cell
->parameters
["\\CLR_POLARITY"] = clr_polarity
;
1983 cell
->parameters
["\\WIDTH"] = sig_q
.size();
1984 cell
->setPort("\\SET", sig_set
);
1985 cell
->setPort("\\CLR", sig_clr
);
1986 cell
->setPort("\\Q", sig_q
);
1987 cell
->set_src_attribute(src
);
1991 RTLIL::Cell
* RTLIL::Module::addFf(RTLIL::IdString name
, RTLIL::SigSpec sig_d
, RTLIL::SigSpec sig_q
, const std::string
&src
)
1993 RTLIL::Cell
*cell
= addCell(name
, "$ff");
1994 cell
->parameters
["\\WIDTH"] = sig_q
.size();
1995 cell
->setPort("\\D", sig_d
);
1996 cell
->setPort("\\Q", sig_q
);
1997 cell
->set_src_attribute(src
);
2001 RTLIL::Cell
* RTLIL::Module::addDff(RTLIL::IdString name
, RTLIL::SigSpec sig_clk
, RTLIL::SigSpec sig_d
, RTLIL::SigSpec sig_q
, bool clk_polarity
, const std::string
&src
)
2003 RTLIL::Cell
*cell
= addCell(name
, "$dff");
2004 cell
->parameters
["\\CLK_POLARITY"] = clk_polarity
;
2005 cell
->parameters
["\\WIDTH"] = sig_q
.size();
2006 cell
->setPort("\\CLK", sig_clk
);
2007 cell
->setPort("\\D", sig_d
);
2008 cell
->setPort("\\Q", sig_q
);
2009 cell
->set_src_attribute(src
);
2013 RTLIL::Cell
* RTLIL::Module::addDffe(RTLIL::IdString name
, RTLIL::SigSpec sig_clk
, RTLIL::SigSpec sig_en
, RTLIL::SigSpec sig_d
, RTLIL::SigSpec sig_q
, bool clk_polarity
, bool en_polarity
, const std::string
&src
)
2015 RTLIL::Cell
*cell
= addCell(name
, "$dffe");
2016 cell
->parameters
["\\CLK_POLARITY"] = clk_polarity
;
2017 cell
->parameters
["\\EN_POLARITY"] = en_polarity
;
2018 cell
->parameters
["\\WIDTH"] = sig_q
.size();
2019 cell
->setPort("\\CLK", sig_clk
);
2020 cell
->setPort("\\EN", sig_en
);
2021 cell
->setPort("\\D", sig_d
);
2022 cell
->setPort("\\Q", sig_q
);
2023 cell
->set_src_attribute(src
);
2027 RTLIL::Cell
* RTLIL::Module::addDffsr(RTLIL::IdString name
, RTLIL::SigSpec sig_clk
, RTLIL::SigSpec sig_set
, RTLIL::SigSpec sig_clr
,
2028 RTLIL::SigSpec sig_d
, RTLIL::SigSpec sig_q
, bool clk_polarity
, bool set_polarity
, bool clr_polarity
, const std::string
&src
)
2030 RTLIL::Cell
*cell
= addCell(name
, "$dffsr");
2031 cell
->parameters
["\\CLK_POLARITY"] = clk_polarity
;
2032 cell
->parameters
["\\SET_POLARITY"] = set_polarity
;
2033 cell
->parameters
["\\CLR_POLARITY"] = clr_polarity
;
2034 cell
->parameters
["\\WIDTH"] = sig_q
.size();
2035 cell
->setPort("\\CLK", sig_clk
);
2036 cell
->setPort("\\SET", sig_set
);
2037 cell
->setPort("\\CLR", sig_clr
);
2038 cell
->setPort("\\D", sig_d
);
2039 cell
->setPort("\\Q", sig_q
);
2040 cell
->set_src_attribute(src
);
2044 RTLIL::Cell
* RTLIL::Module::addAdff(RTLIL::IdString name
, RTLIL::SigSpec sig_clk
, RTLIL::SigSpec sig_arst
, RTLIL::SigSpec sig_d
, RTLIL::SigSpec sig_q
,
2045 RTLIL::Const arst_value
, bool clk_polarity
, bool arst_polarity
, const std::string
&src
)
2047 RTLIL::Cell
*cell
= addCell(name
, "$adff");
2048 cell
->parameters
["\\CLK_POLARITY"] = clk_polarity
;
2049 cell
->parameters
["\\ARST_POLARITY"] = arst_polarity
;
2050 cell
->parameters
["\\ARST_VALUE"] = arst_value
;
2051 cell
->parameters
["\\WIDTH"] = sig_q
.size();
2052 cell
->setPort("\\CLK", sig_clk
);
2053 cell
->setPort("\\ARST", sig_arst
);
2054 cell
->setPort("\\D", sig_d
);
2055 cell
->setPort("\\Q", sig_q
);
2056 cell
->set_src_attribute(src
);
2060 RTLIL::Cell
* RTLIL::Module::addDlatch(RTLIL::IdString name
, RTLIL::SigSpec sig_en
, RTLIL::SigSpec sig_d
, RTLIL::SigSpec sig_q
, bool en_polarity
, const std::string
&src
)
2062 RTLIL::Cell
*cell
= addCell(name
, "$dlatch");
2063 cell
->parameters
["\\EN_POLARITY"] = en_polarity
;
2064 cell
->parameters
["\\WIDTH"] = sig_q
.size();
2065 cell
->setPort("\\EN", sig_en
);
2066 cell
->setPort("\\D", sig_d
);
2067 cell
->setPort("\\Q", sig_q
);
2068 cell
->set_src_attribute(src
);
2072 RTLIL::Cell
* RTLIL::Module::addDlatchsr(RTLIL::IdString name
, RTLIL::SigSpec sig_en
, RTLIL::SigSpec sig_set
, RTLIL::SigSpec sig_clr
,
2073 RTLIL::SigSpec sig_d
, RTLIL::SigSpec sig_q
, bool en_polarity
, bool set_polarity
, bool clr_polarity
, const std::string
&src
)
2075 RTLIL::Cell
*cell
= addCell(name
, "$dlatchsr");
2076 cell
->parameters
["\\EN_POLARITY"] = en_polarity
;
2077 cell
->parameters
["\\SET_POLARITY"] = set_polarity
;
2078 cell
->parameters
["\\CLR_POLARITY"] = clr_polarity
;
2079 cell
->parameters
["\\WIDTH"] = sig_q
.size();
2080 cell
->setPort("\\EN", sig_en
);
2081 cell
->setPort("\\SET", sig_set
);
2082 cell
->setPort("\\CLR", sig_clr
);
2083 cell
->setPort("\\D", sig_d
);
2084 cell
->setPort("\\Q", sig_q
);
2085 cell
->set_src_attribute(src
);
2089 RTLIL::Cell
* RTLIL::Module::addFfGate(RTLIL::IdString name
, RTLIL::SigSpec sig_d
, RTLIL::SigSpec sig_q
, const std::string
&src
)
2091 RTLIL::Cell
*cell
= addCell(name
, "$_FF_");
2092 cell
->setPort("\\D", sig_d
);
2093 cell
->setPort("\\Q", sig_q
);
2094 cell
->set_src_attribute(src
);
2098 RTLIL::Cell
* RTLIL::Module::addDffGate(RTLIL::IdString name
, RTLIL::SigSpec sig_clk
, RTLIL::SigSpec sig_d
, RTLIL::SigSpec sig_q
, bool clk_polarity
, const std::string
&src
)
2100 RTLIL::Cell
*cell
= addCell(name
, stringf("$_DFF_%c_", clk_polarity
? 'P' : 'N'));
2101 cell
->setPort("\\C", sig_clk
);
2102 cell
->setPort("\\D", sig_d
);
2103 cell
->setPort("\\Q", sig_q
);
2104 cell
->set_src_attribute(src
);
2108 RTLIL::Cell
* RTLIL::Module::addDffeGate(RTLIL::IdString name
, RTLIL::SigSpec sig_clk
, RTLIL::SigSpec sig_en
, RTLIL::SigSpec sig_d
, RTLIL::SigSpec sig_q
, bool clk_polarity
, bool en_polarity
, const std::string
&src
)
2110 RTLIL::Cell
*cell
= addCell(name
, stringf("$_DFFE_%c%c_", clk_polarity
? 'P' : 'N', en_polarity
? 'P' : 'N'));
2111 cell
->setPort("\\C", sig_clk
);
2112 cell
->setPort("\\E", sig_en
);
2113 cell
->setPort("\\D", sig_d
);
2114 cell
->setPort("\\Q", sig_q
);
2115 cell
->set_src_attribute(src
);
2119 RTLIL::Cell
* RTLIL::Module::addDffsrGate(RTLIL::IdString name
, RTLIL::SigSpec sig_clk
, RTLIL::SigSpec sig_set
, RTLIL::SigSpec sig_clr
,
2120 RTLIL::SigSpec sig_d
, RTLIL::SigSpec sig_q
, bool clk_polarity
, bool set_polarity
, bool clr_polarity
, const std::string
&src
)
2122 RTLIL::Cell
*cell
= addCell(name
, stringf("$_DFFSR_%c%c%c_", clk_polarity
? 'P' : 'N', set_polarity
? 'P' : 'N', clr_polarity
? 'P' : 'N'));
2123 cell
->setPort("\\C", sig_clk
);
2124 cell
->setPort("\\S", sig_set
);
2125 cell
->setPort("\\R", sig_clr
);
2126 cell
->setPort("\\D", sig_d
);
2127 cell
->setPort("\\Q", sig_q
);
2128 cell
->set_src_attribute(src
);
2132 RTLIL::Cell
* RTLIL::Module::addAdffGate(RTLIL::IdString name
, RTLIL::SigSpec sig_clk
, RTLIL::SigSpec sig_arst
, RTLIL::SigSpec sig_d
, RTLIL::SigSpec sig_q
,
2133 bool arst_value
, bool clk_polarity
, bool arst_polarity
, const std::string
&src
)
2135 RTLIL::Cell
*cell
= addCell(name
, stringf("$_DFF_%c%c%c_", clk_polarity
? 'P' : 'N', arst_polarity
? 'P' : 'N', arst_value
? '1' : '0'));
2136 cell
->setPort("\\C", sig_clk
);
2137 cell
->setPort("\\R", sig_arst
);
2138 cell
->setPort("\\D", sig_d
);
2139 cell
->setPort("\\Q", sig_q
);
2140 cell
->set_src_attribute(src
);
2144 RTLIL::Cell
* RTLIL::Module::addDlatchGate(RTLIL::IdString name
, RTLIL::SigSpec sig_en
, RTLIL::SigSpec sig_d
, RTLIL::SigSpec sig_q
, bool en_polarity
, const std::string
&src
)
2146 RTLIL::Cell
*cell
= addCell(name
, stringf("$_DLATCH_%c_", en_polarity
? 'P' : 'N'));
2147 cell
->setPort("\\E", sig_en
);
2148 cell
->setPort("\\D", sig_d
);
2149 cell
->setPort("\\Q", sig_q
);
2150 cell
->set_src_attribute(src
);
2154 RTLIL::Cell
* RTLIL::Module::addDlatchsrGate(RTLIL::IdString name
, RTLIL::SigSpec sig_en
, RTLIL::SigSpec sig_set
, RTLIL::SigSpec sig_clr
,
2155 RTLIL::SigSpec sig_d
, RTLIL::SigSpec sig_q
, bool en_polarity
, bool set_polarity
, bool clr_polarity
, const std::string
&src
)
2157 RTLIL::Cell
*cell
= addCell(name
, stringf("$_DLATCHSR_%c%c%c_", en_polarity
? 'P' : 'N', set_polarity
? 'P' : 'N', clr_polarity
? 'P' : 'N'));
2158 cell
->setPort("\\E", sig_en
);
2159 cell
->setPort("\\S", sig_set
);
2160 cell
->setPort("\\R", sig_clr
);
2161 cell
->setPort("\\D", sig_d
);
2162 cell
->setPort("\\Q", sig_q
);
2163 cell
->set_src_attribute(src
);
2167 RTLIL::SigSpec
RTLIL::Module::Anyconst(RTLIL::IdString name
, int width
, const std::string
&src
)
2169 RTLIL::SigSpec sig
= addWire(NEW_ID
, width
);
2170 Cell
*cell
= addCell(name
, "$anyconst");
2171 cell
->setParam("\\WIDTH", width
);
2172 cell
->setPort("\\Y", sig
);
2173 cell
->set_src_attribute(src
);
2177 RTLIL::SigSpec
RTLIL::Module::Anyseq(RTLIL::IdString name
, int width
, const std::string
&src
)
2179 RTLIL::SigSpec sig
= addWire(NEW_ID
, width
);
2180 Cell
*cell
= addCell(name
, "$anyseq");
2181 cell
->setParam("\\WIDTH", width
);
2182 cell
->setPort("\\Y", sig
);
2183 cell
->set_src_attribute(src
);
2187 RTLIL::SigSpec
RTLIL::Module::Allconst(RTLIL::IdString name
, int width
, const std::string
&src
)
2189 RTLIL::SigSpec sig
= addWire(NEW_ID
, width
);
2190 Cell
*cell
= addCell(name
, "$allconst");
2191 cell
->setParam("\\WIDTH", width
);
2192 cell
->setPort("\\Y", sig
);
2193 cell
->set_src_attribute(src
);
2197 RTLIL::SigSpec
RTLIL::Module::Allseq(RTLIL::IdString name
, int width
, const std::string
&src
)
2199 RTLIL::SigSpec sig
= addWire(NEW_ID
, width
);
2200 Cell
*cell
= addCell(name
, "$allseq");
2201 cell
->setParam("\\WIDTH", width
);
2202 cell
->setPort("\\Y", sig
);
2203 cell
->set_src_attribute(src
);
2207 RTLIL::SigSpec
RTLIL::Module::Initstate(RTLIL::IdString name
, const std::string
&src
)
2209 RTLIL::SigSpec sig
= addWire(NEW_ID
);
2210 Cell
*cell
= addCell(name
, "$initstate");
2211 cell
->setPort("\\Y", sig
);
2212 cell
->set_src_attribute(src
);
2218 static unsigned int hashidx_count
= 123456789;
2219 hashidx_count
= mkhash_xorshift(hashidx_count
);
2220 hashidx_
= hashidx_count
;
2227 port_output
= false;
2231 RTLIL::Memory::Memory()
2233 static unsigned int hashidx_count
= 123456789;
2234 hashidx_count
= mkhash_xorshift(hashidx_count
);
2235 hashidx_
= hashidx_count
;
2242 RTLIL::Cell::Cell() : module(nullptr)
2244 static unsigned int hashidx_count
= 123456789;
2245 hashidx_count
= mkhash_xorshift(hashidx_count
);
2246 hashidx_
= hashidx_count
;
2248 // log("#memtrace# %p\n", this);
2252 bool RTLIL::Cell::hasPort(RTLIL::IdString portname
) const
2254 return connections_
.count(portname
) != 0;
2257 void RTLIL::Cell::unsetPort(RTLIL::IdString portname
)
2259 RTLIL::SigSpec signal
;
2260 auto conn_it
= connections_
.find(portname
);
2262 if (conn_it
!= connections_
.end())
2264 for (auto mon
: module
->monitors
)
2265 mon
->notify_connect(this, conn_it
->first
, conn_it
->second
, signal
);
2268 for (auto mon
: module
->design
->monitors
)
2269 mon
->notify_connect(this, conn_it
->first
, conn_it
->second
, signal
);
2272 log("#X# Unconnect %s.%s.%s\n", log_id(this->module
), log_id(this), log_id(portname
));
2273 log_backtrace("-X- ", yosys_xtrace
-1);
2276 connections_
.erase(conn_it
);
2280 void RTLIL::Cell::setPort(RTLIL::IdString portname
, RTLIL::SigSpec signal
)
2282 auto conn_it
= connections_
.find(portname
);
2284 if (conn_it
== connections_
.end()) {
2285 connections_
[portname
] = RTLIL::SigSpec();
2286 conn_it
= connections_
.find(portname
);
2287 log_assert(conn_it
!= connections_
.end());
2289 if (conn_it
->second
== signal
)
2292 for (auto mon
: module
->monitors
)
2293 mon
->notify_connect(this, conn_it
->first
, conn_it
->second
, signal
);
2296 for (auto mon
: module
->design
->monitors
)
2297 mon
->notify_connect(this, conn_it
->first
, conn_it
->second
, signal
);
2300 log("#X# Connect %s.%s.%s = %s (%d)\n", log_id(this->module
), log_id(this), log_id(portname
), log_signal(signal
), GetSize(signal
));
2301 log_backtrace("-X- ", yosys_xtrace
-1);
2304 conn_it
->second
= signal
;
2307 const RTLIL::SigSpec
&RTLIL::Cell::getPort(RTLIL::IdString portname
) const
2309 return connections_
.at(portname
);
2312 const dict
<RTLIL::IdString
, RTLIL::SigSpec
> &RTLIL::Cell::connections() const
2314 return connections_
;
2317 bool RTLIL::Cell::known() const
2319 if (yosys_celltypes
.cell_known(type
))
2321 if (module
&& module
->design
&& module
->design
->module(type
))
2326 bool RTLIL::Cell::input(RTLIL::IdString portname
) const
2328 if (yosys_celltypes
.cell_known(type
))
2329 return yosys_celltypes
.cell_input(type
, portname
);
2330 if (module
&& module
->design
) {
2331 RTLIL::Module
*m
= module
->design
->module(type
);
2332 RTLIL::Wire
*w
= m
? m
->wire(portname
) : nullptr;
2333 return w
&& w
->port_input
;
2338 bool RTLIL::Cell::output(RTLIL::IdString portname
) const
2340 if (yosys_celltypes
.cell_known(type
))
2341 return yosys_celltypes
.cell_output(type
, portname
);
2342 if (module
&& module
->design
) {
2343 RTLIL::Module
*m
= module
->design
->module(type
);
2344 RTLIL::Wire
*w
= m
? m
->wire(portname
) : nullptr;
2345 return w
&& w
->port_output
;
2350 bool RTLIL::Cell::hasParam(RTLIL::IdString paramname
) const
2352 return parameters
.count(paramname
) != 0;
2355 void RTLIL::Cell::unsetParam(RTLIL::IdString paramname
)
2357 parameters
.erase(paramname
);
2360 void RTLIL::Cell::setParam(RTLIL::IdString paramname
, RTLIL::Const value
)
2362 parameters
[paramname
] = value
;
2365 const RTLIL::Const
&RTLIL::Cell::getParam(RTLIL::IdString paramname
) const
2367 return parameters
.at(paramname
);
2370 void RTLIL::Cell::sort()
2372 connections_
.sort(sort_by_id_str());
2373 parameters
.sort(sort_by_id_str());
2374 attributes
.sort(sort_by_id_str());
2377 void RTLIL::Cell::check()
2380 InternalCellChecker
checker(NULL
, this);
2385 void RTLIL::Cell::fixup_parameters(bool set_a_signed
, bool set_b_signed
)
2387 if (type
.substr(0, 1) != "$" || type
.substr(0, 2) == "$_" || type
.substr(0, 8) == "$paramod" || type
.substr(0,10) == "$fmcombine" ||
2388 type
.substr(0, 9) == "$verific$" || type
.substr(0, 7) == "$array:" || type
.substr(0, 8) == "$extern:")
2391 if (type
== "$mux" || type
== "$pmux") {
2392 parameters
["\\WIDTH"] = GetSize(connections_
["\\Y"]);
2393 if (type
== "$pmux")
2394 parameters
["\\S_WIDTH"] = GetSize(connections_
["\\S"]);
2399 if (type
== "$lut" || type
== "$sop") {
2400 parameters
["\\WIDTH"] = GetSize(connections_
["\\A"]);
2404 if (type
== "$fa") {
2405 parameters
["\\WIDTH"] = GetSize(connections_
["\\Y"]);
2409 if (type
== "$lcu") {
2410 parameters
["\\WIDTH"] = GetSize(connections_
["\\CO"]);
2414 bool signedness_ab
= !type
.in("$slice", "$concat", "$macc");
2416 if (connections_
.count("\\A")) {
2417 if (signedness_ab
) {
2419 parameters
["\\A_SIGNED"] = true;
2420 else if (parameters
.count("\\A_SIGNED") == 0)
2421 parameters
["\\A_SIGNED"] = false;
2423 parameters
["\\A_WIDTH"] = GetSize(connections_
["\\A"]);
2426 if (connections_
.count("\\B")) {
2427 if (signedness_ab
) {
2429 parameters
["\\B_SIGNED"] = true;
2430 else if (parameters
.count("\\B_SIGNED") == 0)
2431 parameters
["\\B_SIGNED"] = false;
2433 parameters
["\\B_WIDTH"] = GetSize(connections_
["\\B"]);
2436 if (connections_
.count("\\Y"))
2437 parameters
["\\Y_WIDTH"] = GetSize(connections_
["\\Y"]);
2439 if (connections_
.count("\\Q"))
2440 parameters
["\\WIDTH"] = GetSize(connections_
["\\Q"]);
2445 RTLIL::SigChunk::SigChunk()
2452 RTLIL::SigChunk::SigChunk(const RTLIL::Const
&value
)
2456 width
= GetSize(data
);
2460 RTLIL::SigChunk::SigChunk(RTLIL::Wire
*wire
)
2462 log_assert(wire
!= nullptr);
2464 this->width
= wire
->width
;
2468 RTLIL::SigChunk::SigChunk(RTLIL::Wire
*wire
, int offset
, int width
)
2470 log_assert(wire
!= nullptr);
2472 this->width
= width
;
2473 this->offset
= offset
;
2476 RTLIL::SigChunk::SigChunk(const std::string
&str
)
2479 data
= RTLIL::Const(str
).bits
;
2480 width
= GetSize(data
);
2484 RTLIL::SigChunk::SigChunk(int val
, int width
)
2487 data
= RTLIL::Const(val
, width
).bits
;
2488 this->width
= GetSize(data
);
2492 RTLIL::SigChunk::SigChunk(RTLIL::State bit
, int width
)
2495 data
= RTLIL::Const(bit
, width
).bits
;
2496 this->width
= GetSize(data
);
2500 RTLIL::SigChunk::SigChunk(RTLIL::SigBit bit
)
2505 data
= RTLIL::Const(bit
.data
).bits
;
2507 offset
= bit
.offset
;
2511 RTLIL::SigChunk
RTLIL::SigChunk::extract(int offset
, int length
) const
2513 RTLIL::SigChunk ret
;
2516 ret
.offset
= this->offset
+ offset
;
2519 for (int i
= 0; i
< length
; i
++)
2520 ret
.data
.push_back(data
[offset
+i
]);
2526 bool RTLIL::SigChunk::operator <(const RTLIL::SigChunk
&other
) const
2528 if (wire
&& other
.wire
)
2529 if (wire
->name
!= other
.wire
->name
)
2530 return wire
->name
< other
.wire
->name
;
2532 if (wire
!= other
.wire
)
2533 return wire
< other
.wire
;
2535 if (offset
!= other
.offset
)
2536 return offset
< other
.offset
;
2538 if (width
!= other
.width
)
2539 return width
< other
.width
;
2541 return data
< other
.data
;
2544 bool RTLIL::SigChunk::operator ==(const RTLIL::SigChunk
&other
) const
2546 return wire
== other
.wire
&& width
== other
.width
&& offset
== other
.offset
&& data
== other
.data
;
2549 bool RTLIL::SigChunk::operator !=(const RTLIL::SigChunk
&other
) const
2556 RTLIL::SigSpec::SigSpec()
2562 RTLIL::SigSpec::SigSpec(const RTLIL::SigSpec
&other
)
2567 RTLIL::SigSpec::SigSpec(std::initializer_list
<RTLIL::SigSpec
> parts
)
2569 cover("kernel.rtlil.sigspec.init.list");
2574 std::vector
<RTLIL::SigSpec
> parts_vec(parts
.begin(), parts
.end());
2575 for (auto it
= parts_vec
.rbegin(); it
!= parts_vec
.rend(); it
++)
2579 const RTLIL::SigSpec
&RTLIL::SigSpec::operator=(const RTLIL::SigSpec
&other
)
2581 cover("kernel.rtlil.sigspec.assign");
2583 width_
= other
.width_
;
2584 hash_
= other
.hash_
;
2585 chunks_
= other
.chunks_
;
2588 if (!other
.bits_
.empty())
2590 RTLIL::SigChunk
*last
= NULL
;
2591 int last_end_offset
= 0;
2593 for (auto &bit
: other
.bits_
) {
2594 if (last
&& bit
.wire
== last
->wire
) {
2595 if (bit
.wire
== NULL
) {
2596 last
->data
.push_back(bit
.data
);
2599 } else if (last_end_offset
== bit
.offset
) {
2605 chunks_
.push_back(bit
);
2606 last
= &chunks_
.back();
2607 last_end_offset
= bit
.offset
+ 1;
2616 RTLIL::SigSpec::SigSpec(const RTLIL::Const
&value
)
2618 cover("kernel.rtlil.sigspec.init.const");
2620 chunks_
.push_back(RTLIL::SigChunk(value
));
2621 width_
= chunks_
.back().width
;
2626 RTLIL::SigSpec::SigSpec(const RTLIL::SigChunk
&chunk
)
2628 cover("kernel.rtlil.sigspec.init.chunk");
2630 chunks_
.push_back(chunk
);
2631 width_
= chunks_
.back().width
;
2636 RTLIL::SigSpec::SigSpec(RTLIL::Wire
*wire
)
2638 cover("kernel.rtlil.sigspec.init.wire");
2640 chunks_
.push_back(RTLIL::SigChunk(wire
));
2641 width_
= chunks_
.back().width
;
2646 RTLIL::SigSpec::SigSpec(RTLIL::Wire
*wire
, int offset
, int width
)
2648 cover("kernel.rtlil.sigspec.init.wire_part");
2650 chunks_
.push_back(RTLIL::SigChunk(wire
, offset
, width
));
2651 width_
= chunks_
.back().width
;
2656 RTLIL::SigSpec::SigSpec(const std::string
&str
)
2658 cover("kernel.rtlil.sigspec.init.str");
2660 chunks_
.push_back(RTLIL::SigChunk(str
));
2661 width_
= chunks_
.back().width
;
2666 RTLIL::SigSpec::SigSpec(int val
, int width
)
2668 cover("kernel.rtlil.sigspec.init.int");
2670 chunks_
.push_back(RTLIL::SigChunk(val
, width
));
2676 RTLIL::SigSpec::SigSpec(RTLIL::State bit
, int width
)
2678 cover("kernel.rtlil.sigspec.init.state");
2680 chunks_
.push_back(RTLIL::SigChunk(bit
, width
));
2686 RTLIL::SigSpec::SigSpec(RTLIL::SigBit bit
, int width
)
2688 cover("kernel.rtlil.sigspec.init.bit");
2690 if (bit
.wire
== NULL
)
2691 chunks_
.push_back(RTLIL::SigChunk(bit
.data
, width
));
2693 for (int i
= 0; i
< width
; i
++)
2694 chunks_
.push_back(bit
);
2700 RTLIL::SigSpec::SigSpec(std::vector
<RTLIL::SigChunk
> chunks
)
2702 cover("kernel.rtlil.sigspec.init.stdvec_chunks");
2706 for (auto &c
: chunks
)
2711 RTLIL::SigSpec::SigSpec(std::vector
<RTLIL::SigBit
> bits
)
2713 cover("kernel.rtlil.sigspec.init.stdvec_bits");
2717 for (auto &bit
: bits
)
2722 RTLIL::SigSpec::SigSpec(pool
<RTLIL::SigBit
> bits
)
2724 cover("kernel.rtlil.sigspec.init.pool_bits");
2728 for (auto &bit
: bits
)
2733 RTLIL::SigSpec::SigSpec(std::set
<RTLIL::SigBit
> bits
)
2735 cover("kernel.rtlil.sigspec.init.stdset_bits");
2739 for (auto &bit
: bits
)
2744 RTLIL::SigSpec::SigSpec(bool bit
)
2746 cover("kernel.rtlil.sigspec.init.bool");
2754 void RTLIL::SigSpec::pack() const
2756 RTLIL::SigSpec
*that
= (RTLIL::SigSpec
*)this;
2758 if (that
->bits_
.empty())
2761 cover("kernel.rtlil.sigspec.convert.pack");
2762 log_assert(that
->chunks_
.empty());
2764 std::vector
<RTLIL::SigBit
> old_bits
;
2765 old_bits
.swap(that
->bits_
);
2767 RTLIL::SigChunk
*last
= NULL
;
2768 int last_end_offset
= 0;
2770 for (auto &bit
: old_bits
) {
2771 if (last
&& bit
.wire
== last
->wire
) {
2772 if (bit
.wire
== NULL
) {
2773 last
->data
.push_back(bit
.data
);
2776 } else if (last_end_offset
== bit
.offset
) {
2782 that
->chunks_
.push_back(bit
);
2783 last
= &that
->chunks_
.back();
2784 last_end_offset
= bit
.offset
+ 1;
2790 void RTLIL::SigSpec::unpack() const
2792 RTLIL::SigSpec
*that
= (RTLIL::SigSpec
*)this;
2794 if (that
->chunks_
.empty())
2797 cover("kernel.rtlil.sigspec.convert.unpack");
2798 log_assert(that
->bits_
.empty());
2800 that
->bits_
.reserve(that
->width_
);
2801 for (auto &c
: that
->chunks_
)
2802 for (int i
= 0; i
< c
.width
; i
++)
2803 that
->bits_
.push_back(RTLIL::SigBit(c
, i
));
2805 that
->chunks_
.clear();
2809 void RTLIL::SigSpec::updhash() const
2811 RTLIL::SigSpec
*that
= (RTLIL::SigSpec
*)this;
2813 if (that
->hash_
!= 0)
2816 cover("kernel.rtlil.sigspec.hash");
2819 that
->hash_
= mkhash_init
;
2820 for (auto &c
: that
->chunks_
)
2821 if (c
.wire
== NULL
) {
2822 for (auto &v
: c
.data
)
2823 that
->hash_
= mkhash(that
->hash_
, v
);
2825 that
->hash_
= mkhash(that
->hash_
, c
.wire
->name
.index_
);
2826 that
->hash_
= mkhash(that
->hash_
, c
.offset
);
2827 that
->hash_
= mkhash(that
->hash_
, c
.width
);
2830 if (that
->hash_
== 0)
2834 void RTLIL::SigSpec::sort()
2837 cover("kernel.rtlil.sigspec.sort");
2838 std::sort(bits_
.begin(), bits_
.end());
2841 void RTLIL::SigSpec::sort_and_unify()
2844 cover("kernel.rtlil.sigspec.sort_and_unify");
2846 // A copy of the bits vector is used to prevent duplicating the logic from
2847 // SigSpec::SigSpec(std::vector<SigBit>). This incurrs an extra copy but
2848 // that isn't showing up as significant in profiles.
2849 std::vector
<SigBit
> unique_bits
= bits_
;
2850 std::sort(unique_bits
.begin(), unique_bits
.end());
2851 auto last
= std::unique(unique_bits
.begin(), unique_bits
.end());
2852 unique_bits
.erase(last
, unique_bits
.end());
2854 *this = unique_bits
;
2857 void RTLIL::SigSpec::replace(const RTLIL::SigSpec
&pattern
, const RTLIL::SigSpec
&with
)
2859 replace(pattern
, with
, this);
2862 void RTLIL::SigSpec::replace(const RTLIL::SigSpec
&pattern
, const RTLIL::SigSpec
&with
, RTLIL::SigSpec
*other
) const
2864 log_assert(other
!= NULL
);
2865 log_assert(width_
== other
->width_
);
2866 log_assert(pattern
.width_
== with
.width_
);
2873 for (int i
= 0; i
< GetSize(pattern
.bits_
); i
++) {
2874 if (pattern
.bits_
[i
].wire
!= NULL
) {
2875 for (int j
= 0; j
< GetSize(bits_
); j
++) {
2876 if (bits_
[j
] == pattern
.bits_
[i
]) {
2877 other
->bits_
[j
] = with
.bits_
[i
];
2886 void RTLIL::SigSpec::replace(const dict
<RTLIL::SigBit
, RTLIL::SigBit
> &rules
)
2888 replace(rules
, this);
2891 void RTLIL::SigSpec::replace(const dict
<RTLIL::SigBit
, RTLIL::SigBit
> &rules
, RTLIL::SigSpec
*other
) const
2893 cover("kernel.rtlil.sigspec.replace_dict");
2895 log_assert(other
!= NULL
);
2896 log_assert(width_
== other
->width_
);
2901 for (int i
= 0; i
< GetSize(bits_
); i
++) {
2902 auto it
= rules
.find(bits_
[i
]);
2903 if (it
!= rules
.end())
2904 other
->bits_
[i
] = it
->second
;
2910 void RTLIL::SigSpec::replace(const std::map
<RTLIL::SigBit
, RTLIL::SigBit
> &rules
)
2912 replace(rules
, this);
2915 void RTLIL::SigSpec::replace(const std::map
<RTLIL::SigBit
, RTLIL::SigBit
> &rules
, RTLIL::SigSpec
*other
) const
2917 cover("kernel.rtlil.sigspec.replace_map");
2919 log_assert(other
!= NULL
);
2920 log_assert(width_
== other
->width_
);
2925 for (int i
= 0; i
< GetSize(bits_
); i
++) {
2926 auto it
= rules
.find(bits_
[i
]);
2927 if (it
!= rules
.end())
2928 other
->bits_
[i
] = it
->second
;
2934 void RTLIL::SigSpec::remove(const RTLIL::SigSpec
&pattern
)
2936 remove2(pattern
, NULL
);
2939 void RTLIL::SigSpec::remove(const RTLIL::SigSpec
&pattern
, RTLIL::SigSpec
*other
) const
2941 RTLIL::SigSpec tmp
= *this;
2942 tmp
.remove2(pattern
, other
);
2945 void RTLIL::SigSpec::remove2(const RTLIL::SigSpec
&pattern
, RTLIL::SigSpec
*other
)
2948 cover("kernel.rtlil.sigspec.remove_other");
2950 cover("kernel.rtlil.sigspec.remove");
2953 if (other
!= NULL
) {
2954 log_assert(width_
== other
->width_
);
2958 for (int i
= GetSize(bits_
) - 1; i
>= 0; i
--)
2960 if (bits_
[i
].wire
== NULL
) continue;
2962 for (auto &pattern_chunk
: pattern
.chunks())
2963 if (bits_
[i
].wire
== pattern_chunk
.wire
&&
2964 bits_
[i
].offset
>= pattern_chunk
.offset
&&
2965 bits_
[i
].offset
< pattern_chunk
.offset
+ pattern_chunk
.width
) {
2966 bits_
.erase(bits_
.begin() + i
);
2968 if (other
!= NULL
) {
2969 other
->bits_
.erase(other
->bits_
.begin() + i
);
2979 void RTLIL::SigSpec::remove(const pool
<RTLIL::SigBit
> &pattern
)
2981 remove2(pattern
, NULL
);
2984 void RTLIL::SigSpec::remove(const pool
<RTLIL::SigBit
> &pattern
, RTLIL::SigSpec
*other
) const
2986 RTLIL::SigSpec tmp
= *this;
2987 tmp
.remove2(pattern
, other
);
2990 void RTLIL::SigSpec::remove2(const pool
<RTLIL::SigBit
> &pattern
, RTLIL::SigSpec
*other
)
2993 cover("kernel.rtlil.sigspec.remove_other");
2995 cover("kernel.rtlil.sigspec.remove");
2999 if (other
!= NULL
) {
3000 log_assert(width_
== other
->width_
);
3004 for (int i
= GetSize(bits_
) - 1; i
>= 0; i
--) {
3005 if (bits_
[i
].wire
!= NULL
&& pattern
.count(bits_
[i
])) {
3006 bits_
.erase(bits_
.begin() + i
);
3008 if (other
!= NULL
) {
3009 other
->bits_
.erase(other
->bits_
.begin() + i
);
3018 void RTLIL::SigSpec::remove2(const std::set
<RTLIL::SigBit
> &pattern
, RTLIL::SigSpec
*other
)
3021 cover("kernel.rtlil.sigspec.remove_other");
3023 cover("kernel.rtlil.sigspec.remove");
3027 if (other
!= NULL
) {
3028 log_assert(width_
== other
->width_
);
3032 for (int i
= GetSize(bits_
) - 1; i
>= 0; i
--) {
3033 if (bits_
[i
].wire
!= NULL
&& pattern
.count(bits_
[i
])) {
3034 bits_
.erase(bits_
.begin() + i
);
3036 if (other
!= NULL
) {
3037 other
->bits_
.erase(other
->bits_
.begin() + i
);
3046 RTLIL::SigSpec
RTLIL::SigSpec::extract(const RTLIL::SigSpec
&pattern
, const RTLIL::SigSpec
*other
) const
3049 cover("kernel.rtlil.sigspec.extract_other");
3051 cover("kernel.rtlil.sigspec.extract");
3053 log_assert(other
== NULL
|| width_
== other
->width_
);
3056 std::vector
<RTLIL::SigBit
> bits_match
= to_sigbit_vector();
3058 for (auto& pattern_chunk
: pattern
.chunks()) {
3060 std::vector
<RTLIL::SigBit
> bits_other
= other
->to_sigbit_vector();
3061 for (int i
= 0; i
< width_
; i
++)
3062 if (bits_match
[i
].wire
&&
3063 bits_match
[i
].wire
== pattern_chunk
.wire
&&
3064 bits_match
[i
].offset
>= pattern_chunk
.offset
&&
3065 bits_match
[i
].offset
< pattern_chunk
.offset
+ pattern_chunk
.width
)
3066 ret
.append_bit(bits_other
[i
]);
3068 for (int i
= 0; i
< width_
; i
++)
3069 if (bits_match
[i
].wire
&&
3070 bits_match
[i
].wire
== pattern_chunk
.wire
&&
3071 bits_match
[i
].offset
>= pattern_chunk
.offset
&&
3072 bits_match
[i
].offset
< pattern_chunk
.offset
+ pattern_chunk
.width
)
3073 ret
.append_bit(bits_match
[i
]);
3081 RTLIL::SigSpec
RTLIL::SigSpec::extract(const pool
<RTLIL::SigBit
> &pattern
, const RTLIL::SigSpec
*other
) const
3084 cover("kernel.rtlil.sigspec.extract_other");
3086 cover("kernel.rtlil.sigspec.extract");
3088 log_assert(other
== NULL
|| width_
== other
->width_
);
3090 std::vector
<RTLIL::SigBit
> bits_match
= to_sigbit_vector();
3094 std::vector
<RTLIL::SigBit
> bits_other
= other
->to_sigbit_vector();
3095 for (int i
= 0; i
< width_
; i
++)
3096 if (bits_match
[i
].wire
&& pattern
.count(bits_match
[i
]))
3097 ret
.append_bit(bits_other
[i
]);
3099 for (int i
= 0; i
< width_
; i
++)
3100 if (bits_match
[i
].wire
&& pattern
.count(bits_match
[i
]))
3101 ret
.append_bit(bits_match
[i
]);
3108 void RTLIL::SigSpec::replace(int offset
, const RTLIL::SigSpec
&with
)
3110 cover("kernel.rtlil.sigspec.replace_pos");
3115 log_assert(offset
>= 0);
3116 log_assert(with
.width_
>= 0);
3117 log_assert(offset
+with
.width_
<= width_
);
3119 for (int i
= 0; i
< with
.width_
; i
++)
3120 bits_
.at(offset
+ i
) = with
.bits_
.at(i
);
3125 void RTLIL::SigSpec::remove_const()
3129 cover("kernel.rtlil.sigspec.remove_const.packed");
3131 std::vector
<RTLIL::SigChunk
> new_chunks
;
3132 new_chunks
.reserve(GetSize(chunks_
));
3135 for (auto &chunk
: chunks_
)
3136 if (chunk
.wire
!= NULL
) {
3137 new_chunks
.push_back(chunk
);
3138 width_
+= chunk
.width
;
3141 chunks_
.swap(new_chunks
);
3145 cover("kernel.rtlil.sigspec.remove_const.unpacked");
3147 std::vector
<RTLIL::SigBit
> new_bits
;
3148 new_bits
.reserve(width_
);
3150 for (auto &bit
: bits_
)
3151 if (bit
.wire
!= NULL
)
3152 new_bits
.push_back(bit
);
3154 bits_
.swap(new_bits
);
3155 width_
= bits_
.size();
3161 void RTLIL::SigSpec::remove(int offset
, int length
)
3163 cover("kernel.rtlil.sigspec.remove_pos");
3167 log_assert(offset
>= 0);
3168 log_assert(length
>= 0);
3169 log_assert(offset
+ length
<= width_
);
3171 bits_
.erase(bits_
.begin() + offset
, bits_
.begin() + offset
+ length
);
3172 width_
= bits_
.size();
3177 RTLIL::SigSpec
RTLIL::SigSpec::extract(int offset
, int length
) const
3180 cover("kernel.rtlil.sigspec.extract_pos");
3181 return std::vector
<RTLIL::SigBit
>(bits_
.begin() + offset
, bits_
.begin() + offset
+ length
);
3184 void RTLIL::SigSpec::append(const RTLIL::SigSpec
&signal
)
3186 if (signal
.width_
== 0)
3194 cover("kernel.rtlil.sigspec.append");
3196 if (packed() != signal
.packed()) {
3202 for (auto &other_c
: signal
.chunks_
)
3204 auto &my_last_c
= chunks_
.back();
3205 if (my_last_c
.wire
== NULL
&& other_c
.wire
== NULL
) {
3206 auto &this_data
= my_last_c
.data
;
3207 auto &other_data
= other_c
.data
;
3208 this_data
.insert(this_data
.end(), other_data
.begin(), other_data
.end());
3209 my_last_c
.width
+= other_c
.width
;
3211 if (my_last_c
.wire
== other_c
.wire
&& my_last_c
.offset
+ my_last_c
.width
== other_c
.offset
) {
3212 my_last_c
.width
+= other_c
.width
;
3214 chunks_
.push_back(other_c
);
3217 bits_
.insert(bits_
.end(), signal
.bits_
.begin(), signal
.bits_
.end());
3219 width_
+= signal
.width_
;
3223 void RTLIL::SigSpec::append_bit(const RTLIL::SigBit
&bit
)
3227 cover("kernel.rtlil.sigspec.append_bit.packed");
3229 if (chunks_
.size() == 0)
3230 chunks_
.push_back(bit
);
3232 if (bit
.wire
== NULL
)
3233 if (chunks_
.back().wire
== NULL
) {
3234 chunks_
.back().data
.push_back(bit
.data
);
3235 chunks_
.back().width
++;
3237 chunks_
.push_back(bit
);
3239 if (chunks_
.back().wire
== bit
.wire
&& chunks_
.back().offset
+ chunks_
.back().width
== bit
.offset
)
3240 chunks_
.back().width
++;
3242 chunks_
.push_back(bit
);
3246 cover("kernel.rtlil.sigspec.append_bit.unpacked");
3247 bits_
.push_back(bit
);
3254 void RTLIL::SigSpec::extend_u0(int width
, bool is_signed
)
3256 cover("kernel.rtlil.sigspec.extend_u0");
3261 remove(width
, width_
- width
);
3263 if (width_
< width
) {
3264 RTLIL::SigBit padding
= width_
> 0 ? (*this)[width_
- 1] : RTLIL::State::Sx
;
3266 padding
= RTLIL::State::S0
;
3267 while (width_
< width
)
3273 RTLIL::SigSpec
RTLIL::SigSpec::repeat(int num
) const
3275 cover("kernel.rtlil.sigspec.repeat");
3278 for (int i
= 0; i
< num
; i
++)
3284 void RTLIL::SigSpec::check() const
3288 cover("kernel.rtlil.sigspec.check.skip");
3292 cover("kernel.rtlil.sigspec.check.packed");
3295 for (size_t i
= 0; i
< chunks_
.size(); i
++) {
3296 const RTLIL::SigChunk chunk
= chunks_
[i
];
3297 if (chunk
.wire
== NULL
) {
3299 log_assert(chunks_
[i
-1].wire
!= NULL
);
3300 log_assert(chunk
.offset
== 0);
3301 log_assert(chunk
.data
.size() == (size_t)chunk
.width
);
3303 if (i
> 0 && chunks_
[i
-1].wire
== chunk
.wire
)
3304 log_assert(chunk
.offset
!= chunks_
[i
-1].offset
+ chunks_
[i
-1].width
);
3305 log_assert(chunk
.offset
>= 0);
3306 log_assert(chunk
.width
>= 0);
3307 log_assert(chunk
.offset
+ chunk
.width
<= chunk
.wire
->width
);
3308 log_assert(chunk
.data
.size() == 0);
3312 log_assert(w
== width_
);
3313 log_assert(bits_
.empty());
3317 cover("kernel.rtlil.sigspec.check.unpacked");
3319 log_assert(width_
== GetSize(bits_
));
3320 log_assert(chunks_
.empty());
3325 bool RTLIL::SigSpec::operator <(const RTLIL::SigSpec
&other
) const
3327 cover("kernel.rtlil.sigspec.comp_lt");
3332 if (width_
!= other
.width_
)
3333 return width_
< other
.width_
;
3338 if (chunks_
.size() != other
.chunks_
.size())
3339 return chunks_
.size() < other
.chunks_
.size();
3344 if (hash_
!= other
.hash_
)
3345 return hash_
< other
.hash_
;
3347 for (size_t i
= 0; i
< chunks_
.size(); i
++)
3348 if (chunks_
[i
] != other
.chunks_
[i
]) {
3349 cover("kernel.rtlil.sigspec.comp_lt.hash_collision");
3350 return chunks_
[i
] < other
.chunks_
[i
];
3353 cover("kernel.rtlil.sigspec.comp_lt.equal");
3357 bool RTLIL::SigSpec::operator ==(const RTLIL::SigSpec
&other
) const
3359 cover("kernel.rtlil.sigspec.comp_eq");
3364 if (width_
!= other
.width_
)
3370 if (chunks_
.size() != chunks_
.size())
3376 if (hash_
!= other
.hash_
)
3379 for (size_t i
= 0; i
< chunks_
.size(); i
++)
3380 if (chunks_
[i
] != other
.chunks_
[i
]) {
3381 cover("kernel.rtlil.sigspec.comp_eq.hash_collision");
3385 cover("kernel.rtlil.sigspec.comp_eq.equal");
3389 bool RTLIL::SigSpec::is_wire() const
3391 cover("kernel.rtlil.sigspec.is_wire");
3394 return GetSize(chunks_
) == 1 && chunks_
[0].wire
&& chunks_
[0].wire
->width
== width_
;
3397 bool RTLIL::SigSpec::is_chunk() const
3399 cover("kernel.rtlil.sigspec.is_chunk");
3402 return GetSize(chunks_
) == 1;
3405 bool RTLIL::SigSpec::is_fully_const() const
3407 cover("kernel.rtlil.sigspec.is_fully_const");
3410 for (auto it
= chunks_
.begin(); it
!= chunks_
.end(); it
++)
3411 if (it
->width
> 0 && it
->wire
!= NULL
)
3416 bool RTLIL::SigSpec::is_fully_zero() const
3418 cover("kernel.rtlil.sigspec.is_fully_zero");
3421 for (auto it
= chunks_
.begin(); it
!= chunks_
.end(); it
++) {
3422 if (it
->width
> 0 && it
->wire
!= NULL
)
3424 for (size_t i
= 0; i
< it
->data
.size(); i
++)
3425 if (it
->data
[i
] != RTLIL::State::S0
)
3431 bool RTLIL::SigSpec::is_fully_ones() const
3433 cover("kernel.rtlil.sigspec.is_fully_ones");
3436 for (auto it
= chunks_
.begin(); it
!= chunks_
.end(); it
++) {
3437 if (it
->width
> 0 && it
->wire
!= NULL
)
3439 for (size_t i
= 0; i
< it
->data
.size(); i
++)
3440 if (it
->data
[i
] != RTLIL::State::S1
)
3446 bool RTLIL::SigSpec::is_fully_def() const
3448 cover("kernel.rtlil.sigspec.is_fully_def");
3451 for (auto it
= chunks_
.begin(); it
!= chunks_
.end(); it
++) {
3452 if (it
->width
> 0 && it
->wire
!= NULL
)
3454 for (size_t i
= 0; i
< it
->data
.size(); i
++)
3455 if (it
->data
[i
] != RTLIL::State::S0
&& it
->data
[i
] != RTLIL::State::S1
)
3461 bool RTLIL::SigSpec::is_fully_undef() const
3463 cover("kernel.rtlil.sigspec.is_fully_undef");
3466 for (auto it
= chunks_
.begin(); it
!= chunks_
.end(); it
++) {
3467 if (it
->width
> 0 && it
->wire
!= NULL
)
3469 for (size_t i
= 0; i
< it
->data
.size(); i
++)
3470 if (it
->data
[i
] != RTLIL::State::Sx
&& it
->data
[i
] != RTLIL::State::Sz
)
3476 bool RTLIL::SigSpec::has_const() const
3478 cover("kernel.rtlil.sigspec.has_const");
3481 for (auto it
= chunks_
.begin(); it
!= chunks_
.end(); it
++)
3482 if (it
->width
> 0 && it
->wire
== NULL
)
3487 bool RTLIL::SigSpec::has_marked_bits() const
3489 cover("kernel.rtlil.sigspec.has_marked_bits");
3492 for (auto it
= chunks_
.begin(); it
!= chunks_
.end(); it
++)
3493 if (it
->width
> 0 && it
->wire
== NULL
) {
3494 for (size_t i
= 0; i
< it
->data
.size(); i
++)
3495 if (it
->data
[i
] == RTLIL::State::Sm
)
3501 bool RTLIL::SigSpec::as_bool() const
3503 cover("kernel.rtlil.sigspec.as_bool");
3506 log_assert(is_fully_const() && GetSize(chunks_
) <= 1);
3508 return RTLIL::Const(chunks_
[0].data
).as_bool();
3512 int RTLIL::SigSpec::as_int(bool is_signed
) const
3514 cover("kernel.rtlil.sigspec.as_int");
3517 log_assert(is_fully_const() && GetSize(chunks_
) <= 1);
3519 return RTLIL::Const(chunks_
[0].data
).as_int(is_signed
);
3523 std::string
RTLIL::SigSpec::as_string() const
3525 cover("kernel.rtlil.sigspec.as_string");
3529 for (size_t i
= chunks_
.size(); i
> 0; i
--) {
3530 const RTLIL::SigChunk
&chunk
= chunks_
[i
-1];
3531 if (chunk
.wire
!= NULL
)
3532 for (int j
= 0; j
< chunk
.width
; j
++)
3535 str
+= RTLIL::Const(chunk
.data
).as_string();
3540 RTLIL::Const
RTLIL::SigSpec::as_const() const
3542 cover("kernel.rtlil.sigspec.as_const");
3545 log_assert(is_fully_const() && GetSize(chunks_
) <= 1);
3547 return chunks_
[0].data
;
3548 return RTLIL::Const();
3551 RTLIL::Wire
*RTLIL::SigSpec::as_wire() const
3553 cover("kernel.rtlil.sigspec.as_wire");
3556 log_assert(is_wire());
3557 return chunks_
[0].wire
;
3560 RTLIL::SigChunk
RTLIL::SigSpec::as_chunk() const
3562 cover("kernel.rtlil.sigspec.as_chunk");
3565 log_assert(is_chunk());
3569 RTLIL::SigBit
RTLIL::SigSpec::as_bit() const
3571 cover("kernel.rtlil.sigspec.as_bit");
3573 log_assert(width_
== 1);
3575 return RTLIL::SigBit(*chunks_
.begin());
3580 bool RTLIL::SigSpec::match(std::string pattern
) const
3582 cover("kernel.rtlil.sigspec.match");
3585 std::string str
= as_string();
3586 log_assert(pattern
.size() == str
.size());
3588 for (size_t i
= 0; i
< pattern
.size(); i
++) {
3589 if (pattern
[i
] == ' ')
3591 if (pattern
[i
] == '*') {
3592 if (str
[i
] != 'z' && str
[i
] != 'x')
3596 if (pattern
[i
] != str
[i
])
3603 std::set
<RTLIL::SigBit
> RTLIL::SigSpec::to_sigbit_set() const
3605 cover("kernel.rtlil.sigspec.to_sigbit_set");
3608 std::set
<RTLIL::SigBit
> sigbits
;
3609 for (auto &c
: chunks_
)
3610 for (int i
= 0; i
< c
.width
; i
++)
3611 sigbits
.insert(RTLIL::SigBit(c
, i
));
3615 pool
<RTLIL::SigBit
> RTLIL::SigSpec::to_sigbit_pool() const
3617 cover("kernel.rtlil.sigspec.to_sigbit_pool");
3620 pool
<RTLIL::SigBit
> sigbits
;
3621 for (auto &c
: chunks_
)
3622 for (int i
= 0; i
< c
.width
; i
++)
3623 sigbits
.insert(RTLIL::SigBit(c
, i
));
3627 std::vector
<RTLIL::SigBit
> RTLIL::SigSpec::to_sigbit_vector() const
3629 cover("kernel.rtlil.sigspec.to_sigbit_vector");
3635 std::map
<RTLIL::SigBit
, RTLIL::SigBit
> RTLIL::SigSpec::to_sigbit_map(const RTLIL::SigSpec
&other
) const
3637 cover("kernel.rtlil.sigspec.to_sigbit_map");
3642 log_assert(width_
== other
.width_
);
3644 std::map
<RTLIL::SigBit
, RTLIL::SigBit
> new_map
;
3645 for (int i
= 0; i
< width_
; i
++)
3646 new_map
[bits_
[i
]] = other
.bits_
[i
];
3651 dict
<RTLIL::SigBit
, RTLIL::SigBit
> RTLIL::SigSpec::to_sigbit_dict(const RTLIL::SigSpec
&other
) const
3653 cover("kernel.rtlil.sigspec.to_sigbit_dict");
3658 log_assert(width_
== other
.width_
);
3660 dict
<RTLIL::SigBit
, RTLIL::SigBit
> new_map
;
3661 for (int i
= 0; i
< width_
; i
++)
3662 new_map
[bits_
[i
]] = other
.bits_
[i
];
3667 static void sigspec_parse_split(std::vector
<std::string
> &tokens
, const std::string
&text
, char sep
)
3669 size_t start
= 0, end
= 0;
3670 while ((end
= text
.find(sep
, start
)) != std::string::npos
) {
3671 tokens
.push_back(text
.substr(start
, end
- start
));
3674 tokens
.push_back(text
.substr(start
));
3677 static int sigspec_parse_get_dummy_line_num()
3682 bool RTLIL::SigSpec::parse(RTLIL::SigSpec
&sig
, RTLIL::Module
*module
, std::string str
)
3684 cover("kernel.rtlil.sigspec.parse");
3686 AST::current_filename
= "input";
3687 AST::use_internal_line_num();
3688 AST::set_line_num(0);
3690 std::vector
<std::string
> tokens
;
3691 sigspec_parse_split(tokens
, str
, ',');
3693 sig
= RTLIL::SigSpec();
3694 for (int tokidx
= int(tokens
.size())-1; tokidx
>= 0; tokidx
--)
3696 std::string netname
= tokens
[tokidx
];
3697 std::string indices
;
3699 if (netname
.size() == 0)
3702 if (('0' <= netname
[0] && netname
[0] <= '9') || netname
[0] == '\'') {
3703 cover("kernel.rtlil.sigspec.parse.const");
3704 AST::get_line_num
= sigspec_parse_get_dummy_line_num
;
3705 AST::AstNode
*ast
= VERILOG_FRONTEND::const2ast(netname
);
3708 sig
.append(RTLIL::Const(ast
->bits
));
3716 cover("kernel.rtlil.sigspec.parse.net");
3718 if (netname
[0] != '$' && netname
[0] != '\\')
3719 netname
= "\\" + netname
;
3721 if (module
->wires_
.count(netname
) == 0) {
3722 size_t indices_pos
= netname
.size()-1;
3723 if (indices_pos
> 2 && netname
[indices_pos
] == ']')
3726 while (indices_pos
> 0 && ('0' <= netname
[indices_pos
] && netname
[indices_pos
] <= '9')) indices_pos
--;
3727 if (indices_pos
> 0 && netname
[indices_pos
] == ':') {
3729 while (indices_pos
> 0 && ('0' <= netname
[indices_pos
] && netname
[indices_pos
] <= '9')) indices_pos
--;
3731 if (indices_pos
> 0 && netname
[indices_pos
] == '[') {
3732 indices
= netname
.substr(indices_pos
);
3733 netname
= netname
.substr(0, indices_pos
);
3738 if (module
->wires_
.count(netname
) == 0)
3741 RTLIL::Wire
*wire
= module
->wires_
.at(netname
);
3742 if (!indices
.empty()) {
3743 std::vector
<std::string
> index_tokens
;
3744 sigspec_parse_split(index_tokens
, indices
.substr(1, indices
.size()-2), ':');
3745 if (index_tokens
.size() == 1) {
3746 cover("kernel.rtlil.sigspec.parse.bit_sel");
3747 int a
= atoi(index_tokens
.at(0).c_str());
3748 if (a
< 0 || a
>= wire
->width
)
3750 sig
.append(RTLIL::SigSpec(wire
, a
));
3752 cover("kernel.rtlil.sigspec.parse.part_sel");
3753 int a
= atoi(index_tokens
.at(0).c_str());
3754 int b
= atoi(index_tokens
.at(1).c_str());
3759 if (a
< 0 || a
>= wire
->width
)
3761 if (b
< 0 || b
>= wire
->width
)
3763 sig
.append(RTLIL::SigSpec(wire
, a
, b
-a
+1));
3772 bool RTLIL::SigSpec::parse_sel(RTLIL::SigSpec
&sig
, RTLIL::Design
*design
, RTLIL::Module
*module
, std::string str
)
3774 if (str
.empty() || str
[0] != '@')
3775 return parse(sig
, module
, str
);
3777 cover("kernel.rtlil.sigspec.parse.sel");
3779 str
= RTLIL::escape_id(str
.substr(1));
3780 if (design
->selection_vars
.count(str
) == 0)
3783 sig
= RTLIL::SigSpec();
3784 RTLIL::Selection
&sel
= design
->selection_vars
.at(str
);
3785 for (auto &it
: module
->wires_
)
3786 if (sel
.selected_member(module
->name
, it
.first
))
3787 sig
.append(it
.second
);
3792 bool RTLIL::SigSpec::parse_rhs(const RTLIL::SigSpec
&lhs
, RTLIL::SigSpec
&sig
, RTLIL::Module
*module
, std::string str
)
3795 cover("kernel.rtlil.sigspec.parse.rhs_zeros");
3796 sig
= RTLIL::SigSpec(RTLIL::State::S0
, lhs
.width_
);
3801 cover("kernel.rtlil.sigspec.parse.rhs_ones");
3802 sig
= RTLIL::SigSpec(RTLIL::State::S1
, lhs
.width_
);
3806 if (lhs
.chunks_
.size() == 1) {
3807 char *p
= (char*)str
.c_str(), *endptr
;
3808 long int val
= strtol(p
, &endptr
, 10);
3809 if (endptr
&& endptr
!= p
&& *endptr
== 0) {
3810 sig
= RTLIL::SigSpec(val
, lhs
.width_
);
3811 cover("kernel.rtlil.sigspec.parse.rhs_dec");
3816 return parse(sig
, module
, str
);
3819 RTLIL::CaseRule::~CaseRule()
3821 for (auto it
= switches
.begin(); it
!= switches
.end(); it
++)
3825 bool RTLIL::CaseRule::empty() const
3827 return actions
.empty() && switches
.empty();
3830 RTLIL::CaseRule
*RTLIL::CaseRule::clone() const
3832 RTLIL::CaseRule
*new_caserule
= new RTLIL::CaseRule
;
3833 new_caserule
->compare
= compare
;
3834 new_caserule
->actions
= actions
;
3835 for (auto &it
: switches
)
3836 new_caserule
->switches
.push_back(it
->clone());
3837 return new_caserule
;
3840 RTLIL::SwitchRule::~SwitchRule()
3842 for (auto it
= cases
.begin(); it
!= cases
.end(); it
++)
3846 bool RTLIL::SwitchRule::empty() const
3848 return cases
.empty();
3851 RTLIL::SwitchRule
*RTLIL::SwitchRule::clone() const
3853 RTLIL::SwitchRule
*new_switchrule
= new RTLIL::SwitchRule
;
3854 new_switchrule
->signal
= signal
;
3855 new_switchrule
->attributes
= attributes
;
3856 for (auto &it
: cases
)
3857 new_switchrule
->cases
.push_back(it
->clone());
3858 return new_switchrule
;
3862 RTLIL::SyncRule
*RTLIL::SyncRule::clone() const
3864 RTLIL::SyncRule
*new_syncrule
= new RTLIL::SyncRule
;
3865 new_syncrule
->type
= type
;
3866 new_syncrule
->signal
= signal
;
3867 new_syncrule
->actions
= actions
;
3868 return new_syncrule
;
3871 RTLIL::Process::~Process()
3873 for (auto it
= syncs
.begin(); it
!= syncs
.end(); it
++)
3877 RTLIL::Process
*RTLIL::Process::clone() const
3879 RTLIL::Process
*new_proc
= new RTLIL::Process
;
3881 new_proc
->name
= name
;
3882 new_proc
->attributes
= attributes
;
3884 RTLIL::CaseRule
*rc_ptr
= root_case
.clone();
3885 new_proc
->root_case
= *rc_ptr
;
3886 rc_ptr
->switches
.clear();
3889 for (auto &it
: syncs
)
3890 new_proc
->syncs
.push_back(it
->clone());