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Merge pull request #969 from YosysHQ/clifford/pmgenstuff
[yosys.git] / kernel / rtlil.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 #include "kernel/yosys.h"
21 #include "kernel/macc.h"
22 #include "kernel/celltypes.h"
23 #include "frontends/verilog/verilog_frontend.h"
24 #include "backends/ilang/ilang_backend.h"
25
26 #include <string.h>
27 #include <algorithm>
28
29 YOSYS_NAMESPACE_BEGIN
30
31 RTLIL::IdString::destruct_guard_t RTLIL::IdString::destruct_guard;
32 std::vector<int> RTLIL::IdString::global_refcount_storage_;
33 std::vector<char*> RTLIL::IdString::global_id_storage_;
34 dict<char*, int, hash_cstr_ops> RTLIL::IdString::global_id_index_;
35 std::vector<int> RTLIL::IdString::global_free_idx_list_;
36 int RTLIL::IdString::last_created_idx_[8];
37 int RTLIL::IdString::last_created_idx_ptr_;
38
39 RTLIL::Const::Const()
40 {
41 flags = RTLIL::CONST_FLAG_NONE;
42 }
43
44 RTLIL::Const::Const(std::string str)
45 {
46 flags = RTLIL::CONST_FLAG_STRING;
47 for (int i = str.size()-1; i >= 0; i--) {
48 unsigned char ch = str[i];
49 for (int j = 0; j < 8; j++) {
50 bits.push_back((ch & 1) != 0 ? RTLIL::S1 : RTLIL::S0);
51 ch = ch >> 1;
52 }
53 }
54 }
55
56 RTLIL::Const::Const(int val, int width)
57 {
58 flags = RTLIL::CONST_FLAG_NONE;
59 for (int i = 0; i < width; i++) {
60 bits.push_back((val & 1) != 0 ? RTLIL::S1 : RTLIL::S0);
61 val = val >> 1;
62 }
63 }
64
65 RTLIL::Const::Const(RTLIL::State bit, int width)
66 {
67 flags = RTLIL::CONST_FLAG_NONE;
68 for (int i = 0; i < width; i++)
69 bits.push_back(bit);
70 }
71
72 RTLIL::Const::Const(const std::vector<bool> &bits)
73 {
74 flags = RTLIL::CONST_FLAG_NONE;
75 for (auto b : bits)
76 this->bits.push_back(b ? RTLIL::S1 : RTLIL::S0);
77 }
78
79 RTLIL::Const::Const(const RTLIL::Const &c)
80 {
81 flags = c.flags;
82 for (auto b : c.bits)
83 this->bits.push_back(b);
84 }
85
86 bool RTLIL::Const::operator <(const RTLIL::Const &other) const
87 {
88 if (bits.size() != other.bits.size())
89 return bits.size() < other.bits.size();
90 for (size_t i = 0; i < bits.size(); i++)
91 if (bits[i] != other.bits[i])
92 return bits[i] < other.bits[i];
93 return false;
94 }
95
96 bool RTLIL::Const::operator ==(const RTLIL::Const &other) const
97 {
98 return bits == other.bits;
99 }
100
101 bool RTLIL::Const::operator !=(const RTLIL::Const &other) const
102 {
103 return bits != other.bits;
104 }
105
106 bool RTLIL::Const::as_bool() const
107 {
108 for (size_t i = 0; i < bits.size(); i++)
109 if (bits[i] == RTLIL::S1)
110 return true;
111 return false;
112 }
113
114 int RTLIL::Const::as_int(bool is_signed) const
115 {
116 int32_t ret = 0;
117 for (size_t i = 0; i < bits.size() && i < 32; i++)
118 if (bits[i] == RTLIL::S1)
119 ret |= 1 << i;
120 if (is_signed && bits.back() == RTLIL::S1)
121 for (size_t i = bits.size(); i < 32; i++)
122 ret |= 1 << i;
123 return ret;
124 }
125
126 std::string RTLIL::Const::as_string() const
127 {
128 std::string ret;
129 for (size_t i = bits.size(); i > 0; i--)
130 switch (bits[i-1]) {
131 case S0: ret += "0"; break;
132 case S1: ret += "1"; break;
133 case Sx: ret += "x"; break;
134 case Sz: ret += "z"; break;
135 case Sa: ret += "-"; break;
136 case Sm: ret += "m"; break;
137 }
138 return ret;
139 }
140
141 RTLIL::Const RTLIL::Const::from_string(std::string str)
142 {
143 Const c;
144 for (auto it = str.rbegin(); it != str.rend(); it++)
145 switch (*it) {
146 case '0': c.bits.push_back(State::S0); break;
147 case '1': c.bits.push_back(State::S1); break;
148 case 'x': c.bits.push_back(State::Sx); break;
149 case 'z': c.bits.push_back(State::Sz); break;
150 case 'm': c.bits.push_back(State::Sm); break;
151 default: c.bits.push_back(State::Sa);
152 }
153 return c;
154 }
155
156 std::string RTLIL::Const::decode_string() const
157 {
158 std::string string;
159 std::vector<char> string_chars;
160 for (int i = 0; i < int (bits.size()); i += 8) {
161 char ch = 0;
162 for (int j = 0; j < 8 && i + j < int (bits.size()); j++)
163 if (bits[i + j] == RTLIL::State::S1)
164 ch |= 1 << j;
165 if (ch != 0)
166 string_chars.push_back(ch);
167 }
168 for (int i = int (string_chars.size()) - 1; i >= 0; i--)
169 string += string_chars[i];
170 return string;
171 }
172
173 bool RTLIL::Const::is_fully_zero() const
174 {
175 cover("kernel.rtlil.const.is_fully_zero");
176
177 for (auto bit : bits)
178 if (bit != RTLIL::State::S0)
179 return false;
180
181 return true;
182 }
183
184 bool RTLIL::Const::is_fully_ones() const
185 {
186 cover("kernel.rtlil.const.is_fully_ones");
187
188 for (auto bit : bits)
189 if (bit != RTLIL::State::S1)
190 return false;
191
192 return true;
193 }
194
195 bool RTLIL::Const::is_fully_def() const
196 {
197 cover("kernel.rtlil.const.is_fully_def");
198
199 for (auto bit : bits)
200 if (bit != RTLIL::State::S0 && bit != RTLIL::State::S1)
201 return false;
202
203 return true;
204 }
205
206 bool RTLIL::Const::is_fully_undef() const
207 {
208 cover("kernel.rtlil.const.is_fully_undef");
209
210 for (auto bit : bits)
211 if (bit != RTLIL::State::Sx && bit != RTLIL::State::Sz)
212 return false;
213
214 return true;
215 }
216
217 void RTLIL::AttrObject::set_bool_attribute(RTLIL::IdString id, bool value)
218 {
219 if (value)
220 attributes[id] = RTLIL::Const(1);
221 else if (attributes.count(id))
222 attributes.erase(id);
223 }
224
225 bool RTLIL::AttrObject::get_bool_attribute(RTLIL::IdString id) const
226 {
227 if (attributes.count(id) == 0)
228 return false;
229 return attributes.at(id).as_bool();
230 }
231
232 void RTLIL::AttrObject::set_strpool_attribute(RTLIL::IdString id, const pool<string> &data)
233 {
234 string attrval;
235 for (auto &s : data) {
236 if (!attrval.empty())
237 attrval += "|";
238 attrval += s;
239 }
240 attributes[id] = RTLIL::Const(attrval);
241 }
242
243 void RTLIL::AttrObject::add_strpool_attribute(RTLIL::IdString id, const pool<string> &data)
244 {
245 pool<string> union_data = get_strpool_attribute(id);
246 union_data.insert(data.begin(), data.end());
247 if (!union_data.empty())
248 set_strpool_attribute(id, union_data);
249 }
250
251 pool<string> RTLIL::AttrObject::get_strpool_attribute(RTLIL::IdString id) const
252 {
253 pool<string> data;
254 if (attributes.count(id) != 0)
255 for (auto s : split_tokens(attributes.at(id).decode_string(), "|"))
256 data.insert(s);
257 return data;
258 }
259
260 void RTLIL::AttrObject::set_src_attribute(const std::string &src)
261 {
262 if (src.empty())
263 attributes.erase("\\src");
264 else
265 attributes["\\src"] = src;
266 }
267
268 std::string RTLIL::AttrObject::get_src_attribute() const
269 {
270 std::string src;
271 if (attributes.count("\\src"))
272 src = attributes.at("\\src").decode_string();
273 return src;
274 }
275
276 bool RTLIL::Selection::selected_module(RTLIL::IdString mod_name) const
277 {
278 if (full_selection)
279 return true;
280 if (selected_modules.count(mod_name) > 0)
281 return true;
282 if (selected_members.count(mod_name) > 0)
283 return true;
284 return false;
285 }
286
287 bool RTLIL::Selection::selected_whole_module(RTLIL::IdString mod_name) const
288 {
289 if (full_selection)
290 return true;
291 if (selected_modules.count(mod_name) > 0)
292 return true;
293 return false;
294 }
295
296 bool RTLIL::Selection::selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const
297 {
298 if (full_selection)
299 return true;
300 if (selected_modules.count(mod_name) > 0)
301 return true;
302 if (selected_members.count(mod_name) > 0)
303 if (selected_members.at(mod_name).count(memb_name) > 0)
304 return true;
305 return false;
306 }
307
308 void RTLIL::Selection::optimize(RTLIL::Design *design)
309 {
310 if (full_selection) {
311 selected_modules.clear();
312 selected_members.clear();
313 return;
314 }
315
316 std::vector<RTLIL::IdString> del_list, add_list;
317
318 del_list.clear();
319 for (auto mod_name : selected_modules) {
320 if (design->modules_.count(mod_name) == 0)
321 del_list.push_back(mod_name);
322 selected_members.erase(mod_name);
323 }
324 for (auto mod_name : del_list)
325 selected_modules.erase(mod_name);
326
327 del_list.clear();
328 for (auto &it : selected_members)
329 if (design->modules_.count(it.first) == 0)
330 del_list.push_back(it.first);
331 for (auto mod_name : del_list)
332 selected_members.erase(mod_name);
333
334 for (auto &it : selected_members) {
335 del_list.clear();
336 for (auto memb_name : it.second)
337 if (design->modules_[it.first]->count_id(memb_name) == 0)
338 del_list.push_back(memb_name);
339 for (auto memb_name : del_list)
340 it.second.erase(memb_name);
341 }
342
343 del_list.clear();
344 add_list.clear();
345 for (auto &it : selected_members)
346 if (it.second.size() == 0)
347 del_list.push_back(it.first);
348 else if (it.second.size() == design->modules_[it.first]->wires_.size() + design->modules_[it.first]->memories.size() +
349 design->modules_[it.first]->cells_.size() + design->modules_[it.first]->processes.size())
350 add_list.push_back(it.first);
351 for (auto mod_name : del_list)
352 selected_members.erase(mod_name);
353 for (auto mod_name : add_list) {
354 selected_members.erase(mod_name);
355 selected_modules.insert(mod_name);
356 }
357
358 if (selected_modules.size() == design->modules_.size()) {
359 full_selection = true;
360 selected_modules.clear();
361 selected_members.clear();
362 }
363 }
364
365 RTLIL::Design::Design()
366 {
367 static unsigned int hashidx_count = 123456789;
368 hashidx_count = mkhash_xorshift(hashidx_count);
369 hashidx_ = hashidx_count;
370
371 refcount_modules_ = 0;
372 selection_stack.push_back(RTLIL::Selection());
373
374 #ifdef WITH_PYTHON
375 RTLIL::Design::get_all_designs()->insert(std::pair<unsigned int, RTLIL::Design*>(hashidx_, this));
376 #endif
377 }
378
379 RTLIL::Design::~Design()
380 {
381 for (auto it = modules_.begin(); it != modules_.end(); ++it)
382 delete it->second;
383 for (auto n : verilog_packages)
384 delete n;
385 for (auto n : verilog_globals)
386 delete n;
387 #ifdef WITH_PYTHON
388 RTLIL::Design::get_all_designs()->erase(hashidx_);
389 #endif
390 }
391
392 #ifdef WITH_PYTHON
393 static std::map<unsigned int, RTLIL::Design*> all_designs;
394 std::map<unsigned int, RTLIL::Design*> *RTLIL::Design::get_all_designs(void)
395 {
396 return &all_designs;
397 }
398 #endif
399
400 RTLIL::ObjRange<RTLIL::Module*> RTLIL::Design::modules()
401 {
402 return RTLIL::ObjRange<RTLIL::Module*>(&modules_, &refcount_modules_);
403 }
404
405 RTLIL::Module *RTLIL::Design::module(RTLIL::IdString name)
406 {
407 return modules_.count(name) ? modules_.at(name) : NULL;
408 }
409
410 RTLIL::Module *RTLIL::Design::top_module()
411 {
412 RTLIL::Module *module = nullptr;
413 int module_count = 0;
414
415 for (auto mod : selected_modules()) {
416 if (mod->get_bool_attribute("\\top"))
417 return mod;
418 module_count++;
419 module = mod;
420 }
421
422 return module_count == 1 ? module : nullptr;
423 }
424
425 void RTLIL::Design::add(RTLIL::Module *module)
426 {
427 log_assert(modules_.count(module->name) == 0);
428 log_assert(refcount_modules_ == 0);
429 modules_[module->name] = module;
430 module->design = this;
431
432 for (auto mon : monitors)
433 mon->notify_module_add(module);
434
435 if (yosys_xtrace) {
436 log("#X# New Module: %s\n", log_id(module));
437 log_backtrace("-X- ", yosys_xtrace-1);
438 }
439 }
440
441 RTLIL::Module *RTLIL::Design::addModule(RTLIL::IdString name)
442 {
443 log_assert(modules_.count(name) == 0);
444 log_assert(refcount_modules_ == 0);
445
446 RTLIL::Module *module = new RTLIL::Module;
447 modules_[name] = module;
448 module->design = this;
449 module->name = name;
450
451 for (auto mon : monitors)
452 mon->notify_module_add(module);
453
454 if (yosys_xtrace) {
455 log("#X# New Module: %s\n", log_id(module));
456 log_backtrace("-X- ", yosys_xtrace-1);
457 }
458
459 return module;
460 }
461
462 void RTLIL::Design::scratchpad_unset(std::string varname)
463 {
464 scratchpad.erase(varname);
465 }
466
467 void RTLIL::Design::scratchpad_set_int(std::string varname, int value)
468 {
469 scratchpad[varname] = stringf("%d", value);
470 }
471
472 void RTLIL::Design::scratchpad_set_bool(std::string varname, bool value)
473 {
474 scratchpad[varname] = value ? "true" : "false";
475 }
476
477 void RTLIL::Design::scratchpad_set_string(std::string varname, std::string value)
478 {
479 scratchpad[varname] = value;
480 }
481
482 int RTLIL::Design::scratchpad_get_int(std::string varname, int default_value) const
483 {
484 if (scratchpad.count(varname) == 0)
485 return default_value;
486
487 std::string str = scratchpad.at(varname);
488
489 if (str == "0" || str == "false")
490 return 0;
491
492 if (str == "1" || str == "true")
493 return 1;
494
495 char *endptr = nullptr;
496 long int parsed_value = strtol(str.c_str(), &endptr, 10);
497 return *endptr ? default_value : parsed_value;
498 }
499
500 bool RTLIL::Design::scratchpad_get_bool(std::string varname, bool default_value) const
501 {
502 if (scratchpad.count(varname) == 0)
503 return default_value;
504
505 std::string str = scratchpad.at(varname);
506
507 if (str == "0" || str == "false")
508 return false;
509
510 if (str == "1" || str == "true")
511 return true;
512
513 return default_value;
514 }
515
516 std::string RTLIL::Design::scratchpad_get_string(std::string varname, std::string default_value) const
517 {
518 if (scratchpad.count(varname) == 0)
519 return default_value;
520 return scratchpad.at(varname);
521 }
522
523 void RTLIL::Design::remove(RTLIL::Module *module)
524 {
525 for (auto mon : monitors)
526 mon->notify_module_del(module);
527
528 if (yosys_xtrace) {
529 log("#X# Remove Module: %s\n", log_id(module));
530 log_backtrace("-X- ", yosys_xtrace-1);
531 }
532
533 log_assert(modules_.at(module->name) == module);
534 modules_.erase(module->name);
535 delete module;
536 }
537
538 void RTLIL::Design::rename(RTLIL::Module *module, RTLIL::IdString new_name)
539 {
540 modules_.erase(module->name);
541 module->name = new_name;
542 add(module);
543 }
544
545 void RTLIL::Design::sort()
546 {
547 scratchpad.sort();
548 modules_.sort(sort_by_id_str());
549 for (auto &it : modules_)
550 it.second->sort();
551 }
552
553 void RTLIL::Design::check()
554 {
555 #ifndef NDEBUG
556 for (auto &it : modules_) {
557 log_assert(this == it.second->design);
558 log_assert(it.first == it.second->name);
559 log_assert(!it.first.empty());
560 it.second->check();
561 }
562 #endif
563 }
564
565 void RTLIL::Design::optimize()
566 {
567 for (auto &it : modules_)
568 it.second->optimize();
569 for (auto &it : selection_stack)
570 it.optimize(this);
571 for (auto &it : selection_vars)
572 it.second.optimize(this);
573 }
574
575 bool RTLIL::Design::selected_module(RTLIL::IdString mod_name) const
576 {
577 if (!selected_active_module.empty() && mod_name != selected_active_module)
578 return false;
579 if (selection_stack.size() == 0)
580 return true;
581 return selection_stack.back().selected_module(mod_name);
582 }
583
584 bool RTLIL::Design::selected_whole_module(RTLIL::IdString mod_name) const
585 {
586 if (!selected_active_module.empty() && mod_name != selected_active_module)
587 return false;
588 if (selection_stack.size() == 0)
589 return true;
590 return selection_stack.back().selected_whole_module(mod_name);
591 }
592
593 bool RTLIL::Design::selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const
594 {
595 if (!selected_active_module.empty() && mod_name != selected_active_module)
596 return false;
597 if (selection_stack.size() == 0)
598 return true;
599 return selection_stack.back().selected_member(mod_name, memb_name);
600 }
601
602 bool RTLIL::Design::selected_module(RTLIL::Module *mod) const
603 {
604 return selected_module(mod->name);
605 }
606
607 bool RTLIL::Design::selected_whole_module(RTLIL::Module *mod) const
608 {
609 return selected_whole_module(mod->name);
610 }
611
612 std::vector<RTLIL::Module*> RTLIL::Design::selected_modules() const
613 {
614 std::vector<RTLIL::Module*> result;
615 result.reserve(modules_.size());
616 for (auto &it : modules_)
617 if (selected_module(it.first) && !it.second->get_blackbox_attribute())
618 result.push_back(it.second);
619 return result;
620 }
621
622 std::vector<RTLIL::Module*> RTLIL::Design::selected_whole_modules() const
623 {
624 std::vector<RTLIL::Module*> result;
625 result.reserve(modules_.size());
626 for (auto &it : modules_)
627 if (selected_whole_module(it.first) && !it.second->get_blackbox_attribute())
628 result.push_back(it.second);
629 return result;
630 }
631
632 std::vector<RTLIL::Module*> RTLIL::Design::selected_whole_modules_warn() const
633 {
634 std::vector<RTLIL::Module*> result;
635 result.reserve(modules_.size());
636 for (auto &it : modules_)
637 if (it.second->get_blackbox_attribute())
638 continue;
639 else if (selected_whole_module(it.first))
640 result.push_back(it.second);
641 else if (selected_module(it.first))
642 log_warning("Ignoring partially selected module %s.\n", log_id(it.first));
643 return result;
644 }
645
646 RTLIL::Module::Module()
647 {
648 static unsigned int hashidx_count = 123456789;
649 hashidx_count = mkhash_xorshift(hashidx_count);
650 hashidx_ = hashidx_count;
651
652 design = nullptr;
653 refcount_wires_ = 0;
654 refcount_cells_ = 0;
655
656 #ifdef WITH_PYTHON
657 RTLIL::Module::get_all_modules()->insert(std::pair<unsigned int, RTLIL::Module*>(hashidx_, this));
658 #endif
659 }
660
661 RTLIL::Module::~Module()
662 {
663 for (auto it = wires_.begin(); it != wires_.end(); ++it)
664 delete it->second;
665 for (auto it = memories.begin(); it != memories.end(); ++it)
666 delete it->second;
667 for (auto it = cells_.begin(); it != cells_.end(); ++it)
668 delete it->second;
669 for (auto it = processes.begin(); it != processes.end(); ++it)
670 delete it->second;
671 #ifdef WITH_PYTHON
672 RTLIL::Module::get_all_modules()->erase(hashidx_);
673 #endif
674 }
675
676 #ifdef WITH_PYTHON
677 static std::map<unsigned int, RTLIL::Module*> all_modules;
678 std::map<unsigned int, RTLIL::Module*> *RTLIL::Module::get_all_modules(void)
679 {
680 return &all_modules;
681 }
682 #endif
683
684 void RTLIL::Module::makeblackbox()
685 {
686 pool<RTLIL::Wire*> delwires;
687
688 for (auto it = wires_.begin(); it != wires_.end(); ++it)
689 if (!it->second->port_input && !it->second->port_output)
690 delwires.insert(it->second);
691
692 for (auto it = memories.begin(); it != memories.end(); ++it)
693 delete it->second;
694 memories.clear();
695
696 for (auto it = cells_.begin(); it != cells_.end(); ++it)
697 delete it->second;
698 cells_.clear();
699
700 for (auto it = processes.begin(); it != processes.end(); ++it)
701 delete it->second;
702 processes.clear();
703
704 remove(delwires);
705 set_bool_attribute("\\blackbox");
706 }
707
708 void RTLIL::Module::reprocess_module(RTLIL::Design *, dict<RTLIL::IdString, RTLIL::Module *>)
709 {
710 log_error("Cannot reprocess_module module `%s' !\n", id2cstr(name));
711 }
712
713 RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, dict<RTLIL::IdString, RTLIL::Const>, bool mayfail)
714 {
715 if (mayfail)
716 return RTLIL::IdString();
717 log_error("Module `%s' is used with parameters but is not parametric!\n", id2cstr(name));
718 }
719
720
721 RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, dict<RTLIL::IdString, RTLIL::Const>, dict<RTLIL::IdString, RTLIL::Module*>, dict<RTLIL::IdString, RTLIL::IdString>, bool mayfail)
722 {
723 if (mayfail)
724 return RTLIL::IdString();
725 log_error("Module `%s' is used with parameters but is not parametric!\n", id2cstr(name));
726 }
727
728 size_t RTLIL::Module::count_id(RTLIL::IdString id)
729 {
730 return wires_.count(id) + memories.count(id) + cells_.count(id) + processes.count(id);
731 }
732
733 #ifndef NDEBUG
734 namespace {
735 struct InternalCellChecker
736 {
737 RTLIL::Module *module;
738 RTLIL::Cell *cell;
739 pool<RTLIL::IdString> expected_params, expected_ports;
740
741 InternalCellChecker(RTLIL::Module *module, RTLIL::Cell *cell) : module(module), cell(cell) { }
742
743 void error(int linenr)
744 {
745 std::stringstream buf;
746 ILANG_BACKEND::dump_cell(buf, " ", cell);
747
748 log_error("Found error in internal cell %s%s%s (%s) at %s:%d:\n%s",
749 module ? module->name.c_str() : "", module ? "." : "",
750 cell->name.c_str(), cell->type.c_str(), __FILE__, linenr, buf.str().c_str());
751 }
752
753 int param(const char *name)
754 {
755 if (cell->parameters.count(name) == 0)
756 error(__LINE__);
757 expected_params.insert(name);
758 return cell->parameters.at(name).as_int();
759 }
760
761 int param_bool(const char *name)
762 {
763 int v = param(name);
764 if (cell->parameters.at(name).bits.size() > 32)
765 error(__LINE__);
766 if (v != 0 && v != 1)
767 error(__LINE__);
768 return v;
769 }
770
771 void param_bits(const char *name, int width)
772 {
773 param(name);
774 if (int(cell->parameters.at(name).bits.size()) != width)
775 error(__LINE__);
776 }
777
778 void port(const char *name, int width)
779 {
780 if (!cell->hasPort(name))
781 error(__LINE__);
782 if (cell->getPort(name).size() != width)
783 error(__LINE__);
784 expected_ports.insert(name);
785 }
786
787 void check_expected(bool check_matched_sign = true)
788 {
789 for (auto &para : cell->parameters)
790 if (expected_params.count(para.first) == 0)
791 error(__LINE__);
792 for (auto &conn : cell->connections())
793 if (expected_ports.count(conn.first) == 0)
794 error(__LINE__);
795
796 if (expected_params.count("\\A_SIGNED") != 0 && expected_params.count("\\B_SIGNED") && check_matched_sign) {
797 bool a_is_signed = param("\\A_SIGNED") != 0;
798 bool b_is_signed = param("\\B_SIGNED") != 0;
799 if (a_is_signed != b_is_signed)
800 error(__LINE__);
801 }
802 }
803
804 void check_gate(const char *ports)
805 {
806 if (cell->parameters.size() != 0)
807 error(__LINE__);
808
809 for (const char *p = ports; *p; p++) {
810 char portname[3] = { '\\', *p, 0 };
811 if (!cell->hasPort(portname))
812 error(__LINE__);
813 if (cell->getPort(portname).size() != 1)
814 error(__LINE__);
815 }
816
817 for (auto &conn : cell->connections()) {
818 if (conn.first.size() != 2 || conn.first[0] != '\\')
819 error(__LINE__);
820 if (strchr(ports, conn.first[1]) == NULL)
821 error(__LINE__);
822 }
823 }
824
825 void check()
826 {
827 if (cell->type.substr(0, 1) != "$" || cell->type.substr(0, 3) == "$__" || cell->type.substr(0, 8) == "$paramod" || cell->type.substr(0,10) == "$fmcombine" ||
828 cell->type.substr(0, 9) == "$verific$" || cell->type.substr(0, 7) == "$array:" || cell->type.substr(0, 8) == "$extern:")
829 return;
830
831 if (cell->type.in("$not", "$pos", "$neg")) {
832 param_bool("\\A_SIGNED");
833 port("\\A", param("\\A_WIDTH"));
834 port("\\Y", param("\\Y_WIDTH"));
835 check_expected();
836 return;
837 }
838
839 if (cell->type.in("$and", "$or", "$xor", "$xnor")) {
840 param_bool("\\A_SIGNED");
841 param_bool("\\B_SIGNED");
842 port("\\A", param("\\A_WIDTH"));
843 port("\\B", param("\\B_WIDTH"));
844 port("\\Y", param("\\Y_WIDTH"));
845 check_expected();
846 return;
847 }
848
849 if (cell->type.in("$reduce_and", "$reduce_or", "$reduce_xor", "$reduce_xnor", "$reduce_bool")) {
850 param_bool("\\A_SIGNED");
851 port("\\A", param("\\A_WIDTH"));
852 port("\\Y", param("\\Y_WIDTH"));
853 check_expected();
854 return;
855 }
856
857 if (cell->type.in("$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx")) {
858 param_bool("\\A_SIGNED");
859 param_bool("\\B_SIGNED");
860 port("\\A", param("\\A_WIDTH"));
861 port("\\B", param("\\B_WIDTH"));
862 port("\\Y", param("\\Y_WIDTH"));
863 check_expected(false);
864 return;
865 }
866
867 if (cell->type.in("$lt", "$le", "$eq", "$ne", "$eqx", "$nex", "$ge", "$gt")) {
868 param_bool("\\A_SIGNED");
869 param_bool("\\B_SIGNED");
870 port("\\A", param("\\A_WIDTH"));
871 port("\\B", param("\\B_WIDTH"));
872 port("\\Y", param("\\Y_WIDTH"));
873 check_expected();
874 return;
875 }
876
877 if (cell->type.in("$add", "$sub", "$mul", "$div", "$mod", "$pow")) {
878 param_bool("\\A_SIGNED");
879 param_bool("\\B_SIGNED");
880 port("\\A", param("\\A_WIDTH"));
881 port("\\B", param("\\B_WIDTH"));
882 port("\\Y", param("\\Y_WIDTH"));
883 check_expected(cell->type != "$pow");
884 return;
885 }
886
887 if (cell->type == "$fa") {
888 port("\\A", param("\\WIDTH"));
889 port("\\B", param("\\WIDTH"));
890 port("\\C", param("\\WIDTH"));
891 port("\\X", param("\\WIDTH"));
892 port("\\Y", param("\\WIDTH"));
893 check_expected();
894 return;
895 }
896
897 if (cell->type == "$lcu") {
898 port("\\P", param("\\WIDTH"));
899 port("\\G", param("\\WIDTH"));
900 port("\\CI", 1);
901 port("\\CO", param("\\WIDTH"));
902 check_expected();
903 return;
904 }
905
906 if (cell->type == "$alu") {
907 param_bool("\\A_SIGNED");
908 param_bool("\\B_SIGNED");
909 port("\\A", param("\\A_WIDTH"));
910 port("\\B", param("\\B_WIDTH"));
911 port("\\CI", 1);
912 port("\\BI", 1);
913 port("\\X", param("\\Y_WIDTH"));
914 port("\\Y", param("\\Y_WIDTH"));
915 port("\\CO", param("\\Y_WIDTH"));
916 check_expected();
917 return;
918 }
919
920 if (cell->type == "$macc") {
921 param("\\CONFIG");
922 param("\\CONFIG_WIDTH");
923 port("\\A", param("\\A_WIDTH"));
924 port("\\B", param("\\B_WIDTH"));
925 port("\\Y", param("\\Y_WIDTH"));
926 check_expected();
927 Macc().from_cell(cell);
928 return;
929 }
930
931 if (cell->type == "$logic_not") {
932 param_bool("\\A_SIGNED");
933 port("\\A", param("\\A_WIDTH"));
934 port("\\Y", param("\\Y_WIDTH"));
935 check_expected();
936 return;
937 }
938
939 if (cell->type == "$logic_and" || cell->type == "$logic_or") {
940 param_bool("\\A_SIGNED");
941 param_bool("\\B_SIGNED");
942 port("\\A", param("\\A_WIDTH"));
943 port("\\B", param("\\B_WIDTH"));
944 port("\\Y", param("\\Y_WIDTH"));
945 check_expected(false);
946 return;
947 }
948
949 if (cell->type == "$slice") {
950 param("\\OFFSET");
951 port("\\A", param("\\A_WIDTH"));
952 port("\\Y", param("\\Y_WIDTH"));
953 if (param("\\OFFSET") + param("\\Y_WIDTH") > param("\\A_WIDTH"))
954 error(__LINE__);
955 check_expected();
956 return;
957 }
958
959 if (cell->type == "$concat") {
960 port("\\A", param("\\A_WIDTH"));
961 port("\\B", param("\\B_WIDTH"));
962 port("\\Y", param("\\A_WIDTH") + param("\\B_WIDTH"));
963 check_expected();
964 return;
965 }
966
967 if (cell->type == "$mux") {
968 port("\\A", param("\\WIDTH"));
969 port("\\B", param("\\WIDTH"));
970 port("\\S", 1);
971 port("\\Y", param("\\WIDTH"));
972 check_expected();
973 return;
974 }
975
976 if (cell->type == "$pmux") {
977 port("\\A", param("\\WIDTH"));
978 port("\\B", param("\\WIDTH") * param("\\S_WIDTH"));
979 port("\\S", param("\\S_WIDTH"));
980 port("\\Y", param("\\WIDTH"));
981 check_expected();
982 return;
983 }
984
985 if (cell->type == "$lut") {
986 param("\\LUT");
987 port("\\A", param("\\WIDTH"));
988 port("\\Y", 1);
989 check_expected();
990 return;
991 }
992
993 if (cell->type == "$sop") {
994 param("\\DEPTH");
995 param("\\TABLE");
996 port("\\A", param("\\WIDTH"));
997 port("\\Y", 1);
998 check_expected();
999 return;
1000 }
1001
1002 if (cell->type == "$sr") {
1003 param_bool("\\SET_POLARITY");
1004 param_bool("\\CLR_POLARITY");
1005 port("\\SET", param("\\WIDTH"));
1006 port("\\CLR", param("\\WIDTH"));
1007 port("\\Q", param("\\WIDTH"));
1008 check_expected();
1009 return;
1010 }
1011
1012 if (cell->type == "$ff") {
1013 port("\\D", param("\\WIDTH"));
1014 port("\\Q", param("\\WIDTH"));
1015 check_expected();
1016 return;
1017 }
1018
1019 if (cell->type == "$dff") {
1020 param_bool("\\CLK_POLARITY");
1021 port("\\CLK", 1);
1022 port("\\D", param("\\WIDTH"));
1023 port("\\Q", param("\\WIDTH"));
1024 check_expected();
1025 return;
1026 }
1027
1028 if (cell->type == "$dffe") {
1029 param_bool("\\CLK_POLARITY");
1030 param_bool("\\EN_POLARITY");
1031 port("\\CLK", 1);
1032 port("\\EN", 1);
1033 port("\\D", param("\\WIDTH"));
1034 port("\\Q", param("\\WIDTH"));
1035 check_expected();
1036 return;
1037 }
1038
1039 if (cell->type == "$dffsr") {
1040 param_bool("\\CLK_POLARITY");
1041 param_bool("\\SET_POLARITY");
1042 param_bool("\\CLR_POLARITY");
1043 port("\\CLK", 1);
1044 port("\\SET", param("\\WIDTH"));
1045 port("\\CLR", param("\\WIDTH"));
1046 port("\\D", param("\\WIDTH"));
1047 port("\\Q", param("\\WIDTH"));
1048 check_expected();
1049 return;
1050 }
1051
1052 if (cell->type == "$adff") {
1053 param_bool("\\CLK_POLARITY");
1054 param_bool("\\ARST_POLARITY");
1055 param_bits("\\ARST_VALUE", param("\\WIDTH"));
1056 port("\\CLK", 1);
1057 port("\\ARST", 1);
1058 port("\\D", param("\\WIDTH"));
1059 port("\\Q", param("\\WIDTH"));
1060 check_expected();
1061 return;
1062 }
1063
1064 if (cell->type == "$dlatch") {
1065 param_bool("\\EN_POLARITY");
1066 port("\\EN", 1);
1067 port("\\D", param("\\WIDTH"));
1068 port("\\Q", param("\\WIDTH"));
1069 check_expected();
1070 return;
1071 }
1072
1073 if (cell->type == "$dlatchsr") {
1074 param_bool("\\EN_POLARITY");
1075 param_bool("\\SET_POLARITY");
1076 param_bool("\\CLR_POLARITY");
1077 port("\\EN", 1);
1078 port("\\SET", param("\\WIDTH"));
1079 port("\\CLR", param("\\WIDTH"));
1080 port("\\D", param("\\WIDTH"));
1081 port("\\Q", param("\\WIDTH"));
1082 check_expected();
1083 return;
1084 }
1085
1086 if (cell->type == "$fsm") {
1087 param("\\NAME");
1088 param_bool("\\CLK_POLARITY");
1089 param_bool("\\ARST_POLARITY");
1090 param("\\STATE_BITS");
1091 param("\\STATE_NUM");
1092 param("\\STATE_NUM_LOG2");
1093 param("\\STATE_RST");
1094 param_bits("\\STATE_TABLE", param("\\STATE_BITS") * param("\\STATE_NUM"));
1095 param("\\TRANS_NUM");
1096 param_bits("\\TRANS_TABLE", param("\\TRANS_NUM") * (2*param("\\STATE_NUM_LOG2") + param("\\CTRL_IN_WIDTH") + param("\\CTRL_OUT_WIDTH")));
1097 port("\\CLK", 1);
1098 port("\\ARST", 1);
1099 port("\\CTRL_IN", param("\\CTRL_IN_WIDTH"));
1100 port("\\CTRL_OUT", param("\\CTRL_OUT_WIDTH"));
1101 check_expected();
1102 return;
1103 }
1104
1105 if (cell->type == "$memrd") {
1106 param("\\MEMID");
1107 param_bool("\\CLK_ENABLE");
1108 param_bool("\\CLK_POLARITY");
1109 param_bool("\\TRANSPARENT");
1110 port("\\CLK", 1);
1111 port("\\EN", 1);
1112 port("\\ADDR", param("\\ABITS"));
1113 port("\\DATA", param("\\WIDTH"));
1114 check_expected();
1115 return;
1116 }
1117
1118 if (cell->type == "$memwr") {
1119 param("\\MEMID");
1120 param_bool("\\CLK_ENABLE");
1121 param_bool("\\CLK_POLARITY");
1122 param("\\PRIORITY");
1123 port("\\CLK", 1);
1124 port("\\EN", param("\\WIDTH"));
1125 port("\\ADDR", param("\\ABITS"));
1126 port("\\DATA", param("\\WIDTH"));
1127 check_expected();
1128 return;
1129 }
1130
1131 if (cell->type == "$meminit") {
1132 param("\\MEMID");
1133 param("\\PRIORITY");
1134 port("\\ADDR", param("\\ABITS"));
1135 port("\\DATA", param("\\WIDTH") * param("\\WORDS"));
1136 check_expected();
1137 return;
1138 }
1139
1140 if (cell->type == "$mem") {
1141 param("\\MEMID");
1142 param("\\SIZE");
1143 param("\\OFFSET");
1144 param("\\INIT");
1145 param_bits("\\RD_CLK_ENABLE", max(1, param("\\RD_PORTS")));
1146 param_bits("\\RD_CLK_POLARITY", max(1, param("\\RD_PORTS")));
1147 param_bits("\\RD_TRANSPARENT", max(1, param("\\RD_PORTS")));
1148 param_bits("\\WR_CLK_ENABLE", max(1, param("\\WR_PORTS")));
1149 param_bits("\\WR_CLK_POLARITY", max(1, param("\\WR_PORTS")));
1150 port("\\RD_CLK", param("\\RD_PORTS"));
1151 port("\\RD_EN", param("\\RD_PORTS"));
1152 port("\\RD_ADDR", param("\\RD_PORTS") * param("\\ABITS"));
1153 port("\\RD_DATA", param("\\RD_PORTS") * param("\\WIDTH"));
1154 port("\\WR_CLK", param("\\WR_PORTS"));
1155 port("\\WR_EN", param("\\WR_PORTS") * param("\\WIDTH"));
1156 port("\\WR_ADDR", param("\\WR_PORTS") * param("\\ABITS"));
1157 port("\\WR_DATA", param("\\WR_PORTS") * param("\\WIDTH"));
1158 check_expected();
1159 return;
1160 }
1161
1162 if (cell->type == "$tribuf") {
1163 port("\\A", param("\\WIDTH"));
1164 port("\\Y", param("\\WIDTH"));
1165 port("\\EN", 1);
1166 check_expected();
1167 return;
1168 }
1169
1170 if (cell->type.in("$assert", "$assume", "$live", "$fair", "$cover")) {
1171 port("\\A", 1);
1172 port("\\EN", 1);
1173 check_expected();
1174 return;
1175 }
1176
1177 if (cell->type == "$initstate") {
1178 port("\\Y", 1);
1179 check_expected();
1180 return;
1181 }
1182
1183 if (cell->type.in("$anyconst", "$anyseq", "$allconst", "$allseq")) {
1184 port("\\Y", param("\\WIDTH"));
1185 check_expected();
1186 return;
1187 }
1188
1189 if (cell->type == "$equiv") {
1190 port("\\A", 1);
1191 port("\\B", 1);
1192 port("\\Y", 1);
1193 check_expected();
1194 return;
1195 }
1196
1197 if (cell->type == "$_BUF_") { check_gate("AY"); return; }
1198 if (cell->type == "$_NOT_") { check_gate("AY"); return; }
1199 if (cell->type == "$_AND_") { check_gate("ABY"); return; }
1200 if (cell->type == "$_NAND_") { check_gate("ABY"); return; }
1201 if (cell->type == "$_OR_") { check_gate("ABY"); return; }
1202 if (cell->type == "$_NOR_") { check_gate("ABY"); return; }
1203 if (cell->type == "$_XOR_") { check_gate("ABY"); return; }
1204 if (cell->type == "$_XNOR_") { check_gate("ABY"); return; }
1205 if (cell->type == "$_ANDNOT_") { check_gate("ABY"); return; }
1206 if (cell->type == "$_ORNOT_") { check_gate("ABY"); return; }
1207 if (cell->type == "$_MUX_") { check_gate("ABSY"); return; }
1208 if (cell->type == "$_AOI3_") { check_gate("ABCY"); return; }
1209 if (cell->type == "$_OAI3_") { check_gate("ABCY"); return; }
1210 if (cell->type == "$_AOI4_") { check_gate("ABCDY"); return; }
1211 if (cell->type == "$_OAI4_") { check_gate("ABCDY"); return; }
1212
1213 if (cell->type == "$_TBUF_") { check_gate("AYE"); return; }
1214
1215 if (cell->type == "$_MUX4_") { check_gate("ABCDSTY"); return; }
1216 if (cell->type == "$_MUX8_") { check_gate("ABCDEFGHSTUY"); return; }
1217 if (cell->type == "$_MUX16_") { check_gate("ABCDEFGHIJKLMNOPSTUVY"); return; }
1218
1219 if (cell->type == "$_SR_NN_") { check_gate("SRQ"); return; }
1220 if (cell->type == "$_SR_NP_") { check_gate("SRQ"); return; }
1221 if (cell->type == "$_SR_PN_") { check_gate("SRQ"); return; }
1222 if (cell->type == "$_SR_PP_") { check_gate("SRQ"); return; }
1223
1224 if (cell->type == "$_FF_") { check_gate("DQ"); return; }
1225 if (cell->type == "$_DFF_N_") { check_gate("DQC"); return; }
1226 if (cell->type == "$_DFF_P_") { check_gate("DQC"); return; }
1227
1228 if (cell->type == "$_DFFE_NN_") { check_gate("DQCE"); return; }
1229 if (cell->type == "$_DFFE_NP_") { check_gate("DQCE"); return; }
1230 if (cell->type == "$_DFFE_PN_") { check_gate("DQCE"); return; }
1231 if (cell->type == "$_DFFE_PP_") { check_gate("DQCE"); return; }
1232
1233 if (cell->type == "$_DFF_NN0_") { check_gate("DQCR"); return; }
1234 if (cell->type == "$_DFF_NN1_") { check_gate("DQCR"); return; }
1235 if (cell->type == "$_DFF_NP0_") { check_gate("DQCR"); return; }
1236 if (cell->type == "$_DFF_NP1_") { check_gate("DQCR"); return; }
1237 if (cell->type == "$_DFF_PN0_") { check_gate("DQCR"); return; }
1238 if (cell->type == "$_DFF_PN1_") { check_gate("DQCR"); return; }
1239 if (cell->type == "$_DFF_PP0_") { check_gate("DQCR"); return; }
1240 if (cell->type == "$_DFF_PP1_") { check_gate("DQCR"); return; }
1241
1242 if (cell->type == "$_DFFSR_NNN_") { check_gate("CSRDQ"); return; }
1243 if (cell->type == "$_DFFSR_NNP_") { check_gate("CSRDQ"); return; }
1244 if (cell->type == "$_DFFSR_NPN_") { check_gate("CSRDQ"); return; }
1245 if (cell->type == "$_DFFSR_NPP_") { check_gate("CSRDQ"); return; }
1246 if (cell->type == "$_DFFSR_PNN_") { check_gate("CSRDQ"); return; }
1247 if (cell->type == "$_DFFSR_PNP_") { check_gate("CSRDQ"); return; }
1248 if (cell->type == "$_DFFSR_PPN_") { check_gate("CSRDQ"); return; }
1249 if (cell->type == "$_DFFSR_PPP_") { check_gate("CSRDQ"); return; }
1250
1251 if (cell->type == "$_DLATCH_N_") { check_gate("EDQ"); return; }
1252 if (cell->type == "$_DLATCH_P_") { check_gate("EDQ"); return; }
1253
1254 if (cell->type == "$_DLATCHSR_NNN_") { check_gate("ESRDQ"); return; }
1255 if (cell->type == "$_DLATCHSR_NNP_") { check_gate("ESRDQ"); return; }
1256 if (cell->type == "$_DLATCHSR_NPN_") { check_gate("ESRDQ"); return; }
1257 if (cell->type == "$_DLATCHSR_NPP_") { check_gate("ESRDQ"); return; }
1258 if (cell->type == "$_DLATCHSR_PNN_") { check_gate("ESRDQ"); return; }
1259 if (cell->type == "$_DLATCHSR_PNP_") { check_gate("ESRDQ"); return; }
1260 if (cell->type == "$_DLATCHSR_PPN_") { check_gate("ESRDQ"); return; }
1261 if (cell->type == "$_DLATCHSR_PPP_") { check_gate("ESRDQ"); return; }
1262
1263 error(__LINE__);
1264 }
1265 };
1266 }
1267 #endif
1268
1269 void RTLIL::Module::sort()
1270 {
1271 wires_.sort(sort_by_id_str());
1272 cells_.sort(sort_by_id_str());
1273 avail_parameters.sort(sort_by_id_str());
1274 memories.sort(sort_by_id_str());
1275 processes.sort(sort_by_id_str());
1276 for (auto &it : cells_)
1277 it.second->sort();
1278 for (auto &it : wires_)
1279 it.second->attributes.sort(sort_by_id_str());
1280 for (auto &it : memories)
1281 it.second->attributes.sort(sort_by_id_str());
1282 }
1283
1284 void RTLIL::Module::check()
1285 {
1286 #ifndef NDEBUG
1287 std::vector<bool> ports_declared;
1288 for (auto &it : wires_) {
1289 log_assert(this == it.second->module);
1290 log_assert(it.first == it.second->name);
1291 log_assert(!it.first.empty());
1292 log_assert(it.second->width >= 0);
1293 log_assert(it.second->port_id >= 0);
1294 for (auto &it2 : it.second->attributes)
1295 log_assert(!it2.first.empty());
1296 if (it.second->port_id) {
1297 log_assert(GetSize(ports) >= it.second->port_id);
1298 log_assert(ports.at(it.second->port_id-1) == it.first);
1299 log_assert(it.second->port_input || it.second->port_output);
1300 if (GetSize(ports_declared) < it.second->port_id)
1301 ports_declared.resize(it.second->port_id);
1302 log_assert(ports_declared[it.second->port_id-1] == false);
1303 ports_declared[it.second->port_id-1] = true;
1304 } else
1305 log_assert(!it.second->port_input && !it.second->port_output);
1306 }
1307 for (auto port_declared : ports_declared)
1308 log_assert(port_declared == true);
1309 log_assert(GetSize(ports) == GetSize(ports_declared));
1310
1311 for (auto &it : memories) {
1312 log_assert(it.first == it.second->name);
1313 log_assert(!it.first.empty());
1314 log_assert(it.second->width >= 0);
1315 log_assert(it.second->size >= 0);
1316 for (auto &it2 : it.second->attributes)
1317 log_assert(!it2.first.empty());
1318 }
1319
1320 for (auto &it : cells_) {
1321 log_assert(this == it.second->module);
1322 log_assert(it.first == it.second->name);
1323 log_assert(!it.first.empty());
1324 log_assert(!it.second->type.empty());
1325 for (auto &it2 : it.second->connections()) {
1326 log_assert(!it2.first.empty());
1327 it2.second.check();
1328 }
1329 for (auto &it2 : it.second->attributes)
1330 log_assert(!it2.first.empty());
1331 for (auto &it2 : it.second->parameters)
1332 log_assert(!it2.first.empty());
1333 InternalCellChecker checker(this, it.second);
1334 checker.check();
1335 }
1336
1337 for (auto &it : processes) {
1338 log_assert(it.first == it.second->name);
1339 log_assert(!it.first.empty());
1340 // FIXME: More checks here..
1341 }
1342
1343 for (auto &it : connections_) {
1344 log_assert(it.first.size() == it.second.size());
1345 log_assert(!it.first.has_const());
1346 it.first.check();
1347 it.second.check();
1348 }
1349
1350 for (auto &it : attributes)
1351 log_assert(!it.first.empty());
1352 #endif
1353 }
1354
1355 void RTLIL::Module::optimize()
1356 {
1357 }
1358
1359 void RTLIL::Module::cloneInto(RTLIL::Module *new_mod) const
1360 {
1361 log_assert(new_mod->refcount_wires_ == 0);
1362 log_assert(new_mod->refcount_cells_ == 0);
1363
1364 new_mod->avail_parameters = avail_parameters;
1365
1366 for (auto &conn : connections_)
1367 new_mod->connect(conn);
1368
1369 for (auto &attr : attributes)
1370 new_mod->attributes[attr.first] = attr.second;
1371
1372 for (auto &it : wires_)
1373 new_mod->addWire(it.first, it.second);
1374
1375 for (auto &it : memories)
1376 new_mod->memories[it.first] = new RTLIL::Memory(*it.second);
1377
1378 for (auto &it : cells_)
1379 new_mod->addCell(it.first, it.second);
1380
1381 for (auto &it : processes)
1382 new_mod->processes[it.first] = it.second->clone();
1383
1384 struct RewriteSigSpecWorker
1385 {
1386 RTLIL::Module *mod;
1387 void operator()(RTLIL::SigSpec &sig)
1388 {
1389 std::vector<RTLIL::SigChunk> chunks = sig.chunks();
1390 for (auto &c : chunks)
1391 if (c.wire != NULL)
1392 c.wire = mod->wires_.at(c.wire->name);
1393 sig = chunks;
1394 }
1395 };
1396
1397 RewriteSigSpecWorker rewriteSigSpecWorker;
1398 rewriteSigSpecWorker.mod = new_mod;
1399 new_mod->rewrite_sigspecs(rewriteSigSpecWorker);
1400 new_mod->fixup_ports();
1401 }
1402
1403 RTLIL::Module *RTLIL::Module::clone() const
1404 {
1405 RTLIL::Module *new_mod = new RTLIL::Module;
1406 new_mod->name = name;
1407 cloneInto(new_mod);
1408 return new_mod;
1409 }
1410
1411 bool RTLIL::Module::has_memories() const
1412 {
1413 return !memories.empty();
1414 }
1415
1416 bool RTLIL::Module::has_processes() const
1417 {
1418 return !processes.empty();
1419 }
1420
1421 bool RTLIL::Module::has_memories_warn() const
1422 {
1423 if (!memories.empty())
1424 log_warning("Ignoring module %s because it contains memories (run 'memory' command first).\n", log_id(this));
1425 return !memories.empty();
1426 }
1427
1428 bool RTLIL::Module::has_processes_warn() const
1429 {
1430 if (!processes.empty())
1431 log_warning("Ignoring module %s because it contains processes (run 'proc' command first).\n", log_id(this));
1432 return !processes.empty();
1433 }
1434
1435 std::vector<RTLIL::Wire*> RTLIL::Module::selected_wires() const
1436 {
1437 std::vector<RTLIL::Wire*> result;
1438 result.reserve(wires_.size());
1439 for (auto &it : wires_)
1440 if (design->selected(this, it.second))
1441 result.push_back(it.second);
1442 return result;
1443 }
1444
1445 std::vector<RTLIL::Cell*> RTLIL::Module::selected_cells() const
1446 {
1447 std::vector<RTLIL::Cell*> result;
1448 result.reserve(wires_.size());
1449 for (auto &it : cells_)
1450 if (design->selected(this, it.second))
1451 result.push_back(it.second);
1452 return result;
1453 }
1454
1455 void RTLIL::Module::add(RTLIL::Wire *wire)
1456 {
1457 log_assert(!wire->name.empty());
1458 log_assert(count_id(wire->name) == 0);
1459 log_assert(refcount_wires_ == 0);
1460 wires_[wire->name] = wire;
1461 wire->module = this;
1462 }
1463
1464 void RTLIL::Module::add(RTLIL::Cell *cell)
1465 {
1466 log_assert(!cell->name.empty());
1467 log_assert(count_id(cell->name) == 0);
1468 log_assert(refcount_cells_ == 0);
1469 cells_[cell->name] = cell;
1470 cell->module = this;
1471 }
1472
1473 namespace {
1474 struct DeleteWireWorker
1475 {
1476 RTLIL::Module *module;
1477 const pool<RTLIL::Wire*> *wires_p;
1478
1479 void operator()(RTLIL::SigSpec &sig) {
1480 std::vector<RTLIL::SigChunk> chunks = sig;
1481 for (auto &c : chunks)
1482 if (c.wire != NULL && wires_p->count(c.wire)) {
1483 c.wire = module->addWire(NEW_ID, c.width);
1484 c.offset = 0;
1485 }
1486 sig = chunks;
1487 }
1488 };
1489 }
1490
1491 void RTLIL::Module::remove(const pool<RTLIL::Wire*> &wires)
1492 {
1493 log_assert(refcount_wires_ == 0);
1494
1495 DeleteWireWorker delete_wire_worker;
1496 delete_wire_worker.module = this;
1497 delete_wire_worker.wires_p = &wires;
1498 rewrite_sigspecs(delete_wire_worker);
1499
1500 for (auto &it : wires) {
1501 log_assert(wires_.count(it->name) != 0);
1502 wires_.erase(it->name);
1503 delete it;
1504 }
1505 }
1506
1507 void RTLIL::Module::remove(RTLIL::Cell *cell)
1508 {
1509 while (!cell->connections_.empty())
1510 cell->unsetPort(cell->connections_.begin()->first);
1511
1512 log_assert(cells_.count(cell->name) != 0);
1513 log_assert(refcount_cells_ == 0);
1514 cells_.erase(cell->name);
1515 delete cell;
1516 }
1517
1518 void RTLIL::Module::rename(RTLIL::Wire *wire, RTLIL::IdString new_name)
1519 {
1520 log_assert(wires_[wire->name] == wire);
1521 log_assert(refcount_wires_ == 0);
1522 wires_.erase(wire->name);
1523 wire->name = new_name;
1524 add(wire);
1525 }
1526
1527 void RTLIL::Module::rename(RTLIL::Cell *cell, RTLIL::IdString new_name)
1528 {
1529 log_assert(cells_[cell->name] == cell);
1530 log_assert(refcount_wires_ == 0);
1531 cells_.erase(cell->name);
1532 cell->name = new_name;
1533 add(cell);
1534 }
1535
1536 void RTLIL::Module::rename(RTLIL::IdString old_name, RTLIL::IdString new_name)
1537 {
1538 log_assert(count_id(old_name) != 0);
1539 if (wires_.count(old_name))
1540 rename(wires_.at(old_name), new_name);
1541 else if (cells_.count(old_name))
1542 rename(cells_.at(old_name), new_name);
1543 else
1544 log_abort();
1545 }
1546
1547 void RTLIL::Module::swap_names(RTLIL::Wire *w1, RTLIL::Wire *w2)
1548 {
1549 log_assert(wires_[w1->name] == w1);
1550 log_assert(wires_[w2->name] == w2);
1551 log_assert(refcount_wires_ == 0);
1552
1553 wires_.erase(w1->name);
1554 wires_.erase(w2->name);
1555
1556 std::swap(w1->name, w2->name);
1557
1558 wires_[w1->name] = w1;
1559 wires_[w2->name] = w2;
1560 }
1561
1562 void RTLIL::Module::swap_names(RTLIL::Cell *c1, RTLIL::Cell *c2)
1563 {
1564 log_assert(cells_[c1->name] == c1);
1565 log_assert(cells_[c2->name] == c2);
1566 log_assert(refcount_cells_ == 0);
1567
1568 cells_.erase(c1->name);
1569 cells_.erase(c2->name);
1570
1571 std::swap(c1->name, c2->name);
1572
1573 cells_[c1->name] = c1;
1574 cells_[c2->name] = c2;
1575 }
1576
1577 RTLIL::IdString RTLIL::Module::uniquify(RTLIL::IdString name)
1578 {
1579 int index = 0;
1580 return uniquify(name, index);
1581 }
1582
1583 RTLIL::IdString RTLIL::Module::uniquify(RTLIL::IdString name, int &index)
1584 {
1585 if (index == 0) {
1586 if (count_id(name) == 0)
1587 return name;
1588 index++;
1589 }
1590
1591 while (1) {
1592 RTLIL::IdString new_name = stringf("%s_%d", name.c_str(), index);
1593 if (count_id(new_name) == 0)
1594 return new_name;
1595 index++;
1596 }
1597 }
1598
1599 static bool fixup_ports_compare(const RTLIL::Wire *a, const RTLIL::Wire *b)
1600 {
1601 if (a->port_id && !b->port_id)
1602 return true;
1603 if (!a->port_id && b->port_id)
1604 return false;
1605
1606 if (a->port_id == b->port_id)
1607 return a->name < b->name;
1608 return a->port_id < b->port_id;
1609 }
1610
1611 void RTLIL::Module::connect(const RTLIL::SigSig &conn)
1612 {
1613 for (auto mon : monitors)
1614 mon->notify_connect(this, conn);
1615
1616 if (design)
1617 for (auto mon : design->monitors)
1618 mon->notify_connect(this, conn);
1619
1620 // ignore all attempts to assign constants to other constants
1621 if (conn.first.has_const()) {
1622 RTLIL::SigSig new_conn;
1623 for (int i = 0; i < GetSize(conn.first); i++)
1624 if (conn.first[i].wire) {
1625 new_conn.first.append(conn.first[i]);
1626 new_conn.second.append(conn.second[i]);
1627 }
1628 if (GetSize(new_conn.first))
1629 connect(new_conn);
1630 return;
1631 }
1632
1633 if (yosys_xtrace) {
1634 log("#X# Connect (SigSig) in %s: %s = %s (%d bits)\n", log_id(this), log_signal(conn.first), log_signal(conn.second), GetSize(conn.first));
1635 log_backtrace("-X- ", yosys_xtrace-1);
1636 }
1637
1638 log_assert(GetSize(conn.first) == GetSize(conn.second));
1639 connections_.push_back(conn);
1640 }
1641
1642 void RTLIL::Module::connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs)
1643 {
1644 connect(RTLIL::SigSig(lhs, rhs));
1645 }
1646
1647 void RTLIL::Module::new_connections(const std::vector<RTLIL::SigSig> &new_conn)
1648 {
1649 for (auto mon : monitors)
1650 mon->notify_connect(this, new_conn);
1651
1652 if (design)
1653 for (auto mon : design->monitors)
1654 mon->notify_connect(this, new_conn);
1655
1656 if (yosys_xtrace) {
1657 log("#X# New connections vector in %s:\n", log_id(this));
1658 for (auto &conn: new_conn)
1659 log("#X# %s = %s (%d bits)\n", log_signal(conn.first), log_signal(conn.second), GetSize(conn.first));
1660 log_backtrace("-X- ", yosys_xtrace-1);
1661 }
1662
1663 connections_ = new_conn;
1664 }
1665
1666 const std::vector<RTLIL::SigSig> &RTLIL::Module::connections() const
1667 {
1668 return connections_;
1669 }
1670
1671 void RTLIL::Module::fixup_ports()
1672 {
1673 std::vector<RTLIL::Wire*> all_ports;
1674
1675 for (auto &w : wires_)
1676 if (w.second->port_input || w.second->port_output)
1677 all_ports.push_back(w.second);
1678 else
1679 w.second->port_id = 0;
1680
1681 std::sort(all_ports.begin(), all_ports.end(), fixup_ports_compare);
1682
1683 ports.clear();
1684 for (size_t i = 0; i < all_ports.size(); i++) {
1685 ports.push_back(all_ports[i]->name);
1686 all_ports[i]->port_id = i+1;
1687 }
1688 }
1689
1690 RTLIL::Wire *RTLIL::Module::addWire(RTLIL::IdString name, int width)
1691 {
1692 RTLIL::Wire *wire = new RTLIL::Wire;
1693 wire->name = name;
1694 wire->width = width;
1695 add(wire);
1696 return wire;
1697 }
1698
1699 RTLIL::Wire *RTLIL::Module::addWire(RTLIL::IdString name, const RTLIL::Wire *other)
1700 {
1701 RTLIL::Wire *wire = addWire(name);
1702 wire->width = other->width;
1703 wire->start_offset = other->start_offset;
1704 wire->port_id = other->port_id;
1705 wire->port_input = other->port_input;
1706 wire->port_output = other->port_output;
1707 wire->upto = other->upto;
1708 wire->attributes = other->attributes;
1709 return wire;
1710 }
1711
1712 RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, RTLIL::IdString type)
1713 {
1714 RTLIL::Cell *cell = new RTLIL::Cell;
1715 cell->name = name;
1716 cell->type = type;
1717 add(cell);
1718 return cell;
1719 }
1720
1721 RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, const RTLIL::Cell *other)
1722 {
1723 RTLIL::Cell *cell = addCell(name, other->type);
1724 cell->connections_ = other->connections_;
1725 cell->parameters = other->parameters;
1726 cell->attributes = other->attributes;
1727 return cell;
1728 }
1729
1730 #define DEF_METHOD(_func, _y_size, _type) \
1731 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed, const std::string &src) { \
1732 RTLIL::Cell *cell = addCell(name, _type); \
1733 cell->parameters["\\A_SIGNED"] = is_signed; \
1734 cell->parameters["\\A_WIDTH"] = sig_a.size(); \
1735 cell->parameters["\\Y_WIDTH"] = sig_y.size(); \
1736 cell->setPort("\\A", sig_a); \
1737 cell->setPort("\\Y", sig_y); \
1738 cell->set_src_attribute(src); \
1739 return cell; \
1740 } \
1741 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed, const std::string &src) { \
1742 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
1743 add ## _func(name, sig_a, sig_y, is_signed, src); \
1744 return sig_y; \
1745 }
1746 DEF_METHOD(Not, sig_a.size(), "$not")
1747 DEF_METHOD(Pos, sig_a.size(), "$pos")
1748 DEF_METHOD(Neg, sig_a.size(), "$neg")
1749 DEF_METHOD(ReduceAnd, 1, "$reduce_and")
1750 DEF_METHOD(ReduceOr, 1, "$reduce_or")
1751 DEF_METHOD(ReduceXor, 1, "$reduce_xor")
1752 DEF_METHOD(ReduceXnor, 1, "$reduce_xnor")
1753 DEF_METHOD(ReduceBool, 1, "$reduce_bool")
1754 DEF_METHOD(LogicNot, 1, "$logic_not")
1755 #undef DEF_METHOD
1756
1757 #define DEF_METHOD(_func, _y_size, _type) \
1758 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed, const std::string &src) { \
1759 RTLIL::Cell *cell = addCell(name, _type); \
1760 cell->parameters["\\A_SIGNED"] = is_signed; \
1761 cell->parameters["\\B_SIGNED"] = is_signed; \
1762 cell->parameters["\\A_WIDTH"] = sig_a.size(); \
1763 cell->parameters["\\B_WIDTH"] = sig_b.size(); \
1764 cell->parameters["\\Y_WIDTH"] = sig_y.size(); \
1765 cell->setPort("\\A", sig_a); \
1766 cell->setPort("\\B", sig_b); \
1767 cell->setPort("\\Y", sig_y); \
1768 cell->set_src_attribute(src); \
1769 return cell; \
1770 } \
1771 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed, const std::string &src) { \
1772 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
1773 add ## _func(name, sig_a, sig_b, sig_y, is_signed, src); \
1774 return sig_y; \
1775 }
1776 DEF_METHOD(And, max(sig_a.size(), sig_b.size()), "$and")
1777 DEF_METHOD(Or, max(sig_a.size(), sig_b.size()), "$or")
1778 DEF_METHOD(Xor, max(sig_a.size(), sig_b.size()), "$xor")
1779 DEF_METHOD(Xnor, max(sig_a.size(), sig_b.size()), "$xnor")
1780 DEF_METHOD(Shl, sig_a.size(), "$shl")
1781 DEF_METHOD(Shr, sig_a.size(), "$shr")
1782 DEF_METHOD(Sshl, sig_a.size(), "$sshl")
1783 DEF_METHOD(Sshr, sig_a.size(), "$sshr")
1784 DEF_METHOD(Shift, sig_a.size(), "$shift")
1785 DEF_METHOD(Shiftx, sig_a.size(), "$shiftx")
1786 DEF_METHOD(Lt, 1, "$lt")
1787 DEF_METHOD(Le, 1, "$le")
1788 DEF_METHOD(Eq, 1, "$eq")
1789 DEF_METHOD(Ne, 1, "$ne")
1790 DEF_METHOD(Eqx, 1, "$eqx")
1791 DEF_METHOD(Nex, 1, "$nex")
1792 DEF_METHOD(Ge, 1, "$ge")
1793 DEF_METHOD(Gt, 1, "$gt")
1794 DEF_METHOD(Add, max(sig_a.size(), sig_b.size()), "$add")
1795 DEF_METHOD(Sub, max(sig_a.size(), sig_b.size()), "$sub")
1796 DEF_METHOD(Mul, max(sig_a.size(), sig_b.size()), "$mul")
1797 DEF_METHOD(Div, max(sig_a.size(), sig_b.size()), "$div")
1798 DEF_METHOD(Mod, max(sig_a.size(), sig_b.size()), "$mod")
1799 DEF_METHOD(LogicAnd, 1, "$logic_and")
1800 DEF_METHOD(LogicOr, 1, "$logic_or")
1801 #undef DEF_METHOD
1802
1803 #define DEF_METHOD(_func, _type, _pmux) \
1804 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, RTLIL::SigSpec sig_y, const std::string &src) { \
1805 RTLIL::Cell *cell = addCell(name, _type); \
1806 cell->parameters["\\WIDTH"] = sig_a.size(); \
1807 if (_pmux) cell->parameters["\\S_WIDTH"] = sig_s.size(); \
1808 cell->setPort("\\A", sig_a); \
1809 cell->setPort("\\B", sig_b); \
1810 cell->setPort("\\S", sig_s); \
1811 cell->setPort("\\Y", sig_y); \
1812 cell->set_src_attribute(src); \
1813 return cell; \
1814 } \
1815 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, const std::string &src) { \
1816 RTLIL::SigSpec sig_y = addWire(NEW_ID, sig_a.size()); \
1817 add ## _func(name, sig_a, sig_b, sig_s, sig_y, src); \
1818 return sig_y; \
1819 }
1820 DEF_METHOD(Mux, "$mux", 0)
1821 DEF_METHOD(Pmux, "$pmux", 1)
1822 #undef DEF_METHOD
1823
1824 #define DEF_METHOD_2(_func, _type, _P1, _P2) \
1825 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, const std::string &src) { \
1826 RTLIL::Cell *cell = addCell(name, _type); \
1827 cell->setPort("\\" #_P1, sig1); \
1828 cell->setPort("\\" #_P2, sig2); \
1829 cell->set_src_attribute(src); \
1830 return cell; \
1831 } \
1832 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, const std::string &src) { \
1833 RTLIL::SigBit sig2 = addWire(NEW_ID); \
1834 add ## _func(name, sig1, sig2, src); \
1835 return sig2; \
1836 }
1837 #define DEF_METHOD_3(_func, _type, _P1, _P2, _P3) \
1838 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, const std::string &src) { \
1839 RTLIL::Cell *cell = addCell(name, _type); \
1840 cell->setPort("\\" #_P1, sig1); \
1841 cell->setPort("\\" #_P2, sig2); \
1842 cell->setPort("\\" #_P3, sig3); \
1843 cell->set_src_attribute(src); \
1844 return cell; \
1845 } \
1846 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, const std::string &src) { \
1847 RTLIL::SigBit sig3 = addWire(NEW_ID); \
1848 add ## _func(name, sig1, sig2, sig3, src); \
1849 return sig3; \
1850 }
1851 #define DEF_METHOD_4(_func, _type, _P1, _P2, _P3, _P4) \
1852 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, RTLIL::SigBit sig4, const std::string &src) { \
1853 RTLIL::Cell *cell = addCell(name, _type); \
1854 cell->setPort("\\" #_P1, sig1); \
1855 cell->setPort("\\" #_P2, sig2); \
1856 cell->setPort("\\" #_P3, sig3); \
1857 cell->setPort("\\" #_P4, sig4); \
1858 cell->set_src_attribute(src); \
1859 return cell; \
1860 } \
1861 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, const std::string &src) { \
1862 RTLIL::SigBit sig4 = addWire(NEW_ID); \
1863 add ## _func(name, sig1, sig2, sig3, sig4, src); \
1864 return sig4; \
1865 }
1866 #define DEF_METHOD_5(_func, _type, _P1, _P2, _P3, _P4, _P5) \
1867 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, RTLIL::SigBit sig4, RTLIL::SigBit sig5, const std::string &src) { \
1868 RTLIL::Cell *cell = addCell(name, _type); \
1869 cell->setPort("\\" #_P1, sig1); \
1870 cell->setPort("\\" #_P2, sig2); \
1871 cell->setPort("\\" #_P3, sig3); \
1872 cell->setPort("\\" #_P4, sig4); \
1873 cell->setPort("\\" #_P5, sig5); \
1874 cell->set_src_attribute(src); \
1875 return cell; \
1876 } \
1877 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, RTLIL::SigBit sig4, const std::string &src) { \
1878 RTLIL::SigBit sig5 = addWire(NEW_ID); \
1879 add ## _func(name, sig1, sig2, sig3, sig4, sig5, src); \
1880 return sig5; \
1881 }
1882 DEF_METHOD_2(BufGate, "$_BUF_", A, Y)
1883 DEF_METHOD_2(NotGate, "$_NOT_", A, Y)
1884 DEF_METHOD_3(AndGate, "$_AND_", A, B, Y)
1885 DEF_METHOD_3(NandGate, "$_NAND_", A, B, Y)
1886 DEF_METHOD_3(OrGate, "$_OR_", A, B, Y)
1887 DEF_METHOD_3(NorGate, "$_NOR_", A, B, Y)
1888 DEF_METHOD_3(XorGate, "$_XOR_", A, B, Y)
1889 DEF_METHOD_3(XnorGate, "$_XNOR_", A, B, Y)
1890 DEF_METHOD_3(AndnotGate, "$_ANDNOT_", A, B, Y)
1891 DEF_METHOD_3(OrnotGate, "$_ORNOT_", A, B, Y)
1892 DEF_METHOD_4(MuxGate, "$_MUX_", A, B, S, Y)
1893 DEF_METHOD_4(Aoi3Gate, "$_AOI3_", A, B, C, Y)
1894 DEF_METHOD_4(Oai3Gate, "$_OAI3_", A, B, C, Y)
1895 DEF_METHOD_5(Aoi4Gate, "$_AOI4_", A, B, C, D, Y)
1896 DEF_METHOD_5(Oai4Gate, "$_OAI4_", A, B, C, D, Y)
1897 #undef DEF_METHOD_2
1898 #undef DEF_METHOD_3
1899 #undef DEF_METHOD_4
1900 #undef DEF_METHOD_5
1901
1902 RTLIL::Cell* RTLIL::Module::addPow(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool a_signed, bool b_signed, const std::string &src)
1903 {
1904 RTLIL::Cell *cell = addCell(name, "$pow");
1905 cell->parameters["\\A_SIGNED"] = a_signed;
1906 cell->parameters["\\B_SIGNED"] = b_signed;
1907 cell->parameters["\\A_WIDTH"] = sig_a.size();
1908 cell->parameters["\\B_WIDTH"] = sig_b.size();
1909 cell->parameters["\\Y_WIDTH"] = sig_y.size();
1910 cell->setPort("\\A", sig_a);
1911 cell->setPort("\\B", sig_b);
1912 cell->setPort("\\Y", sig_y);
1913 cell->set_src_attribute(src);
1914 return cell;
1915 }
1916
1917 RTLIL::Cell* RTLIL::Module::addSlice(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, RTLIL::Const offset, const std::string &src)
1918 {
1919 RTLIL::Cell *cell = addCell(name, "$slice");
1920 cell->parameters["\\A_WIDTH"] = sig_a.size();
1921 cell->parameters["\\Y_WIDTH"] = sig_y.size();
1922 cell->parameters["\\OFFSET"] = offset;
1923 cell->setPort("\\A", sig_a);
1924 cell->setPort("\\Y", sig_y);
1925 cell->set_src_attribute(src);
1926 return cell;
1927 }
1928
1929 RTLIL::Cell* RTLIL::Module::addConcat(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, const std::string &src)
1930 {
1931 RTLIL::Cell *cell = addCell(name, "$concat");
1932 cell->parameters["\\A_WIDTH"] = sig_a.size();
1933 cell->parameters["\\B_WIDTH"] = sig_b.size();
1934 cell->setPort("\\A", sig_a);
1935 cell->setPort("\\B", sig_b);
1936 cell->setPort("\\Y", sig_y);
1937 cell->set_src_attribute(src);
1938 return cell;
1939 }
1940
1941 RTLIL::Cell* RTLIL::Module::addLut(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, RTLIL::Const lut, const std::string &src)
1942 {
1943 RTLIL::Cell *cell = addCell(name, "$lut");
1944 cell->parameters["\\LUT"] = lut;
1945 cell->parameters["\\WIDTH"] = sig_a.size();
1946 cell->setPort("\\A", sig_a);
1947 cell->setPort("\\Y", sig_y);
1948 cell->set_src_attribute(src);
1949 return cell;
1950 }
1951
1952 RTLIL::Cell* RTLIL::Module::addTribuf(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_y, const std::string &src)
1953 {
1954 RTLIL::Cell *cell = addCell(name, "$tribuf");
1955 cell->parameters["\\WIDTH"] = sig_a.size();
1956 cell->setPort("\\A", sig_a);
1957 cell->setPort("\\EN", sig_en);
1958 cell->setPort("\\Y", sig_y);
1959 cell->set_src_attribute(src);
1960 return cell;
1961 }
1962
1963 RTLIL::Cell* RTLIL::Module::addAssert(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src)
1964 {
1965 RTLIL::Cell *cell = addCell(name, "$assert");
1966 cell->setPort("\\A", sig_a);
1967 cell->setPort("\\EN", sig_en);
1968 cell->set_src_attribute(src);
1969 return cell;
1970 }
1971
1972 RTLIL::Cell* RTLIL::Module::addAssume(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src)
1973 {
1974 RTLIL::Cell *cell = addCell(name, "$assume");
1975 cell->setPort("\\A", sig_a);
1976 cell->setPort("\\EN", sig_en);
1977 cell->set_src_attribute(src);
1978 return cell;
1979 }
1980
1981 RTLIL::Cell* RTLIL::Module::addLive(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src)
1982 {
1983 RTLIL::Cell *cell = addCell(name, "$live");
1984 cell->setPort("\\A", sig_a);
1985 cell->setPort("\\EN", sig_en);
1986 cell->set_src_attribute(src);
1987 return cell;
1988 }
1989
1990 RTLIL::Cell* RTLIL::Module::addFair(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src)
1991 {
1992 RTLIL::Cell *cell = addCell(name, "$fair");
1993 cell->setPort("\\A", sig_a);
1994 cell->setPort("\\EN", sig_en);
1995 cell->set_src_attribute(src);
1996 return cell;
1997 }
1998
1999 RTLIL::Cell* RTLIL::Module::addCover(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src)
2000 {
2001 RTLIL::Cell *cell = addCell(name, "$cover");
2002 cell->setPort("\\A", sig_a);
2003 cell->setPort("\\EN", sig_en);
2004 cell->set_src_attribute(src);
2005 return cell;
2006 }
2007
2008 RTLIL::Cell* RTLIL::Module::addEquiv(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, const std::string &src)
2009 {
2010 RTLIL::Cell *cell = addCell(name, "$equiv");
2011 cell->setPort("\\A", sig_a);
2012 cell->setPort("\\B", sig_b);
2013 cell->setPort("\\Y", sig_y);
2014 cell->set_src_attribute(src);
2015 return cell;
2016 }
2017
2018 RTLIL::Cell* RTLIL::Module::addSr(RTLIL::IdString name, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr, RTLIL::SigSpec sig_q, bool set_polarity, bool clr_polarity, const std::string &src)
2019 {
2020 RTLIL::Cell *cell = addCell(name, "$sr");
2021 cell->parameters["\\SET_POLARITY"] = set_polarity;
2022 cell->parameters["\\CLR_POLARITY"] = clr_polarity;
2023 cell->parameters["\\WIDTH"] = sig_q.size();
2024 cell->setPort("\\SET", sig_set);
2025 cell->setPort("\\CLR", sig_clr);
2026 cell->setPort("\\Q", sig_q);
2027 cell->set_src_attribute(src);
2028 return cell;
2029 }
2030
2031 RTLIL::Cell* RTLIL::Module::addFf(RTLIL::IdString name, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, const std::string &src)
2032 {
2033 RTLIL::Cell *cell = addCell(name, "$ff");
2034 cell->parameters["\\WIDTH"] = sig_q.size();
2035 cell->setPort("\\D", sig_d);
2036 cell->setPort("\\Q", sig_q);
2037 cell->set_src_attribute(src);
2038 return cell;
2039 }
2040
2041 RTLIL::Cell* RTLIL::Module::addDff(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, const std::string &src)
2042 {
2043 RTLIL::Cell *cell = addCell(name, "$dff");
2044 cell->parameters["\\CLK_POLARITY"] = clk_polarity;
2045 cell->parameters["\\WIDTH"] = sig_q.size();
2046 cell->setPort("\\CLK", sig_clk);
2047 cell->setPort("\\D", sig_d);
2048 cell->setPort("\\Q", sig_q);
2049 cell->set_src_attribute(src);
2050 return cell;
2051 }
2052
2053 RTLIL::Cell* RTLIL::Module::addDffe(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, bool en_polarity, const std::string &src)
2054 {
2055 RTLIL::Cell *cell = addCell(name, "$dffe");
2056 cell->parameters["\\CLK_POLARITY"] = clk_polarity;
2057 cell->parameters["\\EN_POLARITY"] = en_polarity;
2058 cell->parameters["\\WIDTH"] = sig_q.size();
2059 cell->setPort("\\CLK", sig_clk);
2060 cell->setPort("\\EN", sig_en);
2061 cell->setPort("\\D", sig_d);
2062 cell->setPort("\\Q", sig_q);
2063 cell->set_src_attribute(src);
2064 return cell;
2065 }
2066
2067 RTLIL::Cell* RTLIL::Module::addDffsr(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
2068 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
2069 {
2070 RTLIL::Cell *cell = addCell(name, "$dffsr");
2071 cell->parameters["\\CLK_POLARITY"] = clk_polarity;
2072 cell->parameters["\\SET_POLARITY"] = set_polarity;
2073 cell->parameters["\\CLR_POLARITY"] = clr_polarity;
2074 cell->parameters["\\WIDTH"] = sig_q.size();
2075 cell->setPort("\\CLK", sig_clk);
2076 cell->setPort("\\SET", sig_set);
2077 cell->setPort("\\CLR", sig_clr);
2078 cell->setPort("\\D", sig_d);
2079 cell->setPort("\\Q", sig_q);
2080 cell->set_src_attribute(src);
2081 return cell;
2082 }
2083
2084 RTLIL::Cell* RTLIL::Module::addAdff(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_arst, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q,
2085 RTLIL::Const arst_value, bool clk_polarity, bool arst_polarity, const std::string &src)
2086 {
2087 RTLIL::Cell *cell = addCell(name, "$adff");
2088 cell->parameters["\\CLK_POLARITY"] = clk_polarity;
2089 cell->parameters["\\ARST_POLARITY"] = arst_polarity;
2090 cell->parameters["\\ARST_VALUE"] = arst_value;
2091 cell->parameters["\\WIDTH"] = sig_q.size();
2092 cell->setPort("\\CLK", sig_clk);
2093 cell->setPort("\\ARST", sig_arst);
2094 cell->setPort("\\D", sig_d);
2095 cell->setPort("\\Q", sig_q);
2096 cell->set_src_attribute(src);
2097 return cell;
2098 }
2099
2100 RTLIL::Cell* RTLIL::Module::addDlatch(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity, const std::string &src)
2101 {
2102 RTLIL::Cell *cell = addCell(name, "$dlatch");
2103 cell->parameters["\\EN_POLARITY"] = en_polarity;
2104 cell->parameters["\\WIDTH"] = sig_q.size();
2105 cell->setPort("\\EN", sig_en);
2106 cell->setPort("\\D", sig_d);
2107 cell->setPort("\\Q", sig_q);
2108 cell->set_src_attribute(src);
2109 return cell;
2110 }
2111
2112 RTLIL::Cell* RTLIL::Module::addDlatchsr(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
2113 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
2114 {
2115 RTLIL::Cell *cell = addCell(name, "$dlatchsr");
2116 cell->parameters["\\EN_POLARITY"] = en_polarity;
2117 cell->parameters["\\SET_POLARITY"] = set_polarity;
2118 cell->parameters["\\CLR_POLARITY"] = clr_polarity;
2119 cell->parameters["\\WIDTH"] = sig_q.size();
2120 cell->setPort("\\EN", sig_en);
2121 cell->setPort("\\SET", sig_set);
2122 cell->setPort("\\CLR", sig_clr);
2123 cell->setPort("\\D", sig_d);
2124 cell->setPort("\\Q", sig_q);
2125 cell->set_src_attribute(src);
2126 return cell;
2127 }
2128
2129 RTLIL::Cell* RTLIL::Module::addFfGate(RTLIL::IdString name, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, const std::string &src)
2130 {
2131 RTLIL::Cell *cell = addCell(name, "$_FF_");
2132 cell->setPort("\\D", sig_d);
2133 cell->setPort("\\Q", sig_q);
2134 cell->set_src_attribute(src);
2135 return cell;
2136 }
2137
2138 RTLIL::Cell* RTLIL::Module::addDffGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, const std::string &src)
2139 {
2140 RTLIL::Cell *cell = addCell(name, stringf("$_DFF_%c_", clk_polarity ? 'P' : 'N'));
2141 cell->setPort("\\C", sig_clk);
2142 cell->setPort("\\D", sig_d);
2143 cell->setPort("\\Q", sig_q);
2144 cell->set_src_attribute(src);
2145 return cell;
2146 }
2147
2148 RTLIL::Cell* RTLIL::Module::addDffeGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, bool en_polarity, const std::string &src)
2149 {
2150 RTLIL::Cell *cell = addCell(name, stringf("$_DFFE_%c%c_", clk_polarity ? 'P' : 'N', en_polarity ? 'P' : 'N'));
2151 cell->setPort("\\C", sig_clk);
2152 cell->setPort("\\E", sig_en);
2153 cell->setPort("\\D", sig_d);
2154 cell->setPort("\\Q", sig_q);
2155 cell->set_src_attribute(src);
2156 return cell;
2157 }
2158
2159 RTLIL::Cell* RTLIL::Module::addDffsrGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
2160 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
2161 {
2162 RTLIL::Cell *cell = addCell(name, stringf("$_DFFSR_%c%c%c_", clk_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N'));
2163 cell->setPort("\\C", sig_clk);
2164 cell->setPort("\\S", sig_set);
2165 cell->setPort("\\R", sig_clr);
2166 cell->setPort("\\D", sig_d);
2167 cell->setPort("\\Q", sig_q);
2168 cell->set_src_attribute(src);
2169 return cell;
2170 }
2171
2172 RTLIL::Cell* RTLIL::Module::addAdffGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_arst, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q,
2173 bool arst_value, bool clk_polarity, bool arst_polarity, const std::string &src)
2174 {
2175 RTLIL::Cell *cell = addCell(name, stringf("$_DFF_%c%c%c_", clk_polarity ? 'P' : 'N', arst_polarity ? 'P' : 'N', arst_value ? '1' : '0'));
2176 cell->setPort("\\C", sig_clk);
2177 cell->setPort("\\R", sig_arst);
2178 cell->setPort("\\D", sig_d);
2179 cell->setPort("\\Q", sig_q);
2180 cell->set_src_attribute(src);
2181 return cell;
2182 }
2183
2184 RTLIL::Cell* RTLIL::Module::addDlatchGate(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity, const std::string &src)
2185 {
2186 RTLIL::Cell *cell = addCell(name, stringf("$_DLATCH_%c_", en_polarity ? 'P' : 'N'));
2187 cell->setPort("\\E", sig_en);
2188 cell->setPort("\\D", sig_d);
2189 cell->setPort("\\Q", sig_q);
2190 cell->set_src_attribute(src);
2191 return cell;
2192 }
2193
2194 RTLIL::Cell* RTLIL::Module::addDlatchsrGate(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
2195 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
2196 {
2197 RTLIL::Cell *cell = addCell(name, stringf("$_DLATCHSR_%c%c%c_", en_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N'));
2198 cell->setPort("\\E", sig_en);
2199 cell->setPort("\\S", sig_set);
2200 cell->setPort("\\R", sig_clr);
2201 cell->setPort("\\D", sig_d);
2202 cell->setPort("\\Q", sig_q);
2203 cell->set_src_attribute(src);
2204 return cell;
2205 }
2206
2207 RTLIL::SigSpec RTLIL::Module::Anyconst(RTLIL::IdString name, int width, const std::string &src)
2208 {
2209 RTLIL::SigSpec sig = addWire(NEW_ID, width);
2210 Cell *cell = addCell(name, "$anyconst");
2211 cell->setParam("\\WIDTH", width);
2212 cell->setPort("\\Y", sig);
2213 cell->set_src_attribute(src);
2214 return sig;
2215 }
2216
2217 RTLIL::SigSpec RTLIL::Module::Anyseq(RTLIL::IdString name, int width, const std::string &src)
2218 {
2219 RTLIL::SigSpec sig = addWire(NEW_ID, width);
2220 Cell *cell = addCell(name, "$anyseq");
2221 cell->setParam("\\WIDTH", width);
2222 cell->setPort("\\Y", sig);
2223 cell->set_src_attribute(src);
2224 return sig;
2225 }
2226
2227 RTLIL::SigSpec RTLIL::Module::Allconst(RTLIL::IdString name, int width, const std::string &src)
2228 {
2229 RTLIL::SigSpec sig = addWire(NEW_ID, width);
2230 Cell *cell = addCell(name, "$allconst");
2231 cell->setParam("\\WIDTH", width);
2232 cell->setPort("\\Y", sig);
2233 cell->set_src_attribute(src);
2234 return sig;
2235 }
2236
2237 RTLIL::SigSpec RTLIL::Module::Allseq(RTLIL::IdString name, int width, const std::string &src)
2238 {
2239 RTLIL::SigSpec sig = addWire(NEW_ID, width);
2240 Cell *cell = addCell(name, "$allseq");
2241 cell->setParam("\\WIDTH", width);
2242 cell->setPort("\\Y", sig);
2243 cell->set_src_attribute(src);
2244 return sig;
2245 }
2246
2247 RTLIL::SigSpec RTLIL::Module::Initstate(RTLIL::IdString name, const std::string &src)
2248 {
2249 RTLIL::SigSpec sig = addWire(NEW_ID);
2250 Cell *cell = addCell(name, "$initstate");
2251 cell->setPort("\\Y", sig);
2252 cell->set_src_attribute(src);
2253 return sig;
2254 }
2255
2256 RTLIL::Wire::Wire()
2257 {
2258 static unsigned int hashidx_count = 123456789;
2259 hashidx_count = mkhash_xorshift(hashidx_count);
2260 hashidx_ = hashidx_count;
2261
2262 module = nullptr;
2263 width = 1;
2264 start_offset = 0;
2265 port_id = 0;
2266 port_input = false;
2267 port_output = false;
2268 upto = false;
2269
2270 #ifdef WITH_PYTHON
2271 RTLIL::Wire::get_all_wires()->insert(std::pair<unsigned int, RTLIL::Wire*>(hashidx_, this));
2272 #endif
2273 }
2274
2275 RTLIL::Wire::~Wire()
2276 {
2277 #ifdef WITH_PYTHON
2278 RTLIL::Wire::get_all_wires()->erase(hashidx_);
2279 #endif
2280 }
2281
2282 #ifdef WITH_PYTHON
2283 static std::map<unsigned int, RTLIL::Wire*> all_wires;
2284 std::map<unsigned int, RTLIL::Wire*> *RTLIL::Wire::get_all_wires(void)
2285 {
2286 return &all_wires;
2287 }
2288 #endif
2289
2290 RTLIL::Memory::Memory()
2291 {
2292 static unsigned int hashidx_count = 123456789;
2293 hashidx_count = mkhash_xorshift(hashidx_count);
2294 hashidx_ = hashidx_count;
2295
2296 width = 1;
2297 start_offset = 0;
2298 size = 0;
2299 #ifdef WITH_PYTHON
2300 RTLIL::Memory::get_all_memorys()->insert(std::pair<unsigned int, RTLIL::Memory*>(hashidx_, this));
2301 #endif
2302 }
2303
2304 RTLIL::Cell::Cell() : module(nullptr)
2305 {
2306 static unsigned int hashidx_count = 123456789;
2307 hashidx_count = mkhash_xorshift(hashidx_count);
2308 hashidx_ = hashidx_count;
2309
2310 // log("#memtrace# %p\n", this);
2311 memhasher();
2312
2313 #ifdef WITH_PYTHON
2314 RTLIL::Cell::get_all_cells()->insert(std::pair<unsigned int, RTLIL::Cell*>(hashidx_, this));
2315 #endif
2316 }
2317
2318 RTLIL::Cell::~Cell()
2319 {
2320 #ifdef WITH_PYTHON
2321 RTLIL::Cell::get_all_cells()->erase(hashidx_);
2322 #endif
2323 }
2324
2325 #ifdef WITH_PYTHON
2326 static std::map<unsigned int, RTLIL::Cell*> all_cells;
2327 std::map<unsigned int, RTLIL::Cell*> *RTLIL::Cell::get_all_cells(void)
2328 {
2329 return &all_cells;
2330 }
2331 #endif
2332
2333 bool RTLIL::Cell::hasPort(RTLIL::IdString portname) const
2334 {
2335 return connections_.count(portname) != 0;
2336 }
2337
2338 void RTLIL::Cell::unsetPort(RTLIL::IdString portname)
2339 {
2340 RTLIL::SigSpec signal;
2341 auto conn_it = connections_.find(portname);
2342
2343 if (conn_it != connections_.end())
2344 {
2345 for (auto mon : module->monitors)
2346 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
2347
2348 if (module->design)
2349 for (auto mon : module->design->monitors)
2350 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
2351
2352 if (yosys_xtrace) {
2353 log("#X# Unconnect %s.%s.%s\n", log_id(this->module), log_id(this), log_id(portname));
2354 log_backtrace("-X- ", yosys_xtrace-1);
2355 }
2356
2357 connections_.erase(conn_it);
2358 }
2359 }
2360
2361 void RTLIL::Cell::setPort(RTLIL::IdString portname, RTLIL::SigSpec signal)
2362 {
2363 auto conn_it = connections_.find(portname);
2364
2365 if (conn_it == connections_.end()) {
2366 connections_[portname] = RTLIL::SigSpec();
2367 conn_it = connections_.find(portname);
2368 log_assert(conn_it != connections_.end());
2369 } else
2370 if (conn_it->second == signal)
2371 return;
2372
2373 for (auto mon : module->monitors)
2374 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
2375
2376 if (module->design)
2377 for (auto mon : module->design->monitors)
2378 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
2379
2380 if (yosys_xtrace) {
2381 log("#X# Connect %s.%s.%s = %s (%d)\n", log_id(this->module), log_id(this), log_id(portname), log_signal(signal), GetSize(signal));
2382 log_backtrace("-X- ", yosys_xtrace-1);
2383 }
2384
2385 conn_it->second = signal;
2386 }
2387
2388 const RTLIL::SigSpec &RTLIL::Cell::getPort(RTLIL::IdString portname) const
2389 {
2390 return connections_.at(portname);
2391 }
2392
2393 const dict<RTLIL::IdString, RTLIL::SigSpec> &RTLIL::Cell::connections() const
2394 {
2395 return connections_;
2396 }
2397
2398 bool RTLIL::Cell::known() const
2399 {
2400 if (yosys_celltypes.cell_known(type))
2401 return true;
2402 if (module && module->design && module->design->module(type))
2403 return true;
2404 return false;
2405 }
2406
2407 bool RTLIL::Cell::input(RTLIL::IdString portname) const
2408 {
2409 if (yosys_celltypes.cell_known(type))
2410 return yosys_celltypes.cell_input(type, portname);
2411 if (module && module->design) {
2412 RTLIL::Module *m = module->design->module(type);
2413 RTLIL::Wire *w = m ? m->wire(portname) : nullptr;
2414 return w && w->port_input;
2415 }
2416 return false;
2417 }
2418
2419 bool RTLIL::Cell::output(RTLIL::IdString portname) const
2420 {
2421 if (yosys_celltypes.cell_known(type))
2422 return yosys_celltypes.cell_output(type, portname);
2423 if (module && module->design) {
2424 RTLIL::Module *m = module->design->module(type);
2425 RTLIL::Wire *w = m ? m->wire(portname) : nullptr;
2426 return w && w->port_output;
2427 }
2428 return false;
2429 }
2430
2431 bool RTLIL::Cell::hasParam(RTLIL::IdString paramname) const
2432 {
2433 return parameters.count(paramname) != 0;
2434 }
2435
2436 void RTLIL::Cell::unsetParam(RTLIL::IdString paramname)
2437 {
2438 parameters.erase(paramname);
2439 }
2440
2441 void RTLIL::Cell::setParam(RTLIL::IdString paramname, RTLIL::Const value)
2442 {
2443 parameters[paramname] = value;
2444 }
2445
2446 const RTLIL::Const &RTLIL::Cell::getParam(RTLIL::IdString paramname) const
2447 {
2448 return parameters.at(paramname);
2449 }
2450
2451 void RTLIL::Cell::sort()
2452 {
2453 connections_.sort(sort_by_id_str());
2454 parameters.sort(sort_by_id_str());
2455 attributes.sort(sort_by_id_str());
2456 }
2457
2458 void RTLIL::Cell::check()
2459 {
2460 #ifndef NDEBUG
2461 InternalCellChecker checker(NULL, this);
2462 checker.check();
2463 #endif
2464 }
2465
2466 void RTLIL::Cell::fixup_parameters(bool set_a_signed, bool set_b_signed)
2467 {
2468 if (type.substr(0, 1) != "$" || type.substr(0, 2) == "$_" || type.substr(0, 8) == "$paramod" || type.substr(0,10) == "$fmcombine" ||
2469 type.substr(0, 9) == "$verific$" || type.substr(0, 7) == "$array:" || type.substr(0, 8) == "$extern:")
2470 return;
2471
2472 if (type == "$mux" || type == "$pmux") {
2473 parameters["\\WIDTH"] = GetSize(connections_["\\Y"]);
2474 if (type == "$pmux")
2475 parameters["\\S_WIDTH"] = GetSize(connections_["\\S"]);
2476 check();
2477 return;
2478 }
2479
2480 if (type == "$lut" || type == "$sop") {
2481 parameters["\\WIDTH"] = GetSize(connections_["\\A"]);
2482 return;
2483 }
2484
2485 if (type == "$fa") {
2486 parameters["\\WIDTH"] = GetSize(connections_["\\Y"]);
2487 return;
2488 }
2489
2490 if (type == "$lcu") {
2491 parameters["\\WIDTH"] = GetSize(connections_["\\CO"]);
2492 return;
2493 }
2494
2495 bool signedness_ab = !type.in("$slice", "$concat", "$macc");
2496
2497 if (connections_.count("\\A")) {
2498 if (signedness_ab) {
2499 if (set_a_signed)
2500 parameters["\\A_SIGNED"] = true;
2501 else if (parameters.count("\\A_SIGNED") == 0)
2502 parameters["\\A_SIGNED"] = false;
2503 }
2504 parameters["\\A_WIDTH"] = GetSize(connections_["\\A"]);
2505 }
2506
2507 if (connections_.count("\\B")) {
2508 if (signedness_ab) {
2509 if (set_b_signed)
2510 parameters["\\B_SIGNED"] = true;
2511 else if (parameters.count("\\B_SIGNED") == 0)
2512 parameters["\\B_SIGNED"] = false;
2513 }
2514 parameters["\\B_WIDTH"] = GetSize(connections_["\\B"]);
2515 }
2516
2517 if (connections_.count("\\Y"))
2518 parameters["\\Y_WIDTH"] = GetSize(connections_["\\Y"]);
2519
2520 if (connections_.count("\\Q"))
2521 parameters["\\WIDTH"] = GetSize(connections_["\\Q"]);
2522
2523 check();
2524 }
2525
2526 RTLIL::SigChunk::SigChunk()
2527 {
2528 wire = NULL;
2529 width = 0;
2530 offset = 0;
2531 }
2532
2533 RTLIL::SigChunk::SigChunk(const RTLIL::Const &value)
2534 {
2535 wire = NULL;
2536 data = value.bits;
2537 width = GetSize(data);
2538 offset = 0;
2539 }
2540
2541 RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire)
2542 {
2543 log_assert(wire != nullptr);
2544 this->wire = wire;
2545 this->width = wire->width;
2546 this->offset = 0;
2547 }
2548
2549 RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire, int offset, int width)
2550 {
2551 log_assert(wire != nullptr);
2552 this->wire = wire;
2553 this->width = width;
2554 this->offset = offset;
2555 }
2556
2557 RTLIL::SigChunk::SigChunk(const std::string &str)
2558 {
2559 wire = NULL;
2560 data = RTLIL::Const(str).bits;
2561 width = GetSize(data);
2562 offset = 0;
2563 }
2564
2565 RTLIL::SigChunk::SigChunk(int val, int width)
2566 {
2567 wire = NULL;
2568 data = RTLIL::Const(val, width).bits;
2569 this->width = GetSize(data);
2570 offset = 0;
2571 }
2572
2573 RTLIL::SigChunk::SigChunk(RTLIL::State bit, int width)
2574 {
2575 wire = NULL;
2576 data = RTLIL::Const(bit, width).bits;
2577 this->width = GetSize(data);
2578 offset = 0;
2579 }
2580
2581 RTLIL::SigChunk::SigChunk(RTLIL::SigBit bit)
2582 {
2583 wire = bit.wire;
2584 offset = 0;
2585 if (wire == NULL)
2586 data = RTLIL::Const(bit.data).bits;
2587 else
2588 offset = bit.offset;
2589 width = 1;
2590 }
2591
2592 RTLIL::SigChunk::SigChunk(const RTLIL::SigChunk &sigchunk) : data(sigchunk.data)
2593 {
2594 wire = sigchunk.wire;
2595 data = sigchunk.data;
2596 width = sigchunk.width;
2597 offset = sigchunk.offset;
2598 }
2599
2600 RTLIL::SigChunk RTLIL::SigChunk::extract(int offset, int length) const
2601 {
2602 RTLIL::SigChunk ret;
2603 if (wire) {
2604 ret.wire = wire;
2605 ret.offset = this->offset + offset;
2606 ret.width = length;
2607 } else {
2608 for (int i = 0; i < length; i++)
2609 ret.data.push_back(data[offset+i]);
2610 ret.width = length;
2611 }
2612 return ret;
2613 }
2614
2615 bool RTLIL::SigChunk::operator <(const RTLIL::SigChunk &other) const
2616 {
2617 if (wire && other.wire)
2618 if (wire->name != other.wire->name)
2619 return wire->name < other.wire->name;
2620
2621 if (wire != other.wire)
2622 return wire < other.wire;
2623
2624 if (offset != other.offset)
2625 return offset < other.offset;
2626
2627 if (width != other.width)
2628 return width < other.width;
2629
2630 return data < other.data;
2631 }
2632
2633 bool RTLIL::SigChunk::operator ==(const RTLIL::SigChunk &other) const
2634 {
2635 return wire == other.wire && width == other.width && offset == other.offset && data == other.data;
2636 }
2637
2638 bool RTLIL::SigChunk::operator !=(const RTLIL::SigChunk &other) const
2639 {
2640 if (*this == other)
2641 return false;
2642 return true;
2643 }
2644
2645 RTLIL::SigSpec::SigSpec()
2646 {
2647 width_ = 0;
2648 hash_ = 0;
2649 }
2650
2651 RTLIL::SigSpec::SigSpec(const RTLIL::SigSpec &other)
2652 {
2653 *this = other;
2654 }
2655
2656 RTLIL::SigSpec::SigSpec(std::initializer_list<RTLIL::SigSpec> parts)
2657 {
2658 cover("kernel.rtlil.sigspec.init.list");
2659
2660 width_ = 0;
2661 hash_ = 0;
2662
2663 std::vector<RTLIL::SigSpec> parts_vec(parts.begin(), parts.end());
2664 for (auto it = parts_vec.rbegin(); it != parts_vec.rend(); it++)
2665 append(*it);
2666 }
2667
2668 const RTLIL::SigSpec &RTLIL::SigSpec::operator=(const RTLIL::SigSpec &other)
2669 {
2670 cover("kernel.rtlil.sigspec.assign");
2671
2672 width_ = other.width_;
2673 hash_ = other.hash_;
2674 chunks_ = other.chunks_;
2675 bits_.clear();
2676
2677 if (!other.bits_.empty())
2678 {
2679 RTLIL::SigChunk *last = NULL;
2680 int last_end_offset = 0;
2681
2682 for (auto &bit : other.bits_) {
2683 if (last && bit.wire == last->wire) {
2684 if (bit.wire == NULL) {
2685 last->data.push_back(bit.data);
2686 last->width++;
2687 continue;
2688 } else if (last_end_offset == bit.offset) {
2689 last_end_offset++;
2690 last->width++;
2691 continue;
2692 }
2693 }
2694 chunks_.push_back(bit);
2695 last = &chunks_.back();
2696 last_end_offset = bit.offset + 1;
2697 }
2698
2699 check();
2700 }
2701
2702 return *this;
2703 }
2704
2705 RTLIL::SigSpec::SigSpec(const RTLIL::Const &value)
2706 {
2707 cover("kernel.rtlil.sigspec.init.const");
2708
2709 chunks_.push_back(RTLIL::SigChunk(value));
2710 width_ = chunks_.back().width;
2711 hash_ = 0;
2712 check();
2713 }
2714
2715 RTLIL::SigSpec::SigSpec(const RTLIL::SigChunk &chunk)
2716 {
2717 cover("kernel.rtlil.sigspec.init.chunk");
2718
2719 chunks_.push_back(chunk);
2720 width_ = chunks_.back().width;
2721 hash_ = 0;
2722 check();
2723 }
2724
2725 RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire)
2726 {
2727 cover("kernel.rtlil.sigspec.init.wire");
2728
2729 chunks_.push_back(RTLIL::SigChunk(wire));
2730 width_ = chunks_.back().width;
2731 hash_ = 0;
2732 check();
2733 }
2734
2735 RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire, int offset, int width)
2736 {
2737 cover("kernel.rtlil.sigspec.init.wire_part");
2738
2739 chunks_.push_back(RTLIL::SigChunk(wire, offset, width));
2740 width_ = chunks_.back().width;
2741 hash_ = 0;
2742 check();
2743 }
2744
2745 RTLIL::SigSpec::SigSpec(const std::string &str)
2746 {
2747 cover("kernel.rtlil.sigspec.init.str");
2748
2749 chunks_.push_back(RTLIL::SigChunk(str));
2750 width_ = chunks_.back().width;
2751 hash_ = 0;
2752 check();
2753 }
2754
2755 RTLIL::SigSpec::SigSpec(int val, int width)
2756 {
2757 cover("kernel.rtlil.sigspec.init.int");
2758
2759 chunks_.push_back(RTLIL::SigChunk(val, width));
2760 width_ = width;
2761 hash_ = 0;
2762 check();
2763 }
2764
2765 RTLIL::SigSpec::SigSpec(RTLIL::State bit, int width)
2766 {
2767 cover("kernel.rtlil.sigspec.init.state");
2768
2769 chunks_.push_back(RTLIL::SigChunk(bit, width));
2770 width_ = width;
2771 hash_ = 0;
2772 check();
2773 }
2774
2775 RTLIL::SigSpec::SigSpec(RTLIL::SigBit bit, int width)
2776 {
2777 cover("kernel.rtlil.sigspec.init.bit");
2778
2779 if (bit.wire == NULL)
2780 chunks_.push_back(RTLIL::SigChunk(bit.data, width));
2781 else
2782 for (int i = 0; i < width; i++)
2783 chunks_.push_back(bit);
2784 width_ = width;
2785 hash_ = 0;
2786 check();
2787 }
2788
2789 RTLIL::SigSpec::SigSpec(std::vector<RTLIL::SigChunk> chunks)
2790 {
2791 cover("kernel.rtlil.sigspec.init.stdvec_chunks");
2792
2793 width_ = 0;
2794 hash_ = 0;
2795 for (auto &c : chunks)
2796 append(c);
2797 check();
2798 }
2799
2800 RTLIL::SigSpec::SigSpec(std::vector<RTLIL::SigBit> bits)
2801 {
2802 cover("kernel.rtlil.sigspec.init.stdvec_bits");
2803
2804 width_ = 0;
2805 hash_ = 0;
2806 for (auto &bit : bits)
2807 append_bit(bit);
2808 check();
2809 }
2810
2811 RTLIL::SigSpec::SigSpec(pool<RTLIL::SigBit> bits)
2812 {
2813 cover("kernel.rtlil.sigspec.init.pool_bits");
2814
2815 width_ = 0;
2816 hash_ = 0;
2817 for (auto &bit : bits)
2818 append_bit(bit);
2819 check();
2820 }
2821
2822 RTLIL::SigSpec::SigSpec(std::set<RTLIL::SigBit> bits)
2823 {
2824 cover("kernel.rtlil.sigspec.init.stdset_bits");
2825
2826 width_ = 0;
2827 hash_ = 0;
2828 for (auto &bit : bits)
2829 append_bit(bit);
2830 check();
2831 }
2832
2833 RTLIL::SigSpec::SigSpec(bool bit)
2834 {
2835 cover("kernel.rtlil.sigspec.init.bool");
2836
2837 width_ = 0;
2838 hash_ = 0;
2839 append_bit(bit);
2840 check();
2841 }
2842
2843 void RTLIL::SigSpec::pack() const
2844 {
2845 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
2846
2847 if (that->bits_.empty())
2848 return;
2849
2850 cover("kernel.rtlil.sigspec.convert.pack");
2851 log_assert(that->chunks_.empty());
2852
2853 std::vector<RTLIL::SigBit> old_bits;
2854 old_bits.swap(that->bits_);
2855
2856 RTLIL::SigChunk *last = NULL;
2857 int last_end_offset = 0;
2858
2859 for (auto &bit : old_bits) {
2860 if (last && bit.wire == last->wire) {
2861 if (bit.wire == NULL) {
2862 last->data.push_back(bit.data);
2863 last->width++;
2864 continue;
2865 } else if (last_end_offset == bit.offset) {
2866 last_end_offset++;
2867 last->width++;
2868 continue;
2869 }
2870 }
2871 that->chunks_.push_back(bit);
2872 last = &that->chunks_.back();
2873 last_end_offset = bit.offset + 1;
2874 }
2875
2876 check();
2877 }
2878
2879 void RTLIL::SigSpec::unpack() const
2880 {
2881 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
2882
2883 if (that->chunks_.empty())
2884 return;
2885
2886 cover("kernel.rtlil.sigspec.convert.unpack");
2887 log_assert(that->bits_.empty());
2888
2889 that->bits_.reserve(that->width_);
2890 for (auto &c : that->chunks_)
2891 for (int i = 0; i < c.width; i++)
2892 that->bits_.push_back(RTLIL::SigBit(c, i));
2893
2894 that->chunks_.clear();
2895 that->hash_ = 0;
2896 }
2897
2898 void RTLIL::SigSpec::updhash() const
2899 {
2900 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
2901
2902 if (that->hash_ != 0)
2903 return;
2904
2905 cover("kernel.rtlil.sigspec.hash");
2906 that->pack();
2907
2908 that->hash_ = mkhash_init;
2909 for (auto &c : that->chunks_)
2910 if (c.wire == NULL) {
2911 for (auto &v : c.data)
2912 that->hash_ = mkhash(that->hash_, v);
2913 } else {
2914 that->hash_ = mkhash(that->hash_, c.wire->name.index_);
2915 that->hash_ = mkhash(that->hash_, c.offset);
2916 that->hash_ = mkhash(that->hash_, c.width);
2917 }
2918
2919 if (that->hash_ == 0)
2920 that->hash_ = 1;
2921 }
2922
2923 void RTLIL::SigSpec::sort()
2924 {
2925 unpack();
2926 cover("kernel.rtlil.sigspec.sort");
2927 std::sort(bits_.begin(), bits_.end());
2928 }
2929
2930 void RTLIL::SigSpec::sort_and_unify()
2931 {
2932 unpack();
2933 cover("kernel.rtlil.sigspec.sort_and_unify");
2934
2935 // A copy of the bits vector is used to prevent duplicating the logic from
2936 // SigSpec::SigSpec(std::vector<SigBit>). This incurrs an extra copy but
2937 // that isn't showing up as significant in profiles.
2938 std::vector<SigBit> unique_bits = bits_;
2939 std::sort(unique_bits.begin(), unique_bits.end());
2940 auto last = std::unique(unique_bits.begin(), unique_bits.end());
2941 unique_bits.erase(last, unique_bits.end());
2942
2943 *this = unique_bits;
2944 }
2945
2946 void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with)
2947 {
2948 replace(pattern, with, this);
2949 }
2950
2951 void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with, RTLIL::SigSpec *other) const
2952 {
2953 log_assert(other != NULL);
2954 log_assert(width_ == other->width_);
2955 log_assert(pattern.width_ == with.width_);
2956
2957 pattern.unpack();
2958 with.unpack();
2959 unpack();
2960 other->unpack();
2961
2962 for (int i = 0; i < GetSize(pattern.bits_); i++) {
2963 if (pattern.bits_[i].wire != NULL) {
2964 for (int j = 0; j < GetSize(bits_); j++) {
2965 if (bits_[j] == pattern.bits_[i]) {
2966 other->bits_[j] = with.bits_[i];
2967 }
2968 }
2969 }
2970 }
2971
2972 other->check();
2973 }
2974
2975 void RTLIL::SigSpec::replace(const dict<RTLIL::SigBit, RTLIL::SigBit> &rules)
2976 {
2977 replace(rules, this);
2978 }
2979
2980 void RTLIL::SigSpec::replace(const dict<RTLIL::SigBit, RTLIL::SigBit> &rules, RTLIL::SigSpec *other) const
2981 {
2982 cover("kernel.rtlil.sigspec.replace_dict");
2983
2984 log_assert(other != NULL);
2985 log_assert(width_ == other->width_);
2986
2987 unpack();
2988 other->unpack();
2989
2990 for (int i = 0; i < GetSize(bits_); i++) {
2991 auto it = rules.find(bits_[i]);
2992 if (it != rules.end())
2993 other->bits_[i] = it->second;
2994 }
2995
2996 other->check();
2997 }
2998
2999 void RTLIL::SigSpec::replace(const std::map<RTLIL::SigBit, RTLIL::SigBit> &rules)
3000 {
3001 replace(rules, this);
3002 }
3003
3004 void RTLIL::SigSpec::replace(const std::map<RTLIL::SigBit, RTLIL::SigBit> &rules, RTLIL::SigSpec *other) const
3005 {
3006 cover("kernel.rtlil.sigspec.replace_map");
3007
3008 log_assert(other != NULL);
3009 log_assert(width_ == other->width_);
3010
3011 unpack();
3012 other->unpack();
3013
3014 for (int i = 0; i < GetSize(bits_); i++) {
3015 auto it = rules.find(bits_[i]);
3016 if (it != rules.end())
3017 other->bits_[i] = it->second;
3018 }
3019
3020 other->check();
3021 }
3022
3023 void RTLIL::SigSpec::remove(const RTLIL::SigSpec &pattern)
3024 {
3025 remove2(pattern, NULL);
3026 }
3027
3028 void RTLIL::SigSpec::remove(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other) const
3029 {
3030 RTLIL::SigSpec tmp = *this;
3031 tmp.remove2(pattern, other);
3032 }
3033
3034 void RTLIL::SigSpec::remove2(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other)
3035 {
3036 if (other)
3037 cover("kernel.rtlil.sigspec.remove_other");
3038 else
3039 cover("kernel.rtlil.sigspec.remove");
3040
3041 unpack();
3042 if (other != NULL) {
3043 log_assert(width_ == other->width_);
3044 other->unpack();
3045 }
3046
3047 for (int i = GetSize(bits_) - 1; i >= 0; i--)
3048 {
3049 if (bits_[i].wire == NULL) continue;
3050
3051 for (auto &pattern_chunk : pattern.chunks())
3052 if (bits_[i].wire == pattern_chunk.wire &&
3053 bits_[i].offset >= pattern_chunk.offset &&
3054 bits_[i].offset < pattern_chunk.offset + pattern_chunk.width) {
3055 bits_.erase(bits_.begin() + i);
3056 width_--;
3057 if (other != NULL) {
3058 other->bits_.erase(other->bits_.begin() + i);
3059 other->width_--;
3060 }
3061 break;
3062 }
3063 }
3064
3065 check();
3066 }
3067
3068 void RTLIL::SigSpec::remove(const pool<RTLIL::SigBit> &pattern)
3069 {
3070 remove2(pattern, NULL);
3071 }
3072
3073 void RTLIL::SigSpec::remove(const pool<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other) const
3074 {
3075 RTLIL::SigSpec tmp = *this;
3076 tmp.remove2(pattern, other);
3077 }
3078
3079 void RTLIL::SigSpec::remove2(const pool<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other)
3080 {
3081 if (other)
3082 cover("kernel.rtlil.sigspec.remove_other");
3083 else
3084 cover("kernel.rtlil.sigspec.remove");
3085
3086 unpack();
3087
3088 if (other != NULL) {
3089 log_assert(width_ == other->width_);
3090 other->unpack();
3091 }
3092
3093 for (int i = GetSize(bits_) - 1; i >= 0; i--) {
3094 if (bits_[i].wire != NULL && pattern.count(bits_[i])) {
3095 bits_.erase(bits_.begin() + i);
3096 width_--;
3097 if (other != NULL) {
3098 other->bits_.erase(other->bits_.begin() + i);
3099 other->width_--;
3100 }
3101 }
3102 }
3103
3104 check();
3105 }
3106
3107 void RTLIL::SigSpec::remove2(const std::set<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other)
3108 {
3109 if (other)
3110 cover("kernel.rtlil.sigspec.remove_other");
3111 else
3112 cover("kernel.rtlil.sigspec.remove");
3113
3114 unpack();
3115
3116 if (other != NULL) {
3117 log_assert(width_ == other->width_);
3118 other->unpack();
3119 }
3120
3121 for (int i = GetSize(bits_) - 1; i >= 0; i--) {
3122 if (bits_[i].wire != NULL && pattern.count(bits_[i])) {
3123 bits_.erase(bits_.begin() + i);
3124 width_--;
3125 if (other != NULL) {
3126 other->bits_.erase(other->bits_.begin() + i);
3127 other->width_--;
3128 }
3129 }
3130 }
3131
3132 check();
3133 }
3134
3135 RTLIL::SigSpec RTLIL::SigSpec::extract(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec *other) const
3136 {
3137 if (other)
3138 cover("kernel.rtlil.sigspec.extract_other");
3139 else
3140 cover("kernel.rtlil.sigspec.extract");
3141
3142 log_assert(other == NULL || width_ == other->width_);
3143
3144 RTLIL::SigSpec ret;
3145 std::vector<RTLIL::SigBit> bits_match = to_sigbit_vector();
3146
3147 for (auto& pattern_chunk : pattern.chunks()) {
3148 if (other) {
3149 std::vector<RTLIL::SigBit> bits_other = other->to_sigbit_vector();
3150 for (int i = 0; i < width_; i++)
3151 if (bits_match[i].wire &&
3152 bits_match[i].wire == pattern_chunk.wire &&
3153 bits_match[i].offset >= pattern_chunk.offset &&
3154 bits_match[i].offset < pattern_chunk.offset + pattern_chunk.width)
3155 ret.append_bit(bits_other[i]);
3156 } else {
3157 for (int i = 0; i < width_; i++)
3158 if (bits_match[i].wire &&
3159 bits_match[i].wire == pattern_chunk.wire &&
3160 bits_match[i].offset >= pattern_chunk.offset &&
3161 bits_match[i].offset < pattern_chunk.offset + pattern_chunk.width)
3162 ret.append_bit(bits_match[i]);
3163 }
3164 }
3165
3166 ret.check();
3167 return ret;
3168 }
3169
3170 RTLIL::SigSpec RTLIL::SigSpec::extract(const pool<RTLIL::SigBit> &pattern, const RTLIL::SigSpec *other) const
3171 {
3172 if (other)
3173 cover("kernel.rtlil.sigspec.extract_other");
3174 else
3175 cover("kernel.rtlil.sigspec.extract");
3176
3177 log_assert(other == NULL || width_ == other->width_);
3178
3179 std::vector<RTLIL::SigBit> bits_match = to_sigbit_vector();
3180 RTLIL::SigSpec ret;
3181
3182 if (other) {
3183 std::vector<RTLIL::SigBit> bits_other = other->to_sigbit_vector();
3184 for (int i = 0; i < width_; i++)
3185 if (bits_match[i].wire && pattern.count(bits_match[i]))
3186 ret.append_bit(bits_other[i]);
3187 } else {
3188 for (int i = 0; i < width_; i++)
3189 if (bits_match[i].wire && pattern.count(bits_match[i]))
3190 ret.append_bit(bits_match[i]);
3191 }
3192
3193 ret.check();
3194 return ret;
3195 }
3196
3197 void RTLIL::SigSpec::replace(int offset, const RTLIL::SigSpec &with)
3198 {
3199 cover("kernel.rtlil.sigspec.replace_pos");
3200
3201 unpack();
3202 with.unpack();
3203
3204 log_assert(offset >= 0);
3205 log_assert(with.width_ >= 0);
3206 log_assert(offset+with.width_ <= width_);
3207
3208 for (int i = 0; i < with.width_; i++)
3209 bits_.at(offset + i) = with.bits_.at(i);
3210
3211 check();
3212 }
3213
3214 void RTLIL::SigSpec::remove_const()
3215 {
3216 if (packed())
3217 {
3218 cover("kernel.rtlil.sigspec.remove_const.packed");
3219
3220 std::vector<RTLIL::SigChunk> new_chunks;
3221 new_chunks.reserve(GetSize(chunks_));
3222
3223 width_ = 0;
3224 for (auto &chunk : chunks_)
3225 if (chunk.wire != NULL) {
3226 new_chunks.push_back(chunk);
3227 width_ += chunk.width;
3228 }
3229
3230 chunks_.swap(new_chunks);
3231 }
3232 else
3233 {
3234 cover("kernel.rtlil.sigspec.remove_const.unpacked");
3235
3236 std::vector<RTLIL::SigBit> new_bits;
3237 new_bits.reserve(width_);
3238
3239 for (auto &bit : bits_)
3240 if (bit.wire != NULL)
3241 new_bits.push_back(bit);
3242
3243 bits_.swap(new_bits);
3244 width_ = bits_.size();
3245 }
3246
3247 check();
3248 }
3249
3250 void RTLIL::SigSpec::remove(int offset, int length)
3251 {
3252 cover("kernel.rtlil.sigspec.remove_pos");
3253
3254 unpack();
3255
3256 log_assert(offset >= 0);
3257 log_assert(length >= 0);
3258 log_assert(offset + length <= width_);
3259
3260 bits_.erase(bits_.begin() + offset, bits_.begin() + offset + length);
3261 width_ = bits_.size();
3262
3263 check();
3264 }
3265
3266 RTLIL::SigSpec RTLIL::SigSpec::extract(int offset, int length) const
3267 {
3268 unpack();
3269 cover("kernel.rtlil.sigspec.extract_pos");
3270 return std::vector<RTLIL::SigBit>(bits_.begin() + offset, bits_.begin() + offset + length);
3271 }
3272
3273 void RTLIL::SigSpec::append(const RTLIL::SigSpec &signal)
3274 {
3275 if (signal.width_ == 0)
3276 return;
3277
3278 if (width_ == 0) {
3279 *this = signal;
3280 return;
3281 }
3282
3283 cover("kernel.rtlil.sigspec.append");
3284
3285 if (packed() != signal.packed()) {
3286 pack();
3287 signal.pack();
3288 }
3289
3290 if (packed())
3291 for (auto &other_c : signal.chunks_)
3292 {
3293 auto &my_last_c = chunks_.back();
3294 if (my_last_c.wire == NULL && other_c.wire == NULL) {
3295 auto &this_data = my_last_c.data;
3296 auto &other_data = other_c.data;
3297 this_data.insert(this_data.end(), other_data.begin(), other_data.end());
3298 my_last_c.width += other_c.width;
3299 } else
3300 if (my_last_c.wire == other_c.wire && my_last_c.offset + my_last_c.width == other_c.offset) {
3301 my_last_c.width += other_c.width;
3302 } else
3303 chunks_.push_back(other_c);
3304 }
3305 else
3306 bits_.insert(bits_.end(), signal.bits_.begin(), signal.bits_.end());
3307
3308 width_ += signal.width_;
3309 check();
3310 }
3311
3312 void RTLIL::SigSpec::append_bit(const RTLIL::SigBit &bit)
3313 {
3314 if (packed())
3315 {
3316 cover("kernel.rtlil.sigspec.append_bit.packed");
3317
3318 if (chunks_.size() == 0)
3319 chunks_.push_back(bit);
3320 else
3321 if (bit.wire == NULL)
3322 if (chunks_.back().wire == NULL) {
3323 chunks_.back().data.push_back(bit.data);
3324 chunks_.back().width++;
3325 } else
3326 chunks_.push_back(bit);
3327 else
3328 if (chunks_.back().wire == bit.wire && chunks_.back().offset + chunks_.back().width == bit.offset)
3329 chunks_.back().width++;
3330 else
3331 chunks_.push_back(bit);
3332 }
3333 else
3334 {
3335 cover("kernel.rtlil.sigspec.append_bit.unpacked");
3336 bits_.push_back(bit);
3337 }
3338
3339 width_++;
3340 check();
3341 }
3342
3343 void RTLIL::SigSpec::extend_u0(int width, bool is_signed)
3344 {
3345 cover("kernel.rtlil.sigspec.extend_u0");
3346
3347 pack();
3348
3349 if (width_ > width)
3350 remove(width, width_ - width);
3351
3352 if (width_ < width) {
3353 RTLIL::SigBit padding = width_ > 0 ? (*this)[width_ - 1] : RTLIL::State::Sx;
3354 if (!is_signed)
3355 padding = RTLIL::State::S0;
3356 while (width_ < width)
3357 append(padding);
3358 }
3359
3360 }
3361
3362 RTLIL::SigSpec RTLIL::SigSpec::repeat(int num) const
3363 {
3364 cover("kernel.rtlil.sigspec.repeat");
3365
3366 RTLIL::SigSpec sig;
3367 for (int i = 0; i < num; i++)
3368 sig.append(*this);
3369 return sig;
3370 }
3371
3372 #ifndef NDEBUG
3373 void RTLIL::SigSpec::check() const
3374 {
3375 if (width_ > 64)
3376 {
3377 cover("kernel.rtlil.sigspec.check.skip");
3378 }
3379 else if (packed())
3380 {
3381 cover("kernel.rtlil.sigspec.check.packed");
3382
3383 int w = 0;
3384 for (size_t i = 0; i < chunks_.size(); i++) {
3385 const RTLIL::SigChunk chunk = chunks_[i];
3386 if (chunk.wire == NULL) {
3387 if (i > 0)
3388 log_assert(chunks_[i-1].wire != NULL);
3389 log_assert(chunk.offset == 0);
3390 log_assert(chunk.data.size() == (size_t)chunk.width);
3391 } else {
3392 if (i > 0 && chunks_[i-1].wire == chunk.wire)
3393 log_assert(chunk.offset != chunks_[i-1].offset + chunks_[i-1].width);
3394 log_assert(chunk.offset >= 0);
3395 log_assert(chunk.width >= 0);
3396 log_assert(chunk.offset + chunk.width <= chunk.wire->width);
3397 log_assert(chunk.data.size() == 0);
3398 }
3399 w += chunk.width;
3400 }
3401 log_assert(w == width_);
3402 log_assert(bits_.empty());
3403 }
3404 else
3405 {
3406 cover("kernel.rtlil.sigspec.check.unpacked");
3407
3408 log_assert(width_ == GetSize(bits_));
3409 log_assert(chunks_.empty());
3410 }
3411 }
3412 #endif
3413
3414 bool RTLIL::SigSpec::operator <(const RTLIL::SigSpec &other) const
3415 {
3416 cover("kernel.rtlil.sigspec.comp_lt");
3417
3418 if (this == &other)
3419 return false;
3420
3421 if (width_ != other.width_)
3422 return width_ < other.width_;
3423
3424 pack();
3425 other.pack();
3426
3427 if (chunks_.size() != other.chunks_.size())
3428 return chunks_.size() < other.chunks_.size();
3429
3430 updhash();
3431 other.updhash();
3432
3433 if (hash_ != other.hash_)
3434 return hash_ < other.hash_;
3435
3436 for (size_t i = 0; i < chunks_.size(); i++)
3437 if (chunks_[i] != other.chunks_[i]) {
3438 cover("kernel.rtlil.sigspec.comp_lt.hash_collision");
3439 return chunks_[i] < other.chunks_[i];
3440 }
3441
3442 cover("kernel.rtlil.sigspec.comp_lt.equal");
3443 return false;
3444 }
3445
3446 bool RTLIL::SigSpec::operator ==(const RTLIL::SigSpec &other) const
3447 {
3448 cover("kernel.rtlil.sigspec.comp_eq");
3449
3450 if (this == &other)
3451 return true;
3452
3453 if (width_ != other.width_)
3454 return false;
3455
3456 pack();
3457 other.pack();
3458
3459 if (chunks_.size() != other.chunks_.size())
3460 return false;
3461
3462 updhash();
3463 other.updhash();
3464
3465 if (hash_ != other.hash_)
3466 return false;
3467
3468 for (size_t i = 0; i < chunks_.size(); i++)
3469 if (chunks_[i] != other.chunks_[i]) {
3470 cover("kernel.rtlil.sigspec.comp_eq.hash_collision");
3471 return false;
3472 }
3473
3474 cover("kernel.rtlil.sigspec.comp_eq.equal");
3475 return true;
3476 }
3477
3478 bool RTLIL::SigSpec::is_wire() const
3479 {
3480 cover("kernel.rtlil.sigspec.is_wire");
3481
3482 pack();
3483 return GetSize(chunks_) == 1 && chunks_[0].wire && chunks_[0].wire->width == width_;
3484 }
3485
3486 bool RTLIL::SigSpec::is_chunk() const
3487 {
3488 cover("kernel.rtlil.sigspec.is_chunk");
3489
3490 pack();
3491 return GetSize(chunks_) == 1;
3492 }
3493
3494 bool RTLIL::SigSpec::is_fully_const() const
3495 {
3496 cover("kernel.rtlil.sigspec.is_fully_const");
3497
3498 pack();
3499 for (auto it = chunks_.begin(); it != chunks_.end(); it++)
3500 if (it->width > 0 && it->wire != NULL)
3501 return false;
3502 return true;
3503 }
3504
3505 bool RTLIL::SigSpec::is_fully_zero() const
3506 {
3507 cover("kernel.rtlil.sigspec.is_fully_zero");
3508
3509 pack();
3510 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
3511 if (it->width > 0 && it->wire != NULL)
3512 return false;
3513 for (size_t i = 0; i < it->data.size(); i++)
3514 if (it->data[i] != RTLIL::State::S0)
3515 return false;
3516 }
3517 return true;
3518 }
3519
3520 bool RTLIL::SigSpec::is_fully_ones() const
3521 {
3522 cover("kernel.rtlil.sigspec.is_fully_ones");
3523
3524 pack();
3525 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
3526 if (it->width > 0 && it->wire != NULL)
3527 return false;
3528 for (size_t i = 0; i < it->data.size(); i++)
3529 if (it->data[i] != RTLIL::State::S1)
3530 return false;
3531 }
3532 return true;
3533 }
3534
3535 bool RTLIL::SigSpec::is_fully_def() const
3536 {
3537 cover("kernel.rtlil.sigspec.is_fully_def");
3538
3539 pack();
3540 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
3541 if (it->width > 0 && it->wire != NULL)
3542 return false;
3543 for (size_t i = 0; i < it->data.size(); i++)
3544 if (it->data[i] != RTLIL::State::S0 && it->data[i] != RTLIL::State::S1)
3545 return false;
3546 }
3547 return true;
3548 }
3549
3550 bool RTLIL::SigSpec::is_fully_undef() const
3551 {
3552 cover("kernel.rtlil.sigspec.is_fully_undef");
3553
3554 pack();
3555 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
3556 if (it->width > 0 && it->wire != NULL)
3557 return false;
3558 for (size_t i = 0; i < it->data.size(); i++)
3559 if (it->data[i] != RTLIL::State::Sx && it->data[i] != RTLIL::State::Sz)
3560 return false;
3561 }
3562 return true;
3563 }
3564
3565 bool RTLIL::SigSpec::has_const() const
3566 {
3567 cover("kernel.rtlil.sigspec.has_const");
3568
3569 pack();
3570 for (auto it = chunks_.begin(); it != chunks_.end(); it++)
3571 if (it->width > 0 && it->wire == NULL)
3572 return true;
3573 return false;
3574 }
3575
3576 bool RTLIL::SigSpec::has_marked_bits() const
3577 {
3578 cover("kernel.rtlil.sigspec.has_marked_bits");
3579
3580 pack();
3581 for (auto it = chunks_.begin(); it != chunks_.end(); it++)
3582 if (it->width > 0 && it->wire == NULL) {
3583 for (size_t i = 0; i < it->data.size(); i++)
3584 if (it->data[i] == RTLIL::State::Sm)
3585 return true;
3586 }
3587 return false;
3588 }
3589
3590 bool RTLIL::SigSpec::as_bool() const
3591 {
3592 cover("kernel.rtlil.sigspec.as_bool");
3593
3594 pack();
3595 log_assert(is_fully_const() && GetSize(chunks_) <= 1);
3596 if (width_)
3597 return RTLIL::Const(chunks_[0].data).as_bool();
3598 return false;
3599 }
3600
3601 int RTLIL::SigSpec::as_int(bool is_signed) const
3602 {
3603 cover("kernel.rtlil.sigspec.as_int");
3604
3605 pack();
3606 log_assert(is_fully_const() && GetSize(chunks_) <= 1);
3607 if (width_)
3608 return RTLIL::Const(chunks_[0].data).as_int(is_signed);
3609 return 0;
3610 }
3611
3612 std::string RTLIL::SigSpec::as_string() const
3613 {
3614 cover("kernel.rtlil.sigspec.as_string");
3615
3616 pack();
3617 std::string str;
3618 for (size_t i = chunks_.size(); i > 0; i--) {
3619 const RTLIL::SigChunk &chunk = chunks_[i-1];
3620 if (chunk.wire != NULL)
3621 for (int j = 0; j < chunk.width; j++)
3622 str += "?";
3623 else
3624 str += RTLIL::Const(chunk.data).as_string();
3625 }
3626 return str;
3627 }
3628
3629 RTLIL::Const RTLIL::SigSpec::as_const() const
3630 {
3631 cover("kernel.rtlil.sigspec.as_const");
3632
3633 pack();
3634 log_assert(is_fully_const() && GetSize(chunks_) <= 1);
3635 if (width_)
3636 return chunks_[0].data;
3637 return RTLIL::Const();
3638 }
3639
3640 RTLIL::Wire *RTLIL::SigSpec::as_wire() const
3641 {
3642 cover("kernel.rtlil.sigspec.as_wire");
3643
3644 pack();
3645 log_assert(is_wire());
3646 return chunks_[0].wire;
3647 }
3648
3649 RTLIL::SigChunk RTLIL::SigSpec::as_chunk() const
3650 {
3651 cover("kernel.rtlil.sigspec.as_chunk");
3652
3653 pack();
3654 log_assert(is_chunk());
3655 return chunks_[0];
3656 }
3657
3658 RTLIL::SigBit RTLIL::SigSpec::as_bit() const
3659 {
3660 cover("kernel.rtlil.sigspec.as_bit");
3661
3662 log_assert(width_ == 1);
3663 if (packed())
3664 return RTLIL::SigBit(*chunks_.begin());
3665 else
3666 return bits_[0];
3667 }
3668
3669 bool RTLIL::SigSpec::match(std::string pattern) const
3670 {
3671 cover("kernel.rtlil.sigspec.match");
3672
3673 pack();
3674 std::string str = as_string();
3675 log_assert(pattern.size() == str.size());
3676
3677 for (size_t i = 0; i < pattern.size(); i++) {
3678 if (pattern[i] == ' ')
3679 continue;
3680 if (pattern[i] == '*') {
3681 if (str[i] != 'z' && str[i] != 'x')
3682 return false;
3683 continue;
3684 }
3685 if (pattern[i] != str[i])
3686 return false;
3687 }
3688
3689 return true;
3690 }
3691
3692 std::set<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_set() const
3693 {
3694 cover("kernel.rtlil.sigspec.to_sigbit_set");
3695
3696 pack();
3697 std::set<RTLIL::SigBit> sigbits;
3698 for (auto &c : chunks_)
3699 for (int i = 0; i < c.width; i++)
3700 sigbits.insert(RTLIL::SigBit(c, i));
3701 return sigbits;
3702 }
3703
3704 pool<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_pool() const
3705 {
3706 cover("kernel.rtlil.sigspec.to_sigbit_pool");
3707
3708 pack();
3709 pool<RTLIL::SigBit> sigbits;
3710 for (auto &c : chunks_)
3711 for (int i = 0; i < c.width; i++)
3712 sigbits.insert(RTLIL::SigBit(c, i));
3713 return sigbits;
3714 }
3715
3716 std::vector<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_vector() const
3717 {
3718 cover("kernel.rtlil.sigspec.to_sigbit_vector");
3719
3720 unpack();
3721 return bits_;
3722 }
3723
3724 std::map<RTLIL::SigBit, RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_map(const RTLIL::SigSpec &other) const
3725 {
3726 cover("kernel.rtlil.sigspec.to_sigbit_map");
3727
3728 unpack();
3729 other.unpack();
3730
3731 log_assert(width_ == other.width_);
3732
3733 std::map<RTLIL::SigBit, RTLIL::SigBit> new_map;
3734 for (int i = 0; i < width_; i++)
3735 new_map[bits_[i]] = other.bits_[i];
3736
3737 return new_map;
3738 }
3739
3740 dict<RTLIL::SigBit, RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_dict(const RTLIL::SigSpec &other) const
3741 {
3742 cover("kernel.rtlil.sigspec.to_sigbit_dict");
3743
3744 unpack();
3745 other.unpack();
3746
3747 log_assert(width_ == other.width_);
3748
3749 dict<RTLIL::SigBit, RTLIL::SigBit> new_map;
3750 for (int i = 0; i < width_; i++)
3751 new_map[bits_[i]] = other.bits_[i];
3752
3753 return new_map;
3754 }
3755
3756 static void sigspec_parse_split(std::vector<std::string> &tokens, const std::string &text, char sep)
3757 {
3758 size_t start = 0, end = 0;
3759 while ((end = text.find(sep, start)) != std::string::npos) {
3760 tokens.push_back(text.substr(start, end - start));
3761 start = end + 1;
3762 }
3763 tokens.push_back(text.substr(start));
3764 }
3765
3766 static int sigspec_parse_get_dummy_line_num()
3767 {
3768 return 0;
3769 }
3770
3771 bool RTLIL::SigSpec::parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str)
3772 {
3773 cover("kernel.rtlil.sigspec.parse");
3774
3775 AST::current_filename = "input";
3776 AST::use_internal_line_num();
3777 AST::set_line_num(0);
3778
3779 std::vector<std::string> tokens;
3780 sigspec_parse_split(tokens, str, ',');
3781
3782 sig = RTLIL::SigSpec();
3783 for (int tokidx = int(tokens.size())-1; tokidx >= 0; tokidx--)
3784 {
3785 std::string netname = tokens[tokidx];
3786 std::string indices;
3787
3788 if (netname.size() == 0)
3789 continue;
3790
3791 if (('0' <= netname[0] && netname[0] <= '9') || netname[0] == '\'') {
3792 cover("kernel.rtlil.sigspec.parse.const");
3793 AST::get_line_num = sigspec_parse_get_dummy_line_num;
3794 AST::AstNode *ast = VERILOG_FRONTEND::const2ast(netname);
3795 if (ast == NULL)
3796 return false;
3797 sig.append(RTLIL::Const(ast->bits));
3798 delete ast;
3799 continue;
3800 }
3801
3802 if (module == NULL)
3803 return false;
3804
3805 cover("kernel.rtlil.sigspec.parse.net");
3806
3807 if (netname[0] != '$' && netname[0] != '\\')
3808 netname = "\\" + netname;
3809
3810 if (module->wires_.count(netname) == 0) {
3811 size_t indices_pos = netname.size()-1;
3812 if (indices_pos > 2 && netname[indices_pos] == ']')
3813 {
3814 indices_pos--;
3815 while (indices_pos > 0 && ('0' <= netname[indices_pos] && netname[indices_pos] <= '9')) indices_pos--;
3816 if (indices_pos > 0 && netname[indices_pos] == ':') {
3817 indices_pos--;
3818 while (indices_pos > 0 && ('0' <= netname[indices_pos] && netname[indices_pos] <= '9')) indices_pos--;
3819 }
3820 if (indices_pos > 0 && netname[indices_pos] == '[') {
3821 indices = netname.substr(indices_pos);
3822 netname = netname.substr(0, indices_pos);
3823 }
3824 }
3825 }
3826
3827 if (module->wires_.count(netname) == 0)
3828 return false;
3829
3830 RTLIL::Wire *wire = module->wires_.at(netname);
3831 if (!indices.empty()) {
3832 std::vector<std::string> index_tokens;
3833 sigspec_parse_split(index_tokens, indices.substr(1, indices.size()-2), ':');
3834 if (index_tokens.size() == 1) {
3835 cover("kernel.rtlil.sigspec.parse.bit_sel");
3836 int a = atoi(index_tokens.at(0).c_str());
3837 if (a < 0 || a >= wire->width)
3838 return false;
3839 sig.append(RTLIL::SigSpec(wire, a));
3840 } else {
3841 cover("kernel.rtlil.sigspec.parse.part_sel");
3842 int a = atoi(index_tokens.at(0).c_str());
3843 int b = atoi(index_tokens.at(1).c_str());
3844 if (a > b) {
3845 int tmp = a;
3846 a = b, b = tmp;
3847 }
3848 if (a < 0 || a >= wire->width)
3849 return false;
3850 if (b < 0 || b >= wire->width)
3851 return false;
3852 sig.append(RTLIL::SigSpec(wire, a, b-a+1));
3853 }
3854 } else
3855 sig.append(wire);
3856 }
3857
3858 return true;
3859 }
3860
3861 bool RTLIL::SigSpec::parse_sel(RTLIL::SigSpec &sig, RTLIL::Design *design, RTLIL::Module *module, std::string str)
3862 {
3863 if (str.empty() || str[0] != '@')
3864 return parse(sig, module, str);
3865
3866 cover("kernel.rtlil.sigspec.parse.sel");
3867
3868 str = RTLIL::escape_id(str.substr(1));
3869 if (design->selection_vars.count(str) == 0)
3870 return false;
3871
3872 sig = RTLIL::SigSpec();
3873 RTLIL::Selection &sel = design->selection_vars.at(str);
3874 for (auto &it : module->wires_)
3875 if (sel.selected_member(module->name, it.first))
3876 sig.append(it.second);
3877
3878 return true;
3879 }
3880
3881 bool RTLIL::SigSpec::parse_rhs(const RTLIL::SigSpec &lhs, RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str)
3882 {
3883 if (str == "0") {
3884 cover("kernel.rtlil.sigspec.parse.rhs_zeros");
3885 sig = RTLIL::SigSpec(RTLIL::State::S0, lhs.width_);
3886 return true;
3887 }
3888
3889 if (str == "~0") {
3890 cover("kernel.rtlil.sigspec.parse.rhs_ones");
3891 sig = RTLIL::SigSpec(RTLIL::State::S1, lhs.width_);
3892 return true;
3893 }
3894
3895 if (lhs.chunks_.size() == 1) {
3896 char *p = (char*)str.c_str(), *endptr;
3897 long int val = strtol(p, &endptr, 10);
3898 if (endptr && endptr != p && *endptr == 0) {
3899 sig = RTLIL::SigSpec(val, lhs.width_);
3900 cover("kernel.rtlil.sigspec.parse.rhs_dec");
3901 return true;
3902 }
3903 }
3904
3905 return parse(sig, module, str);
3906 }
3907
3908 RTLIL::CaseRule::~CaseRule()
3909 {
3910 for (auto it = switches.begin(); it != switches.end(); it++)
3911 delete *it;
3912 }
3913
3914 bool RTLIL::CaseRule::empty() const
3915 {
3916 return actions.empty() && switches.empty();
3917 }
3918
3919 RTLIL::CaseRule *RTLIL::CaseRule::clone() const
3920 {
3921 RTLIL::CaseRule *new_caserule = new RTLIL::CaseRule;
3922 new_caserule->compare = compare;
3923 new_caserule->actions = actions;
3924 for (auto &it : switches)
3925 new_caserule->switches.push_back(it->clone());
3926 return new_caserule;
3927 }
3928
3929 RTLIL::SwitchRule::~SwitchRule()
3930 {
3931 for (auto it = cases.begin(); it != cases.end(); it++)
3932 delete *it;
3933 }
3934
3935 bool RTLIL::SwitchRule::empty() const
3936 {
3937 return cases.empty();
3938 }
3939
3940 RTLIL::SwitchRule *RTLIL::SwitchRule::clone() const
3941 {
3942 RTLIL::SwitchRule *new_switchrule = new RTLIL::SwitchRule;
3943 new_switchrule->signal = signal;
3944 new_switchrule->attributes = attributes;
3945 for (auto &it : cases)
3946 new_switchrule->cases.push_back(it->clone());
3947 return new_switchrule;
3948
3949 }
3950
3951 RTLIL::SyncRule *RTLIL::SyncRule::clone() const
3952 {
3953 RTLIL::SyncRule *new_syncrule = new RTLIL::SyncRule;
3954 new_syncrule->type = type;
3955 new_syncrule->signal = signal;
3956 new_syncrule->actions = actions;
3957 return new_syncrule;
3958 }
3959
3960 RTLIL::Process::~Process()
3961 {
3962 for (auto it = syncs.begin(); it != syncs.end(); it++)
3963 delete *it;
3964 }
3965
3966 RTLIL::Process *RTLIL::Process::clone() const
3967 {
3968 RTLIL::Process *new_proc = new RTLIL::Process;
3969
3970 new_proc->name = name;
3971 new_proc->attributes = attributes;
3972
3973 RTLIL::CaseRule *rc_ptr = root_case.clone();
3974 new_proc->root_case = *rc_ptr;
3975 rc_ptr->switches.clear();
3976 delete rc_ptr;
3977
3978 for (auto &it : syncs)
3979 new_proc->syncs.push_back(it->clone());
3980
3981 return new_proc;
3982 }
3983
3984 #ifdef WITH_PYTHON
3985 RTLIL::Memory::~Memory()
3986 {
3987 RTLIL::Memory::get_all_memorys()->erase(hashidx_);
3988 }
3989 static std::map<unsigned int, RTLIL::Memory*> all_memorys;
3990 std::map<unsigned int, RTLIL::Memory*> *RTLIL::Memory::get_all_memorys(void)
3991 {
3992 return &all_memorys;
3993 }
3994 #endif
3995 YOSYS_NAMESPACE_END