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Added $shift and $shiftx cell types (needed for correct part select behavior)
[yosys.git] / kernel / rtlil.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 #include "kernel/compatibility.h"
21 #include "kernel/rtlil.h"
22 #include "kernel/log.h"
23 #include "frontends/verilog/verilog_frontend.h"
24 #include "backends/ilang/ilang_backend.h"
25
26 #include <string.h>
27 #include <algorithm>
28
29 int RTLIL::autoidx = 1;
30
31 RTLIL::Const::Const()
32 {
33 flags = RTLIL::CONST_FLAG_NONE;
34 }
35
36 RTLIL::Const::Const(std::string str)
37 {
38 flags = RTLIL::CONST_FLAG_STRING;
39 for (int i = str.size()-1; i >= 0; i--) {
40 unsigned char ch = str[i];
41 for (int j = 0; j < 8; j++) {
42 bits.push_back((ch & 1) != 0 ? RTLIL::S1 : RTLIL::S0);
43 ch = ch >> 1;
44 }
45 }
46 }
47
48 RTLIL::Const::Const(int val, int width)
49 {
50 flags = RTLIL::CONST_FLAG_NONE;
51 for (int i = 0; i < width; i++) {
52 bits.push_back((val & 1) != 0 ? RTLIL::S1 : RTLIL::S0);
53 val = val >> 1;
54 }
55 }
56
57 RTLIL::Const::Const(RTLIL::State bit, int width)
58 {
59 flags = RTLIL::CONST_FLAG_NONE;
60 for (int i = 0; i < width; i++)
61 bits.push_back(bit);
62 }
63
64 bool RTLIL::Const::operator <(const RTLIL::Const &other) const
65 {
66 if (bits.size() != other.bits.size())
67 return bits.size() < other.bits.size();
68 for (size_t i = 0; i < bits.size(); i++)
69 if (bits[i] != other.bits[i])
70 return bits[i] < other.bits[i];
71 return false;
72 }
73
74 bool RTLIL::Const::operator ==(const RTLIL::Const &other) const
75 {
76 return bits == other.bits;
77 }
78
79 bool RTLIL::Const::operator !=(const RTLIL::Const &other) const
80 {
81 return bits != other.bits;
82 }
83
84 bool RTLIL::Const::as_bool() const
85 {
86 for (size_t i = 0; i < bits.size(); i++)
87 if (bits[i] == RTLIL::S1)
88 return true;
89 return false;
90 }
91
92 int RTLIL::Const::as_int() const
93 {
94 int ret = 0;
95 for (size_t i = 0; i < bits.size() && i < 32; i++)
96 if (bits[i] == RTLIL::S1)
97 ret |= 1 << i;
98 return ret;
99 }
100
101 std::string RTLIL::Const::as_string() const
102 {
103 std::string ret;
104 for (size_t i = bits.size(); i > 0; i--)
105 switch (bits[i-1]) {
106 case S0: ret += "0"; break;
107 case S1: ret += "1"; break;
108 case Sx: ret += "x"; break;
109 case Sz: ret += "z"; break;
110 case Sa: ret += "-"; break;
111 case Sm: ret += "m"; break;
112 }
113 return ret;
114 }
115
116 std::string RTLIL::Const::decode_string() const
117 {
118 std::string string;
119 std::vector <char> string_chars;
120 for (int i = 0; i < int (bits.size()); i += 8) {
121 char ch = 0;
122 for (int j = 0; j < 8 && i + j < int (bits.size()); j++)
123 if (bits[i + j] == RTLIL::State::S1)
124 ch |= 1 << j;
125 if (ch != 0)
126 string_chars.push_back(ch);
127 }
128 for (int i = int (string_chars.size()) - 1; i >= 0; i--)
129 string += string_chars[i];
130 return string;
131 }
132
133 bool RTLIL::Selection::selected_module(RTLIL::IdString mod_name) const
134 {
135 if (full_selection)
136 return true;
137 if (selected_modules.count(mod_name) > 0)
138 return true;
139 if (selected_members.count(mod_name) > 0)
140 return true;
141 return false;
142 }
143
144 bool RTLIL::Selection::selected_whole_module(RTLIL::IdString mod_name) const
145 {
146 if (full_selection)
147 return true;
148 if (selected_modules.count(mod_name) > 0)
149 return true;
150 return false;
151 }
152
153 bool RTLIL::Selection::selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const
154 {
155 if (full_selection)
156 return true;
157 if (selected_modules.count(mod_name) > 0)
158 return true;
159 if (selected_members.count(mod_name) > 0)
160 if (selected_members.at(mod_name).count(memb_name) > 0)
161 return true;
162 return false;
163 }
164
165 void RTLIL::Selection::optimize(RTLIL::Design *design)
166 {
167 if (full_selection) {
168 selected_modules.clear();
169 selected_members.clear();
170 return;
171 }
172
173 std::vector<RTLIL::IdString> del_list, add_list;
174
175 del_list.clear();
176 for (auto mod_name : selected_modules) {
177 if (design->modules_.count(mod_name) == 0)
178 del_list.push_back(mod_name);
179 selected_members.erase(mod_name);
180 }
181 for (auto mod_name : del_list)
182 selected_modules.erase(mod_name);
183
184 del_list.clear();
185 for (auto &it : selected_members)
186 if (design->modules_.count(it.first) == 0)
187 del_list.push_back(it.first);
188 for (auto mod_name : del_list)
189 selected_members.erase(mod_name);
190
191 for (auto &it : selected_members) {
192 del_list.clear();
193 for (auto memb_name : it.second)
194 if (design->modules_[it.first]->count_id(memb_name) == 0)
195 del_list.push_back(memb_name);
196 for (auto memb_name : del_list)
197 it.second.erase(memb_name);
198 }
199
200 del_list.clear();
201 add_list.clear();
202 for (auto &it : selected_members)
203 if (it.second.size() == 0)
204 del_list.push_back(it.first);
205 else if (it.second.size() == design->modules_[it.first]->wires_.size() + design->modules_[it.first]->memories.size() +
206 design->modules_[it.first]->cells_.size() + design->modules_[it.first]->processes.size())
207 add_list.push_back(it.first);
208 for (auto mod_name : del_list)
209 selected_members.erase(mod_name);
210 for (auto mod_name : add_list) {
211 selected_members.erase(mod_name);
212 selected_modules.insert(mod_name);
213 }
214
215 if (selected_modules.size() == design->modules_.size()) {
216 full_selection = true;
217 selected_modules.clear();
218 selected_members.clear();
219 }
220 }
221
222 RTLIL::Design::~Design()
223 {
224 for (auto it = modules_.begin(); it != modules_.end(); it++)
225 delete it->second;
226 }
227
228 RTLIL::ObjRange<RTLIL::Module*> RTLIL::Design::modules()
229 {
230 return RTLIL::ObjRange<RTLIL::Module*>(&modules_, &refcount_modules_);
231 }
232
233 RTLIL::Module *RTLIL::Design::module(RTLIL::IdString name)
234 {
235 return modules_.count(name) ? modules_.at(name) : NULL;
236 }
237
238 void RTLIL::Design::add(RTLIL::Module *module)
239 {
240 log_assert(modules_.count(module->name) == 0);
241 log_assert(refcount_modules_ == 0);
242 modules_[module->name] = module;
243 }
244
245 RTLIL::Module *RTLIL::Design::addModule(RTLIL::IdString name)
246 {
247 log_assert(modules_.count(name) == 0);
248 log_assert(refcount_modules_ == 0);
249 modules_[name] = new RTLIL::Module;
250 modules_[name]->name = name;
251 return modules_[name];
252 }
253
254 void RTLIL::Design::remove(RTLIL::Module *module)
255 {
256 log_assert(modules_.at(module->name) == module);
257 modules_.erase(module->name);
258 delete module;
259 }
260
261 void RTLIL::Design::check()
262 {
263 #ifndef NDEBUG
264 for (auto &it : modules_) {
265 log_assert(it.first == it.second->name);
266 log_assert(it.first.size() > 0 && (it.first[0] == '\\' || it.first[0] == '$'));
267 it.second->check();
268 }
269 #endif
270 }
271
272 void RTLIL::Design::optimize()
273 {
274 for (auto &it : modules_)
275 it.second->optimize();
276 for (auto &it : selection_stack)
277 it.optimize(this);
278 for (auto &it : selection_vars)
279 it.second.optimize(this);
280 }
281
282 bool RTLIL::Design::selected_module(RTLIL::IdString mod_name) const
283 {
284 if (!selected_active_module.empty() && mod_name != selected_active_module)
285 return false;
286 if (selection_stack.size() == 0)
287 return true;
288 return selection_stack.back().selected_module(mod_name);
289 }
290
291 bool RTLIL::Design::selected_whole_module(RTLIL::IdString mod_name) const
292 {
293 if (!selected_active_module.empty() && mod_name != selected_active_module)
294 return false;
295 if (selection_stack.size() == 0)
296 return true;
297 return selection_stack.back().selected_whole_module(mod_name);
298 }
299
300 bool RTLIL::Design::selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const
301 {
302 if (!selected_active_module.empty() && mod_name != selected_active_module)
303 return false;
304 if (selection_stack.size() == 0)
305 return true;
306 return selection_stack.back().selected_member(mod_name, memb_name);
307 }
308
309 bool RTLIL::Design::selected_module(RTLIL::Module *mod) const
310 {
311 return selected_module(mod->name);
312 }
313
314 bool RTLIL::Design::selected_whole_module(RTLIL::Module *mod) const
315 {
316 return selected_whole_module(mod->name);
317 }
318
319 RTLIL::Module::Module()
320 {
321 refcount_wires_ = 0;
322 refcount_cells_ = 0;
323 }
324
325 RTLIL::Module::~Module()
326 {
327 for (auto it = wires_.begin(); it != wires_.end(); it++)
328 delete it->second;
329 for (auto it = memories.begin(); it != memories.end(); it++)
330 delete it->second;
331 for (auto it = cells_.begin(); it != cells_.end(); it++)
332 delete it->second;
333 for (auto it = processes.begin(); it != processes.end(); it++)
334 delete it->second;
335 }
336
337 RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, std::map<RTLIL::IdString, RTLIL::Const>)
338 {
339 log_error("Module `%s' is used with parameters but is not parametric!\n", id2cstr(name));
340 }
341
342 size_t RTLIL::Module::count_id(RTLIL::IdString id)
343 {
344 return wires_.count(id) + memories.count(id) + cells_.count(id) + processes.count(id);
345 }
346
347 #ifndef NDEBUG
348 namespace {
349 struct InternalCellChecker
350 {
351 RTLIL::Module *module;
352 RTLIL::Cell *cell;
353 std::set<RTLIL::IdString> expected_params, expected_ports;
354
355 InternalCellChecker(RTLIL::Module *module, RTLIL::Cell *cell) : module(module), cell(cell) { }
356
357 void error(int linenr)
358 {
359 char *ptr;
360 size_t size;
361
362 FILE *f = open_memstream(&ptr, &size);
363 ILANG_BACKEND::dump_cell(f, " ", cell);
364 fputc(0, f);
365 fclose(f);
366
367 log_error("Found error in internal cell %s%s%s (%s) at %s:%d:\n%s",
368 module ? module->name.c_str() : "", module ? "." : "",
369 cell->name.c_str(), cell->type.c_str(), __FILE__, linenr, ptr);
370 }
371
372 int param(const char *name)
373 {
374 if (cell->parameters.count(name) == 0)
375 error(__LINE__);
376 expected_params.insert(name);
377 return cell->parameters.at(name).as_int();
378 }
379
380 int param_bool(const char *name)
381 {
382 int v = param(name);
383 if (cell->parameters.at(name).bits.size() > 32)
384 error(__LINE__);
385 if (v != 0 && v != 1)
386 error(__LINE__);
387 return v;
388 }
389
390 void param_bits(const char *name, int width)
391 {
392 param(name);
393 if (int(cell->parameters.at(name).bits.size()) != width)
394 error(__LINE__);
395 }
396
397 void port(const char *name, int width)
398 {
399 if (!cell->has(name))
400 error(__LINE__);
401 if (cell->get(name).size() != width)
402 error(__LINE__);
403 expected_ports.insert(name);
404 }
405
406 void check_expected(bool check_matched_sign = true)
407 {
408 for (auto &para : cell->parameters)
409 if (expected_params.count(para.first) == 0)
410 error(__LINE__);
411 for (auto &conn : cell->connections())
412 if (expected_ports.count(conn.first) == 0)
413 error(__LINE__);
414
415 if (expected_params.count("\\A_SIGNED") != 0 && expected_params.count("\\B_SIGNED") && check_matched_sign) {
416 bool a_is_signed = param("\\A_SIGNED") != 0;
417 bool b_is_signed = param("\\B_SIGNED") != 0;
418 if (a_is_signed != b_is_signed)
419 error(__LINE__);
420 }
421 }
422
423 void check_gate(const char *ports)
424 {
425 if (cell->parameters.size() != 0)
426 error(__LINE__);
427
428 for (const char *p = ports; *p; p++) {
429 char portname[3] = { '\\', *p, 0 };
430 if (!cell->has(portname))
431 error(__LINE__);
432 if (cell->get(portname).size() != 1)
433 error(__LINE__);
434 }
435
436 for (auto &conn : cell->connections()) {
437 if (conn.first.size() != 2 || conn.first.at(0) != '\\')
438 error(__LINE__);
439 if (strchr(ports, conn.first.at(1)) == NULL)
440 error(__LINE__);
441 }
442 }
443
444 void check()
445 {
446 if (cell->type[0] != '$' || cell->type.substr(0, 3) == "$__" || cell->type.substr(0, 8) == "$paramod" ||
447 cell->type.substr(0, 9) == "$verific$" || cell->type.substr(0, 7) == "$array:" || cell->type.substr(0, 8) == "$extern:")
448 return;
449
450 if (cell->type == "$not" || cell->type == "$pos" || cell->type == "$bu0" || cell->type == "$neg") {
451 param_bool("\\A_SIGNED");
452 port("\\A", param("\\A_WIDTH"));
453 port("\\Y", param("\\Y_WIDTH"));
454 check_expected();
455 return;
456 }
457
458 if (cell->type == "$and" || cell->type == "$or" || cell->type == "$xor" || cell->type == "$xnor") {
459 param_bool("\\A_SIGNED");
460 param_bool("\\B_SIGNED");
461 port("\\A", param("\\A_WIDTH"));
462 port("\\B", param("\\B_WIDTH"));
463 port("\\Y", param("\\Y_WIDTH"));
464 check_expected();
465 return;
466 }
467
468 if (cell->type == "$reduce_and" || cell->type == "$reduce_or" || cell->type == "$reduce_xor" ||
469 cell->type == "$reduce_xnor" || cell->type == "$reduce_bool") {
470 param_bool("\\A_SIGNED");
471 port("\\A", param("\\A_WIDTH"));
472 port("\\Y", param("\\Y_WIDTH"));
473 check_expected();
474 return;
475 }
476
477 if (cell->type == "$shl" || cell->type == "$shr" || cell->type == "$sshl" || cell->type == "$sshr" ||
478 cell->type == "$shift" || cell->type == "$shiftx") {
479 param_bool("\\A_SIGNED");
480 param_bool("\\B_SIGNED");
481 port("\\A", param("\\A_WIDTH"));
482 port("\\B", param("\\B_WIDTH"));
483 port("\\Y", param("\\Y_WIDTH"));
484 check_expected(false);
485 return;
486 }
487
488 if (cell->type == "$lt" || cell->type == "$le" || cell->type == "$eq" || cell->type == "$ne" ||
489 cell->type == "$eqx" || cell->type == "$nex" || cell->type == "$ge" || cell->type == "$gt") {
490 param_bool("\\A_SIGNED");
491 param_bool("\\B_SIGNED");
492 port("\\A", param("\\A_WIDTH"));
493 port("\\B", param("\\B_WIDTH"));
494 port("\\Y", param("\\Y_WIDTH"));
495 check_expected();
496 return;
497 }
498
499 if (cell->type == "$add" || cell->type == "$sub" || cell->type == "$mul" || cell->type == "$div" ||
500 cell->type == "$mod" || cell->type == "$pow") {
501 param_bool("\\A_SIGNED");
502 param_bool("\\B_SIGNED");
503 port("\\A", param("\\A_WIDTH"));
504 port("\\B", param("\\B_WIDTH"));
505 port("\\Y", param("\\Y_WIDTH"));
506 check_expected(cell->type != "$pow");
507 return;
508 }
509
510 if (cell->type == "$logic_not") {
511 param_bool("\\A_SIGNED");
512 port("\\A", param("\\A_WIDTH"));
513 port("\\Y", param("\\Y_WIDTH"));
514 check_expected();
515 return;
516 }
517
518 if (cell->type == "$logic_and" || cell->type == "$logic_or") {
519 param_bool("\\A_SIGNED");
520 param_bool("\\B_SIGNED");
521 port("\\A", param("\\A_WIDTH"));
522 port("\\B", param("\\B_WIDTH"));
523 port("\\Y", param("\\Y_WIDTH"));
524 check_expected(false);
525 return;
526 }
527
528 if (cell->type == "$slice") {
529 param("\\OFFSET");
530 port("\\A", param("\\A_WIDTH"));
531 port("\\Y", param("\\Y_WIDTH"));
532 if (param("\\OFFSET") + param("\\Y_WIDTH") > param("\\A_WIDTH"))
533 error(__LINE__);
534 check_expected();
535 return;
536 }
537
538 if (cell->type == "$concat") {
539 port("\\A", param("\\A_WIDTH"));
540 port("\\B", param("\\B_WIDTH"));
541 port("\\Y", param("\\A_WIDTH") + param("\\B_WIDTH"));
542 check_expected();
543 return;
544 }
545
546 if (cell->type == "$mux") {
547 port("\\A", param("\\WIDTH"));
548 port("\\B", param("\\WIDTH"));
549 port("\\S", 1);
550 port("\\Y", param("\\WIDTH"));
551 check_expected();
552 return;
553 }
554
555 if (cell->type == "$pmux" || cell->type == "$safe_pmux") {
556 port("\\A", param("\\WIDTH"));
557 port("\\B", param("\\WIDTH") * param("\\S_WIDTH"));
558 port("\\S", param("\\S_WIDTH"));
559 port("\\Y", param("\\WIDTH"));
560 check_expected();
561 return;
562 }
563
564 if (cell->type == "$lut") {
565 param("\\LUT");
566 port("\\I", param("\\WIDTH"));
567 port("\\O", 1);
568 check_expected();
569 return;
570 }
571
572 if (cell->type == "$sr") {
573 param_bool("\\SET_POLARITY");
574 param_bool("\\CLR_POLARITY");
575 port("\\SET", param("\\WIDTH"));
576 port("\\CLR", param("\\WIDTH"));
577 port("\\Q", param("\\WIDTH"));
578 check_expected();
579 return;
580 }
581
582 if (cell->type == "$dff") {
583 param_bool("\\CLK_POLARITY");
584 port("\\CLK", 1);
585 port("\\D", param("\\WIDTH"));
586 port("\\Q", param("\\WIDTH"));
587 check_expected();
588 return;
589 }
590
591 if (cell->type == "$dffsr") {
592 param_bool("\\CLK_POLARITY");
593 param_bool("\\SET_POLARITY");
594 param_bool("\\CLR_POLARITY");
595 port("\\CLK", 1);
596 port("\\SET", param("\\WIDTH"));
597 port("\\CLR", param("\\WIDTH"));
598 port("\\D", param("\\WIDTH"));
599 port("\\Q", param("\\WIDTH"));
600 check_expected();
601 return;
602 }
603
604 if (cell->type == "$adff") {
605 param_bool("\\CLK_POLARITY");
606 param_bool("\\ARST_POLARITY");
607 param_bits("\\ARST_VALUE", param("\\WIDTH"));
608 port("\\CLK", 1);
609 port("\\ARST", 1);
610 port("\\D", param("\\WIDTH"));
611 port("\\Q", param("\\WIDTH"));
612 check_expected();
613 return;
614 }
615
616 if (cell->type == "$dlatch") {
617 param_bool("\\EN_POLARITY");
618 port("\\EN", 1);
619 port("\\D", param("\\WIDTH"));
620 port("\\Q", param("\\WIDTH"));
621 check_expected();
622 return;
623 }
624
625 if (cell->type == "$dlatchsr") {
626 param_bool("\\EN_POLARITY");
627 param_bool("\\SET_POLARITY");
628 param_bool("\\CLR_POLARITY");
629 port("\\EN", 1);
630 port("\\SET", param("\\WIDTH"));
631 port("\\CLR", param("\\WIDTH"));
632 port("\\D", param("\\WIDTH"));
633 port("\\Q", param("\\WIDTH"));
634 check_expected();
635 return;
636 }
637
638 if (cell->type == "$fsm") {
639 param("\\NAME");
640 param_bool("\\CLK_POLARITY");
641 param_bool("\\ARST_POLARITY");
642 param("\\STATE_BITS");
643 param("\\STATE_NUM");
644 param("\\STATE_NUM_LOG2");
645 param("\\STATE_RST");
646 param_bits("\\STATE_TABLE", param("\\STATE_BITS") * param("\\STATE_NUM"));
647 param("\\TRANS_NUM");
648 param_bits("\\TRANS_TABLE", param("\\TRANS_NUM") * (2*param("\\STATE_NUM_LOG2") + param("\\CTRL_IN_WIDTH") + param("\\CTRL_OUT_WIDTH")));
649 port("\\CLK", 1);
650 port("\\ARST", 1);
651 port("\\CTRL_IN", param("\\CTRL_IN_WIDTH"));
652 port("\\CTRL_OUT", param("\\CTRL_OUT_WIDTH"));
653 check_expected();
654 return;
655 }
656
657 if (cell->type == "$memrd") {
658 param("\\MEMID");
659 param_bool("\\CLK_ENABLE");
660 param_bool("\\CLK_POLARITY");
661 param_bool("\\TRANSPARENT");
662 port("\\CLK", 1);
663 port("\\ADDR", param("\\ABITS"));
664 port("\\DATA", param("\\WIDTH"));
665 check_expected();
666 return;
667 }
668
669 if (cell->type == "$memwr") {
670 param("\\MEMID");
671 param_bool("\\CLK_ENABLE");
672 param_bool("\\CLK_POLARITY");
673 param("\\PRIORITY");
674 port("\\CLK", 1);
675 port("\\EN", param("\\WIDTH"));
676 port("\\ADDR", param("\\ABITS"));
677 port("\\DATA", param("\\WIDTH"));
678 check_expected();
679 return;
680 }
681
682 if (cell->type == "$mem") {
683 param("\\MEMID");
684 param("\\SIZE");
685 param("\\OFFSET");
686 param_bits("\\RD_CLK_ENABLE", param("\\RD_PORTS"));
687 param_bits("\\RD_CLK_POLARITY", param("\\RD_PORTS"));
688 param_bits("\\RD_TRANSPARENT", param("\\RD_PORTS"));
689 param_bits("\\WR_CLK_ENABLE", param("\\WR_PORTS"));
690 param_bits("\\WR_CLK_POLARITY", param("\\WR_PORTS"));
691 port("\\RD_CLK", param("\\RD_PORTS"));
692 port("\\RD_ADDR", param("\\RD_PORTS") * param("\\ABITS"));
693 port("\\RD_DATA", param("\\RD_PORTS") * param("\\WIDTH"));
694 port("\\WR_CLK", param("\\WR_PORTS"));
695 port("\\WR_EN", param("\\WR_PORTS") * param("\\WIDTH"));
696 port("\\WR_ADDR", param("\\WR_PORTS") * param("\\ABITS"));
697 port("\\WR_DATA", param("\\WR_PORTS") * param("\\WIDTH"));
698 check_expected();
699 return;
700 }
701
702 if (cell->type == "$assert") {
703 port("\\A", 1);
704 port("\\EN", 1);
705 check_expected();
706 return;
707 }
708
709 if (cell->type == "$_INV_") { check_gate("AY"); return; }
710 if (cell->type == "$_AND_") { check_gate("ABY"); return; }
711 if (cell->type == "$_OR_") { check_gate("ABY"); return; }
712 if (cell->type == "$_XOR_") { check_gate("ABY"); return; }
713 if (cell->type == "$_MUX_") { check_gate("ABSY"); return; }
714
715 if (cell->type == "$_SR_NN_") { check_gate("SRQ"); return; }
716 if (cell->type == "$_SR_NP_") { check_gate("SRQ"); return; }
717 if (cell->type == "$_SR_PN_") { check_gate("SRQ"); return; }
718 if (cell->type == "$_SR_PP_") { check_gate("SRQ"); return; }
719
720 if (cell->type == "$_DFF_N_") { check_gate("DQC"); return; }
721 if (cell->type == "$_DFF_P_") { check_gate("DQC"); return; }
722
723 if (cell->type == "$_DFF_NN0_") { check_gate("DQCR"); return; }
724 if (cell->type == "$_DFF_NN1_") { check_gate("DQCR"); return; }
725 if (cell->type == "$_DFF_NP0_") { check_gate("DQCR"); return; }
726 if (cell->type == "$_DFF_NP1_") { check_gate("DQCR"); return; }
727 if (cell->type == "$_DFF_PN0_") { check_gate("DQCR"); return; }
728 if (cell->type == "$_DFF_PN1_") { check_gate("DQCR"); return; }
729 if (cell->type == "$_DFF_PP0_") { check_gate("DQCR"); return; }
730 if (cell->type == "$_DFF_PP1_") { check_gate("DQCR"); return; }
731
732 if (cell->type == "$_DFFSR_NNN_") { check_gate("CSRDQ"); return; }
733 if (cell->type == "$_DFFSR_NNP_") { check_gate("CSRDQ"); return; }
734 if (cell->type == "$_DFFSR_NPN_") { check_gate("CSRDQ"); return; }
735 if (cell->type == "$_DFFSR_NPP_") { check_gate("CSRDQ"); return; }
736 if (cell->type == "$_DFFSR_PNN_") { check_gate("CSRDQ"); return; }
737 if (cell->type == "$_DFFSR_PNP_") { check_gate("CSRDQ"); return; }
738 if (cell->type == "$_DFFSR_PPN_") { check_gate("CSRDQ"); return; }
739 if (cell->type == "$_DFFSR_PPP_") { check_gate("CSRDQ"); return; }
740
741 if (cell->type == "$_DLATCH_N_") { check_gate("EDQ"); return; }
742 if (cell->type == "$_DLATCH_P_") { check_gate("EDQ"); return; }
743
744 if (cell->type == "$_DLATCHSR_NNN_") { check_gate("ESRDQ"); return; }
745 if (cell->type == "$_DLATCHSR_NNP_") { check_gate("ESRDQ"); return; }
746 if (cell->type == "$_DLATCHSR_NPN_") { check_gate("ESRDQ"); return; }
747 if (cell->type == "$_DLATCHSR_NPP_") { check_gate("ESRDQ"); return; }
748 if (cell->type == "$_DLATCHSR_PNN_") { check_gate("ESRDQ"); return; }
749 if (cell->type == "$_DLATCHSR_PNP_") { check_gate("ESRDQ"); return; }
750 if (cell->type == "$_DLATCHSR_PPN_") { check_gate("ESRDQ"); return; }
751 if (cell->type == "$_DLATCHSR_PPP_") { check_gate("ESRDQ"); return; }
752
753 error(__LINE__);
754 }
755 };
756 }
757 #endif
758
759 void RTLIL::Module::check()
760 {
761 #ifndef NDEBUG
762 for (auto &it : wires_) {
763 log_assert(it.first == it.second->name);
764 log_assert(it.first.size() > 0 && (it.first[0] == '\\' || it.first[0] == '$'));
765 log_assert(it.second->width >= 0);
766 log_assert(it.second->port_id >= 0);
767 for (auto &it2 : it.second->attributes) {
768 log_assert(it2.first.size() > 0 && (it2.first[0] == '\\' || it2.first[0] == '$'));
769 }
770 }
771
772 for (auto &it : memories) {
773 log_assert(it.first == it.second->name);
774 log_assert(it.first.size() > 0 && (it.first[0] == '\\' || it.first[0] == '$'));
775 log_assert(it.second->width >= 0);
776 log_assert(it.second->size >= 0);
777 for (auto &it2 : it.second->attributes) {
778 log_assert(it2.first.size() > 0 && (it2.first[0] == '\\' || it2.first[0] == '$'));
779 }
780 }
781
782 for (auto &it : cells_) {
783 log_assert(it.first == it.second->name);
784 log_assert(it.first.size() > 0 && (it.first[0] == '\\' || it.first[0] == '$'));
785 log_assert(it.second->type.size() > 0 && (it.second->type[0] == '\\' || it.second->type[0] == '$'));
786 for (auto &it2 : it.second->connections()) {
787 log_assert(it2.first.size() > 0 && (it2.first[0] == '\\' || it2.first[0] == '$'));
788 it2.second.check();
789 }
790 for (auto &it2 : it.second->attributes) {
791 log_assert(it2.first.size() > 0 && (it2.first[0] == '\\' || it2.first[0] == '$'));
792 }
793 for (auto &it2 : it.second->parameters) {
794 log_assert(it2.first.size() > 0 && (it2.first[0] == '\\' || it2.first[0] == '$'));
795 }
796 InternalCellChecker checker(this, it.second);
797 checker.check();
798 }
799
800 for (auto &it : processes) {
801 log_assert(it.first == it.second->name);
802 log_assert(it.first.size() > 0 && (it.first[0] == '\\' || it.first[0] == '$'));
803 // FIXME: More checks here..
804 }
805
806 for (auto &it : connections_) {
807 log_assert(it.first.size() == it.second.size());
808 it.first.check();
809 it.second.check();
810 }
811
812 for (auto &it : attributes) {
813 log_assert(it.first.size() > 0 && (it.first[0] == '\\' || it.first[0] == '$'));
814 }
815 #endif
816 }
817
818 void RTLIL::Module::optimize()
819 {
820 }
821
822 void RTLIL::Module::cloneInto(RTLIL::Module *new_mod) const
823 {
824 log_assert(new_mod->refcount_wires_ == 0);
825 log_assert(new_mod->refcount_cells_ == 0);
826
827 new_mod->connections_ = connections_;
828 new_mod->attributes = attributes;
829
830 for (auto &it : wires_)
831 new_mod->addWire(it.first, it.second);
832
833 for (auto &it : memories)
834 new_mod->memories[it.first] = new RTLIL::Memory(*it.second);
835
836 for (auto &it : cells_)
837 new_mod->addCell(it.first, it.second);
838
839 for (auto &it : processes)
840 new_mod->processes[it.first] = it.second->clone();
841
842 struct RewriteSigSpecWorker
843 {
844 RTLIL::Module *mod;
845 void operator()(RTLIL::SigSpec &sig)
846 {
847 std::vector<RTLIL::SigChunk> chunks = sig.chunks();
848 for (auto &c : chunks)
849 if (c.wire != NULL)
850 c.wire = mod->wires_.at(c.wire->name);
851 sig = chunks;
852 }
853 };
854
855 RewriteSigSpecWorker rewriteSigSpecWorker;
856 rewriteSigSpecWorker.mod = new_mod;
857 new_mod->rewrite_sigspecs(rewriteSigSpecWorker);
858 }
859
860 RTLIL::Module *RTLIL::Module::clone() const
861 {
862 RTLIL::Module *new_mod = new RTLIL::Module;
863 new_mod->name = name;
864 cloneInto(new_mod);
865 return new_mod;
866 }
867
868 void RTLIL::Module::add(RTLIL::Wire *wire)
869 {
870 log_assert(!wire->name.empty());
871 log_assert(count_id(wire->name) == 0);
872 log_assert(refcount_wires_ == 0);
873 wires_[wire->name] = wire;
874 }
875
876 void RTLIL::Module::add(RTLIL::Cell *cell)
877 {
878 log_assert(!cell->name.empty());
879 log_assert(count_id(cell->name) == 0);
880 log_assert(refcount_cells_ == 0);
881 cells_[cell->name] = cell;
882 }
883
884 namespace {
885 struct DeleteWireWorker
886 {
887 RTLIL::Module *module;
888 const std::set<RTLIL::Wire*> *wires_p;
889
890 void operator()(RTLIL::SigSpec &sig) {
891 std::vector<RTLIL::SigChunk> chunks = sig;
892 for (auto &c : chunks)
893 if (c.wire != NULL && wires_p->count(c.wire)) {
894 c.wire = module->addWire(NEW_ID, c.width);
895 c.offset = 0;
896 }
897 sig = chunks;
898 }
899 };
900 }
901
902 #if 0
903 void RTLIL::Module::remove(RTLIL::Wire *wire)
904 {
905 std::set<RTLIL::Wire*> wires_;
906 wires_.insert(wire);
907 remove(wires_);
908 }
909 #endif
910
911 void RTLIL::Module::remove(const std::set<RTLIL::Wire*> &wires)
912 {
913 log_assert(refcount_wires_ == 0);
914
915 DeleteWireWorker delete_wire_worker;
916 delete_wire_worker.module = this;
917 delete_wire_worker.wires_p = &wires;
918 rewrite_sigspecs(delete_wire_worker);
919
920 for (auto &it : wires) {
921 log_assert(wires_.count(it->name) != 0);
922 wires_.erase(it->name);
923 delete it;
924 }
925 }
926
927 void RTLIL::Module::remove(RTLIL::Cell *cell)
928 {
929 log_assert(cells_.count(cell->name) != 0);
930 log_assert(refcount_cells_ == 0);
931 cells_.erase(cell->name);
932 delete cell;
933 }
934
935 void RTLIL::Module::rename(RTLIL::Wire *wire, RTLIL::IdString new_name)
936 {
937 log_assert(wires_[wire->name] == wire);
938 log_assert(refcount_wires_ == 0);
939 wires_.erase(wire->name);
940 wire->name = new_name;
941 add(wire);
942 }
943
944 void RTLIL::Module::rename(RTLIL::Cell *cell, RTLIL::IdString new_name)
945 {
946 log_assert(cells_[cell->name] == cell);
947 log_assert(refcount_wires_ == 0);
948 cells_.erase(cell->name);
949 cell->name = new_name;
950 add(cell);
951 }
952
953 void RTLIL::Module::rename(RTLIL::IdString old_name, RTLIL::IdString new_name)
954 {
955 log_assert(count_id(old_name) != 0);
956 if (wires_.count(old_name))
957 rename(wires_.at(old_name), new_name);
958 else if (cells_.count(old_name))
959 rename(cells_.at(old_name), new_name);
960 else
961 log_abort();
962 }
963
964 static bool fixup_ports_compare(const RTLIL::Wire *a, const RTLIL::Wire *b)
965 {
966 if (a->port_id && !b->port_id)
967 return true;
968 if (!a->port_id && b->port_id)
969 return false;
970
971 if (a->port_id == b->port_id)
972 return a->name < b->name;
973 return a->port_id < b->port_id;
974 }
975
976 void RTLIL::Module::connect(const RTLIL::SigSig &conn)
977 {
978 connections_.push_back(conn);
979 }
980
981 void RTLIL::Module::connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs)
982 {
983 connections_.push_back(RTLIL::SigSig(lhs, rhs));
984 }
985
986 const std::vector<RTLIL::SigSig> &RTLIL::Module::connections() const
987 {
988 return connections_;
989 }
990
991 void RTLIL::Module::fixup_ports()
992 {
993 std::vector<RTLIL::Wire*> all_ports;
994
995 for (auto &w : wires_)
996 if (w.second->port_input || w.second->port_output)
997 all_ports.push_back(w.second);
998 else
999 w.second->port_id = 0;
1000
1001 std::sort(all_ports.begin(), all_ports.end(), fixup_ports_compare);
1002 for (size_t i = 0; i < all_ports.size(); i++)
1003 all_ports[i]->port_id = i+1;
1004 }
1005
1006 RTLIL::Wire *RTLIL::Module::addWire(RTLIL::IdString name, int width)
1007 {
1008 RTLIL::Wire *wire = new RTLIL::Wire;
1009 wire->name = name;
1010 wire->width = width;
1011 add(wire);
1012 return wire;
1013 }
1014
1015 RTLIL::Wire *RTLIL::Module::addWire(RTLIL::IdString name, const RTLIL::Wire *other)
1016 {
1017 RTLIL::Wire *wire = addWire(name);
1018 wire->width = other->width;
1019 wire->start_offset = other->start_offset;
1020 wire->port_id = other->port_id;
1021 wire->port_input = other->port_input;
1022 wire->port_output = other->port_output;
1023 wire->upto = other->upto;
1024 wire->attributes = other->attributes;
1025 return wire;
1026 }
1027
1028 RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, RTLIL::IdString type)
1029 {
1030 RTLIL::Cell *cell = new RTLIL::Cell;
1031 cell->name = name;
1032 cell->type = type;
1033 add(cell);
1034 return cell;
1035 }
1036
1037 RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, const RTLIL::Cell *other)
1038 {
1039 RTLIL::Cell *cell = addCell(name, other->type);
1040 cell->connections_ = other->connections_;
1041 cell->parameters = other->parameters;
1042 cell->attributes = other->attributes;
1043 return cell;
1044 }
1045
1046 #define DEF_METHOD(_func, _y_size, _type) \
1047 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed) { \
1048 RTLIL::Cell *cell = new RTLIL::Cell; \
1049 cell->name = name; \
1050 cell->type = _type; \
1051 cell->parameters["\\A_SIGNED"] = is_signed; \
1052 cell->parameters["\\A_WIDTH"] = sig_a.size(); \
1053 cell->parameters["\\Y_WIDTH"] = sig_y.size(); \
1054 cell->set("\\A", sig_a); \
1055 cell->set("\\Y", sig_y); \
1056 add(cell); \
1057 return cell; \
1058 } \
1059 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed) { \
1060 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
1061 add ## _func(name, sig_a, sig_y, is_signed); \
1062 return sig_y; \
1063 }
1064 DEF_METHOD(Not, sig_a.size(), "$not")
1065 DEF_METHOD(Pos, sig_a.size(), "$pos")
1066 DEF_METHOD(Bu0, sig_a.size(), "$bu0")
1067 DEF_METHOD(Neg, sig_a.size(), "$neg")
1068 DEF_METHOD(ReduceAnd, 1, "$reduce_and")
1069 DEF_METHOD(ReduceOr, 1, "$reduce_or")
1070 DEF_METHOD(ReduceXor, 1, "$reduce_xor")
1071 DEF_METHOD(ReduceXnor, 1, "$reduce_xnor")
1072 DEF_METHOD(ReduceBool, 1, "$reduce_bool")
1073 DEF_METHOD(LogicNot, 1, "$logic_not")
1074 #undef DEF_METHOD
1075
1076 #define DEF_METHOD(_func, _y_size, _type) \
1077 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed) { \
1078 RTLIL::Cell *cell = new RTLIL::Cell; \
1079 cell->name = name; \
1080 cell->type = _type; \
1081 cell->parameters["\\A_SIGNED"] = is_signed; \
1082 cell->parameters["\\B_SIGNED"] = is_signed; \
1083 cell->parameters["\\A_WIDTH"] = sig_a.size(); \
1084 cell->parameters["\\B_WIDTH"] = sig_b.size(); \
1085 cell->parameters["\\Y_WIDTH"] = sig_y.size(); \
1086 cell->set("\\A", sig_a); \
1087 cell->set("\\B", sig_b); \
1088 cell->set("\\Y", sig_y); \
1089 add(cell); \
1090 return cell; \
1091 } \
1092 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed) { \
1093 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
1094 add ## _func(name, sig_a, sig_b, sig_y, is_signed); \
1095 return sig_y; \
1096 }
1097 DEF_METHOD(And, std::max(sig_a.size(), sig_b.size()), "$and")
1098 DEF_METHOD(Or, std::max(sig_a.size(), sig_b.size()), "$or")
1099 DEF_METHOD(Xor, std::max(sig_a.size(), sig_b.size()), "$xor")
1100 DEF_METHOD(Xnor, std::max(sig_a.size(), sig_b.size()), "$xnor")
1101 DEF_METHOD(Shl, sig_a.size(), "$shl")
1102 DEF_METHOD(Shr, sig_a.size(), "$shr")
1103 DEF_METHOD(Sshl, sig_a.size(), "$sshl")
1104 DEF_METHOD(Sshr, sig_a.size(), "$sshr")
1105 DEF_METHOD(Shift, sig_a.size(), "$shift")
1106 DEF_METHOD(Shiftx, sig_a.size(), "$shiftx")
1107 DEF_METHOD(Lt, 1, "$lt")
1108 DEF_METHOD(Le, 1, "$le")
1109 DEF_METHOD(Eq, 1, "$eq")
1110 DEF_METHOD(Ne, 1, "$ne")
1111 DEF_METHOD(Eqx, 1, "$eqx")
1112 DEF_METHOD(Nex, 1, "$nex")
1113 DEF_METHOD(Ge, 1, "$ge")
1114 DEF_METHOD(Gt, 1, "$gt")
1115 DEF_METHOD(Add, std::max(sig_a.size(), sig_b.size()), "$add")
1116 DEF_METHOD(Sub, std::max(sig_a.size(), sig_b.size()), "$sub")
1117 DEF_METHOD(Mul, std::max(sig_a.size(), sig_b.size()), "$mul")
1118 DEF_METHOD(Div, std::max(sig_a.size(), sig_b.size()), "$div")
1119 DEF_METHOD(Mod, std::max(sig_a.size(), sig_b.size()), "$mod")
1120 DEF_METHOD(LogicAnd, 1, "$logic_and")
1121 DEF_METHOD(LogicOr, 1, "$logic_or")
1122 #undef DEF_METHOD
1123
1124 #define DEF_METHOD(_func, _type, _pmux) \
1125 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, RTLIL::SigSpec sig_y) { \
1126 RTLIL::Cell *cell = new RTLIL::Cell; \
1127 cell->name = name; \
1128 cell->type = _type; \
1129 cell->parameters["\\WIDTH"] = sig_a.size(); \
1130 cell->parameters["\\WIDTH"] = sig_b.size(); \
1131 if (_pmux) cell->parameters["\\S_WIDTH"] = sig_s.size(); \
1132 cell->set("\\A", sig_a); \
1133 cell->set("\\B", sig_b); \
1134 cell->set("\\S", sig_s); \
1135 cell->set("\\Y", sig_y); \
1136 add(cell); \
1137 return cell; \
1138 } \
1139 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s) { \
1140 RTLIL::SigSpec sig_y = addWire(NEW_ID, sig_a.size()); \
1141 add ## _func(name, sig_a, sig_b, sig_s, sig_y); \
1142 return sig_y; \
1143 }
1144 DEF_METHOD(Mux, "$mux", 0)
1145 DEF_METHOD(Pmux, "$pmux", 1)
1146 DEF_METHOD(SafePmux, "$safe_pmux", 1)
1147 #undef DEF_METHOD
1148
1149 #define DEF_METHOD_2(_func, _type, _P1, _P2) \
1150 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig1, RTLIL::SigSpec sig2) { \
1151 RTLIL::Cell *cell = new RTLIL::Cell; \
1152 cell->name = name; \
1153 cell->type = _type; \
1154 cell->set("\\" #_P1, sig1); \
1155 cell->set("\\" #_P2, sig2); \
1156 add(cell); \
1157 return cell; \
1158 } \
1159 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig1) { \
1160 RTLIL::SigSpec sig2 = addWire(NEW_ID); \
1161 add ## _func(name, sig1, sig2); \
1162 return sig2; \
1163 }
1164 #define DEF_METHOD_3(_func, _type, _P1, _P2, _P3) \
1165 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig1, RTLIL::SigSpec sig2, RTLIL::SigSpec sig3) { \
1166 RTLIL::Cell *cell = new RTLIL::Cell; \
1167 cell->name = name; \
1168 cell->type = _type; \
1169 cell->set("\\" #_P1, sig1); \
1170 cell->set("\\" #_P2, sig2); \
1171 cell->set("\\" #_P3, sig3); \
1172 add(cell); \
1173 return cell; \
1174 } \
1175 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig1, RTLIL::SigSpec sig2) { \
1176 RTLIL::SigSpec sig3 = addWire(NEW_ID); \
1177 add ## _func(name, sig1, sig2, sig3); \
1178 return sig3; \
1179 }
1180 #define DEF_METHOD_4(_func, _type, _P1, _P2, _P3, _P4) \
1181 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig1, RTLIL::SigSpec sig2, RTLIL::SigSpec sig3, RTLIL::SigSpec sig4) { \
1182 RTLIL::Cell *cell = new RTLIL::Cell; \
1183 cell->name = name; \
1184 cell->type = _type; \
1185 cell->set("\\" #_P1, sig1); \
1186 cell->set("\\" #_P2, sig2); \
1187 cell->set("\\" #_P3, sig3); \
1188 cell->set("\\" #_P4, sig4); \
1189 add(cell); \
1190 return cell; \
1191 } \
1192 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig1, RTLIL::SigSpec sig2, RTLIL::SigSpec sig3) { \
1193 RTLIL::SigSpec sig4 = addWire(NEW_ID); \
1194 add ## _func(name, sig1, sig2, sig3, sig4); \
1195 return sig4; \
1196 }
1197 DEF_METHOD_2(InvGate, "$_INV_", A, Y)
1198 DEF_METHOD_3(AndGate, "$_AND_", A, B, Y)
1199 DEF_METHOD_3(OrGate, "$_OR_", A, B, Y)
1200 DEF_METHOD_3(XorGate, "$_XOR_", A, B, Y)
1201 DEF_METHOD_4(MuxGate, "$_MUX_", A, B, S, Y)
1202 #undef DEF_METHOD_2
1203 #undef DEF_METHOD_3
1204 #undef DEF_METHOD_4
1205
1206 RTLIL::Cell* RTLIL::Module::addPow(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool a_signed, bool b_signed)
1207 {
1208 RTLIL::Cell *cell = new RTLIL::Cell;
1209 cell->name = name;
1210 cell->type = "$pow";
1211 cell->parameters["\\A_SIGNED"] = a_signed;
1212 cell->parameters["\\B_SIGNED"] = b_signed;
1213 cell->parameters["\\A_WIDTH"] = sig_a.size();
1214 cell->parameters["\\B_WIDTH"] = sig_b.size();
1215 cell->parameters["\\Y_WIDTH"] = sig_y.size();
1216 cell->set("\\A", sig_a);
1217 cell->set("\\B", sig_b);
1218 cell->set("\\Y", sig_y);
1219 add(cell);
1220 return cell;
1221 }
1222
1223 RTLIL::Cell* RTLIL::Module::addSlice(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, RTLIL::Const offset)
1224 {
1225 RTLIL::Cell *cell = new RTLIL::Cell;
1226 cell->name = name;
1227 cell->type = "$slice";
1228 cell->parameters["\\A_WIDTH"] = sig_a.size();
1229 cell->parameters["\\Y_WIDTH"] = sig_y.size();
1230 cell->parameters["\\OFFSET"] = offset;
1231 cell->set("\\A", sig_a);
1232 cell->set("\\Y", sig_y);
1233 add(cell);
1234 return cell;
1235 }
1236
1237 RTLIL::Cell* RTLIL::Module::addConcat(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y)
1238 {
1239 RTLIL::Cell *cell = new RTLIL::Cell;
1240 cell->name = name;
1241 cell->type = "$concat";
1242 cell->parameters["\\A_WIDTH"] = sig_a.size();
1243 cell->parameters["\\B_WIDTH"] = sig_b.size();
1244 cell->set("\\A", sig_a);
1245 cell->set("\\B", sig_b);
1246 cell->set("\\Y", sig_y);
1247 add(cell);
1248 return cell;
1249 }
1250
1251 RTLIL::Cell* RTLIL::Module::addLut(RTLIL::IdString name, RTLIL::SigSpec sig_i, RTLIL::SigSpec sig_o, RTLIL::Const lut)
1252 {
1253 RTLIL::Cell *cell = new RTLIL::Cell;
1254 cell->name = name;
1255 cell->type = "$lut";
1256 cell->parameters["\\LUT"] = lut;
1257 cell->parameters["\\WIDTH"] = sig_i.size();
1258 cell->set("\\I", sig_i);
1259 cell->set("\\O", sig_o);
1260 add(cell);
1261 return cell;
1262 }
1263
1264 RTLIL::Cell* RTLIL::Module::addAssert(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en)
1265 {
1266 RTLIL::Cell *cell = new RTLIL::Cell;
1267 cell->name = name;
1268 cell->type = "$assert";
1269 cell->set("\\A", sig_a);
1270 cell->set("\\EN", sig_en);
1271 add(cell);
1272 return cell;
1273 }
1274
1275 RTLIL::Cell* RTLIL::Module::addSr(RTLIL::IdString name, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr, RTLIL::SigSpec sig_q, bool set_polarity, bool clr_polarity)
1276 {
1277 RTLIL::Cell *cell = new RTLIL::Cell;
1278 cell->name = name;
1279 cell->type = "$sr";
1280 cell->parameters["\\SET_POLARITY"] = set_polarity;
1281 cell->parameters["\\CLR_POLARITY"] = clr_polarity;
1282 cell->parameters["\\WIDTH"] = sig_q.size();
1283 cell->set("\\SET", sig_set);
1284 cell->set("\\CLR", sig_clr);
1285 cell->set("\\Q", sig_q);
1286 add(cell);
1287 return cell;
1288 }
1289
1290 RTLIL::Cell* RTLIL::Module::addDff(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity)
1291 {
1292 RTLIL::Cell *cell = new RTLIL::Cell;
1293 cell->name = name;
1294 cell->type = "$dff";
1295 cell->parameters["\\CLK_POLARITY"] = clk_polarity;
1296 cell->parameters["\\WIDTH"] = sig_q.size();
1297 cell->set("\\CLK", sig_clk);
1298 cell->set("\\D", sig_d);
1299 cell->set("\\Q", sig_q);
1300 add(cell);
1301 return cell;
1302 }
1303
1304 RTLIL::Cell* RTLIL::Module::addDffsr(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
1305 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity)
1306 {
1307 RTLIL::Cell *cell = new RTLIL::Cell;
1308 cell->name = name;
1309 cell->type = "$dffsr";
1310 cell->parameters["\\CLK_POLARITY"] = clk_polarity;
1311 cell->parameters["\\SET_POLARITY"] = set_polarity;
1312 cell->parameters["\\CLR_POLARITY"] = clr_polarity;
1313 cell->parameters["\\WIDTH"] = sig_q.size();
1314 cell->set("\\CLK", sig_clk);
1315 cell->set("\\SET", sig_set);
1316 cell->set("\\CLR", sig_clr);
1317 cell->set("\\D", sig_d);
1318 cell->set("\\Q", sig_q);
1319 add(cell);
1320 return cell;
1321 }
1322
1323 RTLIL::Cell* RTLIL::Module::addAdff(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_arst, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q,
1324 RTLIL::Const arst_value, bool clk_polarity, bool arst_polarity)
1325 {
1326 RTLIL::Cell *cell = new RTLIL::Cell;
1327 cell->name = name;
1328 cell->type = "$adff";
1329 cell->parameters["\\CLK_POLARITY"] = clk_polarity;
1330 cell->parameters["\\ARST_POLARITY"] = arst_polarity;
1331 cell->parameters["\\ARST_VALUE"] = arst_value;
1332 cell->parameters["\\WIDTH"] = sig_q.size();
1333 cell->set("\\CLK", sig_clk);
1334 cell->set("\\ARST", sig_arst);
1335 cell->set("\\D", sig_d);
1336 cell->set("\\Q", sig_q);
1337 add(cell);
1338 return cell;
1339 }
1340
1341 RTLIL::Cell* RTLIL::Module::addDlatch(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity)
1342 {
1343 RTLIL::Cell *cell = new RTLIL::Cell;
1344 cell->name = name;
1345 cell->type = "$dlatch";
1346 cell->parameters["\\EN_POLARITY"] = en_polarity;
1347 cell->parameters["\\WIDTH"] = sig_q.size();
1348 cell->set("\\EN", sig_en);
1349 cell->set("\\D", sig_d);
1350 cell->set("\\Q", sig_q);
1351 add(cell);
1352 return cell;
1353 }
1354
1355 RTLIL::Cell* RTLIL::Module::addDlatchsr(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
1356 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity, bool set_polarity, bool clr_polarity)
1357 {
1358 RTLIL::Cell *cell = new RTLIL::Cell;
1359 cell->name = name;
1360 cell->type = "$dlatchsr";
1361 cell->parameters["\\EN_POLARITY"] = en_polarity;
1362 cell->parameters["\\SET_POLARITY"] = set_polarity;
1363 cell->parameters["\\CLR_POLARITY"] = clr_polarity;
1364 cell->parameters["\\WIDTH"] = sig_q.size();
1365 cell->set("\\EN", sig_en);
1366 cell->set("\\SET", sig_set);
1367 cell->set("\\CLR", sig_clr);
1368 cell->set("\\D", sig_d);
1369 cell->set("\\Q", sig_q);
1370 add(cell);
1371 return cell;
1372 }
1373
1374 RTLIL::Cell* RTLIL::Module::addDffGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity)
1375 {
1376 RTLIL::Cell *cell = new RTLIL::Cell;
1377 cell->name = name;
1378 cell->type = stringf("$_DFF_%c_", clk_polarity ? 'P' : 'N');
1379 cell->set("\\C", sig_clk);
1380 cell->set("\\D", sig_d);
1381 cell->set("\\Q", sig_q);
1382 add(cell);
1383 return cell;
1384 }
1385
1386 RTLIL::Cell* RTLIL::Module::addDffsrGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
1387 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity)
1388 {
1389 RTLIL::Cell *cell = new RTLIL::Cell;
1390 cell->name = name;
1391 cell->type = stringf("$_DFFSR_%c%c%c_", clk_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N');
1392 cell->set("\\C", sig_clk);
1393 cell->set("\\S", sig_set);
1394 cell->set("\\R", sig_clr);
1395 cell->set("\\D", sig_d);
1396 cell->set("\\Q", sig_q);
1397 add(cell);
1398 return cell;
1399 }
1400
1401 RTLIL::Cell* RTLIL::Module::addAdffGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_arst, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q,
1402 bool arst_value, bool clk_polarity, bool arst_polarity)
1403 {
1404 RTLIL::Cell *cell = new RTLIL::Cell;
1405 cell->name = name;
1406 cell->type = stringf("$_DFF_%c%c%c_", clk_polarity ? 'P' : 'N', arst_polarity ? 'P' : 'N', arst_value ? '1' : '0');
1407 cell->set("\\C", sig_clk);
1408 cell->set("\\R", sig_arst);
1409 cell->set("\\D", sig_d);
1410 cell->set("\\Q", sig_q);
1411 add(cell);
1412 return cell;
1413 }
1414
1415 RTLIL::Cell* RTLIL::Module::addDlatchGate(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity)
1416 {
1417 RTLIL::Cell *cell = new RTLIL::Cell;
1418 cell->name = name;
1419 cell->type = stringf("$_DLATCH_%c_", en_polarity ? 'P' : 'N');
1420 cell->set("\\E", sig_en);
1421 cell->set("\\D", sig_d);
1422 cell->set("\\Q", sig_q);
1423 add(cell);
1424 return cell;
1425 }
1426
1427 RTLIL::Cell* RTLIL::Module::addDlatchsrGate(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
1428 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity, bool set_polarity, bool clr_polarity)
1429 {
1430 RTLIL::Cell *cell = new RTLIL::Cell;
1431 cell->name = name;
1432 cell->type = stringf("$_DLATCHSR_%c%c%c_", en_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N');
1433 cell->set("\\E", sig_en);
1434 cell->set("\\S", sig_set);
1435 cell->set("\\R", sig_clr);
1436 cell->set("\\D", sig_d);
1437 cell->set("\\Q", sig_q);
1438 add(cell);
1439 return cell;
1440 }
1441
1442
1443 RTLIL::Wire::Wire()
1444 {
1445 width = 1;
1446 start_offset = 0;
1447 port_id = 0;
1448 port_input = false;
1449 port_output = false;
1450 upto = false;
1451 }
1452
1453 RTLIL::Memory::Memory()
1454 {
1455 width = 1;
1456 size = 0;
1457 }
1458
1459 bool RTLIL::Cell::has(RTLIL::IdString portname)
1460 {
1461 return connections_.count(portname) != 0;
1462 }
1463
1464 void RTLIL::Cell::unset(RTLIL::IdString portname)
1465 {
1466 connections_.erase(portname);
1467 }
1468
1469 void RTLIL::Cell::set(RTLIL::IdString portname, RTLIL::SigSpec signal)
1470 {
1471 connections_[portname] = signal;
1472 }
1473
1474 const RTLIL::SigSpec &RTLIL::Cell::get(RTLIL::IdString portname) const
1475 {
1476 return connections_.at(portname);
1477 }
1478
1479 const std::map<RTLIL::IdString, RTLIL::SigSpec> &RTLIL::Cell::connections() const
1480 {
1481 return connections_;
1482 }
1483
1484 void RTLIL::Cell::check()
1485 {
1486 #ifndef NDEBUG
1487 InternalCellChecker checker(NULL, this);
1488 checker.check();
1489 #endif
1490 }
1491
1492 void RTLIL::Cell::fixup_parameters(bool set_a_signed, bool set_b_signed)
1493 {
1494 if (type[0] != '$' || type.substr(0, 2) == "$_" || type.substr(0, 8) == "$paramod" ||
1495 type.substr(0, 9) == "$verific$" || type.substr(0, 7) == "$array:" || type.substr(0, 8) == "$extern:")
1496 return;
1497
1498 if (type == "$mux" || type == "$pmux" || type == "$safe_pmux")
1499 {
1500 parameters["\\WIDTH"] = SIZE(connections_["\\Y"]);
1501 if (type == "$pmux" || type == "$safe_pmux")
1502 parameters["\\S_WIDTH"] = SIZE(connections_["\\S"]);
1503 check();
1504 return;
1505 }
1506
1507 bool signedness_ab = type != "$slice" && type != "$concat";
1508
1509 if (connections_.count("\\A")) {
1510 if (signedness_ab) {
1511 if (set_a_signed)
1512 parameters["\\A_SIGNED"] = true;
1513 else if (parameters.count("\\A_SIGNED") == 0)
1514 parameters["\\A_SIGNED"] = false;
1515 }
1516 parameters["\\A_WIDTH"] = SIZE(connections_["\\A"]);
1517 }
1518
1519 if (connections_.count("\\B")) {
1520 if (signedness_ab) {
1521 if (set_b_signed)
1522 parameters["\\B_SIGNED"] = true;
1523 else if (parameters.count("\\B_SIGNED") == 0)
1524 parameters["\\B_SIGNED"] = false;
1525 }
1526 parameters["\\B_WIDTH"] = SIZE(connections_["\\B"]);
1527 }
1528
1529 if (connections_.count("\\Y"))
1530 parameters["\\Y_WIDTH"] = SIZE(connections_["\\Y"]);
1531
1532 check();
1533 }
1534
1535 RTLIL::SigChunk::SigChunk()
1536 {
1537 wire = NULL;
1538 width = 0;
1539 offset = 0;
1540 }
1541
1542 RTLIL::SigChunk::SigChunk(const RTLIL::Const &value)
1543 {
1544 wire = NULL;
1545 data = value;
1546 width = data.bits.size();
1547 offset = 0;
1548 }
1549
1550 RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire)
1551 {
1552 log_assert(wire != nullptr);
1553 this->wire = wire;
1554 this->width = wire->width;
1555 this->offset = 0;
1556 }
1557
1558 RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire, int offset, int width)
1559 {
1560 log_assert(wire != nullptr);
1561 this->wire = wire;
1562 this->width = width;
1563 this->offset = offset;
1564 }
1565
1566 RTLIL::SigChunk::SigChunk(const std::string &str)
1567 {
1568 wire = NULL;
1569 data = RTLIL::Const(str);
1570 width = data.bits.size();
1571 offset = 0;
1572 }
1573
1574 RTLIL::SigChunk::SigChunk(int val, int width)
1575 {
1576 wire = NULL;
1577 data = RTLIL::Const(val, width);
1578 this->width = data.bits.size();
1579 offset = 0;
1580 }
1581
1582 RTLIL::SigChunk::SigChunk(RTLIL::State bit, int width)
1583 {
1584 wire = NULL;
1585 data = RTLIL::Const(bit, width);
1586 this->width = data.bits.size();
1587 offset = 0;
1588 }
1589
1590 RTLIL::SigChunk::SigChunk(RTLIL::SigBit bit)
1591 {
1592 wire = bit.wire;
1593 if (wire == NULL)
1594 data = RTLIL::Const(bit.data);
1595 offset = bit.offset;
1596 width = 1;
1597 }
1598
1599 RTLIL::SigChunk RTLIL::SigChunk::extract(int offset, int length) const
1600 {
1601 RTLIL::SigChunk ret;
1602 if (wire) {
1603 ret.wire = wire;
1604 ret.offset = this->offset + offset;
1605 ret.width = length;
1606 } else {
1607 for (int i = 0; i < length; i++)
1608 ret.data.bits.push_back(data.bits[offset+i]);
1609 ret.width = length;
1610 }
1611 return ret;
1612 }
1613
1614 bool RTLIL::SigChunk::operator <(const RTLIL::SigChunk &other) const
1615 {
1616 if (wire && other.wire)
1617 if (wire->name != other.wire->name)
1618 return wire->name < other.wire->name;
1619
1620 if (wire != other.wire)
1621 return wire < other.wire;
1622
1623 if (offset != other.offset)
1624 return offset < other.offset;
1625
1626 if (width != other.width)
1627 return width < other.width;
1628
1629 return data.bits < other.data.bits;
1630 }
1631
1632 bool RTLIL::SigChunk::operator ==(const RTLIL::SigChunk &other) const
1633 {
1634 if (wire != other.wire || width != other.width || offset != other.offset)
1635 return false;
1636 if (data.bits != other.data.bits)
1637 return false;
1638 return true;
1639 }
1640
1641 bool RTLIL::SigChunk::operator !=(const RTLIL::SigChunk &other) const
1642 {
1643 if (*this == other)
1644 return false;
1645 return true;
1646 }
1647
1648 RTLIL::SigSpec::SigSpec()
1649 {
1650 width_ = 0;
1651 hash_ = 0;
1652 }
1653
1654 RTLIL::SigSpec::SigSpec(const RTLIL::SigSpec &other)
1655 {
1656 *this = other;
1657 }
1658
1659 RTLIL::SigSpec::SigSpec(std::initializer_list<RTLIL::SigSpec> parts)
1660 {
1661 cover("kernel.rtlil.sigspec.init.list");
1662
1663 width_ = 0;
1664 hash_ = 0;
1665
1666 std::vector<RTLIL::SigSpec> parts_vec(parts.begin(), parts.end());
1667 for (auto it = parts_vec.rbegin(); it != parts_vec.rend(); it++)
1668 append(*it);
1669 }
1670
1671 const RTLIL::SigSpec &RTLIL::SigSpec::operator=(const RTLIL::SigSpec &other)
1672 {
1673 cover("kernel.rtlil.sigspec.assign");
1674
1675 width_ = other.width_;
1676 hash_ = other.hash_;
1677 chunks_ = other.chunks_;
1678 bits_.clear();
1679
1680 if (!other.bits_.empty())
1681 {
1682 RTLIL::SigChunk *last = NULL;
1683 int last_end_offset = 0;
1684
1685 for (auto &bit : other.bits_) {
1686 if (last && bit.wire == last->wire) {
1687 if (bit.wire == NULL) {
1688 last->data.bits.push_back(bit.data);
1689 last->width++;
1690 continue;
1691 } else if (last_end_offset == bit.offset) {
1692 last_end_offset++;
1693 last->width++;
1694 continue;
1695 }
1696 }
1697 chunks_.push_back(bit);
1698 last = &chunks_.back();
1699 last_end_offset = bit.offset + 1;
1700 }
1701
1702 check();
1703 }
1704
1705 return *this;
1706 }
1707
1708 RTLIL::SigSpec::SigSpec(const RTLIL::Const &value)
1709 {
1710 cover("kernel.rtlil.sigspec.init.const");
1711
1712 chunks_.push_back(RTLIL::SigChunk(value));
1713 width_ = chunks_.back().width;
1714 hash_ = 0;
1715 check();
1716 }
1717
1718 RTLIL::SigSpec::SigSpec(const RTLIL::SigChunk &chunk)
1719 {
1720 cover("kernel.rtlil.sigspec.init.chunk");
1721
1722 chunks_.push_back(chunk);
1723 width_ = chunks_.back().width;
1724 hash_ = 0;
1725 check();
1726 }
1727
1728 RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire)
1729 {
1730 cover("kernel.rtlil.sigspec.init.wire");
1731
1732 chunks_.push_back(RTLIL::SigChunk(wire));
1733 width_ = chunks_.back().width;
1734 hash_ = 0;
1735 check();
1736 }
1737
1738 RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire, int offset, int width)
1739 {
1740 cover("kernel.rtlil.sigspec.init.wire_part");
1741
1742 chunks_.push_back(RTLIL::SigChunk(wire, offset, width));
1743 width_ = chunks_.back().width;
1744 hash_ = 0;
1745 check();
1746 }
1747
1748 RTLIL::SigSpec::SigSpec(const std::string &str)
1749 {
1750 cover("kernel.rtlil.sigspec.init.str");
1751
1752 chunks_.push_back(RTLIL::SigChunk(str));
1753 width_ = chunks_.back().width;
1754 hash_ = 0;
1755 check();
1756 }
1757
1758 RTLIL::SigSpec::SigSpec(int val, int width)
1759 {
1760 cover("kernel.rtlil.sigspec.init.int");
1761
1762 chunks_.push_back(RTLIL::SigChunk(val, width));
1763 width_ = width;
1764 hash_ = 0;
1765 check();
1766 }
1767
1768 RTLIL::SigSpec::SigSpec(RTLIL::State bit, int width)
1769 {
1770 cover("kernel.rtlil.sigspec.init.state");
1771
1772 chunks_.push_back(RTLIL::SigChunk(bit, width));
1773 width_ = width;
1774 hash_ = 0;
1775 check();
1776 }
1777
1778 RTLIL::SigSpec::SigSpec(RTLIL::SigBit bit, int width)
1779 {
1780 cover("kernel.rtlil.sigspec.init.bit");
1781
1782 if (bit.wire == NULL)
1783 chunks_.push_back(RTLIL::SigChunk(bit.data, width));
1784 else
1785 for (int i = 0; i < width; i++)
1786 chunks_.push_back(bit);
1787 width_ = width;
1788 hash_ = 0;
1789 check();
1790 }
1791
1792 RTLIL::SigSpec::SigSpec(std::vector<RTLIL::SigChunk> chunks)
1793 {
1794 cover("kernel.rtlil.sigspec.init.stdvec_chunks");
1795
1796 width_ = 0;
1797 hash_ = 0;
1798 for (auto &c : chunks)
1799 append(c);
1800 check();
1801 }
1802
1803 RTLIL::SigSpec::SigSpec(std::vector<RTLIL::SigBit> bits)
1804 {
1805 cover("kernel.rtlil.sigspec.init.stdvec_bits");
1806
1807 width_ = 0;
1808 hash_ = 0;
1809 for (auto &bit : bits)
1810 append_bit(bit);
1811 check();
1812 }
1813
1814 RTLIL::SigSpec::SigSpec(std::set<RTLIL::SigBit> bits)
1815 {
1816 cover("kernel.rtlil.sigspec.init.stdset_bits");
1817
1818 width_ = 0;
1819 hash_ = 0;
1820 for (auto &bit : bits)
1821 append_bit(bit);
1822 check();
1823 }
1824
1825 void RTLIL::SigSpec::pack() const
1826 {
1827 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
1828
1829 if (that->bits_.empty())
1830 return;
1831
1832 cover("kernel.rtlil.sigspec.convert.pack");
1833 log_assert(that->chunks_.empty());
1834
1835 std::vector<RTLIL::SigBit> old_bits;
1836 old_bits.swap(that->bits_);
1837
1838 RTLIL::SigChunk *last = NULL;
1839 int last_end_offset = 0;
1840
1841 for (auto &bit : old_bits) {
1842 if (last && bit.wire == last->wire) {
1843 if (bit.wire == NULL) {
1844 last->data.bits.push_back(bit.data);
1845 last->width++;
1846 continue;
1847 } else if (last_end_offset == bit.offset) {
1848 last_end_offset++;
1849 last->width++;
1850 continue;
1851 }
1852 }
1853 that->chunks_.push_back(bit);
1854 last = &that->chunks_.back();
1855 last_end_offset = bit.offset + 1;
1856 }
1857
1858 check();
1859 }
1860
1861 void RTLIL::SigSpec::unpack() const
1862 {
1863 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
1864
1865 if (that->chunks_.empty())
1866 return;
1867
1868 cover("kernel.rtlil.sigspec.convert.unpack");
1869 log_assert(that->bits_.empty());
1870
1871 that->bits_.reserve(that->width_);
1872 for (auto &c : that->chunks_)
1873 for (int i = 0; i < c.width; i++)
1874 that->bits_.push_back(RTLIL::SigBit(c, i));
1875
1876 that->chunks_.clear();
1877 that->hash_ = 0;
1878 }
1879
1880 #define DJB2(_hash, _value) do { (_hash) = (((_hash) << 5) + (_hash)) + (_value); } while (0)
1881
1882 void RTLIL::SigSpec::hash() const
1883 {
1884 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
1885
1886 if (that->hash_ != 0)
1887 return;
1888
1889 cover("kernel.rtlil.sigspec.hash");
1890 that->pack();
1891
1892 that->hash_ = 5381;
1893 for (auto &c : that->chunks_)
1894 if (c.wire == NULL) {
1895 for (auto &v : c.data.bits)
1896 DJB2(that->hash_, v);
1897 } else {
1898 for (auto &v : c.wire->name)
1899 DJB2(that->hash_, v);
1900 DJB2(that->hash_, c.offset);
1901 DJB2(that->hash_, c.width);
1902 }
1903
1904 if (that->hash_ == 0)
1905 that->hash_ = 1;
1906 }
1907
1908 void RTLIL::SigSpec::sort()
1909 {
1910 unpack();
1911 cover("kernel.rtlil.sigspec.sort");
1912 std::sort(bits_.begin(), bits_.end());
1913 }
1914
1915 void RTLIL::SigSpec::sort_and_unify()
1916 {
1917 cover("kernel.rtlil.sigspec.sort_and_unify");
1918 *this = this->to_sigbit_set();
1919 }
1920
1921 void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with)
1922 {
1923 replace(pattern, with, this);
1924 }
1925
1926 void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with, RTLIL::SigSpec *other) const
1927 {
1928 cover("kernel.rtlil.sigspec.replace");
1929
1930 unpack();
1931 pattern.unpack();
1932 with.unpack();
1933
1934 log_assert(other != NULL);
1935 log_assert(width_ == other->width_);
1936 other->unpack();
1937
1938 log_assert(pattern.width_ == with.width_);
1939
1940 std::map<RTLIL::SigBit, RTLIL::SigBit> pattern_map;
1941 for (int i = 0; i < SIZE(pattern.bits_); i++)
1942 if (pattern.bits_[i].wire != NULL)
1943 pattern_map[pattern.bits_[i]] = with.bits_[i];
1944
1945 for (int i = 0; i < SIZE(bits_); i++)
1946 if (pattern_map.count(bits_[i]))
1947 other->bits_[i] = pattern_map.at(bits_[i]);
1948
1949 other->check();
1950 }
1951
1952 void RTLIL::SigSpec::remove(const RTLIL::SigSpec &pattern)
1953 {
1954 remove2(pattern, NULL);
1955 }
1956
1957 void RTLIL::SigSpec::remove(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other) const
1958 {
1959 RTLIL::SigSpec tmp = *this;
1960 tmp.remove2(pattern, other);
1961 }
1962
1963 void RTLIL::SigSpec::remove2(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other)
1964 {
1965 if (other)
1966 cover("kernel.rtlil.sigspec.remove_other");
1967 else
1968 cover("kernel.rtlil.sigspec.remove");
1969
1970 unpack();
1971
1972 if (other != NULL) {
1973 log_assert(width_ == other->width_);
1974 other->unpack();
1975 }
1976
1977 std::set<RTLIL::SigBit> pattern_bits = pattern.to_sigbit_set();
1978 std::vector<RTLIL::SigBit> new_bits, new_other_bits;
1979
1980 for (int i = 0; i < SIZE(bits_); i++) {
1981 if (bits_[i].wire != NULL && pattern_bits.count(bits_[i]))
1982 continue;
1983 if (other != NULL)
1984 new_other_bits.push_back(other->bits_[i]);
1985 new_bits.push_back(bits_[i]);
1986 }
1987
1988 bits_.swap(new_bits);
1989 width_ = SIZE(bits_);
1990
1991 if (other != NULL) {
1992 other->bits_.swap(new_other_bits);
1993 other->width_ = SIZE(other->bits_);
1994 }
1995
1996 check();
1997 }
1998
1999 RTLIL::SigSpec RTLIL::SigSpec::extract(RTLIL::SigSpec pattern, const RTLIL::SigSpec *other) const
2000 {
2001 if (other)
2002 cover("kernel.rtlil.sigspec.extract_other");
2003 else
2004 cover("kernel.rtlil.sigspec.extract");
2005
2006 pack();
2007 pattern.pack();
2008
2009 if (other != NULL)
2010 other->pack();
2011
2012 log_assert(other == NULL || width_ == other->width_);
2013
2014 std::set<RTLIL::SigBit> pat = pattern.to_sigbit_set();
2015 std::vector<RTLIL::SigBit> bits_match = to_sigbit_vector();
2016 RTLIL::SigSpec ret;
2017
2018 if (other) {
2019 std::vector<RTLIL::SigBit> bits_other = other->to_sigbit_vector();
2020 for (int i = 0; i < width_; i++)
2021 if (bits_match[i].wire && pat.count(bits_match[i]))
2022 ret.append_bit(bits_other[i]);
2023 } else {
2024 for (int i = 0; i < width_; i++)
2025 if (bits_match[i].wire && pat.count(bits_match[i]))
2026 ret.append_bit(bits_match[i]);
2027 }
2028
2029 ret.check();
2030 return ret;
2031 }
2032
2033 void RTLIL::SigSpec::replace(int offset, const RTLIL::SigSpec &with)
2034 {
2035 cover("kernel.rtlil.sigspec.replace_pos");
2036
2037 unpack();
2038 with.unpack();
2039
2040 log_assert(offset >= 0);
2041 log_assert(with.width_ >= 0);
2042 log_assert(offset+with.width_ <= width_);
2043
2044 for (int i = 0; i < with.width_; i++)
2045 bits_.at(offset + i) = with.bits_.at(i);
2046
2047 check();
2048 }
2049
2050 void RTLIL::SigSpec::remove_const()
2051 {
2052 if (packed())
2053 {
2054 cover("kernel.rtlil.sigspec.remove_const.packed");
2055
2056 std::vector<RTLIL::SigChunk> new_chunks;
2057 new_chunks.reserve(SIZE(chunks_));
2058
2059 width_ = 0;
2060 for (auto &chunk : chunks_)
2061 if (chunk.wire != NULL) {
2062 new_chunks.push_back(chunk);
2063 width_ += chunk.width;
2064 }
2065
2066 chunks_.swap(new_chunks);
2067 }
2068 else
2069 {
2070 cover("kernel.rtlil.sigspec.remove_const.unpacked");
2071
2072 std::vector<RTLIL::SigBit> new_bits;
2073 new_bits.reserve(width_);
2074
2075 for (auto &bit : bits_)
2076 if (bit.wire != NULL)
2077 new_bits.push_back(bit);
2078
2079 bits_.swap(new_bits);
2080 width_ = bits_.size();
2081 }
2082
2083 check();
2084 }
2085
2086 void RTLIL::SigSpec::remove(int offset, int length)
2087 {
2088 cover("kernel.rtlil.sigspec.remove_pos");
2089
2090 unpack();
2091
2092 log_assert(offset >= 0);
2093 log_assert(length >= 0);
2094 log_assert(offset + length <= width_);
2095
2096 bits_.erase(bits_.begin() + offset, bits_.begin() + offset + length);
2097 width_ = bits_.size();
2098
2099 check();
2100 }
2101
2102 RTLIL::SigSpec RTLIL::SigSpec::extract(int offset, int length) const
2103 {
2104 unpack();
2105 cover("kernel.rtlil.sigspec.extract_pos");
2106 return std::vector<RTLIL::SigBit>(bits_.begin() + offset, bits_.begin() + offset + length);
2107 }
2108
2109 void RTLIL::SigSpec::append(const RTLIL::SigSpec &signal)
2110 {
2111 if (signal.width_ == 0)
2112 return;
2113
2114 if (width_ == 0) {
2115 *this = signal;
2116 return;
2117 }
2118
2119 cover("kernel.rtlil.sigspec.append");
2120
2121 if (packed() != signal.packed()) {
2122 pack();
2123 signal.pack();
2124 }
2125
2126 if (packed())
2127 for (auto &other_c : signal.chunks_)
2128 {
2129 auto &my_last_c = chunks_.back();
2130 if (my_last_c.wire == NULL && other_c.wire == NULL) {
2131 auto &this_data = my_last_c.data.bits;
2132 auto &other_data = other_c.data.bits;
2133 this_data.insert(this_data.end(), other_data.begin(), other_data.end());
2134 my_last_c.width += other_c.width;
2135 } else
2136 if (my_last_c.wire == other_c.wire && my_last_c.offset + my_last_c.width == other_c.offset) {
2137 my_last_c.width += other_c.width;
2138 } else
2139 chunks_.push_back(other_c);
2140 }
2141 else
2142 bits_.insert(bits_.end(), signal.bits_.begin(), signal.bits_.end());
2143
2144 width_ += signal.width_;
2145 check();
2146 }
2147
2148 void RTLIL::SigSpec::append_bit(const RTLIL::SigBit &bit)
2149 {
2150 if (packed())
2151 {
2152 cover("kernel.rtlil.sigspec.append_bit.packed");
2153
2154 if (chunks_.size() == 0)
2155 chunks_.push_back(bit);
2156 else
2157 if (bit.wire == NULL)
2158 if (chunks_.back().wire == NULL) {
2159 chunks_.back().data.bits.push_back(bit.data);
2160 chunks_.back().width++;
2161 } else
2162 chunks_.push_back(bit);
2163 else
2164 if (chunks_.back().wire == bit.wire && chunks_.back().offset + chunks_.back().width == bit.offset)
2165 chunks_.back().width++;
2166 else
2167 chunks_.push_back(bit);
2168 }
2169 else
2170 {
2171 cover("kernel.rtlil.sigspec.append_bit.unpacked");
2172 bits_.push_back(bit);
2173 }
2174
2175 width_++;
2176 check();
2177 }
2178
2179 void RTLIL::SigSpec::extend(int width, bool is_signed)
2180 {
2181 cover("kernel.rtlil.sigspec.extend");
2182
2183 pack();
2184
2185 if (width_ > width)
2186 remove(width, width_ - width);
2187
2188 if (width_ < width) {
2189 RTLIL::SigSpec padding = width_ > 0 ? extract(width_ - 1, 1) : RTLIL::SigSpec(RTLIL::State::S0);
2190 if (!is_signed && padding != RTLIL::SigSpec(RTLIL::State::Sx) && padding != RTLIL::SigSpec(RTLIL::State::Sz) &&
2191 padding != RTLIL::SigSpec(RTLIL::State::Sa) && padding != RTLIL::SigSpec(RTLIL::State::Sm))
2192 padding = RTLIL::SigSpec(RTLIL::State::S0);
2193 while (width_ < width)
2194 append(padding);
2195 }
2196 }
2197
2198 void RTLIL::SigSpec::extend_u0(int width, bool is_signed)
2199 {
2200 cover("kernel.rtlil.sigspec.extend_u0");
2201
2202 pack();
2203
2204 if (width_ > width)
2205 remove(width, width_ - width);
2206
2207 if (width_ < width) {
2208 RTLIL::SigSpec padding = width_ > 0 ? extract(width_ - 1, 1) : RTLIL::SigSpec(RTLIL::State::S0);
2209 if (!is_signed)
2210 padding = RTLIL::SigSpec(RTLIL::State::S0);
2211 while (width_ < width)
2212 append(padding);
2213 }
2214
2215 }
2216
2217 RTLIL::SigSpec RTLIL::SigSpec::repeat(int num) const
2218 {
2219 cover("kernel.rtlil.sigspec.repeat");
2220
2221 RTLIL::SigSpec sig;
2222 for (int i = 0; i < num; i++)
2223 sig.append(*this);
2224 return sig;
2225 }
2226
2227 #ifndef NDEBUG
2228 void RTLIL::SigSpec::check() const
2229 {
2230 if (width_ > 64)
2231 {
2232 cover("kernel.rtlil.sigspec.check.skip");
2233 }
2234 else if (packed())
2235 {
2236 cover("kernel.rtlil.sigspec.check.packed");
2237
2238 int w = 0;
2239 for (size_t i = 0; i < chunks_.size(); i++) {
2240 const RTLIL::SigChunk chunk = chunks_[i];
2241 if (chunk.wire == NULL) {
2242 if (i > 0)
2243 log_assert(chunks_[i-1].wire != NULL);
2244 log_assert(chunk.offset == 0);
2245 log_assert(chunk.data.bits.size() == (size_t)chunk.width);
2246 } else {
2247 if (i > 0 && chunks_[i-1].wire == chunk.wire)
2248 log_assert(chunk.offset != chunks_[i-1].offset + chunks_[i-1].width);
2249 log_assert(chunk.offset >= 0);
2250 log_assert(chunk.width >= 0);
2251 log_assert(chunk.offset + chunk.width <= chunk.wire->width);
2252 log_assert(chunk.data.bits.size() == 0);
2253 }
2254 w += chunk.width;
2255 }
2256 log_assert(w == width_);
2257 log_assert(bits_.empty());
2258 }
2259 else
2260 {
2261 cover("kernel.rtlil.sigspec.check.unpacked");
2262
2263 log_assert(width_ == SIZE(bits_));
2264 log_assert(chunks_.empty());
2265 }
2266 }
2267 #endif
2268
2269 bool RTLIL::SigSpec::operator <(const RTLIL::SigSpec &other) const
2270 {
2271 cover("kernel.rtlil.sigspec.comp_lt");
2272
2273 if (this == &other)
2274 return false;
2275
2276 if (width_ != other.width_)
2277 return width_ < other.width_;
2278
2279 pack();
2280 other.pack();
2281
2282 if (chunks_.size() != other.chunks_.size())
2283 return chunks_.size() < other.chunks_.size();
2284
2285 hash();
2286 other.hash();
2287
2288 if (hash_ != other.hash_)
2289 return hash_ < other.hash_;
2290
2291 for (size_t i = 0; i < chunks_.size(); i++)
2292 if (chunks_[i] != other.chunks_[i]) {
2293 cover("kernel.rtlil.sigspec.comp_lt.hash_collision");
2294 return chunks_[i] < other.chunks_[i];
2295 }
2296
2297 cover("kernel.rtlil.sigspec.comp_lt.equal");
2298 return false;
2299 }
2300
2301 bool RTLIL::SigSpec::operator ==(const RTLIL::SigSpec &other) const
2302 {
2303 cover("kernel.rtlil.sigspec.comp_eq");
2304
2305 if (this == &other)
2306 return true;
2307
2308 if (width_ != other.width_)
2309 return false;
2310
2311 pack();
2312 other.pack();
2313
2314 if (chunks_.size() != chunks_.size())
2315 return false;
2316
2317 hash();
2318 other.hash();
2319
2320 if (hash_ != other.hash_)
2321 return false;
2322
2323 for (size_t i = 0; i < chunks_.size(); i++)
2324 if (chunks_[i] != other.chunks_[i]) {
2325 cover("kernel.rtlil.sigspec.comp_eq.hash_collision");
2326 return false;
2327 }
2328
2329 cover("kernel.rtlil.sigspec.comp_eq.equal");
2330 return true;
2331 }
2332
2333 bool RTLIL::SigSpec::is_wire() const
2334 {
2335 cover("kernel.rtlil.sigspec.is_wire");
2336
2337 pack();
2338 return SIZE(chunks_) == 1 && chunks_[0].wire && chunks_[0].wire->width == width_;
2339 }
2340
2341 bool RTLIL::SigSpec::is_chunk() const
2342 {
2343 cover("kernel.rtlil.sigspec.is_chunk");
2344
2345 pack();
2346 return SIZE(chunks_) == 1;
2347 }
2348
2349 bool RTLIL::SigSpec::is_fully_const() const
2350 {
2351 cover("kernel.rtlil.sigspec.is_fully_const");
2352
2353 pack();
2354 for (auto it = chunks_.begin(); it != chunks_.end(); it++)
2355 if (it->width > 0 && it->wire != NULL)
2356 return false;
2357 return true;
2358 }
2359
2360 bool RTLIL::SigSpec::is_fully_def() const
2361 {
2362 cover("kernel.rtlil.sigspec.is_fully_def");
2363
2364 pack();
2365 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
2366 if (it->width > 0 && it->wire != NULL)
2367 return false;
2368 for (size_t i = 0; i < it->data.bits.size(); i++)
2369 if (it->data.bits[i] != RTLIL::State::S0 && it->data.bits[i] != RTLIL::State::S1)
2370 return false;
2371 }
2372 return true;
2373 }
2374
2375 bool RTLIL::SigSpec::is_fully_undef() const
2376 {
2377 cover("kernel.rtlil.sigspec.is_fully_undef");
2378
2379 pack();
2380 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
2381 if (it->width > 0 && it->wire != NULL)
2382 return false;
2383 for (size_t i = 0; i < it->data.bits.size(); i++)
2384 if (it->data.bits[i] != RTLIL::State::Sx && it->data.bits[i] != RTLIL::State::Sz)
2385 return false;
2386 }
2387 return true;
2388 }
2389
2390 bool RTLIL::SigSpec::has_marked_bits() const
2391 {
2392 cover("kernel.rtlil.sigspec.has_marked_bits");
2393
2394 pack();
2395 for (auto it = chunks_.begin(); it != chunks_.end(); it++)
2396 if (it->width > 0 && it->wire == NULL) {
2397 for (size_t i = 0; i < it->data.bits.size(); i++)
2398 if (it->data.bits[i] == RTLIL::State::Sm)
2399 return true;
2400 }
2401 return false;
2402 }
2403
2404 bool RTLIL::SigSpec::as_bool() const
2405 {
2406 cover("kernel.rtlil.sigspec.as_bool");
2407
2408 pack();
2409 log_assert(is_fully_const() && SIZE(chunks_) <= 1);
2410 if (width_)
2411 return chunks_[0].data.as_bool();
2412 return false;
2413 }
2414
2415 int RTLIL::SigSpec::as_int() const
2416 {
2417 cover("kernel.rtlil.sigspec.as_int");
2418
2419 pack();
2420 log_assert(is_fully_const() && SIZE(chunks_) <= 1);
2421 if (width_)
2422 return chunks_[0].data.as_int();
2423 return 0;
2424 }
2425
2426 std::string RTLIL::SigSpec::as_string() const
2427 {
2428 cover("kernel.rtlil.sigspec.as_string");
2429
2430 pack();
2431 std::string str;
2432 for (size_t i = chunks_.size(); i > 0; i--) {
2433 const RTLIL::SigChunk &chunk = chunks_[i-1];
2434 if (chunk.wire != NULL)
2435 for (int j = 0; j < chunk.width; j++)
2436 str += "?";
2437 else
2438 str += chunk.data.as_string();
2439 }
2440 return str;
2441 }
2442
2443 RTLIL::Const RTLIL::SigSpec::as_const() const
2444 {
2445 cover("kernel.rtlil.sigspec.as_const");
2446
2447 pack();
2448 log_assert(is_fully_const() && SIZE(chunks_) <= 1);
2449 if (width_)
2450 return chunks_[0].data;
2451 return RTLIL::Const();
2452 }
2453
2454 RTLIL::Wire *RTLIL::SigSpec::as_wire() const
2455 {
2456 cover("kernel.rtlil.sigspec.as_wire");
2457
2458 pack();
2459 log_assert(is_wire());
2460 return chunks_[0].wire;
2461 }
2462
2463 RTLIL::SigChunk RTLIL::SigSpec::as_chunk() const
2464 {
2465 cover("kernel.rtlil.sigspec.as_chunk");
2466
2467 pack();
2468 log_assert(is_chunk());
2469 return chunks_[0];
2470 }
2471
2472 bool RTLIL::SigSpec::match(std::string pattern) const
2473 {
2474 cover("kernel.rtlil.sigspec.match");
2475
2476 pack();
2477 std::string str = as_string();
2478 log_assert(pattern.size() == str.size());
2479
2480 for (size_t i = 0; i < pattern.size(); i++) {
2481 if (pattern[i] == ' ')
2482 continue;
2483 if (pattern[i] == '*') {
2484 if (str[i] != 'z' && str[i] != 'x')
2485 return false;
2486 continue;
2487 }
2488 if (pattern[i] != str[i])
2489 return false;
2490 }
2491
2492 return true;
2493 }
2494
2495 std::set<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_set() const
2496 {
2497 cover("kernel.rtlil.sigspec.to_sigbit_set");
2498
2499 pack();
2500 std::set<RTLIL::SigBit> sigbits;
2501 for (auto &c : chunks_)
2502 for (int i = 0; i < c.width; i++)
2503 sigbits.insert(RTLIL::SigBit(c, i));
2504 return sigbits;
2505 }
2506
2507 std::vector<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_vector() const
2508 {
2509 cover("kernel.rtlil.sigspec.to_sigbit_vector");
2510
2511 unpack();
2512 return bits_;
2513 }
2514
2515 RTLIL::SigBit RTLIL::SigSpec::to_single_sigbit() const
2516 {
2517 cover("kernel.rtlil.sigspec.to_single_sigbit");
2518
2519 pack();
2520 log_assert(width_ == 1);
2521 for (auto &c : chunks_)
2522 if (c.width)
2523 return RTLIL::SigBit(c);
2524 log_abort();
2525 }
2526
2527 static void sigspec_parse_split(std::vector<std::string> &tokens, const std::string &text, char sep)
2528 {
2529 size_t start = 0, end = 0;
2530 while ((end = text.find(sep, start)) != std::string::npos) {
2531 tokens.push_back(text.substr(start, end - start));
2532 start = end + 1;
2533 }
2534 tokens.push_back(text.substr(start));
2535 }
2536
2537 static int sigspec_parse_get_dummy_line_num()
2538 {
2539 return 0;
2540 }
2541
2542 bool RTLIL::SigSpec::parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str)
2543 {
2544 cover("kernel.rtlil.sigspec.parse");
2545
2546 std::vector<std::string> tokens;
2547 sigspec_parse_split(tokens, str, ',');
2548
2549 sig = RTLIL::SigSpec();
2550 for (int tokidx = int(tokens.size())-1; tokidx >= 0; tokidx--)
2551 {
2552 std::string netname = tokens[tokidx];
2553 std::string indices;
2554
2555 if (netname.size() == 0)
2556 continue;
2557
2558 if ('0' <= netname[0] && netname[0] <= '9') {
2559 cover("kernel.rtlil.sigspec.parse.const");
2560 AST::get_line_num = sigspec_parse_get_dummy_line_num;
2561 AST::AstNode *ast = VERILOG_FRONTEND::const2ast(netname);
2562 if (ast == NULL)
2563 return false;
2564 sig.append(RTLIL::Const(ast->bits));
2565 delete ast;
2566 continue;
2567 }
2568
2569 if (module == NULL)
2570 return false;
2571
2572 cover("kernel.rtlil.sigspec.parse.net");
2573
2574 if (netname[0] != '$' && netname[0] != '\\')
2575 netname = "\\" + netname;
2576
2577 if (module->wires_.count(netname) == 0) {
2578 size_t indices_pos = netname.size()-1;
2579 if (indices_pos > 2 && netname[indices_pos] == ']')
2580 {
2581 indices_pos--;
2582 while (indices_pos > 0 && ('0' <= netname[indices_pos] && netname[indices_pos] <= '9')) indices_pos--;
2583 if (indices_pos > 0 && netname[indices_pos] == ':') {
2584 indices_pos--;
2585 while (indices_pos > 0 && ('0' <= netname[indices_pos] && netname[indices_pos] <= '9')) indices_pos--;
2586 }
2587 if (indices_pos > 0 && netname[indices_pos] == '[') {
2588 indices = netname.substr(indices_pos);
2589 netname = netname.substr(0, indices_pos);
2590 }
2591 }
2592 }
2593
2594 if (module->wires_.count(netname) == 0)
2595 return false;
2596
2597 RTLIL::Wire *wire = module->wires_.at(netname);
2598 if (!indices.empty()) {
2599 std::vector<std::string> index_tokens;
2600 sigspec_parse_split(index_tokens, indices.substr(1, indices.size()-2), ':');
2601 if (index_tokens.size() == 1) {
2602 cover("kernel.rtlil.sigspec.parse.bit_sel");
2603 sig.append(RTLIL::SigSpec(wire, atoi(index_tokens.at(0).c_str())));
2604 } else {
2605 cover("kernel.rtlil.sigspec.parse.part_sel");
2606 int a = atoi(index_tokens.at(0).c_str());
2607 int b = atoi(index_tokens.at(1).c_str());
2608 if (a > b) {
2609 int tmp = a;
2610 a = b, b = tmp;
2611 }
2612 sig.append(RTLIL::SigSpec(wire, a, b-a+1));
2613 }
2614 } else
2615 sig.append(wire);
2616 }
2617
2618 return true;
2619 }
2620
2621 bool RTLIL::SigSpec::parse_sel(RTLIL::SigSpec &sig, RTLIL::Design *design, RTLIL::Module *module, std::string str)
2622 {
2623 if (str.empty() || str[0] != '@')
2624 return parse(sig, module, str);
2625
2626 cover("kernel.rtlil.sigspec.parse.sel");
2627
2628 str = RTLIL::escape_id(str.substr(1));
2629 if (design->selection_vars.count(str) == 0)
2630 return false;
2631
2632 sig = RTLIL::SigSpec();
2633 RTLIL::Selection &sel = design->selection_vars.at(str);
2634 for (auto &it : module->wires_)
2635 if (sel.selected_member(module->name, it.first))
2636 sig.append(it.second);
2637
2638 return true;
2639 }
2640
2641 bool RTLIL::SigSpec::parse_rhs(const RTLIL::SigSpec &lhs, RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str)
2642 {
2643 if (str == "0") {
2644 cover("kernel.rtlil.sigspec.parse.rhs_zeros");
2645 sig = RTLIL::SigSpec(RTLIL::State::S0, lhs.width_);
2646 return true;
2647 }
2648
2649 if (str == "~0") {
2650 cover("kernel.rtlil.sigspec.parse.rhs_ones");
2651 sig = RTLIL::SigSpec(RTLIL::State::S1, lhs.width_);
2652 return true;
2653 }
2654
2655 if (lhs.chunks_.size() == 1) {
2656 char *p = (char*)str.c_str(), *endptr;
2657 long long int val = strtoll(p, &endptr, 10);
2658 if (endptr && endptr != p && *endptr == 0) {
2659 sig = RTLIL::SigSpec(val, lhs.width_);
2660 cover("kernel.rtlil.sigspec.parse.rhs_dec");
2661 return true;
2662 }
2663 }
2664
2665 return parse(sig, module, str);
2666 }
2667
2668 RTLIL::CaseRule::~CaseRule()
2669 {
2670 for (auto it = switches.begin(); it != switches.end(); it++)
2671 delete *it;
2672 }
2673
2674 RTLIL::CaseRule *RTLIL::CaseRule::clone() const
2675 {
2676 RTLIL::CaseRule *new_caserule = new RTLIL::CaseRule;
2677 new_caserule->compare = compare;
2678 new_caserule->actions = actions;
2679 for (auto &it : switches)
2680 new_caserule->switches.push_back(it->clone());
2681 return new_caserule;
2682 }
2683
2684 RTLIL::SwitchRule::~SwitchRule()
2685 {
2686 for (auto it = cases.begin(); it != cases.end(); it++)
2687 delete *it;
2688 }
2689
2690 RTLIL::SwitchRule *RTLIL::SwitchRule::clone() const
2691 {
2692 RTLIL::SwitchRule *new_switchrule = new RTLIL::SwitchRule;
2693 new_switchrule->signal = signal;
2694 new_switchrule->attributes = attributes;
2695 for (auto &it : cases)
2696 new_switchrule->cases.push_back(it->clone());
2697 return new_switchrule;
2698
2699 }
2700
2701 RTLIL::SyncRule *RTLIL::SyncRule::clone() const
2702 {
2703 RTLIL::SyncRule *new_syncrule = new RTLIL::SyncRule;
2704 new_syncrule->type = type;
2705 new_syncrule->signal = signal;
2706 new_syncrule->actions = actions;
2707 return new_syncrule;
2708 }
2709
2710 RTLIL::Process::~Process()
2711 {
2712 for (auto it = syncs.begin(); it != syncs.end(); it++)
2713 delete *it;
2714 }
2715
2716 RTLIL::Process *RTLIL::Process::clone() const
2717 {
2718 RTLIL::Process *new_proc = new RTLIL::Process;
2719
2720 new_proc->name = name;
2721 new_proc->attributes = attributes;
2722
2723 RTLIL::CaseRule *rc_ptr = root_case.clone();
2724 new_proc->root_case = *rc_ptr;
2725 rc_ptr->switches.clear();
2726 delete rc_ptr;
2727
2728 for (auto &it : syncs)
2729 new_proc->syncs.push_back(it->clone());
2730
2731 return new_proc;
2732 }
2733