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Fixed RTLIL::SigSpec::parse() for out-of-range bit- and part-selects
[yosys.git] / kernel / rtlil.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 #include "kernel/yosys.h"
21 #include "kernel/macc.h"
22 #include "frontends/verilog/verilog_frontend.h"
23 #include "backends/ilang/ilang_backend.h"
24
25 #include <string.h>
26 #include <algorithm>
27
28 YOSYS_NAMESPACE_BEGIN
29
30 std::vector<int> RTLIL::IdString::global_refcount_storage_;
31 std::vector<char*> RTLIL::IdString::global_id_storage_;
32 std::map<char*, int, RTLIL::IdString::char_ptr_cmp> RTLIL::IdString::global_id_index_;
33 std::vector<int> RTLIL::IdString::global_free_idx_list_;
34
35 RTLIL::Const::Const()
36 {
37 flags = RTLIL::CONST_FLAG_NONE;
38 }
39
40 RTLIL::Const::Const(std::string str)
41 {
42 flags = RTLIL::CONST_FLAG_STRING;
43 for (int i = str.size()-1; i >= 0; i--) {
44 unsigned char ch = str[i];
45 for (int j = 0; j < 8; j++) {
46 bits.push_back((ch & 1) != 0 ? RTLIL::S1 : RTLIL::S0);
47 ch = ch >> 1;
48 }
49 }
50 }
51
52 RTLIL::Const::Const(int val, int width)
53 {
54 flags = RTLIL::CONST_FLAG_NONE;
55 for (int i = 0; i < width; i++) {
56 bits.push_back((val & 1) != 0 ? RTLIL::S1 : RTLIL::S0);
57 val = val >> 1;
58 }
59 }
60
61 RTLIL::Const::Const(RTLIL::State bit, int width)
62 {
63 flags = RTLIL::CONST_FLAG_NONE;
64 for (int i = 0; i < width; i++)
65 bits.push_back(bit);
66 }
67
68 RTLIL::Const::Const(const std::vector<bool> &bits)
69 {
70 flags = RTLIL::CONST_FLAG_NONE;
71 for (auto b : bits)
72 this->bits.push_back(b ? RTLIL::S1 : RTLIL::S0);
73 }
74
75 bool RTLIL::Const::operator <(const RTLIL::Const &other) const
76 {
77 if (bits.size() != other.bits.size())
78 return bits.size() < other.bits.size();
79 for (size_t i = 0; i < bits.size(); i++)
80 if (bits[i] != other.bits[i])
81 return bits[i] < other.bits[i];
82 return false;
83 }
84
85 bool RTLIL::Const::operator ==(const RTLIL::Const &other) const
86 {
87 return bits == other.bits;
88 }
89
90 bool RTLIL::Const::operator !=(const RTLIL::Const &other) const
91 {
92 return bits != other.bits;
93 }
94
95 bool RTLIL::Const::as_bool() const
96 {
97 for (size_t i = 0; i < bits.size(); i++)
98 if (bits[i] == RTLIL::S1)
99 return true;
100 return false;
101 }
102
103 int RTLIL::Const::as_int(bool is_signed) const
104 {
105 int32_t ret = 0;
106 for (size_t i = 0; i < bits.size() && i < 32; i++)
107 if (bits[i] == RTLIL::S1)
108 ret |= 1 << i;
109 if (is_signed && bits.back() == RTLIL::S1)
110 for (size_t i = bits.size(); i < 32; i++)
111 ret |= 1 << i;
112 return ret;
113 }
114
115 std::string RTLIL::Const::as_string() const
116 {
117 std::string ret;
118 for (size_t i = bits.size(); i > 0; i--)
119 switch (bits[i-1]) {
120 case S0: ret += "0"; break;
121 case S1: ret += "1"; break;
122 case Sx: ret += "x"; break;
123 case Sz: ret += "z"; break;
124 case Sa: ret += "-"; break;
125 case Sm: ret += "m"; break;
126 }
127 return ret;
128 }
129
130 std::string RTLIL::Const::decode_string() const
131 {
132 std::string string;
133 std::vector <char> string_chars;
134 for (int i = 0; i < int (bits.size()); i += 8) {
135 char ch = 0;
136 for (int j = 0; j < 8 && i + j < int (bits.size()); j++)
137 if (bits[i + j] == RTLIL::State::S1)
138 ch |= 1 << j;
139 if (ch != 0)
140 string_chars.push_back(ch);
141 }
142 for (int i = int (string_chars.size()) - 1; i >= 0; i--)
143 string += string_chars[i];
144 return string;
145 }
146
147 bool RTLIL::Selection::selected_module(RTLIL::IdString mod_name) const
148 {
149 if (full_selection)
150 return true;
151 if (selected_modules.count(mod_name) > 0)
152 return true;
153 if (selected_members.count(mod_name) > 0)
154 return true;
155 return false;
156 }
157
158 bool RTLIL::Selection::selected_whole_module(RTLIL::IdString mod_name) const
159 {
160 if (full_selection)
161 return true;
162 if (selected_modules.count(mod_name) > 0)
163 return true;
164 return false;
165 }
166
167 bool RTLIL::Selection::selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const
168 {
169 if (full_selection)
170 return true;
171 if (selected_modules.count(mod_name) > 0)
172 return true;
173 if (selected_members.count(mod_name) > 0)
174 if (selected_members.at(mod_name).count(memb_name) > 0)
175 return true;
176 return false;
177 }
178
179 void RTLIL::Selection::optimize(RTLIL::Design *design)
180 {
181 if (full_selection) {
182 selected_modules.clear();
183 selected_members.clear();
184 return;
185 }
186
187 std::vector<RTLIL::IdString> del_list, add_list;
188
189 del_list.clear();
190 for (auto mod_name : selected_modules) {
191 if (design->modules_.count(mod_name) == 0)
192 del_list.push_back(mod_name);
193 selected_members.erase(mod_name);
194 }
195 for (auto mod_name : del_list)
196 selected_modules.erase(mod_name);
197
198 del_list.clear();
199 for (auto &it : selected_members)
200 if (design->modules_.count(it.first) == 0)
201 del_list.push_back(it.first);
202 for (auto mod_name : del_list)
203 selected_members.erase(mod_name);
204
205 for (auto &it : selected_members) {
206 del_list.clear();
207 for (auto memb_name : it.second)
208 if (design->modules_[it.first]->count_id(memb_name) == 0)
209 del_list.push_back(memb_name);
210 for (auto memb_name : del_list)
211 it.second.erase(memb_name);
212 }
213
214 del_list.clear();
215 add_list.clear();
216 for (auto &it : selected_members)
217 if (it.second.size() == 0)
218 del_list.push_back(it.first);
219 else if (it.second.size() == design->modules_[it.first]->wires_.size() + design->modules_[it.first]->memories.size() +
220 design->modules_[it.first]->cells_.size() + design->modules_[it.first]->processes.size())
221 add_list.push_back(it.first);
222 for (auto mod_name : del_list)
223 selected_members.erase(mod_name);
224 for (auto mod_name : add_list) {
225 selected_members.erase(mod_name);
226 selected_modules.insert(mod_name);
227 }
228
229 if (selected_modules.size() == design->modules_.size()) {
230 full_selection = true;
231 selected_modules.clear();
232 selected_members.clear();
233 }
234 }
235
236 RTLIL::Design::Design()
237 {
238 refcount_modules_ = 0;
239 selection_stack.push_back(RTLIL::Selection());
240 }
241
242 RTLIL::Design::~Design()
243 {
244 for (auto it = modules_.begin(); it != modules_.end(); it++)
245 delete it->second;
246 }
247
248 RTLIL::ObjRange<RTLIL::Module*> RTLIL::Design::modules()
249 {
250 return RTLIL::ObjRange<RTLIL::Module*>(&modules_, &refcount_modules_);
251 }
252
253 RTLIL::Module *RTLIL::Design::module(RTLIL::IdString name)
254 {
255 return modules_.count(name) ? modules_.at(name) : NULL;
256 }
257
258 void RTLIL::Design::add(RTLIL::Module *module)
259 {
260 log_assert(modules_.count(module->name) == 0);
261 log_assert(refcount_modules_ == 0);
262 modules_[module->name] = module;
263 module->design = this;
264
265 for (auto mon : monitors)
266 mon->notify_module_add(module);
267 }
268
269 RTLIL::Module *RTLIL::Design::addModule(RTLIL::IdString name)
270 {
271 log_assert(modules_.count(name) == 0);
272 log_assert(refcount_modules_ == 0);
273
274 RTLIL::Module *module = new RTLIL::Module;
275 modules_[name] = module;
276 module->design = this;
277 module->name = name;
278
279 for (auto mon : monitors)
280 mon->notify_module_add(module);
281
282 return module;
283 }
284
285 void RTLIL::Design::scratchpad_unset(std::string varname)
286 {
287 scratchpad.erase(varname);
288 }
289
290 void RTLIL::Design::scratchpad_set_int(std::string varname, int value)
291 {
292 scratchpad[varname] = stringf("%d", value);
293 }
294
295 void RTLIL::Design::scratchpad_set_bool(std::string varname, bool value)
296 {
297 scratchpad[varname] = value ? "true" : "false";
298 }
299
300 void RTLIL::Design::scratchpad_set_string(std::string varname, std::string value)
301 {
302 scratchpad[varname] = value;
303 }
304
305 int RTLIL::Design::scratchpad_get_int(std::string varname, int default_value) const
306 {
307 if (scratchpad.count(varname) == 0)
308 return default_value;
309
310 std::string str = scratchpad.at(varname);
311
312 if (str == "0" || str == "false")
313 return 0;
314
315 if (str == "1" || str == "true")
316 return 1;
317
318 char *endptr = nullptr;
319 long int parsed_value = strtol(str.c_str(), &endptr, 10);
320 return *endptr ? default_value : parsed_value;
321 }
322
323 bool RTLIL::Design::scratchpad_get_bool(std::string varname, bool default_value) const
324 {
325 if (scratchpad.count(varname) == 0)
326 return default_value;
327
328 std::string str = scratchpad.at(varname);
329
330 if (str == "0" || str == "false")
331 return false;
332
333 if (str == "1" || str == "true")
334 return true;
335
336 return default_value;
337 }
338
339 std::string RTLIL::Design::scratchpad_get_string(std::string varname, std::string default_value) const
340 {
341 if (scratchpad.count(varname) == 0)
342 return default_value;
343 return scratchpad.at(varname);
344 }
345
346 void RTLIL::Design::remove(RTLIL::Module *module)
347 {
348 for (auto mon : monitors)
349 mon->notify_module_del(module);
350
351 log_assert(modules_.at(module->name) == module);
352 modules_.erase(module->name);
353 delete module;
354 }
355
356 void RTLIL::Design::check()
357 {
358 #ifndef NDEBUG
359 for (auto &it : modules_) {
360 log_assert(this == it.second->design);
361 log_assert(it.first == it.second->name);
362 log_assert(!it.first.empty());
363 it.second->check();
364 }
365 #endif
366 }
367
368 void RTLIL::Design::optimize()
369 {
370 for (auto &it : modules_)
371 it.second->optimize();
372 for (auto &it : selection_stack)
373 it.optimize(this);
374 for (auto &it : selection_vars)
375 it.second.optimize(this);
376 }
377
378 bool RTLIL::Design::selected_module(RTLIL::IdString mod_name) const
379 {
380 if (!selected_active_module.empty() && mod_name != selected_active_module)
381 return false;
382 if (selection_stack.size() == 0)
383 return true;
384 return selection_stack.back().selected_module(mod_name);
385 }
386
387 bool RTLIL::Design::selected_whole_module(RTLIL::IdString mod_name) const
388 {
389 if (!selected_active_module.empty() && mod_name != selected_active_module)
390 return false;
391 if (selection_stack.size() == 0)
392 return true;
393 return selection_stack.back().selected_whole_module(mod_name);
394 }
395
396 bool RTLIL::Design::selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const
397 {
398 if (!selected_active_module.empty() && mod_name != selected_active_module)
399 return false;
400 if (selection_stack.size() == 0)
401 return true;
402 return selection_stack.back().selected_member(mod_name, memb_name);
403 }
404
405 bool RTLIL::Design::selected_module(RTLIL::Module *mod) const
406 {
407 return selected_module(mod->name);
408 }
409
410 bool RTLIL::Design::selected_whole_module(RTLIL::Module *mod) const
411 {
412 return selected_whole_module(mod->name);
413 }
414
415 std::vector<RTLIL::Module*> RTLIL::Design::selected_modules() const
416 {
417 std::vector<RTLIL::Module*> result;
418 result.reserve(modules_.size());
419 for (auto &it : modules_)
420 if (selected_module(it.first))
421 result.push_back(it.second);
422 return result;
423 }
424
425 std::vector<RTLIL::Module*> RTLIL::Design::selected_whole_modules() const
426 {
427 std::vector<RTLIL::Module*> result;
428 result.reserve(modules_.size());
429 for (auto &it : modules_)
430 if (selected_whole_module(it.first))
431 result.push_back(it.second);
432 return result;
433 }
434
435 std::vector<RTLIL::Module*> RTLIL::Design::selected_whole_modules_warn() const
436 {
437 std::vector<RTLIL::Module*> result;
438 result.reserve(modules_.size());
439 for (auto &it : modules_)
440 if (selected_whole_module(it.first))
441 result.push_back(it.second);
442 else if (selected_module(it.first))
443 log("Warning: Ignoring partially selected module %s.\n", log_id(it.first));
444 return result;
445 }
446
447 RTLIL::Module::Module()
448 {
449 design = nullptr;
450 refcount_wires_ = 0;
451 refcount_cells_ = 0;
452 }
453
454 RTLIL::Module::~Module()
455 {
456 for (auto it = wires_.begin(); it != wires_.end(); it++)
457 delete it->second;
458 for (auto it = memories.begin(); it != memories.end(); it++)
459 delete it->second;
460 for (auto it = cells_.begin(); it != cells_.end(); it++)
461 delete it->second;
462 for (auto it = processes.begin(); it != processes.end(); it++)
463 delete it->second;
464 }
465
466 RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, std::map<RTLIL::IdString, RTLIL::Const>)
467 {
468 log_error("Module `%s' is used with parameters but is not parametric!\n", id2cstr(name));
469 }
470
471 size_t RTLIL::Module::count_id(RTLIL::IdString id)
472 {
473 return wires_.count(id) + memories.count(id) + cells_.count(id) + processes.count(id);
474 }
475
476 #ifndef NDEBUG
477 namespace {
478 struct InternalCellChecker
479 {
480 RTLIL::Module *module;
481 RTLIL::Cell *cell;
482 std::set<RTLIL::IdString> expected_params, expected_ports;
483
484 InternalCellChecker(RTLIL::Module *module, RTLIL::Cell *cell) : module(module), cell(cell) { }
485
486 void error(int linenr)
487 {
488 std::stringstream buf;
489 ILANG_BACKEND::dump_cell(buf, " ", cell);
490
491 log_error("Found error in internal cell %s%s%s (%s) at %s:%d:\n%s",
492 module ? module->name.c_str() : "", module ? "." : "",
493 cell->name.c_str(), cell->type.c_str(), __FILE__, linenr, buf.str().c_str());
494 }
495
496 int param(const char *name)
497 {
498 if (cell->parameters.count(name) == 0)
499 error(__LINE__);
500 expected_params.insert(name);
501 return cell->parameters.at(name).as_int();
502 }
503
504 int param_bool(const char *name)
505 {
506 int v = param(name);
507 if (cell->parameters.at(name).bits.size() > 32)
508 error(__LINE__);
509 if (v != 0 && v != 1)
510 error(__LINE__);
511 return v;
512 }
513
514 void param_bits(const char *name, int width)
515 {
516 param(name);
517 if (int(cell->parameters.at(name).bits.size()) != width)
518 error(__LINE__);
519 }
520
521 void port(const char *name, int width)
522 {
523 if (!cell->hasPort(name))
524 error(__LINE__);
525 if (cell->getPort(name).size() != width)
526 error(__LINE__);
527 expected_ports.insert(name);
528 }
529
530 void check_expected(bool check_matched_sign = true)
531 {
532 for (auto &para : cell->parameters)
533 if (expected_params.count(para.first) == 0)
534 error(__LINE__);
535 for (auto &conn : cell->connections())
536 if (expected_ports.count(conn.first) == 0)
537 error(__LINE__);
538
539 if (expected_params.count("\\A_SIGNED") != 0 && expected_params.count("\\B_SIGNED") && check_matched_sign) {
540 bool a_is_signed = param("\\A_SIGNED") != 0;
541 bool b_is_signed = param("\\B_SIGNED") != 0;
542 if (a_is_signed != b_is_signed)
543 error(__LINE__);
544 }
545 }
546
547 void check_gate(const char *ports)
548 {
549 if (cell->parameters.size() != 0)
550 error(__LINE__);
551
552 for (const char *p = ports; *p; p++) {
553 char portname[3] = { '\\', *p, 0 };
554 if (!cell->hasPort(portname))
555 error(__LINE__);
556 if (cell->getPort(portname).size() != 1)
557 error(__LINE__);
558 }
559
560 for (auto &conn : cell->connections()) {
561 if (conn.first.size() != 2 || conn.first[0] != '\\')
562 error(__LINE__);
563 if (strchr(ports, conn.first[1]) == NULL)
564 error(__LINE__);
565 }
566 }
567
568 void check()
569 {
570 if (cell->type.substr(0, 1) != "$" || cell->type.substr(0, 3) == "$__" || cell->type.substr(0, 8) == "$paramod" ||
571 cell->type.substr(0, 9) == "$verific$" || cell->type.substr(0, 7) == "$array:" || cell->type.substr(0, 8) == "$extern:")
572 return;
573
574 if (cell->type.in("$not", "$pos", "$neg")) {
575 param_bool("\\A_SIGNED");
576 port("\\A", param("\\A_WIDTH"));
577 port("\\Y", param("\\Y_WIDTH"));
578 check_expected();
579 return;
580 }
581
582 if (cell->type.in("$and", "$or", "$xor", "$xnor")) {
583 param_bool("\\A_SIGNED");
584 param_bool("\\B_SIGNED");
585 port("\\A", param("\\A_WIDTH"));
586 port("\\B", param("\\B_WIDTH"));
587 port("\\Y", param("\\Y_WIDTH"));
588 check_expected();
589 return;
590 }
591
592 if (cell->type.in("$reduce_and", "$reduce_or", "$reduce_xor", "$reduce_xnor", "$reduce_bool")) {
593 param_bool("\\A_SIGNED");
594 port("\\A", param("\\A_WIDTH"));
595 port("\\Y", param("\\Y_WIDTH"));
596 check_expected();
597 return;
598 }
599
600 if (cell->type.in("$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx")) {
601 param_bool("\\A_SIGNED");
602 param_bool("\\B_SIGNED");
603 port("\\A", param("\\A_WIDTH"));
604 port("\\B", param("\\B_WIDTH"));
605 port("\\Y", param("\\Y_WIDTH"));
606 check_expected(false);
607 return;
608 }
609
610 if (cell->type.in("$lt", "$le", "$eq", "$ne", "$eqx", "$nex", "$ge", "$gt")) {
611 param_bool("\\A_SIGNED");
612 param_bool("\\B_SIGNED");
613 port("\\A", param("\\A_WIDTH"));
614 port("\\B", param("\\B_WIDTH"));
615 port("\\Y", param("\\Y_WIDTH"));
616 check_expected();
617 return;
618 }
619
620 if (cell->type.in("$add", "$sub", "$mul", "$div", "$mod", "$pow")) {
621 param_bool("\\A_SIGNED");
622 param_bool("\\B_SIGNED");
623 port("\\A", param("\\A_WIDTH"));
624 port("\\B", param("\\B_WIDTH"));
625 port("\\Y", param("\\Y_WIDTH"));
626 check_expected(cell->type != "$pow");
627 return;
628 }
629
630 if (cell->type == "$fa") {
631 port("\\A", param("\\WIDTH"));
632 port("\\B", param("\\WIDTH"));
633 port("\\C", param("\\WIDTH"));
634 port("\\X", param("\\WIDTH"));
635 port("\\Y", param("\\WIDTH"));
636 check_expected();
637 return;
638 }
639
640 if (cell->type == "$lcu") {
641 port("\\P", param("\\WIDTH"));
642 port("\\G", param("\\WIDTH"));
643 port("\\CI", 1);
644 port("\\CO", param("\\WIDTH"));
645 check_expected();
646 return;
647 }
648
649 if (cell->type == "$alu") {
650 param_bool("\\A_SIGNED");
651 param_bool("\\B_SIGNED");
652 port("\\A", param("\\A_WIDTH"));
653 port("\\B", param("\\B_WIDTH"));
654 port("\\CI", 1);
655 port("\\BI", 1);
656 port("\\X", param("\\Y_WIDTH"));
657 port("\\Y", param("\\Y_WIDTH"));
658 port("\\CO", param("\\Y_WIDTH"));
659 check_expected();
660 return;
661 }
662
663 if (cell->type == "$macc") {
664 param("\\CONFIG");
665 param("\\CONFIG_WIDTH");
666 port("\\A", param("\\A_WIDTH"));
667 port("\\B", param("\\B_WIDTH"));
668 port("\\Y", param("\\Y_WIDTH"));
669 check_expected();
670 Macc().from_cell(cell);
671 return;
672 }
673
674 if (cell->type == "$logic_not") {
675 param_bool("\\A_SIGNED");
676 port("\\A", param("\\A_WIDTH"));
677 port("\\Y", param("\\Y_WIDTH"));
678 check_expected();
679 return;
680 }
681
682 if (cell->type == "$logic_and" || cell->type == "$logic_or") {
683 param_bool("\\A_SIGNED");
684 param_bool("\\B_SIGNED");
685 port("\\A", param("\\A_WIDTH"));
686 port("\\B", param("\\B_WIDTH"));
687 port("\\Y", param("\\Y_WIDTH"));
688 check_expected(false);
689 return;
690 }
691
692 if (cell->type == "$slice") {
693 param("\\OFFSET");
694 port("\\A", param("\\A_WIDTH"));
695 port("\\Y", param("\\Y_WIDTH"));
696 if (param("\\OFFSET") + param("\\Y_WIDTH") > param("\\A_WIDTH"))
697 error(__LINE__);
698 check_expected();
699 return;
700 }
701
702 if (cell->type == "$concat") {
703 port("\\A", param("\\A_WIDTH"));
704 port("\\B", param("\\B_WIDTH"));
705 port("\\Y", param("\\A_WIDTH") + param("\\B_WIDTH"));
706 check_expected();
707 return;
708 }
709
710 if (cell->type == "$mux") {
711 port("\\A", param("\\WIDTH"));
712 port("\\B", param("\\WIDTH"));
713 port("\\S", 1);
714 port("\\Y", param("\\WIDTH"));
715 check_expected();
716 return;
717 }
718
719 if (cell->type == "$pmux") {
720 port("\\A", param("\\WIDTH"));
721 port("\\B", param("\\WIDTH") * param("\\S_WIDTH"));
722 port("\\S", param("\\S_WIDTH"));
723 port("\\Y", param("\\WIDTH"));
724 check_expected();
725 return;
726 }
727
728 if (cell->type == "$lut") {
729 param("\\LUT");
730 port("\\A", param("\\WIDTH"));
731 port("\\Y", 1);
732 check_expected();
733 return;
734 }
735
736 if (cell->type == "$sr") {
737 param_bool("\\SET_POLARITY");
738 param_bool("\\CLR_POLARITY");
739 port("\\SET", param("\\WIDTH"));
740 port("\\CLR", param("\\WIDTH"));
741 port("\\Q", param("\\WIDTH"));
742 check_expected();
743 return;
744 }
745
746 if (cell->type == "$dff") {
747 param_bool("\\CLK_POLARITY");
748 port("\\CLK", 1);
749 port("\\D", param("\\WIDTH"));
750 port("\\Q", param("\\WIDTH"));
751 check_expected();
752 return;
753 }
754
755 if (cell->type == "$dffsr") {
756 param_bool("\\CLK_POLARITY");
757 param_bool("\\SET_POLARITY");
758 param_bool("\\CLR_POLARITY");
759 port("\\CLK", 1);
760 port("\\SET", param("\\WIDTH"));
761 port("\\CLR", param("\\WIDTH"));
762 port("\\D", param("\\WIDTH"));
763 port("\\Q", param("\\WIDTH"));
764 check_expected();
765 return;
766 }
767
768 if (cell->type == "$adff") {
769 param_bool("\\CLK_POLARITY");
770 param_bool("\\ARST_POLARITY");
771 param_bits("\\ARST_VALUE", param("\\WIDTH"));
772 port("\\CLK", 1);
773 port("\\ARST", 1);
774 port("\\D", param("\\WIDTH"));
775 port("\\Q", param("\\WIDTH"));
776 check_expected();
777 return;
778 }
779
780 if (cell->type == "$dlatch") {
781 param_bool("\\EN_POLARITY");
782 port("\\EN", 1);
783 port("\\D", param("\\WIDTH"));
784 port("\\Q", param("\\WIDTH"));
785 check_expected();
786 return;
787 }
788
789 if (cell->type == "$dlatchsr") {
790 param_bool("\\EN_POLARITY");
791 param_bool("\\SET_POLARITY");
792 param_bool("\\CLR_POLARITY");
793 port("\\EN", 1);
794 port("\\SET", param("\\WIDTH"));
795 port("\\CLR", param("\\WIDTH"));
796 port("\\D", param("\\WIDTH"));
797 port("\\Q", param("\\WIDTH"));
798 check_expected();
799 return;
800 }
801
802 if (cell->type == "$fsm") {
803 param("\\NAME");
804 param_bool("\\CLK_POLARITY");
805 param_bool("\\ARST_POLARITY");
806 param("\\STATE_BITS");
807 param("\\STATE_NUM");
808 param("\\STATE_NUM_LOG2");
809 param("\\STATE_RST");
810 param_bits("\\STATE_TABLE", param("\\STATE_BITS") * param("\\STATE_NUM"));
811 param("\\TRANS_NUM");
812 param_bits("\\TRANS_TABLE", param("\\TRANS_NUM") * (2*param("\\STATE_NUM_LOG2") + param("\\CTRL_IN_WIDTH") + param("\\CTRL_OUT_WIDTH")));
813 port("\\CLK", 1);
814 port("\\ARST", 1);
815 port("\\CTRL_IN", param("\\CTRL_IN_WIDTH"));
816 port("\\CTRL_OUT", param("\\CTRL_OUT_WIDTH"));
817 check_expected();
818 return;
819 }
820
821 if (cell->type == "$memrd") {
822 param("\\MEMID");
823 param_bool("\\CLK_ENABLE");
824 param_bool("\\CLK_POLARITY");
825 param_bool("\\TRANSPARENT");
826 port("\\CLK", 1);
827 port("\\ADDR", param("\\ABITS"));
828 port("\\DATA", param("\\WIDTH"));
829 check_expected();
830 return;
831 }
832
833 if (cell->type == "$memwr") {
834 param("\\MEMID");
835 param_bool("\\CLK_ENABLE");
836 param_bool("\\CLK_POLARITY");
837 param("\\PRIORITY");
838 port("\\CLK", 1);
839 port("\\EN", param("\\WIDTH"));
840 port("\\ADDR", param("\\ABITS"));
841 port("\\DATA", param("\\WIDTH"));
842 check_expected();
843 return;
844 }
845
846 if (cell->type == "$mem") {
847 param("\\MEMID");
848 param("\\SIZE");
849 param("\\OFFSET");
850 param_bits("\\RD_CLK_ENABLE", param("\\RD_PORTS"));
851 param_bits("\\RD_CLK_POLARITY", param("\\RD_PORTS"));
852 param_bits("\\RD_TRANSPARENT", param("\\RD_PORTS"));
853 param_bits("\\WR_CLK_ENABLE", param("\\WR_PORTS"));
854 param_bits("\\WR_CLK_POLARITY", param("\\WR_PORTS"));
855 port("\\RD_CLK", param("\\RD_PORTS"));
856 port("\\RD_ADDR", param("\\RD_PORTS") * param("\\ABITS"));
857 port("\\RD_DATA", param("\\RD_PORTS") * param("\\WIDTH"));
858 port("\\WR_CLK", param("\\WR_PORTS"));
859 port("\\WR_EN", param("\\WR_PORTS") * param("\\WIDTH"));
860 port("\\WR_ADDR", param("\\WR_PORTS") * param("\\ABITS"));
861 port("\\WR_DATA", param("\\WR_PORTS") * param("\\WIDTH"));
862 check_expected();
863 return;
864 }
865
866 if (cell->type == "$assert") {
867 port("\\A", 1);
868 port("\\EN", 1);
869 check_expected();
870 return;
871 }
872
873 if (cell->type == "$_BUF_") { check_gate("AY"); return; }
874 if (cell->type == "$_NOT_") { check_gate("AY"); return; }
875 if (cell->type == "$_AND_") { check_gate("ABY"); return; }
876 if (cell->type == "$_NAND_") { check_gate("ABY"); return; }
877 if (cell->type == "$_OR_") { check_gate("ABY"); return; }
878 if (cell->type == "$_NOR_") { check_gate("ABY"); return; }
879 if (cell->type == "$_XOR_") { check_gate("ABY"); return; }
880 if (cell->type == "$_XNOR_") { check_gate("ABY"); return; }
881 if (cell->type == "$_MUX_") { check_gate("ABSY"); return; }
882 if (cell->type == "$_AOI3_") { check_gate("ABCY"); return; }
883 if (cell->type == "$_OAI3_") { check_gate("ABCY"); return; }
884 if (cell->type == "$_AOI4_") { check_gate("ABCDY"); return; }
885 if (cell->type == "$_OAI4_") { check_gate("ABCDY"); return; }
886
887 if (cell->type == "$_SR_NN_") { check_gate("SRQ"); return; }
888 if (cell->type == "$_SR_NP_") { check_gate("SRQ"); return; }
889 if (cell->type == "$_SR_PN_") { check_gate("SRQ"); return; }
890 if (cell->type == "$_SR_PP_") { check_gate("SRQ"); return; }
891
892 if (cell->type == "$_DFF_N_") { check_gate("DQC"); return; }
893 if (cell->type == "$_DFF_P_") { check_gate("DQC"); return; }
894
895 if (cell->type == "$_DFF_NN0_") { check_gate("DQCR"); return; }
896 if (cell->type == "$_DFF_NN1_") { check_gate("DQCR"); return; }
897 if (cell->type == "$_DFF_NP0_") { check_gate("DQCR"); return; }
898 if (cell->type == "$_DFF_NP1_") { check_gate("DQCR"); return; }
899 if (cell->type == "$_DFF_PN0_") { check_gate("DQCR"); return; }
900 if (cell->type == "$_DFF_PN1_") { check_gate("DQCR"); return; }
901 if (cell->type == "$_DFF_PP0_") { check_gate("DQCR"); return; }
902 if (cell->type == "$_DFF_PP1_") { check_gate("DQCR"); return; }
903
904 if (cell->type == "$_DFFSR_NNN_") { check_gate("CSRDQ"); return; }
905 if (cell->type == "$_DFFSR_NNP_") { check_gate("CSRDQ"); return; }
906 if (cell->type == "$_DFFSR_NPN_") { check_gate("CSRDQ"); return; }
907 if (cell->type == "$_DFFSR_NPP_") { check_gate("CSRDQ"); return; }
908 if (cell->type == "$_DFFSR_PNN_") { check_gate("CSRDQ"); return; }
909 if (cell->type == "$_DFFSR_PNP_") { check_gate("CSRDQ"); return; }
910 if (cell->type == "$_DFFSR_PPN_") { check_gate("CSRDQ"); return; }
911 if (cell->type == "$_DFFSR_PPP_") { check_gate("CSRDQ"); return; }
912
913 if (cell->type == "$_DLATCH_N_") { check_gate("EDQ"); return; }
914 if (cell->type == "$_DLATCH_P_") { check_gate("EDQ"); return; }
915
916 if (cell->type == "$_DLATCHSR_NNN_") { check_gate("ESRDQ"); return; }
917 if (cell->type == "$_DLATCHSR_NNP_") { check_gate("ESRDQ"); return; }
918 if (cell->type == "$_DLATCHSR_NPN_") { check_gate("ESRDQ"); return; }
919 if (cell->type == "$_DLATCHSR_NPP_") { check_gate("ESRDQ"); return; }
920 if (cell->type == "$_DLATCHSR_PNN_") { check_gate("ESRDQ"); return; }
921 if (cell->type == "$_DLATCHSR_PNP_") { check_gate("ESRDQ"); return; }
922 if (cell->type == "$_DLATCHSR_PPN_") { check_gate("ESRDQ"); return; }
923 if (cell->type == "$_DLATCHSR_PPP_") { check_gate("ESRDQ"); return; }
924
925 error(__LINE__);
926 }
927 };
928 }
929 #endif
930
931 void RTLIL::Module::check()
932 {
933 #ifndef NDEBUG
934 std::vector<bool> ports_declared;
935 for (auto &it : wires_) {
936 log_assert(this == it.second->module);
937 log_assert(it.first == it.second->name);
938 log_assert(!it.first.empty());
939 log_assert(it.second->width >= 0);
940 log_assert(it.second->port_id >= 0);
941 for (auto &it2 : it.second->attributes)
942 log_assert(!it2.first.empty());
943 if (it.second->port_id) {
944 log_assert(GetSize(ports) >= it.second->port_id);
945 log_assert(ports.at(it.second->port_id-1) == it.first);
946 log_assert(it.second->port_input || it.second->port_output);
947 if (GetSize(ports_declared) < it.second->port_id)
948 ports_declared.resize(it.second->port_id);
949 log_assert(ports_declared[it.second->port_id-1] == false);
950 ports_declared[it.second->port_id-1] = true;
951 } else
952 log_assert(!it.second->port_input && !it.second->port_output);
953 }
954 for (auto port_declared : ports_declared)
955 log_assert(port_declared == true);
956 log_assert(GetSize(ports) == GetSize(ports_declared));
957
958 for (auto &it : memories) {
959 log_assert(it.first == it.second->name);
960 log_assert(!it.first.empty());
961 log_assert(it.second->width >= 0);
962 log_assert(it.second->size >= 0);
963 for (auto &it2 : it.second->attributes)
964 log_assert(!it2.first.empty());
965 }
966
967 for (auto &it : cells_) {
968 log_assert(this == it.second->module);
969 log_assert(it.first == it.second->name);
970 log_assert(!it.first.empty());
971 log_assert(!it.second->type.empty());
972 for (auto &it2 : it.second->connections()) {
973 log_assert(!it2.first.empty());
974 it2.second.check();
975 }
976 for (auto &it2 : it.second->attributes)
977 log_assert(!it2.first.empty());
978 for (auto &it2 : it.second->parameters)
979 log_assert(!it2.first.empty());
980 InternalCellChecker checker(this, it.second);
981 checker.check();
982 }
983
984 for (auto &it : processes) {
985 log_assert(it.first == it.second->name);
986 log_assert(!it.first.empty());
987 // FIXME: More checks here..
988 }
989
990 for (auto &it : connections_) {
991 log_assert(it.first.size() == it.second.size());
992 it.first.check();
993 it.second.check();
994 }
995
996 for (auto &it : attributes)
997 log_assert(!it.first.empty());
998 #endif
999 }
1000
1001 void RTLIL::Module::optimize()
1002 {
1003 }
1004
1005 void RTLIL::Module::cloneInto(RTLIL::Module *new_mod) const
1006 {
1007 log_assert(new_mod->refcount_wires_ == 0);
1008 log_assert(new_mod->refcount_cells_ == 0);
1009
1010 new_mod->connections_ = connections_;
1011 new_mod->attributes = attributes;
1012
1013 for (auto &it : wires_)
1014 new_mod->addWire(it.first, it.second);
1015
1016 for (auto &it : memories)
1017 new_mod->memories[it.first] = new RTLIL::Memory(*it.second);
1018
1019 for (auto &it : cells_)
1020 new_mod->addCell(it.first, it.second);
1021
1022 for (auto &it : processes)
1023 new_mod->processes[it.first] = it.second->clone();
1024
1025 struct RewriteSigSpecWorker
1026 {
1027 RTLIL::Module *mod;
1028 void operator()(RTLIL::SigSpec &sig)
1029 {
1030 std::vector<RTLIL::SigChunk> chunks = sig.chunks();
1031 for (auto &c : chunks)
1032 if (c.wire != NULL)
1033 c.wire = mod->wires_.at(c.wire->name);
1034 sig = chunks;
1035 }
1036 };
1037
1038 RewriteSigSpecWorker rewriteSigSpecWorker;
1039 rewriteSigSpecWorker.mod = new_mod;
1040 new_mod->rewrite_sigspecs(rewriteSigSpecWorker);
1041 new_mod->fixup_ports();
1042 }
1043
1044 RTLIL::Module *RTLIL::Module::clone() const
1045 {
1046 RTLIL::Module *new_mod = new RTLIL::Module;
1047 new_mod->name = name;
1048 cloneInto(new_mod);
1049 return new_mod;
1050 }
1051
1052 bool RTLIL::Module::has_memories() const
1053 {
1054 return !memories.empty();
1055 }
1056
1057 bool RTLIL::Module::has_processes() const
1058 {
1059 return !processes.empty();
1060 }
1061
1062 bool RTLIL::Module::has_memories_warn() const
1063 {
1064 if (!memories.empty())
1065 log("Warning: Ignoring module %s because it contains memories (run 'memory' command first).\n", log_id(this));
1066 return !memories.empty();
1067 }
1068
1069 bool RTLIL::Module::has_processes_warn() const
1070 {
1071 if (!processes.empty())
1072 log("Warning: Ignoring module %s because it contains processes (run 'proc' command first).\n", log_id(this));
1073 return !processes.empty();
1074 }
1075
1076 std::vector<RTLIL::Wire*> RTLIL::Module::selected_wires() const
1077 {
1078 std::vector<RTLIL::Wire*> result;
1079 result.reserve(wires_.size());
1080 for (auto &it : wires_)
1081 if (design->selected(this, it.second))
1082 result.push_back(it.second);
1083 return result;
1084 }
1085
1086 std::vector<RTLIL::Cell*> RTLIL::Module::selected_cells() const
1087 {
1088 std::vector<RTLIL::Cell*> result;
1089 result.reserve(wires_.size());
1090 for (auto &it : cells_)
1091 if (design->selected(this, it.second))
1092 result.push_back(it.second);
1093 return result;
1094 }
1095
1096 void RTLIL::Module::add(RTLIL::Wire *wire)
1097 {
1098 log_assert(!wire->name.empty());
1099 log_assert(count_id(wire->name) == 0);
1100 log_assert(refcount_wires_ == 0);
1101 wires_[wire->name] = wire;
1102 wire->module = this;
1103 }
1104
1105 void RTLIL::Module::add(RTLIL::Cell *cell)
1106 {
1107 log_assert(!cell->name.empty());
1108 log_assert(count_id(cell->name) == 0);
1109 log_assert(refcount_cells_ == 0);
1110 cells_[cell->name] = cell;
1111 cell->module = this;
1112 }
1113
1114 namespace {
1115 struct DeleteWireWorker
1116 {
1117 RTLIL::Module *module;
1118 const std::set<RTLIL::Wire*> *wires_p;
1119
1120 void operator()(RTLIL::SigSpec &sig) {
1121 std::vector<RTLIL::SigChunk> chunks = sig;
1122 for (auto &c : chunks)
1123 if (c.wire != NULL && wires_p->count(c.wire)) {
1124 c.wire = module->addWire(NEW_ID, c.width);
1125 c.offset = 0;
1126 }
1127 sig = chunks;
1128 }
1129 };
1130 }
1131
1132 #if 0
1133 void RTLIL::Module::remove(RTLIL::Wire *wire)
1134 {
1135 std::setPort<RTLIL::Wire*> wires_;
1136 wires_.insert(wire);
1137 remove(wires_);
1138 }
1139 #endif
1140
1141 void RTLIL::Module::remove(const std::set<RTLIL::Wire*> &wires)
1142 {
1143 log_assert(refcount_wires_ == 0);
1144
1145 DeleteWireWorker delete_wire_worker;
1146 delete_wire_worker.module = this;
1147 delete_wire_worker.wires_p = &wires;
1148 rewrite_sigspecs(delete_wire_worker);
1149
1150 for (auto &it : wires) {
1151 log_assert(wires_.count(it->name) != 0);
1152 wires_.erase(it->name);
1153 delete it;
1154 }
1155 }
1156
1157 void RTLIL::Module::remove(RTLIL::Cell *cell)
1158 {
1159 while (!cell->connections_.empty())
1160 cell->unsetPort(cell->connections_.begin()->first);
1161
1162 log_assert(cells_.count(cell->name) != 0);
1163 log_assert(refcount_cells_ == 0);
1164 cells_.erase(cell->name);
1165 delete cell;
1166 }
1167
1168 void RTLIL::Module::rename(RTLIL::Wire *wire, RTLIL::IdString new_name)
1169 {
1170 log_assert(wires_[wire->name] == wire);
1171 log_assert(refcount_wires_ == 0);
1172 wires_.erase(wire->name);
1173 wire->name = new_name;
1174 add(wire);
1175 }
1176
1177 void RTLIL::Module::rename(RTLIL::Cell *cell, RTLIL::IdString new_name)
1178 {
1179 log_assert(cells_[cell->name] == cell);
1180 log_assert(refcount_wires_ == 0);
1181 cells_.erase(cell->name);
1182 cell->name = new_name;
1183 add(cell);
1184 }
1185
1186 void RTLIL::Module::rename(RTLIL::IdString old_name, RTLIL::IdString new_name)
1187 {
1188 log_assert(count_id(old_name) != 0);
1189 if (wires_.count(old_name))
1190 rename(wires_.at(old_name), new_name);
1191 else if (cells_.count(old_name))
1192 rename(cells_.at(old_name), new_name);
1193 else
1194 log_abort();
1195 }
1196
1197 void RTLIL::Module::swap_names(RTLIL::Wire *w1, RTLIL::Wire *w2)
1198 {
1199 log_assert(wires_[w1->name] == w1);
1200 log_assert(wires_[w2->name] == w2);
1201 log_assert(refcount_wires_ == 0);
1202
1203 wires_.erase(w1->name);
1204 wires_.erase(w2->name);
1205
1206 std::swap(w1->name, w2->name);
1207
1208 wires_[w1->name] = w1;
1209 wires_[w2->name] = w2;
1210 }
1211
1212 void RTLIL::Module::swap_names(RTLIL::Cell *c1, RTLIL::Cell *c2)
1213 {
1214 log_assert(cells_[c1->name] == c1);
1215 log_assert(cells_[c2->name] == c2);
1216 log_assert(refcount_cells_ == 0);
1217
1218 cells_.erase(c1->name);
1219 cells_.erase(c2->name);
1220
1221 std::swap(c1->name, c2->name);
1222
1223 cells_[c1->name] = c1;
1224 cells_[c2->name] = c2;
1225 }
1226
1227 RTLIL::IdString RTLIL::Module::uniquify(RTLIL::IdString name)
1228 {
1229 int index = 0;
1230 return uniquify(name, index);
1231 }
1232
1233 RTLIL::IdString RTLIL::Module::uniquify(RTLIL::IdString name, int &index)
1234 {
1235 if (index == 0) {
1236 if (count_id(name) == 0)
1237 return name;
1238 index++;
1239 }
1240
1241 while (1) {
1242 RTLIL::IdString new_name = stringf("%s_%d", name.c_str(), index);
1243 if (count_id(new_name) == 0)
1244 return new_name;
1245 index++;
1246 }
1247 }
1248
1249 static bool fixup_ports_compare(const RTLIL::Wire *a, const RTLIL::Wire *b)
1250 {
1251 if (a->port_id && !b->port_id)
1252 return true;
1253 if (!a->port_id && b->port_id)
1254 return false;
1255
1256 if (a->port_id == b->port_id)
1257 return a->name < b->name;
1258 return a->port_id < b->port_id;
1259 }
1260
1261 void RTLIL::Module::connect(const RTLIL::SigSig &conn)
1262 {
1263 for (auto mon : monitors)
1264 mon->notify_connect(this, conn);
1265
1266 if (design)
1267 for (auto mon : design->monitors)
1268 mon->notify_connect(this, conn);
1269
1270 connections_.push_back(conn);
1271 }
1272
1273 void RTLIL::Module::connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs)
1274 {
1275 connect(RTLIL::SigSig(lhs, rhs));
1276 }
1277
1278 void RTLIL::Module::new_connections(const std::vector<RTLIL::SigSig> &new_conn)
1279 {
1280 for (auto mon : monitors)
1281 mon->notify_connect(this, new_conn);
1282
1283 if (design)
1284 for (auto mon : design->monitors)
1285 mon->notify_connect(this, new_conn);
1286
1287 connections_ = new_conn;
1288 }
1289
1290 const std::vector<RTLIL::SigSig> &RTLIL::Module::connections() const
1291 {
1292 return connections_;
1293 }
1294
1295 void RTLIL::Module::fixup_ports()
1296 {
1297 std::vector<RTLIL::Wire*> all_ports;
1298
1299 for (auto &w : wires_)
1300 if (w.second->port_input || w.second->port_output)
1301 all_ports.push_back(w.second);
1302 else
1303 w.second->port_id = 0;
1304
1305 std::sort(all_ports.begin(), all_ports.end(), fixup_ports_compare);
1306
1307 ports.clear();
1308 for (size_t i = 0; i < all_ports.size(); i++) {
1309 ports.push_back(all_ports[i]->name);
1310 all_ports[i]->port_id = i+1;
1311 }
1312 }
1313
1314 RTLIL::Wire *RTLIL::Module::addWire(RTLIL::IdString name, int width)
1315 {
1316 RTLIL::Wire *wire = new RTLIL::Wire;
1317 wire->name = name;
1318 wire->width = width;
1319 add(wire);
1320 return wire;
1321 }
1322
1323 RTLIL::Wire *RTLIL::Module::addWire(RTLIL::IdString name, const RTLIL::Wire *other)
1324 {
1325 RTLIL::Wire *wire = addWire(name);
1326 wire->width = other->width;
1327 wire->start_offset = other->start_offset;
1328 wire->port_id = other->port_id;
1329 wire->port_input = other->port_input;
1330 wire->port_output = other->port_output;
1331 wire->upto = other->upto;
1332 wire->attributes = other->attributes;
1333 return wire;
1334 }
1335
1336 RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, RTLIL::IdString type)
1337 {
1338 RTLIL::Cell *cell = new RTLIL::Cell;
1339 cell->name = name;
1340 cell->type = type;
1341 add(cell);
1342 return cell;
1343 }
1344
1345 RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, const RTLIL::Cell *other)
1346 {
1347 RTLIL::Cell *cell = addCell(name, other->type);
1348 cell->connections_ = other->connections_;
1349 cell->parameters = other->parameters;
1350 cell->attributes = other->attributes;
1351 return cell;
1352 }
1353
1354 #define DEF_METHOD(_func, _y_size, _type) \
1355 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed) { \
1356 RTLIL::Cell *cell = addCell(name, _type); \
1357 cell->parameters["\\A_SIGNED"] = is_signed; \
1358 cell->parameters["\\A_WIDTH"] = sig_a.size(); \
1359 cell->parameters["\\Y_WIDTH"] = sig_y.size(); \
1360 cell->setPort("\\A", sig_a); \
1361 cell->setPort("\\Y", sig_y); \
1362 return cell; \
1363 } \
1364 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed) { \
1365 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
1366 add ## _func(name, sig_a, sig_y, is_signed); \
1367 return sig_y; \
1368 }
1369 DEF_METHOD(Not, sig_a.size(), "$not")
1370 DEF_METHOD(Pos, sig_a.size(), "$pos")
1371 DEF_METHOD(Neg, sig_a.size(), "$neg")
1372 DEF_METHOD(ReduceAnd, 1, "$reduce_and")
1373 DEF_METHOD(ReduceOr, 1, "$reduce_or")
1374 DEF_METHOD(ReduceXor, 1, "$reduce_xor")
1375 DEF_METHOD(ReduceXnor, 1, "$reduce_xnor")
1376 DEF_METHOD(ReduceBool, 1, "$reduce_bool")
1377 DEF_METHOD(LogicNot, 1, "$logic_not")
1378 #undef DEF_METHOD
1379
1380 #define DEF_METHOD(_func, _y_size, _type) \
1381 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed) { \
1382 RTLIL::Cell *cell = addCell(name, _type); \
1383 cell->parameters["\\A_SIGNED"] = is_signed; \
1384 cell->parameters["\\B_SIGNED"] = is_signed; \
1385 cell->parameters["\\A_WIDTH"] = sig_a.size(); \
1386 cell->parameters["\\B_WIDTH"] = sig_b.size(); \
1387 cell->parameters["\\Y_WIDTH"] = sig_y.size(); \
1388 cell->setPort("\\A", sig_a); \
1389 cell->setPort("\\B", sig_b); \
1390 cell->setPort("\\Y", sig_y); \
1391 return cell; \
1392 } \
1393 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed) { \
1394 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
1395 add ## _func(name, sig_a, sig_b, sig_y, is_signed); \
1396 return sig_y; \
1397 }
1398 DEF_METHOD(And, std::max(sig_a.size(), sig_b.size()), "$and")
1399 DEF_METHOD(Or, std::max(sig_a.size(), sig_b.size()), "$or")
1400 DEF_METHOD(Xor, std::max(sig_a.size(), sig_b.size()), "$xor")
1401 DEF_METHOD(Xnor, std::max(sig_a.size(), sig_b.size()), "$xnor")
1402 DEF_METHOD(Shl, sig_a.size(), "$shl")
1403 DEF_METHOD(Shr, sig_a.size(), "$shr")
1404 DEF_METHOD(Sshl, sig_a.size(), "$sshl")
1405 DEF_METHOD(Sshr, sig_a.size(), "$sshr")
1406 DEF_METHOD(Shift, sig_a.size(), "$shift")
1407 DEF_METHOD(Shiftx, sig_a.size(), "$shiftx")
1408 DEF_METHOD(Lt, 1, "$lt")
1409 DEF_METHOD(Le, 1, "$le")
1410 DEF_METHOD(Eq, 1, "$eq")
1411 DEF_METHOD(Ne, 1, "$ne")
1412 DEF_METHOD(Eqx, 1, "$eqx")
1413 DEF_METHOD(Nex, 1, "$nex")
1414 DEF_METHOD(Ge, 1, "$ge")
1415 DEF_METHOD(Gt, 1, "$gt")
1416 DEF_METHOD(Add, std::max(sig_a.size(), sig_b.size()), "$add")
1417 DEF_METHOD(Sub, std::max(sig_a.size(), sig_b.size()), "$sub")
1418 DEF_METHOD(Mul, std::max(sig_a.size(), sig_b.size()), "$mul")
1419 DEF_METHOD(Div, std::max(sig_a.size(), sig_b.size()), "$div")
1420 DEF_METHOD(Mod, std::max(sig_a.size(), sig_b.size()), "$mod")
1421 DEF_METHOD(LogicAnd, 1, "$logic_and")
1422 DEF_METHOD(LogicOr, 1, "$logic_or")
1423 #undef DEF_METHOD
1424
1425 #define DEF_METHOD(_func, _type, _pmux) \
1426 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, RTLIL::SigSpec sig_y) { \
1427 RTLIL::Cell *cell = addCell(name, _type); \
1428 cell->parameters["\\WIDTH"] = sig_a.size(); \
1429 if (_pmux) cell->parameters["\\S_WIDTH"] = sig_s.size(); \
1430 cell->setPort("\\A", sig_a); \
1431 cell->setPort("\\B", sig_b); \
1432 cell->setPort("\\S", sig_s); \
1433 cell->setPort("\\Y", sig_y); \
1434 return cell; \
1435 } \
1436 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s) { \
1437 RTLIL::SigSpec sig_y = addWire(NEW_ID, sig_a.size()); \
1438 add ## _func(name, sig_a, sig_b, sig_s, sig_y); \
1439 return sig_y; \
1440 }
1441 DEF_METHOD(Mux, "$mux", 0)
1442 DEF_METHOD(Pmux, "$pmux", 1)
1443 #undef DEF_METHOD
1444
1445 #define DEF_METHOD_2(_func, _type, _P1, _P2) \
1446 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2) { \
1447 RTLIL::Cell *cell = addCell(name, _type); \
1448 cell->setPort("\\" #_P1, sig1); \
1449 cell->setPort("\\" #_P2, sig2); \
1450 return cell; \
1451 } \
1452 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1) { \
1453 RTLIL::SigBit sig2 = addWire(NEW_ID); \
1454 add ## _func(name, sig1, sig2); \
1455 return sig2; \
1456 }
1457 #define DEF_METHOD_3(_func, _type, _P1, _P2, _P3) \
1458 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3) { \
1459 RTLIL::Cell *cell = addCell(name, _type); \
1460 cell->setPort("\\" #_P1, sig1); \
1461 cell->setPort("\\" #_P2, sig2); \
1462 cell->setPort("\\" #_P3, sig3); \
1463 return cell; \
1464 } \
1465 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2) { \
1466 RTLIL::SigBit sig3 = addWire(NEW_ID); \
1467 add ## _func(name, sig1, sig2, sig3); \
1468 return sig3; \
1469 }
1470 #define DEF_METHOD_4(_func, _type, _P1, _P2, _P3, _P4) \
1471 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, RTLIL::SigBit sig4) { \
1472 RTLIL::Cell *cell = addCell(name, _type); \
1473 cell->setPort("\\" #_P1, sig1); \
1474 cell->setPort("\\" #_P2, sig2); \
1475 cell->setPort("\\" #_P3, sig3); \
1476 cell->setPort("\\" #_P4, sig4); \
1477 return cell; \
1478 } \
1479 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3) { \
1480 RTLIL::SigBit sig4 = addWire(NEW_ID); \
1481 add ## _func(name, sig1, sig2, sig3, sig4); \
1482 return sig4; \
1483 }
1484 #define DEF_METHOD_5(_func, _type, _P1, _P2, _P3, _P4, _P5) \
1485 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, RTLIL::SigBit sig4, RTLIL::SigBit sig5) { \
1486 RTLIL::Cell *cell = addCell(name, _type); \
1487 cell->setPort("\\" #_P1, sig1); \
1488 cell->setPort("\\" #_P2, sig2); \
1489 cell->setPort("\\" #_P3, sig3); \
1490 cell->setPort("\\" #_P4, sig4); \
1491 cell->setPort("\\" #_P5, sig5); \
1492 return cell; \
1493 } \
1494 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, RTLIL::SigBit sig4) { \
1495 RTLIL::SigBit sig5 = addWire(NEW_ID); \
1496 add ## _func(name, sig1, sig2, sig3, sig4, sig5); \
1497 return sig5; \
1498 }
1499 DEF_METHOD_2(NotGate, "$_NOT_", A, Y)
1500 DEF_METHOD_3(AndGate, "$_AND_", A, B, Y)
1501 DEF_METHOD_3(NandGate, "$_NAND_", A, B, Y)
1502 DEF_METHOD_3(OrGate, "$_OR_", A, B, Y)
1503 DEF_METHOD_3(NorGate, "$_NOR_", A, B, Y)
1504 DEF_METHOD_3(XorGate, "$_XOR_", A, B, Y)
1505 DEF_METHOD_3(XnorGate, "$_XNOR_", A, B, Y)
1506 DEF_METHOD_4(MuxGate, "$_MUX_", A, B, S, Y)
1507 DEF_METHOD_4(Aoi3Gate, "$_AOI3_", A, B, C, Y)
1508 DEF_METHOD_4(Oai3Gate, "$_OAI3_", A, B, C, Y)
1509 DEF_METHOD_5(Aoi4Gate, "$_AOI4_", A, B, C, D, Y)
1510 DEF_METHOD_5(Oai4Gate, "$_OAI4_", A, B, C, D, Y)
1511 #undef DEF_METHOD_2
1512 #undef DEF_METHOD_3
1513 #undef DEF_METHOD_4
1514 #undef DEF_METHOD_5
1515
1516 RTLIL::Cell* RTLIL::Module::addPow(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool a_signed, bool b_signed)
1517 {
1518 RTLIL::Cell *cell = addCell(name, "$pow");
1519 cell->parameters["\\A_SIGNED"] = a_signed;
1520 cell->parameters["\\B_SIGNED"] = b_signed;
1521 cell->parameters["\\A_WIDTH"] = sig_a.size();
1522 cell->parameters["\\B_WIDTH"] = sig_b.size();
1523 cell->parameters["\\Y_WIDTH"] = sig_y.size();
1524 cell->setPort("\\A", sig_a);
1525 cell->setPort("\\B", sig_b);
1526 cell->setPort("\\Y", sig_y);
1527 return cell;
1528 }
1529
1530 RTLIL::Cell* RTLIL::Module::addSlice(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, RTLIL::Const offset)
1531 {
1532 RTLIL::Cell *cell = addCell(name, "$slice");
1533 cell->parameters["\\A_WIDTH"] = sig_a.size();
1534 cell->parameters["\\Y_WIDTH"] = sig_y.size();
1535 cell->parameters["\\OFFSET"] = offset;
1536 cell->setPort("\\A", sig_a);
1537 cell->setPort("\\Y", sig_y);
1538 return cell;
1539 }
1540
1541 RTLIL::Cell* RTLIL::Module::addConcat(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y)
1542 {
1543 RTLIL::Cell *cell = addCell(name, "$concat");
1544 cell->parameters["\\A_WIDTH"] = sig_a.size();
1545 cell->parameters["\\B_WIDTH"] = sig_b.size();
1546 cell->setPort("\\A", sig_a);
1547 cell->setPort("\\B", sig_b);
1548 cell->setPort("\\Y", sig_y);
1549 return cell;
1550 }
1551
1552 RTLIL::Cell* RTLIL::Module::addLut(RTLIL::IdString name, RTLIL::SigSpec sig_i, RTLIL::SigSpec sig_o, RTLIL::Const lut)
1553 {
1554 RTLIL::Cell *cell = addCell(name, "$lut");
1555 cell->parameters["\\LUT"] = lut;
1556 cell->parameters["\\WIDTH"] = sig_i.size();
1557 cell->setPort("\\A", sig_i);
1558 cell->setPort("\\Y", sig_o);
1559 return cell;
1560 }
1561
1562 RTLIL::Cell* RTLIL::Module::addAssert(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en)
1563 {
1564 RTLIL::Cell *cell = addCell(name, "$assert");
1565 cell->setPort("\\A", sig_a);
1566 cell->setPort("\\EN", sig_en);
1567 return cell;
1568 }
1569
1570 RTLIL::Cell* RTLIL::Module::addSr(RTLIL::IdString name, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr, RTLIL::SigSpec sig_q, bool set_polarity, bool clr_polarity)
1571 {
1572 RTLIL::Cell *cell = addCell(name, "$sr");
1573 cell->parameters["\\SET_POLARITY"] = set_polarity;
1574 cell->parameters["\\CLR_POLARITY"] = clr_polarity;
1575 cell->parameters["\\WIDTH"] = sig_q.size();
1576 cell->setPort("\\SET", sig_set);
1577 cell->setPort("\\CLR", sig_clr);
1578 cell->setPort("\\Q", sig_q);
1579 return cell;
1580 }
1581
1582 RTLIL::Cell* RTLIL::Module::addDff(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity)
1583 {
1584 RTLIL::Cell *cell = addCell(name, "$dff");
1585 cell->parameters["\\CLK_POLARITY"] = clk_polarity;
1586 cell->parameters["\\WIDTH"] = sig_q.size();
1587 cell->setPort("\\CLK", sig_clk);
1588 cell->setPort("\\D", sig_d);
1589 cell->setPort("\\Q", sig_q);
1590 return cell;
1591 }
1592
1593 RTLIL::Cell* RTLIL::Module::addDffsr(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
1594 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity)
1595 {
1596 RTLIL::Cell *cell = addCell(name, "$dffsr");
1597 cell->parameters["\\CLK_POLARITY"] = clk_polarity;
1598 cell->parameters["\\SET_POLARITY"] = set_polarity;
1599 cell->parameters["\\CLR_POLARITY"] = clr_polarity;
1600 cell->parameters["\\WIDTH"] = sig_q.size();
1601 cell->setPort("\\CLK", sig_clk);
1602 cell->setPort("\\SET", sig_set);
1603 cell->setPort("\\CLR", sig_clr);
1604 cell->setPort("\\D", sig_d);
1605 cell->setPort("\\Q", sig_q);
1606 return cell;
1607 }
1608
1609 RTLIL::Cell* RTLIL::Module::addAdff(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_arst, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q,
1610 RTLIL::Const arst_value, bool clk_polarity, bool arst_polarity)
1611 {
1612 RTLIL::Cell *cell = addCell(name, "$adff");
1613 cell->parameters["\\CLK_POLARITY"] = clk_polarity;
1614 cell->parameters["\\ARST_POLARITY"] = arst_polarity;
1615 cell->parameters["\\ARST_VALUE"] = arst_value;
1616 cell->parameters["\\WIDTH"] = sig_q.size();
1617 cell->setPort("\\CLK", sig_clk);
1618 cell->setPort("\\ARST", sig_arst);
1619 cell->setPort("\\D", sig_d);
1620 cell->setPort("\\Q", sig_q);
1621 return cell;
1622 }
1623
1624 RTLIL::Cell* RTLIL::Module::addDlatch(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity)
1625 {
1626 RTLIL::Cell *cell = addCell(name, "$dlatch");
1627 cell->parameters["\\EN_POLARITY"] = en_polarity;
1628 cell->parameters["\\WIDTH"] = sig_q.size();
1629 cell->setPort("\\EN", sig_en);
1630 cell->setPort("\\D", sig_d);
1631 cell->setPort("\\Q", sig_q);
1632 return cell;
1633 }
1634
1635 RTLIL::Cell* RTLIL::Module::addDlatchsr(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
1636 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity, bool set_polarity, bool clr_polarity)
1637 {
1638 RTLIL::Cell *cell = addCell(name, "$dlatchsr");
1639 cell->parameters["\\EN_POLARITY"] = en_polarity;
1640 cell->parameters["\\SET_POLARITY"] = set_polarity;
1641 cell->parameters["\\CLR_POLARITY"] = clr_polarity;
1642 cell->parameters["\\WIDTH"] = sig_q.size();
1643 cell->setPort("\\EN", sig_en);
1644 cell->setPort("\\SET", sig_set);
1645 cell->setPort("\\CLR", sig_clr);
1646 cell->setPort("\\D", sig_d);
1647 cell->setPort("\\Q", sig_q);
1648 return cell;
1649 }
1650
1651 RTLIL::Cell* RTLIL::Module::addDffGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity)
1652 {
1653 RTLIL::Cell *cell = addCell(name, stringf("$_DFF_%c_", clk_polarity ? 'P' : 'N'));
1654 cell->setPort("\\C", sig_clk);
1655 cell->setPort("\\D", sig_d);
1656 cell->setPort("\\Q", sig_q);
1657 return cell;
1658 }
1659
1660 RTLIL::Cell* RTLIL::Module::addDffsrGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
1661 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity)
1662 {
1663 RTLIL::Cell *cell = addCell(name, stringf("$_DFFSR_%c%c%c_", clk_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N'));
1664 cell->setPort("\\C", sig_clk);
1665 cell->setPort("\\S", sig_set);
1666 cell->setPort("\\R", sig_clr);
1667 cell->setPort("\\D", sig_d);
1668 cell->setPort("\\Q", sig_q);
1669 return cell;
1670 }
1671
1672 RTLIL::Cell* RTLIL::Module::addAdffGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_arst, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q,
1673 bool arst_value, bool clk_polarity, bool arst_polarity)
1674 {
1675 RTLIL::Cell *cell = addCell(name, stringf("$_DFF_%c%c%c_", clk_polarity ? 'P' : 'N', arst_polarity ? 'P' : 'N', arst_value ? '1' : '0'));
1676 cell->setPort("\\C", sig_clk);
1677 cell->setPort("\\R", sig_arst);
1678 cell->setPort("\\D", sig_d);
1679 cell->setPort("\\Q", sig_q);
1680 return cell;
1681 }
1682
1683 RTLIL::Cell* RTLIL::Module::addDlatchGate(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity)
1684 {
1685 RTLIL::Cell *cell = addCell(name, stringf("$_DLATCH_%c_", en_polarity ? 'P' : 'N'));
1686 cell->setPort("\\E", sig_en);
1687 cell->setPort("\\D", sig_d);
1688 cell->setPort("\\Q", sig_q);
1689 return cell;
1690 }
1691
1692 RTLIL::Cell* RTLIL::Module::addDlatchsrGate(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
1693 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity, bool set_polarity, bool clr_polarity)
1694 {
1695 RTLIL::Cell *cell = addCell(name, stringf("$_DLATCHSR_%c%c%c_", en_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N'));
1696 cell->setPort("\\E", sig_en);
1697 cell->setPort("\\S", sig_set);
1698 cell->setPort("\\R", sig_clr);
1699 cell->setPort("\\D", sig_d);
1700 cell->setPort("\\Q", sig_q);
1701 return cell;
1702 }
1703
1704
1705 RTLIL::Wire::Wire()
1706 {
1707 module = nullptr;
1708 width = 1;
1709 start_offset = 0;
1710 port_id = 0;
1711 port_input = false;
1712 port_output = false;
1713 upto = false;
1714 }
1715
1716 RTLIL::Memory::Memory()
1717 {
1718 width = 1;
1719 size = 0;
1720 }
1721
1722 RTLIL::Cell::Cell() : module(nullptr)
1723 {
1724 }
1725
1726 bool RTLIL::Cell::hasPort(RTLIL::IdString portname) const
1727 {
1728 return connections_.count(portname) != 0;
1729 }
1730
1731 void RTLIL::Cell::unsetPort(RTLIL::IdString portname)
1732 {
1733 RTLIL::SigSpec signal;
1734 auto conn_it = connections_.find(portname);
1735
1736 if (conn_it != connections_.end())
1737 {
1738 for (auto mon : module->monitors)
1739 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
1740
1741 if (module->design)
1742 for (auto mon : module->design->monitors)
1743 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
1744
1745 connections_.erase(conn_it);
1746 }
1747 }
1748
1749 void RTLIL::Cell::setPort(RTLIL::IdString portname, RTLIL::SigSpec signal)
1750 {
1751 auto conn_it = connections_.find(portname);
1752
1753 if (conn_it == connections_.end()) {
1754 connections_[portname] = RTLIL::SigSpec();
1755 conn_it = connections_.find(portname);
1756 log_assert(conn_it != connections_.end());
1757 }
1758
1759 for (auto mon : module->monitors)
1760 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
1761
1762 if (module->design)
1763 for (auto mon : module->design->monitors)
1764 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
1765
1766 conn_it->second = signal;
1767 }
1768
1769 const RTLIL::SigSpec &RTLIL::Cell::getPort(RTLIL::IdString portname) const
1770 {
1771 return connections_.at(portname);
1772 }
1773
1774 const std::map<RTLIL::IdString, RTLIL::SigSpec> &RTLIL::Cell::connections() const
1775 {
1776 return connections_;
1777 }
1778
1779 bool RTLIL::Cell::hasParam(RTLIL::IdString paramname) const
1780 {
1781 return parameters.count(paramname);
1782 }
1783
1784 void RTLIL::Cell::unsetParam(RTLIL::IdString paramname)
1785 {
1786 parameters.erase(paramname);
1787 }
1788
1789 void RTLIL::Cell::setParam(RTLIL::IdString paramname, RTLIL::Const value)
1790 {
1791 parameters[paramname] = value;
1792 }
1793
1794 const RTLIL::Const &RTLIL::Cell::getParam(RTLIL::IdString paramname) const
1795 {
1796 return parameters.at(paramname);
1797 }
1798
1799 void RTLIL::Cell::check()
1800 {
1801 #ifndef NDEBUG
1802 InternalCellChecker checker(NULL, this);
1803 checker.check();
1804 #endif
1805 }
1806
1807 void RTLIL::Cell::fixup_parameters(bool set_a_signed, bool set_b_signed)
1808 {
1809 if (type.substr(0, 1) != "$" || type.substr(0, 2) == "$_" || type.substr(0, 8) == "$paramod" ||
1810 type.substr(0, 9) == "$verific$" || type.substr(0, 7) == "$array:" || type.substr(0, 8) == "$extern:")
1811 return;
1812
1813 if (type == "$mux" || type == "$pmux") {
1814 parameters["\\WIDTH"] = GetSize(connections_["\\Y"]);
1815 if (type == "$pmux")
1816 parameters["\\S_WIDTH"] = GetSize(connections_["\\S"]);
1817 check();
1818 return;
1819 }
1820
1821 if (type == "$lut") {
1822 parameters["\\WIDTH"] = GetSize(connections_["\\A"]);
1823 return;
1824 }
1825
1826 if (type == "$fa") {
1827 parameters["\\WIDTH"] = GetSize(connections_["\\Y"]);
1828 return;
1829 }
1830
1831 if (type == "$lcu") {
1832 parameters["\\WIDTH"] = GetSize(connections_["\\CO"]);
1833 return;
1834 }
1835
1836 bool signedness_ab = !type.in("$slice", "$concat", "$macc");
1837
1838 if (connections_.count("\\A")) {
1839 if (signedness_ab) {
1840 if (set_a_signed)
1841 parameters["\\A_SIGNED"] = true;
1842 else if (parameters.count("\\A_SIGNED") == 0)
1843 parameters["\\A_SIGNED"] = false;
1844 }
1845 parameters["\\A_WIDTH"] = GetSize(connections_["\\A"]);
1846 }
1847
1848 if (connections_.count("\\B")) {
1849 if (signedness_ab) {
1850 if (set_b_signed)
1851 parameters["\\B_SIGNED"] = true;
1852 else if (parameters.count("\\B_SIGNED") == 0)
1853 parameters["\\B_SIGNED"] = false;
1854 }
1855 parameters["\\B_WIDTH"] = GetSize(connections_["\\B"]);
1856 }
1857
1858 if (connections_.count("\\Y"))
1859 parameters["\\Y_WIDTH"] = GetSize(connections_["\\Y"]);
1860
1861 check();
1862 }
1863
1864 RTLIL::SigChunk::SigChunk()
1865 {
1866 wire = NULL;
1867 width = 0;
1868 offset = 0;
1869 }
1870
1871 RTLIL::SigChunk::SigChunk(const RTLIL::Const &value)
1872 {
1873 wire = NULL;
1874 data = value.bits;
1875 width = GetSize(data);
1876 offset = 0;
1877 }
1878
1879 RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire)
1880 {
1881 log_assert(wire != nullptr);
1882 this->wire = wire;
1883 this->width = wire->width;
1884 this->offset = 0;
1885 }
1886
1887 RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire, int offset, int width)
1888 {
1889 log_assert(wire != nullptr);
1890 this->wire = wire;
1891 this->width = width;
1892 this->offset = offset;
1893 }
1894
1895 RTLIL::SigChunk::SigChunk(const std::string &str)
1896 {
1897 wire = NULL;
1898 data = RTLIL::Const(str).bits;
1899 width = GetSize(data);
1900 offset = 0;
1901 }
1902
1903 RTLIL::SigChunk::SigChunk(int val, int width)
1904 {
1905 wire = NULL;
1906 data = RTLIL::Const(val, width).bits;
1907 this->width = GetSize(data);
1908 offset = 0;
1909 }
1910
1911 RTLIL::SigChunk::SigChunk(RTLIL::State bit, int width)
1912 {
1913 wire = NULL;
1914 data = RTLIL::Const(bit, width).bits;
1915 this->width = GetSize(data);
1916 offset = 0;
1917 }
1918
1919 RTLIL::SigChunk::SigChunk(RTLIL::SigBit bit)
1920 {
1921 wire = bit.wire;
1922 offset = 0;
1923 if (wire == NULL)
1924 data = RTLIL::Const(bit.data).bits;
1925 else
1926 offset = bit.offset;
1927 width = 1;
1928 }
1929
1930 RTLIL::SigChunk RTLIL::SigChunk::extract(int offset, int length) const
1931 {
1932 RTLIL::SigChunk ret;
1933 if (wire) {
1934 ret.wire = wire;
1935 ret.offset = this->offset + offset;
1936 ret.width = length;
1937 } else {
1938 for (int i = 0; i < length; i++)
1939 ret.data.push_back(data[offset+i]);
1940 ret.width = length;
1941 }
1942 return ret;
1943 }
1944
1945 bool RTLIL::SigChunk::operator <(const RTLIL::SigChunk &other) const
1946 {
1947 if (wire && other.wire)
1948 if (wire->name != other.wire->name)
1949 return wire->name < other.wire->name;
1950
1951 if (wire != other.wire)
1952 return wire < other.wire;
1953
1954 if (offset != other.offset)
1955 return offset < other.offset;
1956
1957 if (width != other.width)
1958 return width < other.width;
1959
1960 return data < other.data;
1961 }
1962
1963 bool RTLIL::SigChunk::operator ==(const RTLIL::SigChunk &other) const
1964 {
1965 return wire == other.wire && width == other.width && offset == other.offset && data == other.data;
1966 }
1967
1968 bool RTLIL::SigChunk::operator !=(const RTLIL::SigChunk &other) const
1969 {
1970 if (*this == other)
1971 return false;
1972 return true;
1973 }
1974
1975 RTLIL::SigSpec::SigSpec()
1976 {
1977 width_ = 0;
1978 hash_ = 0;
1979 }
1980
1981 RTLIL::SigSpec::SigSpec(const RTLIL::SigSpec &other)
1982 {
1983 *this = other;
1984 }
1985
1986 RTLIL::SigSpec::SigSpec(std::initializer_list<RTLIL::SigSpec> parts)
1987 {
1988 cover("kernel.rtlil.sigspec.init.list");
1989
1990 width_ = 0;
1991 hash_ = 0;
1992
1993 std::vector<RTLIL::SigSpec> parts_vec(parts.begin(), parts.end());
1994 for (auto it = parts_vec.rbegin(); it != parts_vec.rend(); it++)
1995 append(*it);
1996 }
1997
1998 const RTLIL::SigSpec &RTLIL::SigSpec::operator=(const RTLIL::SigSpec &other)
1999 {
2000 cover("kernel.rtlil.sigspec.assign");
2001
2002 width_ = other.width_;
2003 hash_ = other.hash_;
2004 chunks_ = other.chunks_;
2005 bits_.clear();
2006
2007 if (!other.bits_.empty())
2008 {
2009 RTLIL::SigChunk *last = NULL;
2010 int last_end_offset = 0;
2011
2012 for (auto &bit : other.bits_) {
2013 if (last && bit.wire == last->wire) {
2014 if (bit.wire == NULL) {
2015 last->data.push_back(bit.data);
2016 last->width++;
2017 continue;
2018 } else if (last_end_offset == bit.offset) {
2019 last_end_offset++;
2020 last->width++;
2021 continue;
2022 }
2023 }
2024 chunks_.push_back(bit);
2025 last = &chunks_.back();
2026 last_end_offset = bit.offset + 1;
2027 }
2028
2029 check();
2030 }
2031
2032 return *this;
2033 }
2034
2035 RTLIL::SigSpec::SigSpec(const RTLIL::Const &value)
2036 {
2037 cover("kernel.rtlil.sigspec.init.const");
2038
2039 chunks_.push_back(RTLIL::SigChunk(value));
2040 width_ = chunks_.back().width;
2041 hash_ = 0;
2042 check();
2043 }
2044
2045 RTLIL::SigSpec::SigSpec(const RTLIL::SigChunk &chunk)
2046 {
2047 cover("kernel.rtlil.sigspec.init.chunk");
2048
2049 chunks_.push_back(chunk);
2050 width_ = chunks_.back().width;
2051 hash_ = 0;
2052 check();
2053 }
2054
2055 RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire)
2056 {
2057 cover("kernel.rtlil.sigspec.init.wire");
2058
2059 chunks_.push_back(RTLIL::SigChunk(wire));
2060 width_ = chunks_.back().width;
2061 hash_ = 0;
2062 check();
2063 }
2064
2065 RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire, int offset, int width)
2066 {
2067 cover("kernel.rtlil.sigspec.init.wire_part");
2068
2069 chunks_.push_back(RTLIL::SigChunk(wire, offset, width));
2070 width_ = chunks_.back().width;
2071 hash_ = 0;
2072 check();
2073 }
2074
2075 RTLIL::SigSpec::SigSpec(const std::string &str)
2076 {
2077 cover("kernel.rtlil.sigspec.init.str");
2078
2079 chunks_.push_back(RTLIL::SigChunk(str));
2080 width_ = chunks_.back().width;
2081 hash_ = 0;
2082 check();
2083 }
2084
2085 RTLIL::SigSpec::SigSpec(int val, int width)
2086 {
2087 cover("kernel.rtlil.sigspec.init.int");
2088
2089 chunks_.push_back(RTLIL::SigChunk(val, width));
2090 width_ = width;
2091 hash_ = 0;
2092 check();
2093 }
2094
2095 RTLIL::SigSpec::SigSpec(RTLIL::State bit, int width)
2096 {
2097 cover("kernel.rtlil.sigspec.init.state");
2098
2099 chunks_.push_back(RTLIL::SigChunk(bit, width));
2100 width_ = width;
2101 hash_ = 0;
2102 check();
2103 }
2104
2105 RTLIL::SigSpec::SigSpec(RTLIL::SigBit bit, int width)
2106 {
2107 cover("kernel.rtlil.sigspec.init.bit");
2108
2109 if (bit.wire == NULL)
2110 chunks_.push_back(RTLIL::SigChunk(bit.data, width));
2111 else
2112 for (int i = 0; i < width; i++)
2113 chunks_.push_back(bit);
2114 width_ = width;
2115 hash_ = 0;
2116 check();
2117 }
2118
2119 RTLIL::SigSpec::SigSpec(std::vector<RTLIL::SigChunk> chunks)
2120 {
2121 cover("kernel.rtlil.sigspec.init.stdvec_chunks");
2122
2123 width_ = 0;
2124 hash_ = 0;
2125 for (auto &c : chunks)
2126 append(c);
2127 check();
2128 }
2129
2130 RTLIL::SigSpec::SigSpec(std::vector<RTLIL::SigBit> bits)
2131 {
2132 cover("kernel.rtlil.sigspec.init.stdvec_bits");
2133
2134 width_ = 0;
2135 hash_ = 0;
2136 for (auto &bit : bits)
2137 append_bit(bit);
2138 check();
2139 }
2140
2141 RTLIL::SigSpec::SigSpec(std::set<RTLIL::SigBit> bits)
2142 {
2143 cover("kernel.rtlil.sigspec.init.stdset_bits");
2144
2145 width_ = 0;
2146 hash_ = 0;
2147 for (auto &bit : bits)
2148 append_bit(bit);
2149 check();
2150 }
2151
2152 void RTLIL::SigSpec::pack() const
2153 {
2154 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
2155
2156 if (that->bits_.empty())
2157 return;
2158
2159 cover("kernel.rtlil.sigspec.convert.pack");
2160 log_assert(that->chunks_.empty());
2161
2162 std::vector<RTLIL::SigBit> old_bits;
2163 old_bits.swap(that->bits_);
2164
2165 RTLIL::SigChunk *last = NULL;
2166 int last_end_offset = 0;
2167
2168 for (auto &bit : old_bits) {
2169 if (last && bit.wire == last->wire) {
2170 if (bit.wire == NULL) {
2171 last->data.push_back(bit.data);
2172 last->width++;
2173 continue;
2174 } else if (last_end_offset == bit.offset) {
2175 last_end_offset++;
2176 last->width++;
2177 continue;
2178 }
2179 }
2180 that->chunks_.push_back(bit);
2181 last = &that->chunks_.back();
2182 last_end_offset = bit.offset + 1;
2183 }
2184
2185 check();
2186 }
2187
2188 void RTLIL::SigSpec::unpack() const
2189 {
2190 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
2191
2192 if (that->chunks_.empty())
2193 return;
2194
2195 cover("kernel.rtlil.sigspec.convert.unpack");
2196 log_assert(that->bits_.empty());
2197
2198 that->bits_.reserve(that->width_);
2199 for (auto &c : that->chunks_)
2200 for (int i = 0; i < c.width; i++)
2201 that->bits_.push_back(RTLIL::SigBit(c, i));
2202
2203 that->chunks_.clear();
2204 that->hash_ = 0;
2205 }
2206
2207 #define DJB2(_hash, _value) do { (_hash) = (((_hash) << 5) + (_hash)) + (_value); } while (0)
2208
2209 void RTLIL::SigSpec::hash() const
2210 {
2211 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
2212
2213 if (that->hash_ != 0)
2214 return;
2215
2216 cover("kernel.rtlil.sigspec.hash");
2217 that->pack();
2218
2219 that->hash_ = 5381;
2220 for (auto &c : that->chunks_)
2221 if (c.wire == NULL) {
2222 for (auto &v : c.data)
2223 DJB2(that->hash_, v);
2224 } else {
2225 DJB2(that->hash_, c.wire->name.index_);
2226 DJB2(that->hash_, c.offset);
2227 DJB2(that->hash_, c.width);
2228 }
2229
2230 if (that->hash_ == 0)
2231 that->hash_ = 1;
2232 }
2233
2234 void RTLIL::SigSpec::sort()
2235 {
2236 unpack();
2237 cover("kernel.rtlil.sigspec.sort");
2238 std::sort(bits_.begin(), bits_.end());
2239 }
2240
2241 void RTLIL::SigSpec::sort_and_unify()
2242 {
2243 cover("kernel.rtlil.sigspec.sort_and_unify");
2244 *this = this->to_sigbit_set();
2245 }
2246
2247 void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with)
2248 {
2249 replace(pattern, with, this);
2250 }
2251
2252 void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with, RTLIL::SigSpec *other) const
2253 {
2254 log_assert(pattern.width_ == with.width_);
2255
2256 pattern.unpack();
2257 with.unpack();
2258
2259 std::map<RTLIL::SigBit, RTLIL::SigBit> rules;
2260
2261 for (int i = 0; i < GetSize(pattern.bits_); i++)
2262 if (pattern.bits_[i].wire != NULL)
2263 rules[pattern.bits_[i]] = with.bits_[i];
2264
2265 replace(rules, other);
2266 }
2267
2268 void RTLIL::SigSpec::replace(const std::map<RTLIL::SigBit, RTLIL::SigBit> &rules)
2269 {
2270 replace(rules, this);
2271 }
2272
2273 void RTLIL::SigSpec::replace(const std::map<RTLIL::SigBit, RTLIL::SigBit> &rules, RTLIL::SigSpec *other) const
2274 {
2275 cover("kernel.rtlil.sigspec.replace");
2276
2277 log_assert(other != NULL);
2278 log_assert(width_ == other->width_);
2279
2280 unpack();
2281 other->unpack();
2282
2283 for (int i = 0; i < GetSize(bits_); i++) {
2284 auto it = rules.find(bits_[i]);
2285 if (it != rules.end())
2286 other->bits_[i] = it->second;
2287 }
2288
2289 other->check();
2290 }
2291
2292 void RTLIL::SigSpec::remove(const RTLIL::SigSpec &pattern)
2293 {
2294 remove2(pattern, NULL);
2295 }
2296
2297 void RTLIL::SigSpec::remove(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other) const
2298 {
2299 RTLIL::SigSpec tmp = *this;
2300 tmp.remove2(pattern, other);
2301 }
2302
2303 void RTLIL::SigSpec::remove2(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other)
2304 {
2305 std::set<RTLIL::SigBit> pattern_bits = pattern.to_sigbit_set();
2306 remove2(pattern_bits, other);
2307 }
2308
2309 void RTLIL::SigSpec::remove(const std::set<RTLIL::SigBit> &pattern)
2310 {
2311 remove2(pattern, NULL);
2312 }
2313
2314 void RTLIL::SigSpec::remove(const std::set<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other) const
2315 {
2316 RTLIL::SigSpec tmp = *this;
2317 tmp.remove2(pattern, other);
2318 }
2319
2320 void RTLIL::SigSpec::remove2(const std::set<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other)
2321 {
2322 if (other)
2323 cover("kernel.rtlil.sigspec.remove_other");
2324 else
2325 cover("kernel.rtlil.sigspec.remove");
2326
2327 unpack();
2328
2329 if (other != NULL) {
2330 log_assert(width_ == other->width_);
2331 other->unpack();
2332 }
2333
2334 std::vector<RTLIL::SigBit> new_bits, new_other_bits;
2335
2336 new_bits.resize(GetSize(bits_));
2337 if (other != NULL)
2338 new_other_bits.resize(GetSize(bits_));
2339
2340 int k = 0;
2341 for (int i = 0; i < GetSize(bits_); i++) {
2342 if (bits_[i].wire != NULL && pattern.count(bits_[i]))
2343 continue;
2344 if (other != NULL)
2345 new_other_bits[k] = other->bits_[i];
2346 new_bits[k++] = bits_[i];
2347 }
2348
2349 new_bits.resize(k);
2350 if (other != NULL)
2351 new_other_bits.resize(k);
2352
2353 bits_.swap(new_bits);
2354 width_ = GetSize(bits_);
2355
2356 if (other != NULL) {
2357 other->bits_.swap(new_other_bits);
2358 other->width_ = GetSize(other->bits_);
2359 }
2360
2361 check();
2362 }
2363
2364 RTLIL::SigSpec RTLIL::SigSpec::extract(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec *other) const
2365 {
2366 std::set<RTLIL::SigBit> pattern_bits = pattern.to_sigbit_set();
2367 return extract(pattern_bits, other);
2368 }
2369
2370 RTLIL::SigSpec RTLIL::SigSpec::extract(const std::set<RTLIL::SigBit> &pattern, const RTLIL::SigSpec *other) const
2371 {
2372 if (other)
2373 cover("kernel.rtlil.sigspec.extract_other");
2374 else
2375 cover("kernel.rtlil.sigspec.extract");
2376
2377 log_assert(other == NULL || width_ == other->width_);
2378
2379 std::vector<RTLIL::SigBit> bits_match = to_sigbit_vector();
2380 RTLIL::SigSpec ret;
2381
2382 if (other) {
2383 std::vector<RTLIL::SigBit> bits_other = other->to_sigbit_vector();
2384 for (int i = 0; i < width_; i++)
2385 if (bits_match[i].wire && pattern.count(bits_match[i]))
2386 ret.append_bit(bits_other[i]);
2387 } else {
2388 for (int i = 0; i < width_; i++)
2389 if (bits_match[i].wire && pattern.count(bits_match[i]))
2390 ret.append_bit(bits_match[i]);
2391 }
2392
2393 ret.check();
2394 return ret;
2395 }
2396
2397 void RTLIL::SigSpec::replace(int offset, const RTLIL::SigSpec &with)
2398 {
2399 cover("kernel.rtlil.sigspec.replace_pos");
2400
2401 unpack();
2402 with.unpack();
2403
2404 log_assert(offset >= 0);
2405 log_assert(with.width_ >= 0);
2406 log_assert(offset+with.width_ <= width_);
2407
2408 for (int i = 0; i < with.width_; i++)
2409 bits_.at(offset + i) = with.bits_.at(i);
2410
2411 check();
2412 }
2413
2414 void RTLIL::SigSpec::remove_const()
2415 {
2416 if (packed())
2417 {
2418 cover("kernel.rtlil.sigspec.remove_const.packed");
2419
2420 std::vector<RTLIL::SigChunk> new_chunks;
2421 new_chunks.reserve(GetSize(chunks_));
2422
2423 width_ = 0;
2424 for (auto &chunk : chunks_)
2425 if (chunk.wire != NULL) {
2426 new_chunks.push_back(chunk);
2427 width_ += chunk.width;
2428 }
2429
2430 chunks_.swap(new_chunks);
2431 }
2432 else
2433 {
2434 cover("kernel.rtlil.sigspec.remove_const.unpacked");
2435
2436 std::vector<RTLIL::SigBit> new_bits;
2437 new_bits.reserve(width_);
2438
2439 for (auto &bit : bits_)
2440 if (bit.wire != NULL)
2441 new_bits.push_back(bit);
2442
2443 bits_.swap(new_bits);
2444 width_ = bits_.size();
2445 }
2446
2447 check();
2448 }
2449
2450 void RTLIL::SigSpec::remove(int offset, int length)
2451 {
2452 cover("kernel.rtlil.sigspec.remove_pos");
2453
2454 unpack();
2455
2456 log_assert(offset >= 0);
2457 log_assert(length >= 0);
2458 log_assert(offset + length <= width_);
2459
2460 bits_.erase(bits_.begin() + offset, bits_.begin() + offset + length);
2461 width_ = bits_.size();
2462
2463 check();
2464 }
2465
2466 RTLIL::SigSpec RTLIL::SigSpec::extract(int offset, int length) const
2467 {
2468 unpack();
2469 cover("kernel.rtlil.sigspec.extract_pos");
2470 return std::vector<RTLIL::SigBit>(bits_.begin() + offset, bits_.begin() + offset + length);
2471 }
2472
2473 void RTLIL::SigSpec::append(const RTLIL::SigSpec &signal)
2474 {
2475 if (signal.width_ == 0)
2476 return;
2477
2478 if (width_ == 0) {
2479 *this = signal;
2480 return;
2481 }
2482
2483 cover("kernel.rtlil.sigspec.append");
2484
2485 if (packed() != signal.packed()) {
2486 pack();
2487 signal.pack();
2488 }
2489
2490 if (packed())
2491 for (auto &other_c : signal.chunks_)
2492 {
2493 auto &my_last_c = chunks_.back();
2494 if (my_last_c.wire == NULL && other_c.wire == NULL) {
2495 auto &this_data = my_last_c.data;
2496 auto &other_data = other_c.data;
2497 this_data.insert(this_data.end(), other_data.begin(), other_data.end());
2498 my_last_c.width += other_c.width;
2499 } else
2500 if (my_last_c.wire == other_c.wire && my_last_c.offset + my_last_c.width == other_c.offset) {
2501 my_last_c.width += other_c.width;
2502 } else
2503 chunks_.push_back(other_c);
2504 }
2505 else
2506 bits_.insert(bits_.end(), signal.bits_.begin(), signal.bits_.end());
2507
2508 width_ += signal.width_;
2509 check();
2510 }
2511
2512 void RTLIL::SigSpec::append_bit(const RTLIL::SigBit &bit)
2513 {
2514 if (packed())
2515 {
2516 cover("kernel.rtlil.sigspec.append_bit.packed");
2517
2518 if (chunks_.size() == 0)
2519 chunks_.push_back(bit);
2520 else
2521 if (bit.wire == NULL)
2522 if (chunks_.back().wire == NULL) {
2523 chunks_.back().data.push_back(bit.data);
2524 chunks_.back().width++;
2525 } else
2526 chunks_.push_back(bit);
2527 else
2528 if (chunks_.back().wire == bit.wire && chunks_.back().offset + chunks_.back().width == bit.offset)
2529 chunks_.back().width++;
2530 else
2531 chunks_.push_back(bit);
2532 }
2533 else
2534 {
2535 cover("kernel.rtlil.sigspec.append_bit.unpacked");
2536 bits_.push_back(bit);
2537 }
2538
2539 width_++;
2540 check();
2541 }
2542
2543 void RTLIL::SigSpec::extend(int width, bool is_signed)
2544 {
2545 cover("kernel.rtlil.sigspec.extend");
2546
2547 pack();
2548
2549 if (width_ > width)
2550 remove(width, width_ - width);
2551
2552 if (width_ < width) {
2553 RTLIL::SigSpec padding = width_ > 0 ? extract(width_ - 1, 1) : RTLIL::SigSpec(RTLIL::State::S0);
2554 if (!is_signed && padding != RTLIL::SigSpec(RTLIL::State::Sx) && padding != RTLIL::SigSpec(RTLIL::State::Sz) &&
2555 padding != RTLIL::SigSpec(RTLIL::State::Sa) && padding != RTLIL::SigSpec(RTLIL::State::Sm))
2556 padding = RTLIL::SigSpec(RTLIL::State::S0);
2557 while (width_ < width)
2558 append(padding);
2559 }
2560 }
2561
2562 void RTLIL::SigSpec::extend_u0(int width, bool is_signed)
2563 {
2564 cover("kernel.rtlil.sigspec.extend_u0");
2565
2566 pack();
2567
2568 if (width_ > width)
2569 remove(width, width_ - width);
2570
2571 if (width_ < width) {
2572 RTLIL::SigSpec padding = width_ > 0 ? extract(width_ - 1, 1) : RTLIL::SigSpec(RTLIL::State::S0);
2573 if (!is_signed)
2574 padding = RTLIL::SigSpec(RTLIL::State::S0);
2575 while (width_ < width)
2576 append(padding);
2577 }
2578
2579 }
2580
2581 RTLIL::SigSpec RTLIL::SigSpec::repeat(int num) const
2582 {
2583 cover("kernel.rtlil.sigspec.repeat");
2584
2585 RTLIL::SigSpec sig;
2586 for (int i = 0; i < num; i++)
2587 sig.append(*this);
2588 return sig;
2589 }
2590
2591 #ifndef NDEBUG
2592 void RTLIL::SigSpec::check() const
2593 {
2594 if (width_ > 64)
2595 {
2596 cover("kernel.rtlil.sigspec.check.skip");
2597 }
2598 else if (packed())
2599 {
2600 cover("kernel.rtlil.sigspec.check.packed");
2601
2602 int w = 0;
2603 for (size_t i = 0; i < chunks_.size(); i++) {
2604 const RTLIL::SigChunk chunk = chunks_[i];
2605 if (chunk.wire == NULL) {
2606 if (i > 0)
2607 log_assert(chunks_[i-1].wire != NULL);
2608 log_assert(chunk.offset == 0);
2609 log_assert(chunk.data.size() == (size_t)chunk.width);
2610 } else {
2611 if (i > 0 && chunks_[i-1].wire == chunk.wire)
2612 log_assert(chunk.offset != chunks_[i-1].offset + chunks_[i-1].width);
2613 log_assert(chunk.offset >= 0);
2614 log_assert(chunk.width >= 0);
2615 log_assert(chunk.offset + chunk.width <= chunk.wire->width);
2616 log_assert(chunk.data.size() == 0);
2617 }
2618 w += chunk.width;
2619 }
2620 log_assert(w == width_);
2621 log_assert(bits_.empty());
2622 }
2623 else
2624 {
2625 cover("kernel.rtlil.sigspec.check.unpacked");
2626
2627 log_assert(width_ == GetSize(bits_));
2628 log_assert(chunks_.empty());
2629 }
2630 }
2631 #endif
2632
2633 bool RTLIL::SigSpec::operator <(const RTLIL::SigSpec &other) const
2634 {
2635 cover("kernel.rtlil.sigspec.comp_lt");
2636
2637 if (this == &other)
2638 return false;
2639
2640 if (width_ != other.width_)
2641 return width_ < other.width_;
2642
2643 pack();
2644 other.pack();
2645
2646 if (chunks_.size() != other.chunks_.size())
2647 return chunks_.size() < other.chunks_.size();
2648
2649 hash();
2650 other.hash();
2651
2652 if (hash_ != other.hash_)
2653 return hash_ < other.hash_;
2654
2655 for (size_t i = 0; i < chunks_.size(); i++)
2656 if (chunks_[i] != other.chunks_[i]) {
2657 cover("kernel.rtlil.sigspec.comp_lt.hash_collision");
2658 return chunks_[i] < other.chunks_[i];
2659 }
2660
2661 cover("kernel.rtlil.sigspec.comp_lt.equal");
2662 return false;
2663 }
2664
2665 bool RTLIL::SigSpec::operator ==(const RTLIL::SigSpec &other) const
2666 {
2667 cover("kernel.rtlil.sigspec.comp_eq");
2668
2669 if (this == &other)
2670 return true;
2671
2672 if (width_ != other.width_)
2673 return false;
2674
2675 pack();
2676 other.pack();
2677
2678 if (chunks_.size() != chunks_.size())
2679 return false;
2680
2681 hash();
2682 other.hash();
2683
2684 if (hash_ != other.hash_)
2685 return false;
2686
2687 for (size_t i = 0; i < chunks_.size(); i++)
2688 if (chunks_[i] != other.chunks_[i]) {
2689 cover("kernel.rtlil.sigspec.comp_eq.hash_collision");
2690 return false;
2691 }
2692
2693 cover("kernel.rtlil.sigspec.comp_eq.equal");
2694 return true;
2695 }
2696
2697 bool RTLIL::SigSpec::is_wire() const
2698 {
2699 cover("kernel.rtlil.sigspec.is_wire");
2700
2701 pack();
2702 return GetSize(chunks_) == 1 && chunks_[0].wire && chunks_[0].wire->width == width_;
2703 }
2704
2705 bool RTLIL::SigSpec::is_chunk() const
2706 {
2707 cover("kernel.rtlil.sigspec.is_chunk");
2708
2709 pack();
2710 return GetSize(chunks_) == 1;
2711 }
2712
2713 bool RTLIL::SigSpec::is_fully_const() const
2714 {
2715 cover("kernel.rtlil.sigspec.is_fully_const");
2716
2717 pack();
2718 for (auto it = chunks_.begin(); it != chunks_.end(); it++)
2719 if (it->width > 0 && it->wire != NULL)
2720 return false;
2721 return true;
2722 }
2723
2724 bool RTLIL::SigSpec::is_fully_def() const
2725 {
2726 cover("kernel.rtlil.sigspec.is_fully_def");
2727
2728 pack();
2729 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
2730 if (it->width > 0 && it->wire != NULL)
2731 return false;
2732 for (size_t i = 0; i < it->data.size(); i++)
2733 if (it->data[i] != RTLIL::State::S0 && it->data[i] != RTLIL::State::S1)
2734 return false;
2735 }
2736 return true;
2737 }
2738
2739 bool RTLIL::SigSpec::is_fully_undef() const
2740 {
2741 cover("kernel.rtlil.sigspec.is_fully_undef");
2742
2743 pack();
2744 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
2745 if (it->width > 0 && it->wire != NULL)
2746 return false;
2747 for (size_t i = 0; i < it->data.size(); i++)
2748 if (it->data[i] != RTLIL::State::Sx && it->data[i] != RTLIL::State::Sz)
2749 return false;
2750 }
2751 return true;
2752 }
2753
2754 bool RTLIL::SigSpec::has_marked_bits() const
2755 {
2756 cover("kernel.rtlil.sigspec.has_marked_bits");
2757
2758 pack();
2759 for (auto it = chunks_.begin(); it != chunks_.end(); it++)
2760 if (it->width > 0 && it->wire == NULL) {
2761 for (size_t i = 0; i < it->data.size(); i++)
2762 if (it->data[i] == RTLIL::State::Sm)
2763 return true;
2764 }
2765 return false;
2766 }
2767
2768 bool RTLIL::SigSpec::as_bool() const
2769 {
2770 cover("kernel.rtlil.sigspec.as_bool");
2771
2772 pack();
2773 log_assert(is_fully_const() && GetSize(chunks_) <= 1);
2774 if (width_)
2775 return RTLIL::Const(chunks_[0].data).as_bool();
2776 return false;
2777 }
2778
2779 int RTLIL::SigSpec::as_int(bool is_signed) const
2780 {
2781 cover("kernel.rtlil.sigspec.as_int");
2782
2783 pack();
2784 log_assert(is_fully_const() && GetSize(chunks_) <= 1);
2785 if (width_)
2786 return RTLIL::Const(chunks_[0].data).as_int(is_signed);
2787 return 0;
2788 }
2789
2790 std::string RTLIL::SigSpec::as_string() const
2791 {
2792 cover("kernel.rtlil.sigspec.as_string");
2793
2794 pack();
2795 std::string str;
2796 for (size_t i = chunks_.size(); i > 0; i--) {
2797 const RTLIL::SigChunk &chunk = chunks_[i-1];
2798 if (chunk.wire != NULL)
2799 for (int j = 0; j < chunk.width; j++)
2800 str += "?";
2801 else
2802 str += RTLIL::Const(chunk.data).as_string();
2803 }
2804 return str;
2805 }
2806
2807 RTLIL::Const RTLIL::SigSpec::as_const() const
2808 {
2809 cover("kernel.rtlil.sigspec.as_const");
2810
2811 pack();
2812 log_assert(is_fully_const() && GetSize(chunks_) <= 1);
2813 if (width_)
2814 return chunks_[0].data;
2815 return RTLIL::Const();
2816 }
2817
2818 RTLIL::Wire *RTLIL::SigSpec::as_wire() const
2819 {
2820 cover("kernel.rtlil.sigspec.as_wire");
2821
2822 pack();
2823 log_assert(is_wire());
2824 return chunks_[0].wire;
2825 }
2826
2827 RTLIL::SigChunk RTLIL::SigSpec::as_chunk() const
2828 {
2829 cover("kernel.rtlil.sigspec.as_chunk");
2830
2831 pack();
2832 log_assert(is_chunk());
2833 return chunks_[0];
2834 }
2835
2836 bool RTLIL::SigSpec::match(std::string pattern) const
2837 {
2838 cover("kernel.rtlil.sigspec.match");
2839
2840 pack();
2841 std::string str = as_string();
2842 log_assert(pattern.size() == str.size());
2843
2844 for (size_t i = 0; i < pattern.size(); i++) {
2845 if (pattern[i] == ' ')
2846 continue;
2847 if (pattern[i] == '*') {
2848 if (str[i] != 'z' && str[i] != 'x')
2849 return false;
2850 continue;
2851 }
2852 if (pattern[i] != str[i])
2853 return false;
2854 }
2855
2856 return true;
2857 }
2858
2859 std::set<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_set() const
2860 {
2861 cover("kernel.rtlil.sigspec.to_sigbit_set");
2862
2863 pack();
2864 std::set<RTLIL::SigBit> sigbits;
2865 for (auto &c : chunks_)
2866 for (int i = 0; i < c.width; i++)
2867 sigbits.insert(RTLIL::SigBit(c, i));
2868 return sigbits;
2869 }
2870
2871 std::vector<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_vector() const
2872 {
2873 cover("kernel.rtlil.sigspec.to_sigbit_vector");
2874
2875 unpack();
2876 return bits_;
2877 }
2878
2879 std::map<RTLIL::SigBit, RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_map(const RTLIL::SigSpec &other) const
2880 {
2881 cover("kernel.rtlil.sigspec.to_sigbit_map");
2882
2883 unpack();
2884 other.unpack();
2885
2886 log_assert(width_ == other.width_);
2887
2888 std::map<RTLIL::SigBit, RTLIL::SigBit> new_map;
2889 for (int i = 0; i < width_; i++)
2890 new_map[bits_[i]] = other.bits_[i];
2891
2892 return new_map;
2893 }
2894
2895 RTLIL::SigBit RTLIL::SigSpec::to_single_sigbit() const
2896 {
2897 cover("kernel.rtlil.sigspec.to_single_sigbit");
2898
2899 pack();
2900 log_assert(width_ == 1);
2901 for (auto &c : chunks_)
2902 if (c.width)
2903 return RTLIL::SigBit(c);
2904 log_abort();
2905 }
2906
2907 static void sigspec_parse_split(std::vector<std::string> &tokens, const std::string &text, char sep)
2908 {
2909 size_t start = 0, end = 0;
2910 while ((end = text.find(sep, start)) != std::string::npos) {
2911 tokens.push_back(text.substr(start, end - start));
2912 start = end + 1;
2913 }
2914 tokens.push_back(text.substr(start));
2915 }
2916
2917 static int sigspec_parse_get_dummy_line_num()
2918 {
2919 return 0;
2920 }
2921
2922 bool RTLIL::SigSpec::parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str)
2923 {
2924 cover("kernel.rtlil.sigspec.parse");
2925
2926 std::vector<std::string> tokens;
2927 sigspec_parse_split(tokens, str, ',');
2928
2929 sig = RTLIL::SigSpec();
2930 for (int tokidx = int(tokens.size())-1; tokidx >= 0; tokidx--)
2931 {
2932 std::string netname = tokens[tokidx];
2933 std::string indices;
2934
2935 if (netname.size() == 0)
2936 continue;
2937
2938 if ('0' <= netname[0] && netname[0] <= '9') {
2939 cover("kernel.rtlil.sigspec.parse.const");
2940 AST::get_line_num = sigspec_parse_get_dummy_line_num;
2941 AST::AstNode *ast = VERILOG_FRONTEND::const2ast(netname);
2942 if (ast == NULL)
2943 return false;
2944 sig.append(RTLIL::Const(ast->bits));
2945 delete ast;
2946 continue;
2947 }
2948
2949 if (module == NULL)
2950 return false;
2951
2952 cover("kernel.rtlil.sigspec.parse.net");
2953
2954 if (netname[0] != '$' && netname[0] != '\\')
2955 netname = "\\" + netname;
2956
2957 if (module->wires_.count(netname) == 0) {
2958 size_t indices_pos = netname.size()-1;
2959 if (indices_pos > 2 && netname[indices_pos] == ']')
2960 {
2961 indices_pos--;
2962 while (indices_pos > 0 && ('0' <= netname[indices_pos] && netname[indices_pos] <= '9')) indices_pos--;
2963 if (indices_pos > 0 && netname[indices_pos] == ':') {
2964 indices_pos--;
2965 while (indices_pos > 0 && ('0' <= netname[indices_pos] && netname[indices_pos] <= '9')) indices_pos--;
2966 }
2967 if (indices_pos > 0 && netname[indices_pos] == '[') {
2968 indices = netname.substr(indices_pos);
2969 netname = netname.substr(0, indices_pos);
2970 }
2971 }
2972 }
2973
2974 if (module->wires_.count(netname) == 0)
2975 return false;
2976
2977 RTLIL::Wire *wire = module->wires_.at(netname);
2978 if (!indices.empty()) {
2979 std::vector<std::string> index_tokens;
2980 sigspec_parse_split(index_tokens, indices.substr(1, indices.size()-2), ':');
2981 if (index_tokens.size() == 1) {
2982 cover("kernel.rtlil.sigspec.parse.bit_sel");
2983 int a = atoi(index_tokens.at(0).c_str());
2984 if (a < 0 || a >= wire->width)
2985 return false;
2986 sig.append(RTLIL::SigSpec(wire, a));
2987 } else {
2988 cover("kernel.rtlil.sigspec.parse.part_sel");
2989 int a = atoi(index_tokens.at(0).c_str());
2990 int b = atoi(index_tokens.at(1).c_str());
2991 if (a > b) {
2992 int tmp = a;
2993 a = b, b = tmp;
2994 }
2995 if (a < 0 || a >= wire->width)
2996 return false;
2997 if (b < 0 || b >= wire->width)
2998 return false;
2999 sig.append(RTLIL::SigSpec(wire, a, b-a+1));
3000 }
3001 } else
3002 sig.append(wire);
3003 }
3004
3005 return true;
3006 }
3007
3008 bool RTLIL::SigSpec::parse_sel(RTLIL::SigSpec &sig, RTLIL::Design *design, RTLIL::Module *module, std::string str)
3009 {
3010 if (str.empty() || str[0] != '@')
3011 return parse(sig, module, str);
3012
3013 cover("kernel.rtlil.sigspec.parse.sel");
3014
3015 str = RTLIL::escape_id(str.substr(1));
3016 if (design->selection_vars.count(str) == 0)
3017 return false;
3018
3019 sig = RTLIL::SigSpec();
3020 RTLIL::Selection &sel = design->selection_vars.at(str);
3021 for (auto &it : module->wires_)
3022 if (sel.selected_member(module->name, it.first))
3023 sig.append(it.second);
3024
3025 return true;
3026 }
3027
3028 bool RTLIL::SigSpec::parse_rhs(const RTLIL::SigSpec &lhs, RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str)
3029 {
3030 if (str == "0") {
3031 cover("kernel.rtlil.sigspec.parse.rhs_zeros");
3032 sig = RTLIL::SigSpec(RTLIL::State::S0, lhs.width_);
3033 return true;
3034 }
3035
3036 if (str == "~0") {
3037 cover("kernel.rtlil.sigspec.parse.rhs_ones");
3038 sig = RTLIL::SigSpec(RTLIL::State::S1, lhs.width_);
3039 return true;
3040 }
3041
3042 if (lhs.chunks_.size() == 1) {
3043 char *p = (char*)str.c_str(), *endptr;
3044 long long int val = strtoll(p, &endptr, 10);
3045 if (endptr && endptr != p && *endptr == 0) {
3046 sig = RTLIL::SigSpec(val, lhs.width_);
3047 cover("kernel.rtlil.sigspec.parse.rhs_dec");
3048 return true;
3049 }
3050 }
3051
3052 return parse(sig, module, str);
3053 }
3054
3055 RTLIL::CaseRule::~CaseRule()
3056 {
3057 for (auto it = switches.begin(); it != switches.end(); it++)
3058 delete *it;
3059 }
3060
3061 RTLIL::CaseRule *RTLIL::CaseRule::clone() const
3062 {
3063 RTLIL::CaseRule *new_caserule = new RTLIL::CaseRule;
3064 new_caserule->compare = compare;
3065 new_caserule->actions = actions;
3066 for (auto &it : switches)
3067 new_caserule->switches.push_back(it->clone());
3068 return new_caserule;
3069 }
3070
3071 RTLIL::SwitchRule::~SwitchRule()
3072 {
3073 for (auto it = cases.begin(); it != cases.end(); it++)
3074 delete *it;
3075 }
3076
3077 RTLIL::SwitchRule *RTLIL::SwitchRule::clone() const
3078 {
3079 RTLIL::SwitchRule *new_switchrule = new RTLIL::SwitchRule;
3080 new_switchrule->signal = signal;
3081 new_switchrule->attributes = attributes;
3082 for (auto &it : cases)
3083 new_switchrule->cases.push_back(it->clone());
3084 return new_switchrule;
3085
3086 }
3087
3088 RTLIL::SyncRule *RTLIL::SyncRule::clone() const
3089 {
3090 RTLIL::SyncRule *new_syncrule = new RTLIL::SyncRule;
3091 new_syncrule->type = type;
3092 new_syncrule->signal = signal;
3093 new_syncrule->actions = actions;
3094 return new_syncrule;
3095 }
3096
3097 RTLIL::Process::~Process()
3098 {
3099 for (auto it = syncs.begin(); it != syncs.end(); it++)
3100 delete *it;
3101 }
3102
3103 RTLIL::Process *RTLIL::Process::clone() const
3104 {
3105 RTLIL::Process *new_proc = new RTLIL::Process;
3106
3107 new_proc->name = name;
3108 new_proc->attributes = attributes;
3109
3110 RTLIL::CaseRule *rc_ptr = root_case.clone();
3111 new_proc->root_case = *rc_ptr;
3112 rc_ptr->switches.clear();
3113 delete rc_ptr;
3114
3115 for (auto &it : syncs)
3116 new_proc->syncs.push_back(it->clone());
3117
3118 return new_proc;
3119 }
3120
3121 YOSYS_NAMESPACE_END
3122