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Added wire->upto flag for signals such as "wire [0:7] x;"
[yosys.git] / kernel / rtlil.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 #include "kernel/compatibility.h"
21 #include "kernel/rtlil.h"
22 #include "kernel/log.h"
23 #include "frontends/verilog/verilog_frontend.h"
24 #include "backends/ilang/ilang_backend.h"
25
26 #include <string.h>
27 #include <algorithm>
28
29 int RTLIL::autoidx = 1;
30
31 RTLIL::Const::Const()
32 {
33 flags = RTLIL::CONST_FLAG_NONE;
34 }
35
36 RTLIL::Const::Const(std::string str)
37 {
38 flags = RTLIL::CONST_FLAG_STRING;
39 for (int i = str.size()-1; i >= 0; i--) {
40 unsigned char ch = str[i];
41 for (int j = 0; j < 8; j++) {
42 bits.push_back((ch & 1) != 0 ? RTLIL::S1 : RTLIL::S0);
43 ch = ch >> 1;
44 }
45 }
46 }
47
48 RTLIL::Const::Const(int val, int width)
49 {
50 flags = RTLIL::CONST_FLAG_NONE;
51 for (int i = 0; i < width; i++) {
52 bits.push_back((val & 1) != 0 ? RTLIL::S1 : RTLIL::S0);
53 val = val >> 1;
54 }
55 }
56
57 RTLIL::Const::Const(RTLIL::State bit, int width)
58 {
59 flags = RTLIL::CONST_FLAG_NONE;
60 for (int i = 0; i < width; i++)
61 bits.push_back(bit);
62 }
63
64 bool RTLIL::Const::operator <(const RTLIL::Const &other) const
65 {
66 if (bits.size() != other.bits.size())
67 return bits.size() < other.bits.size();
68 for (size_t i = 0; i < bits.size(); i++)
69 if (bits[i] != other.bits[i])
70 return bits[i] < other.bits[i];
71 return false;
72 }
73
74 bool RTLIL::Const::operator ==(const RTLIL::Const &other) const
75 {
76 return bits == other.bits;
77 }
78
79 bool RTLIL::Const::operator !=(const RTLIL::Const &other) const
80 {
81 return bits != other.bits;
82 }
83
84 bool RTLIL::Const::as_bool() const
85 {
86 for (size_t i = 0; i < bits.size(); i++)
87 if (bits[i] == RTLIL::S1)
88 return true;
89 return false;
90 }
91
92 int RTLIL::Const::as_int() const
93 {
94 int ret = 0;
95 for (size_t i = 0; i < bits.size() && i < 32; i++)
96 if (bits[i] == RTLIL::S1)
97 ret |= 1 << i;
98 return ret;
99 }
100
101 std::string RTLIL::Const::as_string() const
102 {
103 std::string ret;
104 for (size_t i = bits.size(); i > 0; i--)
105 switch (bits[i-1]) {
106 case S0: ret += "0"; break;
107 case S1: ret += "1"; break;
108 case Sx: ret += "x"; break;
109 case Sz: ret += "z"; break;
110 case Sa: ret += "-"; break;
111 case Sm: ret += "m"; break;
112 }
113 return ret;
114 }
115
116 std::string RTLIL::Const::decode_string() const
117 {
118 std::string string;
119 std::vector <char> string_chars;
120 for (int i = 0; i < int (bits.size()); i += 8) {
121 char ch = 0;
122 for (int j = 0; j < 8 && i + j < int (bits.size()); j++)
123 if (bits[i + j] == RTLIL::State::S1)
124 ch |= 1 << j;
125 if (ch != 0)
126 string_chars.push_back(ch);
127 }
128 for (int i = int (string_chars.size()) - 1; i >= 0; i--)
129 string += string_chars[i];
130 return string;
131 }
132
133 bool RTLIL::Selection::selected_module(RTLIL::IdString mod_name) const
134 {
135 if (full_selection)
136 return true;
137 if (selected_modules.count(mod_name) > 0)
138 return true;
139 if (selected_members.count(mod_name) > 0)
140 return true;
141 return false;
142 }
143
144 bool RTLIL::Selection::selected_whole_module(RTLIL::IdString mod_name) const
145 {
146 if (full_selection)
147 return true;
148 if (selected_modules.count(mod_name) > 0)
149 return true;
150 return false;
151 }
152
153 bool RTLIL::Selection::selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const
154 {
155 if (full_selection)
156 return true;
157 if (selected_modules.count(mod_name) > 0)
158 return true;
159 if (selected_members.count(mod_name) > 0)
160 if (selected_members.at(mod_name).count(memb_name) > 0)
161 return true;
162 return false;
163 }
164
165 void RTLIL::Selection::optimize(RTLIL::Design *design)
166 {
167 if (full_selection) {
168 selected_modules.clear();
169 selected_members.clear();
170 return;
171 }
172
173 std::vector<RTLIL::IdString> del_list, add_list;
174
175 del_list.clear();
176 for (auto mod_name : selected_modules) {
177 if (design->modules_.count(mod_name) == 0)
178 del_list.push_back(mod_name);
179 selected_members.erase(mod_name);
180 }
181 for (auto mod_name : del_list)
182 selected_modules.erase(mod_name);
183
184 del_list.clear();
185 for (auto &it : selected_members)
186 if (design->modules_.count(it.first) == 0)
187 del_list.push_back(it.first);
188 for (auto mod_name : del_list)
189 selected_members.erase(mod_name);
190
191 for (auto &it : selected_members) {
192 del_list.clear();
193 for (auto memb_name : it.second)
194 if (design->modules_[it.first]->count_id(memb_name) == 0)
195 del_list.push_back(memb_name);
196 for (auto memb_name : del_list)
197 it.second.erase(memb_name);
198 }
199
200 del_list.clear();
201 add_list.clear();
202 for (auto &it : selected_members)
203 if (it.second.size() == 0)
204 del_list.push_back(it.first);
205 else if (it.second.size() == design->modules_[it.first]->wires_.size() + design->modules_[it.first]->memories.size() +
206 design->modules_[it.first]->cells_.size() + design->modules_[it.first]->processes.size())
207 add_list.push_back(it.first);
208 for (auto mod_name : del_list)
209 selected_members.erase(mod_name);
210 for (auto mod_name : add_list) {
211 selected_members.erase(mod_name);
212 selected_modules.insert(mod_name);
213 }
214
215 if (selected_modules.size() == design->modules_.size()) {
216 full_selection = true;
217 selected_modules.clear();
218 selected_members.clear();
219 }
220 }
221
222 RTLIL::Design::~Design()
223 {
224 for (auto it = modules_.begin(); it != modules_.end(); it++)
225 delete it->second;
226 }
227
228 RTLIL::ObjRange<RTLIL::Module*> RTLIL::Design::modules()
229 {
230 return RTLIL::ObjRange<RTLIL::Module*>(&modules_, &refcount_modules_);
231 }
232
233 RTLIL::Module *RTLIL::Design::module(RTLIL::IdString name)
234 {
235 return modules_.count(name) ? modules_.at(name) : NULL;
236 }
237
238 void RTLIL::Design::add(RTLIL::Module *module)
239 {
240 log_assert(modules_.count(module->name) == 0);
241 log_assert(refcount_modules_ == 0);
242 modules_[module->name] = module;
243 }
244
245 RTLIL::Module *RTLIL::Design::addModule(RTLIL::IdString name)
246 {
247 log_assert(modules_.count(name) == 0);
248 log_assert(refcount_modules_ == 0);
249 modules_[name] = new RTLIL::Module;
250 modules_[name]->name = name;
251 return modules_[name];
252 }
253
254 void RTLIL::Design::remove(RTLIL::Module *module)
255 {
256 log_assert(modules_.at(module->name) == module);
257 modules_.erase(module->name);
258 delete module;
259 }
260
261 void RTLIL::Design::check()
262 {
263 #ifndef NDEBUG
264 for (auto &it : modules_) {
265 log_assert(it.first == it.second->name);
266 log_assert(it.first.size() > 0 && (it.first[0] == '\\' || it.first[0] == '$'));
267 it.second->check();
268 }
269 #endif
270 }
271
272 void RTLIL::Design::optimize()
273 {
274 for (auto &it : modules_)
275 it.second->optimize();
276 for (auto &it : selection_stack)
277 it.optimize(this);
278 for (auto &it : selection_vars)
279 it.second.optimize(this);
280 }
281
282 bool RTLIL::Design::selected_module(RTLIL::IdString mod_name) const
283 {
284 if (!selected_active_module.empty() && mod_name != selected_active_module)
285 return false;
286 if (selection_stack.size() == 0)
287 return true;
288 return selection_stack.back().selected_module(mod_name);
289 }
290
291 bool RTLIL::Design::selected_whole_module(RTLIL::IdString mod_name) const
292 {
293 if (!selected_active_module.empty() && mod_name != selected_active_module)
294 return false;
295 if (selection_stack.size() == 0)
296 return true;
297 return selection_stack.back().selected_whole_module(mod_name);
298 }
299
300 bool RTLIL::Design::selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const
301 {
302 if (!selected_active_module.empty() && mod_name != selected_active_module)
303 return false;
304 if (selection_stack.size() == 0)
305 return true;
306 return selection_stack.back().selected_member(mod_name, memb_name);
307 }
308
309 bool RTLIL::Design::selected_module(RTLIL::Module *mod) const
310 {
311 return selected_module(mod->name);
312 }
313
314 bool RTLIL::Design::selected_whole_module(RTLIL::Module *mod) const
315 {
316 return selected_whole_module(mod->name);
317 }
318
319 RTLIL::Module::Module()
320 {
321 refcount_wires_ = 0;
322 refcount_cells_ = 0;
323 }
324
325 RTLIL::Module::~Module()
326 {
327 for (auto it = wires_.begin(); it != wires_.end(); it++)
328 delete it->second;
329 for (auto it = memories.begin(); it != memories.end(); it++)
330 delete it->second;
331 for (auto it = cells_.begin(); it != cells_.end(); it++)
332 delete it->second;
333 for (auto it = processes.begin(); it != processes.end(); it++)
334 delete it->second;
335 }
336
337 RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, std::map<RTLIL::IdString, RTLIL::Const>)
338 {
339 log_error("Module `%s' is used with parameters but is not parametric!\n", id2cstr(name));
340 }
341
342 size_t RTLIL::Module::count_id(RTLIL::IdString id)
343 {
344 return wires_.count(id) + memories.count(id) + cells_.count(id) + processes.count(id);
345 }
346
347 #ifndef NDEBUG
348 namespace {
349 struct InternalCellChecker
350 {
351 RTLIL::Module *module;
352 RTLIL::Cell *cell;
353 std::set<RTLIL::IdString> expected_params, expected_ports;
354
355 InternalCellChecker(RTLIL::Module *module, RTLIL::Cell *cell) : module(module), cell(cell) { }
356
357 void error(int linenr)
358 {
359 char *ptr;
360 size_t size;
361
362 FILE *f = open_memstream(&ptr, &size);
363 ILANG_BACKEND::dump_cell(f, " ", cell);
364 fputc(0, f);
365 fclose(f);
366
367 log_error("Found error in internal cell %s%s%s (%s) at %s:%d:\n%s",
368 module ? module->name.c_str() : "", module ? "." : "",
369 cell->name.c_str(), cell->type.c_str(), __FILE__, linenr, ptr);
370 }
371
372 int param(const char *name)
373 {
374 if (cell->parameters.count(name) == 0)
375 error(__LINE__);
376 expected_params.insert(name);
377 return cell->parameters.at(name).as_int();
378 }
379
380 int param_bool(const char *name)
381 {
382 int v = param(name);
383 if (cell->parameters.at(name).bits.size() > 32)
384 error(__LINE__);
385 if (v != 0 && v != 1)
386 error(__LINE__);
387 return v;
388 }
389
390 void param_bits(const char *name, int width)
391 {
392 param(name);
393 if (int(cell->parameters.at(name).bits.size()) != width)
394 error(__LINE__);
395 }
396
397 void port(const char *name, int width)
398 {
399 if (!cell->has(name))
400 error(__LINE__);
401 if (cell->get(name).size() != width)
402 error(__LINE__);
403 expected_ports.insert(name);
404 }
405
406 void check_expected(bool check_matched_sign = true)
407 {
408 for (auto &para : cell->parameters)
409 if (expected_params.count(para.first) == 0)
410 error(__LINE__);
411 for (auto &conn : cell->connections())
412 if (expected_ports.count(conn.first) == 0)
413 error(__LINE__);
414
415 if (expected_params.count("\\A_SIGNED") != 0 && expected_params.count("\\B_SIGNED") && check_matched_sign) {
416 bool a_is_signed = param("\\A_SIGNED") != 0;
417 bool b_is_signed = param("\\B_SIGNED") != 0;
418 if (a_is_signed != b_is_signed)
419 error(__LINE__);
420 }
421 }
422
423 void check_gate(const char *ports)
424 {
425 if (cell->parameters.size() != 0)
426 error(__LINE__);
427
428 for (const char *p = ports; *p; p++) {
429 char portname[3] = { '\\', *p, 0 };
430 if (!cell->has(portname))
431 error(__LINE__);
432 if (cell->get(portname).size() != 1)
433 error(__LINE__);
434 }
435
436 for (auto &conn : cell->connections()) {
437 if (conn.first.size() != 2 || conn.first.at(0) != '\\')
438 error(__LINE__);
439 if (strchr(ports, conn.first.at(1)) == NULL)
440 error(__LINE__);
441 }
442 }
443
444 void check()
445 {
446 if (cell->type[0] != '$' || cell->type.substr(0, 3) == "$__" || cell->type.substr(0, 8) == "$paramod" ||
447 cell->type.substr(0, 9) == "$verific$" || cell->type.substr(0, 7) == "$array:" || cell->type.substr(0, 8) == "$extern:")
448 return;
449
450 if (cell->type == "$not" || cell->type == "$pos" || cell->type == "$bu0" || cell->type == "$neg") {
451 param_bool("\\A_SIGNED");
452 port("\\A", param("\\A_WIDTH"));
453 port("\\Y", param("\\Y_WIDTH"));
454 check_expected();
455 return;
456 }
457
458 if (cell->type == "$and" || cell->type == "$or" || cell->type == "$xor" || cell->type == "$xnor") {
459 param_bool("\\A_SIGNED");
460 param_bool("\\B_SIGNED");
461 port("\\A", param("\\A_WIDTH"));
462 port("\\B", param("\\B_WIDTH"));
463 port("\\Y", param("\\Y_WIDTH"));
464 check_expected();
465 return;
466 }
467
468 if (cell->type == "$reduce_and" || cell->type == "$reduce_or" || cell->type == "$reduce_xor" ||
469 cell->type == "$reduce_xnor" || cell->type == "$reduce_bool") {
470 param_bool("\\A_SIGNED");
471 port("\\A", param("\\A_WIDTH"));
472 port("\\Y", param("\\Y_WIDTH"));
473 check_expected();
474 return;
475 }
476
477 if (cell->type == "$shl" || cell->type == "$shr" || cell->type == "$sshl" || cell->type == "$sshr") {
478 param_bool("\\A_SIGNED");
479 param_bool("\\B_SIGNED");
480 port("\\A", param("\\A_WIDTH"));
481 port("\\B", param("\\B_WIDTH"));
482 port("\\Y", param("\\Y_WIDTH"));
483 check_expected(false);
484 return;
485 }
486
487 if (cell->type == "$lt" || cell->type == "$le" || cell->type == "$eq" || cell->type == "$ne" ||
488 cell->type == "$eqx" || cell->type == "$nex" || cell->type == "$ge" || cell->type == "$gt") {
489 param_bool("\\A_SIGNED");
490 param_bool("\\B_SIGNED");
491 port("\\A", param("\\A_WIDTH"));
492 port("\\B", param("\\B_WIDTH"));
493 port("\\Y", param("\\Y_WIDTH"));
494 check_expected();
495 return;
496 }
497
498 if (cell->type == "$add" || cell->type == "$sub" || cell->type == "$mul" || cell->type == "$div" ||
499 cell->type == "$mod" || cell->type == "$pow") {
500 param_bool("\\A_SIGNED");
501 param_bool("\\B_SIGNED");
502 port("\\A", param("\\A_WIDTH"));
503 port("\\B", param("\\B_WIDTH"));
504 port("\\Y", param("\\Y_WIDTH"));
505 check_expected(cell->type != "$pow");
506 return;
507 }
508
509 if (cell->type == "$logic_not") {
510 param_bool("\\A_SIGNED");
511 port("\\A", param("\\A_WIDTH"));
512 port("\\Y", param("\\Y_WIDTH"));
513 check_expected();
514 return;
515 }
516
517 if (cell->type == "$logic_and" || cell->type == "$logic_or") {
518 param_bool("\\A_SIGNED");
519 param_bool("\\B_SIGNED");
520 port("\\A", param("\\A_WIDTH"));
521 port("\\B", param("\\B_WIDTH"));
522 port("\\Y", param("\\Y_WIDTH"));
523 check_expected(false);
524 return;
525 }
526
527 if (cell->type == "$slice") {
528 param("\\OFFSET");
529 port("\\A", param("\\A_WIDTH"));
530 port("\\Y", param("\\Y_WIDTH"));
531 if (param("\\OFFSET") + param("\\Y_WIDTH") > param("\\A_WIDTH"))
532 error(__LINE__);
533 check_expected();
534 return;
535 }
536
537 if (cell->type == "$concat") {
538 port("\\A", param("\\A_WIDTH"));
539 port("\\B", param("\\B_WIDTH"));
540 port("\\Y", param("\\A_WIDTH") + param("\\B_WIDTH"));
541 check_expected();
542 return;
543 }
544
545 if (cell->type == "$mux") {
546 port("\\A", param("\\WIDTH"));
547 port("\\B", param("\\WIDTH"));
548 port("\\S", 1);
549 port("\\Y", param("\\WIDTH"));
550 check_expected();
551 return;
552 }
553
554 if (cell->type == "$pmux" || cell->type == "$safe_pmux") {
555 port("\\A", param("\\WIDTH"));
556 port("\\B", param("\\WIDTH") * param("\\S_WIDTH"));
557 port("\\S", param("\\S_WIDTH"));
558 port("\\Y", param("\\WIDTH"));
559 check_expected();
560 return;
561 }
562
563 if (cell->type == "$lut") {
564 param("\\LUT");
565 port("\\I", param("\\WIDTH"));
566 port("\\O", 1);
567 check_expected();
568 return;
569 }
570
571 if (cell->type == "$sr") {
572 param_bool("\\SET_POLARITY");
573 param_bool("\\CLR_POLARITY");
574 port("\\SET", param("\\WIDTH"));
575 port("\\CLR", param("\\WIDTH"));
576 port("\\Q", param("\\WIDTH"));
577 check_expected();
578 return;
579 }
580
581 if (cell->type == "$dff") {
582 param_bool("\\CLK_POLARITY");
583 port("\\CLK", 1);
584 port("\\D", param("\\WIDTH"));
585 port("\\Q", param("\\WIDTH"));
586 check_expected();
587 return;
588 }
589
590 if (cell->type == "$dffsr") {
591 param_bool("\\CLK_POLARITY");
592 param_bool("\\SET_POLARITY");
593 param_bool("\\CLR_POLARITY");
594 port("\\CLK", 1);
595 port("\\SET", param("\\WIDTH"));
596 port("\\CLR", param("\\WIDTH"));
597 port("\\D", param("\\WIDTH"));
598 port("\\Q", param("\\WIDTH"));
599 check_expected();
600 return;
601 }
602
603 if (cell->type == "$adff") {
604 param_bool("\\CLK_POLARITY");
605 param_bool("\\ARST_POLARITY");
606 param_bits("\\ARST_VALUE", param("\\WIDTH"));
607 port("\\CLK", 1);
608 port("\\ARST", 1);
609 port("\\D", param("\\WIDTH"));
610 port("\\Q", param("\\WIDTH"));
611 check_expected();
612 return;
613 }
614
615 if (cell->type == "$dlatch") {
616 param_bool("\\EN_POLARITY");
617 port("\\EN", 1);
618 port("\\D", param("\\WIDTH"));
619 port("\\Q", param("\\WIDTH"));
620 check_expected();
621 return;
622 }
623
624 if (cell->type == "$dlatchsr") {
625 param_bool("\\EN_POLARITY");
626 param_bool("\\SET_POLARITY");
627 param_bool("\\CLR_POLARITY");
628 port("\\EN", 1);
629 port("\\SET", param("\\WIDTH"));
630 port("\\CLR", param("\\WIDTH"));
631 port("\\D", param("\\WIDTH"));
632 port("\\Q", param("\\WIDTH"));
633 check_expected();
634 return;
635 }
636
637 if (cell->type == "$fsm") {
638 param("\\NAME");
639 param_bool("\\CLK_POLARITY");
640 param_bool("\\ARST_POLARITY");
641 param("\\STATE_BITS");
642 param("\\STATE_NUM");
643 param("\\STATE_NUM_LOG2");
644 param("\\STATE_RST");
645 param_bits("\\STATE_TABLE", param("\\STATE_BITS") * param("\\STATE_NUM"));
646 param("\\TRANS_NUM");
647 param_bits("\\TRANS_TABLE", param("\\TRANS_NUM") * (2*param("\\STATE_NUM_LOG2") + param("\\CTRL_IN_WIDTH") + param("\\CTRL_OUT_WIDTH")));
648 port("\\CLK", 1);
649 port("\\ARST", 1);
650 port("\\CTRL_IN", param("\\CTRL_IN_WIDTH"));
651 port("\\CTRL_OUT", param("\\CTRL_OUT_WIDTH"));
652 check_expected();
653 return;
654 }
655
656 if (cell->type == "$memrd") {
657 param("\\MEMID");
658 param_bool("\\CLK_ENABLE");
659 param_bool("\\CLK_POLARITY");
660 param_bool("\\TRANSPARENT");
661 port("\\CLK", 1);
662 port("\\ADDR", param("\\ABITS"));
663 port("\\DATA", param("\\WIDTH"));
664 check_expected();
665 return;
666 }
667
668 if (cell->type == "$memwr") {
669 param("\\MEMID");
670 param_bool("\\CLK_ENABLE");
671 param_bool("\\CLK_POLARITY");
672 param("\\PRIORITY");
673 port("\\CLK", 1);
674 port("\\EN", param("\\WIDTH"));
675 port("\\ADDR", param("\\ABITS"));
676 port("\\DATA", param("\\WIDTH"));
677 check_expected();
678 return;
679 }
680
681 if (cell->type == "$mem") {
682 param("\\MEMID");
683 param("\\SIZE");
684 param("\\OFFSET");
685 param_bits("\\RD_CLK_ENABLE", param("\\RD_PORTS"));
686 param_bits("\\RD_CLK_POLARITY", param("\\RD_PORTS"));
687 param_bits("\\RD_TRANSPARENT", param("\\RD_PORTS"));
688 param_bits("\\WR_CLK_ENABLE", param("\\WR_PORTS"));
689 param_bits("\\WR_CLK_POLARITY", param("\\WR_PORTS"));
690 port("\\RD_CLK", param("\\RD_PORTS"));
691 port("\\RD_ADDR", param("\\RD_PORTS") * param("\\ABITS"));
692 port("\\RD_DATA", param("\\RD_PORTS") * param("\\WIDTH"));
693 port("\\WR_CLK", param("\\WR_PORTS"));
694 port("\\WR_EN", param("\\WR_PORTS") * param("\\WIDTH"));
695 port("\\WR_ADDR", param("\\WR_PORTS") * param("\\ABITS"));
696 port("\\WR_DATA", param("\\WR_PORTS") * param("\\WIDTH"));
697 check_expected();
698 return;
699 }
700
701 if (cell->type == "$assert") {
702 port("\\A", 1);
703 port("\\EN", 1);
704 check_expected();
705 return;
706 }
707
708 if (cell->type == "$_INV_") { check_gate("AY"); return; }
709 if (cell->type == "$_AND_") { check_gate("ABY"); return; }
710 if (cell->type == "$_OR_") { check_gate("ABY"); return; }
711 if (cell->type == "$_XOR_") { check_gate("ABY"); return; }
712 if (cell->type == "$_MUX_") { check_gate("ABSY"); return; }
713
714 if (cell->type == "$_SR_NN_") { check_gate("SRQ"); return; }
715 if (cell->type == "$_SR_NP_") { check_gate("SRQ"); return; }
716 if (cell->type == "$_SR_PN_") { check_gate("SRQ"); return; }
717 if (cell->type == "$_SR_PP_") { check_gate("SRQ"); return; }
718
719 if (cell->type == "$_DFF_N_") { check_gate("DQC"); return; }
720 if (cell->type == "$_DFF_P_") { check_gate("DQC"); return; }
721
722 if (cell->type == "$_DFF_NN0_") { check_gate("DQCR"); return; }
723 if (cell->type == "$_DFF_NN1_") { check_gate("DQCR"); return; }
724 if (cell->type == "$_DFF_NP0_") { check_gate("DQCR"); return; }
725 if (cell->type == "$_DFF_NP1_") { check_gate("DQCR"); return; }
726 if (cell->type == "$_DFF_PN0_") { check_gate("DQCR"); return; }
727 if (cell->type == "$_DFF_PN1_") { check_gate("DQCR"); return; }
728 if (cell->type == "$_DFF_PP0_") { check_gate("DQCR"); return; }
729 if (cell->type == "$_DFF_PP1_") { check_gate("DQCR"); return; }
730
731 if (cell->type == "$_DFFSR_NNN_") { check_gate("CSRDQ"); return; }
732 if (cell->type == "$_DFFSR_NNP_") { check_gate("CSRDQ"); return; }
733 if (cell->type == "$_DFFSR_NPN_") { check_gate("CSRDQ"); return; }
734 if (cell->type == "$_DFFSR_NPP_") { check_gate("CSRDQ"); return; }
735 if (cell->type == "$_DFFSR_PNN_") { check_gate("CSRDQ"); return; }
736 if (cell->type == "$_DFFSR_PNP_") { check_gate("CSRDQ"); return; }
737 if (cell->type == "$_DFFSR_PPN_") { check_gate("CSRDQ"); return; }
738 if (cell->type == "$_DFFSR_PPP_") { check_gate("CSRDQ"); return; }
739
740 if (cell->type == "$_DLATCH_N_") { check_gate("EDQ"); return; }
741 if (cell->type == "$_DLATCH_P_") { check_gate("EDQ"); return; }
742
743 if (cell->type == "$_DLATCHSR_NNN_") { check_gate("ESRDQ"); return; }
744 if (cell->type == "$_DLATCHSR_NNP_") { check_gate("ESRDQ"); return; }
745 if (cell->type == "$_DLATCHSR_NPN_") { check_gate("ESRDQ"); return; }
746 if (cell->type == "$_DLATCHSR_NPP_") { check_gate("ESRDQ"); return; }
747 if (cell->type == "$_DLATCHSR_PNN_") { check_gate("ESRDQ"); return; }
748 if (cell->type == "$_DLATCHSR_PNP_") { check_gate("ESRDQ"); return; }
749 if (cell->type == "$_DLATCHSR_PPN_") { check_gate("ESRDQ"); return; }
750 if (cell->type == "$_DLATCHSR_PPP_") { check_gate("ESRDQ"); return; }
751
752 error(__LINE__);
753 }
754 };
755 }
756 #endif
757
758 void RTLIL::Module::check()
759 {
760 #ifndef NDEBUG
761 for (auto &it : wires_) {
762 log_assert(it.first == it.second->name);
763 log_assert(it.first.size() > 0 && (it.first[0] == '\\' || it.first[0] == '$'));
764 log_assert(it.second->width >= 0);
765 log_assert(it.second->port_id >= 0);
766 for (auto &it2 : it.second->attributes) {
767 log_assert(it2.first.size() > 0 && (it2.first[0] == '\\' || it2.first[0] == '$'));
768 }
769 }
770
771 for (auto &it : memories) {
772 log_assert(it.first == it.second->name);
773 log_assert(it.first.size() > 0 && (it.first[0] == '\\' || it.first[0] == '$'));
774 log_assert(it.second->width >= 0);
775 log_assert(it.second->size >= 0);
776 for (auto &it2 : it.second->attributes) {
777 log_assert(it2.first.size() > 0 && (it2.first[0] == '\\' || it2.first[0] == '$'));
778 }
779 }
780
781 for (auto &it : cells_) {
782 log_assert(it.first == it.second->name);
783 log_assert(it.first.size() > 0 && (it.first[0] == '\\' || it.first[0] == '$'));
784 log_assert(it.second->type.size() > 0 && (it.second->type[0] == '\\' || it.second->type[0] == '$'));
785 for (auto &it2 : it.second->connections()) {
786 log_assert(it2.first.size() > 0 && (it2.first[0] == '\\' || it2.first[0] == '$'));
787 it2.second.check();
788 }
789 for (auto &it2 : it.second->attributes) {
790 log_assert(it2.first.size() > 0 && (it2.first[0] == '\\' || it2.first[0] == '$'));
791 }
792 for (auto &it2 : it.second->parameters) {
793 log_assert(it2.first.size() > 0 && (it2.first[0] == '\\' || it2.first[0] == '$'));
794 }
795 InternalCellChecker checker(this, it.second);
796 checker.check();
797 }
798
799 for (auto &it : processes) {
800 log_assert(it.first == it.second->name);
801 log_assert(it.first.size() > 0 && (it.first[0] == '\\' || it.first[0] == '$'));
802 // FIXME: More checks here..
803 }
804
805 for (auto &it : connections_) {
806 log_assert(it.first.size() == it.second.size());
807 it.first.check();
808 it.second.check();
809 }
810
811 for (auto &it : attributes) {
812 log_assert(it.first.size() > 0 && (it.first[0] == '\\' || it.first[0] == '$'));
813 }
814 #endif
815 }
816
817 void RTLIL::Module::optimize()
818 {
819 }
820
821 void RTLIL::Module::cloneInto(RTLIL::Module *new_mod) const
822 {
823 log_assert(new_mod->refcount_wires_ == 0);
824 log_assert(new_mod->refcount_cells_ == 0);
825
826 new_mod->connections_ = connections_;
827 new_mod->attributes = attributes;
828
829 for (auto &it : wires_)
830 new_mod->addWire(it.first, it.second);
831
832 for (auto &it : memories)
833 new_mod->memories[it.first] = new RTLIL::Memory(*it.second);
834
835 for (auto &it : cells_)
836 new_mod->addCell(it.first, it.second);
837
838 for (auto &it : processes)
839 new_mod->processes[it.first] = it.second->clone();
840
841 struct RewriteSigSpecWorker
842 {
843 RTLIL::Module *mod;
844 void operator()(RTLIL::SigSpec &sig)
845 {
846 std::vector<RTLIL::SigChunk> chunks = sig.chunks();
847 for (auto &c : chunks)
848 if (c.wire != NULL)
849 c.wire = mod->wires_.at(c.wire->name);
850 sig = chunks;
851 }
852 };
853
854 RewriteSigSpecWorker rewriteSigSpecWorker;
855 rewriteSigSpecWorker.mod = new_mod;
856 new_mod->rewrite_sigspecs(rewriteSigSpecWorker);
857 }
858
859 RTLIL::Module *RTLIL::Module::clone() const
860 {
861 RTLIL::Module *new_mod = new RTLIL::Module;
862 new_mod->name = name;
863 cloneInto(new_mod);
864 return new_mod;
865 }
866
867 void RTLIL::Module::add(RTLIL::Wire *wire)
868 {
869 log_assert(!wire->name.empty());
870 log_assert(count_id(wire->name) == 0);
871 log_assert(refcount_wires_ == 0);
872 wires_[wire->name] = wire;
873 }
874
875 void RTLIL::Module::add(RTLIL::Cell *cell)
876 {
877 log_assert(!cell->name.empty());
878 log_assert(count_id(cell->name) == 0);
879 log_assert(refcount_cells_ == 0);
880 cells_[cell->name] = cell;
881 }
882
883 namespace {
884 struct DeleteWireWorker
885 {
886 RTLIL::Module *module;
887 const std::set<RTLIL::Wire*> *wires_p;
888
889 void operator()(RTLIL::SigSpec &sig) {
890 std::vector<RTLIL::SigChunk> chunks = sig;
891 for (auto &c : chunks)
892 if (c.wire != NULL && wires_p->count(c.wire)) {
893 c.wire = module->addWire(NEW_ID, c.width);
894 c.offset = 0;
895 }
896 sig = chunks;
897 }
898 };
899 }
900
901 #if 0
902 void RTLIL::Module::remove(RTLIL::Wire *wire)
903 {
904 std::set<RTLIL::Wire*> wires_;
905 wires_.insert(wire);
906 remove(wires_);
907 }
908 #endif
909
910 void RTLIL::Module::remove(const std::set<RTLIL::Wire*> &wires)
911 {
912 log_assert(refcount_wires_ == 0);
913
914 DeleteWireWorker delete_wire_worker;
915 delete_wire_worker.module = this;
916 delete_wire_worker.wires_p = &wires;
917 rewrite_sigspecs(delete_wire_worker);
918
919 for (auto &it : wires) {
920 log_assert(wires_.count(it->name) != 0);
921 wires_.erase(it->name);
922 delete it;
923 }
924 }
925
926 void RTLIL::Module::remove(RTLIL::Cell *cell)
927 {
928 log_assert(cells_.count(cell->name) != 0);
929 log_assert(refcount_cells_ == 0);
930 cells_.erase(cell->name);
931 delete cell;
932 }
933
934 void RTLIL::Module::rename(RTLIL::Wire *wire, RTLIL::IdString new_name)
935 {
936 log_assert(wires_[wire->name] == wire);
937 log_assert(refcount_wires_ == 0);
938 wires_.erase(wire->name);
939 wire->name = new_name;
940 add(wire);
941 }
942
943 void RTLIL::Module::rename(RTLIL::Cell *cell, RTLIL::IdString new_name)
944 {
945 log_assert(cells_[cell->name] == cell);
946 log_assert(refcount_wires_ == 0);
947 cells_.erase(cell->name);
948 cell->name = new_name;
949 add(cell);
950 }
951
952 void RTLIL::Module::rename(RTLIL::IdString old_name, RTLIL::IdString new_name)
953 {
954 log_assert(count_id(old_name) != 0);
955 if (wires_.count(old_name))
956 rename(wires_.at(old_name), new_name);
957 else if (cells_.count(old_name))
958 rename(cells_.at(old_name), new_name);
959 else
960 log_abort();
961 }
962
963 static bool fixup_ports_compare(const RTLIL::Wire *a, const RTLIL::Wire *b)
964 {
965 if (a->port_id && !b->port_id)
966 return true;
967 if (!a->port_id && b->port_id)
968 return false;
969
970 if (a->port_id == b->port_id)
971 return a->name < b->name;
972 return a->port_id < b->port_id;
973 }
974
975 void RTLIL::Module::connect(const RTLIL::SigSig &conn)
976 {
977 connections_.push_back(conn);
978 }
979
980 void RTLIL::Module::connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs)
981 {
982 connections_.push_back(RTLIL::SigSig(lhs, rhs));
983 }
984
985 const std::vector<RTLIL::SigSig> &RTLIL::Module::connections() const
986 {
987 return connections_;
988 }
989
990 void RTLIL::Module::fixup_ports()
991 {
992 std::vector<RTLIL::Wire*> all_ports;
993
994 for (auto &w : wires_)
995 if (w.second->port_input || w.second->port_output)
996 all_ports.push_back(w.second);
997 else
998 w.second->port_id = 0;
999
1000 std::sort(all_ports.begin(), all_ports.end(), fixup_ports_compare);
1001 for (size_t i = 0; i < all_ports.size(); i++)
1002 all_ports[i]->port_id = i+1;
1003 }
1004
1005 RTLIL::Wire *RTLIL::Module::addWire(RTLIL::IdString name, int width)
1006 {
1007 RTLIL::Wire *wire = new RTLIL::Wire;
1008 wire->name = name;
1009 wire->width = width;
1010 add(wire);
1011 return wire;
1012 }
1013
1014 RTLIL::Wire *RTLIL::Module::addWire(RTLIL::IdString name, const RTLIL::Wire *other)
1015 {
1016 RTLIL::Wire *wire = addWire(name);
1017 wire->width = other->width;
1018 wire->start_offset = other->start_offset;
1019 wire->port_id = other->port_id;
1020 wire->port_input = other->port_input;
1021 wire->port_output = other->port_output;
1022 wire->upto = other->upto;
1023 wire->attributes = other->attributes;
1024 return wire;
1025 }
1026
1027 RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, RTLIL::IdString type)
1028 {
1029 RTLIL::Cell *cell = new RTLIL::Cell;
1030 cell->name = name;
1031 cell->type = type;
1032 add(cell);
1033 return cell;
1034 }
1035
1036 RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, const RTLIL::Cell *other)
1037 {
1038 RTLIL::Cell *cell = addCell(name, other->type);
1039 cell->connections_ = other->connections_;
1040 cell->parameters = other->parameters;
1041 cell->attributes = other->attributes;
1042 return cell;
1043 }
1044
1045 #define DEF_METHOD(_func, _y_size, _type) \
1046 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed) { \
1047 RTLIL::Cell *cell = new RTLIL::Cell; \
1048 cell->name = name; \
1049 cell->type = _type; \
1050 cell->parameters["\\A_SIGNED"] = is_signed; \
1051 cell->parameters["\\A_WIDTH"] = sig_a.size(); \
1052 cell->parameters["\\Y_WIDTH"] = sig_y.size(); \
1053 cell->set("\\A", sig_a); \
1054 cell->set("\\Y", sig_y); \
1055 add(cell); \
1056 return cell; \
1057 } \
1058 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed) { \
1059 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
1060 add ## _func(name, sig_a, sig_y, is_signed); \
1061 return sig_y; \
1062 }
1063 DEF_METHOD(Not, sig_a.size(), "$not")
1064 DEF_METHOD(Pos, sig_a.size(), "$pos")
1065 DEF_METHOD(Bu0, sig_a.size(), "$bu0")
1066 DEF_METHOD(Neg, sig_a.size(), "$neg")
1067 DEF_METHOD(ReduceAnd, 1, "$reduce_and")
1068 DEF_METHOD(ReduceOr, 1, "$reduce_or")
1069 DEF_METHOD(ReduceXor, 1, "$reduce_xor")
1070 DEF_METHOD(ReduceXnor, 1, "$reduce_xnor")
1071 DEF_METHOD(ReduceBool, 1, "$reduce_bool")
1072 DEF_METHOD(LogicNot, 1, "$logic_not")
1073 #undef DEF_METHOD
1074
1075 #define DEF_METHOD(_func, _y_size, _type) \
1076 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed) { \
1077 RTLIL::Cell *cell = new RTLIL::Cell; \
1078 cell->name = name; \
1079 cell->type = _type; \
1080 cell->parameters["\\A_SIGNED"] = is_signed; \
1081 cell->parameters["\\B_SIGNED"] = is_signed; \
1082 cell->parameters["\\A_WIDTH"] = sig_a.size(); \
1083 cell->parameters["\\B_WIDTH"] = sig_b.size(); \
1084 cell->parameters["\\Y_WIDTH"] = sig_y.size(); \
1085 cell->set("\\A", sig_a); \
1086 cell->set("\\B", sig_b); \
1087 cell->set("\\Y", sig_y); \
1088 add(cell); \
1089 return cell; \
1090 } \
1091 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed) { \
1092 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
1093 add ## _func(name, sig_a, sig_b, sig_y, is_signed); \
1094 return sig_y; \
1095 }
1096 DEF_METHOD(And, std::max(sig_a.size(), sig_b.size()), "$and")
1097 DEF_METHOD(Or, std::max(sig_a.size(), sig_b.size()), "$or")
1098 DEF_METHOD(Xor, std::max(sig_a.size(), sig_b.size()), "$xor")
1099 DEF_METHOD(Xnor, std::max(sig_a.size(), sig_b.size()), "$xnor")
1100 DEF_METHOD(Shl, sig_a.size(), "$shl")
1101 DEF_METHOD(Shr, sig_a.size(), "$shr")
1102 DEF_METHOD(Sshl, sig_a.size(), "$sshl")
1103 DEF_METHOD(Sshr, sig_a.size(), "$sshr")
1104 DEF_METHOD(Lt, 1, "$lt")
1105 DEF_METHOD(Le, 1, "$le")
1106 DEF_METHOD(Eq, 1, "$eq")
1107 DEF_METHOD(Ne, 1, "$ne")
1108 DEF_METHOD(Eqx, 1, "$eqx")
1109 DEF_METHOD(Nex, 1, "$nex")
1110 DEF_METHOD(Ge, 1, "$ge")
1111 DEF_METHOD(Gt, 1, "$gt")
1112 DEF_METHOD(Add, std::max(sig_a.size(), sig_b.size()), "$add")
1113 DEF_METHOD(Sub, std::max(sig_a.size(), sig_b.size()), "$sub")
1114 DEF_METHOD(Mul, std::max(sig_a.size(), sig_b.size()), "$mul")
1115 DEF_METHOD(Div, std::max(sig_a.size(), sig_b.size()), "$div")
1116 DEF_METHOD(Mod, std::max(sig_a.size(), sig_b.size()), "$mod")
1117 DEF_METHOD(LogicAnd, 1, "$logic_and")
1118 DEF_METHOD(LogicOr, 1, "$logic_or")
1119 #undef DEF_METHOD
1120
1121 #define DEF_METHOD(_func, _type, _pmux) \
1122 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, RTLIL::SigSpec sig_y) { \
1123 RTLIL::Cell *cell = new RTLIL::Cell; \
1124 cell->name = name; \
1125 cell->type = _type; \
1126 cell->parameters["\\WIDTH"] = sig_a.size(); \
1127 cell->parameters["\\WIDTH"] = sig_b.size(); \
1128 if (_pmux) cell->parameters["\\S_WIDTH"] = sig_s.size(); \
1129 cell->set("\\A", sig_a); \
1130 cell->set("\\B", sig_b); \
1131 cell->set("\\S", sig_s); \
1132 cell->set("\\Y", sig_y); \
1133 add(cell); \
1134 return cell; \
1135 } \
1136 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s) { \
1137 RTLIL::SigSpec sig_y = addWire(NEW_ID, sig_a.size()); \
1138 add ## _func(name, sig_a, sig_b, sig_s, sig_y); \
1139 return sig_y; \
1140 }
1141 DEF_METHOD(Mux, "$mux", 0)
1142 DEF_METHOD(Pmux, "$pmux", 1)
1143 DEF_METHOD(SafePmux, "$safe_pmux", 1)
1144 #undef DEF_METHOD
1145
1146 #define DEF_METHOD_2(_func, _type, _P1, _P2) \
1147 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig1, RTLIL::SigSpec sig2) { \
1148 RTLIL::Cell *cell = new RTLIL::Cell; \
1149 cell->name = name; \
1150 cell->type = _type; \
1151 cell->set("\\" #_P1, sig1); \
1152 cell->set("\\" #_P2, sig2); \
1153 add(cell); \
1154 return cell; \
1155 } \
1156 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig1) { \
1157 RTLIL::SigSpec sig2 = addWire(NEW_ID); \
1158 add ## _func(name, sig1, sig2); \
1159 return sig2; \
1160 }
1161 #define DEF_METHOD_3(_func, _type, _P1, _P2, _P3) \
1162 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig1, RTLIL::SigSpec sig2, RTLIL::SigSpec sig3) { \
1163 RTLIL::Cell *cell = new RTLIL::Cell; \
1164 cell->name = name; \
1165 cell->type = _type; \
1166 cell->set("\\" #_P1, sig1); \
1167 cell->set("\\" #_P2, sig2); \
1168 cell->set("\\" #_P3, sig3); \
1169 add(cell); \
1170 return cell; \
1171 } \
1172 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig1, RTLIL::SigSpec sig2) { \
1173 RTLIL::SigSpec sig3 = addWire(NEW_ID); \
1174 add ## _func(name, sig1, sig2, sig3); \
1175 return sig3; \
1176 }
1177 #define DEF_METHOD_4(_func, _type, _P1, _P2, _P3, _P4) \
1178 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig1, RTLIL::SigSpec sig2, RTLIL::SigSpec sig3, RTLIL::SigSpec sig4) { \
1179 RTLIL::Cell *cell = new RTLIL::Cell; \
1180 cell->name = name; \
1181 cell->type = _type; \
1182 cell->set("\\" #_P1, sig1); \
1183 cell->set("\\" #_P2, sig2); \
1184 cell->set("\\" #_P3, sig3); \
1185 cell->set("\\" #_P4, sig4); \
1186 add(cell); \
1187 return cell; \
1188 } \
1189 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig1, RTLIL::SigSpec sig2, RTLIL::SigSpec sig3) { \
1190 RTLIL::SigSpec sig4 = addWire(NEW_ID); \
1191 add ## _func(name, sig1, sig2, sig3, sig4); \
1192 return sig4; \
1193 }
1194 DEF_METHOD_2(InvGate, "$_INV_", A, Y)
1195 DEF_METHOD_3(AndGate, "$_AND_", A, B, Y)
1196 DEF_METHOD_3(OrGate, "$_OR_", A, B, Y)
1197 DEF_METHOD_3(XorGate, "$_XOR_", A, B, Y)
1198 DEF_METHOD_4(MuxGate, "$_MUX_", A, B, S, Y)
1199 #undef DEF_METHOD_2
1200 #undef DEF_METHOD_3
1201 #undef DEF_METHOD_4
1202
1203 RTLIL::Cell* RTLIL::Module::addPow(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool a_signed, bool b_signed)
1204 {
1205 RTLIL::Cell *cell = new RTLIL::Cell;
1206 cell->name = name;
1207 cell->type = "$pow";
1208 cell->parameters["\\A_SIGNED"] = a_signed;
1209 cell->parameters["\\B_SIGNED"] = b_signed;
1210 cell->parameters["\\A_WIDTH"] = sig_a.size();
1211 cell->parameters["\\B_WIDTH"] = sig_b.size();
1212 cell->parameters["\\Y_WIDTH"] = sig_y.size();
1213 cell->set("\\A", sig_a);
1214 cell->set("\\B", sig_b);
1215 cell->set("\\Y", sig_y);
1216 add(cell);
1217 return cell;
1218 }
1219
1220 RTLIL::Cell* RTLIL::Module::addSlice(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, RTLIL::Const offset)
1221 {
1222 RTLIL::Cell *cell = new RTLIL::Cell;
1223 cell->name = name;
1224 cell->type = "$slice";
1225 cell->parameters["\\A_WIDTH"] = sig_a.size();
1226 cell->parameters["\\Y_WIDTH"] = sig_y.size();
1227 cell->parameters["\\OFFSET"] = offset;
1228 cell->set("\\A", sig_a);
1229 cell->set("\\Y", sig_y);
1230 add(cell);
1231 return cell;
1232 }
1233
1234 RTLIL::Cell* RTLIL::Module::addConcat(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y)
1235 {
1236 RTLIL::Cell *cell = new RTLIL::Cell;
1237 cell->name = name;
1238 cell->type = "$concat";
1239 cell->parameters["\\A_WIDTH"] = sig_a.size();
1240 cell->parameters["\\B_WIDTH"] = sig_b.size();
1241 cell->set("\\A", sig_a);
1242 cell->set("\\B", sig_b);
1243 cell->set("\\Y", sig_y);
1244 add(cell);
1245 return cell;
1246 }
1247
1248 RTLIL::Cell* RTLIL::Module::addLut(RTLIL::IdString name, RTLIL::SigSpec sig_i, RTLIL::SigSpec sig_o, RTLIL::Const lut)
1249 {
1250 RTLIL::Cell *cell = new RTLIL::Cell;
1251 cell->name = name;
1252 cell->type = "$lut";
1253 cell->parameters["\\LUT"] = lut;
1254 cell->parameters["\\WIDTH"] = sig_i.size();
1255 cell->set("\\I", sig_i);
1256 cell->set("\\O", sig_o);
1257 add(cell);
1258 return cell;
1259 }
1260
1261 RTLIL::Cell* RTLIL::Module::addAssert(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en)
1262 {
1263 RTLIL::Cell *cell = new RTLIL::Cell;
1264 cell->name = name;
1265 cell->type = "$assert";
1266 cell->set("\\A", sig_a);
1267 cell->set("\\EN", sig_en);
1268 add(cell);
1269 return cell;
1270 }
1271
1272 RTLIL::Cell* RTLIL::Module::addSr(RTLIL::IdString name, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr, RTLIL::SigSpec sig_q, bool set_polarity, bool clr_polarity)
1273 {
1274 RTLIL::Cell *cell = new RTLIL::Cell;
1275 cell->name = name;
1276 cell->type = "$sr";
1277 cell->parameters["\\SET_POLARITY"] = set_polarity;
1278 cell->parameters["\\CLR_POLARITY"] = clr_polarity;
1279 cell->parameters["\\WIDTH"] = sig_q.size();
1280 cell->set("\\SET", sig_set);
1281 cell->set("\\CLR", sig_clr);
1282 cell->set("\\Q", sig_q);
1283 add(cell);
1284 return cell;
1285 }
1286
1287 RTLIL::Cell* RTLIL::Module::addDff(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity)
1288 {
1289 RTLIL::Cell *cell = new RTLIL::Cell;
1290 cell->name = name;
1291 cell->type = "$dff";
1292 cell->parameters["\\CLK_POLARITY"] = clk_polarity;
1293 cell->parameters["\\WIDTH"] = sig_q.size();
1294 cell->set("\\CLK", sig_clk);
1295 cell->set("\\D", sig_d);
1296 cell->set("\\Q", sig_q);
1297 add(cell);
1298 return cell;
1299 }
1300
1301 RTLIL::Cell* RTLIL::Module::addDffsr(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
1302 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity)
1303 {
1304 RTLIL::Cell *cell = new RTLIL::Cell;
1305 cell->name = name;
1306 cell->type = "$dffsr";
1307 cell->parameters["\\CLK_POLARITY"] = clk_polarity;
1308 cell->parameters["\\SET_POLARITY"] = set_polarity;
1309 cell->parameters["\\CLR_POLARITY"] = clr_polarity;
1310 cell->parameters["\\WIDTH"] = sig_q.size();
1311 cell->set("\\CLK", sig_clk);
1312 cell->set("\\SET", sig_set);
1313 cell->set("\\CLR", sig_clr);
1314 cell->set("\\D", sig_d);
1315 cell->set("\\Q", sig_q);
1316 add(cell);
1317 return cell;
1318 }
1319
1320 RTLIL::Cell* RTLIL::Module::addAdff(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_arst, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q,
1321 RTLIL::Const arst_value, bool clk_polarity, bool arst_polarity)
1322 {
1323 RTLIL::Cell *cell = new RTLIL::Cell;
1324 cell->name = name;
1325 cell->type = "$adff";
1326 cell->parameters["\\CLK_POLARITY"] = clk_polarity;
1327 cell->parameters["\\ARST_POLARITY"] = arst_polarity;
1328 cell->parameters["\\ARST_VALUE"] = arst_value;
1329 cell->parameters["\\WIDTH"] = sig_q.size();
1330 cell->set("\\CLK", sig_clk);
1331 cell->set("\\ARST", sig_arst);
1332 cell->set("\\D", sig_d);
1333 cell->set("\\Q", sig_q);
1334 add(cell);
1335 return cell;
1336 }
1337
1338 RTLIL::Cell* RTLIL::Module::addDlatch(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity)
1339 {
1340 RTLIL::Cell *cell = new RTLIL::Cell;
1341 cell->name = name;
1342 cell->type = "$dlatch";
1343 cell->parameters["\\EN_POLARITY"] = en_polarity;
1344 cell->parameters["\\WIDTH"] = sig_q.size();
1345 cell->set("\\EN", sig_en);
1346 cell->set("\\D", sig_d);
1347 cell->set("\\Q", sig_q);
1348 add(cell);
1349 return cell;
1350 }
1351
1352 RTLIL::Cell* RTLIL::Module::addDlatchsr(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
1353 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity, bool set_polarity, bool clr_polarity)
1354 {
1355 RTLIL::Cell *cell = new RTLIL::Cell;
1356 cell->name = name;
1357 cell->type = "$dlatchsr";
1358 cell->parameters["\\EN_POLARITY"] = en_polarity;
1359 cell->parameters["\\SET_POLARITY"] = set_polarity;
1360 cell->parameters["\\CLR_POLARITY"] = clr_polarity;
1361 cell->parameters["\\WIDTH"] = sig_q.size();
1362 cell->set("\\EN", sig_en);
1363 cell->set("\\SET", sig_set);
1364 cell->set("\\CLR", sig_clr);
1365 cell->set("\\D", sig_d);
1366 cell->set("\\Q", sig_q);
1367 add(cell);
1368 return cell;
1369 }
1370
1371 RTLIL::Cell* RTLIL::Module::addDffGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity)
1372 {
1373 RTLIL::Cell *cell = new RTLIL::Cell;
1374 cell->name = name;
1375 cell->type = stringf("$_DFF_%c_", clk_polarity ? 'P' : 'N');
1376 cell->set("\\C", sig_clk);
1377 cell->set("\\D", sig_d);
1378 cell->set("\\Q", sig_q);
1379 add(cell);
1380 return cell;
1381 }
1382
1383 RTLIL::Cell* RTLIL::Module::addDffsrGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
1384 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity)
1385 {
1386 RTLIL::Cell *cell = new RTLIL::Cell;
1387 cell->name = name;
1388 cell->type = stringf("$_DFFSR_%c%c%c_", clk_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N');
1389 cell->set("\\C", sig_clk);
1390 cell->set("\\S", sig_set);
1391 cell->set("\\R", sig_clr);
1392 cell->set("\\D", sig_d);
1393 cell->set("\\Q", sig_q);
1394 add(cell);
1395 return cell;
1396 }
1397
1398 RTLIL::Cell* RTLIL::Module::addAdffGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_arst, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q,
1399 bool arst_value, bool clk_polarity, bool arst_polarity)
1400 {
1401 RTLIL::Cell *cell = new RTLIL::Cell;
1402 cell->name = name;
1403 cell->type = stringf("$_DFF_%c%c%c_", clk_polarity ? 'P' : 'N', arst_polarity ? 'P' : 'N', arst_value ? '1' : '0');
1404 cell->set("\\C", sig_clk);
1405 cell->set("\\R", sig_arst);
1406 cell->set("\\D", sig_d);
1407 cell->set("\\Q", sig_q);
1408 add(cell);
1409 return cell;
1410 }
1411
1412 RTLIL::Cell* RTLIL::Module::addDlatchGate(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity)
1413 {
1414 RTLIL::Cell *cell = new RTLIL::Cell;
1415 cell->name = name;
1416 cell->type = stringf("$_DLATCH_%c_", en_polarity ? 'P' : 'N');
1417 cell->set("\\E", sig_en);
1418 cell->set("\\D", sig_d);
1419 cell->set("\\Q", sig_q);
1420 add(cell);
1421 return cell;
1422 }
1423
1424 RTLIL::Cell* RTLIL::Module::addDlatchsrGate(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
1425 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity, bool set_polarity, bool clr_polarity)
1426 {
1427 RTLIL::Cell *cell = new RTLIL::Cell;
1428 cell->name = name;
1429 cell->type = stringf("$_DLATCHSR_%c%c%c_", en_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N');
1430 cell->set("\\E", sig_en);
1431 cell->set("\\S", sig_set);
1432 cell->set("\\R", sig_clr);
1433 cell->set("\\D", sig_d);
1434 cell->set("\\Q", sig_q);
1435 add(cell);
1436 return cell;
1437 }
1438
1439
1440 RTLIL::Wire::Wire()
1441 {
1442 width = 1;
1443 start_offset = 0;
1444 port_id = 0;
1445 port_input = false;
1446 port_output = false;
1447 upto = false;
1448 }
1449
1450 RTLIL::Memory::Memory()
1451 {
1452 width = 1;
1453 size = 0;
1454 }
1455
1456 bool RTLIL::Cell::has(RTLIL::IdString portname)
1457 {
1458 return connections_.count(portname) != 0;
1459 }
1460
1461 void RTLIL::Cell::unset(RTLIL::IdString portname)
1462 {
1463 connections_.erase(portname);
1464 }
1465
1466 void RTLIL::Cell::set(RTLIL::IdString portname, RTLIL::SigSpec signal)
1467 {
1468 connections_[portname] = signal;
1469 }
1470
1471 const RTLIL::SigSpec &RTLIL::Cell::get(RTLIL::IdString portname) const
1472 {
1473 return connections_.at(portname);
1474 }
1475
1476 const std::map<RTLIL::IdString, RTLIL::SigSpec> &RTLIL::Cell::connections() const
1477 {
1478 return connections_;
1479 }
1480
1481 void RTLIL::Cell::check()
1482 {
1483 #ifndef NDEBUG
1484 InternalCellChecker checker(NULL, this);
1485 checker.check();
1486 #endif
1487 }
1488
1489 void RTLIL::Cell::fixup_parameters(bool set_a_signed, bool set_b_signed)
1490 {
1491 if (type[0] != '$' || type.substr(0, 2) == "$_" || type.substr(0, 8) == "$paramod" ||
1492 type.substr(0, 9) == "$verific$" || type.substr(0, 7) == "$array:" || type.substr(0, 8) == "$extern:")
1493 return;
1494
1495 if (type == "$mux" || type == "$pmux" || type == "$safe_pmux")
1496 {
1497 parameters["\\WIDTH"] = SIZE(connections_["\\Y"]);
1498 if (type == "$pmux" || type == "$safe_pmux")
1499 parameters["\\S_WIDTH"] = SIZE(connections_["\\S"]);
1500 check();
1501 return;
1502 }
1503
1504 bool signedness_ab = type != "$slice" && type != "$concat";
1505
1506 if (connections_.count("\\A")) {
1507 if (signedness_ab) {
1508 if (set_a_signed)
1509 parameters["\\A_SIGNED"] = true;
1510 else if (parameters.count("\\A_SIGNED") == 0)
1511 parameters["\\A_SIGNED"] = false;
1512 }
1513 parameters["\\A_WIDTH"] = SIZE(connections_["\\A"]);
1514 }
1515
1516 if (connections_.count("\\B")) {
1517 if (signedness_ab) {
1518 if (set_b_signed)
1519 parameters["\\B_SIGNED"] = true;
1520 else if (parameters.count("\\B_SIGNED") == 0)
1521 parameters["\\B_SIGNED"] = false;
1522 }
1523 parameters["\\B_WIDTH"] = SIZE(connections_["\\B"]);
1524 }
1525
1526 if (connections_.count("\\Y"))
1527 parameters["\\Y_WIDTH"] = SIZE(connections_["\\Y"]);
1528
1529 check();
1530 }
1531
1532 RTLIL::SigChunk::SigChunk()
1533 {
1534 wire = NULL;
1535 width = 0;
1536 offset = 0;
1537 }
1538
1539 RTLIL::SigChunk::SigChunk(const RTLIL::Const &value)
1540 {
1541 wire = NULL;
1542 data = value;
1543 width = data.bits.size();
1544 offset = 0;
1545 }
1546
1547 RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire)
1548 {
1549 log_assert(wire != nullptr);
1550 this->wire = wire;
1551 this->width = wire->width;
1552 this->offset = 0;
1553 }
1554
1555 RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire, int offset, int width)
1556 {
1557 log_assert(wire != nullptr);
1558 this->wire = wire;
1559 this->width = width;
1560 this->offset = offset;
1561 }
1562
1563 RTLIL::SigChunk::SigChunk(const std::string &str)
1564 {
1565 wire = NULL;
1566 data = RTLIL::Const(str);
1567 width = data.bits.size();
1568 offset = 0;
1569 }
1570
1571 RTLIL::SigChunk::SigChunk(int val, int width)
1572 {
1573 wire = NULL;
1574 data = RTLIL::Const(val, width);
1575 this->width = data.bits.size();
1576 offset = 0;
1577 }
1578
1579 RTLIL::SigChunk::SigChunk(RTLIL::State bit, int width)
1580 {
1581 wire = NULL;
1582 data = RTLIL::Const(bit, width);
1583 this->width = data.bits.size();
1584 offset = 0;
1585 }
1586
1587 RTLIL::SigChunk::SigChunk(RTLIL::SigBit bit)
1588 {
1589 wire = bit.wire;
1590 if (wire == NULL)
1591 data = RTLIL::Const(bit.data);
1592 offset = bit.offset;
1593 width = 1;
1594 }
1595
1596 RTLIL::SigChunk RTLIL::SigChunk::extract(int offset, int length) const
1597 {
1598 RTLIL::SigChunk ret;
1599 if (wire) {
1600 ret.wire = wire;
1601 ret.offset = this->offset + offset;
1602 ret.width = length;
1603 } else {
1604 for (int i = 0; i < length; i++)
1605 ret.data.bits.push_back(data.bits[offset+i]);
1606 ret.width = length;
1607 }
1608 return ret;
1609 }
1610
1611 bool RTLIL::SigChunk::operator <(const RTLIL::SigChunk &other) const
1612 {
1613 if (wire && other.wire)
1614 if (wire->name != other.wire->name)
1615 return wire->name < other.wire->name;
1616
1617 if (wire != other.wire)
1618 return wire < other.wire;
1619
1620 if (offset != other.offset)
1621 return offset < other.offset;
1622
1623 if (width != other.width)
1624 return width < other.width;
1625
1626 return data.bits < other.data.bits;
1627 }
1628
1629 bool RTLIL::SigChunk::operator ==(const RTLIL::SigChunk &other) const
1630 {
1631 if (wire != other.wire || width != other.width || offset != other.offset)
1632 return false;
1633 if (data.bits != other.data.bits)
1634 return false;
1635 return true;
1636 }
1637
1638 bool RTLIL::SigChunk::operator !=(const RTLIL::SigChunk &other) const
1639 {
1640 if (*this == other)
1641 return false;
1642 return true;
1643 }
1644
1645 RTLIL::SigSpec::SigSpec()
1646 {
1647 width_ = 0;
1648 hash_ = 0;
1649 }
1650
1651 RTLIL::SigSpec::SigSpec(const RTLIL::SigSpec &other)
1652 {
1653 *this = other;
1654 }
1655
1656 RTLIL::SigSpec::SigSpec(std::initializer_list<RTLIL::SigSpec> parts)
1657 {
1658 cover("kernel.rtlil.sigspec.init.list");
1659
1660 width_ = 0;
1661 hash_ = 0;
1662
1663 std::vector<RTLIL::SigSpec> parts_vec(parts.begin(), parts.end());
1664 for (auto it = parts_vec.rbegin(); it != parts_vec.rend(); it++)
1665 append(*it);
1666 }
1667
1668 const RTLIL::SigSpec &RTLIL::SigSpec::operator=(const RTLIL::SigSpec &other)
1669 {
1670 cover("kernel.rtlil.sigspec.assign");
1671
1672 width_ = other.width_;
1673 hash_ = other.hash_;
1674 chunks_ = other.chunks_;
1675 bits_.clear();
1676
1677 if (!other.bits_.empty())
1678 {
1679 RTLIL::SigChunk *last = NULL;
1680 int last_end_offset = 0;
1681
1682 for (auto &bit : other.bits_) {
1683 if (last && bit.wire == last->wire) {
1684 if (bit.wire == NULL) {
1685 last->data.bits.push_back(bit.data);
1686 last->width++;
1687 continue;
1688 } else if (last_end_offset == bit.offset) {
1689 last_end_offset++;
1690 last->width++;
1691 continue;
1692 }
1693 }
1694 chunks_.push_back(bit);
1695 last = &chunks_.back();
1696 last_end_offset = bit.offset + 1;
1697 }
1698
1699 check();
1700 }
1701
1702 return *this;
1703 }
1704
1705 RTLIL::SigSpec::SigSpec(const RTLIL::Const &value)
1706 {
1707 cover("kernel.rtlil.sigspec.init.const");
1708
1709 chunks_.push_back(RTLIL::SigChunk(value));
1710 width_ = chunks_.back().width;
1711 hash_ = 0;
1712 check();
1713 }
1714
1715 RTLIL::SigSpec::SigSpec(const RTLIL::SigChunk &chunk)
1716 {
1717 cover("kernel.rtlil.sigspec.init.chunk");
1718
1719 chunks_.push_back(chunk);
1720 width_ = chunks_.back().width;
1721 hash_ = 0;
1722 check();
1723 }
1724
1725 RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire)
1726 {
1727 cover("kernel.rtlil.sigspec.init.wire");
1728
1729 chunks_.push_back(RTLIL::SigChunk(wire));
1730 width_ = chunks_.back().width;
1731 hash_ = 0;
1732 check();
1733 }
1734
1735 RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire, int offset, int width)
1736 {
1737 cover("kernel.rtlil.sigspec.init.wire_part");
1738
1739 chunks_.push_back(RTLIL::SigChunk(wire, offset, width));
1740 width_ = chunks_.back().width;
1741 hash_ = 0;
1742 check();
1743 }
1744
1745 RTLIL::SigSpec::SigSpec(const std::string &str)
1746 {
1747 cover("kernel.rtlil.sigspec.init.str");
1748
1749 chunks_.push_back(RTLIL::SigChunk(str));
1750 width_ = chunks_.back().width;
1751 hash_ = 0;
1752 check();
1753 }
1754
1755 RTLIL::SigSpec::SigSpec(int val, int width)
1756 {
1757 cover("kernel.rtlil.sigspec.init.int");
1758
1759 chunks_.push_back(RTLIL::SigChunk(val, width));
1760 width_ = width;
1761 hash_ = 0;
1762 check();
1763 }
1764
1765 RTLIL::SigSpec::SigSpec(RTLIL::State bit, int width)
1766 {
1767 cover("kernel.rtlil.sigspec.init.state");
1768
1769 chunks_.push_back(RTLIL::SigChunk(bit, width));
1770 width_ = width;
1771 hash_ = 0;
1772 check();
1773 }
1774
1775 RTLIL::SigSpec::SigSpec(RTLIL::SigBit bit, int width)
1776 {
1777 cover("kernel.rtlil.sigspec.init.bit");
1778
1779 if (bit.wire == NULL)
1780 chunks_.push_back(RTLIL::SigChunk(bit.data, width));
1781 else
1782 for (int i = 0; i < width; i++)
1783 chunks_.push_back(bit);
1784 width_ = width;
1785 hash_ = 0;
1786 check();
1787 }
1788
1789 RTLIL::SigSpec::SigSpec(std::vector<RTLIL::SigChunk> chunks)
1790 {
1791 cover("kernel.rtlil.sigspec.init.stdvec_chunks");
1792
1793 width_ = 0;
1794 hash_ = 0;
1795 for (auto &c : chunks)
1796 append(c);
1797 check();
1798 }
1799
1800 RTLIL::SigSpec::SigSpec(std::vector<RTLIL::SigBit> bits)
1801 {
1802 cover("kernel.rtlil.sigspec.init.stdvec_bits");
1803
1804 width_ = 0;
1805 hash_ = 0;
1806 for (auto &bit : bits)
1807 append_bit(bit);
1808 check();
1809 }
1810
1811 RTLIL::SigSpec::SigSpec(std::set<RTLIL::SigBit> bits)
1812 {
1813 cover("kernel.rtlil.sigspec.init.stdset_bits");
1814
1815 width_ = 0;
1816 hash_ = 0;
1817 for (auto &bit : bits)
1818 append_bit(bit);
1819 check();
1820 }
1821
1822 void RTLIL::SigSpec::pack() const
1823 {
1824 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
1825
1826 if (that->bits_.empty())
1827 return;
1828
1829 cover("kernel.rtlil.sigspec.convert.pack");
1830 log_assert(that->chunks_.empty());
1831
1832 std::vector<RTLIL::SigBit> old_bits;
1833 old_bits.swap(that->bits_);
1834
1835 RTLIL::SigChunk *last = NULL;
1836 int last_end_offset = 0;
1837
1838 for (auto &bit : old_bits) {
1839 if (last && bit.wire == last->wire) {
1840 if (bit.wire == NULL) {
1841 last->data.bits.push_back(bit.data);
1842 last->width++;
1843 continue;
1844 } else if (last_end_offset == bit.offset) {
1845 last_end_offset++;
1846 last->width++;
1847 continue;
1848 }
1849 }
1850 that->chunks_.push_back(bit);
1851 last = &that->chunks_.back();
1852 last_end_offset = bit.offset + 1;
1853 }
1854
1855 check();
1856 }
1857
1858 void RTLIL::SigSpec::unpack() const
1859 {
1860 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
1861
1862 if (that->chunks_.empty())
1863 return;
1864
1865 cover("kernel.rtlil.sigspec.convert.unpack");
1866 log_assert(that->bits_.empty());
1867
1868 that->bits_.reserve(that->width_);
1869 for (auto &c : that->chunks_)
1870 for (int i = 0; i < c.width; i++)
1871 that->bits_.push_back(RTLIL::SigBit(c, i));
1872
1873 that->chunks_.clear();
1874 that->hash_ = 0;
1875 }
1876
1877 #define DJB2(_hash, _value) do { (_hash) = (((_hash) << 5) + (_hash)) + (_value); } while (0)
1878
1879 void RTLIL::SigSpec::hash() const
1880 {
1881 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
1882
1883 if (that->hash_ != 0)
1884 return;
1885
1886 cover("kernel.rtlil.sigspec.hash");
1887 that->pack();
1888
1889 that->hash_ = 5381;
1890 for (auto &c : that->chunks_)
1891 if (c.wire == NULL) {
1892 for (auto &v : c.data.bits)
1893 DJB2(that->hash_, v);
1894 } else {
1895 for (auto &v : c.wire->name)
1896 DJB2(that->hash_, v);
1897 DJB2(that->hash_, c.offset);
1898 DJB2(that->hash_, c.width);
1899 }
1900
1901 if (that->hash_ == 0)
1902 that->hash_ = 1;
1903 }
1904
1905 void RTLIL::SigSpec::sort()
1906 {
1907 unpack();
1908 cover("kernel.rtlil.sigspec.sort");
1909 std::sort(bits_.begin(), bits_.end());
1910 }
1911
1912 void RTLIL::SigSpec::sort_and_unify()
1913 {
1914 cover("kernel.rtlil.sigspec.sort_and_unify");
1915 *this = this->to_sigbit_set();
1916 }
1917
1918 void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with)
1919 {
1920 replace(pattern, with, this);
1921 }
1922
1923 void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with, RTLIL::SigSpec *other) const
1924 {
1925 cover("kernel.rtlil.sigspec.replace");
1926
1927 unpack();
1928 pattern.unpack();
1929 with.unpack();
1930
1931 log_assert(other != NULL);
1932 log_assert(width_ == other->width_);
1933 other->unpack();
1934
1935 log_assert(pattern.width_ == with.width_);
1936
1937 std::map<RTLIL::SigBit, RTLIL::SigBit> pattern_map;
1938 for (int i = 0; i < SIZE(pattern.bits_); i++)
1939 if (pattern.bits_[i].wire != NULL)
1940 pattern_map[pattern.bits_[i]] = with.bits_[i];
1941
1942 for (int i = 0; i < SIZE(bits_); i++)
1943 if (pattern_map.count(bits_[i]))
1944 other->bits_[i] = pattern_map.at(bits_[i]);
1945
1946 other->check();
1947 }
1948
1949 void RTLIL::SigSpec::remove(const RTLIL::SigSpec &pattern)
1950 {
1951 remove2(pattern, NULL);
1952 }
1953
1954 void RTLIL::SigSpec::remove(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other) const
1955 {
1956 RTLIL::SigSpec tmp = *this;
1957 tmp.remove2(pattern, other);
1958 }
1959
1960 void RTLIL::SigSpec::remove2(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other)
1961 {
1962 if (other)
1963 cover("kernel.rtlil.sigspec.remove_other");
1964 else
1965 cover("kernel.rtlil.sigspec.remove");
1966
1967 unpack();
1968
1969 if (other != NULL) {
1970 log_assert(width_ == other->width_);
1971 other->unpack();
1972 }
1973
1974 std::set<RTLIL::SigBit> pattern_bits = pattern.to_sigbit_set();
1975 std::vector<RTLIL::SigBit> new_bits, new_other_bits;
1976
1977 for (int i = 0; i < SIZE(bits_); i++) {
1978 if (bits_[i].wire != NULL && pattern_bits.count(bits_[i]))
1979 continue;
1980 if (other != NULL)
1981 new_other_bits.push_back(other->bits_[i]);
1982 new_bits.push_back(bits_[i]);
1983 }
1984
1985 bits_.swap(new_bits);
1986 width_ = SIZE(bits_);
1987
1988 if (other != NULL) {
1989 other->bits_.swap(new_other_bits);
1990 other->width_ = SIZE(other->bits_);
1991 }
1992
1993 check();
1994 }
1995
1996 RTLIL::SigSpec RTLIL::SigSpec::extract(RTLIL::SigSpec pattern, const RTLIL::SigSpec *other) const
1997 {
1998 if (other)
1999 cover("kernel.rtlil.sigspec.extract_other");
2000 else
2001 cover("kernel.rtlil.sigspec.extract");
2002
2003 pack();
2004 pattern.pack();
2005
2006 if (other != NULL)
2007 other->pack();
2008
2009 log_assert(other == NULL || width_ == other->width_);
2010
2011 std::set<RTLIL::SigBit> pat = pattern.to_sigbit_set();
2012 std::vector<RTLIL::SigBit> bits_match = to_sigbit_vector();
2013 RTLIL::SigSpec ret;
2014
2015 if (other) {
2016 std::vector<RTLIL::SigBit> bits_other = other->to_sigbit_vector();
2017 for (int i = 0; i < width_; i++)
2018 if (bits_match[i].wire && pat.count(bits_match[i]))
2019 ret.append_bit(bits_other[i]);
2020 } else {
2021 for (int i = 0; i < width_; i++)
2022 if (bits_match[i].wire && pat.count(bits_match[i]))
2023 ret.append_bit(bits_match[i]);
2024 }
2025
2026 ret.check();
2027 return ret;
2028 }
2029
2030 void RTLIL::SigSpec::replace(int offset, const RTLIL::SigSpec &with)
2031 {
2032 cover("kernel.rtlil.sigspec.replace_pos");
2033
2034 unpack();
2035 with.unpack();
2036
2037 log_assert(offset >= 0);
2038 log_assert(with.width_ >= 0);
2039 log_assert(offset+with.width_ <= width_);
2040
2041 for (int i = 0; i < with.width_; i++)
2042 bits_.at(offset + i) = with.bits_.at(i);
2043
2044 check();
2045 }
2046
2047 void RTLIL::SigSpec::remove_const()
2048 {
2049 if (packed())
2050 {
2051 cover("kernel.rtlil.sigspec.remove_const.packed");
2052
2053 std::vector<RTLIL::SigChunk> new_chunks;
2054 new_chunks.reserve(SIZE(chunks_));
2055
2056 width_ = 0;
2057 for (auto &chunk : chunks_)
2058 if (chunk.wire != NULL) {
2059 new_chunks.push_back(chunk);
2060 width_ += chunk.width;
2061 }
2062
2063 chunks_.swap(new_chunks);
2064 }
2065 else
2066 {
2067 cover("kernel.rtlil.sigspec.remove_const.unpacked");
2068
2069 std::vector<RTLIL::SigBit> new_bits;
2070 new_bits.reserve(width_);
2071
2072 for (auto &bit : bits_)
2073 if (bit.wire != NULL)
2074 new_bits.push_back(bit);
2075
2076 bits_.swap(new_bits);
2077 width_ = bits_.size();
2078 }
2079
2080 check();
2081 }
2082
2083 void RTLIL::SigSpec::remove(int offset, int length)
2084 {
2085 cover("kernel.rtlil.sigspec.remove_pos");
2086
2087 unpack();
2088
2089 log_assert(offset >= 0);
2090 log_assert(length >= 0);
2091 log_assert(offset + length <= width_);
2092
2093 bits_.erase(bits_.begin() + offset, bits_.begin() + offset + length);
2094 width_ = bits_.size();
2095
2096 check();
2097 }
2098
2099 RTLIL::SigSpec RTLIL::SigSpec::extract(int offset, int length) const
2100 {
2101 unpack();
2102 cover("kernel.rtlil.sigspec.extract_pos");
2103 return std::vector<RTLIL::SigBit>(bits_.begin() + offset, bits_.begin() + offset + length);
2104 }
2105
2106 void RTLIL::SigSpec::append(const RTLIL::SigSpec &signal)
2107 {
2108 if (signal.width_ == 0)
2109 return;
2110
2111 if (width_ == 0) {
2112 *this = signal;
2113 return;
2114 }
2115
2116 cover("kernel.rtlil.sigspec.append");
2117
2118 if (packed() != signal.packed()) {
2119 pack();
2120 signal.pack();
2121 }
2122
2123 if (packed())
2124 for (auto &other_c : signal.chunks_)
2125 {
2126 auto &my_last_c = chunks_.back();
2127 if (my_last_c.wire == NULL && other_c.wire == NULL) {
2128 auto &this_data = my_last_c.data.bits;
2129 auto &other_data = other_c.data.bits;
2130 this_data.insert(this_data.end(), other_data.begin(), other_data.end());
2131 my_last_c.width += other_c.width;
2132 } else
2133 if (my_last_c.wire == other_c.wire && my_last_c.offset + my_last_c.width == other_c.offset) {
2134 my_last_c.width += other_c.width;
2135 } else
2136 chunks_.push_back(other_c);
2137 }
2138 else
2139 bits_.insert(bits_.end(), signal.bits_.begin(), signal.bits_.end());
2140
2141 width_ += signal.width_;
2142 check();
2143 }
2144
2145 void RTLIL::SigSpec::append_bit(const RTLIL::SigBit &bit)
2146 {
2147 if (packed())
2148 {
2149 cover("kernel.rtlil.sigspec.append_bit.packed");
2150
2151 if (chunks_.size() == 0)
2152 chunks_.push_back(bit);
2153 else
2154 if (bit.wire == NULL)
2155 if (chunks_.back().wire == NULL) {
2156 chunks_.back().data.bits.push_back(bit.data);
2157 chunks_.back().width++;
2158 } else
2159 chunks_.push_back(bit);
2160 else
2161 if (chunks_.back().wire == bit.wire && chunks_.back().offset + chunks_.back().width == bit.offset)
2162 chunks_.back().width++;
2163 else
2164 chunks_.push_back(bit);
2165 }
2166 else
2167 {
2168 cover("kernel.rtlil.sigspec.append_bit.unpacked");
2169 bits_.push_back(bit);
2170 }
2171
2172 width_++;
2173 check();
2174 }
2175
2176 void RTLIL::SigSpec::extend(int width, bool is_signed)
2177 {
2178 cover("kernel.rtlil.sigspec.extend");
2179
2180 pack();
2181
2182 if (width_ > width)
2183 remove(width, width_ - width);
2184
2185 if (width_ < width) {
2186 RTLIL::SigSpec padding = width_ > 0 ? extract(width_ - 1, 1) : RTLIL::SigSpec(RTLIL::State::S0);
2187 if (!is_signed && padding != RTLIL::SigSpec(RTLIL::State::Sx) && padding != RTLIL::SigSpec(RTLIL::State::Sz) &&
2188 padding != RTLIL::SigSpec(RTLIL::State::Sa) && padding != RTLIL::SigSpec(RTLIL::State::Sm))
2189 padding = RTLIL::SigSpec(RTLIL::State::S0);
2190 while (width_ < width)
2191 append(padding);
2192 }
2193 }
2194
2195 void RTLIL::SigSpec::extend_u0(int width, bool is_signed)
2196 {
2197 cover("kernel.rtlil.sigspec.extend_u0");
2198
2199 pack();
2200
2201 if (width_ > width)
2202 remove(width, width_ - width);
2203
2204 if (width_ < width) {
2205 RTLIL::SigSpec padding = width_ > 0 ? extract(width_ - 1, 1) : RTLIL::SigSpec(RTLIL::State::S0);
2206 if (!is_signed)
2207 padding = RTLIL::SigSpec(RTLIL::State::S0);
2208 while (width_ < width)
2209 append(padding);
2210 }
2211
2212 }
2213
2214 RTLIL::SigSpec RTLIL::SigSpec::repeat(int num) const
2215 {
2216 cover("kernel.rtlil.sigspec.repeat");
2217
2218 RTLIL::SigSpec sig;
2219 for (int i = 0; i < num; i++)
2220 sig.append(*this);
2221 return sig;
2222 }
2223
2224 #ifndef NDEBUG
2225 void RTLIL::SigSpec::check() const
2226 {
2227 if (width_ > 64)
2228 {
2229 cover("kernel.rtlil.sigspec.check.skip");
2230 }
2231 else if (packed())
2232 {
2233 cover("kernel.rtlil.sigspec.check.packed");
2234
2235 int w = 0;
2236 for (size_t i = 0; i < chunks_.size(); i++) {
2237 const RTLIL::SigChunk chunk = chunks_[i];
2238 if (chunk.wire == NULL) {
2239 if (i > 0)
2240 log_assert(chunks_[i-1].wire != NULL);
2241 log_assert(chunk.offset == 0);
2242 log_assert(chunk.data.bits.size() == (size_t)chunk.width);
2243 } else {
2244 if (i > 0 && chunks_[i-1].wire == chunk.wire)
2245 log_assert(chunk.offset != chunks_[i-1].offset + chunks_[i-1].width);
2246 log_assert(chunk.offset >= 0);
2247 log_assert(chunk.width >= 0);
2248 log_assert(chunk.offset + chunk.width <= chunk.wire->width);
2249 log_assert(chunk.data.bits.size() == 0);
2250 }
2251 w += chunk.width;
2252 }
2253 log_assert(w == width_);
2254 log_assert(bits_.empty());
2255 }
2256 else
2257 {
2258 cover("kernel.rtlil.sigspec.check.unpacked");
2259
2260 log_assert(width_ == SIZE(bits_));
2261 log_assert(chunks_.empty());
2262 }
2263 }
2264 #endif
2265
2266 bool RTLIL::SigSpec::operator <(const RTLIL::SigSpec &other) const
2267 {
2268 cover("kernel.rtlil.sigspec.comp_lt");
2269
2270 if (this == &other)
2271 return false;
2272
2273 if (width_ != other.width_)
2274 return width_ < other.width_;
2275
2276 pack();
2277 other.pack();
2278
2279 if (chunks_.size() != other.chunks_.size())
2280 return chunks_.size() < other.chunks_.size();
2281
2282 hash();
2283 other.hash();
2284
2285 if (hash_ != other.hash_)
2286 return hash_ < other.hash_;
2287
2288 for (size_t i = 0; i < chunks_.size(); i++)
2289 if (chunks_[i] != other.chunks_[i]) {
2290 cover("kernel.rtlil.sigspec.comp_lt.hash_collision");
2291 return chunks_[i] < other.chunks_[i];
2292 }
2293
2294 cover("kernel.rtlil.sigspec.comp_lt.equal");
2295 return false;
2296 }
2297
2298 bool RTLIL::SigSpec::operator ==(const RTLIL::SigSpec &other) const
2299 {
2300 cover("kernel.rtlil.sigspec.comp_eq");
2301
2302 if (this == &other)
2303 return true;
2304
2305 if (width_ != other.width_)
2306 return false;
2307
2308 pack();
2309 other.pack();
2310
2311 if (chunks_.size() != chunks_.size())
2312 return false;
2313
2314 hash();
2315 other.hash();
2316
2317 if (hash_ != other.hash_)
2318 return false;
2319
2320 for (size_t i = 0; i < chunks_.size(); i++)
2321 if (chunks_[i] != other.chunks_[i]) {
2322 cover("kernel.rtlil.sigspec.comp_eq.hash_collision");
2323 return false;
2324 }
2325
2326 cover("kernel.rtlil.sigspec.comp_eq.equal");
2327 return true;
2328 }
2329
2330 bool RTLIL::SigSpec::is_wire() const
2331 {
2332 cover("kernel.rtlil.sigspec.is_wire");
2333
2334 pack();
2335 return SIZE(chunks_) == 1 && chunks_[0].wire && chunks_[0].wire->width == width_;
2336 }
2337
2338 bool RTLIL::SigSpec::is_chunk() const
2339 {
2340 cover("kernel.rtlil.sigspec.is_chunk");
2341
2342 pack();
2343 return SIZE(chunks_) == 1;
2344 }
2345
2346 bool RTLIL::SigSpec::is_fully_const() const
2347 {
2348 cover("kernel.rtlil.sigspec.is_fully_const");
2349
2350 pack();
2351 for (auto it = chunks_.begin(); it != chunks_.end(); it++)
2352 if (it->width > 0 && it->wire != NULL)
2353 return false;
2354 return true;
2355 }
2356
2357 bool RTLIL::SigSpec::is_fully_def() const
2358 {
2359 cover("kernel.rtlil.sigspec.is_fully_def");
2360
2361 pack();
2362 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
2363 if (it->width > 0 && it->wire != NULL)
2364 return false;
2365 for (size_t i = 0; i < it->data.bits.size(); i++)
2366 if (it->data.bits[i] != RTLIL::State::S0 && it->data.bits[i] != RTLIL::State::S1)
2367 return false;
2368 }
2369 return true;
2370 }
2371
2372 bool RTLIL::SigSpec::is_fully_undef() const
2373 {
2374 cover("kernel.rtlil.sigspec.is_fully_undef");
2375
2376 pack();
2377 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
2378 if (it->width > 0 && it->wire != NULL)
2379 return false;
2380 for (size_t i = 0; i < it->data.bits.size(); i++)
2381 if (it->data.bits[i] != RTLIL::State::Sx && it->data.bits[i] != RTLIL::State::Sz)
2382 return false;
2383 }
2384 return true;
2385 }
2386
2387 bool RTLIL::SigSpec::has_marked_bits() const
2388 {
2389 cover("kernel.rtlil.sigspec.has_marked_bits");
2390
2391 pack();
2392 for (auto it = chunks_.begin(); it != chunks_.end(); it++)
2393 if (it->width > 0 && it->wire == NULL) {
2394 for (size_t i = 0; i < it->data.bits.size(); i++)
2395 if (it->data.bits[i] == RTLIL::State::Sm)
2396 return true;
2397 }
2398 return false;
2399 }
2400
2401 bool RTLIL::SigSpec::as_bool() const
2402 {
2403 cover("kernel.rtlil.sigspec.as_bool");
2404
2405 pack();
2406 log_assert(is_fully_const() && SIZE(chunks_) <= 1);
2407 if (width_)
2408 return chunks_[0].data.as_bool();
2409 return false;
2410 }
2411
2412 int RTLIL::SigSpec::as_int() const
2413 {
2414 cover("kernel.rtlil.sigspec.as_int");
2415
2416 pack();
2417 log_assert(is_fully_const() && SIZE(chunks_) <= 1);
2418 if (width_)
2419 return chunks_[0].data.as_int();
2420 return 0;
2421 }
2422
2423 std::string RTLIL::SigSpec::as_string() const
2424 {
2425 cover("kernel.rtlil.sigspec.as_string");
2426
2427 pack();
2428 std::string str;
2429 for (size_t i = chunks_.size(); i > 0; i--) {
2430 const RTLIL::SigChunk &chunk = chunks_[i-1];
2431 if (chunk.wire != NULL)
2432 for (int j = 0; j < chunk.width; j++)
2433 str += "?";
2434 else
2435 str += chunk.data.as_string();
2436 }
2437 return str;
2438 }
2439
2440 RTLIL::Const RTLIL::SigSpec::as_const() const
2441 {
2442 cover("kernel.rtlil.sigspec.as_const");
2443
2444 pack();
2445 log_assert(is_fully_const() && SIZE(chunks_) <= 1);
2446 if (width_)
2447 return chunks_[0].data;
2448 return RTLIL::Const();
2449 }
2450
2451 RTLIL::Wire *RTLIL::SigSpec::as_wire() const
2452 {
2453 cover("kernel.rtlil.sigspec.as_wire");
2454
2455 pack();
2456 log_assert(is_wire());
2457 return chunks_[0].wire;
2458 }
2459
2460 RTLIL::SigChunk RTLIL::SigSpec::as_chunk() const
2461 {
2462 cover("kernel.rtlil.sigspec.as_chunk");
2463
2464 pack();
2465 log_assert(is_chunk());
2466 return chunks_[0];
2467 }
2468
2469 bool RTLIL::SigSpec::match(std::string pattern) const
2470 {
2471 cover("kernel.rtlil.sigspec.match");
2472
2473 pack();
2474 std::string str = as_string();
2475 log_assert(pattern.size() == str.size());
2476
2477 for (size_t i = 0; i < pattern.size(); i++) {
2478 if (pattern[i] == ' ')
2479 continue;
2480 if (pattern[i] == '*') {
2481 if (str[i] != 'z' && str[i] != 'x')
2482 return false;
2483 continue;
2484 }
2485 if (pattern[i] != str[i])
2486 return false;
2487 }
2488
2489 return true;
2490 }
2491
2492 std::set<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_set() const
2493 {
2494 cover("kernel.rtlil.sigspec.to_sigbit_set");
2495
2496 pack();
2497 std::set<RTLIL::SigBit> sigbits;
2498 for (auto &c : chunks_)
2499 for (int i = 0; i < c.width; i++)
2500 sigbits.insert(RTLIL::SigBit(c, i));
2501 return sigbits;
2502 }
2503
2504 std::vector<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_vector() const
2505 {
2506 cover("kernel.rtlil.sigspec.to_sigbit_vector");
2507
2508 unpack();
2509 return bits_;
2510 }
2511
2512 RTLIL::SigBit RTLIL::SigSpec::to_single_sigbit() const
2513 {
2514 cover("kernel.rtlil.sigspec.to_single_sigbit");
2515
2516 pack();
2517 log_assert(width_ == 1);
2518 for (auto &c : chunks_)
2519 if (c.width)
2520 return RTLIL::SigBit(c);
2521 log_abort();
2522 }
2523
2524 static void sigspec_parse_split(std::vector<std::string> &tokens, const std::string &text, char sep)
2525 {
2526 size_t start = 0, end = 0;
2527 while ((end = text.find(sep, start)) != std::string::npos) {
2528 tokens.push_back(text.substr(start, end - start));
2529 start = end + 1;
2530 }
2531 tokens.push_back(text.substr(start));
2532 }
2533
2534 static int sigspec_parse_get_dummy_line_num()
2535 {
2536 return 0;
2537 }
2538
2539 bool RTLIL::SigSpec::parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str)
2540 {
2541 cover("kernel.rtlil.sigspec.parse");
2542
2543 std::vector<std::string> tokens;
2544 sigspec_parse_split(tokens, str, ',');
2545
2546 sig = RTLIL::SigSpec();
2547 for (int tokidx = int(tokens.size())-1; tokidx >= 0; tokidx--)
2548 {
2549 std::string netname = tokens[tokidx];
2550 std::string indices;
2551
2552 if (netname.size() == 0)
2553 continue;
2554
2555 if ('0' <= netname[0] && netname[0] <= '9') {
2556 cover("kernel.rtlil.sigspec.parse.const");
2557 AST::get_line_num = sigspec_parse_get_dummy_line_num;
2558 AST::AstNode *ast = VERILOG_FRONTEND::const2ast(netname);
2559 if (ast == NULL)
2560 return false;
2561 sig.append(RTLIL::Const(ast->bits));
2562 delete ast;
2563 continue;
2564 }
2565
2566 if (module == NULL)
2567 return false;
2568
2569 cover("kernel.rtlil.sigspec.parse.net");
2570
2571 if (netname[0] != '$' && netname[0] != '\\')
2572 netname = "\\" + netname;
2573
2574 if (module->wires_.count(netname) == 0) {
2575 size_t indices_pos = netname.size()-1;
2576 if (indices_pos > 2 && netname[indices_pos] == ']')
2577 {
2578 indices_pos--;
2579 while (indices_pos > 0 && ('0' <= netname[indices_pos] && netname[indices_pos] <= '9')) indices_pos--;
2580 if (indices_pos > 0 && netname[indices_pos] == ':') {
2581 indices_pos--;
2582 while (indices_pos > 0 && ('0' <= netname[indices_pos] && netname[indices_pos] <= '9')) indices_pos--;
2583 }
2584 if (indices_pos > 0 && netname[indices_pos] == '[') {
2585 indices = netname.substr(indices_pos);
2586 netname = netname.substr(0, indices_pos);
2587 }
2588 }
2589 }
2590
2591 if (module->wires_.count(netname) == 0)
2592 return false;
2593
2594 RTLIL::Wire *wire = module->wires_.at(netname);
2595 if (!indices.empty()) {
2596 std::vector<std::string> index_tokens;
2597 sigspec_parse_split(index_tokens, indices.substr(1, indices.size()-2), ':');
2598 if (index_tokens.size() == 1) {
2599 cover("kernel.rtlil.sigspec.parse.bit_sel");
2600 sig.append(RTLIL::SigSpec(wire, atoi(index_tokens.at(0).c_str())));
2601 } else {
2602 cover("kernel.rtlil.sigspec.parse.part_sel");
2603 int a = atoi(index_tokens.at(0).c_str());
2604 int b = atoi(index_tokens.at(1).c_str());
2605 if (a > b) {
2606 int tmp = a;
2607 a = b, b = tmp;
2608 }
2609 sig.append(RTLIL::SigSpec(wire, a, b-a+1));
2610 }
2611 } else
2612 sig.append(wire);
2613 }
2614
2615 return true;
2616 }
2617
2618 bool RTLIL::SigSpec::parse_sel(RTLIL::SigSpec &sig, RTLIL::Design *design, RTLIL::Module *module, std::string str)
2619 {
2620 if (str.empty() || str[0] != '@')
2621 return parse(sig, module, str);
2622
2623 cover("kernel.rtlil.sigspec.parse.sel");
2624
2625 str = RTLIL::escape_id(str.substr(1));
2626 if (design->selection_vars.count(str) == 0)
2627 return false;
2628
2629 sig = RTLIL::SigSpec();
2630 RTLIL::Selection &sel = design->selection_vars.at(str);
2631 for (auto &it : module->wires_)
2632 if (sel.selected_member(module->name, it.first))
2633 sig.append(it.second);
2634
2635 return true;
2636 }
2637
2638 bool RTLIL::SigSpec::parse_rhs(const RTLIL::SigSpec &lhs, RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str)
2639 {
2640 if (str == "0") {
2641 cover("kernel.rtlil.sigspec.parse.rhs_zeros");
2642 sig = RTLIL::SigSpec(RTLIL::State::S0, lhs.width_);
2643 return true;
2644 }
2645
2646 if (str == "~0") {
2647 cover("kernel.rtlil.sigspec.parse.rhs_ones");
2648 sig = RTLIL::SigSpec(RTLIL::State::S1, lhs.width_);
2649 return true;
2650 }
2651
2652 if (lhs.chunks_.size() == 1) {
2653 char *p = (char*)str.c_str(), *endptr;
2654 long long int val = strtoll(p, &endptr, 10);
2655 if (endptr && endptr != p && *endptr == 0) {
2656 sig = RTLIL::SigSpec(val, lhs.width_);
2657 cover("kernel.rtlil.sigspec.parse.rhs_dec");
2658 return true;
2659 }
2660 }
2661
2662 return parse(sig, module, str);
2663 }
2664
2665 RTLIL::CaseRule::~CaseRule()
2666 {
2667 for (auto it = switches.begin(); it != switches.end(); it++)
2668 delete *it;
2669 }
2670
2671 RTLIL::CaseRule *RTLIL::CaseRule::clone() const
2672 {
2673 RTLIL::CaseRule *new_caserule = new RTLIL::CaseRule;
2674 new_caserule->compare = compare;
2675 new_caserule->actions = actions;
2676 for (auto &it : switches)
2677 new_caserule->switches.push_back(it->clone());
2678 return new_caserule;
2679 }
2680
2681 RTLIL::SwitchRule::~SwitchRule()
2682 {
2683 for (auto it = cases.begin(); it != cases.end(); it++)
2684 delete *it;
2685 }
2686
2687 RTLIL::SwitchRule *RTLIL::SwitchRule::clone() const
2688 {
2689 RTLIL::SwitchRule *new_switchrule = new RTLIL::SwitchRule;
2690 new_switchrule->signal = signal;
2691 new_switchrule->attributes = attributes;
2692 for (auto &it : cases)
2693 new_switchrule->cases.push_back(it->clone());
2694 return new_switchrule;
2695
2696 }
2697
2698 RTLIL::SyncRule *RTLIL::SyncRule::clone() const
2699 {
2700 RTLIL::SyncRule *new_syncrule = new RTLIL::SyncRule;
2701 new_syncrule->type = type;
2702 new_syncrule->signal = signal;
2703 new_syncrule->actions = actions;
2704 return new_syncrule;
2705 }
2706
2707 RTLIL::Process::~Process()
2708 {
2709 for (auto it = syncs.begin(); it != syncs.end(); it++)
2710 delete *it;
2711 }
2712
2713 RTLIL::Process *RTLIL::Process::clone() const
2714 {
2715 RTLIL::Process *new_proc = new RTLIL::Process;
2716
2717 new_proc->name = name;
2718 new_proc->attributes = attributes;
2719
2720 RTLIL::CaseRule *rc_ptr = root_case.clone();
2721 new_proc->root_case = *rc_ptr;
2722 rc_ptr->switches.clear();
2723 delete rc_ptr;
2724
2725 for (auto &it : syncs)
2726 new_proc->syncs.push_back(it->clone());
2727
2728 return new_proc;
2729 }
2730