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Added $alu cell type
[yosys.git] / kernel / rtlil.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 #include "kernel/yosys.h"
21 #include "frontends/verilog/verilog_frontend.h"
22 #include "backends/ilang/ilang_backend.h"
23
24 #include <string.h>
25 #include <algorithm>
26
27 YOSYS_NAMESPACE_BEGIN
28
29 std::vector<int> RTLIL::IdString::global_refcount_storage_;
30 std::vector<char*> RTLIL::IdString::global_id_storage_;
31 std::map<char*, int, RTLIL::IdString::char_ptr_cmp> RTLIL::IdString::global_id_index_;
32 std::vector<int> RTLIL::IdString::global_free_idx_list_;
33
34 RTLIL::Const::Const()
35 {
36 flags = RTLIL::CONST_FLAG_NONE;
37 }
38
39 RTLIL::Const::Const(std::string str)
40 {
41 flags = RTLIL::CONST_FLAG_STRING;
42 for (int i = str.size()-1; i >= 0; i--) {
43 unsigned char ch = str[i];
44 for (int j = 0; j < 8; j++) {
45 bits.push_back((ch & 1) != 0 ? RTLIL::S1 : RTLIL::S0);
46 ch = ch >> 1;
47 }
48 }
49 }
50
51 RTLIL::Const::Const(int val, int width)
52 {
53 flags = RTLIL::CONST_FLAG_NONE;
54 for (int i = 0; i < width; i++) {
55 bits.push_back((val & 1) != 0 ? RTLIL::S1 : RTLIL::S0);
56 val = val >> 1;
57 }
58 }
59
60 RTLIL::Const::Const(RTLIL::State bit, int width)
61 {
62 flags = RTLIL::CONST_FLAG_NONE;
63 for (int i = 0; i < width; i++)
64 bits.push_back(bit);
65 }
66
67 bool RTLIL::Const::operator <(const RTLIL::Const &other) const
68 {
69 if (bits.size() != other.bits.size())
70 return bits.size() < other.bits.size();
71 for (size_t i = 0; i < bits.size(); i++)
72 if (bits[i] != other.bits[i])
73 return bits[i] < other.bits[i];
74 return false;
75 }
76
77 bool RTLIL::Const::operator ==(const RTLIL::Const &other) const
78 {
79 return bits == other.bits;
80 }
81
82 bool RTLIL::Const::operator !=(const RTLIL::Const &other) const
83 {
84 return bits != other.bits;
85 }
86
87 bool RTLIL::Const::as_bool() const
88 {
89 for (size_t i = 0; i < bits.size(); i++)
90 if (bits[i] == RTLIL::S1)
91 return true;
92 return false;
93 }
94
95 int RTLIL::Const::as_int(bool is_signed) const
96 {
97 int32_t ret = 0;
98 for (size_t i = 0; i < bits.size() && i < 32; i++)
99 if (bits[i] == RTLIL::S1)
100 ret |= 1 << i;
101 if (is_signed && bits.back() == RTLIL::S1)
102 for (size_t i = bits.size(); i < 32; i++)
103 ret |= 1 << i;
104 return ret;
105 }
106
107 std::string RTLIL::Const::as_string() const
108 {
109 std::string ret;
110 for (size_t i = bits.size(); i > 0; i--)
111 switch (bits[i-1]) {
112 case S0: ret += "0"; break;
113 case S1: ret += "1"; break;
114 case Sx: ret += "x"; break;
115 case Sz: ret += "z"; break;
116 case Sa: ret += "-"; break;
117 case Sm: ret += "m"; break;
118 }
119 return ret;
120 }
121
122 std::string RTLIL::Const::decode_string() const
123 {
124 std::string string;
125 std::vector <char> string_chars;
126 for (int i = 0; i < int (bits.size()); i += 8) {
127 char ch = 0;
128 for (int j = 0; j < 8 && i + j < int (bits.size()); j++)
129 if (bits[i + j] == RTLIL::State::S1)
130 ch |= 1 << j;
131 if (ch != 0)
132 string_chars.push_back(ch);
133 }
134 for (int i = int (string_chars.size()) - 1; i >= 0; i--)
135 string += string_chars[i];
136 return string;
137 }
138
139 bool RTLIL::Selection::selected_module(RTLIL::IdString mod_name) const
140 {
141 if (full_selection)
142 return true;
143 if (selected_modules.count(mod_name) > 0)
144 return true;
145 if (selected_members.count(mod_name) > 0)
146 return true;
147 return false;
148 }
149
150 bool RTLIL::Selection::selected_whole_module(RTLIL::IdString mod_name) const
151 {
152 if (full_selection)
153 return true;
154 if (selected_modules.count(mod_name) > 0)
155 return true;
156 return false;
157 }
158
159 bool RTLIL::Selection::selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const
160 {
161 if (full_selection)
162 return true;
163 if (selected_modules.count(mod_name) > 0)
164 return true;
165 if (selected_members.count(mod_name) > 0)
166 if (selected_members.at(mod_name).count(memb_name) > 0)
167 return true;
168 return false;
169 }
170
171 void RTLIL::Selection::optimize(RTLIL::Design *design)
172 {
173 if (full_selection) {
174 selected_modules.clear();
175 selected_members.clear();
176 return;
177 }
178
179 std::vector<RTLIL::IdString> del_list, add_list;
180
181 del_list.clear();
182 for (auto mod_name : selected_modules) {
183 if (design->modules_.count(mod_name) == 0)
184 del_list.push_back(mod_name);
185 selected_members.erase(mod_name);
186 }
187 for (auto mod_name : del_list)
188 selected_modules.erase(mod_name);
189
190 del_list.clear();
191 for (auto &it : selected_members)
192 if (design->modules_.count(it.first) == 0)
193 del_list.push_back(it.first);
194 for (auto mod_name : del_list)
195 selected_members.erase(mod_name);
196
197 for (auto &it : selected_members) {
198 del_list.clear();
199 for (auto memb_name : it.second)
200 if (design->modules_[it.first]->count_id(memb_name) == 0)
201 del_list.push_back(memb_name);
202 for (auto memb_name : del_list)
203 it.second.erase(memb_name);
204 }
205
206 del_list.clear();
207 add_list.clear();
208 for (auto &it : selected_members)
209 if (it.second.size() == 0)
210 del_list.push_back(it.first);
211 else if (it.second.size() == design->modules_[it.first]->wires_.size() + design->modules_[it.first]->memories.size() +
212 design->modules_[it.first]->cells_.size() + design->modules_[it.first]->processes.size())
213 add_list.push_back(it.first);
214 for (auto mod_name : del_list)
215 selected_members.erase(mod_name);
216 for (auto mod_name : add_list) {
217 selected_members.erase(mod_name);
218 selected_modules.insert(mod_name);
219 }
220
221 if (selected_modules.size() == design->modules_.size()) {
222 full_selection = true;
223 selected_modules.clear();
224 selected_members.clear();
225 }
226 }
227
228 RTLIL::Design::Design()
229 {
230 refcount_modules_ = 0;
231 }
232
233 RTLIL::Design::~Design()
234 {
235 for (auto it = modules_.begin(); it != modules_.end(); it++)
236 delete it->second;
237 }
238
239 RTLIL::ObjRange<RTLIL::Module*> RTLIL::Design::modules()
240 {
241 return RTLIL::ObjRange<RTLIL::Module*>(&modules_, &refcount_modules_);
242 }
243
244 RTLIL::Module *RTLIL::Design::module(RTLIL::IdString name)
245 {
246 return modules_.count(name) ? modules_.at(name) : NULL;
247 }
248
249 void RTLIL::Design::add(RTLIL::Module *module)
250 {
251 log_assert(modules_.count(module->name) == 0);
252 log_assert(refcount_modules_ == 0);
253 modules_[module->name] = module;
254 module->design = this;
255
256 for (auto mon : monitors)
257 mon->notify_module_add(module);
258 }
259
260 RTLIL::Module *RTLIL::Design::addModule(RTLIL::IdString name)
261 {
262 log_assert(modules_.count(name) == 0);
263 log_assert(refcount_modules_ == 0);
264
265 RTLIL::Module *module = new RTLIL::Module;
266 modules_[name] = module;
267 module->design = this;
268 module->name = name;
269
270 for (auto mon : monitors)
271 mon->notify_module_add(module);
272
273 return module;
274 }
275
276 void RTLIL::Design::remove(RTLIL::Module *module)
277 {
278 for (auto mon : monitors)
279 mon->notify_module_del(module);
280
281 log_assert(modules_.at(module->name) == module);
282 modules_.erase(module->name);
283 delete module;
284 }
285
286 void RTLIL::Design::check()
287 {
288 #ifndef NDEBUG
289 for (auto &it : modules_) {
290 log_assert(this == it.second->design);
291 log_assert(it.first == it.second->name);
292 log_assert(!it.first.empty());
293 it.second->check();
294 }
295 #endif
296 }
297
298 void RTLIL::Design::optimize()
299 {
300 for (auto &it : modules_)
301 it.second->optimize();
302 for (auto &it : selection_stack)
303 it.optimize(this);
304 for (auto &it : selection_vars)
305 it.second.optimize(this);
306 }
307
308 bool RTLIL::Design::selected_module(RTLIL::IdString mod_name) const
309 {
310 if (!selected_active_module.empty() && mod_name != selected_active_module)
311 return false;
312 if (selection_stack.size() == 0)
313 return true;
314 return selection_stack.back().selected_module(mod_name);
315 }
316
317 bool RTLIL::Design::selected_whole_module(RTLIL::IdString mod_name) const
318 {
319 if (!selected_active_module.empty() && mod_name != selected_active_module)
320 return false;
321 if (selection_stack.size() == 0)
322 return true;
323 return selection_stack.back().selected_whole_module(mod_name);
324 }
325
326 bool RTLIL::Design::selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const
327 {
328 if (!selected_active_module.empty() && mod_name != selected_active_module)
329 return false;
330 if (selection_stack.size() == 0)
331 return true;
332 return selection_stack.back().selected_member(mod_name, memb_name);
333 }
334
335 bool RTLIL::Design::selected_module(RTLIL::Module *mod) const
336 {
337 return selected_module(mod->name);
338 }
339
340 bool RTLIL::Design::selected_whole_module(RTLIL::Module *mod) const
341 {
342 return selected_whole_module(mod->name);
343 }
344
345 std::vector<RTLIL::Module*> RTLIL::Design::selected_modules() const
346 {
347 std::vector<RTLIL::Module*> result;
348 result.reserve(modules_.size());
349 for (auto &it : modules_)
350 if (selected_module(it.first))
351 result.push_back(it.second);
352 return result;
353 }
354
355 std::vector<RTLIL::Module*> RTLIL::Design::selected_whole_modules() const
356 {
357 std::vector<RTLIL::Module*> result;
358 result.reserve(modules_.size());
359 for (auto &it : modules_)
360 if (selected_whole_module(it.first))
361 result.push_back(it.second);
362 return result;
363 }
364
365 std::vector<RTLIL::Module*> RTLIL::Design::selected_whole_modules_warn() const
366 {
367 std::vector<RTLIL::Module*> result;
368 result.reserve(modules_.size());
369 for (auto &it : modules_)
370 if (selected_whole_module(it.first))
371 result.push_back(it.second);
372 else if (selected_module(it.first))
373 log("Warning: Ignoring partially selected module %s.\n", log_id(it.first));
374 return result;
375 }
376
377 RTLIL::Module::Module()
378 {
379 design = nullptr;
380 refcount_wires_ = 0;
381 refcount_cells_ = 0;
382 }
383
384 RTLIL::Module::~Module()
385 {
386 for (auto it = wires_.begin(); it != wires_.end(); it++)
387 delete it->second;
388 for (auto it = memories.begin(); it != memories.end(); it++)
389 delete it->second;
390 for (auto it = cells_.begin(); it != cells_.end(); it++)
391 delete it->second;
392 for (auto it = processes.begin(); it != processes.end(); it++)
393 delete it->second;
394 }
395
396 RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, std::map<RTLIL::IdString, RTLIL::Const>)
397 {
398 log_error("Module `%s' is used with parameters but is not parametric!\n", id2cstr(name));
399 }
400
401 size_t RTLIL::Module::count_id(RTLIL::IdString id)
402 {
403 return wires_.count(id) + memories.count(id) + cells_.count(id) + processes.count(id);
404 }
405
406 #ifndef NDEBUG
407 namespace {
408 struct InternalCellChecker
409 {
410 RTLIL::Module *module;
411 RTLIL::Cell *cell;
412 std::set<RTLIL::IdString> expected_params, expected_ports;
413
414 InternalCellChecker(RTLIL::Module *module, RTLIL::Cell *cell) : module(module), cell(cell) { }
415
416 void error(int linenr)
417 {
418 std::stringstream buf;
419 ILANG_BACKEND::dump_cell(buf, " ", cell);
420
421 log_error("Found error in internal cell %s%s%s (%s) at %s:%d:\n%s",
422 module ? module->name.c_str() : "", module ? "." : "",
423 cell->name.c_str(), cell->type.c_str(), __FILE__, linenr, buf.str().c_str());
424 }
425
426 int param(const char *name)
427 {
428 if (cell->parameters.count(name) == 0)
429 error(__LINE__);
430 expected_params.insert(name);
431 return cell->parameters.at(name).as_int();
432 }
433
434 int param_bool(const char *name)
435 {
436 int v = param(name);
437 if (cell->parameters.at(name).bits.size() > 32)
438 error(__LINE__);
439 if (v != 0 && v != 1)
440 error(__LINE__);
441 return v;
442 }
443
444 void param_bits(const char *name, int width)
445 {
446 param(name);
447 if (int(cell->parameters.at(name).bits.size()) != width)
448 error(__LINE__);
449 }
450
451 void port(const char *name, int width)
452 {
453 if (!cell->hasPort(name))
454 error(__LINE__);
455 if (cell->getPort(name).size() != width)
456 error(__LINE__);
457 expected_ports.insert(name);
458 }
459
460 void check_expected(bool check_matched_sign = true)
461 {
462 for (auto &para : cell->parameters)
463 if (expected_params.count(para.first) == 0)
464 error(__LINE__);
465 for (auto &conn : cell->connections())
466 if (expected_ports.count(conn.first) == 0)
467 error(__LINE__);
468
469 if (expected_params.count("\\A_SIGNED") != 0 && expected_params.count("\\B_SIGNED") && check_matched_sign) {
470 bool a_is_signed = param("\\A_SIGNED") != 0;
471 bool b_is_signed = param("\\B_SIGNED") != 0;
472 if (a_is_signed != b_is_signed)
473 error(__LINE__);
474 }
475 }
476
477 void check_gate(const char *ports)
478 {
479 if (cell->parameters.size() != 0)
480 error(__LINE__);
481
482 for (const char *p = ports; *p; p++) {
483 char portname[3] = { '\\', *p, 0 };
484 if (!cell->hasPort(portname))
485 error(__LINE__);
486 if (cell->getPort(portname).size() != 1)
487 error(__LINE__);
488 }
489
490 for (auto &conn : cell->connections()) {
491 if (conn.first.size() != 2 || conn.first[0] != '\\')
492 error(__LINE__);
493 if (strchr(ports, conn.first[1]) == NULL)
494 error(__LINE__);
495 }
496 }
497
498 void check()
499 {
500 if (cell->type.substr(0, 1) != "$" || cell->type.substr(0, 3) == "$__" || cell->type.substr(0, 8) == "$paramod" ||
501 cell->type.substr(0, 9) == "$verific$" || cell->type.substr(0, 7) == "$array:" || cell->type.substr(0, 8) == "$extern:")
502 return;
503
504 if (cell->type.in("$not", "$pos", "$bu0", "$neg")) {
505 param_bool("\\A_SIGNED");
506 port("\\A", param("\\A_WIDTH"));
507 port("\\Y", param("\\Y_WIDTH"));
508 check_expected();
509 return;
510 }
511
512 if (cell->type.in("$and", "$or", "$xor", "$xnor")) {
513 param_bool("\\A_SIGNED");
514 param_bool("\\B_SIGNED");
515 port("\\A", param("\\A_WIDTH"));
516 port("\\B", param("\\B_WIDTH"));
517 port("\\Y", param("\\Y_WIDTH"));
518 check_expected();
519 return;
520 }
521
522 if (cell->type.in("$reduce_and", "$reduce_or", "$reduce_xor", "$reduce_xnor", "$reduce_bool")) {
523 param_bool("\\A_SIGNED");
524 port("\\A", param("\\A_WIDTH"));
525 port("\\Y", param("\\Y_WIDTH"));
526 check_expected();
527 return;
528 }
529
530 if (cell->type.in("$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx")) {
531 param_bool("\\A_SIGNED");
532 param_bool("\\B_SIGNED");
533 port("\\A", param("\\A_WIDTH"));
534 port("\\B", param("\\B_WIDTH"));
535 port("\\Y", param("\\Y_WIDTH"));
536 check_expected(false);
537 return;
538 }
539
540 if (cell->type.in("$lt", "$le", "$eq", "$ne", "$eqx", "$nex", "$ge", "$gt")) {
541 param_bool("\\A_SIGNED");
542 param_bool("\\B_SIGNED");
543 port("\\A", param("\\A_WIDTH"));
544 port("\\B", param("\\B_WIDTH"));
545 port("\\Y", param("\\Y_WIDTH"));
546 check_expected();
547 return;
548 }
549
550 if (cell->type.in("$add", "$sub", "$mul", "$div", "$mod", "$pow")) {
551 param_bool("\\A_SIGNED");
552 param_bool("\\B_SIGNED");
553 port("\\A", param("\\A_WIDTH"));
554 port("\\B", param("\\B_WIDTH"));
555 port("\\Y", param("\\Y_WIDTH"));
556 check_expected(cell->type != "$pow");
557 return;
558 }
559
560 if (cell->type == "$alu") {
561 param_bool("\\A_SIGNED");
562 param_bool("\\B_SIGNED");
563 port("\\A", param("\\A_WIDTH"));
564 port("\\B", param("\\B_WIDTH"));
565 port("\\CI", 1);
566 port("\\BI", 1);
567 port("\\X", param("\\Y_WIDTH"));
568 port("\\Y", param("\\Y_WIDTH"));
569 port("\\CO", param("\\Y_WIDTH"));
570 check_expected();
571 return;
572 }
573
574 if (cell->type == "$logic_not") {
575 param_bool("\\A_SIGNED");
576 port("\\A", param("\\A_WIDTH"));
577 port("\\Y", param("\\Y_WIDTH"));
578 check_expected();
579 return;
580 }
581
582 if (cell->type == "$logic_and" || cell->type == "$logic_or") {
583 param_bool("\\A_SIGNED");
584 param_bool("\\B_SIGNED");
585 port("\\A", param("\\A_WIDTH"));
586 port("\\B", param("\\B_WIDTH"));
587 port("\\Y", param("\\Y_WIDTH"));
588 check_expected(false);
589 return;
590 }
591
592 if (cell->type == "$slice") {
593 param("\\OFFSET");
594 port("\\A", param("\\A_WIDTH"));
595 port("\\Y", param("\\Y_WIDTH"));
596 if (param("\\OFFSET") + param("\\Y_WIDTH") > param("\\A_WIDTH"))
597 error(__LINE__);
598 check_expected();
599 return;
600 }
601
602 if (cell->type == "$concat") {
603 port("\\A", param("\\A_WIDTH"));
604 port("\\B", param("\\B_WIDTH"));
605 port("\\Y", param("\\A_WIDTH") + param("\\B_WIDTH"));
606 check_expected();
607 return;
608 }
609
610 if (cell->type == "$mux") {
611 port("\\A", param("\\WIDTH"));
612 port("\\B", param("\\WIDTH"));
613 port("\\S", 1);
614 port("\\Y", param("\\WIDTH"));
615 check_expected();
616 return;
617 }
618
619 if (cell->type == "$pmux") {
620 port("\\A", param("\\WIDTH"));
621 port("\\B", param("\\WIDTH") * param("\\S_WIDTH"));
622 port("\\S", param("\\S_WIDTH"));
623 port("\\Y", param("\\WIDTH"));
624 check_expected();
625 return;
626 }
627
628 if (cell->type == "$lut") {
629 param("\\LUT");
630 port("\\A", param("\\WIDTH"));
631 port("\\Y", 1);
632 check_expected();
633 return;
634 }
635
636 if (cell->type == "$sr") {
637 param_bool("\\SET_POLARITY");
638 param_bool("\\CLR_POLARITY");
639 port("\\SET", param("\\WIDTH"));
640 port("\\CLR", param("\\WIDTH"));
641 port("\\Q", param("\\WIDTH"));
642 check_expected();
643 return;
644 }
645
646 if (cell->type == "$dff") {
647 param_bool("\\CLK_POLARITY");
648 port("\\CLK", 1);
649 port("\\D", param("\\WIDTH"));
650 port("\\Q", param("\\WIDTH"));
651 check_expected();
652 return;
653 }
654
655 if (cell->type == "$dffsr") {
656 param_bool("\\CLK_POLARITY");
657 param_bool("\\SET_POLARITY");
658 param_bool("\\CLR_POLARITY");
659 port("\\CLK", 1);
660 port("\\SET", param("\\WIDTH"));
661 port("\\CLR", param("\\WIDTH"));
662 port("\\D", param("\\WIDTH"));
663 port("\\Q", param("\\WIDTH"));
664 check_expected();
665 return;
666 }
667
668 if (cell->type == "$adff") {
669 param_bool("\\CLK_POLARITY");
670 param_bool("\\ARST_POLARITY");
671 param_bits("\\ARST_VALUE", param("\\WIDTH"));
672 port("\\CLK", 1);
673 port("\\ARST", 1);
674 port("\\D", param("\\WIDTH"));
675 port("\\Q", param("\\WIDTH"));
676 check_expected();
677 return;
678 }
679
680 if (cell->type == "$dlatch") {
681 param_bool("\\EN_POLARITY");
682 port("\\EN", 1);
683 port("\\D", param("\\WIDTH"));
684 port("\\Q", param("\\WIDTH"));
685 check_expected();
686 return;
687 }
688
689 if (cell->type == "$dlatchsr") {
690 param_bool("\\EN_POLARITY");
691 param_bool("\\SET_POLARITY");
692 param_bool("\\CLR_POLARITY");
693 port("\\EN", 1);
694 port("\\SET", param("\\WIDTH"));
695 port("\\CLR", param("\\WIDTH"));
696 port("\\D", param("\\WIDTH"));
697 port("\\Q", param("\\WIDTH"));
698 check_expected();
699 return;
700 }
701
702 if (cell->type == "$fsm") {
703 param("\\NAME");
704 param_bool("\\CLK_POLARITY");
705 param_bool("\\ARST_POLARITY");
706 param("\\STATE_BITS");
707 param("\\STATE_NUM");
708 param("\\STATE_NUM_LOG2");
709 param("\\STATE_RST");
710 param_bits("\\STATE_TABLE", param("\\STATE_BITS") * param("\\STATE_NUM"));
711 param("\\TRANS_NUM");
712 param_bits("\\TRANS_TABLE", param("\\TRANS_NUM") * (2*param("\\STATE_NUM_LOG2") + param("\\CTRL_IN_WIDTH") + param("\\CTRL_OUT_WIDTH")));
713 port("\\CLK", 1);
714 port("\\ARST", 1);
715 port("\\CTRL_IN", param("\\CTRL_IN_WIDTH"));
716 port("\\CTRL_OUT", param("\\CTRL_OUT_WIDTH"));
717 check_expected();
718 return;
719 }
720
721 if (cell->type == "$memrd") {
722 param("\\MEMID");
723 param_bool("\\CLK_ENABLE");
724 param_bool("\\CLK_POLARITY");
725 param_bool("\\TRANSPARENT");
726 port("\\CLK", 1);
727 port("\\ADDR", param("\\ABITS"));
728 port("\\DATA", param("\\WIDTH"));
729 check_expected();
730 return;
731 }
732
733 if (cell->type == "$memwr") {
734 param("\\MEMID");
735 param_bool("\\CLK_ENABLE");
736 param_bool("\\CLK_POLARITY");
737 param("\\PRIORITY");
738 port("\\CLK", 1);
739 port("\\EN", param("\\WIDTH"));
740 port("\\ADDR", param("\\ABITS"));
741 port("\\DATA", param("\\WIDTH"));
742 check_expected();
743 return;
744 }
745
746 if (cell->type == "$mem") {
747 param("\\MEMID");
748 param("\\SIZE");
749 param("\\OFFSET");
750 param_bits("\\RD_CLK_ENABLE", param("\\RD_PORTS"));
751 param_bits("\\RD_CLK_POLARITY", param("\\RD_PORTS"));
752 param_bits("\\RD_TRANSPARENT", param("\\RD_PORTS"));
753 param_bits("\\WR_CLK_ENABLE", param("\\WR_PORTS"));
754 param_bits("\\WR_CLK_POLARITY", param("\\WR_PORTS"));
755 port("\\RD_CLK", param("\\RD_PORTS"));
756 port("\\RD_ADDR", param("\\RD_PORTS") * param("\\ABITS"));
757 port("\\RD_DATA", param("\\RD_PORTS") * param("\\WIDTH"));
758 port("\\WR_CLK", param("\\WR_PORTS"));
759 port("\\WR_EN", param("\\WR_PORTS") * param("\\WIDTH"));
760 port("\\WR_ADDR", param("\\WR_PORTS") * param("\\ABITS"));
761 port("\\WR_DATA", param("\\WR_PORTS") * param("\\WIDTH"));
762 check_expected();
763 return;
764 }
765
766 if (cell->type == "$assert") {
767 port("\\A", 1);
768 port("\\EN", 1);
769 check_expected();
770 return;
771 }
772
773 if (cell->type == "$_NOT_") { check_gate("AY"); return; }
774 if (cell->type == "$_AND_") { check_gate("ABY"); return; }
775 if (cell->type == "$_NAND_") { check_gate("ABY"); return; }
776 if (cell->type == "$_OR_") { check_gate("ABY"); return; }
777 if (cell->type == "$_NOR_") { check_gate("ABY"); return; }
778 if (cell->type == "$_XOR_") { check_gate("ABY"); return; }
779 if (cell->type == "$_XNOR_") { check_gate("ABY"); return; }
780 if (cell->type == "$_MUX_") { check_gate("ABSY"); return; }
781 if (cell->type == "$_AOI3_") { check_gate("ABCY"); return; }
782 if (cell->type == "$_OAI3_") { check_gate("ABCY"); return; }
783 if (cell->type == "$_AOI4_") { check_gate("ABCDY"); return; }
784 if (cell->type == "$_OAI4_") { check_gate("ABCDY"); return; }
785
786 if (cell->type == "$_SR_NN_") { check_gate("SRQ"); return; }
787 if (cell->type == "$_SR_NP_") { check_gate("SRQ"); return; }
788 if (cell->type == "$_SR_PN_") { check_gate("SRQ"); return; }
789 if (cell->type == "$_SR_PP_") { check_gate("SRQ"); return; }
790
791 if (cell->type == "$_DFF_N_") { check_gate("DQC"); return; }
792 if (cell->type == "$_DFF_P_") { check_gate("DQC"); return; }
793
794 if (cell->type == "$_DFF_NN0_") { check_gate("DQCR"); return; }
795 if (cell->type == "$_DFF_NN1_") { check_gate("DQCR"); return; }
796 if (cell->type == "$_DFF_NP0_") { check_gate("DQCR"); return; }
797 if (cell->type == "$_DFF_NP1_") { check_gate("DQCR"); return; }
798 if (cell->type == "$_DFF_PN0_") { check_gate("DQCR"); return; }
799 if (cell->type == "$_DFF_PN1_") { check_gate("DQCR"); return; }
800 if (cell->type == "$_DFF_PP0_") { check_gate("DQCR"); return; }
801 if (cell->type == "$_DFF_PP1_") { check_gate("DQCR"); return; }
802
803 if (cell->type == "$_DFFSR_NNN_") { check_gate("CSRDQ"); return; }
804 if (cell->type == "$_DFFSR_NNP_") { check_gate("CSRDQ"); return; }
805 if (cell->type == "$_DFFSR_NPN_") { check_gate("CSRDQ"); return; }
806 if (cell->type == "$_DFFSR_NPP_") { check_gate("CSRDQ"); return; }
807 if (cell->type == "$_DFFSR_PNN_") { check_gate("CSRDQ"); return; }
808 if (cell->type == "$_DFFSR_PNP_") { check_gate("CSRDQ"); return; }
809 if (cell->type == "$_DFFSR_PPN_") { check_gate("CSRDQ"); return; }
810 if (cell->type == "$_DFFSR_PPP_") { check_gate("CSRDQ"); return; }
811
812 if (cell->type == "$_DLATCH_N_") { check_gate("EDQ"); return; }
813 if (cell->type == "$_DLATCH_P_") { check_gate("EDQ"); return; }
814
815 if (cell->type == "$_DLATCHSR_NNN_") { check_gate("ESRDQ"); return; }
816 if (cell->type == "$_DLATCHSR_NNP_") { check_gate("ESRDQ"); return; }
817 if (cell->type == "$_DLATCHSR_NPN_") { check_gate("ESRDQ"); return; }
818 if (cell->type == "$_DLATCHSR_NPP_") { check_gate("ESRDQ"); return; }
819 if (cell->type == "$_DLATCHSR_PNN_") { check_gate("ESRDQ"); return; }
820 if (cell->type == "$_DLATCHSR_PNP_") { check_gate("ESRDQ"); return; }
821 if (cell->type == "$_DLATCHSR_PPN_") { check_gate("ESRDQ"); return; }
822 if (cell->type == "$_DLATCHSR_PPP_") { check_gate("ESRDQ"); return; }
823
824 error(__LINE__);
825 }
826 };
827 }
828 #endif
829
830 void RTLIL::Module::check()
831 {
832 #ifndef NDEBUG
833 std::vector<bool> ports_declared;
834 for (auto &it : wires_) {
835 log_assert(this == it.second->module);
836 log_assert(it.first == it.second->name);
837 log_assert(!it.first.empty());
838 log_assert(it.second->width >= 0);
839 log_assert(it.second->port_id >= 0);
840 for (auto &it2 : it.second->attributes)
841 log_assert(!it2.first.empty());
842 if (it.second->port_id) {
843 log_assert(SIZE(ports) >= it.second->port_id);
844 log_assert(ports.at(it.second->port_id-1) == it.first);
845 log_assert(it.second->port_input || it.second->port_output);
846 if (SIZE(ports_declared) < it.second->port_id)
847 ports_declared.resize(it.second->port_id);
848 log_assert(ports_declared[it.second->port_id-1] == false);
849 ports_declared[it.second->port_id-1] = true;
850 } else
851 log_assert(!it.second->port_input && !it.second->port_output);
852 }
853 for (auto port_declared : ports_declared)
854 log_assert(port_declared == true);
855 log_assert(SIZE(ports) == SIZE(ports_declared));
856
857 for (auto &it : memories) {
858 log_assert(it.first == it.second->name);
859 log_assert(!it.first.empty());
860 log_assert(it.second->width >= 0);
861 log_assert(it.second->size >= 0);
862 for (auto &it2 : it.second->attributes)
863 log_assert(!it2.first.empty());
864 }
865
866 for (auto &it : cells_) {
867 log_assert(this == it.second->module);
868 log_assert(it.first == it.second->name);
869 log_assert(!it.first.empty());
870 log_assert(!it.second->type.empty());
871 for (auto &it2 : it.second->connections()) {
872 log_assert(!it2.first.empty());
873 it2.second.check();
874 }
875 for (auto &it2 : it.second->attributes)
876 log_assert(!it2.first.empty());
877 for (auto &it2 : it.second->parameters)
878 log_assert(!it2.first.empty());
879 InternalCellChecker checker(this, it.second);
880 checker.check();
881 }
882
883 for (auto &it : processes) {
884 log_assert(it.first == it.second->name);
885 log_assert(!it.first.empty());
886 // FIXME: More checks here..
887 }
888
889 for (auto &it : connections_) {
890 log_assert(it.first.size() == it.second.size());
891 it.first.check();
892 it.second.check();
893 }
894
895 for (auto &it : attributes)
896 log_assert(!it.first.empty());
897 #endif
898 }
899
900 void RTLIL::Module::optimize()
901 {
902 }
903
904 void RTLIL::Module::cloneInto(RTLIL::Module *new_mod) const
905 {
906 log_assert(new_mod->refcount_wires_ == 0);
907 log_assert(new_mod->refcount_cells_ == 0);
908
909 new_mod->connections_ = connections_;
910 new_mod->attributes = attributes;
911
912 for (auto &it : wires_)
913 new_mod->addWire(it.first, it.second);
914
915 for (auto &it : memories)
916 new_mod->memories[it.first] = new RTLIL::Memory(*it.second);
917
918 for (auto &it : cells_)
919 new_mod->addCell(it.first, it.second);
920
921 for (auto &it : processes)
922 new_mod->processes[it.first] = it.second->clone();
923
924 struct RewriteSigSpecWorker
925 {
926 RTLIL::Module *mod;
927 void operator()(RTLIL::SigSpec &sig)
928 {
929 std::vector<RTLIL::SigChunk> chunks = sig.chunks();
930 for (auto &c : chunks)
931 if (c.wire != NULL)
932 c.wire = mod->wires_.at(c.wire->name);
933 sig = chunks;
934 }
935 };
936
937 RewriteSigSpecWorker rewriteSigSpecWorker;
938 rewriteSigSpecWorker.mod = new_mod;
939 new_mod->rewrite_sigspecs(rewriteSigSpecWorker);
940 new_mod->fixup_ports();
941 }
942
943 RTLIL::Module *RTLIL::Module::clone() const
944 {
945 RTLIL::Module *new_mod = new RTLIL::Module;
946 new_mod->name = name;
947 cloneInto(new_mod);
948 return new_mod;
949 }
950
951 bool RTLIL::Module::has_memories() const
952 {
953 return !memories.empty();
954 }
955
956 bool RTLIL::Module::has_processes() const
957 {
958 return !processes.empty();
959 }
960
961 bool RTLIL::Module::has_memories_warn() const
962 {
963 if (!memories.empty())
964 log("Warning: Ignoring module %s because it contains memories (run 'memory' command first).\n", log_id(this));
965 return !memories.empty();
966 }
967
968 bool RTLIL::Module::has_processes_warn() const
969 {
970 if (!processes.empty())
971 log("Warning: Ignoring module %s because it contains processes (run 'proc' command first).\n", log_id(this));
972 return !processes.empty();
973 }
974
975 std::vector<RTLIL::Wire*> RTLIL::Module::selected_wires() const
976 {
977 std::vector<RTLIL::Wire*> result;
978 result.reserve(wires_.size());
979 for (auto &it : wires_)
980 if (design->selected(this, it.second))
981 result.push_back(it.second);
982 return result;
983 }
984
985 std::vector<RTLIL::Cell*> RTLIL::Module::selected_cells() const
986 {
987 std::vector<RTLIL::Cell*> result;
988 result.reserve(wires_.size());
989 for (auto &it : cells_)
990 if (design->selected(this, it.second))
991 result.push_back(it.second);
992 return result;
993 }
994
995 void RTLIL::Module::add(RTLIL::Wire *wire)
996 {
997 log_assert(!wire->name.empty());
998 log_assert(count_id(wire->name) == 0);
999 log_assert(refcount_wires_ == 0);
1000 wires_[wire->name] = wire;
1001 wire->module = this;
1002 }
1003
1004 void RTLIL::Module::add(RTLIL::Cell *cell)
1005 {
1006 log_assert(!cell->name.empty());
1007 log_assert(count_id(cell->name) == 0);
1008 log_assert(refcount_cells_ == 0);
1009 cells_[cell->name] = cell;
1010 cell->module = this;
1011 }
1012
1013 namespace {
1014 struct DeleteWireWorker
1015 {
1016 RTLIL::Module *module;
1017 const std::set<RTLIL::Wire*> *wires_p;
1018
1019 void operator()(RTLIL::SigSpec &sig) {
1020 std::vector<RTLIL::SigChunk> chunks = sig;
1021 for (auto &c : chunks)
1022 if (c.wire != NULL && wires_p->count(c.wire)) {
1023 c.wire = module->addWire(NEW_ID, c.width);
1024 c.offset = 0;
1025 }
1026 sig = chunks;
1027 }
1028 };
1029 }
1030
1031 #if 0
1032 void RTLIL::Module::remove(RTLIL::Wire *wire)
1033 {
1034 std::setPort<RTLIL::Wire*> wires_;
1035 wires_.insert(wire);
1036 remove(wires_);
1037 }
1038 #endif
1039
1040 void RTLIL::Module::remove(const std::set<RTLIL::Wire*> &wires)
1041 {
1042 log_assert(refcount_wires_ == 0);
1043
1044 DeleteWireWorker delete_wire_worker;
1045 delete_wire_worker.module = this;
1046 delete_wire_worker.wires_p = &wires;
1047 rewrite_sigspecs(delete_wire_worker);
1048
1049 for (auto &it : wires) {
1050 log_assert(wires_.count(it->name) != 0);
1051 wires_.erase(it->name);
1052 delete it;
1053 }
1054 }
1055
1056 void RTLIL::Module::remove(RTLIL::Cell *cell)
1057 {
1058 log_assert(cells_.count(cell->name) != 0);
1059 log_assert(refcount_cells_ == 0);
1060 cells_.erase(cell->name);
1061 delete cell;
1062 }
1063
1064 void RTLIL::Module::rename(RTLIL::Wire *wire, RTLIL::IdString new_name)
1065 {
1066 log_assert(wires_[wire->name] == wire);
1067 log_assert(refcount_wires_ == 0);
1068 wires_.erase(wire->name);
1069 wire->name = new_name;
1070 add(wire);
1071 }
1072
1073 void RTLIL::Module::rename(RTLIL::Cell *cell, RTLIL::IdString new_name)
1074 {
1075 log_assert(cells_[cell->name] == cell);
1076 log_assert(refcount_wires_ == 0);
1077 cells_.erase(cell->name);
1078 cell->name = new_name;
1079 add(cell);
1080 }
1081
1082 void RTLIL::Module::rename(RTLIL::IdString old_name, RTLIL::IdString new_name)
1083 {
1084 log_assert(count_id(old_name) != 0);
1085 if (wires_.count(old_name))
1086 rename(wires_.at(old_name), new_name);
1087 else if (cells_.count(old_name))
1088 rename(cells_.at(old_name), new_name);
1089 else
1090 log_abort();
1091 }
1092
1093 void RTLIL::Module::swap_names(RTLIL::Wire *w1, RTLIL::Wire *w2)
1094 {
1095 log_assert(wires_[w1->name] == w1);
1096 log_assert(wires_[w2->name] == w2);
1097 log_assert(refcount_wires_ == 0);
1098
1099 wires_.erase(w1->name);
1100 wires_.erase(w2->name);
1101
1102 std::swap(w1->name, w2->name);
1103
1104 wires_[w1->name] = w1;
1105 wires_[w2->name] = w2;
1106 }
1107
1108 void RTLIL::Module::swap_names(RTLIL::Cell *c1, RTLIL::Cell *c2)
1109 {
1110 log_assert(cells_[c1->name] == c1);
1111 log_assert(cells_[c2->name] == c2);
1112 log_assert(refcount_cells_ == 0);
1113
1114 cells_.erase(c1->name);
1115 cells_.erase(c2->name);
1116
1117 std::swap(c1->name, c2->name);
1118
1119 cells_[c1->name] = c1;
1120 cells_[c2->name] = c2;
1121 }
1122
1123 RTLIL::IdString RTLIL::Module::uniquify(RTLIL::IdString name)
1124 {
1125 int index = 0;
1126 return uniquify(name, index);
1127 }
1128
1129 RTLIL::IdString RTLIL::Module::uniquify(RTLIL::IdString name, int &index)
1130 {
1131 if (index == 0) {
1132 if (count_id(name) == 0)
1133 return name;
1134 index++;
1135 }
1136
1137 while (1) {
1138 RTLIL::IdString new_name = stringf("%s_%d", name.c_str(), index);
1139 if (count_id(new_name) == 0)
1140 return new_name;
1141 index++;
1142 }
1143 }
1144
1145 static bool fixup_ports_compare(const RTLIL::Wire *a, const RTLIL::Wire *b)
1146 {
1147 if (a->port_id && !b->port_id)
1148 return true;
1149 if (!a->port_id && b->port_id)
1150 return false;
1151
1152 if (a->port_id == b->port_id)
1153 return a->name < b->name;
1154 return a->port_id < b->port_id;
1155 }
1156
1157 void RTLIL::Module::connect(const RTLIL::SigSig &conn)
1158 {
1159 for (auto mon : monitors)
1160 mon->notify_connect(this, conn);
1161
1162 if (design)
1163 for (auto mon : design->monitors)
1164 mon->notify_connect(this, conn);
1165
1166 connections_.push_back(conn);
1167 }
1168
1169 void RTLIL::Module::connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs)
1170 {
1171 connect(RTLIL::SigSig(lhs, rhs));
1172 }
1173
1174 void RTLIL::Module::new_connections(const std::vector<RTLIL::SigSig> &new_conn)
1175 {
1176 for (auto mon : monitors)
1177 mon->notify_connect(this, new_conn);
1178
1179 if (design)
1180 for (auto mon : design->monitors)
1181 mon->notify_connect(this, new_conn);
1182
1183 connections_ = new_conn;
1184 }
1185
1186 const std::vector<RTLIL::SigSig> &RTLIL::Module::connections() const
1187 {
1188 return connections_;
1189 }
1190
1191 void RTLIL::Module::fixup_ports()
1192 {
1193 std::vector<RTLIL::Wire*> all_ports;
1194
1195 for (auto &w : wires_)
1196 if (w.second->port_input || w.second->port_output)
1197 all_ports.push_back(w.second);
1198 else
1199 w.second->port_id = 0;
1200
1201 std::sort(all_ports.begin(), all_ports.end(), fixup_ports_compare);
1202
1203 ports.clear();
1204 for (size_t i = 0; i < all_ports.size(); i++) {
1205 ports.push_back(all_ports[i]->name);
1206 all_ports[i]->port_id = i+1;
1207 }
1208 }
1209
1210 RTLIL::Wire *RTLIL::Module::addWire(RTLIL::IdString name, int width)
1211 {
1212 RTLIL::Wire *wire = new RTLIL::Wire;
1213 wire->name = name;
1214 wire->width = width;
1215 add(wire);
1216 return wire;
1217 }
1218
1219 RTLIL::Wire *RTLIL::Module::addWire(RTLIL::IdString name, const RTLIL::Wire *other)
1220 {
1221 RTLIL::Wire *wire = addWire(name);
1222 wire->width = other->width;
1223 wire->start_offset = other->start_offset;
1224 wire->port_id = other->port_id;
1225 wire->port_input = other->port_input;
1226 wire->port_output = other->port_output;
1227 wire->upto = other->upto;
1228 wire->attributes = other->attributes;
1229 return wire;
1230 }
1231
1232 RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, RTLIL::IdString type)
1233 {
1234 RTLIL::Cell *cell = new RTLIL::Cell;
1235 cell->name = name;
1236 cell->type = type;
1237 add(cell);
1238 return cell;
1239 }
1240
1241 RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, const RTLIL::Cell *other)
1242 {
1243 RTLIL::Cell *cell = addCell(name, other->type);
1244 cell->connections_ = other->connections_;
1245 cell->parameters = other->parameters;
1246 cell->attributes = other->attributes;
1247 return cell;
1248 }
1249
1250 #define DEF_METHOD(_func, _y_size, _type) \
1251 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed) { \
1252 RTLIL::Cell *cell = addCell(name, _type); \
1253 cell->parameters["\\A_SIGNED"] = is_signed; \
1254 cell->parameters["\\A_WIDTH"] = sig_a.size(); \
1255 cell->parameters["\\Y_WIDTH"] = sig_y.size(); \
1256 cell->setPort("\\A", sig_a); \
1257 cell->setPort("\\Y", sig_y); \
1258 return cell; \
1259 } \
1260 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed) { \
1261 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
1262 add ## _func(name, sig_a, sig_y, is_signed); \
1263 return sig_y; \
1264 }
1265 DEF_METHOD(Not, sig_a.size(), "$not")
1266 DEF_METHOD(Pos, sig_a.size(), "$pos")
1267 DEF_METHOD(Bu0, sig_a.size(), "$bu0")
1268 DEF_METHOD(Neg, sig_a.size(), "$neg")
1269 DEF_METHOD(ReduceAnd, 1, "$reduce_and")
1270 DEF_METHOD(ReduceOr, 1, "$reduce_or")
1271 DEF_METHOD(ReduceXor, 1, "$reduce_xor")
1272 DEF_METHOD(ReduceXnor, 1, "$reduce_xnor")
1273 DEF_METHOD(ReduceBool, 1, "$reduce_bool")
1274 DEF_METHOD(LogicNot, 1, "$logic_not")
1275 #undef DEF_METHOD
1276
1277 #define DEF_METHOD(_func, _y_size, _type) \
1278 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed) { \
1279 RTLIL::Cell *cell = addCell(name, _type); \
1280 cell->parameters["\\A_SIGNED"] = is_signed; \
1281 cell->parameters["\\B_SIGNED"] = is_signed; \
1282 cell->parameters["\\A_WIDTH"] = sig_a.size(); \
1283 cell->parameters["\\B_WIDTH"] = sig_b.size(); \
1284 cell->parameters["\\Y_WIDTH"] = sig_y.size(); \
1285 cell->setPort("\\A", sig_a); \
1286 cell->setPort("\\B", sig_b); \
1287 cell->setPort("\\Y", sig_y); \
1288 return cell; \
1289 } \
1290 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed) { \
1291 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
1292 add ## _func(name, sig_a, sig_b, sig_y, is_signed); \
1293 return sig_y; \
1294 }
1295 DEF_METHOD(And, std::max(sig_a.size(), sig_b.size()), "$and")
1296 DEF_METHOD(Or, std::max(sig_a.size(), sig_b.size()), "$or")
1297 DEF_METHOD(Xor, std::max(sig_a.size(), sig_b.size()), "$xor")
1298 DEF_METHOD(Xnor, std::max(sig_a.size(), sig_b.size()), "$xnor")
1299 DEF_METHOD(Shl, sig_a.size(), "$shl")
1300 DEF_METHOD(Shr, sig_a.size(), "$shr")
1301 DEF_METHOD(Sshl, sig_a.size(), "$sshl")
1302 DEF_METHOD(Sshr, sig_a.size(), "$sshr")
1303 DEF_METHOD(Shift, sig_a.size(), "$shift")
1304 DEF_METHOD(Shiftx, sig_a.size(), "$shiftx")
1305 DEF_METHOD(Lt, 1, "$lt")
1306 DEF_METHOD(Le, 1, "$le")
1307 DEF_METHOD(Eq, 1, "$eq")
1308 DEF_METHOD(Ne, 1, "$ne")
1309 DEF_METHOD(Eqx, 1, "$eqx")
1310 DEF_METHOD(Nex, 1, "$nex")
1311 DEF_METHOD(Ge, 1, "$ge")
1312 DEF_METHOD(Gt, 1, "$gt")
1313 DEF_METHOD(Add, std::max(sig_a.size(), sig_b.size()), "$add")
1314 DEF_METHOD(Sub, std::max(sig_a.size(), sig_b.size()), "$sub")
1315 DEF_METHOD(Mul, std::max(sig_a.size(), sig_b.size()), "$mul")
1316 DEF_METHOD(Div, std::max(sig_a.size(), sig_b.size()), "$div")
1317 DEF_METHOD(Mod, std::max(sig_a.size(), sig_b.size()), "$mod")
1318 DEF_METHOD(LogicAnd, 1, "$logic_and")
1319 DEF_METHOD(LogicOr, 1, "$logic_or")
1320 #undef DEF_METHOD
1321
1322 #define DEF_METHOD(_func, _type, _pmux) \
1323 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, RTLIL::SigSpec sig_y) { \
1324 RTLIL::Cell *cell = addCell(name, _type); \
1325 cell->parameters["\\WIDTH"] = sig_a.size(); \
1326 if (_pmux) cell->parameters["\\S_WIDTH"] = sig_s.size(); \
1327 cell->setPort("\\A", sig_a); \
1328 cell->setPort("\\B", sig_b); \
1329 cell->setPort("\\S", sig_s); \
1330 cell->setPort("\\Y", sig_y); \
1331 return cell; \
1332 } \
1333 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s) { \
1334 RTLIL::SigSpec sig_y = addWire(NEW_ID, sig_a.size()); \
1335 add ## _func(name, sig_a, sig_b, sig_s, sig_y); \
1336 return sig_y; \
1337 }
1338 DEF_METHOD(Mux, "$mux", 0)
1339 DEF_METHOD(Pmux, "$pmux", 1)
1340 #undef DEF_METHOD
1341
1342 #define DEF_METHOD_2(_func, _type, _P1, _P2) \
1343 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2) { \
1344 RTLIL::Cell *cell = addCell(name, _type); \
1345 cell->setPort("\\" #_P1, sig1); \
1346 cell->setPort("\\" #_P2, sig2); \
1347 return cell; \
1348 } \
1349 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1) { \
1350 RTLIL::SigBit sig2 = addWire(NEW_ID); \
1351 add ## _func(name, sig1, sig2); \
1352 return sig2; \
1353 }
1354 #define DEF_METHOD_3(_func, _type, _P1, _P2, _P3) \
1355 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3) { \
1356 RTLIL::Cell *cell = addCell(name, _type); \
1357 cell->setPort("\\" #_P1, sig1); \
1358 cell->setPort("\\" #_P2, sig2); \
1359 cell->setPort("\\" #_P3, sig3); \
1360 return cell; \
1361 } \
1362 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2) { \
1363 RTLIL::SigBit sig3 = addWire(NEW_ID); \
1364 add ## _func(name, sig1, sig2, sig3); \
1365 return sig3; \
1366 }
1367 #define DEF_METHOD_4(_func, _type, _P1, _P2, _P3, _P4) \
1368 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, RTLIL::SigBit sig4) { \
1369 RTLIL::Cell *cell = addCell(name, _type); \
1370 cell->setPort("\\" #_P1, sig1); \
1371 cell->setPort("\\" #_P2, sig2); \
1372 cell->setPort("\\" #_P3, sig3); \
1373 cell->setPort("\\" #_P4, sig4); \
1374 return cell; \
1375 } \
1376 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3) { \
1377 RTLIL::SigBit sig4 = addWire(NEW_ID); \
1378 add ## _func(name, sig1, sig2, sig3, sig4); \
1379 return sig4; \
1380 }
1381 #define DEF_METHOD_5(_func, _type, _P1, _P2, _P3, _P4, _P5) \
1382 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, RTLIL::SigBit sig4, RTLIL::SigBit sig5) { \
1383 RTLIL::Cell *cell = addCell(name, _type); \
1384 cell->setPort("\\" #_P1, sig1); \
1385 cell->setPort("\\" #_P2, sig2); \
1386 cell->setPort("\\" #_P3, sig3); \
1387 cell->setPort("\\" #_P4, sig4); \
1388 cell->setPort("\\" #_P5, sig5); \
1389 return cell; \
1390 } \
1391 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, RTLIL::SigBit sig4) { \
1392 RTLIL::SigBit sig5 = addWire(NEW_ID); \
1393 add ## _func(name, sig1, sig2, sig3, sig4, sig5); \
1394 return sig5; \
1395 }
1396 DEF_METHOD_2(NotGate, "$_NOT_", A, Y)
1397 DEF_METHOD_3(AndGate, "$_AND_", A, B, Y)
1398 DEF_METHOD_3(NandGate, "$_NAND_", A, B, Y)
1399 DEF_METHOD_3(OrGate, "$_OR_", A, B, Y)
1400 DEF_METHOD_3(NorGate, "$_NOR_", A, B, Y)
1401 DEF_METHOD_3(XorGate, "$_XOR_", A, B, Y)
1402 DEF_METHOD_3(XnorGate, "$_XNOR_", A, B, Y)
1403 DEF_METHOD_4(MuxGate, "$_MUX_", A, B, S, Y)
1404 DEF_METHOD_4(Aoi3Gate, "$_AOI3_", A, B, C, Y)
1405 DEF_METHOD_4(Oai3Gate, "$_OAI3_", A, B, C, Y)
1406 DEF_METHOD_5(Aoi4Gate, "$_AOI4_", A, B, C, D, Y)
1407 DEF_METHOD_5(Oai4Gate, "$_OAI4_", A, B, C, D, Y)
1408 #undef DEF_METHOD_2
1409 #undef DEF_METHOD_3
1410 #undef DEF_METHOD_4
1411 #undef DEF_METHOD_5
1412
1413 RTLIL::Cell* RTLIL::Module::addPow(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool a_signed, bool b_signed)
1414 {
1415 RTLIL::Cell *cell = addCell(name, "$pow");
1416 cell->parameters["\\A_SIGNED"] = a_signed;
1417 cell->parameters["\\B_SIGNED"] = b_signed;
1418 cell->parameters["\\A_WIDTH"] = sig_a.size();
1419 cell->parameters["\\B_WIDTH"] = sig_b.size();
1420 cell->parameters["\\Y_WIDTH"] = sig_y.size();
1421 cell->setPort("\\A", sig_a);
1422 cell->setPort("\\B", sig_b);
1423 cell->setPort("\\Y", sig_y);
1424 return cell;
1425 }
1426
1427 RTLIL::Cell* RTLIL::Module::addSlice(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, RTLIL::Const offset)
1428 {
1429 RTLIL::Cell *cell = addCell(name, "$slice");
1430 cell->parameters["\\A_WIDTH"] = sig_a.size();
1431 cell->parameters["\\Y_WIDTH"] = sig_y.size();
1432 cell->parameters["\\OFFSET"] = offset;
1433 cell->setPort("\\A", sig_a);
1434 cell->setPort("\\Y", sig_y);
1435 return cell;
1436 }
1437
1438 RTLIL::Cell* RTLIL::Module::addConcat(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y)
1439 {
1440 RTLIL::Cell *cell = addCell(name, "$concat");
1441 cell->parameters["\\A_WIDTH"] = sig_a.size();
1442 cell->parameters["\\B_WIDTH"] = sig_b.size();
1443 cell->setPort("\\A", sig_a);
1444 cell->setPort("\\B", sig_b);
1445 cell->setPort("\\Y", sig_y);
1446 return cell;
1447 }
1448
1449 RTLIL::Cell* RTLIL::Module::addLut(RTLIL::IdString name, RTLIL::SigSpec sig_i, RTLIL::SigSpec sig_o, RTLIL::Const lut)
1450 {
1451 RTLIL::Cell *cell = addCell(name, "$lut");
1452 cell->parameters["\\LUT"] = lut;
1453 cell->parameters["\\WIDTH"] = sig_i.size();
1454 cell->setPort("\\A", sig_i);
1455 cell->setPort("\\Y", sig_o);
1456 return cell;
1457 }
1458
1459 RTLIL::Cell* RTLIL::Module::addAssert(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en)
1460 {
1461 RTLIL::Cell *cell = addCell(name, "$assert");
1462 cell->setPort("\\A", sig_a);
1463 cell->setPort("\\EN", sig_en);
1464 return cell;
1465 }
1466
1467 RTLIL::Cell* RTLIL::Module::addSr(RTLIL::IdString name, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr, RTLIL::SigSpec sig_q, bool set_polarity, bool clr_polarity)
1468 {
1469 RTLIL::Cell *cell = addCell(name, "$sr");
1470 cell->parameters["\\SET_POLARITY"] = set_polarity;
1471 cell->parameters["\\CLR_POLARITY"] = clr_polarity;
1472 cell->parameters["\\WIDTH"] = sig_q.size();
1473 cell->setPort("\\SET", sig_set);
1474 cell->setPort("\\CLR", sig_clr);
1475 cell->setPort("\\Q", sig_q);
1476 return cell;
1477 }
1478
1479 RTLIL::Cell* RTLIL::Module::addDff(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity)
1480 {
1481 RTLIL::Cell *cell = addCell(name, "$dff");
1482 cell->parameters["\\CLK_POLARITY"] = clk_polarity;
1483 cell->parameters["\\WIDTH"] = sig_q.size();
1484 cell->setPort("\\CLK", sig_clk);
1485 cell->setPort("\\D", sig_d);
1486 cell->setPort("\\Q", sig_q);
1487 return cell;
1488 }
1489
1490 RTLIL::Cell* RTLIL::Module::addDffsr(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
1491 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity)
1492 {
1493 RTLIL::Cell *cell = addCell(name, "$dffsr");
1494 cell->parameters["\\CLK_POLARITY"] = clk_polarity;
1495 cell->parameters["\\SET_POLARITY"] = set_polarity;
1496 cell->parameters["\\CLR_POLARITY"] = clr_polarity;
1497 cell->parameters["\\WIDTH"] = sig_q.size();
1498 cell->setPort("\\CLK", sig_clk);
1499 cell->setPort("\\SET", sig_set);
1500 cell->setPort("\\CLR", sig_clr);
1501 cell->setPort("\\D", sig_d);
1502 cell->setPort("\\Q", sig_q);
1503 return cell;
1504 }
1505
1506 RTLIL::Cell* RTLIL::Module::addAdff(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_arst, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q,
1507 RTLIL::Const arst_value, bool clk_polarity, bool arst_polarity)
1508 {
1509 RTLIL::Cell *cell = addCell(name, "$adff");
1510 cell->parameters["\\CLK_POLARITY"] = clk_polarity;
1511 cell->parameters["\\ARST_POLARITY"] = arst_polarity;
1512 cell->parameters["\\ARST_VALUE"] = arst_value;
1513 cell->parameters["\\WIDTH"] = sig_q.size();
1514 cell->setPort("\\CLK", sig_clk);
1515 cell->setPort("\\ARST", sig_arst);
1516 cell->setPort("\\D", sig_d);
1517 cell->setPort("\\Q", sig_q);
1518 return cell;
1519 }
1520
1521 RTLIL::Cell* RTLIL::Module::addDlatch(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity)
1522 {
1523 RTLIL::Cell *cell = addCell(name, "$dlatch");
1524 cell->parameters["\\EN_POLARITY"] = en_polarity;
1525 cell->parameters["\\WIDTH"] = sig_q.size();
1526 cell->setPort("\\EN", sig_en);
1527 cell->setPort("\\D", sig_d);
1528 cell->setPort("\\Q", sig_q);
1529 return cell;
1530 }
1531
1532 RTLIL::Cell* RTLIL::Module::addDlatchsr(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
1533 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity, bool set_polarity, bool clr_polarity)
1534 {
1535 RTLIL::Cell *cell = addCell(name, "$dlatchsr");
1536 cell->parameters["\\EN_POLARITY"] = en_polarity;
1537 cell->parameters["\\SET_POLARITY"] = set_polarity;
1538 cell->parameters["\\CLR_POLARITY"] = clr_polarity;
1539 cell->parameters["\\WIDTH"] = sig_q.size();
1540 cell->setPort("\\EN", sig_en);
1541 cell->setPort("\\SET", sig_set);
1542 cell->setPort("\\CLR", sig_clr);
1543 cell->setPort("\\D", sig_d);
1544 cell->setPort("\\Q", sig_q);
1545 return cell;
1546 }
1547
1548 RTLIL::Cell* RTLIL::Module::addDffGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity)
1549 {
1550 RTLIL::Cell *cell = addCell(name, stringf("$_DFF_%c_", clk_polarity ? 'P' : 'N'));
1551 cell->setPort("\\C", sig_clk);
1552 cell->setPort("\\D", sig_d);
1553 cell->setPort("\\Q", sig_q);
1554 return cell;
1555 }
1556
1557 RTLIL::Cell* RTLIL::Module::addDffsrGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
1558 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity)
1559 {
1560 RTLIL::Cell *cell = addCell(name, stringf("$_DFFSR_%c%c%c_", clk_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N'));
1561 cell->setPort("\\C", sig_clk);
1562 cell->setPort("\\S", sig_set);
1563 cell->setPort("\\R", sig_clr);
1564 cell->setPort("\\D", sig_d);
1565 cell->setPort("\\Q", sig_q);
1566 return cell;
1567 }
1568
1569 RTLIL::Cell* RTLIL::Module::addAdffGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_arst, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q,
1570 bool arst_value, bool clk_polarity, bool arst_polarity)
1571 {
1572 RTLIL::Cell *cell = addCell(name, stringf("$_DFF_%c%c%c_", clk_polarity ? 'P' : 'N', arst_polarity ? 'P' : 'N', arst_value ? '1' : '0'));
1573 cell->setPort("\\C", sig_clk);
1574 cell->setPort("\\R", sig_arst);
1575 cell->setPort("\\D", sig_d);
1576 cell->setPort("\\Q", sig_q);
1577 return cell;
1578 }
1579
1580 RTLIL::Cell* RTLIL::Module::addDlatchGate(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity)
1581 {
1582 RTLIL::Cell *cell = addCell(name, stringf("$_DLATCH_%c_", en_polarity ? 'P' : 'N'));
1583 cell->setPort("\\E", sig_en);
1584 cell->setPort("\\D", sig_d);
1585 cell->setPort("\\Q", sig_q);
1586 return cell;
1587 }
1588
1589 RTLIL::Cell* RTLIL::Module::addDlatchsrGate(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
1590 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity, bool set_polarity, bool clr_polarity)
1591 {
1592 RTLIL::Cell *cell = addCell(name, stringf("$_DLATCHSR_%c%c%c_", en_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N'));
1593 cell->setPort("\\E", sig_en);
1594 cell->setPort("\\S", sig_set);
1595 cell->setPort("\\R", sig_clr);
1596 cell->setPort("\\D", sig_d);
1597 cell->setPort("\\Q", sig_q);
1598 return cell;
1599 }
1600
1601
1602 RTLIL::Wire::Wire()
1603 {
1604 module = nullptr;
1605 width = 1;
1606 start_offset = 0;
1607 port_id = 0;
1608 port_input = false;
1609 port_output = false;
1610 upto = false;
1611 }
1612
1613 RTLIL::Memory::Memory()
1614 {
1615 width = 1;
1616 size = 0;
1617 }
1618
1619 RTLIL::Cell::Cell() : module(nullptr)
1620 {
1621 }
1622
1623 bool RTLIL::Cell::hasPort(RTLIL::IdString portname) const
1624 {
1625 return connections_.count(portname) != 0;
1626 }
1627
1628 void RTLIL::Cell::unsetPort(RTLIL::IdString portname)
1629 {
1630 RTLIL::SigSpec signal;
1631 auto conn_it = connections_.find(portname);
1632
1633 if (conn_it != connections_.end())
1634 {
1635 for (auto mon : module->monitors)
1636 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
1637
1638 if (module->design)
1639 for (auto mon : module->design->monitors)
1640 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
1641
1642 connections_.erase(conn_it);
1643 }
1644 }
1645
1646 void RTLIL::Cell::setPort(RTLIL::IdString portname, RTLIL::SigSpec signal)
1647 {
1648 auto conn_it = connections_.find(portname);
1649
1650 if (conn_it == connections_.end()) {
1651 connections_[portname] = RTLIL::SigSpec();
1652 conn_it = connections_.find(portname);
1653 log_assert(conn_it != connections_.end());
1654 }
1655
1656 for (auto mon : module->monitors)
1657 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
1658
1659 if (module->design)
1660 for (auto mon : module->design->monitors)
1661 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
1662
1663 conn_it->second = signal;
1664 }
1665
1666 const RTLIL::SigSpec &RTLIL::Cell::getPort(RTLIL::IdString portname) const
1667 {
1668 return connections_.at(portname);
1669 }
1670
1671 const std::map<RTLIL::IdString, RTLIL::SigSpec> &RTLIL::Cell::connections() const
1672 {
1673 return connections_;
1674 }
1675
1676 bool RTLIL::Cell::hasParam(RTLIL::IdString paramname) const
1677 {
1678 return parameters.count(paramname);
1679 }
1680
1681 void RTLIL::Cell::unsetParam(RTLIL::IdString paramname)
1682 {
1683 parameters.erase(paramname);
1684 }
1685
1686 void RTLIL::Cell::setParam(RTLIL::IdString paramname, RTLIL::Const value)
1687 {
1688 parameters[paramname] = value;
1689 }
1690
1691 const RTLIL::Const &RTLIL::Cell::getParam(RTLIL::IdString paramname) const
1692 {
1693 return parameters.at(paramname);
1694 }
1695
1696 void RTLIL::Cell::check()
1697 {
1698 #ifndef NDEBUG
1699 InternalCellChecker checker(NULL, this);
1700 checker.check();
1701 #endif
1702 }
1703
1704 void RTLIL::Cell::fixup_parameters(bool set_a_signed, bool set_b_signed)
1705 {
1706 if (type.substr(0, 1) != "$" || type.substr(0, 2) == "$_" || type.substr(0, 8) == "$paramod" ||
1707 type.substr(0, 9) == "$verific$" || type.substr(0, 7) == "$array:" || type.substr(0, 8) == "$extern:")
1708 return;
1709
1710 if (type == "$mux" || type == "$pmux")
1711 {
1712 parameters["\\WIDTH"] = SIZE(connections_["\\Y"]);
1713 if (type == "$pmux")
1714 parameters["\\S_WIDTH"] = SIZE(connections_["\\S"]);
1715 check();
1716 return;
1717 }
1718
1719 bool signedness_ab = type != "$slice" && type != "$concat";
1720
1721 if (connections_.count("\\A")) {
1722 if (signedness_ab) {
1723 if (set_a_signed)
1724 parameters["\\A_SIGNED"] = true;
1725 else if (parameters.count("\\A_SIGNED") == 0)
1726 parameters["\\A_SIGNED"] = false;
1727 }
1728 parameters["\\A_WIDTH"] = SIZE(connections_["\\A"]);
1729 }
1730
1731 if (connections_.count("\\B")) {
1732 if (signedness_ab) {
1733 if (set_b_signed)
1734 parameters["\\B_SIGNED"] = true;
1735 else if (parameters.count("\\B_SIGNED") == 0)
1736 parameters["\\B_SIGNED"] = false;
1737 }
1738 parameters["\\B_WIDTH"] = SIZE(connections_["\\B"]);
1739 }
1740
1741 if (connections_.count("\\Y"))
1742 parameters["\\Y_WIDTH"] = SIZE(connections_["\\Y"]);
1743
1744 check();
1745 }
1746
1747 RTLIL::SigChunk::SigChunk()
1748 {
1749 wire = NULL;
1750 width = 0;
1751 offset = 0;
1752 }
1753
1754 RTLIL::SigChunk::SigChunk(const RTLIL::Const &value)
1755 {
1756 wire = NULL;
1757 data = value;
1758 width = data.bits.size();
1759 offset = 0;
1760 }
1761
1762 RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire)
1763 {
1764 log_assert(wire != nullptr);
1765 this->wire = wire;
1766 this->width = wire->width;
1767 this->offset = 0;
1768 }
1769
1770 RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire, int offset, int width)
1771 {
1772 log_assert(wire != nullptr);
1773 this->wire = wire;
1774 this->width = width;
1775 this->offset = offset;
1776 }
1777
1778 RTLIL::SigChunk::SigChunk(const std::string &str)
1779 {
1780 wire = NULL;
1781 data = RTLIL::Const(str);
1782 width = data.bits.size();
1783 offset = 0;
1784 }
1785
1786 RTLIL::SigChunk::SigChunk(int val, int width)
1787 {
1788 wire = NULL;
1789 data = RTLIL::Const(val, width);
1790 this->width = data.bits.size();
1791 offset = 0;
1792 }
1793
1794 RTLIL::SigChunk::SigChunk(RTLIL::State bit, int width)
1795 {
1796 wire = NULL;
1797 data = RTLIL::Const(bit, width);
1798 this->width = data.bits.size();
1799 offset = 0;
1800 }
1801
1802 RTLIL::SigChunk::SigChunk(RTLIL::SigBit bit)
1803 {
1804 wire = bit.wire;
1805 offset = 0;
1806 if (wire == NULL)
1807 data = RTLIL::Const(bit.data);
1808 else
1809 offset = bit.offset;
1810 width = 1;
1811 }
1812
1813 RTLIL::SigChunk RTLIL::SigChunk::extract(int offset, int length) const
1814 {
1815 RTLIL::SigChunk ret;
1816 if (wire) {
1817 ret.wire = wire;
1818 ret.offset = this->offset + offset;
1819 ret.width = length;
1820 } else {
1821 for (int i = 0; i < length; i++)
1822 ret.data.bits.push_back(data.bits[offset+i]);
1823 ret.width = length;
1824 }
1825 return ret;
1826 }
1827
1828 bool RTLIL::SigChunk::operator <(const RTLIL::SigChunk &other) const
1829 {
1830 if (wire && other.wire)
1831 if (wire->name != other.wire->name)
1832 return wire->name < other.wire->name;
1833
1834 if (wire != other.wire)
1835 return wire < other.wire;
1836
1837 if (offset != other.offset)
1838 return offset < other.offset;
1839
1840 if (width != other.width)
1841 return width < other.width;
1842
1843 return data.bits < other.data.bits;
1844 }
1845
1846 bool RTLIL::SigChunk::operator ==(const RTLIL::SigChunk &other) const
1847 {
1848 if (wire != other.wire || width != other.width || offset != other.offset)
1849 return false;
1850 if (data.bits != other.data.bits)
1851 return false;
1852 return true;
1853 }
1854
1855 bool RTLIL::SigChunk::operator !=(const RTLIL::SigChunk &other) const
1856 {
1857 if (*this == other)
1858 return false;
1859 return true;
1860 }
1861
1862 RTLIL::SigSpec::SigSpec()
1863 {
1864 width_ = 0;
1865 hash_ = 0;
1866 }
1867
1868 RTLIL::SigSpec::SigSpec(const RTLIL::SigSpec &other)
1869 {
1870 *this = other;
1871 }
1872
1873 RTLIL::SigSpec::SigSpec(std::initializer_list<RTLIL::SigSpec> parts)
1874 {
1875 cover("kernel.rtlil.sigspec.init.list");
1876
1877 width_ = 0;
1878 hash_ = 0;
1879
1880 std::vector<RTLIL::SigSpec> parts_vec(parts.begin(), parts.end());
1881 for (auto it = parts_vec.rbegin(); it != parts_vec.rend(); it++)
1882 append(*it);
1883 }
1884
1885 const RTLIL::SigSpec &RTLIL::SigSpec::operator=(const RTLIL::SigSpec &other)
1886 {
1887 cover("kernel.rtlil.sigspec.assign");
1888
1889 width_ = other.width_;
1890 hash_ = other.hash_;
1891 chunks_ = other.chunks_;
1892 bits_.clear();
1893
1894 if (!other.bits_.empty())
1895 {
1896 RTLIL::SigChunk *last = NULL;
1897 int last_end_offset = 0;
1898
1899 for (auto &bit : other.bits_) {
1900 if (last && bit.wire == last->wire) {
1901 if (bit.wire == NULL) {
1902 last->data.bits.push_back(bit.data);
1903 last->width++;
1904 continue;
1905 } else if (last_end_offset == bit.offset) {
1906 last_end_offset++;
1907 last->width++;
1908 continue;
1909 }
1910 }
1911 chunks_.push_back(bit);
1912 last = &chunks_.back();
1913 last_end_offset = bit.offset + 1;
1914 }
1915
1916 check();
1917 }
1918
1919 return *this;
1920 }
1921
1922 RTLIL::SigSpec::SigSpec(const RTLIL::Const &value)
1923 {
1924 cover("kernel.rtlil.sigspec.init.const");
1925
1926 chunks_.push_back(RTLIL::SigChunk(value));
1927 width_ = chunks_.back().width;
1928 hash_ = 0;
1929 check();
1930 }
1931
1932 RTLIL::SigSpec::SigSpec(const RTLIL::SigChunk &chunk)
1933 {
1934 cover("kernel.rtlil.sigspec.init.chunk");
1935
1936 chunks_.push_back(chunk);
1937 width_ = chunks_.back().width;
1938 hash_ = 0;
1939 check();
1940 }
1941
1942 RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire)
1943 {
1944 cover("kernel.rtlil.sigspec.init.wire");
1945
1946 chunks_.push_back(RTLIL::SigChunk(wire));
1947 width_ = chunks_.back().width;
1948 hash_ = 0;
1949 check();
1950 }
1951
1952 RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire, int offset, int width)
1953 {
1954 cover("kernel.rtlil.sigspec.init.wire_part");
1955
1956 chunks_.push_back(RTLIL::SigChunk(wire, offset, width));
1957 width_ = chunks_.back().width;
1958 hash_ = 0;
1959 check();
1960 }
1961
1962 RTLIL::SigSpec::SigSpec(const std::string &str)
1963 {
1964 cover("kernel.rtlil.sigspec.init.str");
1965
1966 chunks_.push_back(RTLIL::SigChunk(str));
1967 width_ = chunks_.back().width;
1968 hash_ = 0;
1969 check();
1970 }
1971
1972 RTLIL::SigSpec::SigSpec(int val, int width)
1973 {
1974 cover("kernel.rtlil.sigspec.init.int");
1975
1976 chunks_.push_back(RTLIL::SigChunk(val, width));
1977 width_ = width;
1978 hash_ = 0;
1979 check();
1980 }
1981
1982 RTLIL::SigSpec::SigSpec(RTLIL::State bit, int width)
1983 {
1984 cover("kernel.rtlil.sigspec.init.state");
1985
1986 chunks_.push_back(RTLIL::SigChunk(bit, width));
1987 width_ = width;
1988 hash_ = 0;
1989 check();
1990 }
1991
1992 RTLIL::SigSpec::SigSpec(RTLIL::SigBit bit, int width)
1993 {
1994 cover("kernel.rtlil.sigspec.init.bit");
1995
1996 if (bit.wire == NULL)
1997 chunks_.push_back(RTLIL::SigChunk(bit.data, width));
1998 else
1999 for (int i = 0; i < width; i++)
2000 chunks_.push_back(bit);
2001 width_ = width;
2002 hash_ = 0;
2003 check();
2004 }
2005
2006 RTLIL::SigSpec::SigSpec(std::vector<RTLIL::SigChunk> chunks)
2007 {
2008 cover("kernel.rtlil.sigspec.init.stdvec_chunks");
2009
2010 width_ = 0;
2011 hash_ = 0;
2012 for (auto &c : chunks)
2013 append(c);
2014 check();
2015 }
2016
2017 RTLIL::SigSpec::SigSpec(std::vector<RTLIL::SigBit> bits)
2018 {
2019 cover("kernel.rtlil.sigspec.init.stdvec_bits");
2020
2021 width_ = 0;
2022 hash_ = 0;
2023 for (auto &bit : bits)
2024 append_bit(bit);
2025 check();
2026 }
2027
2028 RTLIL::SigSpec::SigSpec(std::set<RTLIL::SigBit> bits)
2029 {
2030 cover("kernel.rtlil.sigspec.init.stdset_bits");
2031
2032 width_ = 0;
2033 hash_ = 0;
2034 for (auto &bit : bits)
2035 append_bit(bit);
2036 check();
2037 }
2038
2039 void RTLIL::SigSpec::pack() const
2040 {
2041 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
2042
2043 if (that->bits_.empty())
2044 return;
2045
2046 cover("kernel.rtlil.sigspec.convert.pack");
2047 log_assert(that->chunks_.empty());
2048
2049 std::vector<RTLIL::SigBit> old_bits;
2050 old_bits.swap(that->bits_);
2051
2052 RTLIL::SigChunk *last = NULL;
2053 int last_end_offset = 0;
2054
2055 for (auto &bit : old_bits) {
2056 if (last && bit.wire == last->wire) {
2057 if (bit.wire == NULL) {
2058 last->data.bits.push_back(bit.data);
2059 last->width++;
2060 continue;
2061 } else if (last_end_offset == bit.offset) {
2062 last_end_offset++;
2063 last->width++;
2064 continue;
2065 }
2066 }
2067 that->chunks_.push_back(bit);
2068 last = &that->chunks_.back();
2069 last_end_offset = bit.offset + 1;
2070 }
2071
2072 check();
2073 }
2074
2075 void RTLIL::SigSpec::unpack() const
2076 {
2077 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
2078
2079 if (that->chunks_.empty())
2080 return;
2081
2082 cover("kernel.rtlil.sigspec.convert.unpack");
2083 log_assert(that->bits_.empty());
2084
2085 that->bits_.reserve(that->width_);
2086 for (auto &c : that->chunks_)
2087 for (int i = 0; i < c.width; i++)
2088 that->bits_.push_back(RTLIL::SigBit(c, i));
2089
2090 that->chunks_.clear();
2091 that->hash_ = 0;
2092 }
2093
2094 #define DJB2(_hash, _value) do { (_hash) = (((_hash) << 5) + (_hash)) + (_value); } while (0)
2095
2096 void RTLIL::SigSpec::hash() const
2097 {
2098 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
2099
2100 if (that->hash_ != 0)
2101 return;
2102
2103 cover("kernel.rtlil.sigspec.hash");
2104 that->pack();
2105
2106 that->hash_ = 5381;
2107 for (auto &c : that->chunks_)
2108 if (c.wire == NULL) {
2109 for (auto &v : c.data.bits)
2110 DJB2(that->hash_, v);
2111 } else {
2112 DJB2(that->hash_, c.wire->name.index_);
2113 DJB2(that->hash_, c.offset);
2114 DJB2(that->hash_, c.width);
2115 }
2116
2117 if (that->hash_ == 0)
2118 that->hash_ = 1;
2119 }
2120
2121 void RTLIL::SigSpec::sort()
2122 {
2123 unpack();
2124 cover("kernel.rtlil.sigspec.sort");
2125 std::sort(bits_.begin(), bits_.end());
2126 }
2127
2128 void RTLIL::SigSpec::sort_and_unify()
2129 {
2130 cover("kernel.rtlil.sigspec.sort_and_unify");
2131 *this = this->to_sigbit_set();
2132 }
2133
2134 void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with)
2135 {
2136 replace(pattern, with, this);
2137 }
2138
2139 void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with, RTLIL::SigSpec *other) const
2140 {
2141 log_assert(pattern.width_ == with.width_);
2142
2143 pattern.unpack();
2144 with.unpack();
2145
2146 std::map<RTLIL::SigBit, RTLIL::SigBit> rules;
2147
2148 for (int i = 0; i < SIZE(pattern.bits_); i++)
2149 if (pattern.bits_[i].wire != NULL)
2150 rules[pattern.bits_[i]] = with.bits_[i];
2151
2152 replace(rules, other);
2153 }
2154
2155 void RTLIL::SigSpec::replace(const std::map<RTLIL::SigBit, RTLIL::SigBit> &rules)
2156 {
2157 replace(rules, this);
2158 }
2159
2160 void RTLIL::SigSpec::replace(const std::map<RTLIL::SigBit, RTLIL::SigBit> &rules, RTLIL::SigSpec *other) const
2161 {
2162 cover("kernel.rtlil.sigspec.replace");
2163
2164 log_assert(other != NULL);
2165 log_assert(width_ == other->width_);
2166
2167 unpack();
2168 other->unpack();
2169
2170 for (int i = 0; i < SIZE(bits_); i++) {
2171 auto it = rules.find(bits_[i]);
2172 if (it != rules.end())
2173 other->bits_[i] = it->second;
2174 }
2175
2176 other->check();
2177 }
2178
2179 void RTLIL::SigSpec::remove(const RTLIL::SigSpec &pattern)
2180 {
2181 remove2(pattern, NULL);
2182 }
2183
2184 void RTLIL::SigSpec::remove(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other) const
2185 {
2186 RTLIL::SigSpec tmp = *this;
2187 tmp.remove2(pattern, other);
2188 }
2189
2190 void RTLIL::SigSpec::remove2(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other)
2191 {
2192 std::set<RTLIL::SigBit> pattern_bits = pattern.to_sigbit_set();
2193 remove2(pattern_bits, other);
2194 }
2195
2196 void RTLIL::SigSpec::remove(const std::set<RTLIL::SigBit> &pattern)
2197 {
2198 remove2(pattern, NULL);
2199 }
2200
2201 void RTLIL::SigSpec::remove(const std::set<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other) const
2202 {
2203 RTLIL::SigSpec tmp = *this;
2204 tmp.remove2(pattern, other);
2205 }
2206
2207 void RTLIL::SigSpec::remove2(const std::set<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other)
2208 {
2209 if (other)
2210 cover("kernel.rtlil.sigspec.remove_other");
2211 else
2212 cover("kernel.rtlil.sigspec.remove");
2213
2214 unpack();
2215
2216 if (other != NULL) {
2217 log_assert(width_ == other->width_);
2218 other->unpack();
2219 }
2220
2221 std::vector<RTLIL::SigBit> new_bits, new_other_bits;
2222
2223 new_bits.resize(SIZE(bits_));
2224 if (other != NULL)
2225 new_other_bits.resize(SIZE(bits_));
2226
2227 int k = 0;
2228 for (int i = 0; i < SIZE(bits_); i++) {
2229 if (bits_[i].wire != NULL && pattern.count(bits_[i]))
2230 continue;
2231 if (other != NULL)
2232 new_other_bits[k] = other->bits_[i];
2233 new_bits[k++] = bits_[i];
2234 }
2235
2236 new_bits.resize(k);
2237 if (other != NULL)
2238 new_other_bits.resize(k);
2239
2240 bits_.swap(new_bits);
2241 width_ = SIZE(bits_);
2242
2243 if (other != NULL) {
2244 other->bits_.swap(new_other_bits);
2245 other->width_ = SIZE(other->bits_);
2246 }
2247
2248 check();
2249 }
2250
2251 RTLIL::SigSpec RTLIL::SigSpec::extract(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec *other) const
2252 {
2253 std::set<RTLIL::SigBit> pattern_bits = pattern.to_sigbit_set();
2254 return extract(pattern_bits, other);
2255 }
2256
2257 RTLIL::SigSpec RTLIL::SigSpec::extract(const std::set<RTLIL::SigBit> &pattern, const RTLIL::SigSpec *other) const
2258 {
2259 if (other)
2260 cover("kernel.rtlil.sigspec.extract_other");
2261 else
2262 cover("kernel.rtlil.sigspec.extract");
2263
2264 log_assert(other == NULL || width_ == other->width_);
2265
2266 std::vector<RTLIL::SigBit> bits_match = to_sigbit_vector();
2267 RTLIL::SigSpec ret;
2268
2269 if (other) {
2270 std::vector<RTLIL::SigBit> bits_other = other->to_sigbit_vector();
2271 for (int i = 0; i < width_; i++)
2272 if (bits_match[i].wire && pattern.count(bits_match[i]))
2273 ret.append_bit(bits_other[i]);
2274 } else {
2275 for (int i = 0; i < width_; i++)
2276 if (bits_match[i].wire && pattern.count(bits_match[i]))
2277 ret.append_bit(bits_match[i]);
2278 }
2279
2280 ret.check();
2281 return ret;
2282 }
2283
2284 void RTLIL::SigSpec::replace(int offset, const RTLIL::SigSpec &with)
2285 {
2286 cover("kernel.rtlil.sigspec.replace_pos");
2287
2288 unpack();
2289 with.unpack();
2290
2291 log_assert(offset >= 0);
2292 log_assert(with.width_ >= 0);
2293 log_assert(offset+with.width_ <= width_);
2294
2295 for (int i = 0; i < with.width_; i++)
2296 bits_.at(offset + i) = with.bits_.at(i);
2297
2298 check();
2299 }
2300
2301 void RTLIL::SigSpec::remove_const()
2302 {
2303 if (packed())
2304 {
2305 cover("kernel.rtlil.sigspec.remove_const.packed");
2306
2307 std::vector<RTLIL::SigChunk> new_chunks;
2308 new_chunks.reserve(SIZE(chunks_));
2309
2310 width_ = 0;
2311 for (auto &chunk : chunks_)
2312 if (chunk.wire != NULL) {
2313 new_chunks.push_back(chunk);
2314 width_ += chunk.width;
2315 }
2316
2317 chunks_.swap(new_chunks);
2318 }
2319 else
2320 {
2321 cover("kernel.rtlil.sigspec.remove_const.unpacked");
2322
2323 std::vector<RTLIL::SigBit> new_bits;
2324 new_bits.reserve(width_);
2325
2326 for (auto &bit : bits_)
2327 if (bit.wire != NULL)
2328 new_bits.push_back(bit);
2329
2330 bits_.swap(new_bits);
2331 width_ = bits_.size();
2332 }
2333
2334 check();
2335 }
2336
2337 void RTLIL::SigSpec::remove(int offset, int length)
2338 {
2339 cover("kernel.rtlil.sigspec.remove_pos");
2340
2341 unpack();
2342
2343 log_assert(offset >= 0);
2344 log_assert(length >= 0);
2345 log_assert(offset + length <= width_);
2346
2347 bits_.erase(bits_.begin() + offset, bits_.begin() + offset + length);
2348 width_ = bits_.size();
2349
2350 check();
2351 }
2352
2353 RTLIL::SigSpec RTLIL::SigSpec::extract(int offset, int length) const
2354 {
2355 unpack();
2356 cover("kernel.rtlil.sigspec.extract_pos");
2357 return std::vector<RTLIL::SigBit>(bits_.begin() + offset, bits_.begin() + offset + length);
2358 }
2359
2360 void RTLIL::SigSpec::append(const RTLIL::SigSpec &signal)
2361 {
2362 if (signal.width_ == 0)
2363 return;
2364
2365 if (width_ == 0) {
2366 *this = signal;
2367 return;
2368 }
2369
2370 cover("kernel.rtlil.sigspec.append");
2371
2372 if (packed() != signal.packed()) {
2373 pack();
2374 signal.pack();
2375 }
2376
2377 if (packed())
2378 for (auto &other_c : signal.chunks_)
2379 {
2380 auto &my_last_c = chunks_.back();
2381 if (my_last_c.wire == NULL && other_c.wire == NULL) {
2382 auto &this_data = my_last_c.data.bits;
2383 auto &other_data = other_c.data.bits;
2384 this_data.insert(this_data.end(), other_data.begin(), other_data.end());
2385 my_last_c.width += other_c.width;
2386 } else
2387 if (my_last_c.wire == other_c.wire && my_last_c.offset + my_last_c.width == other_c.offset) {
2388 my_last_c.width += other_c.width;
2389 } else
2390 chunks_.push_back(other_c);
2391 }
2392 else
2393 bits_.insert(bits_.end(), signal.bits_.begin(), signal.bits_.end());
2394
2395 width_ += signal.width_;
2396 check();
2397 }
2398
2399 void RTLIL::SigSpec::append_bit(const RTLIL::SigBit &bit)
2400 {
2401 if (packed())
2402 {
2403 cover("kernel.rtlil.sigspec.append_bit.packed");
2404
2405 if (chunks_.size() == 0)
2406 chunks_.push_back(bit);
2407 else
2408 if (bit.wire == NULL)
2409 if (chunks_.back().wire == NULL) {
2410 chunks_.back().data.bits.push_back(bit.data);
2411 chunks_.back().width++;
2412 } else
2413 chunks_.push_back(bit);
2414 else
2415 if (chunks_.back().wire == bit.wire && chunks_.back().offset + chunks_.back().width == bit.offset)
2416 chunks_.back().width++;
2417 else
2418 chunks_.push_back(bit);
2419 }
2420 else
2421 {
2422 cover("kernel.rtlil.sigspec.append_bit.unpacked");
2423 bits_.push_back(bit);
2424 }
2425
2426 width_++;
2427 check();
2428 }
2429
2430 void RTLIL::SigSpec::extend(int width, bool is_signed)
2431 {
2432 cover("kernel.rtlil.sigspec.extend");
2433
2434 pack();
2435
2436 if (width_ > width)
2437 remove(width, width_ - width);
2438
2439 if (width_ < width) {
2440 RTLIL::SigSpec padding = width_ > 0 ? extract(width_ - 1, 1) : RTLIL::SigSpec(RTLIL::State::S0);
2441 if (!is_signed && padding != RTLIL::SigSpec(RTLIL::State::Sx) && padding != RTLIL::SigSpec(RTLIL::State::Sz) &&
2442 padding != RTLIL::SigSpec(RTLIL::State::Sa) && padding != RTLIL::SigSpec(RTLIL::State::Sm))
2443 padding = RTLIL::SigSpec(RTLIL::State::S0);
2444 while (width_ < width)
2445 append(padding);
2446 }
2447 }
2448
2449 void RTLIL::SigSpec::extend_u0(int width, bool is_signed)
2450 {
2451 cover("kernel.rtlil.sigspec.extend_u0");
2452
2453 pack();
2454
2455 if (width_ > width)
2456 remove(width, width_ - width);
2457
2458 if (width_ < width) {
2459 RTLIL::SigSpec padding = width_ > 0 ? extract(width_ - 1, 1) : RTLIL::SigSpec(RTLIL::State::S0);
2460 if (!is_signed)
2461 padding = RTLIL::SigSpec(RTLIL::State::S0);
2462 while (width_ < width)
2463 append(padding);
2464 }
2465
2466 }
2467
2468 RTLIL::SigSpec RTLIL::SigSpec::repeat(int num) const
2469 {
2470 cover("kernel.rtlil.sigspec.repeat");
2471
2472 RTLIL::SigSpec sig;
2473 for (int i = 0; i < num; i++)
2474 sig.append(*this);
2475 return sig;
2476 }
2477
2478 #ifndef NDEBUG
2479 void RTLIL::SigSpec::check() const
2480 {
2481 if (width_ > 64)
2482 {
2483 cover("kernel.rtlil.sigspec.check.skip");
2484 }
2485 else if (packed())
2486 {
2487 cover("kernel.rtlil.sigspec.check.packed");
2488
2489 int w = 0;
2490 for (size_t i = 0; i < chunks_.size(); i++) {
2491 const RTLIL::SigChunk chunk = chunks_[i];
2492 if (chunk.wire == NULL) {
2493 if (i > 0)
2494 log_assert(chunks_[i-1].wire != NULL);
2495 log_assert(chunk.offset == 0);
2496 log_assert(chunk.data.bits.size() == (size_t)chunk.width);
2497 } else {
2498 if (i > 0 && chunks_[i-1].wire == chunk.wire)
2499 log_assert(chunk.offset != chunks_[i-1].offset + chunks_[i-1].width);
2500 log_assert(chunk.offset >= 0);
2501 log_assert(chunk.width >= 0);
2502 log_assert(chunk.offset + chunk.width <= chunk.wire->width);
2503 log_assert(chunk.data.bits.size() == 0);
2504 }
2505 w += chunk.width;
2506 }
2507 log_assert(w == width_);
2508 log_assert(bits_.empty());
2509 }
2510 else
2511 {
2512 cover("kernel.rtlil.sigspec.check.unpacked");
2513
2514 log_assert(width_ == SIZE(bits_));
2515 log_assert(chunks_.empty());
2516 }
2517 }
2518 #endif
2519
2520 bool RTLIL::SigSpec::operator <(const RTLIL::SigSpec &other) const
2521 {
2522 cover("kernel.rtlil.sigspec.comp_lt");
2523
2524 if (this == &other)
2525 return false;
2526
2527 if (width_ != other.width_)
2528 return width_ < other.width_;
2529
2530 pack();
2531 other.pack();
2532
2533 if (chunks_.size() != other.chunks_.size())
2534 return chunks_.size() < other.chunks_.size();
2535
2536 hash();
2537 other.hash();
2538
2539 if (hash_ != other.hash_)
2540 return hash_ < other.hash_;
2541
2542 for (size_t i = 0; i < chunks_.size(); i++)
2543 if (chunks_[i] != other.chunks_[i]) {
2544 cover("kernel.rtlil.sigspec.comp_lt.hash_collision");
2545 return chunks_[i] < other.chunks_[i];
2546 }
2547
2548 cover("kernel.rtlil.sigspec.comp_lt.equal");
2549 return false;
2550 }
2551
2552 bool RTLIL::SigSpec::operator ==(const RTLIL::SigSpec &other) const
2553 {
2554 cover("kernel.rtlil.sigspec.comp_eq");
2555
2556 if (this == &other)
2557 return true;
2558
2559 if (width_ != other.width_)
2560 return false;
2561
2562 pack();
2563 other.pack();
2564
2565 if (chunks_.size() != chunks_.size())
2566 return false;
2567
2568 hash();
2569 other.hash();
2570
2571 if (hash_ != other.hash_)
2572 return false;
2573
2574 for (size_t i = 0; i < chunks_.size(); i++)
2575 if (chunks_[i] != other.chunks_[i]) {
2576 cover("kernel.rtlil.sigspec.comp_eq.hash_collision");
2577 return false;
2578 }
2579
2580 cover("kernel.rtlil.sigspec.comp_eq.equal");
2581 return true;
2582 }
2583
2584 bool RTLIL::SigSpec::is_wire() const
2585 {
2586 cover("kernel.rtlil.sigspec.is_wire");
2587
2588 pack();
2589 return SIZE(chunks_) == 1 && chunks_[0].wire && chunks_[0].wire->width == width_;
2590 }
2591
2592 bool RTLIL::SigSpec::is_chunk() const
2593 {
2594 cover("kernel.rtlil.sigspec.is_chunk");
2595
2596 pack();
2597 return SIZE(chunks_) == 1;
2598 }
2599
2600 bool RTLIL::SigSpec::is_fully_const() const
2601 {
2602 cover("kernel.rtlil.sigspec.is_fully_const");
2603
2604 pack();
2605 for (auto it = chunks_.begin(); it != chunks_.end(); it++)
2606 if (it->width > 0 && it->wire != NULL)
2607 return false;
2608 return true;
2609 }
2610
2611 bool RTLIL::SigSpec::is_fully_def() const
2612 {
2613 cover("kernel.rtlil.sigspec.is_fully_def");
2614
2615 pack();
2616 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
2617 if (it->width > 0 && it->wire != NULL)
2618 return false;
2619 for (size_t i = 0; i < it->data.bits.size(); i++)
2620 if (it->data.bits[i] != RTLIL::State::S0 && it->data.bits[i] != RTLIL::State::S1)
2621 return false;
2622 }
2623 return true;
2624 }
2625
2626 bool RTLIL::SigSpec::is_fully_undef() const
2627 {
2628 cover("kernel.rtlil.sigspec.is_fully_undef");
2629
2630 pack();
2631 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
2632 if (it->width > 0 && it->wire != NULL)
2633 return false;
2634 for (size_t i = 0; i < it->data.bits.size(); i++)
2635 if (it->data.bits[i] != RTLIL::State::Sx && it->data.bits[i] != RTLIL::State::Sz)
2636 return false;
2637 }
2638 return true;
2639 }
2640
2641 bool RTLIL::SigSpec::has_marked_bits() const
2642 {
2643 cover("kernel.rtlil.sigspec.has_marked_bits");
2644
2645 pack();
2646 for (auto it = chunks_.begin(); it != chunks_.end(); it++)
2647 if (it->width > 0 && it->wire == NULL) {
2648 for (size_t i = 0; i < it->data.bits.size(); i++)
2649 if (it->data.bits[i] == RTLIL::State::Sm)
2650 return true;
2651 }
2652 return false;
2653 }
2654
2655 bool RTLIL::SigSpec::as_bool() const
2656 {
2657 cover("kernel.rtlil.sigspec.as_bool");
2658
2659 pack();
2660 log_assert(is_fully_const() && SIZE(chunks_) <= 1);
2661 if (width_)
2662 return chunks_[0].data.as_bool();
2663 return false;
2664 }
2665
2666 int RTLIL::SigSpec::as_int(bool is_signed) const
2667 {
2668 cover("kernel.rtlil.sigspec.as_int");
2669
2670 pack();
2671 log_assert(is_fully_const() && SIZE(chunks_) <= 1);
2672 if (width_)
2673 return chunks_[0].data.as_int(is_signed);
2674 return 0;
2675 }
2676
2677 std::string RTLIL::SigSpec::as_string() const
2678 {
2679 cover("kernel.rtlil.sigspec.as_string");
2680
2681 pack();
2682 std::string str;
2683 for (size_t i = chunks_.size(); i > 0; i--) {
2684 const RTLIL::SigChunk &chunk = chunks_[i-1];
2685 if (chunk.wire != NULL)
2686 for (int j = 0; j < chunk.width; j++)
2687 str += "?";
2688 else
2689 str += chunk.data.as_string();
2690 }
2691 return str;
2692 }
2693
2694 RTLIL::Const RTLIL::SigSpec::as_const() const
2695 {
2696 cover("kernel.rtlil.sigspec.as_const");
2697
2698 pack();
2699 log_assert(is_fully_const() && SIZE(chunks_) <= 1);
2700 if (width_)
2701 return chunks_[0].data;
2702 return RTLIL::Const();
2703 }
2704
2705 RTLIL::Wire *RTLIL::SigSpec::as_wire() const
2706 {
2707 cover("kernel.rtlil.sigspec.as_wire");
2708
2709 pack();
2710 log_assert(is_wire());
2711 return chunks_[0].wire;
2712 }
2713
2714 RTLIL::SigChunk RTLIL::SigSpec::as_chunk() const
2715 {
2716 cover("kernel.rtlil.sigspec.as_chunk");
2717
2718 pack();
2719 log_assert(is_chunk());
2720 return chunks_[0];
2721 }
2722
2723 bool RTLIL::SigSpec::match(std::string pattern) const
2724 {
2725 cover("kernel.rtlil.sigspec.match");
2726
2727 pack();
2728 std::string str = as_string();
2729 log_assert(pattern.size() == str.size());
2730
2731 for (size_t i = 0; i < pattern.size(); i++) {
2732 if (pattern[i] == ' ')
2733 continue;
2734 if (pattern[i] == '*') {
2735 if (str[i] != 'z' && str[i] != 'x')
2736 return false;
2737 continue;
2738 }
2739 if (pattern[i] != str[i])
2740 return false;
2741 }
2742
2743 return true;
2744 }
2745
2746 std::set<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_set() const
2747 {
2748 cover("kernel.rtlil.sigspec.to_sigbit_set");
2749
2750 pack();
2751 std::set<RTLIL::SigBit> sigbits;
2752 for (auto &c : chunks_)
2753 for (int i = 0; i < c.width; i++)
2754 sigbits.insert(RTLIL::SigBit(c, i));
2755 return sigbits;
2756 }
2757
2758 std::vector<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_vector() const
2759 {
2760 cover("kernel.rtlil.sigspec.to_sigbit_vector");
2761
2762 unpack();
2763 return bits_;
2764 }
2765
2766 std::map<RTLIL::SigBit, RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_map(const RTLIL::SigSpec &other) const
2767 {
2768 cover("kernel.rtlil.sigspec.to_sigbit_map");
2769
2770 unpack();
2771 other.unpack();
2772
2773 log_assert(width_ == other.width_);
2774
2775 std::map<RTLIL::SigBit, RTLIL::SigBit> new_map;
2776 for (int i = 0; i < width_; i++)
2777 new_map[bits_[i]] = other.bits_[i];
2778
2779 return new_map;
2780 }
2781
2782 RTLIL::SigBit RTLIL::SigSpec::to_single_sigbit() const
2783 {
2784 cover("kernel.rtlil.sigspec.to_single_sigbit");
2785
2786 pack();
2787 log_assert(width_ == 1);
2788 for (auto &c : chunks_)
2789 if (c.width)
2790 return RTLIL::SigBit(c);
2791 log_abort();
2792 }
2793
2794 static void sigspec_parse_split(std::vector<std::string> &tokens, const std::string &text, char sep)
2795 {
2796 size_t start = 0, end = 0;
2797 while ((end = text.find(sep, start)) != std::string::npos) {
2798 tokens.push_back(text.substr(start, end - start));
2799 start = end + 1;
2800 }
2801 tokens.push_back(text.substr(start));
2802 }
2803
2804 static int sigspec_parse_get_dummy_line_num()
2805 {
2806 return 0;
2807 }
2808
2809 bool RTLIL::SigSpec::parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str)
2810 {
2811 cover("kernel.rtlil.sigspec.parse");
2812
2813 std::vector<std::string> tokens;
2814 sigspec_parse_split(tokens, str, ',');
2815
2816 sig = RTLIL::SigSpec();
2817 for (int tokidx = int(tokens.size())-1; tokidx >= 0; tokidx--)
2818 {
2819 std::string netname = tokens[tokidx];
2820 std::string indices;
2821
2822 if (netname.size() == 0)
2823 continue;
2824
2825 if ('0' <= netname[0] && netname[0] <= '9') {
2826 cover("kernel.rtlil.sigspec.parse.const");
2827 AST::get_line_num = sigspec_parse_get_dummy_line_num;
2828 AST::AstNode *ast = VERILOG_FRONTEND::const2ast(netname);
2829 if (ast == NULL)
2830 return false;
2831 sig.append(RTLIL::Const(ast->bits));
2832 delete ast;
2833 continue;
2834 }
2835
2836 if (module == NULL)
2837 return false;
2838
2839 cover("kernel.rtlil.sigspec.parse.net");
2840
2841 if (netname[0] != '$' && netname[0] != '\\')
2842 netname = "\\" + netname;
2843
2844 if (module->wires_.count(netname) == 0) {
2845 size_t indices_pos = netname.size()-1;
2846 if (indices_pos > 2 && netname[indices_pos] == ']')
2847 {
2848 indices_pos--;
2849 while (indices_pos > 0 && ('0' <= netname[indices_pos] && netname[indices_pos] <= '9')) indices_pos--;
2850 if (indices_pos > 0 && netname[indices_pos] == ':') {
2851 indices_pos--;
2852 while (indices_pos > 0 && ('0' <= netname[indices_pos] && netname[indices_pos] <= '9')) indices_pos--;
2853 }
2854 if (indices_pos > 0 && netname[indices_pos] == '[') {
2855 indices = netname.substr(indices_pos);
2856 netname = netname.substr(0, indices_pos);
2857 }
2858 }
2859 }
2860
2861 if (module->wires_.count(netname) == 0)
2862 return false;
2863
2864 RTLIL::Wire *wire = module->wires_.at(netname);
2865 if (!indices.empty()) {
2866 std::vector<std::string> index_tokens;
2867 sigspec_parse_split(index_tokens, indices.substr(1, indices.size()-2), ':');
2868 if (index_tokens.size() == 1) {
2869 cover("kernel.rtlil.sigspec.parse.bit_sel");
2870 sig.append(RTLIL::SigSpec(wire, atoi(index_tokens.at(0).c_str())));
2871 } else {
2872 cover("kernel.rtlil.sigspec.parse.part_sel");
2873 int a = atoi(index_tokens.at(0).c_str());
2874 int b = atoi(index_tokens.at(1).c_str());
2875 if (a > b) {
2876 int tmp = a;
2877 a = b, b = tmp;
2878 }
2879 sig.append(RTLIL::SigSpec(wire, a, b-a+1));
2880 }
2881 } else
2882 sig.append(wire);
2883 }
2884
2885 return true;
2886 }
2887
2888 bool RTLIL::SigSpec::parse_sel(RTLIL::SigSpec &sig, RTLIL::Design *design, RTLIL::Module *module, std::string str)
2889 {
2890 if (str.empty() || str[0] != '@')
2891 return parse(sig, module, str);
2892
2893 cover("kernel.rtlil.sigspec.parse.sel");
2894
2895 str = RTLIL::escape_id(str.substr(1));
2896 if (design->selection_vars.count(str) == 0)
2897 return false;
2898
2899 sig = RTLIL::SigSpec();
2900 RTLIL::Selection &sel = design->selection_vars.at(str);
2901 for (auto &it : module->wires_)
2902 if (sel.selected_member(module->name, it.first))
2903 sig.append(it.second);
2904
2905 return true;
2906 }
2907
2908 bool RTLIL::SigSpec::parse_rhs(const RTLIL::SigSpec &lhs, RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str)
2909 {
2910 if (str == "0") {
2911 cover("kernel.rtlil.sigspec.parse.rhs_zeros");
2912 sig = RTLIL::SigSpec(RTLIL::State::S0, lhs.width_);
2913 return true;
2914 }
2915
2916 if (str == "~0") {
2917 cover("kernel.rtlil.sigspec.parse.rhs_ones");
2918 sig = RTLIL::SigSpec(RTLIL::State::S1, lhs.width_);
2919 return true;
2920 }
2921
2922 if (lhs.chunks_.size() == 1) {
2923 char *p = (char*)str.c_str(), *endptr;
2924 long long int val = strtoll(p, &endptr, 10);
2925 if (endptr && endptr != p && *endptr == 0) {
2926 sig = RTLIL::SigSpec(val, lhs.width_);
2927 cover("kernel.rtlil.sigspec.parse.rhs_dec");
2928 return true;
2929 }
2930 }
2931
2932 return parse(sig, module, str);
2933 }
2934
2935 RTLIL::CaseRule::~CaseRule()
2936 {
2937 for (auto it = switches.begin(); it != switches.end(); it++)
2938 delete *it;
2939 }
2940
2941 RTLIL::CaseRule *RTLIL::CaseRule::clone() const
2942 {
2943 RTLIL::CaseRule *new_caserule = new RTLIL::CaseRule;
2944 new_caserule->compare = compare;
2945 new_caserule->actions = actions;
2946 for (auto &it : switches)
2947 new_caserule->switches.push_back(it->clone());
2948 return new_caserule;
2949 }
2950
2951 RTLIL::SwitchRule::~SwitchRule()
2952 {
2953 for (auto it = cases.begin(); it != cases.end(); it++)
2954 delete *it;
2955 }
2956
2957 RTLIL::SwitchRule *RTLIL::SwitchRule::clone() const
2958 {
2959 RTLIL::SwitchRule *new_switchrule = new RTLIL::SwitchRule;
2960 new_switchrule->signal = signal;
2961 new_switchrule->attributes = attributes;
2962 for (auto &it : cases)
2963 new_switchrule->cases.push_back(it->clone());
2964 return new_switchrule;
2965
2966 }
2967
2968 RTLIL::SyncRule *RTLIL::SyncRule::clone() const
2969 {
2970 RTLIL::SyncRule *new_syncrule = new RTLIL::SyncRule;
2971 new_syncrule->type = type;
2972 new_syncrule->signal = signal;
2973 new_syncrule->actions = actions;
2974 return new_syncrule;
2975 }
2976
2977 RTLIL::Process::~Process()
2978 {
2979 for (auto it = syncs.begin(); it != syncs.end(); it++)
2980 delete *it;
2981 }
2982
2983 RTLIL::Process *RTLIL::Process::clone() const
2984 {
2985 RTLIL::Process *new_proc = new RTLIL::Process;
2986
2987 new_proc->name = name;
2988 new_proc->attributes = attributes;
2989
2990 RTLIL::CaseRule *rc_ptr = root_case.clone();
2991 new_proc->root_case = *rc_ptr;
2992 rc_ptr->switches.clear();
2993 delete rc_ptr;
2994
2995 for (auto &it : syncs)
2996 new_proc->syncs.push_back(it->clone());
2997
2998 return new_proc;
2999 }
3000
3001 YOSYS_NAMESPACE_END
3002