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Added RTLIL::SigSpec::remove_const() handling of packed SigSpecs
[yosys.git] / kernel / rtlil.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 #include "kernel/compatibility.h"
21 #include "kernel/rtlil.h"
22 #include "kernel/log.h"
23 #include "frontends/verilog/verilog_frontend.h"
24 #include "backends/ilang/ilang_backend.h"
25
26 #include <assert.h>
27 #include <string.h>
28 #include <algorithm>
29
30 int RTLIL::autoidx = 1;
31
32 RTLIL::Const::Const()
33 {
34 flags = RTLIL::CONST_FLAG_NONE;
35 }
36
37 RTLIL::Const::Const(std::string str)
38 {
39 flags = RTLIL::CONST_FLAG_STRING;
40 for (int i = str.size()-1; i >= 0; i--) {
41 unsigned char ch = str[i];
42 for (int j = 0; j < 8; j++) {
43 bits.push_back((ch & 1) != 0 ? RTLIL::S1 : RTLIL::S0);
44 ch = ch >> 1;
45 }
46 }
47 }
48
49 RTLIL::Const::Const(int val, int width)
50 {
51 flags = RTLIL::CONST_FLAG_NONE;
52 for (int i = 0; i < width; i++) {
53 bits.push_back((val & 1) != 0 ? RTLIL::S1 : RTLIL::S0);
54 val = val >> 1;
55 }
56 }
57
58 RTLIL::Const::Const(RTLIL::State bit, int width)
59 {
60 flags = RTLIL::CONST_FLAG_NONE;
61 for (int i = 0; i < width; i++)
62 bits.push_back(bit);
63 }
64
65 bool RTLIL::Const::operator <(const RTLIL::Const &other) const
66 {
67 if (bits.size() != other.bits.size())
68 return bits.size() < other.bits.size();
69 for (size_t i = 0; i < bits.size(); i++)
70 if (bits[i] != other.bits[i])
71 return bits[i] < other.bits[i];
72 return false;
73 }
74
75 bool RTLIL::Const::operator ==(const RTLIL::Const &other) const
76 {
77 return bits == other.bits;
78 }
79
80 bool RTLIL::Const::operator !=(const RTLIL::Const &other) const
81 {
82 return bits != other.bits;
83 }
84
85 bool RTLIL::Const::as_bool() const
86 {
87 for (size_t i = 0; i < bits.size(); i++)
88 if (bits[i] == RTLIL::S1)
89 return true;
90 return false;
91 }
92
93 int RTLIL::Const::as_int() const
94 {
95 int ret = 0;
96 for (size_t i = 0; i < bits.size() && i < 32; i++)
97 if (bits[i] == RTLIL::S1)
98 ret |= 1 << i;
99 return ret;
100 }
101
102 std::string RTLIL::Const::as_string() const
103 {
104 std::string ret;
105 for (size_t i = bits.size(); i > 0; i--)
106 switch (bits[i-1]) {
107 case S0: ret += "0"; break;
108 case S1: ret += "1"; break;
109 case Sx: ret += "x"; break;
110 case Sz: ret += "z"; break;
111 case Sa: ret += "-"; break;
112 case Sm: ret += "m"; break;
113 }
114 return ret;
115 }
116
117 std::string RTLIL::Const::decode_string() const
118 {
119 std::string string;
120 std::vector <char> string_chars;
121 for (int i = 0; i < int (bits.size()); i += 8) {
122 char ch = 0;
123 for (int j = 0; j < 8 && i + j < int (bits.size()); j++)
124 if (bits[i + j] == RTLIL::State::S1)
125 ch |= 1 << j;
126 if (ch != 0)
127 string_chars.push_back(ch);
128 }
129 for (int i = int (string_chars.size()) - 1; i >= 0; i--)
130 string += string_chars[i];
131 return string;
132 }
133
134 bool RTLIL::Selection::selected_module(RTLIL::IdString mod_name) const
135 {
136 if (full_selection)
137 return true;
138 if (selected_modules.count(mod_name) > 0)
139 return true;
140 if (selected_members.count(mod_name) > 0)
141 return true;
142 return false;
143 }
144
145 bool RTLIL::Selection::selected_whole_module(RTLIL::IdString mod_name) const
146 {
147 if (full_selection)
148 return true;
149 if (selected_modules.count(mod_name) > 0)
150 return true;
151 return false;
152 }
153
154 bool RTLIL::Selection::selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const
155 {
156 if (full_selection)
157 return true;
158 if (selected_modules.count(mod_name) > 0)
159 return true;
160 if (selected_members.count(mod_name) > 0)
161 if (selected_members.at(mod_name).count(memb_name) > 0)
162 return true;
163 return false;
164 }
165
166 void RTLIL::Selection::optimize(RTLIL::Design *design)
167 {
168 if (full_selection) {
169 selected_modules.clear();
170 selected_members.clear();
171 return;
172 }
173
174 std::vector<RTLIL::IdString> del_list, add_list;
175
176 del_list.clear();
177 for (auto mod_name : selected_modules) {
178 if (design->modules_.count(mod_name) == 0)
179 del_list.push_back(mod_name);
180 selected_members.erase(mod_name);
181 }
182 for (auto mod_name : del_list)
183 selected_modules.erase(mod_name);
184
185 del_list.clear();
186 for (auto &it : selected_members)
187 if (design->modules_.count(it.first) == 0)
188 del_list.push_back(it.first);
189 for (auto mod_name : del_list)
190 selected_members.erase(mod_name);
191
192 for (auto &it : selected_members) {
193 del_list.clear();
194 for (auto memb_name : it.second)
195 if (design->modules_[it.first]->count_id(memb_name) == 0)
196 del_list.push_back(memb_name);
197 for (auto memb_name : del_list)
198 it.second.erase(memb_name);
199 }
200
201 del_list.clear();
202 add_list.clear();
203 for (auto &it : selected_members)
204 if (it.second.size() == 0)
205 del_list.push_back(it.first);
206 else if (it.second.size() == design->modules_[it.first]->wires_.size() + design->modules_[it.first]->memories.size() +
207 design->modules_[it.first]->cells_.size() + design->modules_[it.first]->processes.size())
208 add_list.push_back(it.first);
209 for (auto mod_name : del_list)
210 selected_members.erase(mod_name);
211 for (auto mod_name : add_list) {
212 selected_members.erase(mod_name);
213 selected_modules.insert(mod_name);
214 }
215
216 if (selected_modules.size() == design->modules_.size()) {
217 full_selection = true;
218 selected_modules.clear();
219 selected_members.clear();
220 }
221 }
222
223 RTLIL::Design::~Design()
224 {
225 for (auto it = modules_.begin(); it != modules_.end(); it++)
226 delete it->second;
227 }
228
229 void RTLIL::Design::check()
230 {
231 #ifndef NDEBUG
232 for (auto &it : modules_) {
233 assert(it.first == it.second->name);
234 assert(it.first.size() > 0 && (it.first[0] == '\\' || it.first[0] == '$'));
235 it.second->check();
236 }
237 #endif
238 }
239
240 void RTLIL::Design::optimize()
241 {
242 for (auto &it : modules_)
243 it.second->optimize();
244 for (auto &it : selection_stack)
245 it.optimize(this);
246 for (auto &it : selection_vars)
247 it.second.optimize(this);
248 }
249
250 bool RTLIL::Design::selected_module(RTLIL::IdString mod_name) const
251 {
252 if (!selected_active_module.empty() && mod_name != selected_active_module)
253 return false;
254 if (selection_stack.size() == 0)
255 return true;
256 return selection_stack.back().selected_module(mod_name);
257 }
258
259 bool RTLIL::Design::selected_whole_module(RTLIL::IdString mod_name) const
260 {
261 if (!selected_active_module.empty() && mod_name != selected_active_module)
262 return false;
263 if (selection_stack.size() == 0)
264 return true;
265 return selection_stack.back().selected_whole_module(mod_name);
266 }
267
268 bool RTLIL::Design::selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const
269 {
270 if (!selected_active_module.empty() && mod_name != selected_active_module)
271 return false;
272 if (selection_stack.size() == 0)
273 return true;
274 return selection_stack.back().selected_member(mod_name, memb_name);
275 }
276
277 bool RTLIL::Design::selected_module(RTLIL::Module *mod) const
278 {
279 return selected_module(mod->name);
280 }
281
282 bool RTLIL::Design::selected_whole_module(RTLIL::Module *mod) const
283 {
284 return selected_whole_module(mod->name);
285 }
286
287 RTLIL::Module::Module()
288 {
289 refcount_wires_ = 0;
290 refcount_cells_ = 0;
291 }
292
293 RTLIL::Module::~Module()
294 {
295 for (auto it = wires_.begin(); it != wires_.end(); it++)
296 delete it->second;
297 for (auto it = memories.begin(); it != memories.end(); it++)
298 delete it->second;
299 for (auto it = cells_.begin(); it != cells_.end(); it++)
300 delete it->second;
301 for (auto it = processes.begin(); it != processes.end(); it++)
302 delete it->second;
303 }
304
305 RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, std::map<RTLIL::IdString, RTLIL::Const>)
306 {
307 log_error("Module `%s' is used with parameters but is not parametric!\n", id2cstr(name));
308 }
309
310 size_t RTLIL::Module::count_id(RTLIL::IdString id)
311 {
312 return wires_.count(id) + memories.count(id) + cells_.count(id) + processes.count(id);
313 }
314
315 #ifndef NDEBUG
316 namespace {
317 struct InternalCellChecker
318 {
319 RTLIL::Module *module;
320 RTLIL::Cell *cell;
321 std::set<RTLIL::IdString> expected_params, expected_ports;
322
323 InternalCellChecker(RTLIL::Module *module, RTLIL::Cell *cell) : module(module), cell(cell) { }
324
325 void error(int linenr)
326 {
327 char *ptr;
328 size_t size;
329
330 FILE *f = open_memstream(&ptr, &size);
331 ILANG_BACKEND::dump_cell(f, " ", cell);
332 fputc(0, f);
333 fclose(f);
334
335 log_error("Found error in internal cell %s%s%s (%s) at %s:%d:\n%s",
336 module ? module->name.c_str() : "", module ? "." : "",
337 cell->name.c_str(), cell->type.c_str(), __FILE__, linenr, ptr);
338 }
339
340 int param(const char *name)
341 {
342 if (cell->parameters.count(name) == 0)
343 error(__LINE__);
344 expected_params.insert(name);
345 return cell->parameters.at(name).as_int();
346 }
347
348 int param_bool(const char *name)
349 {
350 int v = param(name);
351 if (cell->parameters.at(name).bits.size() > 32)
352 error(__LINE__);
353 if (v != 0 && v != 1)
354 error(__LINE__);
355 return v;
356 }
357
358 void param_bits(const char *name, int width)
359 {
360 param(name);
361 if (int(cell->parameters.at(name).bits.size()) != width)
362 error(__LINE__);
363 }
364
365 void port(const char *name, int width)
366 {
367 if (!cell->has(name))
368 error(__LINE__);
369 if (cell->get(name).size() != width)
370 error(__LINE__);
371 expected_ports.insert(name);
372 }
373
374 void check_expected(bool check_matched_sign = true)
375 {
376 for (auto &para : cell->parameters)
377 if (expected_params.count(para.first) == 0)
378 error(__LINE__);
379 for (auto &conn : cell->connections())
380 if (expected_ports.count(conn.first) == 0)
381 error(__LINE__);
382
383 if (expected_params.count("\\A_SIGNED") != 0 && expected_params.count("\\B_SIGNED") && check_matched_sign) {
384 bool a_is_signed = param("\\A_SIGNED") != 0;
385 bool b_is_signed = param("\\B_SIGNED") != 0;
386 if (a_is_signed != b_is_signed)
387 error(__LINE__);
388 }
389 }
390
391 void check_gate(const char *ports)
392 {
393 if (cell->parameters.size() != 0)
394 error(__LINE__);
395
396 for (const char *p = ports; *p; p++) {
397 char portname[3] = { '\\', *p, 0 };
398 if (!cell->has(portname))
399 error(__LINE__);
400 if (cell->get(portname).size() != 1)
401 error(__LINE__);
402 }
403
404 for (auto &conn : cell->connections()) {
405 if (conn.first.size() != 2 || conn.first.at(0) != '\\')
406 error(__LINE__);
407 if (strchr(ports, conn.first.at(1)) == NULL)
408 error(__LINE__);
409 }
410 }
411
412 void check()
413 {
414 if (cell->type[0] != '$' || cell->type.substr(0, 3) == "$__" || cell->type.substr(0, 8) == "$paramod" ||
415 cell->type.substr(0, 9) == "$verific$" || cell->type.substr(0, 7) == "$array:")
416 return;
417
418 if (cell->type == "$not" || cell->type == "$pos" || cell->type == "$bu0" || cell->type == "$neg") {
419 param_bool("\\A_SIGNED");
420 port("\\A", param("\\A_WIDTH"));
421 port("\\Y", param("\\Y_WIDTH"));
422 check_expected();
423 return;
424 }
425
426 if (cell->type == "$and" || cell->type == "$or" || cell->type == "$xor" || cell->type == "$xnor") {
427 param_bool("\\A_SIGNED");
428 param_bool("\\B_SIGNED");
429 port("\\A", param("\\A_WIDTH"));
430 port("\\B", param("\\B_WIDTH"));
431 port("\\Y", param("\\Y_WIDTH"));
432 check_expected();
433 return;
434 }
435
436 if (cell->type == "$reduce_and" || cell->type == "$reduce_or" || cell->type == "$reduce_xor" ||
437 cell->type == "$reduce_xnor" || cell->type == "$reduce_bool") {
438 param_bool("\\A_SIGNED");
439 port("\\A", param("\\A_WIDTH"));
440 port("\\Y", param("\\Y_WIDTH"));
441 check_expected();
442 return;
443 }
444
445 if (cell->type == "$shl" || cell->type == "$shr" || cell->type == "$sshl" || cell->type == "$sshr") {
446 param_bool("\\A_SIGNED");
447 param_bool("\\B_SIGNED");
448 port("\\A", param("\\A_WIDTH"));
449 port("\\B", param("\\B_WIDTH"));
450 port("\\Y", param("\\Y_WIDTH"));
451 check_expected(false);
452 return;
453 }
454
455 if (cell->type == "$lt" || cell->type == "$le" || cell->type == "$eq" || cell->type == "$ne" ||
456 cell->type == "$eqx" || cell->type == "$nex" || cell->type == "$ge" || cell->type == "$gt") {
457 param_bool("\\A_SIGNED");
458 param_bool("\\B_SIGNED");
459 port("\\A", param("\\A_WIDTH"));
460 port("\\B", param("\\B_WIDTH"));
461 port("\\Y", param("\\Y_WIDTH"));
462 check_expected();
463 return;
464 }
465
466 if (cell->type == "$add" || cell->type == "$sub" || cell->type == "$mul" || cell->type == "$div" ||
467 cell->type == "$mod" || cell->type == "$pow") {
468 param_bool("\\A_SIGNED");
469 param_bool("\\B_SIGNED");
470 port("\\A", param("\\A_WIDTH"));
471 port("\\B", param("\\B_WIDTH"));
472 port("\\Y", param("\\Y_WIDTH"));
473 check_expected(cell->type != "$pow");
474 return;
475 }
476
477 if (cell->type == "$logic_not") {
478 param_bool("\\A_SIGNED");
479 port("\\A", param("\\A_WIDTH"));
480 port("\\Y", param("\\Y_WIDTH"));
481 check_expected();
482 return;
483 }
484
485 if (cell->type == "$logic_and" || cell->type == "$logic_or") {
486 param_bool("\\A_SIGNED");
487 param_bool("\\B_SIGNED");
488 port("\\A", param("\\A_WIDTH"));
489 port("\\B", param("\\B_WIDTH"));
490 port("\\Y", param("\\Y_WIDTH"));
491 check_expected(false);
492 return;
493 }
494
495 if (cell->type == "$slice") {
496 param("\\OFFSET");
497 port("\\A", param("\\A_WIDTH"));
498 port("\\Y", param("\\Y_WIDTH"));
499 if (param("\\OFFSET") + param("\\Y_WIDTH") > param("\\A_WIDTH"))
500 error(__LINE__);
501 check_expected();
502 return;
503 }
504
505 if (cell->type == "$concat") {
506 port("\\A", param("\\A_WIDTH"));
507 port("\\B", param("\\B_WIDTH"));
508 port("\\Y", param("\\A_WIDTH") + param("\\B_WIDTH"));
509 check_expected();
510 return;
511 }
512
513 if (cell->type == "$mux") {
514 port("\\A", param("\\WIDTH"));
515 port("\\B", param("\\WIDTH"));
516 port("\\S", 1);
517 port("\\Y", param("\\WIDTH"));
518 check_expected();
519 return;
520 }
521
522 if (cell->type == "$pmux" || cell->type == "$safe_pmux") {
523 port("\\A", param("\\WIDTH"));
524 port("\\B", param("\\WIDTH") * param("\\S_WIDTH"));
525 port("\\S", param("\\S_WIDTH"));
526 port("\\Y", param("\\WIDTH"));
527 check_expected();
528 return;
529 }
530
531 if (cell->type == "$lut") {
532 param("\\LUT");
533 port("\\I", param("\\WIDTH"));
534 port("\\O", 1);
535 check_expected();
536 return;
537 }
538
539 if (cell->type == "$sr") {
540 param_bool("\\SET_POLARITY");
541 param_bool("\\CLR_POLARITY");
542 port("\\SET", param("\\WIDTH"));
543 port("\\CLR", param("\\WIDTH"));
544 port("\\Q", param("\\WIDTH"));
545 check_expected();
546 return;
547 }
548
549 if (cell->type == "$dff") {
550 param_bool("\\CLK_POLARITY");
551 port("\\CLK", 1);
552 port("\\D", param("\\WIDTH"));
553 port("\\Q", param("\\WIDTH"));
554 check_expected();
555 return;
556 }
557
558 if (cell->type == "$dffsr") {
559 param_bool("\\CLK_POLARITY");
560 param_bool("\\SET_POLARITY");
561 param_bool("\\CLR_POLARITY");
562 port("\\CLK", 1);
563 port("\\SET", param("\\WIDTH"));
564 port("\\CLR", param("\\WIDTH"));
565 port("\\D", param("\\WIDTH"));
566 port("\\Q", param("\\WIDTH"));
567 check_expected();
568 return;
569 }
570
571 if (cell->type == "$adff") {
572 param_bool("\\CLK_POLARITY");
573 param_bool("\\ARST_POLARITY");
574 param_bits("\\ARST_VALUE", param("\\WIDTH"));
575 port("\\CLK", 1);
576 port("\\ARST", 1);
577 port("\\D", param("\\WIDTH"));
578 port("\\Q", param("\\WIDTH"));
579 check_expected();
580 return;
581 }
582
583 if (cell->type == "$dlatch") {
584 param_bool("\\EN_POLARITY");
585 port("\\EN", 1);
586 port("\\D", param("\\WIDTH"));
587 port("\\Q", param("\\WIDTH"));
588 check_expected();
589 return;
590 }
591
592 if (cell->type == "$dlatchsr") {
593 param_bool("\\EN_POLARITY");
594 param_bool("\\SET_POLARITY");
595 param_bool("\\CLR_POLARITY");
596 port("\\EN", 1);
597 port("\\SET", param("\\WIDTH"));
598 port("\\CLR", param("\\WIDTH"));
599 port("\\D", param("\\WIDTH"));
600 port("\\Q", param("\\WIDTH"));
601 check_expected();
602 return;
603 }
604
605 if (cell->type == "$fsm") {
606 param("\\NAME");
607 param_bool("\\CLK_POLARITY");
608 param_bool("\\ARST_POLARITY");
609 param("\\STATE_BITS");
610 param("\\STATE_NUM");
611 param("\\STATE_NUM_LOG2");
612 param("\\STATE_RST");
613 param_bits("\\STATE_TABLE", param("\\STATE_BITS") * param("\\STATE_NUM"));
614 param("\\TRANS_NUM");
615 param_bits("\\TRANS_TABLE", param("\\TRANS_NUM") * (2*param("\\STATE_NUM_LOG2") + param("\\CTRL_IN_WIDTH") + param("\\CTRL_OUT_WIDTH")));
616 port("\\CLK", 1);
617 port("\\ARST", 1);
618 port("\\CTRL_IN", param("\\CTRL_IN_WIDTH"));
619 port("\\CTRL_OUT", param("\\CTRL_OUT_WIDTH"));
620 check_expected();
621 return;
622 }
623
624 if (cell->type == "$memrd") {
625 param("\\MEMID");
626 param_bool("\\CLK_ENABLE");
627 param_bool("\\CLK_POLARITY");
628 param_bool("\\TRANSPARENT");
629 port("\\CLK", 1);
630 port("\\ADDR", param("\\ABITS"));
631 port("\\DATA", param("\\WIDTH"));
632 check_expected();
633 return;
634 }
635
636 if (cell->type == "$memwr") {
637 param("\\MEMID");
638 param_bool("\\CLK_ENABLE");
639 param_bool("\\CLK_POLARITY");
640 param("\\PRIORITY");
641 port("\\CLK", 1);
642 port("\\EN", param("\\WIDTH"));
643 port("\\ADDR", param("\\ABITS"));
644 port("\\DATA", param("\\WIDTH"));
645 check_expected();
646 return;
647 }
648
649 if (cell->type == "$mem") {
650 param("\\MEMID");
651 param("\\SIZE");
652 param("\\OFFSET");
653 param_bits("\\RD_CLK_ENABLE", param("\\RD_PORTS"));
654 param_bits("\\RD_CLK_POLARITY", param("\\RD_PORTS"));
655 param_bits("\\RD_TRANSPARENT", param("\\RD_PORTS"));
656 param_bits("\\WR_CLK_ENABLE", param("\\WR_PORTS"));
657 param_bits("\\WR_CLK_POLARITY", param("\\WR_PORTS"));
658 port("\\RD_CLK", param("\\RD_PORTS"));
659 port("\\RD_ADDR", param("\\RD_PORTS") * param("\\ABITS"));
660 port("\\RD_DATA", param("\\RD_PORTS") * param("\\WIDTH"));
661 port("\\WR_CLK", param("\\WR_PORTS"));
662 port("\\WR_EN", param("\\WR_PORTS") * param("\\WIDTH"));
663 port("\\WR_ADDR", param("\\WR_PORTS") * param("\\ABITS"));
664 port("\\WR_DATA", param("\\WR_PORTS") * param("\\WIDTH"));
665 check_expected();
666 return;
667 }
668
669 if (cell->type == "$assert") {
670 port("\\A", 1);
671 port("\\EN", 1);
672 check_expected();
673 return;
674 }
675
676 if (cell->type == "$_INV_") { check_gate("AY"); return; }
677 if (cell->type == "$_AND_") { check_gate("ABY"); return; }
678 if (cell->type == "$_OR_") { check_gate("ABY"); return; }
679 if (cell->type == "$_XOR_") { check_gate("ABY"); return; }
680 if (cell->type == "$_MUX_") { check_gate("ABSY"); return; }
681
682 if (cell->type == "$_SR_NN_") { check_gate("SRQ"); return; }
683 if (cell->type == "$_SR_NP_") { check_gate("SRQ"); return; }
684 if (cell->type == "$_SR_PN_") { check_gate("SRQ"); return; }
685 if (cell->type == "$_SR_PP_") { check_gate("SRQ"); return; }
686
687 if (cell->type == "$_DFF_N_") { check_gate("DQC"); return; }
688 if (cell->type == "$_DFF_P_") { check_gate("DQC"); return; }
689
690 if (cell->type == "$_DFF_NN0_") { check_gate("DQCR"); return; }
691 if (cell->type == "$_DFF_NN1_") { check_gate("DQCR"); return; }
692 if (cell->type == "$_DFF_NP0_") { check_gate("DQCR"); return; }
693 if (cell->type == "$_DFF_NP1_") { check_gate("DQCR"); return; }
694 if (cell->type == "$_DFF_PN0_") { check_gate("DQCR"); return; }
695 if (cell->type == "$_DFF_PN1_") { check_gate("DQCR"); return; }
696 if (cell->type == "$_DFF_PP0_") { check_gate("DQCR"); return; }
697 if (cell->type == "$_DFF_PP1_") { check_gate("DQCR"); return; }
698
699 if (cell->type == "$_DFFSR_NNN_") { check_gate("CSRDQ"); return; }
700 if (cell->type == "$_DFFSR_NNP_") { check_gate("CSRDQ"); return; }
701 if (cell->type == "$_DFFSR_NPN_") { check_gate("CSRDQ"); return; }
702 if (cell->type == "$_DFFSR_NPP_") { check_gate("CSRDQ"); return; }
703 if (cell->type == "$_DFFSR_PNN_") { check_gate("CSRDQ"); return; }
704 if (cell->type == "$_DFFSR_PNP_") { check_gate("CSRDQ"); return; }
705 if (cell->type == "$_DFFSR_PPN_") { check_gate("CSRDQ"); return; }
706 if (cell->type == "$_DFFSR_PPP_") { check_gate("CSRDQ"); return; }
707
708 if (cell->type == "$_DLATCH_N_") { check_gate("EDQ"); return; }
709 if (cell->type == "$_DLATCH_P_") { check_gate("EDQ"); return; }
710
711 if (cell->type == "$_DLATCHSR_NNN_") { check_gate("ESRDQ"); return; }
712 if (cell->type == "$_DLATCHSR_NNP_") { check_gate("ESRDQ"); return; }
713 if (cell->type == "$_DLATCHSR_NPN_") { check_gate("ESRDQ"); return; }
714 if (cell->type == "$_DLATCHSR_NPP_") { check_gate("ESRDQ"); return; }
715 if (cell->type == "$_DLATCHSR_PNN_") { check_gate("ESRDQ"); return; }
716 if (cell->type == "$_DLATCHSR_PNP_") { check_gate("ESRDQ"); return; }
717 if (cell->type == "$_DLATCHSR_PPN_") { check_gate("ESRDQ"); return; }
718 if (cell->type == "$_DLATCHSR_PPP_") { check_gate("ESRDQ"); return; }
719
720 error(__LINE__);
721 }
722 };
723 }
724 #endif
725
726 void RTLIL::Module::check()
727 {
728 #ifndef NDEBUG
729 for (auto &it : wires_) {
730 assert(it.first == it.second->name);
731 assert(it.first.size() > 0 && (it.first[0] == '\\' || it.first[0] == '$'));
732 assert(it.second->width >= 0);
733 assert(it.second->port_id >= 0);
734 for (auto &it2 : it.second->attributes) {
735 assert(it2.first.size() > 0 && (it2.first[0] == '\\' || it2.first[0] == '$'));
736 }
737 }
738
739 for (auto &it : memories) {
740 assert(it.first == it.second->name);
741 assert(it.first.size() > 0 && (it.first[0] == '\\' || it.first[0] == '$'));
742 assert(it.second->width >= 0);
743 assert(it.second->size >= 0);
744 for (auto &it2 : it.second->attributes) {
745 assert(it2.first.size() > 0 && (it2.first[0] == '\\' || it2.first[0] == '$'));
746 }
747 }
748
749 for (auto &it : cells_) {
750 assert(it.first == it.second->name);
751 assert(it.first.size() > 0 && (it.first[0] == '\\' || it.first[0] == '$'));
752 assert(it.second->type.size() > 0 && (it.second->type[0] == '\\' || it.second->type[0] == '$'));
753 for (auto &it2 : it.second->connections()) {
754 assert(it2.first.size() > 0 && (it2.first[0] == '\\' || it2.first[0] == '$'));
755 it2.second.check();
756 }
757 for (auto &it2 : it.second->attributes) {
758 assert(it2.first.size() > 0 && (it2.first[0] == '\\' || it2.first[0] == '$'));
759 }
760 for (auto &it2 : it.second->parameters) {
761 assert(it2.first.size() > 0 && (it2.first[0] == '\\' || it2.first[0] == '$'));
762 }
763 InternalCellChecker checker(this, it.second);
764 checker.check();
765 }
766
767 for (auto &it : processes) {
768 assert(it.first == it.second->name);
769 assert(it.first.size() > 0 && (it.first[0] == '\\' || it.first[0] == '$'));
770 // FIXME: More checks here..
771 }
772
773 for (auto &it : connections_) {
774 assert(it.first.size() == it.second.size());
775 it.first.check();
776 it.second.check();
777 }
778
779 for (auto &it : attributes) {
780 assert(it.first.size() > 0 && (it.first[0] == '\\' || it.first[0] == '$'));
781 }
782 #endif
783 }
784
785 void RTLIL::Module::optimize()
786 {
787 }
788
789 void RTLIL::Module::cloneInto(RTLIL::Module *new_mod) const
790 {
791 log_assert(new_mod->refcount_wires_ == 0);
792 log_assert(new_mod->refcount_cells_ == 0);
793
794 new_mod->name = name;
795 new_mod->connections_ = connections_;
796 new_mod->attributes = attributes;
797
798 for (auto &it : wires_)
799 new_mod->addWire(it.first, it.second);
800
801 for (auto &it : memories)
802 new_mod->memories[it.first] = new RTLIL::Memory(*it.second);
803
804 for (auto &it : cells_)
805 new_mod->addCell(it.first, it.second);
806
807 for (auto &it : processes)
808 new_mod->processes[it.first] = it.second->clone();
809
810 struct RewriteSigSpecWorker
811 {
812 RTLIL::Module *mod;
813 void operator()(RTLIL::SigSpec &sig)
814 {
815 std::vector<RTLIL::SigChunk> chunks = sig.chunks();
816 for (auto &c : chunks)
817 if (c.wire != NULL)
818 c.wire = mod->wires_.at(c.wire->name);
819 sig = chunks;
820 }
821 };
822
823 RewriteSigSpecWorker rewriteSigSpecWorker;
824 rewriteSigSpecWorker.mod = new_mod;
825 new_mod->rewrite_sigspecs(rewriteSigSpecWorker);
826 }
827
828 RTLIL::Module *RTLIL::Module::clone() const
829 {
830 RTLIL::Module *new_mod = new RTLIL::Module;
831 cloneInto(new_mod);
832 return new_mod;
833 }
834
835 void RTLIL::Module::add(RTLIL::Wire *wire)
836 {
837 log_assert(!wire->name.empty());
838 log_assert(count_id(wire->name) == 0);
839 log_assert(refcount_wires_ == 0);
840 wires_[wire->name] = wire;
841 }
842
843 void RTLIL::Module::add(RTLIL::Cell *cell)
844 {
845 log_assert(!cell->name.empty());
846 log_assert(count_id(cell->name) == 0);
847 log_assert(refcount_cells_ == 0);
848 cells_[cell->name] = cell;
849 }
850
851 namespace {
852 struct DeleteWireWorker
853 {
854 RTLIL::Module *module;
855 const std::set<RTLIL::Wire*> *wires_p;
856
857 void operator()(RTLIL::SigSpec &sig) {
858 std::vector<RTLIL::SigChunk> chunks = sig;
859 for (auto &c : chunks)
860 if (c.wire != NULL && wires_p->count(c.wire)) {
861 c.wire = module->addWire(NEW_ID, c.width);
862 c.offset = 0;
863 }
864 sig = chunks;
865 }
866 };
867 }
868
869 #if 0
870 void RTLIL::Module::remove(RTLIL::Wire *wire)
871 {
872 std::set<RTLIL::Wire*> wires_;
873 wires_.insert(wire);
874 remove(wires_);
875 }
876 #endif
877
878 void RTLIL::Module::remove(const std::set<RTLIL::Wire*> &wires)
879 {
880 log_assert(refcount_wires_ == 0);
881
882 DeleteWireWorker delete_wire_worker;
883 delete_wire_worker.module = this;
884 delete_wire_worker.wires_p = &wires;
885 rewrite_sigspecs(delete_wire_worker);
886
887 for (auto &it : wires) {
888 log_assert(wires_.count(it->name) != 0);
889 wires_.erase(it->name);
890 delete it;
891 }
892 }
893
894 void RTLIL::Module::remove(RTLIL::Cell *cell)
895 {
896 log_assert(cells_.count(cell->name) != 0);
897 log_assert(refcount_cells_ == 0);
898 cells_.erase(cell->name);
899 delete cell;
900 }
901
902 void RTLIL::Module::rename(RTLIL::Wire *wire, RTLIL::IdString new_name)
903 {
904 assert(wires_[wire->name] == wire);
905 log_assert(refcount_wires_ == 0);
906 wires_.erase(wire->name);
907 wire->name = new_name;
908 add(wire);
909 }
910
911 void RTLIL::Module::rename(RTLIL::Cell *cell, RTLIL::IdString new_name)
912 {
913 assert(cells_[cell->name] == cell);
914 log_assert(refcount_wires_ == 0);
915 cells_.erase(cell->name);
916 cell->name = new_name;
917 add(cell);
918 }
919
920 void RTLIL::Module::rename(RTLIL::IdString old_name, RTLIL::IdString new_name)
921 {
922 assert(count_id(old_name) != 0);
923 if (wires_.count(old_name))
924 rename(wires_.at(old_name), new_name);
925 else if (cells_.count(old_name))
926 rename(cells_.at(old_name), new_name);
927 else
928 log_abort();
929 }
930
931 static bool fixup_ports_compare(const RTLIL::Wire *a, const RTLIL::Wire *b)
932 {
933 if (a->port_id && !b->port_id)
934 return true;
935 if (!a->port_id && b->port_id)
936 return false;
937
938 if (a->port_id == b->port_id)
939 return a->name < b->name;
940 return a->port_id < b->port_id;
941 }
942
943 void RTLIL::Module::connect(const RTLIL::SigSig &conn)
944 {
945 connections_.push_back(conn);
946 }
947
948 void RTLIL::Module::connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs)
949 {
950 connections_.push_back(RTLIL::SigSig(lhs, rhs));
951 }
952
953 const std::vector<RTLIL::SigSig> &RTLIL::Module::connections() const
954 {
955 return connections_;
956 }
957
958 void RTLIL::Module::fixup_ports()
959 {
960 std::vector<RTLIL::Wire*> all_ports;
961
962 for (auto &w : wires_)
963 if (w.second->port_input || w.second->port_output)
964 all_ports.push_back(w.second);
965 else
966 w.second->port_id = 0;
967
968 std::sort(all_ports.begin(), all_ports.end(), fixup_ports_compare);
969 for (size_t i = 0; i < all_ports.size(); i++)
970 all_ports[i]->port_id = i+1;
971 }
972
973 RTLIL::Wire *RTLIL::Module::addWire(RTLIL::IdString name, int width)
974 {
975 RTLIL::Wire *wire = new RTLIL::Wire;
976 wire->name = name;
977 wire->width = width;
978 add(wire);
979 return wire;
980 }
981
982 RTLIL::Wire *RTLIL::Module::addWire(RTLIL::IdString name, const RTLIL::Wire *other)
983 {
984 RTLIL::Wire *wire = addWire(name);
985 wire->width = other->width;
986 wire->start_offset = other->start_offset;
987 wire->port_id = other->port_id;
988 wire->port_input = other->port_input;
989 wire->port_output = other->port_output;
990 wire->attributes = other->attributes;
991 return wire;
992 }
993
994 RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, RTLIL::IdString type)
995 {
996 RTLIL::Cell *cell = new RTLIL::Cell;
997 cell->name = name;
998 cell->type = type;
999 add(cell);
1000 return cell;
1001 }
1002
1003 RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, const RTLIL::Cell *other)
1004 {
1005 RTLIL::Cell *cell = addCell(name, other->type);
1006 cell->connections_ = other->connections_;
1007 cell->parameters = other->parameters;
1008 cell->attributes = other->attributes;
1009 return cell;
1010 }
1011
1012 #define DEF_METHOD(_func, _y_size, _type) \
1013 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed) { \
1014 RTLIL::Cell *cell = new RTLIL::Cell; \
1015 cell->name = name; \
1016 cell->type = _type; \
1017 cell->parameters["\\A_SIGNED"] = is_signed; \
1018 cell->parameters["\\A_WIDTH"] = sig_a.size(); \
1019 cell->parameters["\\Y_WIDTH"] = sig_y.size(); \
1020 cell->set("\\A", sig_a); \
1021 cell->set("\\Y", sig_y); \
1022 add(cell); \
1023 return cell; \
1024 } \
1025 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed) { \
1026 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
1027 add ## _func(name, sig_a, sig_y, is_signed); \
1028 return sig_y; \
1029 }
1030 DEF_METHOD(Not, sig_a.size(), "$not")
1031 DEF_METHOD(Pos, sig_a.size(), "$pos")
1032 DEF_METHOD(Bu0, sig_a.size(), "$bu0")
1033 DEF_METHOD(Neg, sig_a.size(), "$neg")
1034 DEF_METHOD(ReduceAnd, 1, "$reduce_and")
1035 DEF_METHOD(ReduceOr, 1, "$reduce_or")
1036 DEF_METHOD(ReduceXor, 1, "$reduce_xor")
1037 DEF_METHOD(ReduceXnor, 1, "$reduce_xnor")
1038 DEF_METHOD(ReduceBool, 1, "$reduce_bool")
1039 DEF_METHOD(LogicNot, 1, "$logic_not")
1040 #undef DEF_METHOD
1041
1042 #define DEF_METHOD(_func, _y_size, _type) \
1043 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed) { \
1044 RTLIL::Cell *cell = new RTLIL::Cell; \
1045 cell->name = name; \
1046 cell->type = _type; \
1047 cell->parameters["\\A_SIGNED"] = is_signed; \
1048 cell->parameters["\\B_SIGNED"] = is_signed; \
1049 cell->parameters["\\A_WIDTH"] = sig_a.size(); \
1050 cell->parameters["\\B_WIDTH"] = sig_b.size(); \
1051 cell->parameters["\\Y_WIDTH"] = sig_y.size(); \
1052 cell->set("\\A", sig_a); \
1053 cell->set("\\B", sig_b); \
1054 cell->set("\\Y", sig_y); \
1055 add(cell); \
1056 return cell; \
1057 } \
1058 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed) { \
1059 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
1060 add ## _func(name, sig_a, sig_b, sig_y, is_signed); \
1061 return sig_y; \
1062 }
1063 DEF_METHOD(And, std::max(sig_a.size(), sig_b.size()), "$and")
1064 DEF_METHOD(Or, std::max(sig_a.size(), sig_b.size()), "$or")
1065 DEF_METHOD(Xor, std::max(sig_a.size(), sig_b.size()), "$xor")
1066 DEF_METHOD(Xnor, std::max(sig_a.size(), sig_b.size()), "$xnor")
1067 DEF_METHOD(Shl, sig_a.size(), "$shl")
1068 DEF_METHOD(Shr, sig_a.size(), "$shr")
1069 DEF_METHOD(Sshl, sig_a.size(), "$sshl")
1070 DEF_METHOD(Sshr, sig_a.size(), "$sshr")
1071 DEF_METHOD(Lt, 1, "$lt")
1072 DEF_METHOD(Le, 1, "$le")
1073 DEF_METHOD(Eq, 1, "$eq")
1074 DEF_METHOD(Ne, 1, "$ne")
1075 DEF_METHOD(Eqx, 1, "$eqx")
1076 DEF_METHOD(Nex, 1, "$nex")
1077 DEF_METHOD(Ge, 1, "$ge")
1078 DEF_METHOD(Gt, 1, "$gt")
1079 DEF_METHOD(Add, std::max(sig_a.size(), sig_b.size()), "$add")
1080 DEF_METHOD(Sub, std::max(sig_a.size(), sig_b.size()), "$sub")
1081 DEF_METHOD(Mul, std::max(sig_a.size(), sig_b.size()), "$mul")
1082 DEF_METHOD(Div, std::max(sig_a.size(), sig_b.size()), "$div")
1083 DEF_METHOD(Mod, std::max(sig_a.size(), sig_b.size()), "$mod")
1084 DEF_METHOD(LogicAnd, 1, "$logic_and")
1085 DEF_METHOD(LogicOr, 1, "$logic_or")
1086 #undef DEF_METHOD
1087
1088 #define DEF_METHOD(_func, _type, _pmux) \
1089 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, RTLIL::SigSpec sig_y) { \
1090 RTLIL::Cell *cell = new RTLIL::Cell; \
1091 cell->name = name; \
1092 cell->type = _type; \
1093 cell->parameters["\\WIDTH"] = sig_a.size(); \
1094 cell->parameters["\\WIDTH"] = sig_b.size(); \
1095 if (_pmux) cell->parameters["\\S_WIDTH"] = sig_s.size(); \
1096 cell->set("\\A", sig_a); \
1097 cell->set("\\B", sig_b); \
1098 cell->set("\\S", sig_s); \
1099 cell->set("\\Y", sig_y); \
1100 add(cell); \
1101 return cell; \
1102 } \
1103 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s) { \
1104 RTLIL::SigSpec sig_y = addWire(NEW_ID, sig_a.size()); \
1105 add ## _func(name, sig_a, sig_b, sig_s, sig_y); \
1106 return sig_y; \
1107 }
1108 DEF_METHOD(Mux, "$mux", 0)
1109 DEF_METHOD(Pmux, "$pmux", 1)
1110 DEF_METHOD(SafePmux, "$safe_pmux", 1)
1111 #undef DEF_METHOD
1112
1113 #define DEF_METHOD_2(_func, _type, _P1, _P2) \
1114 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig1, RTLIL::SigSpec sig2) { \
1115 RTLIL::Cell *cell = new RTLIL::Cell; \
1116 cell->name = name; \
1117 cell->type = _type; \
1118 cell->set("\\" #_P1, sig1); \
1119 cell->set("\\" #_P2, sig2); \
1120 add(cell); \
1121 return cell; \
1122 } \
1123 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig1) { \
1124 RTLIL::SigSpec sig2 = addWire(NEW_ID); \
1125 add ## _func(name, sig1, sig2); \
1126 return sig2; \
1127 }
1128 #define DEF_METHOD_3(_func, _type, _P1, _P2, _P3) \
1129 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig1, RTLIL::SigSpec sig2, RTLIL::SigSpec sig3) { \
1130 RTLIL::Cell *cell = new RTLIL::Cell; \
1131 cell->name = name; \
1132 cell->type = _type; \
1133 cell->set("\\" #_P1, sig1); \
1134 cell->set("\\" #_P2, sig2); \
1135 cell->set("\\" #_P3, sig3); \
1136 add(cell); \
1137 return cell; \
1138 } \
1139 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig1, RTLIL::SigSpec sig2) { \
1140 RTLIL::SigSpec sig3 = addWire(NEW_ID); \
1141 add ## _func(name, sig1, sig2, sig3); \
1142 return sig3; \
1143 }
1144 #define DEF_METHOD_4(_func, _type, _P1, _P2, _P3, _P4) \
1145 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig1, RTLIL::SigSpec sig2, RTLIL::SigSpec sig3, RTLIL::SigSpec sig4) { \
1146 RTLIL::Cell *cell = new RTLIL::Cell; \
1147 cell->name = name; \
1148 cell->type = _type; \
1149 cell->set("\\" #_P1, sig1); \
1150 cell->set("\\" #_P2, sig2); \
1151 cell->set("\\" #_P3, sig3); \
1152 cell->set("\\" #_P4, sig4); \
1153 add(cell); \
1154 return cell; \
1155 } \
1156 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig1, RTLIL::SigSpec sig2, RTLIL::SigSpec sig3) { \
1157 RTLIL::SigSpec sig4 = addWire(NEW_ID); \
1158 add ## _func(name, sig1, sig2, sig3, sig4); \
1159 return sig4; \
1160 }
1161 DEF_METHOD_2(InvGate, "$_INV_", A, Y)
1162 DEF_METHOD_3(AndGate, "$_AND_", A, B, Y)
1163 DEF_METHOD_3(OrGate, "$_OR_", A, B, Y)
1164 DEF_METHOD_3(XorGate, "$_XOR_", A, B, Y)
1165 DEF_METHOD_4(MuxGate, "$_MUX_", A, B, S, Y)
1166 #undef DEF_METHOD_2
1167 #undef DEF_METHOD_3
1168 #undef DEF_METHOD_4
1169
1170 RTLIL::Cell* RTLIL::Module::addPow(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool a_signed, bool b_signed)
1171 {
1172 RTLIL::Cell *cell = new RTLIL::Cell;
1173 cell->name = name;
1174 cell->type = "$pow";
1175 cell->parameters["\\A_SIGNED"] = a_signed;
1176 cell->parameters["\\B_SIGNED"] = b_signed;
1177 cell->parameters["\\A_WIDTH"] = sig_a.size();
1178 cell->parameters["\\B_WIDTH"] = sig_b.size();
1179 cell->parameters["\\Y_WIDTH"] = sig_y.size();
1180 cell->set("\\A", sig_a);
1181 cell->set("\\B", sig_b);
1182 cell->set("\\Y", sig_y);
1183 add(cell);
1184 return cell;
1185 }
1186
1187 RTLIL::Cell* RTLIL::Module::addSlice(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, RTLIL::Const offset)
1188 {
1189 RTLIL::Cell *cell = new RTLIL::Cell;
1190 cell->name = name;
1191 cell->type = "$slice";
1192 cell->parameters["\\A_WIDTH"] = sig_a.size();
1193 cell->parameters["\\Y_WIDTH"] = sig_y.size();
1194 cell->parameters["\\OFFSET"] = offset;
1195 cell->set("\\A", sig_a);
1196 cell->set("\\Y", sig_y);
1197 add(cell);
1198 return cell;
1199 }
1200
1201 RTLIL::Cell* RTLIL::Module::addConcat(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y)
1202 {
1203 RTLIL::Cell *cell = new RTLIL::Cell;
1204 cell->name = name;
1205 cell->type = "$concat";
1206 cell->parameters["\\A_WIDTH"] = sig_a.size();
1207 cell->parameters["\\B_WIDTH"] = sig_b.size();
1208 cell->set("\\A", sig_a);
1209 cell->set("\\B", sig_b);
1210 cell->set("\\Y", sig_y);
1211 add(cell);
1212 return cell;
1213 }
1214
1215 RTLIL::Cell* RTLIL::Module::addLut(RTLIL::IdString name, RTLIL::SigSpec sig_i, RTLIL::SigSpec sig_o, RTLIL::Const lut)
1216 {
1217 RTLIL::Cell *cell = new RTLIL::Cell;
1218 cell->name = name;
1219 cell->type = "$lut";
1220 cell->parameters["\\LUT"] = lut;
1221 cell->parameters["\\WIDTH"] = sig_i.size();
1222 cell->set("\\I", sig_i);
1223 cell->set("\\O", sig_o);
1224 add(cell);
1225 return cell;
1226 }
1227
1228 RTLIL::Cell* RTLIL::Module::addAssert(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en)
1229 {
1230 RTLIL::Cell *cell = new RTLIL::Cell;
1231 cell->name = name;
1232 cell->type = "$assert";
1233 cell->set("\\A", sig_a);
1234 cell->set("\\EN", sig_en);
1235 add(cell);
1236 return cell;
1237 }
1238
1239 RTLIL::Cell* RTLIL::Module::addSr(RTLIL::IdString name, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr, RTLIL::SigSpec sig_q, bool set_polarity, bool clr_polarity)
1240 {
1241 RTLIL::Cell *cell = new RTLIL::Cell;
1242 cell->name = name;
1243 cell->type = "$sr";
1244 cell->parameters["\\SET_POLARITY"] = set_polarity;
1245 cell->parameters["\\CLR_POLARITY"] = clr_polarity;
1246 cell->parameters["\\WIDTH"] = sig_q.size();
1247 cell->set("\\SET", sig_set);
1248 cell->set("\\CLR", sig_clr);
1249 cell->set("\\Q", sig_q);
1250 add(cell);
1251 return cell;
1252 }
1253
1254 RTLIL::Cell* RTLIL::Module::addDff(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity)
1255 {
1256 RTLIL::Cell *cell = new RTLIL::Cell;
1257 cell->name = name;
1258 cell->type = "$dff";
1259 cell->parameters["\\CLK_POLARITY"] = clk_polarity;
1260 cell->parameters["\\WIDTH"] = sig_q.size();
1261 cell->set("\\CLK", sig_clk);
1262 cell->set("\\D", sig_d);
1263 cell->set("\\Q", sig_q);
1264 add(cell);
1265 return cell;
1266 }
1267
1268 RTLIL::Cell* RTLIL::Module::addDffsr(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
1269 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity)
1270 {
1271 RTLIL::Cell *cell = new RTLIL::Cell;
1272 cell->name = name;
1273 cell->type = "$dffsr";
1274 cell->parameters["\\CLK_POLARITY"] = clk_polarity;
1275 cell->parameters["\\SET_POLARITY"] = set_polarity;
1276 cell->parameters["\\CLR_POLARITY"] = clr_polarity;
1277 cell->parameters["\\WIDTH"] = sig_q.size();
1278 cell->set("\\CLK", sig_clk);
1279 cell->set("\\SET", sig_set);
1280 cell->set("\\CLR", sig_clr);
1281 cell->set("\\D", sig_d);
1282 cell->set("\\Q", sig_q);
1283 add(cell);
1284 return cell;
1285 }
1286
1287 RTLIL::Cell* RTLIL::Module::addAdff(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_arst, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q,
1288 RTLIL::Const arst_value, bool clk_polarity, bool arst_polarity)
1289 {
1290 RTLIL::Cell *cell = new RTLIL::Cell;
1291 cell->name = name;
1292 cell->type = "$adff";
1293 cell->parameters["\\CLK_POLARITY"] = clk_polarity;
1294 cell->parameters["\\ARST_POLARITY"] = arst_polarity;
1295 cell->parameters["\\ARST_VALUE"] = arst_value;
1296 cell->parameters["\\WIDTH"] = sig_q.size();
1297 cell->set("\\CLK", sig_clk);
1298 cell->set("\\ARST", sig_arst);
1299 cell->set("\\D", sig_d);
1300 cell->set("\\Q", sig_q);
1301 add(cell);
1302 return cell;
1303 }
1304
1305 RTLIL::Cell* RTLIL::Module::addDlatch(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity)
1306 {
1307 RTLIL::Cell *cell = new RTLIL::Cell;
1308 cell->name = name;
1309 cell->type = "$dlatch";
1310 cell->parameters["\\EN_POLARITY"] = en_polarity;
1311 cell->parameters["\\WIDTH"] = sig_q.size();
1312 cell->set("\\EN", sig_en);
1313 cell->set("\\D", sig_d);
1314 cell->set("\\Q", sig_q);
1315 add(cell);
1316 return cell;
1317 }
1318
1319 RTLIL::Cell* RTLIL::Module::addDlatchsr(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
1320 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity, bool set_polarity, bool clr_polarity)
1321 {
1322 RTLIL::Cell *cell = new RTLIL::Cell;
1323 cell->name = name;
1324 cell->type = "$dlatchsr";
1325 cell->parameters["\\EN_POLARITY"] = en_polarity;
1326 cell->parameters["\\SET_POLARITY"] = set_polarity;
1327 cell->parameters["\\CLR_POLARITY"] = clr_polarity;
1328 cell->parameters["\\WIDTH"] = sig_q.size();
1329 cell->set("\\EN", sig_en);
1330 cell->set("\\SET", sig_set);
1331 cell->set("\\CLR", sig_clr);
1332 cell->set("\\D", sig_d);
1333 cell->set("\\Q", sig_q);
1334 add(cell);
1335 return cell;
1336 }
1337
1338 RTLIL::Cell* RTLIL::Module::addDffGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity)
1339 {
1340 RTLIL::Cell *cell = new RTLIL::Cell;
1341 cell->name = name;
1342 cell->type = stringf("$_DFF_%c_", clk_polarity ? 'P' : 'N');
1343 cell->set("\\C", sig_clk);
1344 cell->set("\\D", sig_d);
1345 cell->set("\\Q", sig_q);
1346 add(cell);
1347 return cell;
1348 }
1349
1350 RTLIL::Cell* RTLIL::Module::addDffsrGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
1351 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity)
1352 {
1353 RTLIL::Cell *cell = new RTLIL::Cell;
1354 cell->name = name;
1355 cell->type = stringf("$_DFFSR_%c%c%c_", clk_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N');
1356 cell->set("\\C", sig_clk);
1357 cell->set("\\S", sig_set);
1358 cell->set("\\R", sig_clr);
1359 cell->set("\\D", sig_d);
1360 cell->set("\\Q", sig_q);
1361 add(cell);
1362 return cell;
1363 }
1364
1365 RTLIL::Cell* RTLIL::Module::addAdffGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_arst, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q,
1366 bool arst_value, bool clk_polarity, bool arst_polarity)
1367 {
1368 RTLIL::Cell *cell = new RTLIL::Cell;
1369 cell->name = name;
1370 cell->type = stringf("$_DFF_%c%c%c_", clk_polarity ? 'P' : 'N', arst_polarity ? 'P' : 'N', arst_value ? '1' : '0');
1371 cell->set("\\C", sig_clk);
1372 cell->set("\\R", sig_arst);
1373 cell->set("\\D", sig_d);
1374 cell->set("\\Q", sig_q);
1375 add(cell);
1376 return cell;
1377 }
1378
1379 RTLIL::Cell* RTLIL::Module::addDlatchGate(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity)
1380 {
1381 RTLIL::Cell *cell = new RTLIL::Cell;
1382 cell->name = name;
1383 cell->type = stringf("$_DLATCH_%c_", en_polarity ? 'P' : 'N');
1384 cell->set("\\E", sig_en);
1385 cell->set("\\D", sig_d);
1386 cell->set("\\Q", sig_q);
1387 add(cell);
1388 return cell;
1389 }
1390
1391 RTLIL::Cell* RTLIL::Module::addDlatchsrGate(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
1392 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity, bool set_polarity, bool clr_polarity)
1393 {
1394 RTLIL::Cell *cell = new RTLIL::Cell;
1395 cell->name = name;
1396 cell->type = stringf("$_DLATCHSR_%c%c%c_", en_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N');
1397 cell->set("\\E", sig_en);
1398 cell->set("\\S", sig_set);
1399 cell->set("\\R", sig_clr);
1400 cell->set("\\D", sig_d);
1401 cell->set("\\Q", sig_q);
1402 add(cell);
1403 return cell;
1404 }
1405
1406
1407 RTLIL::Wire::Wire()
1408 {
1409 width = 1;
1410 start_offset = 0;
1411 port_id = 0;
1412 port_input = false;
1413 port_output = false;
1414 }
1415
1416 RTLIL::Memory::Memory()
1417 {
1418 width = 1;
1419 size = 0;
1420 }
1421
1422 bool RTLIL::Cell::has(RTLIL::IdString portname)
1423 {
1424 return connections_.count(portname) != 0;
1425 }
1426
1427 void RTLIL::Cell::unset(RTLIL::IdString portname)
1428 {
1429 connections_.erase(portname);
1430 }
1431
1432 void RTLIL::Cell::set(RTLIL::IdString portname, RTLIL::SigSpec signal)
1433 {
1434 connections_[portname] = signal;
1435 }
1436
1437 const RTLIL::SigSpec &RTLIL::Cell::get(RTLIL::IdString portname) const
1438 {
1439 return connections_.at(portname);
1440 }
1441
1442 const std::map<RTLIL::IdString, RTLIL::SigSpec> &RTLIL::Cell::connections() const
1443 {
1444 return connections_;
1445 }
1446
1447 void RTLIL::Cell::check()
1448 {
1449 #ifndef NDEBUG
1450 InternalCellChecker checker(NULL, this);
1451 checker.check();
1452 #endif
1453 }
1454
1455 void RTLIL::Cell::fixup_parameters(bool set_a_signed, bool set_b_signed)
1456 {
1457 if (type[0] != '$' || type.substr(0, 2) == "$_" || type.substr(0, 8) == "$paramod" ||
1458 type.substr(0, 9) == "$verific$" || type.substr(0, 7) == "$array:")
1459 return;
1460
1461 if (type == "$mux" || type == "$pmux" || type == "$safe_pmux")
1462 {
1463 parameters["\\WIDTH"] = SIZE(connections_["\\Y"]);
1464 if (type == "$pmux" || type == "$safe_pmux")
1465 parameters["\\S_WIDTH"] = SIZE(connections_["\\S"]);
1466 check();
1467 return;
1468 }
1469
1470 bool signedness_ab = type != "$slice" && type != "$concat";
1471
1472 if (connections_.count("\\A")) {
1473 if (signedness_ab) {
1474 if (set_a_signed)
1475 parameters["\\A_SIGNED"] = true;
1476 else if (parameters.count("\\A_SIGNED") == 0)
1477 parameters["\\A_SIGNED"] = false;
1478 }
1479 parameters["\\A_WIDTH"] = SIZE(connections_["\\A"]);
1480 }
1481
1482 if (connections_.count("\\B")) {
1483 if (signedness_ab) {
1484 if (set_b_signed)
1485 parameters["\\B_SIGNED"] = true;
1486 else if (parameters.count("\\B_SIGNED") == 0)
1487 parameters["\\B_SIGNED"] = false;
1488 }
1489 parameters["\\B_WIDTH"] = SIZE(connections_["\\B"]);
1490 }
1491
1492 if (connections_.count("\\Y"))
1493 parameters["\\Y_WIDTH"] = SIZE(connections_["\\Y"]);
1494
1495 check();
1496 }
1497
1498 RTLIL::SigChunk::SigChunk()
1499 {
1500 wire = NULL;
1501 width = 0;
1502 offset = 0;
1503 }
1504
1505 RTLIL::SigChunk::SigChunk(const RTLIL::Const &value)
1506 {
1507 wire = NULL;
1508 data = value;
1509 width = data.bits.size();
1510 offset = 0;
1511 }
1512
1513 RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire)
1514 {
1515 log_assert(wire != nullptr);
1516 this->wire = wire;
1517 this->width = wire->width;
1518 this->offset = 0;
1519 }
1520
1521 RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire, int offset, int width)
1522 {
1523 log_assert(wire != nullptr);
1524 this->wire = wire;
1525 this->width = width;
1526 this->offset = offset;
1527 }
1528
1529 RTLIL::SigChunk::SigChunk(const std::string &str)
1530 {
1531 wire = NULL;
1532 data = RTLIL::Const(str);
1533 width = data.bits.size();
1534 offset = 0;
1535 }
1536
1537 RTLIL::SigChunk::SigChunk(int val, int width)
1538 {
1539 wire = NULL;
1540 data = RTLIL::Const(val, width);
1541 this->width = data.bits.size();
1542 offset = 0;
1543 }
1544
1545 RTLIL::SigChunk::SigChunk(RTLIL::State bit, int width)
1546 {
1547 wire = NULL;
1548 data = RTLIL::Const(bit, width);
1549 this->width = data.bits.size();
1550 offset = 0;
1551 }
1552
1553 RTLIL::SigChunk::SigChunk(RTLIL::SigBit bit)
1554 {
1555 wire = bit.wire;
1556 if (wire == NULL)
1557 data = RTLIL::Const(bit.data);
1558 offset = bit.offset;
1559 width = 1;
1560 }
1561
1562 RTLIL::SigChunk RTLIL::SigChunk::extract(int offset, int length) const
1563 {
1564 RTLIL::SigChunk ret;
1565 if (wire) {
1566 ret.wire = wire;
1567 ret.offset = this->offset + offset;
1568 ret.width = length;
1569 } else {
1570 for (int i = 0; i < length; i++)
1571 ret.data.bits.push_back(data.bits[offset+i]);
1572 ret.width = length;
1573 }
1574 return ret;
1575 }
1576
1577 bool RTLIL::SigChunk::operator <(const RTLIL::SigChunk &other) const
1578 {
1579 if (wire && other.wire)
1580 if (wire->name != other.wire->name)
1581 return wire->name < other.wire->name;
1582
1583 if (wire != other.wire)
1584 return wire < other.wire;
1585
1586 if (offset != other.offset)
1587 return offset < other.offset;
1588
1589 if (width != other.width)
1590 return width < other.width;
1591
1592 return data.bits < other.data.bits;
1593 }
1594
1595 bool RTLIL::SigChunk::operator ==(const RTLIL::SigChunk &other) const
1596 {
1597 if (wire != other.wire || width != other.width || offset != other.offset)
1598 return false;
1599 if (data.bits != other.data.bits)
1600 return false;
1601 return true;
1602 }
1603
1604 bool RTLIL::SigChunk::operator !=(const RTLIL::SigChunk &other) const
1605 {
1606 if (*this == other)
1607 return false;
1608 return true;
1609 }
1610
1611 RTLIL::SigSpec::SigSpec()
1612 {
1613 width_ = 0;
1614 hash_ = 0;
1615 }
1616
1617 RTLIL::SigSpec::SigSpec(const RTLIL::SigSpec &other)
1618 {
1619 *this = other;
1620 }
1621
1622 const RTLIL::SigSpec &RTLIL::SigSpec::operator=(const RTLIL::SigSpec &other)
1623 {
1624 cover("kernel.rtlil.sigspec.assign");
1625
1626 width_ = other.width_;
1627 hash_ = other.hash_;
1628 chunks_ = other.chunks_;
1629 bits_.clear();
1630
1631 if (!other.bits_.empty())
1632 {
1633 RTLIL::SigChunk *last = NULL;
1634 int last_end_offset = 0;
1635
1636 for (auto &bit : other.bits_) {
1637 if (last && bit.wire == last->wire) {
1638 if (bit.wire == NULL) {
1639 last->data.bits.push_back(bit.data);
1640 last->width++;
1641 continue;
1642 } else if (last_end_offset == bit.offset) {
1643 last_end_offset++;
1644 last->width++;
1645 continue;
1646 }
1647 }
1648 chunks_.push_back(bit);
1649 last = &chunks_.back();
1650 last_end_offset = bit.offset + 1;
1651 }
1652
1653 check();
1654 }
1655
1656 return *this;
1657 }
1658
1659 RTLIL::SigSpec::SigSpec(const RTLIL::Const &value)
1660 {
1661 chunks_.push_back(RTLIL::SigChunk(value));
1662 width_ = chunks_.back().width;
1663 hash_ = 0;
1664 check();
1665 }
1666
1667 RTLIL::SigSpec::SigSpec(const RTLIL::SigChunk &chunk)
1668 {
1669 chunks_.push_back(chunk);
1670 width_ = chunks_.back().width;
1671 hash_ = 0;
1672 check();
1673 }
1674
1675 RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire)
1676 {
1677 chunks_.push_back(RTLIL::SigChunk(wire));
1678 width_ = chunks_.back().width;
1679 hash_ = 0;
1680 check();
1681 }
1682
1683 RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire, int offset, int width)
1684 {
1685 chunks_.push_back(RTLIL::SigChunk(wire, offset, width));
1686 width_ = chunks_.back().width;
1687 hash_ = 0;
1688 check();
1689 }
1690
1691 RTLIL::SigSpec::SigSpec(const std::string &str)
1692 {
1693 chunks_.push_back(RTLIL::SigChunk(str));
1694 width_ = chunks_.back().width;
1695 hash_ = 0;
1696 check();
1697 }
1698
1699 RTLIL::SigSpec::SigSpec(int val, int width)
1700 {
1701 chunks_.push_back(RTLIL::SigChunk(val, width));
1702 width_ = width;
1703 hash_ = 0;
1704 check();
1705 }
1706
1707 RTLIL::SigSpec::SigSpec(RTLIL::State bit, int width)
1708 {
1709 chunks_.push_back(RTLIL::SigChunk(bit, width));
1710 width_ = width;
1711 hash_ = 0;
1712 check();
1713 }
1714
1715 RTLIL::SigSpec::SigSpec(RTLIL::SigBit bit, int width)
1716 {
1717 if (bit.wire == NULL)
1718 chunks_.push_back(RTLIL::SigChunk(bit.data, width));
1719 else
1720 for (int i = 0; i < width; i++)
1721 chunks_.push_back(bit);
1722 width_ = width;
1723 hash_ = 0;
1724 check();
1725 }
1726
1727 RTLIL::SigSpec::SigSpec(std::vector<RTLIL::SigChunk> chunks)
1728 {
1729 width_ = 0;
1730 hash_ = 0;
1731 for (auto &c : chunks)
1732 append(c);
1733 check();
1734 }
1735
1736 RTLIL::SigSpec::SigSpec(std::vector<RTLIL::SigBit> bits)
1737 {
1738 width_ = 0;
1739 hash_ = 0;
1740 for (auto &bit : bits)
1741 append_bit(bit);
1742 check();
1743 }
1744
1745 RTLIL::SigSpec::SigSpec(std::set<RTLIL::SigBit> bits)
1746 {
1747 width_ = 0;
1748 hash_ = 0;
1749 for (auto &bit : bits)
1750 append_bit(bit);
1751 check();
1752 }
1753
1754 void RTLIL::SigSpec::pack() const
1755 {
1756 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
1757
1758 if (that->bits_.empty())
1759 return;
1760
1761 cover("kernel.rtlil.sigspec.convert.pack");
1762 log_assert(that->chunks_.empty());
1763
1764 std::vector<RTLIL::SigBit> old_bits;
1765 old_bits.swap(that->bits_);
1766
1767 RTLIL::SigChunk *last = NULL;
1768 int last_end_offset = 0;
1769
1770 for (auto &bit : old_bits) {
1771 if (last && bit.wire == last->wire) {
1772 if (bit.wire == NULL) {
1773 last->data.bits.push_back(bit.data);
1774 last->width++;
1775 continue;
1776 } else if (last_end_offset == bit.offset) {
1777 last_end_offset++;
1778 last->width++;
1779 continue;
1780 }
1781 }
1782 that->chunks_.push_back(bit);
1783 last = &that->chunks_.back();
1784 last_end_offset = bit.offset + 1;
1785 }
1786
1787 check();
1788 }
1789
1790 void RTLIL::SigSpec::unpack() const
1791 {
1792 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
1793
1794 if (that->chunks_.empty())
1795 return;
1796
1797 cover("kernel.rtlil.sigspec.convert.unpack");
1798 log_assert(that->bits_.empty());
1799
1800 that->bits_.reserve(that->width_);
1801 for (auto &c : that->chunks_)
1802 for (int i = 0; i < c.width; i++)
1803 that->bits_.push_back(RTLIL::SigBit(c, i));
1804
1805 that->chunks_.clear();
1806 that->hash_ = 0;
1807 }
1808
1809 #define DJB2(_hash, _value) do { (_hash) = (((_hash) << 5) + (_hash)) + (_value); } while (0)
1810
1811 void RTLIL::SigSpec::hash() const
1812 {
1813 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
1814
1815 if (that->hash_ != 0)
1816 return;
1817
1818 cover("kernel.rtlil.sigspec.hash");
1819 that->pack();
1820
1821 that->hash_ = 5381;
1822 for (auto &c : that->chunks_)
1823 if (c.wire == NULL) {
1824 for (auto &v : c.data.bits)
1825 DJB2(that->hash_, v);
1826 } else {
1827 for (auto &v : c.wire->name)
1828 DJB2(that->hash_, v);
1829 DJB2(that->hash_, c.offset);
1830 DJB2(that->hash_, c.width);
1831 }
1832
1833 if (that->hash_ == 0)
1834 that->hash_ = 1;
1835 }
1836
1837 void RTLIL::SigSpec::sort()
1838 {
1839 unpack();
1840 cover("kernel.rtlil.sigspec.sort");
1841 std::sort(bits_.begin(), bits_.end());
1842 }
1843
1844 void RTLIL::SigSpec::sort_and_unify()
1845 {
1846 cover("kernel.rtlil.sigspec.sort_and_unify");
1847 *this = this->to_sigbit_set();
1848 }
1849
1850 void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with)
1851 {
1852 replace(pattern, with, this);
1853 }
1854
1855 void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with, RTLIL::SigSpec *other) const
1856 {
1857 cover("kernel.rtlil.sigspec.replace");
1858
1859 unpack();
1860 pattern.unpack();
1861 with.unpack();
1862
1863 assert(other != NULL);
1864 assert(width_ == other->width_);
1865 other->unpack();
1866
1867 assert(pattern.width_ == with.width_);
1868
1869 std::map<RTLIL::SigBit, RTLIL::SigBit> pattern_map;
1870 for (int i = 0; i < SIZE(pattern.bits_); i++)
1871 if (pattern.bits_[i].wire != NULL)
1872 pattern_map[pattern.bits_[i]] = with.bits_[i];
1873
1874 for (int i = 0; i < SIZE(bits_); i++)
1875 if (pattern_map.count(bits_[i]))
1876 other->bits_[i] = pattern_map.at(bits_[i]);
1877
1878 other->check();
1879 }
1880
1881 void RTLIL::SigSpec::remove(const RTLIL::SigSpec &pattern)
1882 {
1883 remove2(pattern, NULL);
1884 }
1885
1886 void RTLIL::SigSpec::remove(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other) const
1887 {
1888 RTLIL::SigSpec tmp = *this;
1889 tmp.remove2(pattern, other);
1890 }
1891
1892 void RTLIL::SigSpec::remove2(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other)
1893 {
1894 if (other)
1895 cover("kernel.rtlil.sigspec.remove_other");
1896 else
1897 cover("kernel.rtlil.sigspec.remove");
1898
1899 unpack();
1900
1901 if (other != NULL) {
1902 assert(width_ == other->width_);
1903 other->unpack();
1904 }
1905
1906 std::set<RTLIL::SigBit> pattern_bits = pattern.to_sigbit_set();
1907 std::vector<RTLIL::SigBit> new_bits, new_other_bits;
1908
1909 for (int i = 0; i < SIZE(bits_); i++) {
1910 if (bits_[i].wire != NULL && pattern_bits.count(bits_[i]))
1911 continue;
1912 if (other != NULL)
1913 new_other_bits.push_back(other->bits_[i]);
1914 new_bits.push_back(bits_[i]);
1915 }
1916
1917 bits_.swap(new_bits);
1918 width_ = SIZE(bits_);
1919
1920 if (other != NULL) {
1921 other->bits_.swap(new_other_bits);
1922 other->width_ = SIZE(other->bits_);
1923 }
1924
1925 check();
1926 }
1927
1928 RTLIL::SigSpec RTLIL::SigSpec::extract(RTLIL::SigSpec pattern, const RTLIL::SigSpec *other) const
1929 {
1930 if (other)
1931 cover("kernel.rtlil.sigspec.extract_other");
1932 else
1933 cover("kernel.rtlil.sigspec.extract");
1934
1935 pack();
1936 pattern.pack();
1937
1938 if (other != NULL)
1939 other->pack();
1940
1941 assert(other == NULL || width_ == other->width_);
1942
1943 std::set<RTLIL::SigBit> pat = pattern.to_sigbit_set();
1944 std::vector<RTLIL::SigBit> bits_match = to_sigbit_vector();
1945 RTLIL::SigSpec ret;
1946
1947 if (other) {
1948 std::vector<RTLIL::SigBit> bits_other = other->to_sigbit_vector();
1949 for (int i = 0; i < width_; i++)
1950 if (bits_match[i].wire && pat.count(bits_match[i]))
1951 ret.append_bit(bits_other[i]);
1952 } else {
1953 for (int i = 0; i < width_; i++)
1954 if (bits_match[i].wire && pat.count(bits_match[i]))
1955 ret.append_bit(bits_match[i]);
1956 }
1957
1958 ret.check();
1959 return ret;
1960 }
1961
1962 void RTLIL::SigSpec::replace(int offset, const RTLIL::SigSpec &with)
1963 {
1964 cover("kernel.rtlil.sigspec.replace_pos");
1965
1966 unpack();
1967 with.unpack();
1968
1969 assert(offset >= 0);
1970 assert(with.width_ >= 0);
1971 assert(offset+with.width_ <= width_);
1972
1973 for (int i = 0; i < with.width_; i++)
1974 bits_.at(offset + i) = with.bits_.at(i);
1975
1976 check();
1977 }
1978
1979 void RTLIL::SigSpec::remove_const()
1980 {
1981 if (packed())
1982 {
1983 cover("kernel.rtlil.sigspec.remove_const.packed");
1984
1985 std::vector<RTLIL::SigChunk> new_chunks;
1986 new_chunks.reserve(SIZE(chunks_));
1987
1988 width_ = 0;
1989 for (auto &chunk : chunks_)
1990 if (chunk.wire != NULL) {
1991 new_chunks.push_back(chunk);
1992 width_ += chunk.width;
1993 }
1994
1995 chunks_.swap(new_chunks);
1996 }
1997 else
1998 {
1999 cover("kernel.rtlil.sigspec.remove_const.unpacked");
2000
2001 std::vector<RTLIL::SigBit> new_bits;
2002 new_bits.reserve(width_);
2003
2004 for (auto &bit : bits_)
2005 if (bit.wire != NULL)
2006 new_bits.push_back(bit);
2007
2008 bits_.swap(new_bits);
2009 width_ = bits_.size();
2010 }
2011
2012 check();
2013 }
2014
2015 void RTLIL::SigSpec::remove(int offset, int length)
2016 {
2017 cover("kernel.rtlil.sigspec.remove_pos");
2018
2019 unpack();
2020
2021 assert(offset >= 0);
2022 assert(length >= 0);
2023 assert(offset + length <= width_);
2024
2025 bits_.erase(bits_.begin() + offset, bits_.begin() + offset + length);
2026 width_ = bits_.size();
2027
2028 check();
2029 }
2030
2031 RTLIL::SigSpec RTLIL::SigSpec::extract(int offset, int length) const
2032 {
2033 unpack();
2034 cover("kernel.rtlil.sigspec.extract_pos");
2035 return std::vector<RTLIL::SigBit>(bits_.begin() + offset, bits_.begin() + offset + length);
2036 }
2037
2038 void RTLIL::SigSpec::append(const RTLIL::SigSpec &signal)
2039 {
2040 if (signal.width_ == 0)
2041 return;
2042
2043 if (width_ == 0) {
2044 *this = signal;
2045 return;
2046 }
2047
2048 cover("kernel.rtlil.sigspec.append");
2049
2050 if (packed() != signal.packed()) {
2051 pack();
2052 signal.pack();
2053 }
2054
2055 if (packed())
2056 for (auto &other_c : signal.chunks_)
2057 {
2058 auto &my_last_c = chunks_.back();
2059 if (my_last_c.wire == NULL && other_c.wire == NULL) {
2060 auto &this_data = my_last_c.data.bits;
2061 auto &other_data = other_c.data.bits;
2062 this_data.insert(this_data.end(), other_data.begin(), other_data.end());
2063 my_last_c.width += other_c.width;
2064 } else
2065 if (my_last_c.wire == other_c.wire && my_last_c.offset + my_last_c.width == other_c.offset) {
2066 my_last_c.width += other_c.width;
2067 } else
2068 chunks_.push_back(other_c);
2069 }
2070 else
2071 bits_.insert(bits_.end(), signal.bits_.begin(), signal.bits_.end());
2072
2073 width_ += signal.width_;
2074 check();
2075 }
2076
2077 void RTLIL::SigSpec::append_bit(const RTLIL::SigBit &bit)
2078 {
2079 if (packed())
2080 {
2081 cover("kernel.rtlil.sigspec.append_bit.packed");
2082
2083 if (chunks_.size() == 0)
2084 chunks_.push_back(bit);
2085 else
2086 if (bit.wire == NULL)
2087 if (chunks_.back().wire == NULL) {
2088 chunks_.back().data.bits.push_back(bit.data);
2089 chunks_.back().width++;
2090 } else
2091 chunks_.push_back(bit);
2092 else
2093 if (chunks_.back().wire == bit.wire && chunks_.back().offset + chunks_.back().width == bit.offset)
2094 chunks_.back().width++;
2095 else
2096 chunks_.push_back(bit);
2097 }
2098 else
2099 {
2100 cover("kernel.rtlil.sigspec.append_bit.unpacked");
2101 bits_.push_back(bit);
2102 }
2103
2104 width_++;
2105 check();
2106 }
2107
2108 void RTLIL::SigSpec::extend(int width, bool is_signed)
2109 {
2110 cover("kernel.rtlil.sigspec.extend");
2111
2112 pack();
2113
2114 if (width_ > width)
2115 remove(width, width_ - width);
2116
2117 if (width_ < width) {
2118 RTLIL::SigSpec padding = width_ > 0 ? extract(width_ - 1, 1) : RTLIL::SigSpec(RTLIL::State::S0);
2119 if (!is_signed && padding != RTLIL::SigSpec(RTLIL::State::Sx) && padding != RTLIL::SigSpec(RTLIL::State::Sz) &&
2120 padding != RTLIL::SigSpec(RTLIL::State::Sa) && padding != RTLIL::SigSpec(RTLIL::State::Sm))
2121 padding = RTLIL::SigSpec(RTLIL::State::S0);
2122 while (width_ < width)
2123 append(padding);
2124 }
2125 }
2126
2127 void RTLIL::SigSpec::extend_u0(int width, bool is_signed)
2128 {
2129 cover("kernel.rtlil.sigspec.extend_u0");
2130
2131 pack();
2132
2133 if (width_ > width)
2134 remove(width, width_ - width);
2135
2136 if (width_ < width) {
2137 RTLIL::SigSpec padding = width_ > 0 ? extract(width_ - 1, 1) : RTLIL::SigSpec(RTLIL::State::S0);
2138 if (!is_signed)
2139 padding = RTLIL::SigSpec(RTLIL::State::S0);
2140 while (width_ < width)
2141 append(padding);
2142 }
2143
2144 }
2145
2146 RTLIL::SigSpec RTLIL::SigSpec::repeat(int num) const
2147 {
2148 cover("kernel.rtlil.sigspec.repeat");
2149
2150 RTLIL::SigSpec sig;
2151 for (int i = 0; i < num; i++)
2152 sig.append(*this);
2153 return sig;
2154 }
2155
2156 #ifndef NDEBUG
2157 void RTLIL::SigSpec::check() const
2158 {
2159 if (width_ > 64)
2160 {
2161 cover("kernel.rtlil.sigspec.check.skip");
2162 }
2163 else if (packed())
2164 {
2165 cover("kernel.rtlil.sigspec.check.packed");
2166
2167 int w = 0;
2168 for (size_t i = 0; i < chunks_.size(); i++) {
2169 const RTLIL::SigChunk chunk = chunks_[i];
2170 if (chunk.wire == NULL) {
2171 if (i > 0)
2172 assert(chunks_[i-1].wire != NULL);
2173 assert(chunk.offset == 0);
2174 assert(chunk.data.bits.size() == (size_t)chunk.width);
2175 } else {
2176 if (i > 0 && chunks_[i-1].wire == chunk.wire)
2177 assert(chunk.offset != chunks_[i-1].offset + chunks_[i-1].width);
2178 assert(chunk.offset >= 0);
2179 assert(chunk.width >= 0);
2180 assert(chunk.offset + chunk.width <= chunk.wire->width);
2181 assert(chunk.data.bits.size() == 0);
2182 }
2183 w += chunk.width;
2184 }
2185 assert(w == width_);
2186 assert(bits_.empty());
2187 }
2188 else
2189 {
2190 cover("kernel.rtlil.sigspec.check.unpacked");
2191
2192 assert(width_ == SIZE(bits_));
2193 assert(chunks_.empty());
2194 }
2195 }
2196 #endif
2197
2198 bool RTLIL::SigSpec::operator <(const RTLIL::SigSpec &other) const
2199 {
2200 cover("kernel.rtlil.sigspec.comp_lt");
2201
2202 if (this == &other)
2203 return false;
2204
2205 if (width_ != other.width_)
2206 return width_ < other.width_;
2207
2208 pack();
2209 other.pack();
2210
2211 if (chunks_.size() != other.chunks_.size())
2212 return chunks_.size() < other.chunks_.size();
2213
2214 hash();
2215 other.hash();
2216
2217 if (hash_ != other.hash_)
2218 return hash_ < other.hash_;
2219
2220 for (size_t i = 0; i < chunks_.size(); i++)
2221 if (chunks_[i] != other.chunks_[i]) {
2222 cover("kernel.rtlil.sigspec.comp_lt.hash_collision");
2223 return chunks_[i] < other.chunks_[i];
2224 }
2225
2226 cover("kernel.rtlil.sigspec.comp_lt.equal");
2227 return false;
2228 }
2229
2230 bool RTLIL::SigSpec::operator ==(const RTLIL::SigSpec &other) const
2231 {
2232 cover("kernel.rtlil.sigspec.comp_eq");
2233
2234 if (this == &other)
2235 return true;
2236
2237 if (width_ != other.width_)
2238 return false;
2239
2240 pack();
2241 other.pack();
2242
2243 if (chunks_.size() != chunks_.size())
2244 return false;
2245
2246 hash();
2247 other.hash();
2248
2249 if (hash_ != other.hash_)
2250 return false;
2251
2252 for (size_t i = 0; i < chunks_.size(); i++)
2253 if (chunks_[i] != other.chunks_[i]) {
2254 cover("kernel.rtlil.sigspec.comp_eq.hash_collision");
2255 return false;
2256 }
2257
2258 cover("kernel.rtlil.sigspec.comp_eq.equal");
2259 return true;
2260 }
2261
2262 bool RTLIL::SigSpec::is_wire() const
2263 {
2264 cover("kernel.rtlil.sigspec.is_wire");
2265
2266 pack();
2267 return SIZE(chunks_) == 1 && chunks_[0].wire && chunks_[0].wire->width == width_;
2268 }
2269
2270 bool RTLIL::SigSpec::is_chunk() const
2271 {
2272 cover("kernel.rtlil.sigspec.is_chunk");
2273
2274 pack();
2275 return SIZE(chunks_) == 1;
2276 }
2277
2278 bool RTLIL::SigSpec::is_fully_const() const
2279 {
2280 cover("kernel.rtlil.sigspec.is_fully_const");
2281
2282 pack();
2283 for (auto it = chunks_.begin(); it != chunks_.end(); it++)
2284 if (it->width > 0 && it->wire != NULL)
2285 return false;
2286 return true;
2287 }
2288
2289 bool RTLIL::SigSpec::is_fully_def() const
2290 {
2291 cover("kernel.rtlil.sigspec.is_fully_def");
2292
2293 pack();
2294 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
2295 if (it->width > 0 && it->wire != NULL)
2296 return false;
2297 for (size_t i = 0; i < it->data.bits.size(); i++)
2298 if (it->data.bits[i] != RTLIL::State::S0 && it->data.bits[i] != RTLIL::State::S1)
2299 return false;
2300 }
2301 return true;
2302 }
2303
2304 bool RTLIL::SigSpec::is_fully_undef() const
2305 {
2306 cover("kernel.rtlil.sigspec.is_fully_undef");
2307
2308 pack();
2309 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
2310 if (it->width > 0 && it->wire != NULL)
2311 return false;
2312 for (size_t i = 0; i < it->data.bits.size(); i++)
2313 if (it->data.bits[i] != RTLIL::State::Sx && it->data.bits[i] != RTLIL::State::Sz)
2314 return false;
2315 }
2316 return true;
2317 }
2318
2319 bool RTLIL::SigSpec::has_marked_bits() const
2320 {
2321 cover("kernel.rtlil.sigspec.has_marked_bits");
2322
2323 pack();
2324 for (auto it = chunks_.begin(); it != chunks_.end(); it++)
2325 if (it->width > 0 && it->wire == NULL) {
2326 for (size_t i = 0; i < it->data.bits.size(); i++)
2327 if (it->data.bits[i] == RTLIL::State::Sm)
2328 return true;
2329 }
2330 return false;
2331 }
2332
2333 bool RTLIL::SigSpec::as_bool() const
2334 {
2335 cover("kernel.rtlil.sigspec.as_bool");
2336
2337 pack();
2338 assert(is_fully_const() && SIZE(chunks_) <= 1);
2339 if (width_)
2340 return chunks_[0].data.as_bool();
2341 return false;
2342 }
2343
2344 int RTLIL::SigSpec::as_int() const
2345 {
2346 cover("kernel.rtlil.sigspec.as_int");
2347
2348 pack();
2349 assert(is_fully_const() && SIZE(chunks_) <= 1);
2350 if (width_)
2351 return chunks_[0].data.as_int();
2352 return 0;
2353 }
2354
2355 std::string RTLIL::SigSpec::as_string() const
2356 {
2357 cover("kernel.rtlil.sigspec.as_string");
2358
2359 pack();
2360 std::string str;
2361 for (size_t i = chunks_.size(); i > 0; i--) {
2362 const RTLIL::SigChunk &chunk = chunks_[i-1];
2363 if (chunk.wire != NULL)
2364 for (int j = 0; j < chunk.width; j++)
2365 str += "?";
2366 else
2367 str += chunk.data.as_string();
2368 }
2369 return str;
2370 }
2371
2372 RTLIL::Const RTLIL::SigSpec::as_const() const
2373 {
2374 cover("kernel.rtlil.sigspec.as_const");
2375
2376 pack();
2377 assert(is_fully_const() && SIZE(chunks_) <= 1);
2378 if (width_)
2379 return chunks_[0].data;
2380 return RTLIL::Const();
2381 }
2382
2383 RTLIL::Wire *RTLIL::SigSpec::as_wire() const
2384 {
2385 cover("kernel.rtlil.sigspec.as_wire");
2386
2387 pack();
2388 assert(is_wire());
2389 return chunks_[0].wire;
2390 }
2391
2392 RTLIL::SigChunk RTLIL::SigSpec::as_chunk() const
2393 {
2394 cover("kernel.rtlil.sigspec.as_chunk");
2395
2396 pack();
2397 assert(is_chunk());
2398 return chunks_[0];
2399 }
2400
2401 bool RTLIL::SigSpec::match(std::string pattern) const
2402 {
2403 cover("kernel.rtlil.sigspec.match");
2404
2405 pack();
2406 std::string str = as_string();
2407 assert(pattern.size() == str.size());
2408
2409 for (size_t i = 0; i < pattern.size(); i++) {
2410 if (pattern[i] == ' ')
2411 continue;
2412 if (pattern[i] == '*') {
2413 if (str[i] != 'z' && str[i] != 'x')
2414 return false;
2415 continue;
2416 }
2417 if (pattern[i] != str[i])
2418 return false;
2419 }
2420
2421 return true;
2422 }
2423
2424 std::set<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_set() const
2425 {
2426 cover("kernel.rtlil.sigspec.to_sigbit_set");
2427
2428 pack();
2429 std::set<RTLIL::SigBit> sigbits;
2430 for (auto &c : chunks_)
2431 for (int i = 0; i < c.width; i++)
2432 sigbits.insert(RTLIL::SigBit(c, i));
2433 return sigbits;
2434 }
2435
2436 std::vector<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_vector() const
2437 {
2438 cover("kernel.rtlil.sigspec.to_sigbit_vector");
2439
2440 unpack();
2441 return bits_;
2442 }
2443
2444 RTLIL::SigBit RTLIL::SigSpec::to_single_sigbit() const
2445 {
2446 cover("kernel.rtlil.sigspec.to_single_sigbit");
2447
2448 pack();
2449 log_assert(width_ == 1);
2450 for (auto &c : chunks_)
2451 if (c.width)
2452 return RTLIL::SigBit(c);
2453 log_abort();
2454 }
2455
2456 static void sigspec_parse_split(std::vector<std::string> &tokens, const std::string &text, char sep)
2457 {
2458 size_t start = 0, end = 0;
2459 while ((end = text.find(sep, start)) != std::string::npos) {
2460 tokens.push_back(text.substr(start, end - start));
2461 start = end + 1;
2462 }
2463 tokens.push_back(text.substr(start));
2464 }
2465
2466 static int sigspec_parse_get_dummy_line_num()
2467 {
2468 return 0;
2469 }
2470
2471 bool RTLIL::SigSpec::parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str)
2472 {
2473 cover("kernel.rtlil.sigspec.parse");
2474
2475 std::vector<std::string> tokens;
2476 sigspec_parse_split(tokens, str, ',');
2477
2478 sig = RTLIL::SigSpec();
2479 for (int tokidx = int(tokens.size())-1; tokidx >= 0; tokidx--)
2480 {
2481 std::string netname = tokens[tokidx];
2482 std::string indices;
2483
2484 if (netname.size() == 0)
2485 continue;
2486
2487 if ('0' <= netname[0] && netname[0] <= '9') {
2488 cover("kernel.rtlil.sigspec.parse.const");
2489 AST::get_line_num = sigspec_parse_get_dummy_line_num;
2490 AST::AstNode *ast = VERILOG_FRONTEND::const2ast(netname);
2491 if (ast == NULL)
2492 return false;
2493 sig.append(RTLIL::Const(ast->bits));
2494 delete ast;
2495 continue;
2496 }
2497
2498 if (module == NULL)
2499 return false;
2500
2501 cover("kernel.rtlil.sigspec.parse.net");
2502
2503 if (netname[0] != '$' && netname[0] != '\\')
2504 netname = "\\" + netname;
2505
2506 if (module->wires_.count(netname) == 0) {
2507 size_t indices_pos = netname.size()-1;
2508 if (indices_pos > 2 && netname[indices_pos] == ']')
2509 {
2510 indices_pos--;
2511 while (indices_pos > 0 && ('0' <= netname[indices_pos] && netname[indices_pos] <= '9')) indices_pos--;
2512 if (indices_pos > 0 && netname[indices_pos] == ':') {
2513 indices_pos--;
2514 while (indices_pos > 0 && ('0' <= netname[indices_pos] && netname[indices_pos] <= '9')) indices_pos--;
2515 }
2516 if (indices_pos > 0 && netname[indices_pos] == '[') {
2517 indices = netname.substr(indices_pos);
2518 netname = netname.substr(0, indices_pos);
2519 }
2520 }
2521 }
2522
2523 if (module->wires_.count(netname) == 0)
2524 return false;
2525
2526 RTLIL::Wire *wire = module->wires_.at(netname);
2527 if (!indices.empty()) {
2528 std::vector<std::string> index_tokens;
2529 sigspec_parse_split(index_tokens, indices.substr(1, indices.size()-2), ':');
2530 if (index_tokens.size() == 1) {
2531 cover("kernel.rtlil.sigspec.parse.bit_sel");
2532 sig.append(RTLIL::SigSpec(wire, atoi(index_tokens.at(0).c_str())));
2533 } else {
2534 cover("kernel.rtlil.sigspec.parse.part_sel");
2535 int a = atoi(index_tokens.at(0).c_str());
2536 int b = atoi(index_tokens.at(1).c_str());
2537 if (a > b) {
2538 int tmp = a;
2539 a = b, b = tmp;
2540 }
2541 sig.append(RTLIL::SigSpec(wire, a, b-a+1));
2542 }
2543 } else
2544 sig.append(wire);
2545 }
2546
2547 return true;
2548 }
2549
2550 bool RTLIL::SigSpec::parse_sel(RTLIL::SigSpec &sig, RTLIL::Design *design, RTLIL::Module *module, std::string str)
2551 {
2552 if (str.empty() || str[0] != '@')
2553 return parse(sig, module, str);
2554
2555 cover("kernel.rtlil.sigspec.parse.sel");
2556
2557 str = RTLIL::escape_id(str.substr(1));
2558 if (design->selection_vars.count(str) == 0)
2559 return false;
2560
2561 sig = RTLIL::SigSpec();
2562 RTLIL::Selection &sel = design->selection_vars.at(str);
2563 for (auto &it : module->wires_)
2564 if (sel.selected_member(module->name, it.first))
2565 sig.append(it.second);
2566
2567 return true;
2568 }
2569
2570 bool RTLIL::SigSpec::parse_rhs(const RTLIL::SigSpec &lhs, RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str)
2571 {
2572 if (str == "0") {
2573 cover("kernel.rtlil.sigspec.parse.rhs_zeros");
2574 sig = RTLIL::SigSpec(RTLIL::State::S0, lhs.width_);
2575 return true;
2576 }
2577
2578 if (str == "~0") {
2579 cover("kernel.rtlil.sigspec.parse.rhs_ones");
2580 sig = RTLIL::SigSpec(RTLIL::State::S1, lhs.width_);
2581 return true;
2582 }
2583
2584 if (lhs.chunks_.size() == 1) {
2585 char *p = (char*)str.c_str(), *endptr;
2586 long long int val = strtoll(p, &endptr, 10);
2587 if (endptr && endptr != p && *endptr == 0) {
2588 sig = RTLIL::SigSpec(val, lhs.width_);
2589 cover("kernel.rtlil.sigspec.parse.rhs_dec");
2590 return true;
2591 }
2592 }
2593
2594 return parse(sig, module, str);
2595 }
2596
2597 RTLIL::CaseRule::~CaseRule()
2598 {
2599 for (auto it = switches.begin(); it != switches.end(); it++)
2600 delete *it;
2601 }
2602
2603 RTLIL::CaseRule *RTLIL::CaseRule::clone() const
2604 {
2605 RTLIL::CaseRule *new_caserule = new RTLIL::CaseRule;
2606 new_caserule->compare = compare;
2607 new_caserule->actions = actions;
2608 for (auto &it : switches)
2609 new_caserule->switches.push_back(it->clone());
2610 return new_caserule;
2611 }
2612
2613 RTLIL::SwitchRule::~SwitchRule()
2614 {
2615 for (auto it = cases.begin(); it != cases.end(); it++)
2616 delete *it;
2617 }
2618
2619 RTLIL::SwitchRule *RTLIL::SwitchRule::clone() const
2620 {
2621 RTLIL::SwitchRule *new_switchrule = new RTLIL::SwitchRule;
2622 new_switchrule->signal = signal;
2623 new_switchrule->attributes = attributes;
2624 for (auto &it : cases)
2625 new_switchrule->cases.push_back(it->clone());
2626 return new_switchrule;
2627
2628 }
2629
2630 RTLIL::SyncRule *RTLIL::SyncRule::clone() const
2631 {
2632 RTLIL::SyncRule *new_syncrule = new RTLIL::SyncRule;
2633 new_syncrule->type = type;
2634 new_syncrule->signal = signal;
2635 new_syncrule->actions = actions;
2636 return new_syncrule;
2637 }
2638
2639 RTLIL::Process::~Process()
2640 {
2641 for (auto it = syncs.begin(); it != syncs.end(); it++)
2642 delete *it;
2643 }
2644
2645 RTLIL::Process *RTLIL::Process::clone() const
2646 {
2647 RTLIL::Process *new_proc = new RTLIL::Process;
2648
2649 new_proc->name = name;
2650 new_proc->attributes = attributes;
2651
2652 RTLIL::CaseRule *rc_ptr = root_case.clone();
2653 new_proc->root_case = *rc_ptr;
2654 rc_ptr->switches.clear();
2655 delete rc_ptr;
2656
2657 for (auto &it : syncs)
2658 new_proc->syncs.push_back(it->clone());
2659
2660 return new_proc;
2661 }
2662