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Added support for truncating of wires to wreduce pass
[yosys.git] / kernel / rtlil.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 #include "kernel/yosys.h"
21 #include "frontends/verilog/verilog_frontend.h"
22 #include "backends/ilang/ilang_backend.h"
23
24 #include <string.h>
25 #include <algorithm>
26
27 YOSYS_NAMESPACE_BEGIN
28
29 std::vector<int> RTLIL::IdString::global_refcount_storage_;
30 std::vector<char*> RTLIL::IdString::global_id_storage_;
31 std::map<char*, int, RTLIL::IdString::char_ptr_cmp> RTLIL::IdString::global_id_index_;
32 std::vector<int> RTLIL::IdString::global_free_idx_list_;
33
34 RTLIL::Const::Const()
35 {
36 flags = RTLIL::CONST_FLAG_NONE;
37 }
38
39 RTLIL::Const::Const(std::string str)
40 {
41 flags = RTLIL::CONST_FLAG_STRING;
42 for (int i = str.size()-1; i >= 0; i--) {
43 unsigned char ch = str[i];
44 for (int j = 0; j < 8; j++) {
45 bits.push_back((ch & 1) != 0 ? RTLIL::S1 : RTLIL::S0);
46 ch = ch >> 1;
47 }
48 }
49 }
50
51 RTLIL::Const::Const(int val, int width)
52 {
53 flags = RTLIL::CONST_FLAG_NONE;
54 for (int i = 0; i < width; i++) {
55 bits.push_back((val & 1) != 0 ? RTLIL::S1 : RTLIL::S0);
56 val = val >> 1;
57 }
58 }
59
60 RTLIL::Const::Const(RTLIL::State bit, int width)
61 {
62 flags = RTLIL::CONST_FLAG_NONE;
63 for (int i = 0; i < width; i++)
64 bits.push_back(bit);
65 }
66
67 bool RTLIL::Const::operator <(const RTLIL::Const &other) const
68 {
69 if (bits.size() != other.bits.size())
70 return bits.size() < other.bits.size();
71 for (size_t i = 0; i < bits.size(); i++)
72 if (bits[i] != other.bits[i])
73 return bits[i] < other.bits[i];
74 return false;
75 }
76
77 bool RTLIL::Const::operator ==(const RTLIL::Const &other) const
78 {
79 return bits == other.bits;
80 }
81
82 bool RTLIL::Const::operator !=(const RTLIL::Const &other) const
83 {
84 return bits != other.bits;
85 }
86
87 bool RTLIL::Const::as_bool() const
88 {
89 for (size_t i = 0; i < bits.size(); i++)
90 if (bits[i] == RTLIL::S1)
91 return true;
92 return false;
93 }
94
95 int RTLIL::Const::as_int() const
96 {
97 int ret = 0;
98 for (size_t i = 0; i < bits.size() && i < 32; i++)
99 if (bits[i] == RTLIL::S1)
100 ret |= 1 << i;
101 return ret;
102 }
103
104 std::string RTLIL::Const::as_string() const
105 {
106 std::string ret;
107 for (size_t i = bits.size(); i > 0; i--)
108 switch (bits[i-1]) {
109 case S0: ret += "0"; break;
110 case S1: ret += "1"; break;
111 case Sx: ret += "x"; break;
112 case Sz: ret += "z"; break;
113 case Sa: ret += "-"; break;
114 case Sm: ret += "m"; break;
115 }
116 return ret;
117 }
118
119 std::string RTLIL::Const::decode_string() const
120 {
121 std::string string;
122 std::vector <char> string_chars;
123 for (int i = 0; i < int (bits.size()); i += 8) {
124 char ch = 0;
125 for (int j = 0; j < 8 && i + j < int (bits.size()); j++)
126 if (bits[i + j] == RTLIL::State::S1)
127 ch |= 1 << j;
128 if (ch != 0)
129 string_chars.push_back(ch);
130 }
131 for (int i = int (string_chars.size()) - 1; i >= 0; i--)
132 string += string_chars[i];
133 return string;
134 }
135
136 bool RTLIL::Selection::selected_module(RTLIL::IdString mod_name) const
137 {
138 if (full_selection)
139 return true;
140 if (selected_modules.count(mod_name) > 0)
141 return true;
142 if (selected_members.count(mod_name) > 0)
143 return true;
144 return false;
145 }
146
147 bool RTLIL::Selection::selected_whole_module(RTLIL::IdString mod_name) const
148 {
149 if (full_selection)
150 return true;
151 if (selected_modules.count(mod_name) > 0)
152 return true;
153 return false;
154 }
155
156 bool RTLIL::Selection::selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const
157 {
158 if (full_selection)
159 return true;
160 if (selected_modules.count(mod_name) > 0)
161 return true;
162 if (selected_members.count(mod_name) > 0)
163 if (selected_members.at(mod_name).count(memb_name) > 0)
164 return true;
165 return false;
166 }
167
168 void RTLIL::Selection::optimize(RTLIL::Design *design)
169 {
170 if (full_selection) {
171 selected_modules.clear();
172 selected_members.clear();
173 return;
174 }
175
176 std::vector<RTLIL::IdString> del_list, add_list;
177
178 del_list.clear();
179 for (auto mod_name : selected_modules) {
180 if (design->modules_.count(mod_name) == 0)
181 del_list.push_back(mod_name);
182 selected_members.erase(mod_name);
183 }
184 for (auto mod_name : del_list)
185 selected_modules.erase(mod_name);
186
187 del_list.clear();
188 for (auto &it : selected_members)
189 if (design->modules_.count(it.first) == 0)
190 del_list.push_back(it.first);
191 for (auto mod_name : del_list)
192 selected_members.erase(mod_name);
193
194 for (auto &it : selected_members) {
195 del_list.clear();
196 for (auto memb_name : it.second)
197 if (design->modules_[it.first]->count_id(memb_name) == 0)
198 del_list.push_back(memb_name);
199 for (auto memb_name : del_list)
200 it.second.erase(memb_name);
201 }
202
203 del_list.clear();
204 add_list.clear();
205 for (auto &it : selected_members)
206 if (it.second.size() == 0)
207 del_list.push_back(it.first);
208 else if (it.second.size() == design->modules_[it.first]->wires_.size() + design->modules_[it.first]->memories.size() +
209 design->modules_[it.first]->cells_.size() + design->modules_[it.first]->processes.size())
210 add_list.push_back(it.first);
211 for (auto mod_name : del_list)
212 selected_members.erase(mod_name);
213 for (auto mod_name : add_list) {
214 selected_members.erase(mod_name);
215 selected_modules.insert(mod_name);
216 }
217
218 if (selected_modules.size() == design->modules_.size()) {
219 full_selection = true;
220 selected_modules.clear();
221 selected_members.clear();
222 }
223 }
224
225 RTLIL::Design::Design()
226 {
227 refcount_modules_ = 0;
228 }
229
230 RTLIL::Design::~Design()
231 {
232 for (auto it = modules_.begin(); it != modules_.end(); it++)
233 delete it->second;
234 }
235
236 RTLIL::ObjRange<RTLIL::Module*> RTLIL::Design::modules()
237 {
238 return RTLIL::ObjRange<RTLIL::Module*>(&modules_, &refcount_modules_);
239 }
240
241 RTLIL::Module *RTLIL::Design::module(RTLIL::IdString name)
242 {
243 return modules_.count(name) ? modules_.at(name) : NULL;
244 }
245
246 void RTLIL::Design::add(RTLIL::Module *module)
247 {
248 log_assert(modules_.count(module->name) == 0);
249 log_assert(refcount_modules_ == 0);
250 modules_[module->name] = module;
251 module->design = this;
252
253 for (auto mon : monitors)
254 mon->notify_module_add(module);
255 }
256
257 RTLIL::Module *RTLIL::Design::addModule(RTLIL::IdString name)
258 {
259 log_assert(modules_.count(name) == 0);
260 log_assert(refcount_modules_ == 0);
261
262 RTLIL::Module *module = new RTLIL::Module;
263 modules_[name] = module;
264 module->design = this;
265 module->name = name;
266
267 for (auto mon : monitors)
268 mon->notify_module_add(module);
269
270 return module;
271 }
272
273 void RTLIL::Design::remove(RTLIL::Module *module)
274 {
275 for (auto mon : monitors)
276 mon->notify_module_del(module);
277
278 log_assert(modules_.at(module->name) == module);
279 modules_.erase(module->name);
280 delete module;
281 }
282
283 void RTLIL::Design::check()
284 {
285 #ifndef NDEBUG
286 for (auto &it : modules_) {
287 log_assert(this == it.second->design);
288 log_assert(it.first == it.second->name);
289 log_assert(!it.first.empty());
290 it.second->check();
291 }
292 #endif
293 }
294
295 void RTLIL::Design::optimize()
296 {
297 for (auto &it : modules_)
298 it.second->optimize();
299 for (auto &it : selection_stack)
300 it.optimize(this);
301 for (auto &it : selection_vars)
302 it.second.optimize(this);
303 }
304
305 bool RTLIL::Design::selected_module(RTLIL::IdString mod_name) const
306 {
307 if (!selected_active_module.empty() && mod_name != selected_active_module)
308 return false;
309 if (selection_stack.size() == 0)
310 return true;
311 return selection_stack.back().selected_module(mod_name);
312 }
313
314 bool RTLIL::Design::selected_whole_module(RTLIL::IdString mod_name) const
315 {
316 if (!selected_active_module.empty() && mod_name != selected_active_module)
317 return false;
318 if (selection_stack.size() == 0)
319 return true;
320 return selection_stack.back().selected_whole_module(mod_name);
321 }
322
323 bool RTLIL::Design::selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const
324 {
325 if (!selected_active_module.empty() && mod_name != selected_active_module)
326 return false;
327 if (selection_stack.size() == 0)
328 return true;
329 return selection_stack.back().selected_member(mod_name, memb_name);
330 }
331
332 bool RTLIL::Design::selected_module(RTLIL::Module *mod) const
333 {
334 return selected_module(mod->name);
335 }
336
337 bool RTLIL::Design::selected_whole_module(RTLIL::Module *mod) const
338 {
339 return selected_whole_module(mod->name);
340 }
341
342 std::vector<RTLIL::Module*> RTLIL::Design::selected_modules() const
343 {
344 std::vector<RTLIL::Module*> result;
345 result.reserve(modules_.size());
346 for (auto &it : modules_)
347 if (selected_module(it.first))
348 result.push_back(it.second);
349 return result;
350 }
351
352 std::vector<RTLIL::Module*> RTLIL::Design::selected_whole_modules() const
353 {
354 std::vector<RTLIL::Module*> result;
355 result.reserve(modules_.size());
356 for (auto &it : modules_)
357 if (selected_whole_module(it.first))
358 result.push_back(it.second);
359 return result;
360 }
361
362 std::vector<RTLIL::Module*> RTLIL::Design::selected_whole_modules_warn() const
363 {
364 std::vector<RTLIL::Module*> result;
365 result.reserve(modules_.size());
366 for (auto &it : modules_)
367 if (selected_whole_module(it.first))
368 result.push_back(it.second);
369 else if (selected_module(it.first))
370 log("Warning: Ignoring partially selected module %s.\n", log_id(it.first));
371 return result;
372 }
373
374 RTLIL::Module::Module()
375 {
376 design = nullptr;
377 refcount_wires_ = 0;
378 refcount_cells_ = 0;
379 }
380
381 RTLIL::Module::~Module()
382 {
383 for (auto it = wires_.begin(); it != wires_.end(); it++)
384 delete it->second;
385 for (auto it = memories.begin(); it != memories.end(); it++)
386 delete it->second;
387 for (auto it = cells_.begin(); it != cells_.end(); it++)
388 delete it->second;
389 for (auto it = processes.begin(); it != processes.end(); it++)
390 delete it->second;
391 }
392
393 RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, std::map<RTLIL::IdString, RTLIL::Const>)
394 {
395 log_error("Module `%s' is used with parameters but is not parametric!\n", id2cstr(name));
396 }
397
398 size_t RTLIL::Module::count_id(RTLIL::IdString id)
399 {
400 return wires_.count(id) + memories.count(id) + cells_.count(id) + processes.count(id);
401 }
402
403 #ifndef NDEBUG
404 namespace {
405 struct InternalCellChecker
406 {
407 RTLIL::Module *module;
408 RTLIL::Cell *cell;
409 std::set<RTLIL::IdString> expected_params, expected_ports;
410
411 InternalCellChecker(RTLIL::Module *module, RTLIL::Cell *cell) : module(module), cell(cell) { }
412
413 void error(int linenr)
414 {
415 char *ptr;
416 size_t size;
417
418 FILE *f = open_memstream(&ptr, &size);
419 ILANG_BACKEND::dump_cell(f, " ", cell);
420 fputc(0, f);
421 fclose(f);
422
423 log_error("Found error in internal cell %s%s%s (%s) at %s:%d:\n%s",
424 module ? module->name.c_str() : "", module ? "." : "",
425 cell->name.c_str(), cell->type.c_str(), __FILE__, linenr, ptr);
426 }
427
428 int param(const char *name)
429 {
430 if (cell->parameters.count(name) == 0)
431 error(__LINE__);
432 expected_params.insert(name);
433 return cell->parameters.at(name).as_int();
434 }
435
436 int param_bool(const char *name)
437 {
438 int v = param(name);
439 if (cell->parameters.at(name).bits.size() > 32)
440 error(__LINE__);
441 if (v != 0 && v != 1)
442 error(__LINE__);
443 return v;
444 }
445
446 void param_bits(const char *name, int width)
447 {
448 param(name);
449 if (int(cell->parameters.at(name).bits.size()) != width)
450 error(__LINE__);
451 }
452
453 void port(const char *name, int width)
454 {
455 if (!cell->hasPort(name))
456 error(__LINE__);
457 if (cell->getPort(name).size() != width)
458 error(__LINE__);
459 expected_ports.insert(name);
460 }
461
462 void check_expected(bool check_matched_sign = true)
463 {
464 for (auto &para : cell->parameters)
465 if (expected_params.count(para.first) == 0)
466 error(__LINE__);
467 for (auto &conn : cell->connections())
468 if (expected_ports.count(conn.first) == 0)
469 error(__LINE__);
470
471 if (expected_params.count("\\A_SIGNED") != 0 && expected_params.count("\\B_SIGNED") && check_matched_sign) {
472 bool a_is_signed = param("\\A_SIGNED") != 0;
473 bool b_is_signed = param("\\B_SIGNED") != 0;
474 if (a_is_signed != b_is_signed)
475 error(__LINE__);
476 }
477 }
478
479 void check_gate(const char *ports)
480 {
481 if (cell->parameters.size() != 0)
482 error(__LINE__);
483
484 for (const char *p = ports; *p; p++) {
485 char portname[3] = { '\\', *p, 0 };
486 if (!cell->hasPort(portname))
487 error(__LINE__);
488 if (cell->getPort(portname).size() != 1)
489 error(__LINE__);
490 }
491
492 for (auto &conn : cell->connections()) {
493 if (conn.first.size() != 2 || conn.first[0] != '\\')
494 error(__LINE__);
495 if (strchr(ports, conn.first[1]) == NULL)
496 error(__LINE__);
497 }
498 }
499
500 void check()
501 {
502 if (cell->type.substr(0, 1) != "$" || cell->type.substr(0, 3) == "$__" || cell->type.substr(0, 8) == "$paramod" ||
503 cell->type.substr(0, 9) == "$verific$" || cell->type.substr(0, 7) == "$array:" || cell->type.substr(0, 8) == "$extern:")
504 return;
505
506 if (cell->type == "$not" || cell->type == "$pos" || cell->type == "$bu0" || cell->type == "$neg") {
507 param_bool("\\A_SIGNED");
508 port("\\A", param("\\A_WIDTH"));
509 port("\\Y", param("\\Y_WIDTH"));
510 check_expected();
511 return;
512 }
513
514 if (cell->type == "$and" || cell->type == "$or" || cell->type == "$xor" || cell->type == "$xnor") {
515 param_bool("\\A_SIGNED");
516 param_bool("\\B_SIGNED");
517 port("\\A", param("\\A_WIDTH"));
518 port("\\B", param("\\B_WIDTH"));
519 port("\\Y", param("\\Y_WIDTH"));
520 check_expected();
521 return;
522 }
523
524 if (cell->type == "$reduce_and" || cell->type == "$reduce_or" || cell->type == "$reduce_xor" ||
525 cell->type == "$reduce_xnor" || cell->type == "$reduce_bool") {
526 param_bool("\\A_SIGNED");
527 port("\\A", param("\\A_WIDTH"));
528 port("\\Y", param("\\Y_WIDTH"));
529 check_expected();
530 return;
531 }
532
533 if (cell->type == "$shl" || cell->type == "$shr" || cell->type == "$sshl" || cell->type == "$sshr" ||
534 cell->type == "$shift" || cell->type == "$shiftx") {
535 param_bool("\\A_SIGNED");
536 param_bool("\\B_SIGNED");
537 port("\\A", param("\\A_WIDTH"));
538 port("\\B", param("\\B_WIDTH"));
539 port("\\Y", param("\\Y_WIDTH"));
540 check_expected(false);
541 return;
542 }
543
544 if (cell->type == "$lt" || cell->type == "$le" || cell->type == "$eq" || cell->type == "$ne" ||
545 cell->type == "$eqx" || cell->type == "$nex" || cell->type == "$ge" || cell->type == "$gt") {
546 param_bool("\\A_SIGNED");
547 param_bool("\\B_SIGNED");
548 port("\\A", param("\\A_WIDTH"));
549 port("\\B", param("\\B_WIDTH"));
550 port("\\Y", param("\\Y_WIDTH"));
551 check_expected();
552 return;
553 }
554
555 if (cell->type == "$add" || cell->type == "$sub" || cell->type == "$mul" || cell->type == "$div" ||
556 cell->type == "$mod" || cell->type == "$pow") {
557 param_bool("\\A_SIGNED");
558 param_bool("\\B_SIGNED");
559 port("\\A", param("\\A_WIDTH"));
560 port("\\B", param("\\B_WIDTH"));
561 port("\\Y", param("\\Y_WIDTH"));
562 check_expected(cell->type != "$pow");
563 return;
564 }
565
566 if (cell->type == "$logic_not") {
567 param_bool("\\A_SIGNED");
568 port("\\A", param("\\A_WIDTH"));
569 port("\\Y", param("\\Y_WIDTH"));
570 check_expected();
571 return;
572 }
573
574 if (cell->type == "$logic_and" || cell->type == "$logic_or") {
575 param_bool("\\A_SIGNED");
576 param_bool("\\B_SIGNED");
577 port("\\A", param("\\A_WIDTH"));
578 port("\\B", param("\\B_WIDTH"));
579 port("\\Y", param("\\Y_WIDTH"));
580 check_expected(false);
581 return;
582 }
583
584 if (cell->type == "$slice") {
585 param("\\OFFSET");
586 port("\\A", param("\\A_WIDTH"));
587 port("\\Y", param("\\Y_WIDTH"));
588 if (param("\\OFFSET") + param("\\Y_WIDTH") > param("\\A_WIDTH"))
589 error(__LINE__);
590 check_expected();
591 return;
592 }
593
594 if (cell->type == "$concat") {
595 port("\\A", param("\\A_WIDTH"));
596 port("\\B", param("\\B_WIDTH"));
597 port("\\Y", param("\\A_WIDTH") + param("\\B_WIDTH"));
598 check_expected();
599 return;
600 }
601
602 if (cell->type == "$mux") {
603 port("\\A", param("\\WIDTH"));
604 port("\\B", param("\\WIDTH"));
605 port("\\S", 1);
606 port("\\Y", param("\\WIDTH"));
607 check_expected();
608 return;
609 }
610
611 if (cell->type == "$pmux" || cell->type == "$safe_pmux") {
612 port("\\A", param("\\WIDTH"));
613 port("\\B", param("\\WIDTH") * param("\\S_WIDTH"));
614 port("\\S", param("\\S_WIDTH"));
615 port("\\Y", param("\\WIDTH"));
616 check_expected();
617 return;
618 }
619
620 if (cell->type == "$lut") {
621 param("\\LUT");
622 port("\\I", param("\\WIDTH"));
623 port("\\O", 1);
624 check_expected();
625 return;
626 }
627
628 if (cell->type == "$sr") {
629 param_bool("\\SET_POLARITY");
630 param_bool("\\CLR_POLARITY");
631 port("\\SET", param("\\WIDTH"));
632 port("\\CLR", param("\\WIDTH"));
633 port("\\Q", param("\\WIDTH"));
634 check_expected();
635 return;
636 }
637
638 if (cell->type == "$dff") {
639 param_bool("\\CLK_POLARITY");
640 port("\\CLK", 1);
641 port("\\D", param("\\WIDTH"));
642 port("\\Q", param("\\WIDTH"));
643 check_expected();
644 return;
645 }
646
647 if (cell->type == "$dffsr") {
648 param_bool("\\CLK_POLARITY");
649 param_bool("\\SET_POLARITY");
650 param_bool("\\CLR_POLARITY");
651 port("\\CLK", 1);
652 port("\\SET", param("\\WIDTH"));
653 port("\\CLR", param("\\WIDTH"));
654 port("\\D", param("\\WIDTH"));
655 port("\\Q", param("\\WIDTH"));
656 check_expected();
657 return;
658 }
659
660 if (cell->type == "$adff") {
661 param_bool("\\CLK_POLARITY");
662 param_bool("\\ARST_POLARITY");
663 param_bits("\\ARST_VALUE", param("\\WIDTH"));
664 port("\\CLK", 1);
665 port("\\ARST", 1);
666 port("\\D", param("\\WIDTH"));
667 port("\\Q", param("\\WIDTH"));
668 check_expected();
669 return;
670 }
671
672 if (cell->type == "$dlatch") {
673 param_bool("\\EN_POLARITY");
674 port("\\EN", 1);
675 port("\\D", param("\\WIDTH"));
676 port("\\Q", param("\\WIDTH"));
677 check_expected();
678 return;
679 }
680
681 if (cell->type == "$dlatchsr") {
682 param_bool("\\EN_POLARITY");
683 param_bool("\\SET_POLARITY");
684 param_bool("\\CLR_POLARITY");
685 port("\\EN", 1);
686 port("\\SET", param("\\WIDTH"));
687 port("\\CLR", param("\\WIDTH"));
688 port("\\D", param("\\WIDTH"));
689 port("\\Q", param("\\WIDTH"));
690 check_expected();
691 return;
692 }
693
694 if (cell->type == "$fsm") {
695 param("\\NAME");
696 param_bool("\\CLK_POLARITY");
697 param_bool("\\ARST_POLARITY");
698 param("\\STATE_BITS");
699 param("\\STATE_NUM");
700 param("\\STATE_NUM_LOG2");
701 param("\\STATE_RST");
702 param_bits("\\STATE_TABLE", param("\\STATE_BITS") * param("\\STATE_NUM"));
703 param("\\TRANS_NUM");
704 param_bits("\\TRANS_TABLE", param("\\TRANS_NUM") * (2*param("\\STATE_NUM_LOG2") + param("\\CTRL_IN_WIDTH") + param("\\CTRL_OUT_WIDTH")));
705 port("\\CLK", 1);
706 port("\\ARST", 1);
707 port("\\CTRL_IN", param("\\CTRL_IN_WIDTH"));
708 port("\\CTRL_OUT", param("\\CTRL_OUT_WIDTH"));
709 check_expected();
710 return;
711 }
712
713 if (cell->type == "$memrd") {
714 param("\\MEMID");
715 param_bool("\\CLK_ENABLE");
716 param_bool("\\CLK_POLARITY");
717 param_bool("\\TRANSPARENT");
718 port("\\CLK", 1);
719 port("\\ADDR", param("\\ABITS"));
720 port("\\DATA", param("\\WIDTH"));
721 check_expected();
722 return;
723 }
724
725 if (cell->type == "$memwr") {
726 param("\\MEMID");
727 param_bool("\\CLK_ENABLE");
728 param_bool("\\CLK_POLARITY");
729 param("\\PRIORITY");
730 port("\\CLK", 1);
731 port("\\EN", param("\\WIDTH"));
732 port("\\ADDR", param("\\ABITS"));
733 port("\\DATA", param("\\WIDTH"));
734 check_expected();
735 return;
736 }
737
738 if (cell->type == "$mem") {
739 param("\\MEMID");
740 param("\\SIZE");
741 param("\\OFFSET");
742 param_bits("\\RD_CLK_ENABLE", param("\\RD_PORTS"));
743 param_bits("\\RD_CLK_POLARITY", param("\\RD_PORTS"));
744 param_bits("\\RD_TRANSPARENT", param("\\RD_PORTS"));
745 param_bits("\\WR_CLK_ENABLE", param("\\WR_PORTS"));
746 param_bits("\\WR_CLK_POLARITY", param("\\WR_PORTS"));
747 port("\\RD_CLK", param("\\RD_PORTS"));
748 port("\\RD_ADDR", param("\\RD_PORTS") * param("\\ABITS"));
749 port("\\RD_DATA", param("\\RD_PORTS") * param("\\WIDTH"));
750 port("\\WR_CLK", param("\\WR_PORTS"));
751 port("\\WR_EN", param("\\WR_PORTS") * param("\\WIDTH"));
752 port("\\WR_ADDR", param("\\WR_PORTS") * param("\\ABITS"));
753 port("\\WR_DATA", param("\\WR_PORTS") * param("\\WIDTH"));
754 check_expected();
755 return;
756 }
757
758 if (cell->type == "$assert") {
759 port("\\A", 1);
760 port("\\EN", 1);
761 check_expected();
762 return;
763 }
764
765 if (cell->type == "$_INV_") { check_gate("AY"); return; }
766 if (cell->type == "$_AND_") { check_gate("ABY"); return; }
767 if (cell->type == "$_OR_") { check_gate("ABY"); return; }
768 if (cell->type == "$_XOR_") { check_gate("ABY"); return; }
769 if (cell->type == "$_MUX_") { check_gate("ABSY"); return; }
770
771 if (cell->type == "$_SR_NN_") { check_gate("SRQ"); return; }
772 if (cell->type == "$_SR_NP_") { check_gate("SRQ"); return; }
773 if (cell->type == "$_SR_PN_") { check_gate("SRQ"); return; }
774 if (cell->type == "$_SR_PP_") { check_gate("SRQ"); return; }
775
776 if (cell->type == "$_DFF_N_") { check_gate("DQC"); return; }
777 if (cell->type == "$_DFF_P_") { check_gate("DQC"); return; }
778
779 if (cell->type == "$_DFF_NN0_") { check_gate("DQCR"); return; }
780 if (cell->type == "$_DFF_NN1_") { check_gate("DQCR"); return; }
781 if (cell->type == "$_DFF_NP0_") { check_gate("DQCR"); return; }
782 if (cell->type == "$_DFF_NP1_") { check_gate("DQCR"); return; }
783 if (cell->type == "$_DFF_PN0_") { check_gate("DQCR"); return; }
784 if (cell->type == "$_DFF_PN1_") { check_gate("DQCR"); return; }
785 if (cell->type == "$_DFF_PP0_") { check_gate("DQCR"); return; }
786 if (cell->type == "$_DFF_PP1_") { check_gate("DQCR"); return; }
787
788 if (cell->type == "$_DFFSR_NNN_") { check_gate("CSRDQ"); return; }
789 if (cell->type == "$_DFFSR_NNP_") { check_gate("CSRDQ"); return; }
790 if (cell->type == "$_DFFSR_NPN_") { check_gate("CSRDQ"); return; }
791 if (cell->type == "$_DFFSR_NPP_") { check_gate("CSRDQ"); return; }
792 if (cell->type == "$_DFFSR_PNN_") { check_gate("CSRDQ"); return; }
793 if (cell->type == "$_DFFSR_PNP_") { check_gate("CSRDQ"); return; }
794 if (cell->type == "$_DFFSR_PPN_") { check_gate("CSRDQ"); return; }
795 if (cell->type == "$_DFFSR_PPP_") { check_gate("CSRDQ"); return; }
796
797 if (cell->type == "$_DLATCH_N_") { check_gate("EDQ"); return; }
798 if (cell->type == "$_DLATCH_P_") { check_gate("EDQ"); return; }
799
800 if (cell->type == "$_DLATCHSR_NNN_") { check_gate("ESRDQ"); return; }
801 if (cell->type == "$_DLATCHSR_NNP_") { check_gate("ESRDQ"); return; }
802 if (cell->type == "$_DLATCHSR_NPN_") { check_gate("ESRDQ"); return; }
803 if (cell->type == "$_DLATCHSR_NPP_") { check_gate("ESRDQ"); return; }
804 if (cell->type == "$_DLATCHSR_PNN_") { check_gate("ESRDQ"); return; }
805 if (cell->type == "$_DLATCHSR_PNP_") { check_gate("ESRDQ"); return; }
806 if (cell->type == "$_DLATCHSR_PPN_") { check_gate("ESRDQ"); return; }
807 if (cell->type == "$_DLATCHSR_PPP_") { check_gate("ESRDQ"); return; }
808
809 error(__LINE__);
810 }
811 };
812 }
813 #endif
814
815 void RTLIL::Module::check()
816 {
817 #ifndef NDEBUG
818 std::vector<bool> ports_declared;
819 for (auto &it : wires_) {
820 log_assert(this == it.second->module);
821 log_assert(it.first == it.second->name);
822 log_assert(!it.first.empty());
823 log_assert(it.second->width >= 0);
824 log_assert(it.second->port_id >= 0);
825 for (auto &it2 : it.second->attributes)
826 log_assert(!it2.first.empty());
827 if (it.second->port_id) {
828 log_assert(it.second->port_input || it.second->port_output);
829 if (SIZE(ports_declared) < it.second->port_id)
830 ports_declared.resize(it.second->port_id);
831 log_assert(ports_declared[it.second->port_id-1] == false);
832 ports_declared[it.second->port_id-1] = true;
833 } else
834 log_assert(!it.second->port_input && !it.second->port_output);
835 }
836 for (auto port_declared : ports_declared)
837 log_assert(port_declared == true);
838
839 for (auto &it : memories) {
840 log_assert(it.first == it.second->name);
841 log_assert(!it.first.empty());
842 log_assert(it.second->width >= 0);
843 log_assert(it.second->size >= 0);
844 for (auto &it2 : it.second->attributes)
845 log_assert(!it2.first.empty());
846 }
847
848 for (auto &it : cells_) {
849 log_assert(this == it.second->module);
850 log_assert(it.first == it.second->name);
851 log_assert(!it.first.empty());
852 log_assert(!it.second->type.empty());
853 for (auto &it2 : it.second->connections()) {
854 log_assert(!it2.first.empty());
855 it2.second.check();
856 }
857 for (auto &it2 : it.second->attributes)
858 log_assert(!it2.first.empty());
859 for (auto &it2 : it.second->parameters)
860 log_assert(!it2.first.empty());
861 InternalCellChecker checker(this, it.second);
862 checker.check();
863 }
864
865 for (auto &it : processes) {
866 log_assert(it.first == it.second->name);
867 log_assert(!it.first.empty());
868 // FIXME: More checks here..
869 }
870
871 for (auto &it : connections_) {
872 log_assert(it.first.size() == it.second.size());
873 it.first.check();
874 it.second.check();
875 }
876
877 for (auto &it : attributes)
878 log_assert(!it.first.empty());
879 #endif
880 }
881
882 void RTLIL::Module::optimize()
883 {
884 }
885
886 void RTLIL::Module::cloneInto(RTLIL::Module *new_mod) const
887 {
888 log_assert(new_mod->refcount_wires_ == 0);
889 log_assert(new_mod->refcount_cells_ == 0);
890
891 new_mod->connections_ = connections_;
892 new_mod->attributes = attributes;
893
894 for (auto &it : wires_)
895 new_mod->addWire(it.first, it.second);
896
897 for (auto &it : memories)
898 new_mod->memories[it.first] = new RTLIL::Memory(*it.second);
899
900 for (auto &it : cells_)
901 new_mod->addCell(it.first, it.second);
902
903 for (auto &it : processes)
904 new_mod->processes[it.first] = it.second->clone();
905
906 struct RewriteSigSpecWorker
907 {
908 RTLIL::Module *mod;
909 void operator()(RTLIL::SigSpec &sig)
910 {
911 std::vector<RTLIL::SigChunk> chunks = sig.chunks();
912 for (auto &c : chunks)
913 if (c.wire != NULL)
914 c.wire = mod->wires_.at(c.wire->name);
915 sig = chunks;
916 }
917 };
918
919 RewriteSigSpecWorker rewriteSigSpecWorker;
920 rewriteSigSpecWorker.mod = new_mod;
921 new_mod->rewrite_sigspecs(rewriteSigSpecWorker);
922 }
923
924 RTLIL::Module *RTLIL::Module::clone() const
925 {
926 RTLIL::Module *new_mod = new RTLIL::Module;
927 new_mod->name = name;
928 cloneInto(new_mod);
929 return new_mod;
930 }
931
932 bool RTLIL::Module::has_memories() const
933 {
934 return !memories.empty();
935 }
936
937 bool RTLIL::Module::has_processes() const
938 {
939 return !processes.empty();
940 }
941
942 bool RTLIL::Module::has_memories_warn() const
943 {
944 if (!memories.empty())
945 log("Warning: Ignoring module %s because it contains memories (run 'memory' command first).\n", log_id(this));
946 return !memories.empty();
947 }
948
949 bool RTLIL::Module::has_processes_warn() const
950 {
951 if (!processes.empty())
952 log("Warning: Ignoring module %s because it contains processes (run 'proc' command first).\n", log_id(this));
953 return !processes.empty();
954 }
955
956 std::vector<RTLIL::Wire*> RTLIL::Module::selected_wires() const
957 {
958 std::vector<RTLIL::Wire*> result;
959 result.reserve(wires_.size());
960 for (auto &it : wires_)
961 if (design->selected(this, it.second))
962 result.push_back(it.second);
963 return result;
964 }
965
966 std::vector<RTLIL::Cell*> RTLIL::Module::selected_cells() const
967 {
968 std::vector<RTLIL::Cell*> result;
969 result.reserve(wires_.size());
970 for (auto &it : cells_)
971 if (design->selected(this, it.second))
972 result.push_back(it.second);
973 return result;
974 }
975
976 void RTLIL::Module::add(RTLIL::Wire *wire)
977 {
978 log_assert(!wire->name.empty());
979 log_assert(count_id(wire->name) == 0);
980 log_assert(refcount_wires_ == 0);
981 wires_[wire->name] = wire;
982 wire->module = this;
983 }
984
985 void RTLIL::Module::add(RTLIL::Cell *cell)
986 {
987 log_assert(!cell->name.empty());
988 log_assert(count_id(cell->name) == 0);
989 log_assert(refcount_cells_ == 0);
990 cells_[cell->name] = cell;
991 cell->module = this;
992 }
993
994 namespace {
995 struct DeleteWireWorker
996 {
997 RTLIL::Module *module;
998 const std::set<RTLIL::Wire*> *wires_p;
999
1000 void operator()(RTLIL::SigSpec &sig) {
1001 std::vector<RTLIL::SigChunk> chunks = sig;
1002 for (auto &c : chunks)
1003 if (c.wire != NULL && wires_p->count(c.wire)) {
1004 c.wire = module->addWire(NEW_ID, c.width);
1005 c.offset = 0;
1006 }
1007 sig = chunks;
1008 }
1009 };
1010 }
1011
1012 #if 0
1013 void RTLIL::Module::remove(RTLIL::Wire *wire)
1014 {
1015 std::setPort<RTLIL::Wire*> wires_;
1016 wires_.insert(wire);
1017 remove(wires_);
1018 }
1019 #endif
1020
1021 void RTLIL::Module::remove(const std::set<RTLIL::Wire*> &wires)
1022 {
1023 log_assert(refcount_wires_ == 0);
1024
1025 DeleteWireWorker delete_wire_worker;
1026 delete_wire_worker.module = this;
1027 delete_wire_worker.wires_p = &wires;
1028 rewrite_sigspecs(delete_wire_worker);
1029
1030 for (auto &it : wires) {
1031 log_assert(wires_.count(it->name) != 0);
1032 wires_.erase(it->name);
1033 delete it;
1034 }
1035 }
1036
1037 void RTLIL::Module::remove(RTLIL::Cell *cell)
1038 {
1039 log_assert(cells_.count(cell->name) != 0);
1040 log_assert(refcount_cells_ == 0);
1041 cells_.erase(cell->name);
1042 delete cell;
1043 }
1044
1045 void RTLIL::Module::rename(RTLIL::Wire *wire, RTLIL::IdString new_name)
1046 {
1047 log_assert(wires_[wire->name] == wire);
1048 log_assert(refcount_wires_ == 0);
1049 wires_.erase(wire->name);
1050 wire->name = new_name;
1051 add(wire);
1052 }
1053
1054 void RTLIL::Module::rename(RTLIL::Cell *cell, RTLIL::IdString new_name)
1055 {
1056 log_assert(cells_[cell->name] == cell);
1057 log_assert(refcount_wires_ == 0);
1058 cells_.erase(cell->name);
1059 cell->name = new_name;
1060 add(cell);
1061 }
1062
1063 void RTLIL::Module::rename(RTLIL::IdString old_name, RTLIL::IdString new_name)
1064 {
1065 log_assert(count_id(old_name) != 0);
1066 if (wires_.count(old_name))
1067 rename(wires_.at(old_name), new_name);
1068 else if (cells_.count(old_name))
1069 rename(cells_.at(old_name), new_name);
1070 else
1071 log_abort();
1072 }
1073
1074 void RTLIL::Module::swap_names(RTLIL::Wire *w1, RTLIL::Wire *w2)
1075 {
1076 log_assert(wires_[w1->name] == w1);
1077 log_assert(wires_[w2->name] == w2);
1078 log_assert(refcount_wires_ == 0);
1079
1080 wires_.erase(w1->name);
1081 wires_.erase(w2->name);
1082
1083 std::swap(w1->name, w2->name);
1084
1085 wires_[w1->name] = w1;
1086 wires_[w2->name] = w2;
1087 }
1088
1089 void RTLIL::Module::swap_names(RTLIL::Cell *c1, RTLIL::Cell *c2)
1090 {
1091 log_assert(cells_[c1->name] == c1);
1092 log_assert(cells_[c2->name] == c2);
1093 log_assert(refcount_cells_ == 0);
1094
1095 cells_.erase(c1->name);
1096 cells_.erase(c2->name);
1097
1098 std::swap(c1->name, c2->name);
1099
1100 cells_[c1->name] = c1;
1101 cells_[c2->name] = c2;
1102 }
1103
1104 static bool fixup_ports_compare(const RTLIL::Wire *a, const RTLIL::Wire *b)
1105 {
1106 if (a->port_id && !b->port_id)
1107 return true;
1108 if (!a->port_id && b->port_id)
1109 return false;
1110
1111 if (a->port_id == b->port_id)
1112 return a->name < b->name;
1113 return a->port_id < b->port_id;
1114 }
1115
1116 void RTLIL::Module::connect(const RTLIL::SigSig &conn)
1117 {
1118 for (auto mon : monitors)
1119 mon->notify_connect(this, conn);
1120
1121 if (design)
1122 for (auto mon : design->monitors)
1123 mon->notify_connect(this, conn);
1124
1125 connections_.push_back(conn);
1126 }
1127
1128 void RTLIL::Module::connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs)
1129 {
1130 connect(RTLIL::SigSig(lhs, rhs));
1131 }
1132
1133 void RTLIL::Module::new_connections(const std::vector<RTLIL::SigSig> &new_conn)
1134 {
1135 for (auto mon : monitors)
1136 mon->notify_connect(this, new_conn);
1137
1138 if (design)
1139 for (auto mon : design->monitors)
1140 mon->notify_connect(this, new_conn);
1141
1142 connections_ = new_conn;
1143 }
1144
1145 const std::vector<RTLIL::SigSig> &RTLIL::Module::connections() const
1146 {
1147 return connections_;
1148 }
1149
1150 void RTLIL::Module::fixup_ports()
1151 {
1152 std::vector<RTLIL::Wire*> all_ports;
1153
1154 for (auto &w : wires_)
1155 if (w.second->port_input || w.second->port_output)
1156 all_ports.push_back(w.second);
1157 else
1158 w.second->port_id = 0;
1159
1160 std::sort(all_ports.begin(), all_ports.end(), fixup_ports_compare);
1161 for (size_t i = 0; i < all_ports.size(); i++)
1162 all_ports[i]->port_id = i+1;
1163 }
1164
1165 RTLIL::Wire *RTLIL::Module::addWire(RTLIL::IdString name, int width)
1166 {
1167 RTLIL::Wire *wire = new RTLIL::Wire;
1168 wire->name = name;
1169 wire->width = width;
1170 add(wire);
1171 return wire;
1172 }
1173
1174 RTLIL::Wire *RTLIL::Module::addWire(RTLIL::IdString name, const RTLIL::Wire *other)
1175 {
1176 RTLIL::Wire *wire = addWire(name);
1177 wire->width = other->width;
1178 wire->start_offset = other->start_offset;
1179 wire->port_id = other->port_id;
1180 wire->port_input = other->port_input;
1181 wire->port_output = other->port_output;
1182 wire->upto = other->upto;
1183 wire->attributes = other->attributes;
1184 return wire;
1185 }
1186
1187 RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, RTLIL::IdString type)
1188 {
1189 RTLIL::Cell *cell = new RTLIL::Cell;
1190 cell->name = name;
1191 cell->type = type;
1192 add(cell);
1193 return cell;
1194 }
1195
1196 RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, const RTLIL::Cell *other)
1197 {
1198 RTLIL::Cell *cell = addCell(name, other->type);
1199 cell->connections_ = other->connections_;
1200 cell->parameters = other->parameters;
1201 cell->attributes = other->attributes;
1202 return cell;
1203 }
1204
1205 #define DEF_METHOD(_func, _y_size, _type) \
1206 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed) { \
1207 RTLIL::Cell *cell = addCell(name, _type); \
1208 cell->parameters["\\A_SIGNED"] = is_signed; \
1209 cell->parameters["\\A_WIDTH"] = sig_a.size(); \
1210 cell->parameters["\\Y_WIDTH"] = sig_y.size(); \
1211 cell->setPort("\\A", sig_a); \
1212 cell->setPort("\\Y", sig_y); \
1213 return cell; \
1214 } \
1215 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed) { \
1216 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
1217 add ## _func(name, sig_a, sig_y, is_signed); \
1218 return sig_y; \
1219 }
1220 DEF_METHOD(Not, sig_a.size(), "$not")
1221 DEF_METHOD(Pos, sig_a.size(), "$pos")
1222 DEF_METHOD(Bu0, sig_a.size(), "$bu0")
1223 DEF_METHOD(Neg, sig_a.size(), "$neg")
1224 DEF_METHOD(ReduceAnd, 1, "$reduce_and")
1225 DEF_METHOD(ReduceOr, 1, "$reduce_or")
1226 DEF_METHOD(ReduceXor, 1, "$reduce_xor")
1227 DEF_METHOD(ReduceXnor, 1, "$reduce_xnor")
1228 DEF_METHOD(ReduceBool, 1, "$reduce_bool")
1229 DEF_METHOD(LogicNot, 1, "$logic_not")
1230 #undef DEF_METHOD
1231
1232 #define DEF_METHOD(_func, _y_size, _type) \
1233 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed) { \
1234 RTLIL::Cell *cell = addCell(name, _type); \
1235 cell->parameters["\\A_SIGNED"] = is_signed; \
1236 cell->parameters["\\B_SIGNED"] = is_signed; \
1237 cell->parameters["\\A_WIDTH"] = sig_a.size(); \
1238 cell->parameters["\\B_WIDTH"] = sig_b.size(); \
1239 cell->parameters["\\Y_WIDTH"] = sig_y.size(); \
1240 cell->setPort("\\A", sig_a); \
1241 cell->setPort("\\B", sig_b); \
1242 cell->setPort("\\Y", sig_y); \
1243 return cell; \
1244 } \
1245 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed) { \
1246 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
1247 add ## _func(name, sig_a, sig_b, sig_y, is_signed); \
1248 return sig_y; \
1249 }
1250 DEF_METHOD(And, std::max(sig_a.size(), sig_b.size()), "$and")
1251 DEF_METHOD(Or, std::max(sig_a.size(), sig_b.size()), "$or")
1252 DEF_METHOD(Xor, std::max(sig_a.size(), sig_b.size()), "$xor")
1253 DEF_METHOD(Xnor, std::max(sig_a.size(), sig_b.size()), "$xnor")
1254 DEF_METHOD(Shl, sig_a.size(), "$shl")
1255 DEF_METHOD(Shr, sig_a.size(), "$shr")
1256 DEF_METHOD(Sshl, sig_a.size(), "$sshl")
1257 DEF_METHOD(Sshr, sig_a.size(), "$sshr")
1258 DEF_METHOD(Shift, sig_a.size(), "$shift")
1259 DEF_METHOD(Shiftx, sig_a.size(), "$shiftx")
1260 DEF_METHOD(Lt, 1, "$lt")
1261 DEF_METHOD(Le, 1, "$le")
1262 DEF_METHOD(Eq, 1, "$eq")
1263 DEF_METHOD(Ne, 1, "$ne")
1264 DEF_METHOD(Eqx, 1, "$eqx")
1265 DEF_METHOD(Nex, 1, "$nex")
1266 DEF_METHOD(Ge, 1, "$ge")
1267 DEF_METHOD(Gt, 1, "$gt")
1268 DEF_METHOD(Add, std::max(sig_a.size(), sig_b.size()), "$add")
1269 DEF_METHOD(Sub, std::max(sig_a.size(), sig_b.size()), "$sub")
1270 DEF_METHOD(Mul, std::max(sig_a.size(), sig_b.size()), "$mul")
1271 DEF_METHOD(Div, std::max(sig_a.size(), sig_b.size()), "$div")
1272 DEF_METHOD(Mod, std::max(sig_a.size(), sig_b.size()), "$mod")
1273 DEF_METHOD(LogicAnd, 1, "$logic_and")
1274 DEF_METHOD(LogicOr, 1, "$logic_or")
1275 #undef DEF_METHOD
1276
1277 #define DEF_METHOD(_func, _type, _pmux) \
1278 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, RTLIL::SigSpec sig_y) { \
1279 RTLIL::Cell *cell = addCell(name, _type); \
1280 cell->parameters["\\WIDTH"] = sig_a.size(); \
1281 cell->parameters["\\WIDTH"] = sig_b.size(); \
1282 if (_pmux) cell->parameters["\\S_WIDTH"] = sig_s.size(); \
1283 cell->setPort("\\A", sig_a); \
1284 cell->setPort("\\B", sig_b); \
1285 cell->setPort("\\S", sig_s); \
1286 cell->setPort("\\Y", sig_y); \
1287 return cell; \
1288 } \
1289 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s) { \
1290 RTLIL::SigSpec sig_y = addWire(NEW_ID, sig_a.size()); \
1291 add ## _func(name, sig_a, sig_b, sig_s, sig_y); \
1292 return sig_y; \
1293 }
1294 DEF_METHOD(Mux, "$mux", 0)
1295 DEF_METHOD(Pmux, "$pmux", 1)
1296 DEF_METHOD(SafePmux, "$safe_pmux", 1)
1297 #undef DEF_METHOD
1298
1299 #define DEF_METHOD_2(_func, _type, _P1, _P2) \
1300 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig1, RTLIL::SigSpec sig2) { \
1301 RTLIL::Cell *cell = addCell(name, _type); \
1302 cell->setPort("\\" #_P1, sig1); \
1303 cell->setPort("\\" #_P2, sig2); \
1304 return cell; \
1305 } \
1306 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig1) { \
1307 RTLIL::SigSpec sig2 = addWire(NEW_ID); \
1308 add ## _func(name, sig1, sig2); \
1309 return sig2; \
1310 }
1311 #define DEF_METHOD_3(_func, _type, _P1, _P2, _P3) \
1312 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig1, RTLIL::SigSpec sig2, RTLIL::SigSpec sig3) { \
1313 RTLIL::Cell *cell = addCell(name, _type); \
1314 cell->setPort("\\" #_P1, sig1); \
1315 cell->setPort("\\" #_P2, sig2); \
1316 cell->setPort("\\" #_P3, sig3); \
1317 return cell; \
1318 } \
1319 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig1, RTLIL::SigSpec sig2) { \
1320 RTLIL::SigSpec sig3 = addWire(NEW_ID); \
1321 add ## _func(name, sig1, sig2, sig3); \
1322 return sig3; \
1323 }
1324 #define DEF_METHOD_4(_func, _type, _P1, _P2, _P3, _P4) \
1325 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig1, RTLIL::SigSpec sig2, RTLIL::SigSpec sig3, RTLIL::SigSpec sig4) { \
1326 RTLIL::Cell *cell = addCell(name, _type); \
1327 cell->setPort("\\" #_P1, sig1); \
1328 cell->setPort("\\" #_P2, sig2); \
1329 cell->setPort("\\" #_P3, sig3); \
1330 cell->setPort("\\" #_P4, sig4); \
1331 return cell; \
1332 } \
1333 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig1, RTLIL::SigSpec sig2, RTLIL::SigSpec sig3) { \
1334 RTLIL::SigSpec sig4 = addWire(NEW_ID); \
1335 add ## _func(name, sig1, sig2, sig3, sig4); \
1336 return sig4; \
1337 }
1338 DEF_METHOD_2(InvGate, "$_INV_", A, Y)
1339 DEF_METHOD_3(AndGate, "$_AND_", A, B, Y)
1340 DEF_METHOD_3(OrGate, "$_OR_", A, B, Y)
1341 DEF_METHOD_3(XorGate, "$_XOR_", A, B, Y)
1342 DEF_METHOD_4(MuxGate, "$_MUX_", A, B, S, Y)
1343 #undef DEF_METHOD_2
1344 #undef DEF_METHOD_3
1345 #undef DEF_METHOD_4
1346
1347 RTLIL::Cell* RTLIL::Module::addPow(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool a_signed, bool b_signed)
1348 {
1349 RTLIL::Cell *cell = addCell(name, "$pow");
1350 cell->parameters["\\A_SIGNED"] = a_signed;
1351 cell->parameters["\\B_SIGNED"] = b_signed;
1352 cell->parameters["\\A_WIDTH"] = sig_a.size();
1353 cell->parameters["\\B_WIDTH"] = sig_b.size();
1354 cell->parameters["\\Y_WIDTH"] = sig_y.size();
1355 cell->setPort("\\A", sig_a);
1356 cell->setPort("\\B", sig_b);
1357 cell->setPort("\\Y", sig_y);
1358 return cell;
1359 }
1360
1361 RTLIL::Cell* RTLIL::Module::addSlice(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, RTLIL::Const offset)
1362 {
1363 RTLIL::Cell *cell = addCell(name, "$slice");
1364 cell->parameters["\\A_WIDTH"] = sig_a.size();
1365 cell->parameters["\\Y_WIDTH"] = sig_y.size();
1366 cell->parameters["\\OFFSET"] = offset;
1367 cell->setPort("\\A", sig_a);
1368 cell->setPort("\\Y", sig_y);
1369 return cell;
1370 }
1371
1372 RTLIL::Cell* RTLIL::Module::addConcat(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y)
1373 {
1374 RTLIL::Cell *cell = addCell(name, "$concat");
1375 cell->parameters["\\A_WIDTH"] = sig_a.size();
1376 cell->parameters["\\B_WIDTH"] = sig_b.size();
1377 cell->setPort("\\A", sig_a);
1378 cell->setPort("\\B", sig_b);
1379 cell->setPort("\\Y", sig_y);
1380 return cell;
1381 }
1382
1383 RTLIL::Cell* RTLIL::Module::addLut(RTLIL::IdString name, RTLIL::SigSpec sig_i, RTLIL::SigSpec sig_o, RTLIL::Const lut)
1384 {
1385 RTLIL::Cell *cell = addCell(name, "$lut");
1386 cell->parameters["\\LUT"] = lut;
1387 cell->parameters["\\WIDTH"] = sig_i.size();
1388 cell->setPort("\\I", sig_i);
1389 cell->setPort("\\O", sig_o);
1390 return cell;
1391 }
1392
1393 RTLIL::Cell* RTLIL::Module::addAssert(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en)
1394 {
1395 RTLIL::Cell *cell = addCell(name, "$assert");
1396 cell->setPort("\\A", sig_a);
1397 cell->setPort("\\EN", sig_en);
1398 return cell;
1399 }
1400
1401 RTLIL::Cell* RTLIL::Module::addSr(RTLIL::IdString name, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr, RTLIL::SigSpec sig_q, bool set_polarity, bool clr_polarity)
1402 {
1403 RTLIL::Cell *cell = addCell(name, "$sr");
1404 cell->parameters["\\SET_POLARITY"] = set_polarity;
1405 cell->parameters["\\CLR_POLARITY"] = clr_polarity;
1406 cell->parameters["\\WIDTH"] = sig_q.size();
1407 cell->setPort("\\SET", sig_set);
1408 cell->setPort("\\CLR", sig_clr);
1409 cell->setPort("\\Q", sig_q);
1410 return cell;
1411 }
1412
1413 RTLIL::Cell* RTLIL::Module::addDff(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity)
1414 {
1415 RTLIL::Cell *cell = addCell(name, "$dff");
1416 cell->parameters["\\CLK_POLARITY"] = clk_polarity;
1417 cell->parameters["\\WIDTH"] = sig_q.size();
1418 cell->setPort("\\CLK", sig_clk);
1419 cell->setPort("\\D", sig_d);
1420 cell->setPort("\\Q", sig_q);
1421 return cell;
1422 }
1423
1424 RTLIL::Cell* RTLIL::Module::addDffsr(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
1425 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity)
1426 {
1427 RTLIL::Cell *cell = addCell(name, "$dffsr");
1428 cell->parameters["\\CLK_POLARITY"] = clk_polarity;
1429 cell->parameters["\\SET_POLARITY"] = set_polarity;
1430 cell->parameters["\\CLR_POLARITY"] = clr_polarity;
1431 cell->parameters["\\WIDTH"] = sig_q.size();
1432 cell->setPort("\\CLK", sig_clk);
1433 cell->setPort("\\SET", sig_set);
1434 cell->setPort("\\CLR", sig_clr);
1435 cell->setPort("\\D", sig_d);
1436 cell->setPort("\\Q", sig_q);
1437 return cell;
1438 }
1439
1440 RTLIL::Cell* RTLIL::Module::addAdff(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_arst, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q,
1441 RTLIL::Const arst_value, bool clk_polarity, bool arst_polarity)
1442 {
1443 RTLIL::Cell *cell = addCell(name, "$adff");
1444 cell->parameters["\\CLK_POLARITY"] = clk_polarity;
1445 cell->parameters["\\ARST_POLARITY"] = arst_polarity;
1446 cell->parameters["\\ARST_VALUE"] = arst_value;
1447 cell->parameters["\\WIDTH"] = sig_q.size();
1448 cell->setPort("\\CLK", sig_clk);
1449 cell->setPort("\\ARST", sig_arst);
1450 cell->setPort("\\D", sig_d);
1451 cell->setPort("\\Q", sig_q);
1452 return cell;
1453 }
1454
1455 RTLIL::Cell* RTLIL::Module::addDlatch(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity)
1456 {
1457 RTLIL::Cell *cell = addCell(name, "$dlatch");
1458 cell->parameters["\\EN_POLARITY"] = en_polarity;
1459 cell->parameters["\\WIDTH"] = sig_q.size();
1460 cell->setPort("\\EN", sig_en);
1461 cell->setPort("\\D", sig_d);
1462 cell->setPort("\\Q", sig_q);
1463 return cell;
1464 }
1465
1466 RTLIL::Cell* RTLIL::Module::addDlatchsr(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
1467 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity, bool set_polarity, bool clr_polarity)
1468 {
1469 RTLIL::Cell *cell = addCell(name, "$dlatchsr");
1470 cell->parameters["\\EN_POLARITY"] = en_polarity;
1471 cell->parameters["\\SET_POLARITY"] = set_polarity;
1472 cell->parameters["\\CLR_POLARITY"] = clr_polarity;
1473 cell->parameters["\\WIDTH"] = sig_q.size();
1474 cell->setPort("\\EN", sig_en);
1475 cell->setPort("\\SET", sig_set);
1476 cell->setPort("\\CLR", sig_clr);
1477 cell->setPort("\\D", sig_d);
1478 cell->setPort("\\Q", sig_q);
1479 return cell;
1480 }
1481
1482 RTLIL::Cell* RTLIL::Module::addDffGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity)
1483 {
1484 RTLIL::Cell *cell = addCell(name, stringf("$_DFF_%c_", clk_polarity ? 'P' : 'N'));
1485 cell->setPort("\\C", sig_clk);
1486 cell->setPort("\\D", sig_d);
1487 cell->setPort("\\Q", sig_q);
1488 return cell;
1489 }
1490
1491 RTLIL::Cell* RTLIL::Module::addDffsrGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
1492 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity)
1493 {
1494 RTLIL::Cell *cell = addCell(name, stringf("$_DFFSR_%c%c%c_", clk_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N'));
1495 cell->setPort("\\C", sig_clk);
1496 cell->setPort("\\S", sig_set);
1497 cell->setPort("\\R", sig_clr);
1498 cell->setPort("\\D", sig_d);
1499 cell->setPort("\\Q", sig_q);
1500 return cell;
1501 }
1502
1503 RTLIL::Cell* RTLIL::Module::addAdffGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_arst, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q,
1504 bool arst_value, bool clk_polarity, bool arst_polarity)
1505 {
1506 RTLIL::Cell *cell = addCell(name, stringf("$_DFF_%c%c%c_", clk_polarity ? 'P' : 'N', arst_polarity ? 'P' : 'N', arst_value ? '1' : '0'));
1507 cell->setPort("\\C", sig_clk);
1508 cell->setPort("\\R", sig_arst);
1509 cell->setPort("\\D", sig_d);
1510 cell->setPort("\\Q", sig_q);
1511 return cell;
1512 }
1513
1514 RTLIL::Cell* RTLIL::Module::addDlatchGate(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity)
1515 {
1516 RTLIL::Cell *cell = addCell(name, stringf("$_DLATCH_%c_", en_polarity ? 'P' : 'N'));
1517 cell->setPort("\\E", sig_en);
1518 cell->setPort("\\D", sig_d);
1519 cell->setPort("\\Q", sig_q);
1520 return cell;
1521 }
1522
1523 RTLIL::Cell* RTLIL::Module::addDlatchsrGate(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
1524 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity, bool set_polarity, bool clr_polarity)
1525 {
1526 RTLIL::Cell *cell = addCell(name, stringf("$_DLATCHSR_%c%c%c_", en_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N'));
1527 cell->setPort("\\E", sig_en);
1528 cell->setPort("\\S", sig_set);
1529 cell->setPort("\\R", sig_clr);
1530 cell->setPort("\\D", sig_d);
1531 cell->setPort("\\Q", sig_q);
1532 return cell;
1533 }
1534
1535
1536 RTLIL::Wire::Wire()
1537 {
1538 module = nullptr;
1539 width = 1;
1540 start_offset = 0;
1541 port_id = 0;
1542 port_input = false;
1543 port_output = false;
1544 upto = false;
1545 }
1546
1547 RTLIL::Memory::Memory()
1548 {
1549 width = 1;
1550 size = 0;
1551 }
1552
1553 bool RTLIL::Cell::hasPort(RTLIL::IdString portname) const
1554 {
1555 return connections_.count(portname) != 0;
1556 }
1557
1558 void RTLIL::Cell::unsetPort(RTLIL::IdString portname)
1559 {
1560 RTLIL::SigSpec signal;
1561 auto conn_it = connections_.find(portname);
1562
1563 if (conn_it != connections_.end())
1564 {
1565 for (auto mon : module->monitors)
1566 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
1567
1568 if (module->design)
1569 for (auto mon : module->design->monitors)
1570 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
1571
1572 connections_.erase(conn_it);
1573 }
1574 }
1575
1576 void RTLIL::Cell::setPort(RTLIL::IdString portname, RTLIL::SigSpec signal)
1577 {
1578 auto conn_it = connections_.find(portname);
1579
1580 if (conn_it == connections_.end()) {
1581 connections_[portname] = RTLIL::SigSpec();
1582 conn_it = connections_.find(portname);
1583 log_assert(conn_it != connections_.end());
1584 }
1585
1586 for (auto mon : module->monitors)
1587 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
1588
1589 if (module->design)
1590 for (auto mon : module->design->monitors)
1591 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
1592
1593 conn_it->second = signal;
1594 }
1595
1596 const RTLIL::SigSpec &RTLIL::Cell::getPort(RTLIL::IdString portname) const
1597 {
1598 return connections_.at(portname);
1599 }
1600
1601 const std::map<RTLIL::IdString, RTLIL::SigSpec> &RTLIL::Cell::connections() const
1602 {
1603 return connections_;
1604 }
1605
1606 bool RTLIL::Cell::hasParam(RTLIL::IdString paramname) const
1607 {
1608 return parameters.count(paramname);
1609 }
1610
1611 void RTLIL::Cell::unsetParam(RTLIL::IdString paramname)
1612 {
1613 parameters.erase(paramname);
1614 }
1615
1616 void RTLIL::Cell::setParam(RTLIL::IdString paramname, RTLIL::Const value)
1617 {
1618 parameters[paramname] = value;
1619 }
1620
1621 const RTLIL::Const &RTLIL::Cell::getParam(RTLIL::IdString paramname) const
1622 {
1623 return parameters.at(paramname);
1624 }
1625
1626 void RTLIL::Cell::check()
1627 {
1628 #ifndef NDEBUG
1629 InternalCellChecker checker(NULL, this);
1630 checker.check();
1631 #endif
1632 }
1633
1634 void RTLIL::Cell::fixup_parameters(bool set_a_signed, bool set_b_signed)
1635 {
1636 if (type.substr(0, 1) != "$" || type.substr(0, 2) == "$_" || type.substr(0, 8) == "$paramod" ||
1637 type.substr(0, 9) == "$verific$" || type.substr(0, 7) == "$array:" || type.substr(0, 8) == "$extern:")
1638 return;
1639
1640 if (type == "$mux" || type == "$pmux" || type == "$safe_pmux")
1641 {
1642 parameters["\\WIDTH"] = SIZE(connections_["\\Y"]);
1643 if (type == "$pmux" || type == "$safe_pmux")
1644 parameters["\\S_WIDTH"] = SIZE(connections_["\\S"]);
1645 check();
1646 return;
1647 }
1648
1649 bool signedness_ab = type != "$slice" && type != "$concat";
1650
1651 if (connections_.count("\\A")) {
1652 if (signedness_ab) {
1653 if (set_a_signed)
1654 parameters["\\A_SIGNED"] = true;
1655 else if (parameters.count("\\A_SIGNED") == 0)
1656 parameters["\\A_SIGNED"] = false;
1657 }
1658 parameters["\\A_WIDTH"] = SIZE(connections_["\\A"]);
1659 }
1660
1661 if (connections_.count("\\B")) {
1662 if (signedness_ab) {
1663 if (set_b_signed)
1664 parameters["\\B_SIGNED"] = true;
1665 else if (parameters.count("\\B_SIGNED") == 0)
1666 parameters["\\B_SIGNED"] = false;
1667 }
1668 parameters["\\B_WIDTH"] = SIZE(connections_["\\B"]);
1669 }
1670
1671 if (connections_.count("\\Y"))
1672 parameters["\\Y_WIDTH"] = SIZE(connections_["\\Y"]);
1673
1674 check();
1675 }
1676
1677 RTLIL::SigChunk::SigChunk()
1678 {
1679 wire = NULL;
1680 width = 0;
1681 offset = 0;
1682 }
1683
1684 RTLIL::SigChunk::SigChunk(const RTLIL::Const &value)
1685 {
1686 wire = NULL;
1687 data = value;
1688 width = data.bits.size();
1689 offset = 0;
1690 }
1691
1692 RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire)
1693 {
1694 log_assert(wire != nullptr);
1695 this->wire = wire;
1696 this->width = wire->width;
1697 this->offset = 0;
1698 }
1699
1700 RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire, int offset, int width)
1701 {
1702 log_assert(wire != nullptr);
1703 this->wire = wire;
1704 this->width = width;
1705 this->offset = offset;
1706 }
1707
1708 RTLIL::SigChunk::SigChunk(const std::string &str)
1709 {
1710 wire = NULL;
1711 data = RTLIL::Const(str);
1712 width = data.bits.size();
1713 offset = 0;
1714 }
1715
1716 RTLIL::SigChunk::SigChunk(int val, int width)
1717 {
1718 wire = NULL;
1719 data = RTLIL::Const(val, width);
1720 this->width = data.bits.size();
1721 offset = 0;
1722 }
1723
1724 RTLIL::SigChunk::SigChunk(RTLIL::State bit, int width)
1725 {
1726 wire = NULL;
1727 data = RTLIL::Const(bit, width);
1728 this->width = data.bits.size();
1729 offset = 0;
1730 }
1731
1732 RTLIL::SigChunk::SigChunk(RTLIL::SigBit bit)
1733 {
1734 wire = bit.wire;
1735 offset = 0;
1736 if (wire == NULL)
1737 data = RTLIL::Const(bit.data);
1738 else
1739 offset = bit.offset;
1740 width = 1;
1741 }
1742
1743 RTLIL::SigChunk RTLIL::SigChunk::extract(int offset, int length) const
1744 {
1745 RTLIL::SigChunk ret;
1746 if (wire) {
1747 ret.wire = wire;
1748 ret.offset = this->offset + offset;
1749 ret.width = length;
1750 } else {
1751 for (int i = 0; i < length; i++)
1752 ret.data.bits.push_back(data.bits[offset+i]);
1753 ret.width = length;
1754 }
1755 return ret;
1756 }
1757
1758 bool RTLIL::SigChunk::operator <(const RTLIL::SigChunk &other) const
1759 {
1760 if (wire && other.wire)
1761 if (wire->name != other.wire->name)
1762 return wire->name < other.wire->name;
1763
1764 if (wire != other.wire)
1765 return wire < other.wire;
1766
1767 if (offset != other.offset)
1768 return offset < other.offset;
1769
1770 if (width != other.width)
1771 return width < other.width;
1772
1773 return data.bits < other.data.bits;
1774 }
1775
1776 bool RTLIL::SigChunk::operator ==(const RTLIL::SigChunk &other) const
1777 {
1778 if (wire != other.wire || width != other.width || offset != other.offset)
1779 return false;
1780 if (data.bits != other.data.bits)
1781 return false;
1782 return true;
1783 }
1784
1785 bool RTLIL::SigChunk::operator !=(const RTLIL::SigChunk &other) const
1786 {
1787 if (*this == other)
1788 return false;
1789 return true;
1790 }
1791
1792 RTLIL::SigSpec::SigSpec()
1793 {
1794 width_ = 0;
1795 hash_ = 0;
1796 }
1797
1798 RTLIL::SigSpec::SigSpec(const RTLIL::SigSpec &other)
1799 {
1800 *this = other;
1801 }
1802
1803 RTLIL::SigSpec::SigSpec(std::initializer_list<RTLIL::SigSpec> parts)
1804 {
1805 cover("kernel.rtlil.sigspec.init.list");
1806
1807 width_ = 0;
1808 hash_ = 0;
1809
1810 std::vector<RTLIL::SigSpec> parts_vec(parts.begin(), parts.end());
1811 for (auto it = parts_vec.rbegin(); it != parts_vec.rend(); it++)
1812 append(*it);
1813 }
1814
1815 const RTLIL::SigSpec &RTLIL::SigSpec::operator=(const RTLIL::SigSpec &other)
1816 {
1817 cover("kernel.rtlil.sigspec.assign");
1818
1819 width_ = other.width_;
1820 hash_ = other.hash_;
1821 chunks_ = other.chunks_;
1822 bits_.clear();
1823
1824 if (!other.bits_.empty())
1825 {
1826 RTLIL::SigChunk *last = NULL;
1827 int last_end_offset = 0;
1828
1829 for (auto &bit : other.bits_) {
1830 if (last && bit.wire == last->wire) {
1831 if (bit.wire == NULL) {
1832 last->data.bits.push_back(bit.data);
1833 last->width++;
1834 continue;
1835 } else if (last_end_offset == bit.offset) {
1836 last_end_offset++;
1837 last->width++;
1838 continue;
1839 }
1840 }
1841 chunks_.push_back(bit);
1842 last = &chunks_.back();
1843 last_end_offset = bit.offset + 1;
1844 }
1845
1846 check();
1847 }
1848
1849 return *this;
1850 }
1851
1852 RTLIL::SigSpec::SigSpec(const RTLIL::Const &value)
1853 {
1854 cover("kernel.rtlil.sigspec.init.const");
1855
1856 chunks_.push_back(RTLIL::SigChunk(value));
1857 width_ = chunks_.back().width;
1858 hash_ = 0;
1859 check();
1860 }
1861
1862 RTLIL::SigSpec::SigSpec(const RTLIL::SigChunk &chunk)
1863 {
1864 cover("kernel.rtlil.sigspec.init.chunk");
1865
1866 chunks_.push_back(chunk);
1867 width_ = chunks_.back().width;
1868 hash_ = 0;
1869 check();
1870 }
1871
1872 RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire)
1873 {
1874 cover("kernel.rtlil.sigspec.init.wire");
1875
1876 chunks_.push_back(RTLIL::SigChunk(wire));
1877 width_ = chunks_.back().width;
1878 hash_ = 0;
1879 check();
1880 }
1881
1882 RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire, int offset, int width)
1883 {
1884 cover("kernel.rtlil.sigspec.init.wire_part");
1885
1886 chunks_.push_back(RTLIL::SigChunk(wire, offset, width));
1887 width_ = chunks_.back().width;
1888 hash_ = 0;
1889 check();
1890 }
1891
1892 RTLIL::SigSpec::SigSpec(const std::string &str)
1893 {
1894 cover("kernel.rtlil.sigspec.init.str");
1895
1896 chunks_.push_back(RTLIL::SigChunk(str));
1897 width_ = chunks_.back().width;
1898 hash_ = 0;
1899 check();
1900 }
1901
1902 RTLIL::SigSpec::SigSpec(int val, int width)
1903 {
1904 cover("kernel.rtlil.sigspec.init.int");
1905
1906 chunks_.push_back(RTLIL::SigChunk(val, width));
1907 width_ = width;
1908 hash_ = 0;
1909 check();
1910 }
1911
1912 RTLIL::SigSpec::SigSpec(RTLIL::State bit, int width)
1913 {
1914 cover("kernel.rtlil.sigspec.init.state");
1915
1916 chunks_.push_back(RTLIL::SigChunk(bit, width));
1917 width_ = width;
1918 hash_ = 0;
1919 check();
1920 }
1921
1922 RTLIL::SigSpec::SigSpec(RTLIL::SigBit bit, int width)
1923 {
1924 cover("kernel.rtlil.sigspec.init.bit");
1925
1926 if (bit.wire == NULL)
1927 chunks_.push_back(RTLIL::SigChunk(bit.data, width));
1928 else
1929 for (int i = 0; i < width; i++)
1930 chunks_.push_back(bit);
1931 width_ = width;
1932 hash_ = 0;
1933 check();
1934 }
1935
1936 RTLIL::SigSpec::SigSpec(std::vector<RTLIL::SigChunk> chunks)
1937 {
1938 cover("kernel.rtlil.sigspec.init.stdvec_chunks");
1939
1940 width_ = 0;
1941 hash_ = 0;
1942 for (auto &c : chunks)
1943 append(c);
1944 check();
1945 }
1946
1947 RTLIL::SigSpec::SigSpec(std::vector<RTLIL::SigBit> bits)
1948 {
1949 cover("kernel.rtlil.sigspec.init.stdvec_bits");
1950
1951 width_ = 0;
1952 hash_ = 0;
1953 for (auto &bit : bits)
1954 append_bit(bit);
1955 check();
1956 }
1957
1958 RTLIL::SigSpec::SigSpec(std::set<RTLIL::SigBit> bits)
1959 {
1960 cover("kernel.rtlil.sigspec.init.stdset_bits");
1961
1962 width_ = 0;
1963 hash_ = 0;
1964 for (auto &bit : bits)
1965 append_bit(bit);
1966 check();
1967 }
1968
1969 void RTLIL::SigSpec::pack() const
1970 {
1971 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
1972
1973 if (that->bits_.empty())
1974 return;
1975
1976 cover("kernel.rtlil.sigspec.convert.pack");
1977 log_assert(that->chunks_.empty());
1978
1979 std::vector<RTLIL::SigBit> old_bits;
1980 old_bits.swap(that->bits_);
1981
1982 RTLIL::SigChunk *last = NULL;
1983 int last_end_offset = 0;
1984
1985 for (auto &bit : old_bits) {
1986 if (last && bit.wire == last->wire) {
1987 if (bit.wire == NULL) {
1988 last->data.bits.push_back(bit.data);
1989 last->width++;
1990 continue;
1991 } else if (last_end_offset == bit.offset) {
1992 last_end_offset++;
1993 last->width++;
1994 continue;
1995 }
1996 }
1997 that->chunks_.push_back(bit);
1998 last = &that->chunks_.back();
1999 last_end_offset = bit.offset + 1;
2000 }
2001
2002 check();
2003 }
2004
2005 void RTLIL::SigSpec::unpack() const
2006 {
2007 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
2008
2009 if (that->chunks_.empty())
2010 return;
2011
2012 cover("kernel.rtlil.sigspec.convert.unpack");
2013 log_assert(that->bits_.empty());
2014
2015 that->bits_.reserve(that->width_);
2016 for (auto &c : that->chunks_)
2017 for (int i = 0; i < c.width; i++)
2018 that->bits_.push_back(RTLIL::SigBit(c, i));
2019
2020 that->chunks_.clear();
2021 that->hash_ = 0;
2022 }
2023
2024 #define DJB2(_hash, _value) do { (_hash) = (((_hash) << 5) + (_hash)) + (_value); } while (0)
2025
2026 void RTLIL::SigSpec::hash() const
2027 {
2028 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
2029
2030 if (that->hash_ != 0)
2031 return;
2032
2033 cover("kernel.rtlil.sigspec.hash");
2034 that->pack();
2035
2036 that->hash_ = 5381;
2037 for (auto &c : that->chunks_)
2038 if (c.wire == NULL) {
2039 for (auto &v : c.data.bits)
2040 DJB2(that->hash_, v);
2041 } else {
2042 DJB2(that->hash_, c.wire->name.index_);
2043 DJB2(that->hash_, c.offset);
2044 DJB2(that->hash_, c.width);
2045 }
2046
2047 if (that->hash_ == 0)
2048 that->hash_ = 1;
2049 }
2050
2051 void RTLIL::SigSpec::sort()
2052 {
2053 unpack();
2054 cover("kernel.rtlil.sigspec.sort");
2055 std::sort(bits_.begin(), bits_.end());
2056 }
2057
2058 void RTLIL::SigSpec::sort_and_unify()
2059 {
2060 cover("kernel.rtlil.sigspec.sort_and_unify");
2061 *this = this->to_sigbit_set();
2062 }
2063
2064 void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with)
2065 {
2066 replace(pattern, with, this);
2067 }
2068
2069 void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with, RTLIL::SigSpec *other) const
2070 {
2071 cover("kernel.rtlil.sigspec.replace");
2072
2073 unpack();
2074 pattern.unpack();
2075 with.unpack();
2076
2077 log_assert(other != NULL);
2078 log_assert(width_ == other->width_);
2079 other->unpack();
2080
2081 log_assert(pattern.width_ == with.width_);
2082
2083 std::map<RTLIL::SigBit, RTLIL::SigBit> pattern_map;
2084 for (int i = 0; i < SIZE(pattern.bits_); i++)
2085 if (pattern.bits_[i].wire != NULL)
2086 pattern_map[pattern.bits_[i]] = with.bits_[i];
2087
2088 for (int i = 0; i < SIZE(bits_); i++)
2089 if (pattern_map.count(bits_[i]))
2090 other->bits_[i] = pattern_map.at(bits_[i]);
2091
2092 other->check();
2093 }
2094
2095 void RTLIL::SigSpec::remove(const RTLIL::SigSpec &pattern)
2096 {
2097 remove2(pattern, NULL);
2098 }
2099
2100 void RTLIL::SigSpec::remove(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other) const
2101 {
2102 RTLIL::SigSpec tmp = *this;
2103 tmp.remove2(pattern, other);
2104 }
2105
2106 void RTLIL::SigSpec::remove2(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other)
2107 {
2108 if (other)
2109 cover("kernel.rtlil.sigspec.remove_other");
2110 else
2111 cover("kernel.rtlil.sigspec.remove");
2112
2113 unpack();
2114
2115 if (other != NULL) {
2116 log_assert(width_ == other->width_);
2117 other->unpack();
2118 }
2119
2120 std::set<RTLIL::SigBit> pattern_bits = pattern.to_sigbit_set();
2121 std::vector<RTLIL::SigBit> new_bits, new_other_bits;
2122
2123 for (int i = 0; i < SIZE(bits_); i++) {
2124 if (bits_[i].wire != NULL && pattern_bits.count(bits_[i]))
2125 continue;
2126 if (other != NULL)
2127 new_other_bits.push_back(other->bits_[i]);
2128 new_bits.push_back(bits_[i]);
2129 }
2130
2131 bits_.swap(new_bits);
2132 width_ = SIZE(bits_);
2133
2134 if (other != NULL) {
2135 other->bits_.swap(new_other_bits);
2136 other->width_ = SIZE(other->bits_);
2137 }
2138
2139 check();
2140 }
2141
2142 RTLIL::SigSpec RTLIL::SigSpec::extract(RTLIL::SigSpec pattern, const RTLIL::SigSpec *other) const
2143 {
2144 if (other)
2145 cover("kernel.rtlil.sigspec.extract_other");
2146 else
2147 cover("kernel.rtlil.sigspec.extract");
2148
2149 pack();
2150 pattern.pack();
2151
2152 if (other != NULL)
2153 other->pack();
2154
2155 log_assert(other == NULL || width_ == other->width_);
2156
2157 std::set<RTLIL::SigBit> pat = pattern.to_sigbit_set();
2158 std::vector<RTLIL::SigBit> bits_match = to_sigbit_vector();
2159 RTLIL::SigSpec ret;
2160
2161 if (other) {
2162 std::vector<RTLIL::SigBit> bits_other = other->to_sigbit_vector();
2163 for (int i = 0; i < width_; i++)
2164 if (bits_match[i].wire && pat.count(bits_match[i]))
2165 ret.append_bit(bits_other[i]);
2166 } else {
2167 for (int i = 0; i < width_; i++)
2168 if (bits_match[i].wire && pat.count(bits_match[i]))
2169 ret.append_bit(bits_match[i]);
2170 }
2171
2172 ret.check();
2173 return ret;
2174 }
2175
2176 void RTLIL::SigSpec::replace(int offset, const RTLIL::SigSpec &with)
2177 {
2178 cover("kernel.rtlil.sigspec.replace_pos");
2179
2180 unpack();
2181 with.unpack();
2182
2183 log_assert(offset >= 0);
2184 log_assert(with.width_ >= 0);
2185 log_assert(offset+with.width_ <= width_);
2186
2187 for (int i = 0; i < with.width_; i++)
2188 bits_.at(offset + i) = with.bits_.at(i);
2189
2190 check();
2191 }
2192
2193 void RTLIL::SigSpec::remove_const()
2194 {
2195 if (packed())
2196 {
2197 cover("kernel.rtlil.sigspec.remove_const.packed");
2198
2199 std::vector<RTLIL::SigChunk> new_chunks;
2200 new_chunks.reserve(SIZE(chunks_));
2201
2202 width_ = 0;
2203 for (auto &chunk : chunks_)
2204 if (chunk.wire != NULL) {
2205 new_chunks.push_back(chunk);
2206 width_ += chunk.width;
2207 }
2208
2209 chunks_.swap(new_chunks);
2210 }
2211 else
2212 {
2213 cover("kernel.rtlil.sigspec.remove_const.unpacked");
2214
2215 std::vector<RTLIL::SigBit> new_bits;
2216 new_bits.reserve(width_);
2217
2218 for (auto &bit : bits_)
2219 if (bit.wire != NULL)
2220 new_bits.push_back(bit);
2221
2222 bits_.swap(new_bits);
2223 width_ = bits_.size();
2224 }
2225
2226 check();
2227 }
2228
2229 void RTLIL::SigSpec::remove(int offset, int length)
2230 {
2231 cover("kernel.rtlil.sigspec.remove_pos");
2232
2233 unpack();
2234
2235 log_assert(offset >= 0);
2236 log_assert(length >= 0);
2237 log_assert(offset + length <= width_);
2238
2239 bits_.erase(bits_.begin() + offset, bits_.begin() + offset + length);
2240 width_ = bits_.size();
2241
2242 check();
2243 }
2244
2245 RTLIL::SigSpec RTLIL::SigSpec::extract(int offset, int length) const
2246 {
2247 unpack();
2248 cover("kernel.rtlil.sigspec.extract_pos");
2249 return std::vector<RTLIL::SigBit>(bits_.begin() + offset, bits_.begin() + offset + length);
2250 }
2251
2252 void RTLIL::SigSpec::append(const RTLIL::SigSpec &signal)
2253 {
2254 if (signal.width_ == 0)
2255 return;
2256
2257 if (width_ == 0) {
2258 *this = signal;
2259 return;
2260 }
2261
2262 cover("kernel.rtlil.sigspec.append");
2263
2264 if (packed() != signal.packed()) {
2265 pack();
2266 signal.pack();
2267 }
2268
2269 if (packed())
2270 for (auto &other_c : signal.chunks_)
2271 {
2272 auto &my_last_c = chunks_.back();
2273 if (my_last_c.wire == NULL && other_c.wire == NULL) {
2274 auto &this_data = my_last_c.data.bits;
2275 auto &other_data = other_c.data.bits;
2276 this_data.insert(this_data.end(), other_data.begin(), other_data.end());
2277 my_last_c.width += other_c.width;
2278 } else
2279 if (my_last_c.wire == other_c.wire && my_last_c.offset + my_last_c.width == other_c.offset) {
2280 my_last_c.width += other_c.width;
2281 } else
2282 chunks_.push_back(other_c);
2283 }
2284 else
2285 bits_.insert(bits_.end(), signal.bits_.begin(), signal.bits_.end());
2286
2287 width_ += signal.width_;
2288 check();
2289 }
2290
2291 void RTLIL::SigSpec::append_bit(const RTLIL::SigBit &bit)
2292 {
2293 if (packed())
2294 {
2295 cover("kernel.rtlil.sigspec.append_bit.packed");
2296
2297 if (chunks_.size() == 0)
2298 chunks_.push_back(bit);
2299 else
2300 if (bit.wire == NULL)
2301 if (chunks_.back().wire == NULL) {
2302 chunks_.back().data.bits.push_back(bit.data);
2303 chunks_.back().width++;
2304 } else
2305 chunks_.push_back(bit);
2306 else
2307 if (chunks_.back().wire == bit.wire && chunks_.back().offset + chunks_.back().width == bit.offset)
2308 chunks_.back().width++;
2309 else
2310 chunks_.push_back(bit);
2311 }
2312 else
2313 {
2314 cover("kernel.rtlil.sigspec.append_bit.unpacked");
2315 bits_.push_back(bit);
2316 }
2317
2318 width_++;
2319 check();
2320 }
2321
2322 void RTLIL::SigSpec::extend(int width, bool is_signed)
2323 {
2324 cover("kernel.rtlil.sigspec.extend");
2325
2326 pack();
2327
2328 if (width_ > width)
2329 remove(width, width_ - width);
2330
2331 if (width_ < width) {
2332 RTLIL::SigSpec padding = width_ > 0 ? extract(width_ - 1, 1) : RTLIL::SigSpec(RTLIL::State::S0);
2333 if (!is_signed && padding != RTLIL::SigSpec(RTLIL::State::Sx) && padding != RTLIL::SigSpec(RTLIL::State::Sz) &&
2334 padding != RTLIL::SigSpec(RTLIL::State::Sa) && padding != RTLIL::SigSpec(RTLIL::State::Sm))
2335 padding = RTLIL::SigSpec(RTLIL::State::S0);
2336 while (width_ < width)
2337 append(padding);
2338 }
2339 }
2340
2341 void RTLIL::SigSpec::extend_u0(int width, bool is_signed)
2342 {
2343 cover("kernel.rtlil.sigspec.extend_u0");
2344
2345 pack();
2346
2347 if (width_ > width)
2348 remove(width, width_ - width);
2349
2350 if (width_ < width) {
2351 RTLIL::SigSpec padding = width_ > 0 ? extract(width_ - 1, 1) : RTLIL::SigSpec(RTLIL::State::S0);
2352 if (!is_signed)
2353 padding = RTLIL::SigSpec(RTLIL::State::S0);
2354 while (width_ < width)
2355 append(padding);
2356 }
2357
2358 }
2359
2360 RTLIL::SigSpec RTLIL::SigSpec::repeat(int num) const
2361 {
2362 cover("kernel.rtlil.sigspec.repeat");
2363
2364 RTLIL::SigSpec sig;
2365 for (int i = 0; i < num; i++)
2366 sig.append(*this);
2367 return sig;
2368 }
2369
2370 #ifndef NDEBUG
2371 void RTLIL::SigSpec::check() const
2372 {
2373 if (width_ > 64)
2374 {
2375 cover("kernel.rtlil.sigspec.check.skip");
2376 }
2377 else if (packed())
2378 {
2379 cover("kernel.rtlil.sigspec.check.packed");
2380
2381 int w = 0;
2382 for (size_t i = 0; i < chunks_.size(); i++) {
2383 const RTLIL::SigChunk chunk = chunks_[i];
2384 if (chunk.wire == NULL) {
2385 if (i > 0)
2386 log_assert(chunks_[i-1].wire != NULL);
2387 log_assert(chunk.offset == 0);
2388 log_assert(chunk.data.bits.size() == (size_t)chunk.width);
2389 } else {
2390 if (i > 0 && chunks_[i-1].wire == chunk.wire)
2391 log_assert(chunk.offset != chunks_[i-1].offset + chunks_[i-1].width);
2392 log_assert(chunk.offset >= 0);
2393 log_assert(chunk.width >= 0);
2394 log_assert(chunk.offset + chunk.width <= chunk.wire->width);
2395 log_assert(chunk.data.bits.size() == 0);
2396 }
2397 w += chunk.width;
2398 }
2399 log_assert(w == width_);
2400 log_assert(bits_.empty());
2401 }
2402 else
2403 {
2404 cover("kernel.rtlil.sigspec.check.unpacked");
2405
2406 log_assert(width_ == SIZE(bits_));
2407 log_assert(chunks_.empty());
2408 }
2409 }
2410 #endif
2411
2412 bool RTLIL::SigSpec::operator <(const RTLIL::SigSpec &other) const
2413 {
2414 cover("kernel.rtlil.sigspec.comp_lt");
2415
2416 if (this == &other)
2417 return false;
2418
2419 if (width_ != other.width_)
2420 return width_ < other.width_;
2421
2422 pack();
2423 other.pack();
2424
2425 if (chunks_.size() != other.chunks_.size())
2426 return chunks_.size() < other.chunks_.size();
2427
2428 hash();
2429 other.hash();
2430
2431 if (hash_ != other.hash_)
2432 return hash_ < other.hash_;
2433
2434 for (size_t i = 0; i < chunks_.size(); i++)
2435 if (chunks_[i] != other.chunks_[i]) {
2436 cover("kernel.rtlil.sigspec.comp_lt.hash_collision");
2437 return chunks_[i] < other.chunks_[i];
2438 }
2439
2440 cover("kernel.rtlil.sigspec.comp_lt.equal");
2441 return false;
2442 }
2443
2444 bool RTLIL::SigSpec::operator ==(const RTLIL::SigSpec &other) const
2445 {
2446 cover("kernel.rtlil.sigspec.comp_eq");
2447
2448 if (this == &other)
2449 return true;
2450
2451 if (width_ != other.width_)
2452 return false;
2453
2454 pack();
2455 other.pack();
2456
2457 if (chunks_.size() != chunks_.size())
2458 return false;
2459
2460 hash();
2461 other.hash();
2462
2463 if (hash_ != other.hash_)
2464 return false;
2465
2466 for (size_t i = 0; i < chunks_.size(); i++)
2467 if (chunks_[i] != other.chunks_[i]) {
2468 cover("kernel.rtlil.sigspec.comp_eq.hash_collision");
2469 return false;
2470 }
2471
2472 cover("kernel.rtlil.sigspec.comp_eq.equal");
2473 return true;
2474 }
2475
2476 bool RTLIL::SigSpec::is_wire() const
2477 {
2478 cover("kernel.rtlil.sigspec.is_wire");
2479
2480 pack();
2481 return SIZE(chunks_) == 1 && chunks_[0].wire && chunks_[0].wire->width == width_;
2482 }
2483
2484 bool RTLIL::SigSpec::is_chunk() const
2485 {
2486 cover("kernel.rtlil.sigspec.is_chunk");
2487
2488 pack();
2489 return SIZE(chunks_) == 1;
2490 }
2491
2492 bool RTLIL::SigSpec::is_fully_const() const
2493 {
2494 cover("kernel.rtlil.sigspec.is_fully_const");
2495
2496 pack();
2497 for (auto it = chunks_.begin(); it != chunks_.end(); it++)
2498 if (it->width > 0 && it->wire != NULL)
2499 return false;
2500 return true;
2501 }
2502
2503 bool RTLIL::SigSpec::is_fully_def() const
2504 {
2505 cover("kernel.rtlil.sigspec.is_fully_def");
2506
2507 pack();
2508 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
2509 if (it->width > 0 && it->wire != NULL)
2510 return false;
2511 for (size_t i = 0; i < it->data.bits.size(); i++)
2512 if (it->data.bits[i] != RTLIL::State::S0 && it->data.bits[i] != RTLIL::State::S1)
2513 return false;
2514 }
2515 return true;
2516 }
2517
2518 bool RTLIL::SigSpec::is_fully_undef() const
2519 {
2520 cover("kernel.rtlil.sigspec.is_fully_undef");
2521
2522 pack();
2523 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
2524 if (it->width > 0 && it->wire != NULL)
2525 return false;
2526 for (size_t i = 0; i < it->data.bits.size(); i++)
2527 if (it->data.bits[i] != RTLIL::State::Sx && it->data.bits[i] != RTLIL::State::Sz)
2528 return false;
2529 }
2530 return true;
2531 }
2532
2533 bool RTLIL::SigSpec::has_marked_bits() const
2534 {
2535 cover("kernel.rtlil.sigspec.has_marked_bits");
2536
2537 pack();
2538 for (auto it = chunks_.begin(); it != chunks_.end(); it++)
2539 if (it->width > 0 && it->wire == NULL) {
2540 for (size_t i = 0; i < it->data.bits.size(); i++)
2541 if (it->data.bits[i] == RTLIL::State::Sm)
2542 return true;
2543 }
2544 return false;
2545 }
2546
2547 bool RTLIL::SigSpec::as_bool() const
2548 {
2549 cover("kernel.rtlil.sigspec.as_bool");
2550
2551 pack();
2552 log_assert(is_fully_const() && SIZE(chunks_) <= 1);
2553 if (width_)
2554 return chunks_[0].data.as_bool();
2555 return false;
2556 }
2557
2558 int RTLIL::SigSpec::as_int() const
2559 {
2560 cover("kernel.rtlil.sigspec.as_int");
2561
2562 pack();
2563 log_assert(is_fully_const() && SIZE(chunks_) <= 1);
2564 if (width_)
2565 return chunks_[0].data.as_int();
2566 return 0;
2567 }
2568
2569 std::string RTLIL::SigSpec::as_string() const
2570 {
2571 cover("kernel.rtlil.sigspec.as_string");
2572
2573 pack();
2574 std::string str;
2575 for (size_t i = chunks_.size(); i > 0; i--) {
2576 const RTLIL::SigChunk &chunk = chunks_[i-1];
2577 if (chunk.wire != NULL)
2578 for (int j = 0; j < chunk.width; j++)
2579 str += "?";
2580 else
2581 str += chunk.data.as_string();
2582 }
2583 return str;
2584 }
2585
2586 RTLIL::Const RTLIL::SigSpec::as_const() const
2587 {
2588 cover("kernel.rtlil.sigspec.as_const");
2589
2590 pack();
2591 log_assert(is_fully_const() && SIZE(chunks_) <= 1);
2592 if (width_)
2593 return chunks_[0].data;
2594 return RTLIL::Const();
2595 }
2596
2597 RTLIL::Wire *RTLIL::SigSpec::as_wire() const
2598 {
2599 cover("kernel.rtlil.sigspec.as_wire");
2600
2601 pack();
2602 log_assert(is_wire());
2603 return chunks_[0].wire;
2604 }
2605
2606 RTLIL::SigChunk RTLIL::SigSpec::as_chunk() const
2607 {
2608 cover("kernel.rtlil.sigspec.as_chunk");
2609
2610 pack();
2611 log_assert(is_chunk());
2612 return chunks_[0];
2613 }
2614
2615 bool RTLIL::SigSpec::match(std::string pattern) const
2616 {
2617 cover("kernel.rtlil.sigspec.match");
2618
2619 pack();
2620 std::string str = as_string();
2621 log_assert(pattern.size() == str.size());
2622
2623 for (size_t i = 0; i < pattern.size(); i++) {
2624 if (pattern[i] == ' ')
2625 continue;
2626 if (pattern[i] == '*') {
2627 if (str[i] != 'z' && str[i] != 'x')
2628 return false;
2629 continue;
2630 }
2631 if (pattern[i] != str[i])
2632 return false;
2633 }
2634
2635 return true;
2636 }
2637
2638 std::set<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_set() const
2639 {
2640 cover("kernel.rtlil.sigspec.to_sigbit_set");
2641
2642 pack();
2643 std::set<RTLIL::SigBit> sigbits;
2644 for (auto &c : chunks_)
2645 for (int i = 0; i < c.width; i++)
2646 sigbits.insert(RTLIL::SigBit(c, i));
2647 return sigbits;
2648 }
2649
2650 std::vector<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_vector() const
2651 {
2652 cover("kernel.rtlil.sigspec.to_sigbit_vector");
2653
2654 unpack();
2655 return bits_;
2656 }
2657
2658 RTLIL::SigBit RTLIL::SigSpec::to_single_sigbit() const
2659 {
2660 cover("kernel.rtlil.sigspec.to_single_sigbit");
2661
2662 pack();
2663 log_assert(width_ == 1);
2664 for (auto &c : chunks_)
2665 if (c.width)
2666 return RTLIL::SigBit(c);
2667 log_abort();
2668 }
2669
2670 static void sigspec_parse_split(std::vector<std::string> &tokens, const std::string &text, char sep)
2671 {
2672 size_t start = 0, end = 0;
2673 while ((end = text.find(sep, start)) != std::string::npos) {
2674 tokens.push_back(text.substr(start, end - start));
2675 start = end + 1;
2676 }
2677 tokens.push_back(text.substr(start));
2678 }
2679
2680 static int sigspec_parse_get_dummy_line_num()
2681 {
2682 return 0;
2683 }
2684
2685 bool RTLIL::SigSpec::parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str)
2686 {
2687 cover("kernel.rtlil.sigspec.parse");
2688
2689 std::vector<std::string> tokens;
2690 sigspec_parse_split(tokens, str, ',');
2691
2692 sig = RTLIL::SigSpec();
2693 for (int tokidx = int(tokens.size())-1; tokidx >= 0; tokidx--)
2694 {
2695 std::string netname = tokens[tokidx];
2696 std::string indices;
2697
2698 if (netname.size() == 0)
2699 continue;
2700
2701 if ('0' <= netname[0] && netname[0] <= '9') {
2702 cover("kernel.rtlil.sigspec.parse.const");
2703 AST::get_line_num = sigspec_parse_get_dummy_line_num;
2704 AST::AstNode *ast = VERILOG_FRONTEND::const2ast(netname);
2705 if (ast == NULL)
2706 return false;
2707 sig.append(RTLIL::Const(ast->bits));
2708 delete ast;
2709 continue;
2710 }
2711
2712 if (module == NULL)
2713 return false;
2714
2715 cover("kernel.rtlil.sigspec.parse.net");
2716
2717 if (netname[0] != '$' && netname[0] != '\\')
2718 netname = "\\" + netname;
2719
2720 if (module->wires_.count(netname) == 0) {
2721 size_t indices_pos = netname.size()-1;
2722 if (indices_pos > 2 && netname[indices_pos] == ']')
2723 {
2724 indices_pos--;
2725 while (indices_pos > 0 && ('0' <= netname[indices_pos] && netname[indices_pos] <= '9')) indices_pos--;
2726 if (indices_pos > 0 && netname[indices_pos] == ':') {
2727 indices_pos--;
2728 while (indices_pos > 0 && ('0' <= netname[indices_pos] && netname[indices_pos] <= '9')) indices_pos--;
2729 }
2730 if (indices_pos > 0 && netname[indices_pos] == '[') {
2731 indices = netname.substr(indices_pos);
2732 netname = netname.substr(0, indices_pos);
2733 }
2734 }
2735 }
2736
2737 if (module->wires_.count(netname) == 0)
2738 return false;
2739
2740 RTLIL::Wire *wire = module->wires_.at(netname);
2741 if (!indices.empty()) {
2742 std::vector<std::string> index_tokens;
2743 sigspec_parse_split(index_tokens, indices.substr(1, indices.size()-2), ':');
2744 if (index_tokens.size() == 1) {
2745 cover("kernel.rtlil.sigspec.parse.bit_sel");
2746 sig.append(RTLIL::SigSpec(wire, atoi(index_tokens.at(0).c_str())));
2747 } else {
2748 cover("kernel.rtlil.sigspec.parse.part_sel");
2749 int a = atoi(index_tokens.at(0).c_str());
2750 int b = atoi(index_tokens.at(1).c_str());
2751 if (a > b) {
2752 int tmp = a;
2753 a = b, b = tmp;
2754 }
2755 sig.append(RTLIL::SigSpec(wire, a, b-a+1));
2756 }
2757 } else
2758 sig.append(wire);
2759 }
2760
2761 return true;
2762 }
2763
2764 bool RTLIL::SigSpec::parse_sel(RTLIL::SigSpec &sig, RTLIL::Design *design, RTLIL::Module *module, std::string str)
2765 {
2766 if (str.empty() || str[0] != '@')
2767 return parse(sig, module, str);
2768
2769 cover("kernel.rtlil.sigspec.parse.sel");
2770
2771 str = RTLIL::escape_id(str.substr(1));
2772 if (design->selection_vars.count(str) == 0)
2773 return false;
2774
2775 sig = RTLIL::SigSpec();
2776 RTLIL::Selection &sel = design->selection_vars.at(str);
2777 for (auto &it : module->wires_)
2778 if (sel.selected_member(module->name, it.first))
2779 sig.append(it.second);
2780
2781 return true;
2782 }
2783
2784 bool RTLIL::SigSpec::parse_rhs(const RTLIL::SigSpec &lhs, RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str)
2785 {
2786 if (str == "0") {
2787 cover("kernel.rtlil.sigspec.parse.rhs_zeros");
2788 sig = RTLIL::SigSpec(RTLIL::State::S0, lhs.width_);
2789 return true;
2790 }
2791
2792 if (str == "~0") {
2793 cover("kernel.rtlil.sigspec.parse.rhs_ones");
2794 sig = RTLIL::SigSpec(RTLIL::State::S1, lhs.width_);
2795 return true;
2796 }
2797
2798 if (lhs.chunks_.size() == 1) {
2799 char *p = (char*)str.c_str(), *endptr;
2800 long long int val = strtoll(p, &endptr, 10);
2801 if (endptr && endptr != p && *endptr == 0) {
2802 sig = RTLIL::SigSpec(val, lhs.width_);
2803 cover("kernel.rtlil.sigspec.parse.rhs_dec");
2804 return true;
2805 }
2806 }
2807
2808 return parse(sig, module, str);
2809 }
2810
2811 RTLIL::CaseRule::~CaseRule()
2812 {
2813 for (auto it = switches.begin(); it != switches.end(); it++)
2814 delete *it;
2815 }
2816
2817 RTLIL::CaseRule *RTLIL::CaseRule::clone() const
2818 {
2819 RTLIL::CaseRule *new_caserule = new RTLIL::CaseRule;
2820 new_caserule->compare = compare;
2821 new_caserule->actions = actions;
2822 for (auto &it : switches)
2823 new_caserule->switches.push_back(it->clone());
2824 return new_caserule;
2825 }
2826
2827 RTLIL::SwitchRule::~SwitchRule()
2828 {
2829 for (auto it = cases.begin(); it != cases.end(); it++)
2830 delete *it;
2831 }
2832
2833 RTLIL::SwitchRule *RTLIL::SwitchRule::clone() const
2834 {
2835 RTLIL::SwitchRule *new_switchrule = new RTLIL::SwitchRule;
2836 new_switchrule->signal = signal;
2837 new_switchrule->attributes = attributes;
2838 for (auto &it : cases)
2839 new_switchrule->cases.push_back(it->clone());
2840 return new_switchrule;
2841
2842 }
2843
2844 RTLIL::SyncRule *RTLIL::SyncRule::clone() const
2845 {
2846 RTLIL::SyncRule *new_syncrule = new RTLIL::SyncRule;
2847 new_syncrule->type = type;
2848 new_syncrule->signal = signal;
2849 new_syncrule->actions = actions;
2850 return new_syncrule;
2851 }
2852
2853 RTLIL::Process::~Process()
2854 {
2855 for (auto it = syncs.begin(); it != syncs.end(); it++)
2856 delete *it;
2857 }
2858
2859 RTLIL::Process *RTLIL::Process::clone() const
2860 {
2861 RTLIL::Process *new_proc = new RTLIL::Process;
2862
2863 new_proc->name = name;
2864 new_proc->attributes = attributes;
2865
2866 RTLIL::CaseRule *rc_ptr = root_case.clone();
2867 new_proc->root_case = *rc_ptr;
2868 rc_ptr->switches.clear();
2869 delete rc_ptr;
2870
2871 for (auto &it : syncs)
2872 new_proc->syncs.push_back(it->clone());
2873
2874 return new_proc;
2875 }
2876
2877 YOSYS_NAMESPACE_END
2878