2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include "kernel/yosys.h"
21 #include "kernel/macc.h"
22 #include "kernel/celltypes.h"
23 #include "frontends/verilog/verilog_frontend.h"
24 #include "frontends/verilog/preproc.h"
25 #include "backends/ilang/ilang_backend.h"
32 RTLIL::IdString::destruct_guard_t
RTLIL::IdString::destruct_guard
;
33 std::vector
<char*> RTLIL::IdString::global_id_storage_
;
34 dict
<char*, int, hash_cstr_ops
> RTLIL::IdString::global_id_index_
;
35 #ifndef YOSYS_NO_IDS_REFCNT
36 std::vector
<int> RTLIL::IdString::global_refcount_storage_
;
37 std::vector
<int> RTLIL::IdString::global_free_idx_list_
;
39 #ifdef YOSYS_USE_STICKY_IDS
40 int RTLIL::IdString::last_created_idx_
[8];
41 int RTLIL::IdString::last_created_idx_ptr_
;
44 #define X(_id) IdString RTLIL::ID::_id;
45 #include "kernel/constids.inc"
48 dict
<std::string
, std::string
> RTLIL::constpad
;
52 flags
= RTLIL::CONST_FLAG_NONE
;
55 RTLIL::Const::Const(std::string str
)
57 flags
= RTLIL::CONST_FLAG_STRING
;
58 for (int i
= str
.size()-1; i
>= 0; i
--) {
59 unsigned char ch
= str
[i
];
60 for (int j
= 0; j
< 8; j
++) {
61 bits
.push_back((ch
& 1) != 0 ? State::S1
: State::S0
);
67 RTLIL::Const::Const(int val
, int width
)
69 flags
= RTLIL::CONST_FLAG_NONE
;
70 for (int i
= 0; i
< width
; i
++) {
71 bits
.push_back((val
& 1) != 0 ? State::S1
: State::S0
);
76 RTLIL::Const::Const(RTLIL::State bit
, int width
)
78 flags
= RTLIL::CONST_FLAG_NONE
;
79 for (int i
= 0; i
< width
; i
++)
83 RTLIL::Const::Const(const std::vector
<bool> &bits
)
85 flags
= RTLIL::CONST_FLAG_NONE
;
86 for (const auto &b
: bits
)
87 this->bits
.emplace_back(b
? State::S1
: State::S0
);
90 RTLIL::Const::Const(const RTLIL::Const
&c
)
93 for (const auto &b
: c
.bits
)
94 this->bits
.push_back(b
);
97 bool RTLIL::Const::operator <(const RTLIL::Const
&other
) const
99 if (bits
.size() != other
.bits
.size())
100 return bits
.size() < other
.bits
.size();
101 for (size_t i
= 0; i
< bits
.size(); i
++)
102 if (bits
[i
] != other
.bits
[i
])
103 return bits
[i
] < other
.bits
[i
];
107 bool RTLIL::Const::operator ==(const RTLIL::Const
&other
) const
109 return bits
== other
.bits
;
112 bool RTLIL::Const::operator !=(const RTLIL::Const
&other
) const
114 return bits
!= other
.bits
;
117 bool RTLIL::Const::as_bool() const
119 for (size_t i
= 0; i
< bits
.size(); i
++)
120 if (bits
[i
] == State::S1
)
125 int RTLIL::Const::as_int(bool is_signed
) const
128 for (size_t i
= 0; i
< bits
.size() && i
< 32; i
++)
129 if (bits
[i
] == State::S1
)
131 if (is_signed
&& bits
.back() == State::S1
)
132 for (size_t i
= bits
.size(); i
< 32; i
++)
137 std::string
RTLIL::Const::as_string() const
140 ret
.reserve(bits
.size());
141 for (size_t i
= bits
.size(); i
> 0; i
--)
143 case S0
: ret
+= "0"; break;
144 case S1
: ret
+= "1"; break;
145 case Sx
: ret
+= "x"; break;
146 case Sz
: ret
+= "z"; break;
147 case Sa
: ret
+= "-"; break;
148 case Sm
: ret
+= "m"; break;
153 RTLIL::Const
RTLIL::Const::from_string(const std::string
&str
)
156 c
.bits
.reserve(str
.size());
157 for (auto it
= str
.rbegin(); it
!= str
.rend(); it
++)
159 case '0': c
.bits
.push_back(State::S0
); break;
160 case '1': c
.bits
.push_back(State::S1
); break;
161 case 'x': c
.bits
.push_back(State::Sx
); break;
162 case 'z': c
.bits
.push_back(State::Sz
); break;
163 case 'm': c
.bits
.push_back(State::Sm
); break;
164 default: c
.bits
.push_back(State::Sa
);
169 std::string
RTLIL::Const::decode_string() const
172 string
.reserve(GetSize(bits
)/8);
173 for (int i
= 0; i
< GetSize(bits
); i
+= 8) {
175 for (int j
= 0; j
< 8 && i
+ j
< int (bits
.size()); j
++)
176 if (bits
[i
+ j
] == RTLIL::State::S1
)
181 std::reverse(string
.begin(), string
.end());
185 bool RTLIL::Const::is_fully_zero() const
187 cover("kernel.rtlil.const.is_fully_zero");
189 for (const auto &bit
: bits
)
190 if (bit
!= RTLIL::State::S0
)
196 bool RTLIL::Const::is_fully_ones() const
198 cover("kernel.rtlil.const.is_fully_ones");
200 for (const auto &bit
: bits
)
201 if (bit
!= RTLIL::State::S1
)
207 bool RTLIL::Const::is_fully_def() const
209 cover("kernel.rtlil.const.is_fully_def");
211 for (const auto &bit
: bits
)
212 if (bit
!= RTLIL::State::S0
&& bit
!= RTLIL::State::S1
)
218 bool RTLIL::Const::is_fully_undef() const
220 cover("kernel.rtlil.const.is_fully_undef");
222 for (const auto &bit
: bits
)
223 if (bit
!= RTLIL::State::Sx
&& bit
!= RTLIL::State::Sz
)
229 void RTLIL::AttrObject::set_bool_attribute(RTLIL::IdString id
, bool value
)
232 attributes
[id
] = RTLIL::Const(1);
234 attributes
.erase(id
);
237 bool RTLIL::AttrObject::get_bool_attribute(RTLIL::IdString id
) const
239 const auto it
= attributes
.find(id
);
240 if (it
== attributes
.end())
242 return it
->second
.as_bool();
245 void RTLIL::AttrObject::set_strpool_attribute(RTLIL::IdString id
, const pool
<string
> &data
)
248 for (const auto &s
: data
) {
249 if (!attrval
.empty())
253 attributes
[id
] = RTLIL::Const(attrval
);
256 void RTLIL::AttrObject::add_strpool_attribute(RTLIL::IdString id
, const pool
<string
> &data
)
258 pool
<string
> union_data
= get_strpool_attribute(id
);
259 union_data
.insert(data
.begin(), data
.end());
260 if (!union_data
.empty())
261 set_strpool_attribute(id
, union_data
);
264 pool
<string
> RTLIL::AttrObject::get_strpool_attribute(RTLIL::IdString id
) const
267 if (attributes
.count(id
) != 0)
268 for (auto s
: split_tokens(attributes
.at(id
).decode_string(), "|"))
273 void RTLIL::AttrObject::set_src_attribute(const std::string
&src
)
276 attributes
.erase(ID::src
);
278 attributes
[ID::src
] = src
;
281 std::string
RTLIL::AttrObject::get_src_attribute() const
284 const auto it
= attributes
.find(ID::src
);
285 if (it
!= attributes
.end())
286 src
= it
->second
.decode_string();
290 bool RTLIL::Selection::selected_module(RTLIL::IdString mod_name
) const
294 if (selected_modules
.count(mod_name
) > 0)
296 if (selected_members
.count(mod_name
) > 0)
301 bool RTLIL::Selection::selected_whole_module(RTLIL::IdString mod_name
) const
305 if (selected_modules
.count(mod_name
) > 0)
310 bool RTLIL::Selection::selected_member(RTLIL::IdString mod_name
, RTLIL::IdString memb_name
) const
314 if (selected_modules
.count(mod_name
) > 0)
316 if (selected_members
.count(mod_name
) > 0)
317 if (selected_members
.at(mod_name
).count(memb_name
) > 0)
322 void RTLIL::Selection::optimize(RTLIL::Design
*design
)
324 if (full_selection
) {
325 selected_modules
.clear();
326 selected_members
.clear();
330 std::vector
<RTLIL::IdString
> del_list
, add_list
;
333 for (auto mod_name
: selected_modules
) {
334 if (design
->modules_
.count(mod_name
) == 0)
335 del_list
.push_back(mod_name
);
336 selected_members
.erase(mod_name
);
338 for (auto mod_name
: del_list
)
339 selected_modules
.erase(mod_name
);
342 for (auto &it
: selected_members
)
343 if (design
->modules_
.count(it
.first
) == 0)
344 del_list
.push_back(it
.first
);
345 for (auto mod_name
: del_list
)
346 selected_members
.erase(mod_name
);
348 for (auto &it
: selected_members
) {
350 for (auto memb_name
: it
.second
)
351 if (design
->modules_
[it
.first
]->count_id(memb_name
) == 0)
352 del_list
.push_back(memb_name
);
353 for (auto memb_name
: del_list
)
354 it
.second
.erase(memb_name
);
359 for (auto &it
: selected_members
)
360 if (it
.second
.size() == 0)
361 del_list
.push_back(it
.first
);
362 else if (it
.second
.size() == design
->modules_
[it
.first
]->wires_
.size() + design
->modules_
[it
.first
]->memories
.size() +
363 design
->modules_
[it
.first
]->cells_
.size() + design
->modules_
[it
.first
]->processes
.size())
364 add_list
.push_back(it
.first
);
365 for (auto mod_name
: del_list
)
366 selected_members
.erase(mod_name
);
367 for (auto mod_name
: add_list
) {
368 selected_members
.erase(mod_name
);
369 selected_modules
.insert(mod_name
);
372 if (selected_modules
.size() == design
->modules_
.size()) {
373 full_selection
= true;
374 selected_modules
.clear();
375 selected_members
.clear();
379 RTLIL::Design::Design()
380 : verilog_defines (new define_map_t
)
382 static unsigned int hashidx_count
= 123456789;
383 hashidx_count
= mkhash_xorshift(hashidx_count
);
384 hashidx_
= hashidx_count
;
386 refcount_modules_
= 0;
387 selection_stack
.push_back(RTLIL::Selection());
390 RTLIL::Design::get_all_designs()->insert(std::pair
<unsigned int, RTLIL::Design
*>(hashidx_
, this));
394 RTLIL::Design::~Design()
396 for (auto it
= modules_
.begin(); it
!= modules_
.end(); ++it
)
398 for (auto n
: verilog_packages
)
400 for (auto n
: verilog_globals
)
403 RTLIL::Design::get_all_designs()->erase(hashidx_
);
408 static std::map
<unsigned int, RTLIL::Design
*> all_designs
;
409 std::map
<unsigned int, RTLIL::Design
*> *RTLIL::Design::get_all_designs(void)
415 RTLIL::ObjRange
<RTLIL::Module
*> RTLIL::Design::modules()
417 return RTLIL::ObjRange
<RTLIL::Module
*>(&modules_
, &refcount_modules_
);
420 RTLIL::Module
*RTLIL::Design::module(RTLIL::IdString name
)
422 return modules_
.count(name
) ? modules_
.at(name
) : NULL
;
425 RTLIL::Module
*RTLIL::Design::top_module()
427 RTLIL::Module
*module
= nullptr;
428 int module_count
= 0;
430 for (auto mod
: selected_modules()) {
431 if (mod
->get_bool_attribute(ID::top
))
437 return module_count
== 1 ? module
: nullptr;
440 void RTLIL::Design::add(RTLIL::Module
*module
)
442 log_assert(modules_
.count(module
->name
) == 0);
443 log_assert(refcount_modules_
== 0);
444 modules_
[module
->name
] = module
;
445 module
->design
= this;
447 for (auto mon
: monitors
)
448 mon
->notify_module_add(module
);
451 log("#X# New Module: %s\n", log_id(module
));
452 log_backtrace("-X- ", yosys_xtrace
-1);
456 RTLIL::Module
*RTLIL::Design::addModule(RTLIL::IdString name
)
458 log_assert(modules_
.count(name
) == 0);
459 log_assert(refcount_modules_
== 0);
461 RTLIL::Module
*module
= new RTLIL::Module
;
462 modules_
[name
] = module
;
463 module
->design
= this;
466 for (auto mon
: monitors
)
467 mon
->notify_module_add(module
);
470 log("#X# New Module: %s\n", log_id(module
));
471 log_backtrace("-X- ", yosys_xtrace
-1);
477 void RTLIL::Design::scratchpad_unset(const std::string
&varname
)
479 scratchpad
.erase(varname
);
482 void RTLIL::Design::scratchpad_set_int(const std::string
&varname
, int value
)
484 scratchpad
[varname
] = stringf("%d", value
);
487 void RTLIL::Design::scratchpad_set_bool(const std::string
&varname
, bool value
)
489 scratchpad
[varname
] = value
? "true" : "false";
492 void RTLIL::Design::scratchpad_set_string(const std::string
&varname
, std::string value
)
494 scratchpad
[varname
] = std::move(value
);
497 int RTLIL::Design::scratchpad_get_int(const std::string
&varname
, int default_value
) const
499 auto it
= scratchpad
.find(varname
);
500 if (it
== scratchpad
.end())
501 return default_value
;
503 const std::string
&str
= it
->second
;
505 if (str
== "0" || str
== "false")
508 if (str
== "1" || str
== "true")
511 char *endptr
= nullptr;
512 long int parsed_value
= strtol(str
.c_str(), &endptr
, 10);
513 return *endptr
? default_value
: parsed_value
;
516 bool RTLIL::Design::scratchpad_get_bool(const std::string
&varname
, bool default_value
) const
518 auto it
= scratchpad
.find(varname
);
519 if (it
== scratchpad
.end())
520 return default_value
;
522 const std::string
&str
= it
->second
;
524 if (str
== "0" || str
== "false")
527 if (str
== "1" || str
== "true")
530 return default_value
;
533 std::string
RTLIL::Design::scratchpad_get_string(const std::string
&varname
, const std::string
&default_value
) const
535 auto it
= scratchpad
.find(varname
);
536 if (it
== scratchpad
.end())
537 return default_value
;
542 void RTLIL::Design::remove(RTLIL::Module
*module
)
544 for (auto mon
: monitors
)
545 mon
->notify_module_del(module
);
548 log("#X# Remove Module: %s\n", log_id(module
));
549 log_backtrace("-X- ", yosys_xtrace
-1);
552 log_assert(modules_
.at(module
->name
) == module
);
553 modules_
.erase(module
->name
);
557 void RTLIL::Design::rename(RTLIL::Module
*module
, RTLIL::IdString new_name
)
559 modules_
.erase(module
->name
);
560 module
->name
= new_name
;
564 void RTLIL::Design::sort()
567 modules_
.sort(sort_by_id_str());
568 for (auto &it
: modules_
)
572 void RTLIL::Design::check()
575 for (auto &it
: modules_
) {
576 log_assert(this == it
.second
->design
);
577 log_assert(it
.first
== it
.second
->name
);
578 log_assert(!it
.first
.empty());
584 void RTLIL::Design::optimize()
586 for (auto &it
: modules_
)
587 it
.second
->optimize();
588 for (auto &it
: selection_stack
)
590 for (auto &it
: selection_vars
)
591 it
.second
.optimize(this);
594 bool RTLIL::Design::selected_module(RTLIL::IdString mod_name
) const
596 if (!selected_active_module
.empty() && mod_name
!= selected_active_module
)
598 if (selection_stack
.size() == 0)
600 return selection_stack
.back().selected_module(mod_name
);
603 bool RTLIL::Design::selected_whole_module(RTLIL::IdString mod_name
) const
605 if (!selected_active_module
.empty() && mod_name
!= selected_active_module
)
607 if (selection_stack
.size() == 0)
609 return selection_stack
.back().selected_whole_module(mod_name
);
612 bool RTLIL::Design::selected_member(RTLIL::IdString mod_name
, RTLIL::IdString memb_name
) const
614 if (!selected_active_module
.empty() && mod_name
!= selected_active_module
)
616 if (selection_stack
.size() == 0)
618 return selection_stack
.back().selected_member(mod_name
, memb_name
);
621 bool RTLIL::Design::selected_module(RTLIL::Module
*mod
) const
623 return selected_module(mod
->name
);
626 bool RTLIL::Design::selected_whole_module(RTLIL::Module
*mod
) const
628 return selected_whole_module(mod
->name
);
631 std::vector
<RTLIL::Module
*> RTLIL::Design::selected_modules() const
633 std::vector
<RTLIL::Module
*> result
;
634 result
.reserve(modules_
.size());
635 for (auto &it
: modules_
)
636 if (selected_module(it
.first
) && !it
.second
->get_blackbox_attribute())
637 result
.push_back(it
.second
);
641 std::vector
<RTLIL::Module
*> RTLIL::Design::selected_whole_modules() const
643 std::vector
<RTLIL::Module
*> result
;
644 result
.reserve(modules_
.size());
645 for (auto &it
: modules_
)
646 if (selected_whole_module(it
.first
) && !it
.second
->get_blackbox_attribute())
647 result
.push_back(it
.second
);
651 std::vector
<RTLIL::Module
*> RTLIL::Design::selected_whole_modules_warn() const
653 std::vector
<RTLIL::Module
*> result
;
654 result
.reserve(modules_
.size());
655 for (auto &it
: modules_
)
656 if (it
.second
->get_blackbox_attribute())
658 else if (selected_whole_module(it
.first
))
659 result
.push_back(it
.second
);
660 else if (selected_module(it
.first
))
661 log_warning("Ignoring partially selected module %s.\n", log_id(it
.first
));
665 RTLIL::Module::Module()
667 static unsigned int hashidx_count
= 123456789;
668 hashidx_count
= mkhash_xorshift(hashidx_count
);
669 hashidx_
= hashidx_count
;
676 RTLIL::Module::get_all_modules()->insert(std::pair
<unsigned int, RTLIL::Module
*>(hashidx_
, this));
680 RTLIL::Module::~Module()
682 for (auto it
= wires_
.begin(); it
!= wires_
.end(); ++it
)
684 for (auto it
= memories
.begin(); it
!= memories
.end(); ++it
)
686 for (auto it
= cells_
.begin(); it
!= cells_
.end(); ++it
)
688 for (auto it
= processes
.begin(); it
!= processes
.end(); ++it
)
691 RTLIL::Module::get_all_modules()->erase(hashidx_
);
696 static std::map
<unsigned int, RTLIL::Module
*> all_modules
;
697 std::map
<unsigned int, RTLIL::Module
*> *RTLIL::Module::get_all_modules(void)
703 void RTLIL::Module::makeblackbox()
705 pool
<RTLIL::Wire
*> delwires
;
707 for (auto it
= wires_
.begin(); it
!= wires_
.end(); ++it
)
708 if (!it
->second
->port_input
&& !it
->second
->port_output
)
709 delwires
.insert(it
->second
);
711 for (auto it
= memories
.begin(); it
!= memories
.end(); ++it
)
715 for (auto it
= cells_
.begin(); it
!= cells_
.end(); ++it
)
719 for (auto it
= processes
.begin(); it
!= processes
.end(); ++it
)
724 set_bool_attribute(ID::blackbox
);
727 void RTLIL::Module::reprocess_module(RTLIL::Design
*, const dict
<RTLIL::IdString
, RTLIL::Module
*> &)
729 log_error("Cannot reprocess_module module `%s' !\n", id2cstr(name
));
732 RTLIL::IdString
RTLIL::Module::derive(RTLIL::Design
*, const dict
<RTLIL::IdString
, RTLIL::Const
> &, bool mayfail
)
735 return RTLIL::IdString();
736 log_error("Module `%s' is used with parameters but is not parametric!\n", id2cstr(name
));
740 RTLIL::IdString
RTLIL::Module::derive(RTLIL::Design
*, const dict
<RTLIL::IdString
, RTLIL::Const
> &, const dict
<RTLIL::IdString
, RTLIL::Module
*> &, const dict
<RTLIL::IdString
, RTLIL::IdString
> &, bool mayfail
)
743 return RTLIL::IdString();
744 log_error("Module `%s' is used with parameters but is not parametric!\n", id2cstr(name
));
747 size_t RTLIL::Module::count_id(RTLIL::IdString id
)
749 return wires_
.count(id
) + memories
.count(id
) + cells_
.count(id
) + processes
.count(id
);
754 struct InternalCellChecker
756 RTLIL::Module
*module
;
758 pool
<RTLIL::IdString
> expected_params
, expected_ports
;
760 InternalCellChecker(RTLIL::Module
*module
, RTLIL::Cell
*cell
) : module(module
), cell(cell
) { }
762 void error(int linenr
)
764 std::stringstream buf
;
765 ILANG_BACKEND::dump_cell(buf
, " ", cell
);
767 log_error("Found error in internal cell %s%s%s (%s) at %s:%d:\n%s",
768 module
? module
->name
.c_str() : "", module
? "." : "",
769 cell
->name
.c_str(), cell
->type
.c_str(), __FILE__
, linenr
, buf
.str().c_str());
772 int param(RTLIL::IdString name
)
774 auto it
= cell
->parameters
.find(name
);
775 if (it
== cell
->parameters
.end())
777 expected_params
.insert(name
);
778 return it
->second
.as_int();
781 int param_bool(RTLIL::IdString name
)
784 if (GetSize(cell
->parameters
.at(name
)) > 32)
786 if (v
!= 0 && v
!= 1)
791 int param_bool(RTLIL::IdString name
, bool expected
)
793 int v
= param_bool(name
);
799 void param_bits(RTLIL::IdString name
, int width
)
802 if (GetSize(cell
->parameters
.at(name
).bits
) != width
)
806 void port(RTLIL::IdString name
, int width
)
808 auto it
= cell
->connections_
.find(name
);
809 if (it
== cell
->connections_
.end())
811 if (GetSize(it
->second
) != width
)
813 expected_ports
.insert(name
);
816 void check_expected(bool check_matched_sign
= false)
818 for (auto ¶
: cell
->parameters
)
819 if (expected_params
.count(para
.first
) == 0)
821 for (auto &conn
: cell
->connections())
822 if (expected_ports
.count(conn
.first
) == 0)
825 if (check_matched_sign
) {
826 log_assert(expected_params
.count(ID::A_SIGNED
) != 0 && expected_params
.count(ID::B_SIGNED
) != 0);
827 bool a_is_signed
= cell
->parameters
.at(ID::A_SIGNED
).as_bool();
828 bool b_is_signed
= cell
->parameters
.at(ID::B_SIGNED
).as_bool();
829 if (a_is_signed
!= b_is_signed
)
836 if (!cell
->type
.begins_with("$") || cell
->type
.begins_with("$__") || cell
->type
.begins_with("$paramod") || cell
->type
.begins_with("$fmcombine") ||
837 cell
->type
.begins_with("$verific$") || cell
->type
.begins_with("$array:") || cell
->type
.begins_with("$extern:"))
840 if (cell
->type
.in(ID($
not), ID($pos
), ID($neg
))) {
841 param_bool(ID::A_SIGNED
);
842 port(ID::A
, param(ID::A_WIDTH
));
843 port(ID::Y
, param(ID::Y_WIDTH
));
848 if (cell
->type
.in(ID($
and), ID($
or), ID($
xor), ID($xnor
))) {
849 param_bool(ID::A_SIGNED
);
850 param_bool(ID::B_SIGNED
);
851 port(ID::A
, param(ID::A_WIDTH
));
852 port(ID::B
, param(ID::B_WIDTH
));
853 port(ID::Y
, param(ID::Y_WIDTH
));
854 check_expected(true);
858 if (cell
->type
.in(ID($reduce_and
), ID($reduce_or
), ID($reduce_xor
), ID($reduce_xnor
), ID($reduce_bool
))) {
859 param_bool(ID::A_SIGNED
);
860 port(ID::A
, param(ID::A_WIDTH
));
861 port(ID::Y
, param(ID::Y_WIDTH
));
866 if (cell
->type
.in(ID($shl
), ID($shr
), ID($sshl
), ID($sshr
))) {
867 param_bool(ID::A_SIGNED
);
868 param_bool(ID::B_SIGNED
, /*expected=*/false);
869 port(ID::A
, param(ID::A_WIDTH
));
870 port(ID::B
, param(ID::B_WIDTH
));
871 port(ID::Y
, param(ID::Y_WIDTH
));
872 check_expected(/*check_matched_sign=*/false);
876 if (cell
->type
.in(ID($shift
), ID($shiftx
))) {
877 param_bool(ID::A_SIGNED
);
878 param_bool(ID::B_SIGNED
);
879 port(ID::A
, param(ID::A_WIDTH
));
880 port(ID::B
, param(ID::B_WIDTH
));
881 port(ID::Y
, param(ID::Y_WIDTH
));
882 check_expected(/*check_matched_sign=*/false);
886 if (cell
->type
.in(ID($lt
), ID($le
), ID($eq
), ID($ne
), ID($eqx
), ID($nex
), ID($ge
), ID($gt
))) {
887 param_bool(ID::A_SIGNED
);
888 param_bool(ID::B_SIGNED
);
889 port(ID::A
, param(ID::A_WIDTH
));
890 port(ID::B
, param(ID::B_WIDTH
));
891 port(ID::Y
, param(ID::Y_WIDTH
));
892 check_expected(true);
896 if (cell
->type
.in(ID($add
), ID($sub
), ID($mul
), ID($div
), ID($mod
), ID($pow
))) {
897 param_bool(ID::A_SIGNED
);
898 param_bool(ID::B_SIGNED
);
899 port(ID::A
, param(ID::A_WIDTH
));
900 port(ID::B
, param(ID::B_WIDTH
));
901 port(ID::Y
, param(ID::Y_WIDTH
));
902 check_expected(cell
->type
!= ID($pow
));
906 if (cell
->type
== ID($fa
)) {
907 port(ID::A
, param(ID::WIDTH
));
908 port(ID::B
, param(ID::WIDTH
));
909 port(ID::C
, param(ID::WIDTH
));
910 port(ID::X
, param(ID::WIDTH
));
911 port(ID::Y
, param(ID::WIDTH
));
916 if (cell
->type
== ID($lcu
)) {
917 port(ID::P
, param(ID::WIDTH
));
918 port(ID::G
, param(ID::WIDTH
));
920 port(ID::CO
, param(ID::WIDTH
));
925 if (cell
->type
== ID($alu
)) {
926 param_bool(ID::A_SIGNED
);
927 param_bool(ID::B_SIGNED
);
928 port(ID::A
, param(ID::A_WIDTH
));
929 port(ID::B
, param(ID::B_WIDTH
));
932 port(ID::X
, param(ID::Y_WIDTH
));
933 port(ID::Y
, param(ID::Y_WIDTH
));
934 port(ID::CO
, param(ID::Y_WIDTH
));
935 check_expected(true);
939 if (cell
->type
== ID($macc
)) {
941 param(ID::CONFIG_WIDTH
);
942 port(ID::A
, param(ID::A_WIDTH
));
943 port(ID::B
, param(ID::B_WIDTH
));
944 port(ID::Y
, param(ID::Y_WIDTH
));
946 Macc().from_cell(cell
);
950 if (cell
->type
== ID($logic_not
)) {
951 param_bool(ID::A_SIGNED
);
952 port(ID::A
, param(ID::A_WIDTH
));
953 port(ID::Y
, param(ID::Y_WIDTH
));
958 if (cell
->type
.in(ID($logic_and
), ID($logic_or
))) {
959 param_bool(ID::A_SIGNED
);
960 param_bool(ID::B_SIGNED
);
961 port(ID::A
, param(ID::A_WIDTH
));
962 port(ID::B
, param(ID::B_WIDTH
));
963 port(ID::Y
, param(ID::Y_WIDTH
));
964 check_expected(/*check_matched_sign=*/false);
968 if (cell
->type
== ID($slice
)) {
970 port(ID::A
, param(ID::A_WIDTH
));
971 port(ID::Y
, param(ID::Y_WIDTH
));
972 if (param(ID::OFFSET
) + param(ID::Y_WIDTH
) > param(ID::A_WIDTH
))
978 if (cell
->type
== ID($concat
)) {
979 port(ID::A
, param(ID::A_WIDTH
));
980 port(ID::B
, param(ID::B_WIDTH
));
981 port(ID::Y
, param(ID::A_WIDTH
) + param(ID::B_WIDTH
));
986 if (cell
->type
== ID($mux
)) {
987 port(ID::A
, param(ID::WIDTH
));
988 port(ID::B
, param(ID::WIDTH
));
990 port(ID::Y
, param(ID::WIDTH
));
995 if (cell
->type
== ID($pmux
)) {
996 port(ID::A
, param(ID::WIDTH
));
997 port(ID::B
, param(ID::WIDTH
) * param(ID::S_WIDTH
));
998 port(ID::S
, param(ID::S_WIDTH
));
999 port(ID::Y
, param(ID::WIDTH
));
1004 if (cell
->type
== ID($lut
)) {
1006 port(ID::A
, param(ID::WIDTH
));
1012 if (cell
->type
== ID($sop
)) {
1015 port(ID::A
, param(ID::WIDTH
));
1021 if (cell
->type
== ID($sr
)) {
1022 param_bool(ID::SET_POLARITY
);
1023 param_bool(ID::CLR_POLARITY
);
1024 port(ID::SET
, param(ID::WIDTH
));
1025 port(ID::CLR
, param(ID::WIDTH
));
1026 port(ID::Q
, param(ID::WIDTH
));
1031 if (cell
->type
== ID($ff
)) {
1032 port(ID::D
, param(ID::WIDTH
));
1033 port(ID::Q
, param(ID::WIDTH
));
1038 if (cell
->type
== ID($dff
)) {
1039 param_bool(ID::CLK_POLARITY
);
1041 port(ID::D
, param(ID::WIDTH
));
1042 port(ID::Q
, param(ID::WIDTH
));
1047 if (cell
->type
== ID($dffe
)) {
1048 param_bool(ID::CLK_POLARITY
);
1049 param_bool(ID::EN_POLARITY
);
1052 port(ID::D
, param(ID::WIDTH
));
1053 port(ID::Q
, param(ID::WIDTH
));
1058 if (cell
->type
== ID($dffsr
)) {
1059 param_bool(ID::CLK_POLARITY
);
1060 param_bool(ID::SET_POLARITY
);
1061 param_bool(ID::CLR_POLARITY
);
1063 port(ID::SET
, param(ID::WIDTH
));
1064 port(ID::CLR
, param(ID::WIDTH
));
1065 port(ID::D
, param(ID::WIDTH
));
1066 port(ID::Q
, param(ID::WIDTH
));
1071 if (cell
->type
== ID($adff
)) {
1072 param_bool(ID::CLK_POLARITY
);
1073 param_bool(ID::ARST_POLARITY
);
1074 param_bits(ID::ARST_VALUE
, param(ID::WIDTH
));
1077 port(ID::D
, param(ID::WIDTH
));
1078 port(ID::Q
, param(ID::WIDTH
));
1083 if (cell
->type
== ID($dlatch
)) {
1084 param_bool(ID::EN_POLARITY
);
1086 port(ID::D
, param(ID::WIDTH
));
1087 port(ID::Q
, param(ID::WIDTH
));
1092 if (cell
->type
== ID($dlatchsr
)) {
1093 param_bool(ID::EN_POLARITY
);
1094 param_bool(ID::SET_POLARITY
);
1095 param_bool(ID::CLR_POLARITY
);
1097 port(ID::SET
, param(ID::WIDTH
));
1098 port(ID::CLR
, param(ID::WIDTH
));
1099 port(ID::D
, param(ID::WIDTH
));
1100 port(ID::Q
, param(ID::WIDTH
));
1105 if (cell
->type
== ID($fsm
)) {
1107 param_bool(ID::CLK_POLARITY
);
1108 param_bool(ID::ARST_POLARITY
);
1109 param(ID::STATE_BITS
);
1110 param(ID::STATE_NUM
);
1111 param(ID::STATE_NUM_LOG2
);
1112 param(ID::STATE_RST
);
1113 param_bits(ID::STATE_TABLE
, param(ID::STATE_BITS
) * param(ID::STATE_NUM
));
1114 param(ID::TRANS_NUM
);
1115 param_bits(ID::TRANS_TABLE
, param(ID::TRANS_NUM
) * (2*param(ID::STATE_NUM_LOG2
) + param(ID::CTRL_IN_WIDTH
) + param(ID::CTRL_OUT_WIDTH
)));
1118 port(ID::CTRL_IN
, param(ID::CTRL_IN_WIDTH
));
1119 port(ID::CTRL_OUT
, param(ID::CTRL_OUT_WIDTH
));
1124 if (cell
->type
== ID($memrd
)) {
1126 param_bool(ID::CLK_ENABLE
);
1127 param_bool(ID::CLK_POLARITY
);
1128 param_bool(ID::TRANSPARENT
);
1131 port(ID::ADDR
, param(ID::ABITS
));
1132 port(ID::DATA
, param(ID::WIDTH
));
1137 if (cell
->type
== ID($memwr
)) {
1139 param_bool(ID::CLK_ENABLE
);
1140 param_bool(ID::CLK_POLARITY
);
1141 param(ID::PRIORITY
);
1143 port(ID::EN
, param(ID::WIDTH
));
1144 port(ID::ADDR
, param(ID::ABITS
));
1145 port(ID::DATA
, param(ID::WIDTH
));
1150 if (cell
->type
== ID($meminit
)) {
1152 param(ID::PRIORITY
);
1153 port(ID::ADDR
, param(ID::ABITS
));
1154 port(ID::DATA
, param(ID::WIDTH
) * param(ID::WORDS
));
1159 if (cell
->type
== ID($mem
)) {
1164 param_bits(ID::RD_CLK_ENABLE
, max(1, param(ID::RD_PORTS
)));
1165 param_bits(ID::RD_CLK_POLARITY
, max(1, param(ID::RD_PORTS
)));
1166 param_bits(ID::RD_TRANSPARENT
, max(1, param(ID::RD_PORTS
)));
1167 param_bits(ID::WR_CLK_ENABLE
, max(1, param(ID::WR_PORTS
)));
1168 param_bits(ID::WR_CLK_POLARITY
, max(1, param(ID::WR_PORTS
)));
1169 port(ID::RD_CLK
, param(ID::RD_PORTS
));
1170 port(ID::RD_EN
, param(ID::RD_PORTS
));
1171 port(ID::RD_ADDR
, param(ID::RD_PORTS
) * param(ID::ABITS
));
1172 port(ID::RD_DATA
, param(ID::RD_PORTS
) * param(ID::WIDTH
));
1173 port(ID::WR_CLK
, param(ID::WR_PORTS
));
1174 port(ID::WR_EN
, param(ID::WR_PORTS
) * param(ID::WIDTH
));
1175 port(ID::WR_ADDR
, param(ID::WR_PORTS
) * param(ID::ABITS
));
1176 port(ID::WR_DATA
, param(ID::WR_PORTS
) * param(ID::WIDTH
));
1181 if (cell
->type
== ID($tribuf
)) {
1182 port(ID::A
, param(ID::WIDTH
));
1183 port(ID::Y
, param(ID::WIDTH
));
1189 if (cell
->type
.in(ID($
assert), ID($assume
), ID($live
), ID($fair
), ID($cover
))) {
1196 if (cell
->type
== ID($initstate
)) {
1202 if (cell
->type
.in(ID($anyconst
), ID($anyseq
), ID($allconst
), ID($allseq
))) {
1203 port(ID::Y
, param(ID::WIDTH
));
1208 if (cell
->type
== ID($equiv
)) {
1216 if (cell
->type
.in(ID($specify2
), ID($specify3
))) {
1217 param_bool(ID::FULL
);
1218 param_bool(ID::SRC_DST_PEN
);
1219 param_bool(ID::SRC_DST_POL
);
1220 param(ID::T_RISE_MIN
);
1221 param(ID::T_RISE_TYP
);
1222 param(ID::T_RISE_MAX
);
1223 param(ID::T_FALL_MIN
);
1224 param(ID::T_FALL_TYP
);
1225 param(ID::T_FALL_MAX
);
1227 port(ID::SRC
, param(ID::SRC_WIDTH
));
1228 port(ID::DST
, param(ID::DST_WIDTH
));
1229 if (cell
->type
== ID($specify3
)) {
1230 param_bool(ID::EDGE_EN
);
1231 param_bool(ID::EDGE_POL
);
1232 param_bool(ID::DAT_DST_PEN
);
1233 param_bool(ID::DAT_DST_POL
);
1234 port(ID::DAT
, param(ID::DST_WIDTH
));
1240 if (cell
->type
== ID($specrule
)) {
1242 param_bool(ID::SRC_PEN
);
1243 param_bool(ID::SRC_POL
);
1244 param_bool(ID::DST_PEN
);
1245 param_bool(ID::DST_POL
);
1246 param(ID::T_LIMIT_MIN
);
1247 param(ID::T_LIMIT_TYP
);
1248 param(ID::T_LIMIT_MAX
);
1249 param(ID::T_LIMIT2_MIN
);
1250 param(ID::T_LIMIT2_TYP
);
1251 param(ID::T_LIMIT2_MAX
);
1252 port(ID::SRC_EN
, 1);
1253 port(ID::DST_EN
, 1);
1254 port(ID::SRC
, param(ID::SRC_WIDTH
));
1255 port(ID::DST
, param(ID::DST_WIDTH
));
1260 if (cell
->type
== ID($_BUF_
)) { port(ID::A
,1); port(ID::Y
,1); check_expected(); return; }
1261 if (cell
->type
== ID($_NOT_
)) { port(ID::A
,1); port(ID::Y
,1); check_expected(); return; }
1262 if (cell
->type
== ID($_AND_
)) { port(ID::A
,1); port(ID::B
,1); port(ID::Y
,1); check_expected(); return; }
1263 if (cell
->type
== ID($_NAND_
)) { port(ID::A
,1); port(ID::B
,1); port(ID::Y
,1); check_expected(); return; }
1264 if (cell
->type
== ID($_OR_
)) { port(ID::A
,1); port(ID::B
,1); port(ID::Y
,1); check_expected(); return; }
1265 if (cell
->type
== ID($_NOR_
)) { port(ID::A
,1); port(ID::B
,1); port(ID::Y
,1); check_expected(); return; }
1266 if (cell
->type
== ID($_XOR_
)) { port(ID::A
,1); port(ID::B
,1); port(ID::Y
,1); check_expected(); return; }
1267 if (cell
->type
== ID($_XNOR_
)) { port(ID::A
,1); port(ID::B
,1); port(ID::Y
,1); check_expected(); return; }
1268 if (cell
->type
== ID($_ANDNOT_
)) { port(ID::A
,1); port(ID::B
,1); port(ID::Y
,1); check_expected(); return; }
1269 if (cell
->type
== ID($_ORNOT_
)) { port(ID::A
,1); port(ID::B
,1); port(ID::Y
,1); check_expected(); return; }
1270 if (cell
->type
== ID($_MUX_
)) { port(ID::A
,1); port(ID::B
,1); port(ID::S
,1); port(ID::Y
,1); check_expected(); return; }
1271 if (cell
->type
== ID($_NMUX_
)) { port(ID::A
,1); port(ID::B
,1); port(ID::S
,1); port(ID::Y
,1); check_expected(); return; }
1272 if (cell
->type
== ID($_AOI3_
)) { port(ID::A
,1); port(ID::B
,1); port(ID::C
,1); port(ID::Y
,1); check_expected(); return; }
1273 if (cell
->type
== ID($_OAI3_
)) { port(ID::A
,1); port(ID::B
,1); port(ID::C
,1); port(ID::Y
,1); check_expected(); return; }
1274 if (cell
->type
== ID($_AOI4_
)) { port(ID::A
,1); port(ID::B
,1); port(ID::C
,1); port(ID::D
,1); port(ID::Y
,1); check_expected(); return; }
1275 if (cell
->type
== ID($_OAI4_
)) { port(ID::A
,1); port(ID::B
,1); port(ID::C
,1); port(ID::D
,1); port(ID::Y
,1); check_expected(); return; }
1277 if (cell
->type
== ID($_TBUF_
)) { port(ID::A
,1); port(ID::Y
,1); port(ID::E
,1); check_expected(); return; }
1279 if (cell
->type
== ID($_MUX4_
)) { port(ID::A
,1); port(ID::B
,1); port(ID::C
,1); port(ID::D
,1); port(ID::S
,1); port(ID::T
,1); port(ID::Y
,1); check_expected(); return; }
1280 if (cell
->type
== ID($_MUX8_
)) { port(ID::A
,1); port(ID::B
,1); port(ID::C
,1); port(ID::D
,1); port(ID::E
,1); port(ID::F
,1); port(ID::G
,1); port(ID::H
,1); port(ID::S
,1); port(ID::T
,1); port(ID::U
,1); port(ID::Y
,1); check_expected(); return; }
1281 if (cell
->type
== ID($_MUX16_
)) { port(ID::A
,1); port(ID::B
,1); port(ID::C
,1); port(ID::D
,1); port(ID::E
,1); port(ID::F
,1); port(ID::G
,1); port(ID::H
,1); port(ID::I
,1); port(ID::J
,1); port(ID::K
,1); port(ID::L
,1); port(ID::M
,1); port(ID::N
,1); port(ID::O
,1); port(ID::P
,1); port(ID::S
,1); port(ID::T
,1); port(ID::U
,1); port(ID::V
,1); port(ID::Y
,1); check_expected(); return; }
1283 if (cell
->type
== ID($_SR_NN_
)) { port(ID::S
,1); port(ID::R
,1); port(ID::Q
,1); check_expected(); return; }
1284 if (cell
->type
== ID($_SR_NP_
)) { port(ID::S
,1); port(ID::R
,1); port(ID::Q
,1); check_expected(); return; }
1285 if (cell
->type
== ID($_SR_PN_
)) { port(ID::S
,1); port(ID::R
,1); port(ID::Q
,1); check_expected(); return; }
1286 if (cell
->type
== ID($_SR_PP_
)) { port(ID::S
,1); port(ID::R
,1); port(ID::Q
,1); check_expected(); return; }
1288 if (cell
->type
== ID($_FF_
)) { port(ID::D
,1); port(ID::Q
,1); check_expected(); return; }
1289 if (cell
->type
== ID($_DFF_N_
)) { port(ID::D
,1); port(ID::Q
,1); port(ID::C
,1); check_expected(); return; }
1290 if (cell
->type
== ID($_DFF_P_
)) { port(ID::D
,1); port(ID::Q
,1); port(ID::C
,1); check_expected(); return; }
1292 if (cell
->type
== ID($_DFFE_NN_
)) { port(ID::D
,1); port(ID::Q
,1); port(ID::C
,1); port(ID::E
,1); check_expected(); return; }
1293 if (cell
->type
== ID($_DFFE_NP_
)) { port(ID::D
,1); port(ID::Q
,1); port(ID::C
,1); port(ID::E
,1); check_expected(); return; }
1294 if (cell
->type
== ID($_DFFE_PN_
)) { port(ID::D
,1); port(ID::Q
,1); port(ID::C
,1); port(ID::E
,1); check_expected(); return; }
1295 if (cell
->type
== ID($_DFFE_PP_
)) { port(ID::D
,1); port(ID::Q
,1); port(ID::C
,1); port(ID::E
,1); check_expected(); return; }
1297 if (cell
->type
== ID($_DFF_NN0_
)) { port(ID::D
,1); port(ID::Q
,1); port(ID::C
,1); port(ID::R
,1); check_expected(); return; }
1298 if (cell
->type
== ID($_DFF_NN1_
)) { port(ID::D
,1); port(ID::Q
,1); port(ID::C
,1); port(ID::R
,1); check_expected(); return; }
1299 if (cell
->type
== ID($_DFF_NP0_
)) { port(ID::D
,1); port(ID::Q
,1); port(ID::C
,1); port(ID::R
,1); check_expected(); return; }
1300 if (cell
->type
== ID($_DFF_NP1_
)) { port(ID::D
,1); port(ID::Q
,1); port(ID::C
,1); port(ID::R
,1); check_expected(); return; }
1301 if (cell
->type
== ID($_DFF_PN0_
)) { port(ID::D
,1); port(ID::Q
,1); port(ID::C
,1); port(ID::R
,1); check_expected(); return; }
1302 if (cell
->type
== ID($_DFF_PN1_
)) { port(ID::D
,1); port(ID::Q
,1); port(ID::C
,1); port(ID::R
,1); check_expected(); return; }
1303 if (cell
->type
== ID($_DFF_PP0_
)) { port(ID::D
,1); port(ID::Q
,1); port(ID::C
,1); port(ID::R
,1); check_expected(); return; }
1304 if (cell
->type
== ID($_DFF_PP1_
)) { port(ID::D
,1); port(ID::Q
,1); port(ID::C
,1); port(ID::R
,1); check_expected(); return; }
1306 if (cell
->type
== ID($_DFFSR_NNN_
)) { port(ID::C
,1); port(ID::S
,1); port(ID::R
,1); port(ID::D
,1); port(ID::Q
,1); check_expected(); return; }
1307 if (cell
->type
== ID($_DFFSR_NNP_
)) { port(ID::C
,1); port(ID::S
,1); port(ID::R
,1); port(ID::D
,1); port(ID::Q
,1); check_expected(); return; }
1308 if (cell
->type
== ID($_DFFSR_NPN_
)) { port(ID::C
,1); port(ID::S
,1); port(ID::R
,1); port(ID::D
,1); port(ID::Q
,1); check_expected(); return; }
1309 if (cell
->type
== ID($_DFFSR_NPP_
)) { port(ID::C
,1); port(ID::S
,1); port(ID::R
,1); port(ID::D
,1); port(ID::Q
,1); check_expected(); return; }
1310 if (cell
->type
== ID($_DFFSR_PNN_
)) { port(ID::C
,1); port(ID::S
,1); port(ID::R
,1); port(ID::D
,1); port(ID::Q
,1); check_expected(); return; }
1311 if (cell
->type
== ID($_DFFSR_PNP_
)) { port(ID::C
,1); port(ID::S
,1); port(ID::R
,1); port(ID::D
,1); port(ID::Q
,1); check_expected(); return; }
1312 if (cell
->type
== ID($_DFFSR_PPN_
)) { port(ID::C
,1); port(ID::S
,1); port(ID::R
,1); port(ID::D
,1); port(ID::Q
,1); check_expected(); return; }
1313 if (cell
->type
== ID($_DFFSR_PPP_
)) { port(ID::C
,1); port(ID::S
,1); port(ID::R
,1); port(ID::D
,1); port(ID::Q
,1); check_expected(); return; }
1315 if (cell
->type
== ID($_DLATCH_N_
)) { port(ID::E
,1); port(ID::D
,1); port(ID::Q
,1); check_expected(); return; }
1316 if (cell
->type
== ID($_DLATCH_P_
)) { port(ID::E
,1); port(ID::D
,1); port(ID::Q
,1); check_expected(); return; }
1318 if (cell
->type
== ID($_DLATCHSR_NNN_
)) { port(ID::E
,1); port(ID::S
,1); port(ID::R
,1); port(ID::D
,1); port(ID::Q
,1); check_expected(); return; }
1319 if (cell
->type
== ID($_DLATCHSR_NNP_
)) { port(ID::E
,1); port(ID::S
,1); port(ID::R
,1); port(ID::D
,1); port(ID::Q
,1); check_expected(); return; }
1320 if (cell
->type
== ID($_DLATCHSR_NPN_
)) { port(ID::E
,1); port(ID::S
,1); port(ID::R
,1); port(ID::D
,1); port(ID::Q
,1); check_expected(); return; }
1321 if (cell
->type
== ID($_DLATCHSR_NPP_
)) { port(ID::E
,1); port(ID::S
,1); port(ID::R
,1); port(ID::D
,1); port(ID::Q
,1); check_expected(); return; }
1322 if (cell
->type
== ID($_DLATCHSR_PNN_
)) { port(ID::E
,1); port(ID::S
,1); port(ID::R
,1); port(ID::D
,1); port(ID::Q
,1); check_expected(); return; }
1323 if (cell
->type
== ID($_DLATCHSR_PNP_
)) { port(ID::E
,1); port(ID::S
,1); port(ID::R
,1); port(ID::D
,1); port(ID::Q
,1); check_expected(); return; }
1324 if (cell
->type
== ID($_DLATCHSR_PPN_
)) { port(ID::E
,1); port(ID::S
,1); port(ID::R
,1); port(ID::D
,1); port(ID::Q
,1); check_expected(); return; }
1325 if (cell
->type
== ID($_DLATCHSR_PPP_
)) { port(ID::E
,1); port(ID::S
,1); port(ID::R
,1); port(ID::D
,1); port(ID::Q
,1); check_expected(); return; }
1333 void RTLIL::Module::sort()
1335 wires_
.sort(sort_by_id_str());
1336 cells_
.sort(sort_by_id_str());
1337 avail_parameters
.sort(sort_by_id_str());
1338 memories
.sort(sort_by_id_str());
1339 processes
.sort(sort_by_id_str());
1340 for (auto &it
: cells_
)
1342 for (auto &it
: wires_
)
1343 it
.second
->attributes
.sort(sort_by_id_str());
1344 for (auto &it
: memories
)
1345 it
.second
->attributes
.sort(sort_by_id_str());
1348 void RTLIL::Module::check()
1351 std::vector
<bool> ports_declared
;
1352 for (auto &it
: wires_
) {
1353 log_assert(this == it
.second
->module
);
1354 log_assert(it
.first
== it
.second
->name
);
1355 log_assert(!it
.first
.empty());
1356 log_assert(it
.second
->width
>= 0);
1357 log_assert(it
.second
->port_id
>= 0);
1358 for (auto &it2
: it
.second
->attributes
)
1359 log_assert(!it2
.first
.empty());
1360 if (it
.second
->port_id
) {
1361 log_assert(GetSize(ports
) >= it
.second
->port_id
);
1362 log_assert(ports
.at(it
.second
->port_id
-1) == it
.first
);
1363 log_assert(it
.second
->port_input
|| it
.second
->port_output
);
1364 if (GetSize(ports_declared
) < it
.second
->port_id
)
1365 ports_declared
.resize(it
.second
->port_id
);
1366 log_assert(ports_declared
[it
.second
->port_id
-1] == false);
1367 ports_declared
[it
.second
->port_id
-1] = true;
1369 log_assert(!it
.second
->port_input
&& !it
.second
->port_output
);
1371 for (auto port_declared
: ports_declared
)
1372 log_assert(port_declared
== true);
1373 log_assert(GetSize(ports
) == GetSize(ports_declared
));
1375 for (auto &it
: memories
) {
1376 log_assert(it
.first
== it
.second
->name
);
1377 log_assert(!it
.first
.empty());
1378 log_assert(it
.second
->width
>= 0);
1379 log_assert(it
.second
->size
>= 0);
1380 for (auto &it2
: it
.second
->attributes
)
1381 log_assert(!it2
.first
.empty());
1384 for (auto &it
: cells_
) {
1385 log_assert(this == it
.second
->module
);
1386 log_assert(it
.first
== it
.second
->name
);
1387 log_assert(!it
.first
.empty());
1388 log_assert(!it
.second
->type
.empty());
1389 for (auto &it2
: it
.second
->connections()) {
1390 log_assert(!it2
.first
.empty());
1393 for (auto &it2
: it
.second
->attributes
)
1394 log_assert(!it2
.first
.empty());
1395 for (auto &it2
: it
.second
->parameters
)
1396 log_assert(!it2
.first
.empty());
1397 InternalCellChecker
checker(this, it
.second
);
1401 for (auto &it
: processes
) {
1402 log_assert(it
.first
== it
.second
->name
);
1403 log_assert(!it
.first
.empty());
1404 log_assert(it
.second
->root_case
.compare
.empty());
1405 std::vector
<CaseRule
*> all_cases
= {&it
.second
->root_case
};
1406 for (size_t i
= 0; i
< all_cases
.size(); i
++) {
1407 for (auto &switch_it
: all_cases
[i
]->switches
) {
1408 for (auto &case_it
: switch_it
->cases
) {
1409 for (auto &compare_it
: case_it
->compare
) {
1410 log_assert(switch_it
->signal
.size() == compare_it
.size());
1412 all_cases
.push_back(case_it
);
1416 for (auto &sync_it
: it
.second
->syncs
) {
1417 switch (sync_it
->type
) {
1423 log_assert(!sync_it
->signal
.empty());
1428 log_assert(sync_it
->signal
.empty());
1434 for (auto &it
: connections_
) {
1435 log_assert(it
.first
.size() == it
.second
.size());
1436 log_assert(!it
.first
.has_const());
1441 for (auto &it
: attributes
)
1442 log_assert(!it
.first
.empty());
1446 void RTLIL::Module::optimize()
1450 void RTLIL::Module::cloneInto(RTLIL::Module
*new_mod
) const
1452 log_assert(new_mod
->refcount_wires_
== 0);
1453 log_assert(new_mod
->refcount_cells_
== 0);
1455 new_mod
->avail_parameters
= avail_parameters
;
1457 for (auto &conn
: connections_
)
1458 new_mod
->connect(conn
);
1460 for (auto &attr
: attributes
)
1461 new_mod
->attributes
[attr
.first
] = attr
.second
;
1463 for (auto &it
: wires_
)
1464 new_mod
->addWire(it
.first
, it
.second
);
1466 for (auto &it
: memories
)
1467 new_mod
->memories
[it
.first
] = new RTLIL::Memory(*it
.second
);
1469 for (auto &it
: cells_
)
1470 new_mod
->addCell(it
.first
, it
.second
);
1472 for (auto &it
: processes
)
1473 new_mod
->processes
[it
.first
] = it
.second
->clone();
1475 struct RewriteSigSpecWorker
1478 void operator()(RTLIL::SigSpec
&sig
)
1481 for (auto &c
: sig
.chunks_
)
1483 c
.wire
= mod
->wires_
.at(c
.wire
->name
);
1487 RewriteSigSpecWorker rewriteSigSpecWorker
;
1488 rewriteSigSpecWorker
.mod
= new_mod
;
1489 new_mod
->rewrite_sigspecs(rewriteSigSpecWorker
);
1490 new_mod
->fixup_ports();
1493 RTLIL::Module
*RTLIL::Module::clone() const
1495 RTLIL::Module
*new_mod
= new RTLIL::Module
;
1496 new_mod
->name
= name
;
1501 bool RTLIL::Module::has_memories() const
1503 return !memories
.empty();
1506 bool RTLIL::Module::has_processes() const
1508 return !processes
.empty();
1511 bool RTLIL::Module::has_memories_warn() const
1513 if (!memories
.empty())
1514 log_warning("Ignoring module %s because it contains memories (run 'memory' command first).\n", log_id(this));
1515 return !memories
.empty();
1518 bool RTLIL::Module::has_processes_warn() const
1520 if (!processes
.empty())
1521 log_warning("Ignoring module %s because it contains processes (run 'proc' command first).\n", log_id(this));
1522 return !processes
.empty();
1525 std::vector
<RTLIL::Wire
*> RTLIL::Module::selected_wires() const
1527 std::vector
<RTLIL::Wire
*> result
;
1528 result
.reserve(wires_
.size());
1529 for (auto &it
: wires_
)
1530 if (design
->selected(this, it
.second
))
1531 result
.push_back(it
.second
);
1535 std::vector
<RTLIL::Cell
*> RTLIL::Module::selected_cells() const
1537 std::vector
<RTLIL::Cell
*> result
;
1538 result
.reserve(cells_
.size());
1539 for (auto &it
: cells_
)
1540 if (design
->selected(this, it
.second
))
1541 result
.push_back(it
.second
);
1545 void RTLIL::Module::add(RTLIL::Wire
*wire
)
1547 log_assert(!wire
->name
.empty());
1548 log_assert(count_id(wire
->name
) == 0);
1549 log_assert(refcount_wires_
== 0);
1550 wires_
[wire
->name
] = wire
;
1551 wire
->module
= this;
1554 void RTLIL::Module::add(RTLIL::Cell
*cell
)
1556 log_assert(!cell
->name
.empty());
1557 log_assert(count_id(cell
->name
) == 0);
1558 log_assert(refcount_cells_
== 0);
1559 cells_
[cell
->name
] = cell
;
1560 cell
->module
= this;
1563 void RTLIL::Module::remove(const pool
<RTLIL::Wire
*> &wires
)
1565 log_assert(refcount_wires_
== 0);
1567 struct DeleteWireWorker
1569 RTLIL::Module
*module
;
1570 const pool
<RTLIL::Wire
*> *wires_p
;
1572 void operator()(RTLIL::SigSpec
&sig
) {
1574 for (auto &c
: sig
.chunks_
)
1575 if (c
.wire
!= NULL
&& wires_p
->count(c
.wire
)) {
1576 c
.wire
= module
->addWire(NEW_ID
, c
.width
);
1581 void operator()(RTLIL::SigSpec
&lhs
, RTLIL::SigSpec
&rhs
) {
1582 log_assert(GetSize(lhs
) == GetSize(rhs
));
1585 for (int i
= 0; i
< GetSize(lhs
); i
++) {
1586 RTLIL::SigBit
&lhs_bit
= lhs
.bits_
[i
];
1587 RTLIL::SigBit
&rhs_bit
= rhs
.bits_
[i
];
1588 if ((lhs_bit
.wire
!= nullptr && wires_p
->count(lhs_bit
.wire
)) || (rhs_bit
.wire
!= nullptr && wires_p
->count(rhs_bit
.wire
))) {
1589 lhs_bit
= State::Sx
;
1590 rhs_bit
= State::Sx
;
1596 DeleteWireWorker delete_wire_worker
;
1597 delete_wire_worker
.module
= this;
1598 delete_wire_worker
.wires_p
= &wires
;
1599 rewrite_sigspecs2(delete_wire_worker
);
1601 for (auto &it
: wires
) {
1602 log_assert(wires_
.count(it
->name
) != 0);
1603 wires_
.erase(it
->name
);
1608 void RTLIL::Module::remove(RTLIL::Cell
*cell
)
1610 while (!cell
->connections_
.empty())
1611 cell
->unsetPort(cell
->connections_
.begin()->first
);
1613 log_assert(cells_
.count(cell
->name
) != 0);
1614 log_assert(refcount_cells_
== 0);
1615 cells_
.erase(cell
->name
);
1619 void RTLIL::Module::rename(RTLIL::Wire
*wire
, RTLIL::IdString new_name
)
1621 log_assert(wires_
[wire
->name
] == wire
);
1622 log_assert(refcount_wires_
== 0);
1623 wires_
.erase(wire
->name
);
1624 wire
->name
= new_name
;
1628 void RTLIL::Module::rename(RTLIL::Cell
*cell
, RTLIL::IdString new_name
)
1630 log_assert(cells_
[cell
->name
] == cell
);
1631 log_assert(refcount_wires_
== 0);
1632 cells_
.erase(cell
->name
);
1633 cell
->name
= new_name
;
1637 void RTLIL::Module::rename(RTLIL::IdString old_name
, RTLIL::IdString new_name
)
1639 log_assert(count_id(old_name
) != 0);
1640 if (wires_
.count(old_name
))
1641 rename(wires_
.at(old_name
), new_name
);
1642 else if (cells_
.count(old_name
))
1643 rename(cells_
.at(old_name
), new_name
);
1648 void RTLIL::Module::swap_names(RTLIL::Wire
*w1
, RTLIL::Wire
*w2
)
1650 log_assert(wires_
[w1
->name
] == w1
);
1651 log_assert(wires_
[w2
->name
] == w2
);
1652 log_assert(refcount_wires_
== 0);
1654 wires_
.erase(w1
->name
);
1655 wires_
.erase(w2
->name
);
1657 std::swap(w1
->name
, w2
->name
);
1659 wires_
[w1
->name
] = w1
;
1660 wires_
[w2
->name
] = w2
;
1663 void RTLIL::Module::swap_names(RTLIL::Cell
*c1
, RTLIL::Cell
*c2
)
1665 log_assert(cells_
[c1
->name
] == c1
);
1666 log_assert(cells_
[c2
->name
] == c2
);
1667 log_assert(refcount_cells_
== 0);
1669 cells_
.erase(c1
->name
);
1670 cells_
.erase(c2
->name
);
1672 std::swap(c1
->name
, c2
->name
);
1674 cells_
[c1
->name
] = c1
;
1675 cells_
[c2
->name
] = c2
;
1678 RTLIL::IdString
RTLIL::Module::uniquify(RTLIL::IdString name
)
1681 return uniquify(name
, index
);
1684 RTLIL::IdString
RTLIL::Module::uniquify(RTLIL::IdString name
, int &index
)
1687 if (count_id(name
) == 0)
1693 RTLIL::IdString new_name
= stringf("%s_%d", name
.c_str(), index
);
1694 if (count_id(new_name
) == 0)
1700 static bool fixup_ports_compare(const RTLIL::Wire
*a
, const RTLIL::Wire
*b
)
1702 if (a
->port_id
&& !b
->port_id
)
1704 if (!a
->port_id
&& b
->port_id
)
1707 if (a
->port_id
== b
->port_id
)
1708 return a
->name
< b
->name
;
1709 return a
->port_id
< b
->port_id
;
1712 void RTLIL::Module::connect(const RTLIL::SigSig
&conn
)
1714 for (auto mon
: monitors
)
1715 mon
->notify_connect(this, conn
);
1718 for (auto mon
: design
->monitors
)
1719 mon
->notify_connect(this, conn
);
1721 // ignore all attempts to assign constants to other constants
1722 if (conn
.first
.has_const()) {
1723 RTLIL::SigSig new_conn
;
1724 for (int i
= 0; i
< GetSize(conn
.first
); i
++)
1725 if (conn
.first
[i
].wire
) {
1726 new_conn
.first
.append(conn
.first
[i
]);
1727 new_conn
.second
.append(conn
.second
[i
]);
1729 if (GetSize(new_conn
.first
))
1735 log("#X# Connect (SigSig) in %s: %s = %s (%d bits)\n", log_id(this), log_signal(conn
.first
), log_signal(conn
.second
), GetSize(conn
.first
));
1736 log_backtrace("-X- ", yosys_xtrace
-1);
1739 log_assert(GetSize(conn
.first
) == GetSize(conn
.second
));
1740 connections_
.push_back(conn
);
1743 void RTLIL::Module::connect(const RTLIL::SigSpec
&lhs
, const RTLIL::SigSpec
&rhs
)
1745 connect(RTLIL::SigSig(lhs
, rhs
));
1748 void RTLIL::Module::new_connections(const std::vector
<RTLIL::SigSig
> &new_conn
)
1750 for (auto mon
: monitors
)
1751 mon
->notify_connect(this, new_conn
);
1754 for (auto mon
: design
->monitors
)
1755 mon
->notify_connect(this, new_conn
);
1758 log("#X# New connections vector in %s:\n", log_id(this));
1759 for (auto &conn
: new_conn
)
1760 log("#X# %s = %s (%d bits)\n", log_signal(conn
.first
), log_signal(conn
.second
), GetSize(conn
.first
));
1761 log_backtrace("-X- ", yosys_xtrace
-1);
1764 connections_
= new_conn
;
1767 const std::vector
<RTLIL::SigSig
> &RTLIL::Module::connections() const
1769 return connections_
;
1772 void RTLIL::Module::fixup_ports()
1774 std::vector
<RTLIL::Wire
*> all_ports
;
1776 for (auto &w
: wires_
)
1777 if (w
.second
->port_input
|| w
.second
->port_output
)
1778 all_ports
.push_back(w
.second
);
1780 w
.second
->port_id
= 0;
1782 std::sort(all_ports
.begin(), all_ports
.end(), fixup_ports_compare
);
1785 for (size_t i
= 0; i
< all_ports
.size(); i
++) {
1786 ports
.push_back(all_ports
[i
]->name
);
1787 all_ports
[i
]->port_id
= i
+1;
1791 RTLIL::Wire
*RTLIL::Module::addWire(RTLIL::IdString name
, int width
)
1793 RTLIL::Wire
*wire
= new RTLIL::Wire
;
1795 wire
->width
= width
;
1800 RTLIL::Wire
*RTLIL::Module::addWire(RTLIL::IdString name
, const RTLIL::Wire
*other
)
1802 RTLIL::Wire
*wire
= addWire(name
);
1803 wire
->width
= other
->width
;
1804 wire
->start_offset
= other
->start_offset
;
1805 wire
->port_id
= other
->port_id
;
1806 wire
->port_input
= other
->port_input
;
1807 wire
->port_output
= other
->port_output
;
1808 wire
->upto
= other
->upto
;
1809 wire
->attributes
= other
->attributes
;
1813 RTLIL::Cell
*RTLIL::Module::addCell(RTLIL::IdString name
, RTLIL::IdString type
)
1815 RTLIL::Cell
*cell
= new RTLIL::Cell
;
1822 RTLIL::Cell
*RTLIL::Module::addCell(RTLIL::IdString name
, const RTLIL::Cell
*other
)
1824 RTLIL::Cell
*cell
= addCell(name
, other
->type
);
1825 cell
->connections_
= other
->connections_
;
1826 cell
->parameters
= other
->parameters
;
1827 cell
->attributes
= other
->attributes
;
1831 #define DEF_METHOD(_func, _y_size, _type) \
1832 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed, const std::string &src) { \
1833 RTLIL::Cell *cell = addCell(name, _type); \
1834 cell->parameters[ID::A_SIGNED] = is_signed; \
1835 cell->parameters[ID::A_WIDTH] = sig_a.size(); \
1836 cell->parameters[ID::Y_WIDTH] = sig_y.size(); \
1837 cell->setPort(ID::A, sig_a); \
1838 cell->setPort(ID::Y, sig_y); \
1839 cell->set_src_attribute(src); \
1842 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed, const std::string &src) { \
1843 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
1844 add ## _func(name, sig_a, sig_y, is_signed, src); \
1847 DEF_METHOD(Not
, sig_a
.size(), ID($
not))
1848 DEF_METHOD(Pos
, sig_a
.size(), ID($pos
))
1849 DEF_METHOD(Neg
, sig_a
.size(), ID($neg
))
1850 DEF_METHOD(ReduceAnd
, 1, ID($reduce_and
))
1851 DEF_METHOD(ReduceOr
, 1, ID($reduce_or
))
1852 DEF_METHOD(ReduceXor
, 1, ID($reduce_xor
))
1853 DEF_METHOD(ReduceXnor
, 1, ID($reduce_xnor
))
1854 DEF_METHOD(ReduceBool
, 1, ID($reduce_bool
))
1855 DEF_METHOD(LogicNot
, 1, ID($logic_not
))
1858 #define DEF_METHOD(_func, _y_size, _type) \
1859 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed, const std::string &src) { \
1860 RTLIL::Cell *cell = addCell(name, _type); \
1861 cell->parameters[ID::A_SIGNED] = is_signed; \
1862 cell->parameters[ID::B_SIGNED] = is_signed; \
1863 cell->parameters[ID::A_WIDTH] = sig_a.size(); \
1864 cell->parameters[ID::B_WIDTH] = sig_b.size(); \
1865 cell->parameters[ID::Y_WIDTH] = sig_y.size(); \
1866 cell->setPort(ID::A, sig_a); \
1867 cell->setPort(ID::B, sig_b); \
1868 cell->setPort(ID::Y, sig_y); \
1869 cell->set_src_attribute(src); \
1872 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed, const std::string &src) { \
1873 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
1874 add ## _func(name, sig_a, sig_b, sig_y, is_signed, src); \
1877 DEF_METHOD(And
, max(sig_a
.size(), sig_b
.size()), ID($
and))
1878 DEF_METHOD(Or
, max(sig_a
.size(), sig_b
.size()), ID($
or))
1879 DEF_METHOD(Xor
, max(sig_a
.size(), sig_b
.size()), ID($
xor))
1880 DEF_METHOD(Xnor
, max(sig_a
.size(), sig_b
.size()), ID($xnor
))
1881 DEF_METHOD(Shift
, sig_a
.size(), ID($shift
))
1882 DEF_METHOD(Shiftx
, sig_a
.size(), ID($shiftx
))
1883 DEF_METHOD(Lt
, 1, ID($lt
))
1884 DEF_METHOD(Le
, 1, ID($le
))
1885 DEF_METHOD(Eq
, 1, ID($eq
))
1886 DEF_METHOD(Ne
, 1, ID($ne
))
1887 DEF_METHOD(Eqx
, 1, ID($eqx
))
1888 DEF_METHOD(Nex
, 1, ID($nex
))
1889 DEF_METHOD(Ge
, 1, ID($ge
))
1890 DEF_METHOD(Gt
, 1, ID($gt
))
1891 DEF_METHOD(Add
, max(sig_a
.size(), sig_b
.size()), ID($add
))
1892 DEF_METHOD(Sub
, max(sig_a
.size(), sig_b
.size()), ID($sub
))
1893 DEF_METHOD(Mul
, max(sig_a
.size(), sig_b
.size()), ID($mul
))
1894 DEF_METHOD(Div
, max(sig_a
.size(), sig_b
.size()), ID($div
))
1895 DEF_METHOD(Mod
, max(sig_a
.size(), sig_b
.size()), ID($mod
))
1896 DEF_METHOD(LogicAnd
, 1, ID($logic_and
))
1897 DEF_METHOD(LogicOr
, 1, ID($logic_or
))
1900 #define DEF_METHOD(_func, _y_size, _type) \
1901 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed, const std::string &src) { \
1902 RTLIL::Cell *cell = addCell(name, _type); \
1903 cell->parameters[ID::A_SIGNED] = is_signed; \
1904 cell->parameters[ID::B_SIGNED] = false; \
1905 cell->parameters[ID::A_WIDTH] = sig_a.size(); \
1906 cell->parameters[ID::B_WIDTH] = sig_b.size(); \
1907 cell->parameters[ID::Y_WIDTH] = sig_y.size(); \
1908 cell->setPort(ID::A, sig_a); \
1909 cell->setPort(ID::B, sig_b); \
1910 cell->setPort(ID::Y, sig_y); \
1911 cell->set_src_attribute(src); \
1914 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed, const std::string &src) { \
1915 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
1916 add ## _func(name, sig_a, sig_b, sig_y, is_signed, src); \
1919 DEF_METHOD(Shl
, sig_a
.size(), ID($shl
))
1920 DEF_METHOD(Shr
, sig_a
.size(), ID($shr
))
1921 DEF_METHOD(Sshl
, sig_a
.size(), ID($sshl
))
1922 DEF_METHOD(Sshr
, sig_a
.size(), ID($sshr
))
1925 #define DEF_METHOD(_func, _type, _pmux) \
1926 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, const std::string &src) { \
1927 RTLIL::Cell *cell = addCell(name, _type); \
1928 cell->parameters[ID::WIDTH] = sig_a.size(); \
1929 if (_pmux) cell->parameters[ID::S_WIDTH] = sig_s.size(); \
1930 cell->setPort(ID::A, sig_a); \
1931 cell->setPort(ID::B, sig_b); \
1932 cell->setPort(ID::S, sig_s); \
1933 cell->setPort(ID::Y, sig_y); \
1934 cell->set_src_attribute(src); \
1937 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const std::string &src) { \
1938 RTLIL::SigSpec sig_y = addWire(NEW_ID, sig_a.size()); \
1939 add ## _func(name, sig_a, sig_b, sig_s, sig_y, src); \
1942 DEF_METHOD(Mux
, ID($mux
), 0)
1943 DEF_METHOD(Pmux
, ID($pmux
), 1)
1946 #define DEF_METHOD_2(_func, _type, _P1, _P2) \
1947 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const std::string &src) { \
1948 RTLIL::Cell *cell = addCell(name, _type); \
1949 cell->setPort("\\" #_P1, sig1); \
1950 cell->setPort("\\" #_P2, sig2); \
1951 cell->set_src_attribute(src); \
1954 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const std::string &src) { \
1955 RTLIL::SigBit sig2 = addWire(NEW_ID); \
1956 add ## _func(name, sig1, sig2, src); \
1959 #define DEF_METHOD_3(_func, _type, _P1, _P2, _P3) \
1960 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const RTLIL::SigBit &sig3, const std::string &src) { \
1961 RTLIL::Cell *cell = addCell(name, _type); \
1962 cell->setPort("\\" #_P1, sig1); \
1963 cell->setPort("\\" #_P2, sig2); \
1964 cell->setPort("\\" #_P3, sig3); \
1965 cell->set_src_attribute(src); \
1968 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const std::string &src) { \
1969 RTLIL::SigBit sig3 = addWire(NEW_ID); \
1970 add ## _func(name, sig1, sig2, sig3, src); \
1973 #define DEF_METHOD_4(_func, _type, _P1, _P2, _P3, _P4) \
1974 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const RTLIL::SigBit &sig3, const RTLIL::SigBit &sig4, const std::string &src) { \
1975 RTLIL::Cell *cell = addCell(name, _type); \
1976 cell->setPort("\\" #_P1, sig1); \
1977 cell->setPort("\\" #_P2, sig2); \
1978 cell->setPort("\\" #_P3, sig3); \
1979 cell->setPort("\\" #_P4, sig4); \
1980 cell->set_src_attribute(src); \
1983 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const RTLIL::SigBit &sig3, const std::string &src) { \
1984 RTLIL::SigBit sig4 = addWire(NEW_ID); \
1985 add ## _func(name, sig1, sig2, sig3, sig4, src); \
1988 #define DEF_METHOD_5(_func, _type, _P1, _P2, _P3, _P4, _P5) \
1989 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const RTLIL::SigBit &sig3, const RTLIL::SigBit &sig4, const RTLIL::SigBit &sig5, const std::string &src) { \
1990 RTLIL::Cell *cell = addCell(name, _type); \
1991 cell->setPort("\\" #_P1, sig1); \
1992 cell->setPort("\\" #_P2, sig2); \
1993 cell->setPort("\\" #_P3, sig3); \
1994 cell->setPort("\\" #_P4, sig4); \
1995 cell->setPort("\\" #_P5, sig5); \
1996 cell->set_src_attribute(src); \
1999 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const RTLIL::SigBit &sig3, const RTLIL::SigBit &sig4, const std::string &src) { \
2000 RTLIL::SigBit sig5 = addWire(NEW_ID); \
2001 add ## _func(name, sig1, sig2, sig3, sig4, sig5, src); \
2004 DEF_METHOD_2(BufGate
, ID($_BUF_
), A
, Y
)
2005 DEF_METHOD_2(NotGate
, ID($_NOT_
), A
, Y
)
2006 DEF_METHOD_3(AndGate
, ID($_AND_
), A
, B
, Y
)
2007 DEF_METHOD_3(NandGate
, ID($_NAND_
), A
, B
, Y
)
2008 DEF_METHOD_3(OrGate
, ID($_OR_
), A
, B
, Y
)
2009 DEF_METHOD_3(NorGate
, ID($_NOR_
), A
, B
, Y
)
2010 DEF_METHOD_3(XorGate
, ID($_XOR_
), A
, B
, Y
)
2011 DEF_METHOD_3(XnorGate
, ID($_XNOR_
), A
, B
, Y
)
2012 DEF_METHOD_3(AndnotGate
, ID($_ANDNOT_
), A
, B
, Y
)
2013 DEF_METHOD_3(OrnotGate
, ID($_ORNOT_
), A
, B
, Y
)
2014 DEF_METHOD_4(MuxGate
, ID($_MUX_
), A
, B
, S
, Y
)
2015 DEF_METHOD_4(NmuxGate
, ID($_NMUX_
), A
, B
, S
, Y
)
2016 DEF_METHOD_4(Aoi3Gate
, ID($_AOI3_
), A
, B
, C
, Y
)
2017 DEF_METHOD_4(Oai3Gate
, ID($_OAI3_
), A
, B
, C
, Y
)
2018 DEF_METHOD_5(Aoi4Gate
, ID($_AOI4_
), A
, B
, C
, D
, Y
)
2019 DEF_METHOD_5(Oai4Gate
, ID($_OAI4_
), A
, B
, C
, D
, Y
)
2025 RTLIL::Cell
* RTLIL::Module::addPow(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_a
, const RTLIL::SigSpec
&sig_b
, const RTLIL::SigSpec
&sig_y
, bool a_signed
, bool b_signed
, const std::string
&src
)
2027 RTLIL::Cell
*cell
= addCell(name
, ID($pow
));
2028 cell
->parameters
[ID::A_SIGNED
] = a_signed
;
2029 cell
->parameters
[ID::B_SIGNED
] = b_signed
;
2030 cell
->parameters
[ID::A_WIDTH
] = sig_a
.size();
2031 cell
->parameters
[ID::B_WIDTH
] = sig_b
.size();
2032 cell
->parameters
[ID::Y_WIDTH
] = sig_y
.size();
2033 cell
->setPort(ID::A
, sig_a
);
2034 cell
->setPort(ID::B
, sig_b
);
2035 cell
->setPort(ID::Y
, sig_y
);
2036 cell
->set_src_attribute(src
);
2040 RTLIL::Cell
* RTLIL::Module::addSlice(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_a
, const RTLIL::SigSpec
&sig_y
, RTLIL::Const offset
, const std::string
&src
)
2042 RTLIL::Cell
*cell
= addCell(name
, ID($slice
));
2043 cell
->parameters
[ID::A_WIDTH
] = sig_a
.size();
2044 cell
->parameters
[ID::Y_WIDTH
] = sig_y
.size();
2045 cell
->parameters
[ID::OFFSET
] = offset
;
2046 cell
->setPort(ID::A
, sig_a
);
2047 cell
->setPort(ID::Y
, sig_y
);
2048 cell
->set_src_attribute(src
);
2052 RTLIL::Cell
* RTLIL::Module::addConcat(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_a
, const RTLIL::SigSpec
&sig_b
, const RTLIL::SigSpec
&sig_y
, const std::string
&src
)
2054 RTLIL::Cell
*cell
= addCell(name
, ID($concat
));
2055 cell
->parameters
[ID::A_WIDTH
] = sig_a
.size();
2056 cell
->parameters
[ID::B_WIDTH
] = sig_b
.size();
2057 cell
->setPort(ID::A
, sig_a
);
2058 cell
->setPort(ID::B
, sig_b
);
2059 cell
->setPort(ID::Y
, sig_y
);
2060 cell
->set_src_attribute(src
);
2064 RTLIL::Cell
* RTLIL::Module::addLut(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_a
, const RTLIL::SigSpec
&sig_y
, RTLIL::Const lut
, const std::string
&src
)
2066 RTLIL::Cell
*cell
= addCell(name
, ID($lut
));
2067 cell
->parameters
[ID::LUT
] = lut
;
2068 cell
->parameters
[ID::WIDTH
] = sig_a
.size();
2069 cell
->setPort(ID::A
, sig_a
);
2070 cell
->setPort(ID::Y
, sig_y
);
2071 cell
->set_src_attribute(src
);
2075 RTLIL::Cell
* RTLIL::Module::addTribuf(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_a
, const RTLIL::SigSpec
&sig_en
, const RTLIL::SigSpec
&sig_y
, const std::string
&src
)
2077 RTLIL::Cell
*cell
= addCell(name
, ID($tribuf
));
2078 cell
->parameters
[ID::WIDTH
] = sig_a
.size();
2079 cell
->setPort(ID::A
, sig_a
);
2080 cell
->setPort(ID::EN
, sig_en
);
2081 cell
->setPort(ID::Y
, sig_y
);
2082 cell
->set_src_attribute(src
);
2086 RTLIL::Cell
* RTLIL::Module::addAssert(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_a
, const RTLIL::SigSpec
&sig_en
, const std::string
&src
)
2088 RTLIL::Cell
*cell
= addCell(name
, ID($
assert));
2089 cell
->setPort(ID::A
, sig_a
);
2090 cell
->setPort(ID::EN
, sig_en
);
2091 cell
->set_src_attribute(src
);
2095 RTLIL::Cell
* RTLIL::Module::addAssume(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_a
, const RTLIL::SigSpec
&sig_en
, const std::string
&src
)
2097 RTLIL::Cell
*cell
= addCell(name
, ID($assume
));
2098 cell
->setPort(ID::A
, sig_a
);
2099 cell
->setPort(ID::EN
, sig_en
);
2100 cell
->set_src_attribute(src
);
2104 RTLIL::Cell
* RTLIL::Module::addLive(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_a
, const RTLIL::SigSpec
&sig_en
, const std::string
&src
)
2106 RTLIL::Cell
*cell
= addCell(name
, ID($live
));
2107 cell
->setPort(ID::A
, sig_a
);
2108 cell
->setPort(ID::EN
, sig_en
);
2109 cell
->set_src_attribute(src
);
2113 RTLIL::Cell
* RTLIL::Module::addFair(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_a
, const RTLIL::SigSpec
&sig_en
, const std::string
&src
)
2115 RTLIL::Cell
*cell
= addCell(name
, ID($fair
));
2116 cell
->setPort(ID::A
, sig_a
);
2117 cell
->setPort(ID::EN
, sig_en
);
2118 cell
->set_src_attribute(src
);
2122 RTLIL::Cell
* RTLIL::Module::addCover(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_a
, const RTLIL::SigSpec
&sig_en
, const std::string
&src
)
2124 RTLIL::Cell
*cell
= addCell(name
, ID($cover
));
2125 cell
->setPort(ID::A
, sig_a
);
2126 cell
->setPort(ID::EN
, sig_en
);
2127 cell
->set_src_attribute(src
);
2131 RTLIL::Cell
* RTLIL::Module::addEquiv(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_a
, const RTLIL::SigSpec
&sig_b
, const RTLIL::SigSpec
&sig_y
, const std::string
&src
)
2133 RTLIL::Cell
*cell
= addCell(name
, ID($equiv
));
2134 cell
->setPort(ID::A
, sig_a
);
2135 cell
->setPort(ID::B
, sig_b
);
2136 cell
->setPort(ID::Y
, sig_y
);
2137 cell
->set_src_attribute(src
);
2141 RTLIL::Cell
* RTLIL::Module::addSr(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_set
, const RTLIL::SigSpec
&sig_clr
, const RTLIL::SigSpec
&sig_q
, bool set_polarity
, bool clr_polarity
, const std::string
&src
)
2143 RTLIL::Cell
*cell
= addCell(name
, ID($sr
));
2144 cell
->parameters
[ID::SET_POLARITY
] = set_polarity
;
2145 cell
->parameters
[ID::CLR_POLARITY
] = clr_polarity
;
2146 cell
->parameters
[ID::WIDTH
] = sig_q
.size();
2147 cell
->setPort(ID::SET
, sig_set
);
2148 cell
->setPort(ID::CLR
, sig_clr
);
2149 cell
->setPort(ID::Q
, sig_q
);
2150 cell
->set_src_attribute(src
);
2154 RTLIL::Cell
* RTLIL::Module::addFf(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_d
, const RTLIL::SigSpec
&sig_q
, const std::string
&src
)
2156 RTLIL::Cell
*cell
= addCell(name
, ID($ff
));
2157 cell
->parameters
[ID::WIDTH
] = sig_q
.size();
2158 cell
->setPort(ID::D
, sig_d
);
2159 cell
->setPort(ID::Q
, sig_q
);
2160 cell
->set_src_attribute(src
);
2164 RTLIL::Cell
* RTLIL::Module::addDff(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_clk
, const RTLIL::SigSpec
&sig_d
, const RTLIL::SigSpec
&sig_q
, bool clk_polarity
, const std::string
&src
)
2166 RTLIL::Cell
*cell
= addCell(name
, ID($dff
));
2167 cell
->parameters
[ID::CLK_POLARITY
] = clk_polarity
;
2168 cell
->parameters
[ID::WIDTH
] = sig_q
.size();
2169 cell
->setPort(ID::CLK
, sig_clk
);
2170 cell
->setPort(ID::D
, sig_d
);
2171 cell
->setPort(ID::Q
, sig_q
);
2172 cell
->set_src_attribute(src
);
2176 RTLIL::Cell
* RTLIL::Module::addDffe(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_clk
, const RTLIL::SigSpec
&sig_en
, const RTLIL::SigSpec
&sig_d
, const RTLIL::SigSpec
&sig_q
, bool clk_polarity
, bool en_polarity
, const std::string
&src
)
2178 RTLIL::Cell
*cell
= addCell(name
, ID($dffe
));
2179 cell
->parameters
[ID::CLK_POLARITY
] = clk_polarity
;
2180 cell
->parameters
[ID::EN_POLARITY
] = en_polarity
;
2181 cell
->parameters
[ID::WIDTH
] = sig_q
.size();
2182 cell
->setPort(ID::CLK
, sig_clk
);
2183 cell
->setPort(ID::EN
, sig_en
);
2184 cell
->setPort(ID::D
, sig_d
);
2185 cell
->setPort(ID::Q
, sig_q
);
2186 cell
->set_src_attribute(src
);
2190 RTLIL::Cell
* RTLIL::Module::addDffsr(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_clk
, const RTLIL::SigSpec
&sig_set
, const RTLIL::SigSpec
&sig_clr
,
2191 RTLIL::SigSpec sig_d
, const RTLIL::SigSpec
&sig_q
, bool clk_polarity
, bool set_polarity
, bool clr_polarity
, const std::string
&src
)
2193 RTLIL::Cell
*cell
= addCell(name
, ID($dffsr
));
2194 cell
->parameters
[ID::CLK_POLARITY
] = clk_polarity
;
2195 cell
->parameters
[ID::SET_POLARITY
] = set_polarity
;
2196 cell
->parameters
[ID::CLR_POLARITY
] = clr_polarity
;
2197 cell
->parameters
[ID::WIDTH
] = sig_q
.size();
2198 cell
->setPort(ID::CLK
, sig_clk
);
2199 cell
->setPort(ID::SET
, sig_set
);
2200 cell
->setPort(ID::CLR
, sig_clr
);
2201 cell
->setPort(ID::D
, sig_d
);
2202 cell
->setPort(ID::Q
, sig_q
);
2203 cell
->set_src_attribute(src
);
2207 RTLIL::Cell
* RTLIL::Module::addAdff(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_clk
, const RTLIL::SigSpec
&sig_arst
, const RTLIL::SigSpec
&sig_d
, const RTLIL::SigSpec
&sig_q
,
2208 RTLIL::Const arst_value
, bool clk_polarity
, bool arst_polarity
, const std::string
&src
)
2210 RTLIL::Cell
*cell
= addCell(name
, ID($adff
));
2211 cell
->parameters
[ID::CLK_POLARITY
] = clk_polarity
;
2212 cell
->parameters
[ID::ARST_POLARITY
] = arst_polarity
;
2213 cell
->parameters
[ID::ARST_VALUE
] = arst_value
;
2214 cell
->parameters
[ID::WIDTH
] = sig_q
.size();
2215 cell
->setPort(ID::CLK
, sig_clk
);
2216 cell
->setPort(ID::ARST
, sig_arst
);
2217 cell
->setPort(ID::D
, sig_d
);
2218 cell
->setPort(ID::Q
, sig_q
);
2219 cell
->set_src_attribute(src
);
2223 RTLIL::Cell
* RTLIL::Module::addDlatch(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_en
, const RTLIL::SigSpec
&sig_d
, const RTLIL::SigSpec
&sig_q
, bool en_polarity
, const std::string
&src
)
2225 RTLIL::Cell
*cell
= addCell(name
, ID($dlatch
));
2226 cell
->parameters
[ID::EN_POLARITY
] = en_polarity
;
2227 cell
->parameters
[ID::WIDTH
] = sig_q
.size();
2228 cell
->setPort(ID::EN
, sig_en
);
2229 cell
->setPort(ID::D
, sig_d
);
2230 cell
->setPort(ID::Q
, sig_q
);
2231 cell
->set_src_attribute(src
);
2235 RTLIL::Cell
* RTLIL::Module::addDlatchsr(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_en
, const RTLIL::SigSpec
&sig_set
, const RTLIL::SigSpec
&sig_clr
,
2236 RTLIL::SigSpec sig_d
, const RTLIL::SigSpec
&sig_q
, bool en_polarity
, bool set_polarity
, bool clr_polarity
, const std::string
&src
)
2238 RTLIL::Cell
*cell
= addCell(name
, ID($dlatchsr
));
2239 cell
->parameters
[ID::EN_POLARITY
] = en_polarity
;
2240 cell
->parameters
[ID::SET_POLARITY
] = set_polarity
;
2241 cell
->parameters
[ID::CLR_POLARITY
] = clr_polarity
;
2242 cell
->parameters
[ID::WIDTH
] = sig_q
.size();
2243 cell
->setPort(ID::EN
, sig_en
);
2244 cell
->setPort(ID::SET
, sig_set
);
2245 cell
->setPort(ID::CLR
, sig_clr
);
2246 cell
->setPort(ID::D
, sig_d
);
2247 cell
->setPort(ID::Q
, sig_q
);
2248 cell
->set_src_attribute(src
);
2252 RTLIL::Cell
* RTLIL::Module::addFfGate(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_d
, const RTLIL::SigSpec
&sig_q
, const std::string
&src
)
2254 RTLIL::Cell
*cell
= addCell(name
, ID($_FF_
));
2255 cell
->setPort(ID::D
, sig_d
);
2256 cell
->setPort(ID::Q
, sig_q
);
2257 cell
->set_src_attribute(src
);
2261 RTLIL::Cell
* RTLIL::Module::addDffGate(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_clk
, const RTLIL::SigSpec
&sig_d
, const RTLIL::SigSpec
&sig_q
, bool clk_polarity
, const std::string
&src
)
2263 RTLIL::Cell
*cell
= addCell(name
, stringf("$_DFF_%c_", clk_polarity
? 'P' : 'N'));
2264 cell
->setPort(ID::C
, sig_clk
);
2265 cell
->setPort(ID::D
, sig_d
);
2266 cell
->setPort(ID::Q
, sig_q
);
2267 cell
->set_src_attribute(src
);
2271 RTLIL::Cell
* RTLIL::Module::addDffeGate(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_clk
, const RTLIL::SigSpec
&sig_en
, const RTLIL::SigSpec
&sig_d
, const RTLIL::SigSpec
&sig_q
, bool clk_polarity
, bool en_polarity
, const std::string
&src
)
2273 RTLIL::Cell
*cell
= addCell(name
, stringf("$_DFFE_%c%c_", clk_polarity
? 'P' : 'N', en_polarity
? 'P' : 'N'));
2274 cell
->setPort(ID::C
, sig_clk
);
2275 cell
->setPort(ID::E
, sig_en
);
2276 cell
->setPort(ID::D
, sig_d
);
2277 cell
->setPort(ID::Q
, sig_q
);
2278 cell
->set_src_attribute(src
);
2282 RTLIL::Cell
* RTLIL::Module::addDffsrGate(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_clk
, const RTLIL::SigSpec
&sig_set
, const RTLIL::SigSpec
&sig_clr
,
2283 RTLIL::SigSpec sig_d
, const RTLIL::SigSpec
&sig_q
, bool clk_polarity
, bool set_polarity
, bool clr_polarity
, const std::string
&src
)
2285 RTLIL::Cell
*cell
= addCell(name
, stringf("$_DFFSR_%c%c%c_", clk_polarity
? 'P' : 'N', set_polarity
? 'P' : 'N', clr_polarity
? 'P' : 'N'));
2286 cell
->setPort(ID::C
, sig_clk
);
2287 cell
->setPort(ID::S
, sig_set
);
2288 cell
->setPort(ID::R
, sig_clr
);
2289 cell
->setPort(ID::D
, sig_d
);
2290 cell
->setPort(ID::Q
, sig_q
);
2291 cell
->set_src_attribute(src
);
2295 RTLIL::Cell
* RTLIL::Module::addAdffGate(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_clk
, const RTLIL::SigSpec
&sig_arst
, const RTLIL::SigSpec
&sig_d
, const RTLIL::SigSpec
&sig_q
,
2296 bool arst_value
, bool clk_polarity
, bool arst_polarity
, const std::string
&src
)
2298 RTLIL::Cell
*cell
= addCell(name
, stringf("$_DFF_%c%c%c_", clk_polarity
? 'P' : 'N', arst_polarity
? 'P' : 'N', arst_value
? '1' : '0'));
2299 cell
->setPort(ID::C
, sig_clk
);
2300 cell
->setPort(ID::R
, sig_arst
);
2301 cell
->setPort(ID::D
, sig_d
);
2302 cell
->setPort(ID::Q
, sig_q
);
2303 cell
->set_src_attribute(src
);
2307 RTLIL::Cell
* RTLIL::Module::addDlatchGate(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_en
, const RTLIL::SigSpec
&sig_d
, const RTLIL::SigSpec
&sig_q
, bool en_polarity
, const std::string
&src
)
2309 RTLIL::Cell
*cell
= addCell(name
, stringf("$_DLATCH_%c_", en_polarity
? 'P' : 'N'));
2310 cell
->setPort(ID::E
, sig_en
);
2311 cell
->setPort(ID::D
, sig_d
);
2312 cell
->setPort(ID::Q
, sig_q
);
2313 cell
->set_src_attribute(src
);
2317 RTLIL::Cell
* RTLIL::Module::addDlatchsrGate(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_en
, const RTLIL::SigSpec
&sig_set
, const RTLIL::SigSpec
&sig_clr
,
2318 RTLIL::SigSpec sig_d
, const RTLIL::SigSpec
&sig_q
, bool en_polarity
, bool set_polarity
, bool clr_polarity
, const std::string
&src
)
2320 RTLIL::Cell
*cell
= addCell(name
, stringf("$_DLATCHSR_%c%c%c_", en_polarity
? 'P' : 'N', set_polarity
? 'P' : 'N', clr_polarity
? 'P' : 'N'));
2321 cell
->setPort(ID::E
, sig_en
);
2322 cell
->setPort(ID::S
, sig_set
);
2323 cell
->setPort(ID::R
, sig_clr
);
2324 cell
->setPort(ID::D
, sig_d
);
2325 cell
->setPort(ID::Q
, sig_q
);
2326 cell
->set_src_attribute(src
);
2330 RTLIL::SigSpec
RTLIL::Module::Anyconst(RTLIL::IdString name
, int width
, const std::string
&src
)
2332 RTLIL::SigSpec sig
= addWire(NEW_ID
, width
);
2333 Cell
*cell
= addCell(name
, ID($anyconst
));
2334 cell
->setParam(ID::WIDTH
, width
);
2335 cell
->setPort(ID::Y
, sig
);
2336 cell
->set_src_attribute(src
);
2340 RTLIL::SigSpec
RTLIL::Module::Anyseq(RTLIL::IdString name
, int width
, const std::string
&src
)
2342 RTLIL::SigSpec sig
= addWire(NEW_ID
, width
);
2343 Cell
*cell
= addCell(name
, ID($anyseq
));
2344 cell
->setParam(ID::WIDTH
, width
);
2345 cell
->setPort(ID::Y
, sig
);
2346 cell
->set_src_attribute(src
);
2350 RTLIL::SigSpec
RTLIL::Module::Allconst(RTLIL::IdString name
, int width
, const std::string
&src
)
2352 RTLIL::SigSpec sig
= addWire(NEW_ID
, width
);
2353 Cell
*cell
= addCell(name
, ID($allconst
));
2354 cell
->setParam(ID::WIDTH
, width
);
2355 cell
->setPort(ID::Y
, sig
);
2356 cell
->set_src_attribute(src
);
2360 RTLIL::SigSpec
RTLIL::Module::Allseq(RTLIL::IdString name
, int width
, const std::string
&src
)
2362 RTLIL::SigSpec sig
= addWire(NEW_ID
, width
);
2363 Cell
*cell
= addCell(name
, ID($allseq
));
2364 cell
->setParam(ID::WIDTH
, width
);
2365 cell
->setPort(ID::Y
, sig
);
2366 cell
->set_src_attribute(src
);
2370 RTLIL::SigSpec
RTLIL::Module::Initstate(RTLIL::IdString name
, const std::string
&src
)
2372 RTLIL::SigSpec sig
= addWire(NEW_ID
);
2373 Cell
*cell
= addCell(name
, ID($initstate
));
2374 cell
->setPort(ID::Y
, sig
);
2375 cell
->set_src_attribute(src
);
2381 static unsigned int hashidx_count
= 123456789;
2382 hashidx_count
= mkhash_xorshift(hashidx_count
);
2383 hashidx_
= hashidx_count
;
2390 port_output
= false;
2394 RTLIL::Wire::get_all_wires()->insert(std::pair
<unsigned int, RTLIL::Wire
*>(hashidx_
, this));
2398 RTLIL::Wire::~Wire()
2401 RTLIL::Wire::get_all_wires()->erase(hashidx_
);
2406 static std::map
<unsigned int, RTLIL::Wire
*> all_wires
;
2407 std::map
<unsigned int, RTLIL::Wire
*> *RTLIL::Wire::get_all_wires(void)
2413 RTLIL::Memory::Memory()
2415 static unsigned int hashidx_count
= 123456789;
2416 hashidx_count
= mkhash_xorshift(hashidx_count
);
2417 hashidx_
= hashidx_count
;
2423 RTLIL::Memory::get_all_memorys()->insert(std::pair
<unsigned int, RTLIL::Memory
*>(hashidx_
, this));
2427 RTLIL::Cell::Cell() : module(nullptr)
2429 static unsigned int hashidx_count
= 123456789;
2430 hashidx_count
= mkhash_xorshift(hashidx_count
);
2431 hashidx_
= hashidx_count
;
2433 // log("#memtrace# %p\n", this);
2437 RTLIL::Cell::get_all_cells()->insert(std::pair
<unsigned int, RTLIL::Cell
*>(hashidx_
, this));
2441 RTLIL::Cell::~Cell()
2444 RTLIL::Cell::get_all_cells()->erase(hashidx_
);
2449 static std::map
<unsigned int, RTLIL::Cell
*> all_cells
;
2450 std::map
<unsigned int, RTLIL::Cell
*> *RTLIL::Cell::get_all_cells(void)
2456 bool RTLIL::Cell::hasPort(RTLIL::IdString portname
) const
2458 return connections_
.count(portname
) != 0;
2461 void RTLIL::Cell::unsetPort(RTLIL::IdString portname
)
2463 RTLIL::SigSpec signal
;
2464 auto conn_it
= connections_
.find(portname
);
2466 if (conn_it
!= connections_
.end())
2468 for (auto mon
: module
->monitors
)
2469 mon
->notify_connect(this, conn_it
->first
, conn_it
->second
, signal
);
2472 for (auto mon
: module
->design
->monitors
)
2473 mon
->notify_connect(this, conn_it
->first
, conn_it
->second
, signal
);
2476 log("#X# Unconnect %s.%s.%s\n", log_id(this->module
), log_id(this), log_id(portname
));
2477 log_backtrace("-X- ", yosys_xtrace
-1);
2480 connections_
.erase(conn_it
);
2484 void RTLIL::Cell::setPort(RTLIL::IdString portname
, RTLIL::SigSpec signal
)
2486 auto r
= connections_
.insert(portname
);
2487 auto conn_it
= r
.first
;
2488 if (!r
.second
&& conn_it
->second
== signal
)
2491 for (auto mon
: module
->monitors
)
2492 mon
->notify_connect(this, conn_it
->first
, conn_it
->second
, signal
);
2495 for (auto mon
: module
->design
->monitors
)
2496 mon
->notify_connect(this, conn_it
->first
, conn_it
->second
, signal
);
2499 log("#X# Connect %s.%s.%s = %s (%d)\n", log_id(this->module
), log_id(this), log_id(portname
), log_signal(signal
), GetSize(signal
));
2500 log_backtrace("-X- ", yosys_xtrace
-1);
2503 conn_it
->second
= std::move(signal
);
2506 const RTLIL::SigSpec
&RTLIL::Cell::getPort(RTLIL::IdString portname
) const
2508 return connections_
.at(portname
);
2511 const dict
<RTLIL::IdString
, RTLIL::SigSpec
> &RTLIL::Cell::connections() const
2513 return connections_
;
2516 bool RTLIL::Cell::known() const
2518 if (yosys_celltypes
.cell_known(type
))
2520 if (module
&& module
->design
&& module
->design
->module(type
))
2525 bool RTLIL::Cell::input(RTLIL::IdString portname
) const
2527 if (yosys_celltypes
.cell_known(type
))
2528 return yosys_celltypes
.cell_input(type
, portname
);
2529 if (module
&& module
->design
) {
2530 RTLIL::Module
*m
= module
->design
->module(type
);
2531 RTLIL::Wire
*w
= m
? m
->wire(portname
) : nullptr;
2532 return w
&& w
->port_input
;
2537 bool RTLIL::Cell::output(RTLIL::IdString portname
) const
2539 if (yosys_celltypes
.cell_known(type
))
2540 return yosys_celltypes
.cell_output(type
, portname
);
2541 if (module
&& module
->design
) {
2542 RTLIL::Module
*m
= module
->design
->module(type
);
2543 RTLIL::Wire
*w
= m
? m
->wire(portname
) : nullptr;
2544 return w
&& w
->port_output
;
2549 bool RTLIL::Cell::hasParam(RTLIL::IdString paramname
) const
2551 return parameters
.count(paramname
) != 0;
2554 void RTLIL::Cell::unsetParam(RTLIL::IdString paramname
)
2556 parameters
.erase(paramname
);
2559 void RTLIL::Cell::setParam(RTLIL::IdString paramname
, RTLIL::Const value
)
2561 parameters
[paramname
] = std::move(value
);
2564 const RTLIL::Const
&RTLIL::Cell::getParam(RTLIL::IdString paramname
) const
2566 return parameters
.at(paramname
);
2569 void RTLIL::Cell::sort()
2571 connections_
.sort(sort_by_id_str());
2572 parameters
.sort(sort_by_id_str());
2573 attributes
.sort(sort_by_id_str());
2576 void RTLIL::Cell::check()
2579 InternalCellChecker
checker(NULL
, this);
2584 void RTLIL::Cell::fixup_parameters(bool set_a_signed
, bool set_b_signed
)
2586 if (!type
.begins_with("$") || type
.begins_with("$_") || type
.begins_with("$paramod") || type
.begins_with("$fmcombine") ||
2587 type
.begins_with("$verific$") || type
.begins_with("$array:") || type
.begins_with("$extern:"))
2590 if (type
== ID($mux
) || type
== ID($pmux
)) {
2591 parameters
[ID::WIDTH
] = GetSize(connections_
[ID::Y
]);
2592 if (type
== ID($pmux
))
2593 parameters
[ID::S_WIDTH
] = GetSize(connections_
[ID::S
]);
2598 if (type
== ID($lut
) || type
== ID($sop
)) {
2599 parameters
[ID::WIDTH
] = GetSize(connections_
[ID::A
]);
2603 if (type
== ID($fa
)) {
2604 parameters
[ID::WIDTH
] = GetSize(connections_
[ID::Y
]);
2608 if (type
== ID($lcu
)) {
2609 parameters
[ID::WIDTH
] = GetSize(connections_
[ID::CO
]);
2613 bool signedness_ab
= !type
.in(ID($slice
), ID($concat
), ID($macc
));
2615 if (connections_
.count(ID::A
)) {
2616 if (signedness_ab
) {
2618 parameters
[ID::A_SIGNED
] = true;
2619 else if (parameters
.count(ID::A_SIGNED
) == 0)
2620 parameters
[ID::A_SIGNED
] = false;
2622 parameters
[ID::A_WIDTH
] = GetSize(connections_
[ID::A
]);
2625 if (connections_
.count(ID::B
)) {
2626 if (signedness_ab
) {
2628 parameters
[ID::B_SIGNED
] = true;
2629 else if (parameters
.count(ID::B_SIGNED
) == 0)
2630 parameters
[ID::B_SIGNED
] = false;
2632 parameters
[ID::B_WIDTH
] = GetSize(connections_
[ID::B
]);
2635 if (connections_
.count(ID::Y
))
2636 parameters
[ID::Y_WIDTH
] = GetSize(connections_
[ID::Y
]);
2638 if (connections_
.count(ID::Q
))
2639 parameters
[ID::WIDTH
] = GetSize(connections_
[ID::Q
]);
2644 RTLIL::SigChunk::SigChunk()
2651 RTLIL::SigChunk::SigChunk(const RTLIL::Const
&value
)
2655 width
= GetSize(data
);
2659 RTLIL::SigChunk::SigChunk(RTLIL::Wire
*wire
)
2661 log_assert(wire
!= nullptr);
2663 this->width
= wire
->width
;
2667 RTLIL::SigChunk::SigChunk(RTLIL::Wire
*wire
, int offset
, int width
)
2669 log_assert(wire
!= nullptr);
2671 this->width
= width
;
2672 this->offset
= offset
;
2675 RTLIL::SigChunk::SigChunk(const std::string
&str
)
2678 data
= RTLIL::Const(str
).bits
;
2679 width
= GetSize(data
);
2683 RTLIL::SigChunk::SigChunk(int val
, int width
)
2686 data
= RTLIL::Const(val
, width
).bits
;
2687 this->width
= GetSize(data
);
2691 RTLIL::SigChunk::SigChunk(RTLIL::State bit
, int width
)
2694 data
= RTLIL::Const(bit
, width
).bits
;
2695 this->width
= GetSize(data
);
2699 RTLIL::SigChunk::SigChunk(const RTLIL::SigBit
&bit
)
2704 data
= RTLIL::Const(bit
.data
).bits
;
2706 offset
= bit
.offset
;
2710 RTLIL::SigChunk::SigChunk(const RTLIL::SigChunk
&sigchunk
)
2715 RTLIL::SigChunk
RTLIL::SigChunk::extract(int offset
, int length
) const
2717 RTLIL::SigChunk ret
;
2720 ret
.offset
= this->offset
+ offset
;
2723 for (int i
= 0; i
< length
; i
++)
2724 ret
.data
.push_back(data
[offset
+i
]);
2730 bool RTLIL::SigChunk::operator <(const RTLIL::SigChunk
&other
) const
2732 if (wire
&& other
.wire
)
2733 if (wire
->name
!= other
.wire
->name
)
2734 return wire
->name
< other
.wire
->name
;
2736 if (wire
!= other
.wire
)
2737 return wire
< other
.wire
;
2739 if (offset
!= other
.offset
)
2740 return offset
< other
.offset
;
2742 if (width
!= other
.width
)
2743 return width
< other
.width
;
2745 return data
< other
.data
;
2748 bool RTLIL::SigChunk::operator ==(const RTLIL::SigChunk
&other
) const
2750 return wire
== other
.wire
&& width
== other
.width
&& offset
== other
.offset
&& data
== other
.data
;
2753 bool RTLIL::SigChunk::operator !=(const RTLIL::SigChunk
&other
) const
2760 RTLIL::SigSpec::SigSpec()
2766 RTLIL::SigSpec::SigSpec(const RTLIL::SigSpec
&other
)
2771 RTLIL::SigSpec::SigSpec(std::initializer_list
<RTLIL::SigSpec
> parts
)
2773 cover("kernel.rtlil.sigspec.init.list");
2778 log_assert(parts
.size() > 0);
2779 auto ie
= parts
.begin();
2780 auto it
= ie
+ parts
.size() - 1;
2785 RTLIL::SigSpec
&RTLIL::SigSpec::operator=(const RTLIL::SigSpec
&other
)
2787 cover("kernel.rtlil.sigspec.assign");
2789 width_
= other
.width_
;
2790 hash_
= other
.hash_
;
2791 chunks_
= other
.chunks_
;
2792 bits_
= other
.bits_
;
2796 RTLIL::SigSpec::SigSpec(const RTLIL::Const
&value
)
2798 cover("kernel.rtlil.sigspec.init.const");
2800 chunks_
.emplace_back(value
);
2801 width_
= chunks_
.back().width
;
2806 RTLIL::SigSpec::SigSpec(const RTLIL::SigChunk
&chunk
)
2808 cover("kernel.rtlil.sigspec.init.chunk");
2810 chunks_
.emplace_back(chunk
);
2811 width_
= chunks_
.back().width
;
2816 RTLIL::SigSpec::SigSpec(RTLIL::Wire
*wire
)
2818 cover("kernel.rtlil.sigspec.init.wire");
2820 chunks_
.emplace_back(wire
);
2821 width_
= chunks_
.back().width
;
2826 RTLIL::SigSpec::SigSpec(RTLIL::Wire
*wire
, int offset
, int width
)
2828 cover("kernel.rtlil.sigspec.init.wire_part");
2830 chunks_
.emplace_back(wire
, offset
, width
);
2831 width_
= chunks_
.back().width
;
2836 RTLIL::SigSpec::SigSpec(const std::string
&str
)
2838 cover("kernel.rtlil.sigspec.init.str");
2840 chunks_
.emplace_back(str
);
2841 width_
= chunks_
.back().width
;
2846 RTLIL::SigSpec::SigSpec(int val
, int width
)
2848 cover("kernel.rtlil.sigspec.init.int");
2850 chunks_
.emplace_back(val
, width
);
2856 RTLIL::SigSpec::SigSpec(RTLIL::State bit
, int width
)
2858 cover("kernel.rtlil.sigspec.init.state");
2860 chunks_
.emplace_back(bit
, width
);
2866 RTLIL::SigSpec::SigSpec(const RTLIL::SigBit
&bit
, int width
)
2868 cover("kernel.rtlil.sigspec.init.bit");
2870 if (bit
.wire
== NULL
)
2871 chunks_
.emplace_back(bit
.data
, width
);
2873 for (int i
= 0; i
< width
; i
++)
2874 chunks_
.push_back(bit
);
2880 RTLIL::SigSpec::SigSpec(const std::vector
<RTLIL::SigChunk
> &chunks
)
2882 cover("kernel.rtlil.sigspec.init.stdvec_chunks");
2886 for (const auto &c
: chunks
)
2891 RTLIL::SigSpec::SigSpec(const std::vector
<RTLIL::SigBit
> &bits
)
2893 cover("kernel.rtlil.sigspec.init.stdvec_bits");
2897 for (const auto &bit
: bits
)
2902 RTLIL::SigSpec::SigSpec(const pool
<RTLIL::SigBit
> &bits
)
2904 cover("kernel.rtlil.sigspec.init.pool_bits");
2908 for (const auto &bit
: bits
)
2913 RTLIL::SigSpec::SigSpec(const std::set
<RTLIL::SigBit
> &bits
)
2915 cover("kernel.rtlil.sigspec.init.stdset_bits");
2919 for (const auto &bit
: bits
)
2924 RTLIL::SigSpec::SigSpec(bool bit
)
2926 cover("kernel.rtlil.sigspec.init.bool");
2930 append(SigBit(bit
));
2934 void RTLIL::SigSpec::pack() const
2936 RTLIL::SigSpec
*that
= (RTLIL::SigSpec
*)this;
2938 if (that
->bits_
.empty())
2941 cover("kernel.rtlil.sigspec.convert.pack");
2942 log_assert(that
->chunks_
.empty());
2944 std::vector
<RTLIL::SigBit
> old_bits
;
2945 old_bits
.swap(that
->bits_
);
2947 RTLIL::SigChunk
*last
= NULL
;
2948 int last_end_offset
= 0;
2950 for (auto &bit
: old_bits
) {
2951 if (last
&& bit
.wire
== last
->wire
) {
2952 if (bit
.wire
== NULL
) {
2953 last
->data
.push_back(bit
.data
);
2956 } else if (last_end_offset
== bit
.offset
) {
2962 that
->chunks_
.push_back(bit
);
2963 last
= &that
->chunks_
.back();
2964 last_end_offset
= bit
.offset
+ 1;
2970 void RTLIL::SigSpec::unpack() const
2972 RTLIL::SigSpec
*that
= (RTLIL::SigSpec
*)this;
2974 if (that
->chunks_
.empty())
2977 cover("kernel.rtlil.sigspec.convert.unpack");
2978 log_assert(that
->bits_
.empty());
2980 that
->bits_
.reserve(that
->width_
);
2981 for (auto &c
: that
->chunks_
)
2982 for (int i
= 0; i
< c
.width
; i
++)
2983 that
->bits_
.emplace_back(c
, i
);
2985 that
->chunks_
.clear();
2989 void RTLIL::SigSpec::updhash() const
2991 RTLIL::SigSpec
*that
= (RTLIL::SigSpec
*)this;
2993 if (that
->hash_
!= 0)
2996 cover("kernel.rtlil.sigspec.hash");
2999 that
->hash_
= mkhash_init
;
3000 for (auto &c
: that
->chunks_
)
3001 if (c
.wire
== NULL
) {
3002 for (auto &v
: c
.data
)
3003 that
->hash_
= mkhash(that
->hash_
, v
);
3005 that
->hash_
= mkhash(that
->hash_
, c
.wire
->name
.index_
);
3006 that
->hash_
= mkhash(that
->hash_
, c
.offset
);
3007 that
->hash_
= mkhash(that
->hash_
, c
.width
);
3010 if (that
->hash_
== 0)
3014 void RTLIL::SigSpec::sort()
3017 cover("kernel.rtlil.sigspec.sort");
3018 std::sort(bits_
.begin(), bits_
.end());
3021 void RTLIL::SigSpec::sort_and_unify()
3024 cover("kernel.rtlil.sigspec.sort_and_unify");
3026 // A copy of the bits vector is used to prevent duplicating the logic from
3027 // SigSpec::SigSpec(std::vector<SigBit>). This incurrs an extra copy but
3028 // that isn't showing up as significant in profiles.
3029 std::vector
<SigBit
> unique_bits
= bits_
;
3030 std::sort(unique_bits
.begin(), unique_bits
.end());
3031 auto last
= std::unique(unique_bits
.begin(), unique_bits
.end());
3032 unique_bits
.erase(last
, unique_bits
.end());
3034 *this = unique_bits
;
3037 void RTLIL::SigSpec::replace(const RTLIL::SigSpec
&pattern
, const RTLIL::SigSpec
&with
)
3039 replace(pattern
, with
, this);
3042 void RTLIL::SigSpec::replace(const RTLIL::SigSpec
&pattern
, const RTLIL::SigSpec
&with
, RTLIL::SigSpec
*other
) const
3044 log_assert(other
!= NULL
);
3045 log_assert(width_
== other
->width_
);
3046 log_assert(pattern
.width_
== with
.width_
);
3053 for (int i
= 0; i
< GetSize(pattern
.bits_
); i
++) {
3054 if (pattern
.bits_
[i
].wire
!= NULL
) {
3055 for (int j
= 0; j
< GetSize(bits_
); j
++) {
3056 if (bits_
[j
] == pattern
.bits_
[i
]) {
3057 other
->bits_
[j
] = with
.bits_
[i
];
3066 void RTLIL::SigSpec::replace(const dict
<RTLIL::SigBit
, RTLIL::SigBit
> &rules
)
3068 replace(rules
, this);
3071 void RTLIL::SigSpec::replace(const dict
<RTLIL::SigBit
, RTLIL::SigBit
> &rules
, RTLIL::SigSpec
*other
) const
3073 cover("kernel.rtlil.sigspec.replace_dict");
3075 log_assert(other
!= NULL
);
3076 log_assert(width_
== other
->width_
);
3078 if (rules
.empty()) return;
3082 for (int i
= 0; i
< GetSize(bits_
); i
++) {
3083 auto it
= rules
.find(bits_
[i
]);
3084 if (it
!= rules
.end())
3085 other
->bits_
[i
] = it
->second
;
3091 void RTLIL::SigSpec::replace(const std::map
<RTLIL::SigBit
, RTLIL::SigBit
> &rules
)
3093 replace(rules
, this);
3096 void RTLIL::SigSpec::replace(const std::map
<RTLIL::SigBit
, RTLIL::SigBit
> &rules
, RTLIL::SigSpec
*other
) const
3098 cover("kernel.rtlil.sigspec.replace_map");
3100 log_assert(other
!= NULL
);
3101 log_assert(width_
== other
->width_
);
3103 if (rules
.empty()) return;
3107 for (int i
= 0; i
< GetSize(bits_
); i
++) {
3108 auto it
= rules
.find(bits_
[i
]);
3109 if (it
!= rules
.end())
3110 other
->bits_
[i
] = it
->second
;
3116 void RTLIL::SigSpec::remove(const RTLIL::SigSpec
&pattern
)
3118 remove2(pattern
, NULL
);
3121 void RTLIL::SigSpec::remove(const RTLIL::SigSpec
&pattern
, RTLIL::SigSpec
*other
) const
3123 RTLIL::SigSpec tmp
= *this;
3124 tmp
.remove2(pattern
, other
);
3127 void RTLIL::SigSpec::remove2(const RTLIL::SigSpec
&pattern
, RTLIL::SigSpec
*other
)
3130 cover("kernel.rtlil.sigspec.remove_other");
3132 cover("kernel.rtlil.sigspec.remove");
3135 if (other
!= NULL
) {
3136 log_assert(width_
== other
->width_
);
3140 for (int i
= GetSize(bits_
) - 1; i
>= 0; i
--)
3142 if (bits_
[i
].wire
== NULL
) continue;
3144 for (auto &pattern_chunk
: pattern
.chunks())
3145 if (bits_
[i
].wire
== pattern_chunk
.wire
&&
3146 bits_
[i
].offset
>= pattern_chunk
.offset
&&
3147 bits_
[i
].offset
< pattern_chunk
.offset
+ pattern_chunk
.width
) {
3148 bits_
.erase(bits_
.begin() + i
);
3150 if (other
!= NULL
) {
3151 other
->bits_
.erase(other
->bits_
.begin() + i
);
3161 void RTLIL::SigSpec::remove(const pool
<RTLIL::SigBit
> &pattern
)
3163 remove2(pattern
, NULL
);
3166 void RTLIL::SigSpec::remove(const pool
<RTLIL::SigBit
> &pattern
, RTLIL::SigSpec
*other
) const
3168 RTLIL::SigSpec tmp
= *this;
3169 tmp
.remove2(pattern
, other
);
3172 void RTLIL::SigSpec::remove2(const pool
<RTLIL::SigBit
> &pattern
, RTLIL::SigSpec
*other
)
3175 cover("kernel.rtlil.sigspec.remove_other");
3177 cover("kernel.rtlil.sigspec.remove");
3181 if (other
!= NULL
) {
3182 log_assert(width_
== other
->width_
);
3186 for (int i
= GetSize(bits_
) - 1; i
>= 0; i
--) {
3187 if (bits_
[i
].wire
!= NULL
&& pattern
.count(bits_
[i
])) {
3188 bits_
.erase(bits_
.begin() + i
);
3190 if (other
!= NULL
) {
3191 other
->bits_
.erase(other
->bits_
.begin() + i
);
3200 void RTLIL::SigSpec::remove2(const std::set
<RTLIL::SigBit
> &pattern
, RTLIL::SigSpec
*other
)
3203 cover("kernel.rtlil.sigspec.remove_other");
3205 cover("kernel.rtlil.sigspec.remove");
3209 if (other
!= NULL
) {
3210 log_assert(width_
== other
->width_
);
3214 for (int i
= GetSize(bits_
) - 1; i
>= 0; i
--) {
3215 if (bits_
[i
].wire
!= NULL
&& pattern
.count(bits_
[i
])) {
3216 bits_
.erase(bits_
.begin() + i
);
3218 if (other
!= NULL
) {
3219 other
->bits_
.erase(other
->bits_
.begin() + i
);
3228 RTLIL::SigSpec
RTLIL::SigSpec::extract(const RTLIL::SigSpec
&pattern
, const RTLIL::SigSpec
*other
) const
3231 cover("kernel.rtlil.sigspec.extract_other");
3233 cover("kernel.rtlil.sigspec.extract");
3235 log_assert(other
== NULL
|| width_
== other
->width_
);
3238 std::vector
<RTLIL::SigBit
> bits_match
= to_sigbit_vector();
3240 for (auto& pattern_chunk
: pattern
.chunks()) {
3242 std::vector
<RTLIL::SigBit
> bits_other
= other
->to_sigbit_vector();
3243 for (int i
= 0; i
< width_
; i
++)
3244 if (bits_match
[i
].wire
&&
3245 bits_match
[i
].wire
== pattern_chunk
.wire
&&
3246 bits_match
[i
].offset
>= pattern_chunk
.offset
&&
3247 bits_match
[i
].offset
< pattern_chunk
.offset
+ pattern_chunk
.width
)
3248 ret
.append(bits_other
[i
]);
3250 for (int i
= 0; i
< width_
; i
++)
3251 if (bits_match
[i
].wire
&&
3252 bits_match
[i
].wire
== pattern_chunk
.wire
&&
3253 bits_match
[i
].offset
>= pattern_chunk
.offset
&&
3254 bits_match
[i
].offset
< pattern_chunk
.offset
+ pattern_chunk
.width
)
3255 ret
.append(bits_match
[i
]);
3263 RTLIL::SigSpec
RTLIL::SigSpec::extract(const pool
<RTLIL::SigBit
> &pattern
, const RTLIL::SigSpec
*other
) const
3266 cover("kernel.rtlil.sigspec.extract_other");
3268 cover("kernel.rtlil.sigspec.extract");
3270 log_assert(other
== NULL
|| width_
== other
->width_
);
3272 std::vector
<RTLIL::SigBit
> bits_match
= to_sigbit_vector();
3276 std::vector
<RTLIL::SigBit
> bits_other
= other
->to_sigbit_vector();
3277 for (int i
= 0; i
< width_
; i
++)
3278 if (bits_match
[i
].wire
&& pattern
.count(bits_match
[i
]))
3279 ret
.append(bits_other
[i
]);
3281 for (int i
= 0; i
< width_
; i
++)
3282 if (bits_match
[i
].wire
&& pattern
.count(bits_match
[i
]))
3283 ret
.append(bits_match
[i
]);
3290 void RTLIL::SigSpec::replace(int offset
, const RTLIL::SigSpec
&with
)
3292 cover("kernel.rtlil.sigspec.replace_pos");
3297 log_assert(offset
>= 0);
3298 log_assert(with
.width_
>= 0);
3299 log_assert(offset
+with
.width_
<= width_
);
3301 for (int i
= 0; i
< with
.width_
; i
++)
3302 bits_
.at(offset
+ i
) = with
.bits_
.at(i
);
3307 void RTLIL::SigSpec::remove_const()
3311 cover("kernel.rtlil.sigspec.remove_const.packed");
3313 std::vector
<RTLIL::SigChunk
> new_chunks
;
3314 new_chunks
.reserve(GetSize(chunks_
));
3317 for (auto &chunk
: chunks_
)
3318 if (chunk
.wire
!= NULL
) {
3319 new_chunks
.push_back(chunk
);
3320 width_
+= chunk
.width
;
3323 chunks_
.swap(new_chunks
);
3327 cover("kernel.rtlil.sigspec.remove_const.unpacked");
3329 std::vector
<RTLIL::SigBit
> new_bits
;
3330 new_bits
.reserve(width_
);
3332 for (auto &bit
: bits_
)
3333 if (bit
.wire
!= NULL
)
3334 new_bits
.push_back(bit
);
3336 bits_
.swap(new_bits
);
3337 width_
= bits_
.size();
3343 void RTLIL::SigSpec::remove(int offset
, int length
)
3345 cover("kernel.rtlil.sigspec.remove_pos");
3349 log_assert(offset
>= 0);
3350 log_assert(length
>= 0);
3351 log_assert(offset
+ length
<= width_
);
3353 bits_
.erase(bits_
.begin() + offset
, bits_
.begin() + offset
+ length
);
3354 width_
= bits_
.size();
3359 RTLIL::SigSpec
RTLIL::SigSpec::extract(int offset
, int length
) const
3362 cover("kernel.rtlil.sigspec.extract_pos");
3363 return std::vector
<RTLIL::SigBit
>(bits_
.begin() + offset
, bits_
.begin() + offset
+ length
);
3366 void RTLIL::SigSpec::append(const RTLIL::SigSpec
&signal
)
3368 if (signal
.width_
== 0)
3376 cover("kernel.rtlil.sigspec.append");
3378 if (packed() != signal
.packed()) {
3384 for (auto &other_c
: signal
.chunks_
)
3386 auto &my_last_c
= chunks_
.back();
3387 if (my_last_c
.wire
== NULL
&& other_c
.wire
== NULL
) {
3388 auto &this_data
= my_last_c
.data
;
3389 auto &other_data
= other_c
.data
;
3390 this_data
.insert(this_data
.end(), other_data
.begin(), other_data
.end());
3391 my_last_c
.width
+= other_c
.width
;
3393 if (my_last_c
.wire
== other_c
.wire
&& my_last_c
.offset
+ my_last_c
.width
== other_c
.offset
) {
3394 my_last_c
.width
+= other_c
.width
;
3396 chunks_
.push_back(other_c
);
3399 bits_
.insert(bits_
.end(), signal
.bits_
.begin(), signal
.bits_
.end());
3401 width_
+= signal
.width_
;
3405 void RTLIL::SigSpec::append(const RTLIL::SigBit
&bit
)
3409 cover("kernel.rtlil.sigspec.append_bit.packed");
3411 if (chunks_
.size() == 0)
3412 chunks_
.push_back(bit
);
3414 if (bit
.wire
== NULL
)
3415 if (chunks_
.back().wire
== NULL
) {
3416 chunks_
.back().data
.push_back(bit
.data
);
3417 chunks_
.back().width
++;
3419 chunks_
.push_back(bit
);
3421 if (chunks_
.back().wire
== bit
.wire
&& chunks_
.back().offset
+ chunks_
.back().width
== bit
.offset
)
3422 chunks_
.back().width
++;
3424 chunks_
.push_back(bit
);
3428 cover("kernel.rtlil.sigspec.append_bit.unpacked");
3429 bits_
.push_back(bit
);
3436 void RTLIL::SigSpec::extend_u0(int width
, bool is_signed
)
3438 cover("kernel.rtlil.sigspec.extend_u0");
3443 remove(width
, width_
- width
);
3445 if (width_
< width
) {
3446 RTLIL::SigBit padding
= width_
> 0 ? (*this)[width_
- 1] : RTLIL::State::Sx
;
3448 padding
= RTLIL::State::S0
;
3449 while (width_
< width
)
3455 RTLIL::SigSpec
RTLIL::SigSpec::repeat(int num
) const
3457 cover("kernel.rtlil.sigspec.repeat");
3460 for (int i
= 0; i
< num
; i
++)
3466 void RTLIL::SigSpec::check() const
3470 cover("kernel.rtlil.sigspec.check.skip");
3474 cover("kernel.rtlil.sigspec.check.packed");
3477 for (size_t i
= 0; i
< chunks_
.size(); i
++) {
3478 const RTLIL::SigChunk
&chunk
= chunks_
[i
];
3479 if (chunk
.wire
== NULL
) {
3481 log_assert(chunks_
[i
-1].wire
!= NULL
);
3482 log_assert(chunk
.offset
== 0);
3483 log_assert(chunk
.data
.size() == (size_t)chunk
.width
);
3485 if (i
> 0 && chunks_
[i
-1].wire
== chunk
.wire
)
3486 log_assert(chunk
.offset
!= chunks_
[i
-1].offset
+ chunks_
[i
-1].width
);
3487 log_assert(chunk
.offset
>= 0);
3488 log_assert(chunk
.width
>= 0);
3489 log_assert(chunk
.offset
+ chunk
.width
<= chunk
.wire
->width
);
3490 log_assert(chunk
.data
.size() == 0);
3494 log_assert(w
== width_
);
3495 log_assert(bits_
.empty());
3499 cover("kernel.rtlil.sigspec.check.unpacked");
3501 log_assert(width_
== GetSize(bits_
));
3502 log_assert(chunks_
.empty());
3507 bool RTLIL::SigSpec::operator <(const RTLIL::SigSpec
&other
) const
3509 cover("kernel.rtlil.sigspec.comp_lt");
3514 if (width_
!= other
.width_
)
3515 return width_
< other
.width_
;
3520 if (chunks_
.size() != other
.chunks_
.size())
3521 return chunks_
.size() < other
.chunks_
.size();
3526 if (hash_
!= other
.hash_
)
3527 return hash_
< other
.hash_
;
3529 for (size_t i
= 0; i
< chunks_
.size(); i
++)
3530 if (chunks_
[i
] != other
.chunks_
[i
]) {
3531 cover("kernel.rtlil.sigspec.comp_lt.hash_collision");
3532 return chunks_
[i
] < other
.chunks_
[i
];
3535 cover("kernel.rtlil.sigspec.comp_lt.equal");
3539 bool RTLIL::SigSpec::operator ==(const RTLIL::SigSpec
&other
) const
3541 cover("kernel.rtlil.sigspec.comp_eq");
3546 if (width_
!= other
.width_
)
3549 // Without this, SigSpec() == SigSpec(State::S0, 0) will fail
3550 // since the RHS will contain one SigChunk of width 0 causing
3551 // the size check below to fail
3558 if (chunks_
.size() != other
.chunks_
.size())
3564 if (hash_
!= other
.hash_
)
3567 for (size_t i
= 0; i
< chunks_
.size(); i
++)
3568 if (chunks_
[i
] != other
.chunks_
[i
]) {
3569 cover("kernel.rtlil.sigspec.comp_eq.hash_collision");
3573 cover("kernel.rtlil.sigspec.comp_eq.equal");
3577 bool RTLIL::SigSpec::is_wire() const
3579 cover("kernel.rtlil.sigspec.is_wire");
3582 return GetSize(chunks_
) == 1 && chunks_
[0].wire
&& chunks_
[0].wire
->width
== width_
;
3585 bool RTLIL::SigSpec::is_chunk() const
3587 cover("kernel.rtlil.sigspec.is_chunk");
3590 return GetSize(chunks_
) == 1;
3593 bool RTLIL::SigSpec::is_fully_const() const
3595 cover("kernel.rtlil.sigspec.is_fully_const");
3598 for (auto it
= chunks_
.begin(); it
!= chunks_
.end(); it
++)
3599 if (it
->width
> 0 && it
->wire
!= NULL
)
3604 bool RTLIL::SigSpec::is_fully_zero() const
3606 cover("kernel.rtlil.sigspec.is_fully_zero");
3609 for (auto it
= chunks_
.begin(); it
!= chunks_
.end(); it
++) {
3610 if (it
->width
> 0 && it
->wire
!= NULL
)
3612 for (size_t i
= 0; i
< it
->data
.size(); i
++)
3613 if (it
->data
[i
] != RTLIL::State::S0
)
3619 bool RTLIL::SigSpec::is_fully_ones() const
3621 cover("kernel.rtlil.sigspec.is_fully_ones");
3624 for (auto it
= chunks_
.begin(); it
!= chunks_
.end(); it
++) {
3625 if (it
->width
> 0 && it
->wire
!= NULL
)
3627 for (size_t i
= 0; i
< it
->data
.size(); i
++)
3628 if (it
->data
[i
] != RTLIL::State::S1
)
3634 bool RTLIL::SigSpec::is_fully_def() const
3636 cover("kernel.rtlil.sigspec.is_fully_def");
3639 for (auto it
= chunks_
.begin(); it
!= chunks_
.end(); it
++) {
3640 if (it
->width
> 0 && it
->wire
!= NULL
)
3642 for (size_t i
= 0; i
< it
->data
.size(); i
++)
3643 if (it
->data
[i
] != RTLIL::State::S0
&& it
->data
[i
] != RTLIL::State::S1
)
3649 bool RTLIL::SigSpec::is_fully_undef() const
3651 cover("kernel.rtlil.sigspec.is_fully_undef");
3654 for (auto it
= chunks_
.begin(); it
!= chunks_
.end(); it
++) {
3655 if (it
->width
> 0 && it
->wire
!= NULL
)
3657 for (size_t i
= 0; i
< it
->data
.size(); i
++)
3658 if (it
->data
[i
] != RTLIL::State::Sx
&& it
->data
[i
] != RTLIL::State::Sz
)
3664 bool RTLIL::SigSpec::has_const() const
3666 cover("kernel.rtlil.sigspec.has_const");
3669 for (auto it
= chunks_
.begin(); it
!= chunks_
.end(); it
++)
3670 if (it
->width
> 0 && it
->wire
== NULL
)
3675 bool RTLIL::SigSpec::has_marked_bits() const
3677 cover("kernel.rtlil.sigspec.has_marked_bits");
3680 for (auto it
= chunks_
.begin(); it
!= chunks_
.end(); it
++)
3681 if (it
->width
> 0 && it
->wire
== NULL
) {
3682 for (size_t i
= 0; i
< it
->data
.size(); i
++)
3683 if (it
->data
[i
] == RTLIL::State::Sm
)
3689 bool RTLIL::SigSpec::as_bool() const
3691 cover("kernel.rtlil.sigspec.as_bool");
3694 log_assert(is_fully_const() && GetSize(chunks_
) <= 1);
3696 return RTLIL::Const(chunks_
[0].data
).as_bool();
3700 int RTLIL::SigSpec::as_int(bool is_signed
) const
3702 cover("kernel.rtlil.sigspec.as_int");
3705 log_assert(is_fully_const() && GetSize(chunks_
) <= 1);
3707 return RTLIL::Const(chunks_
[0].data
).as_int(is_signed
);
3711 std::string
RTLIL::SigSpec::as_string() const
3713 cover("kernel.rtlil.sigspec.as_string");
3717 str
.reserve(size());
3718 for (size_t i
= chunks_
.size(); i
> 0; i
--) {
3719 const RTLIL::SigChunk
&chunk
= chunks_
[i
-1];
3720 if (chunk
.wire
!= NULL
)
3721 str
.append(chunk
.width
, '?');
3723 str
+= RTLIL::Const(chunk
.data
).as_string();
3728 RTLIL::Const
RTLIL::SigSpec::as_const() const
3730 cover("kernel.rtlil.sigspec.as_const");
3733 log_assert(is_fully_const() && GetSize(chunks_
) <= 1);
3735 return chunks_
[0].data
;
3736 return RTLIL::Const();
3739 RTLIL::Wire
*RTLIL::SigSpec::as_wire() const
3741 cover("kernel.rtlil.sigspec.as_wire");
3744 log_assert(is_wire());
3745 return chunks_
[0].wire
;
3748 RTLIL::SigChunk
RTLIL::SigSpec::as_chunk() const
3750 cover("kernel.rtlil.sigspec.as_chunk");
3753 log_assert(is_chunk());
3757 RTLIL::SigBit
RTLIL::SigSpec::as_bit() const
3759 cover("kernel.rtlil.sigspec.as_bit");
3761 log_assert(width_
== 1);
3763 return RTLIL::SigBit(*chunks_
.begin());
3768 bool RTLIL::SigSpec::match(const char* pattern
) const
3770 cover("kernel.rtlil.sigspec.match");
3773 log_assert(int(strlen(pattern
)) == GetSize(bits_
));
3775 for (auto it
= bits_
.rbegin(); it
!= bits_
.rend(); it
++, pattern
++) {
3776 if (*pattern
== ' ')
3778 if (*pattern
== '*') {
3779 if (*it
!= State::Sz
&& *it
!= State::Sx
)
3783 if (*pattern
== '0') {
3784 if (*it
!= State::S0
)
3787 if (*pattern
== '1') {
3788 if (*it
!= State::S1
)
3797 std::set
<RTLIL::SigBit
> RTLIL::SigSpec::to_sigbit_set() const
3799 cover("kernel.rtlil.sigspec.to_sigbit_set");
3802 std::set
<RTLIL::SigBit
> sigbits
;
3803 for (auto &c
: chunks_
)
3804 for (int i
= 0; i
< c
.width
; i
++)
3805 sigbits
.insert(RTLIL::SigBit(c
, i
));
3809 pool
<RTLIL::SigBit
> RTLIL::SigSpec::to_sigbit_pool() const
3811 cover("kernel.rtlil.sigspec.to_sigbit_pool");
3814 pool
<RTLIL::SigBit
> sigbits
;
3815 sigbits
.reserve(size());
3816 for (auto &c
: chunks_
)
3817 for (int i
= 0; i
< c
.width
; i
++)
3818 sigbits
.insert(RTLIL::SigBit(c
, i
));
3822 std::vector
<RTLIL::SigBit
> RTLIL::SigSpec::to_sigbit_vector() const
3824 cover("kernel.rtlil.sigspec.to_sigbit_vector");
3830 std::map
<RTLIL::SigBit
, RTLIL::SigBit
> RTLIL::SigSpec::to_sigbit_map(const RTLIL::SigSpec
&other
) const
3832 cover("kernel.rtlil.sigspec.to_sigbit_map");
3837 log_assert(width_
== other
.width_
);
3839 std::map
<RTLIL::SigBit
, RTLIL::SigBit
> new_map
;
3840 for (int i
= 0; i
< width_
; i
++)
3841 new_map
[bits_
[i
]] = other
.bits_
[i
];
3846 dict
<RTLIL::SigBit
, RTLIL::SigBit
> RTLIL::SigSpec::to_sigbit_dict(const RTLIL::SigSpec
&other
) const
3848 cover("kernel.rtlil.sigspec.to_sigbit_dict");
3853 log_assert(width_
== other
.width_
);
3855 dict
<RTLIL::SigBit
, RTLIL::SigBit
> new_map
;
3856 new_map
.reserve(size());
3857 for (int i
= 0; i
< width_
; i
++)
3858 new_map
[bits_
[i
]] = other
.bits_
[i
];
3863 static void sigspec_parse_split(std::vector
<std::string
> &tokens
, const std::string
&text
, char sep
)
3865 size_t start
= 0, end
= 0;
3866 while ((end
= text
.find(sep
, start
)) != std::string::npos
) {
3867 tokens
.push_back(text
.substr(start
, end
- start
));
3870 tokens
.push_back(text
.substr(start
));
3873 static int sigspec_parse_get_dummy_line_num()
3878 bool RTLIL::SigSpec::parse(RTLIL::SigSpec
&sig
, RTLIL::Module
*module
, std::string str
)
3880 cover("kernel.rtlil.sigspec.parse");
3882 AST::current_filename
= "input";
3884 std::vector
<std::string
> tokens
;
3885 sigspec_parse_split(tokens
, str
, ',');
3887 sig
= RTLIL::SigSpec();
3888 for (int tokidx
= int(tokens
.size())-1; tokidx
>= 0; tokidx
--)
3890 std::string netname
= tokens
[tokidx
];
3891 std::string indices
;
3893 if (netname
.size() == 0)
3896 if (('0' <= netname
[0] && netname
[0] <= '9') || netname
[0] == '\'') {
3897 cover("kernel.rtlil.sigspec.parse.const");
3898 AST::get_line_num
= sigspec_parse_get_dummy_line_num
;
3899 AST::AstNode
*ast
= VERILOG_FRONTEND::const2ast(netname
);
3902 sig
.append(RTLIL::Const(ast
->bits
));
3910 cover("kernel.rtlil.sigspec.parse.net");
3912 if (netname
[0] != '$' && netname
[0] != '\\')
3913 netname
= "\\" + netname
;
3915 if (module
->wires_
.count(netname
) == 0) {
3916 size_t indices_pos
= netname
.size()-1;
3917 if (indices_pos
> 2 && netname
[indices_pos
] == ']')
3920 while (indices_pos
> 0 && ('0' <= netname
[indices_pos
] && netname
[indices_pos
] <= '9')) indices_pos
--;
3921 if (indices_pos
> 0 && netname
[indices_pos
] == ':') {
3923 while (indices_pos
> 0 && ('0' <= netname
[indices_pos
] && netname
[indices_pos
] <= '9')) indices_pos
--;
3925 if (indices_pos
> 0 && netname
[indices_pos
] == '[') {
3926 indices
= netname
.substr(indices_pos
);
3927 netname
= netname
.substr(0, indices_pos
);
3932 if (module
->wires_
.count(netname
) == 0)
3935 RTLIL::Wire
*wire
= module
->wires_
.at(netname
);
3936 if (!indices
.empty()) {
3937 std::vector
<std::string
> index_tokens
;
3938 sigspec_parse_split(index_tokens
, indices
.substr(1, indices
.size()-2), ':');
3939 if (index_tokens
.size() == 1) {
3940 cover("kernel.rtlil.sigspec.parse.bit_sel");
3941 int a
= atoi(index_tokens
.at(0).c_str());
3942 if (a
< 0 || a
>= wire
->width
)
3944 sig
.append(RTLIL::SigSpec(wire
, a
));
3946 cover("kernel.rtlil.sigspec.parse.part_sel");
3947 int a
= atoi(index_tokens
.at(0).c_str());
3948 int b
= atoi(index_tokens
.at(1).c_str());
3953 if (a
< 0 || a
>= wire
->width
)
3955 if (b
< 0 || b
>= wire
->width
)
3957 sig
.append(RTLIL::SigSpec(wire
, a
, b
-a
+1));
3966 bool RTLIL::SigSpec::parse_sel(RTLIL::SigSpec
&sig
, RTLIL::Design
*design
, RTLIL::Module
*module
, std::string str
)
3968 if (str
.empty() || str
[0] != '@')
3969 return parse(sig
, module
, str
);
3971 cover("kernel.rtlil.sigspec.parse.sel");
3973 str
= RTLIL::escape_id(str
.substr(1));
3974 if (design
->selection_vars
.count(str
) == 0)
3977 sig
= RTLIL::SigSpec();
3978 RTLIL::Selection
&sel
= design
->selection_vars
.at(str
);
3979 for (auto &it
: module
->wires_
)
3980 if (sel
.selected_member(module
->name
, it
.first
))
3981 sig
.append(it
.second
);
3986 bool RTLIL::SigSpec::parse_rhs(const RTLIL::SigSpec
&lhs
, RTLIL::SigSpec
&sig
, RTLIL::Module
*module
, std::string str
)
3989 cover("kernel.rtlil.sigspec.parse.rhs_zeros");
3990 sig
= RTLIL::SigSpec(RTLIL::State::S0
, lhs
.width_
);
3995 cover("kernel.rtlil.sigspec.parse.rhs_ones");
3996 sig
= RTLIL::SigSpec(RTLIL::State::S1
, lhs
.width_
);
4000 if (lhs
.chunks_
.size() == 1) {
4001 char *p
= (char*)str
.c_str(), *endptr
;
4002 long int val
= strtol(p
, &endptr
, 10);
4003 if (endptr
&& endptr
!= p
&& *endptr
== 0) {
4004 sig
= RTLIL::SigSpec(val
, lhs
.width_
);
4005 cover("kernel.rtlil.sigspec.parse.rhs_dec");
4010 return parse(sig
, module
, str
);
4013 RTLIL::CaseRule::~CaseRule()
4015 for (auto it
= switches
.begin(); it
!= switches
.end(); it
++)
4019 bool RTLIL::CaseRule::empty() const
4021 return actions
.empty() && switches
.empty();
4024 RTLIL::CaseRule
*RTLIL::CaseRule::clone() const
4026 RTLIL::CaseRule
*new_caserule
= new RTLIL::CaseRule
;
4027 new_caserule
->compare
= compare
;
4028 new_caserule
->actions
= actions
;
4029 for (auto &it
: switches
)
4030 new_caserule
->switches
.push_back(it
->clone());
4031 return new_caserule
;
4034 RTLIL::SwitchRule::~SwitchRule()
4036 for (auto it
= cases
.begin(); it
!= cases
.end(); it
++)
4040 bool RTLIL::SwitchRule::empty() const
4042 return cases
.empty();
4045 RTLIL::SwitchRule
*RTLIL::SwitchRule::clone() const
4047 RTLIL::SwitchRule
*new_switchrule
= new RTLIL::SwitchRule
;
4048 new_switchrule
->signal
= signal
;
4049 new_switchrule
->attributes
= attributes
;
4050 for (auto &it
: cases
)
4051 new_switchrule
->cases
.push_back(it
->clone());
4052 return new_switchrule
;
4056 RTLIL::SyncRule
*RTLIL::SyncRule::clone() const
4058 RTLIL::SyncRule
*new_syncrule
= new RTLIL::SyncRule
;
4059 new_syncrule
->type
= type
;
4060 new_syncrule
->signal
= signal
;
4061 new_syncrule
->actions
= actions
;
4062 return new_syncrule
;
4065 RTLIL::Process::~Process()
4067 for (auto it
= syncs
.begin(); it
!= syncs
.end(); it
++)
4071 RTLIL::Process
*RTLIL::Process::clone() const
4073 RTLIL::Process
*new_proc
= new RTLIL::Process
;
4075 new_proc
->name
= name
;
4076 new_proc
->attributes
= attributes
;
4078 RTLIL::CaseRule
*rc_ptr
= root_case
.clone();
4079 new_proc
->root_case
= *rc_ptr
;
4080 rc_ptr
->switches
.clear();
4083 for (auto &it
: syncs
)
4084 new_proc
->syncs
.push_back(it
->clone());
4090 RTLIL::Memory::~Memory()
4092 RTLIL::Memory::get_all_memorys()->erase(hashidx_
);
4094 static std::map
<unsigned int, RTLIL::Memory
*> all_memorys
;
4095 std::map
<unsigned int, RTLIL::Memory
*> *RTLIL::Memory::get_all_memorys(void)
4097 return &all_memorys
;