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kernel: Design::remove(RTLIL::Module *) to check refcount_modules_
[yosys.git] / kernel / rtlil.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 #include "kernel/yosys.h"
21 #include "kernel/macc.h"
22 #include "kernel/celltypes.h"
23 #include "frontends/verilog/verilog_frontend.h"
24 #include "frontends/verilog/preproc.h"
25 #include "backends/ilang/ilang_backend.h"
26
27 #include <string.h>
28 #include <algorithm>
29
30 YOSYS_NAMESPACE_BEGIN
31
32 RTLIL::IdString::destruct_guard_t RTLIL::IdString::destruct_guard;
33 std::vector<char*> RTLIL::IdString::global_id_storage_;
34 dict<char*, int, hash_cstr_ops> RTLIL::IdString::global_id_index_;
35 #ifndef YOSYS_NO_IDS_REFCNT
36 std::vector<int> RTLIL::IdString::global_refcount_storage_;
37 std::vector<int> RTLIL::IdString::global_free_idx_list_;
38 #endif
39 #ifdef YOSYS_USE_STICKY_IDS
40 int RTLIL::IdString::last_created_idx_[8];
41 int RTLIL::IdString::last_created_idx_ptr_;
42 #endif
43
44 #define X(_id) IdString RTLIL::ID::_id;
45 #include "kernel/constids.inc"
46 #undef X
47
48 dict<std::string, std::string> RTLIL::constpad;
49
50 const pool<IdString> &RTLIL::builtin_ff_cell_types() {
51 static const pool<IdString> res = {
52 ID($sr),
53 ID($ff),
54 ID($dff),
55 ID($dffe),
56 ID($dffsr),
57 ID($adff),
58 ID($dlatch),
59 ID($dlatchsr),
60 ID($_DFFE_NN_),
61 ID($_DFFE_NP_),
62 ID($_DFFE_PN_),
63 ID($_DFFE_PP_),
64 ID($_DFFSR_NNN_),
65 ID($_DFFSR_NNP_),
66 ID($_DFFSR_NPN_),
67 ID($_DFFSR_NPP_),
68 ID($_DFFSR_PNN_),
69 ID($_DFFSR_PNP_),
70 ID($_DFFSR_PPN_),
71 ID($_DFFSR_PPP_),
72 ID($_DFF_NN0_),
73 ID($_DFF_NN1_),
74 ID($_DFF_NP0_),
75 ID($_DFF_NP1_),
76 ID($_DFF_N_),
77 ID($_DFF_PN0_),
78 ID($_DFF_PN1_),
79 ID($_DFF_PP0_),
80 ID($_DFF_PP1_),
81 ID($_DFF_P_),
82 ID($_DLATCHSR_NNN_),
83 ID($_DLATCHSR_NNP_),
84 ID($_DLATCHSR_NPN_),
85 ID($_DLATCHSR_NPP_),
86 ID($_DLATCHSR_PNN_),
87 ID($_DLATCHSR_PNP_),
88 ID($_DLATCHSR_PPN_),
89 ID($_DLATCHSR_PPP_),
90 ID($_DLATCH_N_),
91 ID($_DLATCH_P_),
92 ID($_FF_),
93 };
94 return res;
95 }
96
97 RTLIL::Const::Const()
98 {
99 flags = RTLIL::CONST_FLAG_NONE;
100 }
101
102 RTLIL::Const::Const(std::string str)
103 {
104 flags = RTLIL::CONST_FLAG_STRING;
105 for (int i = str.size()-1; i >= 0; i--) {
106 unsigned char ch = str[i];
107 for (int j = 0; j < 8; j++) {
108 bits.push_back((ch & 1) != 0 ? State::S1 : State::S0);
109 ch = ch >> 1;
110 }
111 }
112 }
113
114 RTLIL::Const::Const(int val, int width)
115 {
116 flags = RTLIL::CONST_FLAG_NONE;
117 for (int i = 0; i < width; i++) {
118 bits.push_back((val & 1) != 0 ? State::S1 : State::S0);
119 val = val >> 1;
120 }
121 }
122
123 RTLIL::Const::Const(RTLIL::State bit, int width)
124 {
125 flags = RTLIL::CONST_FLAG_NONE;
126 for (int i = 0; i < width; i++)
127 bits.push_back(bit);
128 }
129
130 RTLIL::Const::Const(const std::vector<bool> &bits)
131 {
132 flags = RTLIL::CONST_FLAG_NONE;
133 for (const auto &b : bits)
134 this->bits.emplace_back(b ? State::S1 : State::S0);
135 }
136
137 RTLIL::Const::Const(const RTLIL::Const &c)
138 {
139 flags = c.flags;
140 for (const auto &b : c.bits)
141 this->bits.push_back(b);
142 }
143
144 bool RTLIL::Const::operator <(const RTLIL::Const &other) const
145 {
146 if (bits.size() != other.bits.size())
147 return bits.size() < other.bits.size();
148 for (size_t i = 0; i < bits.size(); i++)
149 if (bits[i] != other.bits[i])
150 return bits[i] < other.bits[i];
151 return false;
152 }
153
154 bool RTLIL::Const::operator ==(const RTLIL::Const &other) const
155 {
156 return bits == other.bits;
157 }
158
159 bool RTLIL::Const::operator !=(const RTLIL::Const &other) const
160 {
161 return bits != other.bits;
162 }
163
164 bool RTLIL::Const::as_bool() const
165 {
166 for (size_t i = 0; i < bits.size(); i++)
167 if (bits[i] == State::S1)
168 return true;
169 return false;
170 }
171
172 int RTLIL::Const::as_int(bool is_signed) const
173 {
174 int32_t ret = 0;
175 for (size_t i = 0; i < bits.size() && i < 32; i++)
176 if (bits[i] == State::S1)
177 ret |= 1 << i;
178 if (is_signed && bits.back() == State::S1)
179 for (size_t i = bits.size(); i < 32; i++)
180 ret |= 1 << i;
181 return ret;
182 }
183
184 std::string RTLIL::Const::as_string() const
185 {
186 std::string ret;
187 ret.reserve(bits.size());
188 for (size_t i = bits.size(); i > 0; i--)
189 switch (bits[i-1]) {
190 case S0: ret += "0"; break;
191 case S1: ret += "1"; break;
192 case Sx: ret += "x"; break;
193 case Sz: ret += "z"; break;
194 case Sa: ret += "-"; break;
195 case Sm: ret += "m"; break;
196 }
197 return ret;
198 }
199
200 RTLIL::Const RTLIL::Const::from_string(const std::string &str)
201 {
202 Const c;
203 c.bits.reserve(str.size());
204 for (auto it = str.rbegin(); it != str.rend(); it++)
205 switch (*it) {
206 case '0': c.bits.push_back(State::S0); break;
207 case '1': c.bits.push_back(State::S1); break;
208 case 'x': c.bits.push_back(State::Sx); break;
209 case 'z': c.bits.push_back(State::Sz); break;
210 case 'm': c.bits.push_back(State::Sm); break;
211 default: c.bits.push_back(State::Sa);
212 }
213 return c;
214 }
215
216 std::string RTLIL::Const::decode_string() const
217 {
218 std::string string;
219 string.reserve(GetSize(bits)/8);
220 for (int i = 0; i < GetSize(bits); i += 8) {
221 char ch = 0;
222 for (int j = 0; j < 8 && i + j < int (bits.size()); j++)
223 if (bits[i + j] == RTLIL::State::S1)
224 ch |= 1 << j;
225 if (ch != 0)
226 string.append({ch});
227 }
228 std::reverse(string.begin(), string.end());
229 return string;
230 }
231
232 bool RTLIL::Const::is_fully_zero() const
233 {
234 cover("kernel.rtlil.const.is_fully_zero");
235
236 for (const auto &bit : bits)
237 if (bit != RTLIL::State::S0)
238 return false;
239
240 return true;
241 }
242
243 bool RTLIL::Const::is_fully_ones() const
244 {
245 cover("kernel.rtlil.const.is_fully_ones");
246
247 for (const auto &bit : bits)
248 if (bit != RTLIL::State::S1)
249 return false;
250
251 return true;
252 }
253
254 bool RTLIL::Const::is_fully_def() const
255 {
256 cover("kernel.rtlil.const.is_fully_def");
257
258 for (const auto &bit : bits)
259 if (bit != RTLIL::State::S0 && bit != RTLIL::State::S1)
260 return false;
261
262 return true;
263 }
264
265 bool RTLIL::Const::is_fully_undef() const
266 {
267 cover("kernel.rtlil.const.is_fully_undef");
268
269 for (const auto &bit : bits)
270 if (bit != RTLIL::State::Sx && bit != RTLIL::State::Sz)
271 return false;
272
273 return true;
274 }
275
276 void RTLIL::AttrObject::set_bool_attribute(RTLIL::IdString id, bool value)
277 {
278 if (value)
279 attributes[id] = RTLIL::Const(1);
280 else
281 attributes.erase(id);
282 }
283
284 bool RTLIL::AttrObject::get_bool_attribute(RTLIL::IdString id) const
285 {
286 const auto it = attributes.find(id);
287 if (it == attributes.end())
288 return false;
289 return it->second.as_bool();
290 }
291
292 void RTLIL::AttrObject::set_strpool_attribute(RTLIL::IdString id, const pool<string> &data)
293 {
294 string attrval;
295 for (const auto &s : data) {
296 if (!attrval.empty())
297 attrval += "|";
298 attrval += s;
299 }
300 attributes[id] = RTLIL::Const(attrval);
301 }
302
303 void RTLIL::AttrObject::add_strpool_attribute(RTLIL::IdString id, const pool<string> &data)
304 {
305 pool<string> union_data = get_strpool_attribute(id);
306 union_data.insert(data.begin(), data.end());
307 if (!union_data.empty())
308 set_strpool_attribute(id, union_data);
309 }
310
311 pool<string> RTLIL::AttrObject::get_strpool_attribute(RTLIL::IdString id) const
312 {
313 pool<string> data;
314 if (attributes.count(id) != 0)
315 for (auto s : split_tokens(attributes.at(id).decode_string(), "|"))
316 data.insert(s);
317 return data;
318 }
319
320 void RTLIL::AttrObject::set_src_attribute(const std::string &src)
321 {
322 if (src.empty())
323 attributes.erase(ID::src);
324 else
325 attributes[ID::src] = src;
326 }
327
328 std::string RTLIL::AttrObject::get_src_attribute() const
329 {
330 std::string src;
331 const auto it = attributes.find(ID::src);
332 if (it != attributes.end())
333 src = it->second.decode_string();
334 return src;
335 }
336
337 bool RTLIL::Selection::selected_module(RTLIL::IdString mod_name) const
338 {
339 if (full_selection)
340 return true;
341 if (selected_modules.count(mod_name) > 0)
342 return true;
343 if (selected_members.count(mod_name) > 0)
344 return true;
345 return false;
346 }
347
348 bool RTLIL::Selection::selected_whole_module(RTLIL::IdString mod_name) const
349 {
350 if (full_selection)
351 return true;
352 if (selected_modules.count(mod_name) > 0)
353 return true;
354 return false;
355 }
356
357 bool RTLIL::Selection::selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const
358 {
359 if (full_selection)
360 return true;
361 if (selected_modules.count(mod_name) > 0)
362 return true;
363 if (selected_members.count(mod_name) > 0)
364 if (selected_members.at(mod_name).count(memb_name) > 0)
365 return true;
366 return false;
367 }
368
369 void RTLIL::Selection::optimize(RTLIL::Design *design)
370 {
371 if (full_selection) {
372 selected_modules.clear();
373 selected_members.clear();
374 return;
375 }
376
377 std::vector<RTLIL::IdString> del_list, add_list;
378
379 del_list.clear();
380 for (auto mod_name : selected_modules) {
381 if (design->modules_.count(mod_name) == 0)
382 del_list.push_back(mod_name);
383 selected_members.erase(mod_name);
384 }
385 for (auto mod_name : del_list)
386 selected_modules.erase(mod_name);
387
388 del_list.clear();
389 for (auto &it : selected_members)
390 if (design->modules_.count(it.first) == 0)
391 del_list.push_back(it.first);
392 for (auto mod_name : del_list)
393 selected_members.erase(mod_name);
394
395 for (auto &it : selected_members) {
396 del_list.clear();
397 for (auto memb_name : it.second)
398 if (design->modules_[it.first]->count_id(memb_name) == 0)
399 del_list.push_back(memb_name);
400 for (auto memb_name : del_list)
401 it.second.erase(memb_name);
402 }
403
404 del_list.clear();
405 add_list.clear();
406 for (auto &it : selected_members)
407 if (it.second.size() == 0)
408 del_list.push_back(it.first);
409 else if (it.second.size() == design->modules_[it.first]->wires_.size() + design->modules_[it.first]->memories.size() +
410 design->modules_[it.first]->cells_.size() + design->modules_[it.first]->processes.size())
411 add_list.push_back(it.first);
412 for (auto mod_name : del_list)
413 selected_members.erase(mod_name);
414 for (auto mod_name : add_list) {
415 selected_members.erase(mod_name);
416 selected_modules.insert(mod_name);
417 }
418
419 if (selected_modules.size() == design->modules_.size()) {
420 full_selection = true;
421 selected_modules.clear();
422 selected_members.clear();
423 }
424 }
425
426 RTLIL::Design::Design()
427 : verilog_defines (new define_map_t)
428 {
429 static unsigned int hashidx_count = 123456789;
430 hashidx_count = mkhash_xorshift(hashidx_count);
431 hashidx_ = hashidx_count;
432
433 refcount_modules_ = 0;
434 selection_stack.push_back(RTLIL::Selection());
435
436 #ifdef WITH_PYTHON
437 RTLIL::Design::get_all_designs()->insert(std::pair<unsigned int, RTLIL::Design*>(hashidx_, this));
438 #endif
439 }
440
441 RTLIL::Design::~Design()
442 {
443 for (auto it = modules_.begin(); it != modules_.end(); ++it)
444 delete it->second;
445 for (auto n : verilog_packages)
446 delete n;
447 for (auto n : verilog_globals)
448 delete n;
449 #ifdef WITH_PYTHON
450 RTLIL::Design::get_all_designs()->erase(hashidx_);
451 #endif
452 }
453
454 #ifdef WITH_PYTHON
455 static std::map<unsigned int, RTLIL::Design*> all_designs;
456 std::map<unsigned int, RTLIL::Design*> *RTLIL::Design::get_all_designs(void)
457 {
458 return &all_designs;
459 }
460 #endif
461
462 RTLIL::ObjRange<RTLIL::Module*> RTLIL::Design::modules()
463 {
464 return RTLIL::ObjRange<RTLIL::Module*>(&modules_, &refcount_modules_);
465 }
466
467 RTLIL::Module *RTLIL::Design::module(RTLIL::IdString name)
468 {
469 return modules_.count(name) ? modules_.at(name) : NULL;
470 }
471
472 RTLIL::Module *RTLIL::Design::top_module()
473 {
474 RTLIL::Module *module = nullptr;
475 int module_count = 0;
476
477 for (auto mod : selected_modules()) {
478 if (mod->get_bool_attribute(ID::top))
479 return mod;
480 module_count++;
481 module = mod;
482 }
483
484 return module_count == 1 ? module : nullptr;
485 }
486
487 void RTLIL::Design::add(RTLIL::Module *module)
488 {
489 log_assert(modules_.count(module->name) == 0);
490 log_assert(refcount_modules_ == 0);
491 modules_[module->name] = module;
492 module->design = this;
493
494 for (auto mon : monitors)
495 mon->notify_module_add(module);
496
497 if (yosys_xtrace) {
498 log("#X# New Module: %s\n", log_id(module));
499 log_backtrace("-X- ", yosys_xtrace-1);
500 }
501 }
502
503 RTLIL::Module *RTLIL::Design::addModule(RTLIL::IdString name)
504 {
505 log_assert(modules_.count(name) == 0);
506 log_assert(refcount_modules_ == 0);
507
508 RTLIL::Module *module = new RTLIL::Module;
509 modules_[name] = module;
510 module->design = this;
511 module->name = name;
512
513 for (auto mon : monitors)
514 mon->notify_module_add(module);
515
516 if (yosys_xtrace) {
517 log("#X# New Module: %s\n", log_id(module));
518 log_backtrace("-X- ", yosys_xtrace-1);
519 }
520
521 return module;
522 }
523
524 void RTLIL::Design::scratchpad_unset(const std::string &varname)
525 {
526 scratchpad.erase(varname);
527 }
528
529 void RTLIL::Design::scratchpad_set_int(const std::string &varname, int value)
530 {
531 scratchpad[varname] = stringf("%d", value);
532 }
533
534 void RTLIL::Design::scratchpad_set_bool(const std::string &varname, bool value)
535 {
536 scratchpad[varname] = value ? "true" : "false";
537 }
538
539 void RTLIL::Design::scratchpad_set_string(const std::string &varname, std::string value)
540 {
541 scratchpad[varname] = std::move(value);
542 }
543
544 int RTLIL::Design::scratchpad_get_int(const std::string &varname, int default_value) const
545 {
546 auto it = scratchpad.find(varname);
547 if (it == scratchpad.end())
548 return default_value;
549
550 const std::string &str = it->second;
551
552 if (str == "0" || str == "false")
553 return 0;
554
555 if (str == "1" || str == "true")
556 return 1;
557
558 char *endptr = nullptr;
559 long int parsed_value = strtol(str.c_str(), &endptr, 10);
560 return *endptr ? default_value : parsed_value;
561 }
562
563 bool RTLIL::Design::scratchpad_get_bool(const std::string &varname, bool default_value) const
564 {
565 auto it = scratchpad.find(varname);
566 if (it == scratchpad.end())
567 return default_value;
568
569 const std::string &str = it->second;
570
571 if (str == "0" || str == "false")
572 return false;
573
574 if (str == "1" || str == "true")
575 return true;
576
577 return default_value;
578 }
579
580 std::string RTLIL::Design::scratchpad_get_string(const std::string &varname, const std::string &default_value) const
581 {
582 auto it = scratchpad.find(varname);
583 if (it == scratchpad.end())
584 return default_value;
585
586 return it->second;
587 }
588
589 void RTLIL::Design::remove(RTLIL::Module *module)
590 {
591 for (auto mon : monitors)
592 mon->notify_module_del(module);
593
594 if (yosys_xtrace) {
595 log("#X# Remove Module: %s\n", log_id(module));
596 log_backtrace("-X- ", yosys_xtrace-1);
597 }
598
599 log_assert(modules_.at(module->name) == module);
600 log_assert(refcount_modules_ == 0);
601 modules_.erase(module->name);
602 delete module;
603 }
604
605 void RTLIL::Design::rename(RTLIL::Module *module, RTLIL::IdString new_name)
606 {
607 modules_.erase(module->name);
608 module->name = new_name;
609 add(module);
610 }
611
612 void RTLIL::Design::sort()
613 {
614 scratchpad.sort();
615 modules_.sort(sort_by_id_str());
616 for (auto &it : modules_)
617 it.second->sort();
618 }
619
620 void RTLIL::Design::check()
621 {
622 #ifndef NDEBUG
623 for (auto &it : modules_) {
624 log_assert(this == it.second->design);
625 log_assert(it.first == it.second->name);
626 log_assert(!it.first.empty());
627 it.second->check();
628 }
629 #endif
630 }
631
632 void RTLIL::Design::optimize()
633 {
634 for (auto &it : modules_)
635 it.second->optimize();
636 for (auto &it : selection_stack)
637 it.optimize(this);
638 for (auto &it : selection_vars)
639 it.second.optimize(this);
640 }
641
642 bool RTLIL::Design::selected_module(RTLIL::IdString mod_name) const
643 {
644 if (!selected_active_module.empty() && mod_name != selected_active_module)
645 return false;
646 if (selection_stack.size() == 0)
647 return true;
648 return selection_stack.back().selected_module(mod_name);
649 }
650
651 bool RTLIL::Design::selected_whole_module(RTLIL::IdString mod_name) const
652 {
653 if (!selected_active_module.empty() && mod_name != selected_active_module)
654 return false;
655 if (selection_stack.size() == 0)
656 return true;
657 return selection_stack.back().selected_whole_module(mod_name);
658 }
659
660 bool RTLIL::Design::selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const
661 {
662 if (!selected_active_module.empty() && mod_name != selected_active_module)
663 return false;
664 if (selection_stack.size() == 0)
665 return true;
666 return selection_stack.back().selected_member(mod_name, memb_name);
667 }
668
669 bool RTLIL::Design::selected_module(RTLIL::Module *mod) const
670 {
671 return selected_module(mod->name);
672 }
673
674 bool RTLIL::Design::selected_whole_module(RTLIL::Module *mod) const
675 {
676 return selected_whole_module(mod->name);
677 }
678
679 std::vector<RTLIL::Module*> RTLIL::Design::selected_modules() const
680 {
681 std::vector<RTLIL::Module*> result;
682 result.reserve(modules_.size());
683 for (auto &it : modules_)
684 if (selected_module(it.first) && !it.second->get_blackbox_attribute())
685 result.push_back(it.second);
686 return result;
687 }
688
689 std::vector<RTLIL::Module*> RTLIL::Design::selected_whole_modules() const
690 {
691 std::vector<RTLIL::Module*> result;
692 result.reserve(modules_.size());
693 for (auto &it : modules_)
694 if (selected_whole_module(it.first) && !it.second->get_blackbox_attribute())
695 result.push_back(it.second);
696 return result;
697 }
698
699 std::vector<RTLIL::Module*> RTLIL::Design::selected_whole_modules_warn() const
700 {
701 std::vector<RTLIL::Module*> result;
702 result.reserve(modules_.size());
703 for (auto &it : modules_)
704 if (it.second->get_blackbox_attribute())
705 continue;
706 else if (selected_whole_module(it.first))
707 result.push_back(it.second);
708 else if (selected_module(it.first))
709 log_warning("Ignoring partially selected module %s.\n", log_id(it.first));
710 return result;
711 }
712
713 RTLIL::Module::Module()
714 {
715 static unsigned int hashidx_count = 123456789;
716 hashidx_count = mkhash_xorshift(hashidx_count);
717 hashidx_ = hashidx_count;
718
719 design = nullptr;
720 refcount_wires_ = 0;
721 refcount_cells_ = 0;
722
723 #ifdef WITH_PYTHON
724 RTLIL::Module::get_all_modules()->insert(std::pair<unsigned int, RTLIL::Module*>(hashidx_, this));
725 #endif
726 }
727
728 RTLIL::Module::~Module()
729 {
730 for (auto it = wires_.begin(); it != wires_.end(); ++it)
731 delete it->second;
732 for (auto it = memories.begin(); it != memories.end(); ++it)
733 delete it->second;
734 for (auto it = cells_.begin(); it != cells_.end(); ++it)
735 delete it->second;
736 for (auto it = processes.begin(); it != processes.end(); ++it)
737 delete it->second;
738 #ifdef WITH_PYTHON
739 RTLIL::Module::get_all_modules()->erase(hashidx_);
740 #endif
741 }
742
743 #ifdef WITH_PYTHON
744 static std::map<unsigned int, RTLIL::Module*> all_modules;
745 std::map<unsigned int, RTLIL::Module*> *RTLIL::Module::get_all_modules(void)
746 {
747 return &all_modules;
748 }
749 #endif
750
751 void RTLIL::Module::makeblackbox()
752 {
753 pool<RTLIL::Wire*> delwires;
754
755 for (auto it = wires_.begin(); it != wires_.end(); ++it)
756 if (!it->second->port_input && !it->second->port_output)
757 delwires.insert(it->second);
758
759 for (auto it = memories.begin(); it != memories.end(); ++it)
760 delete it->second;
761 memories.clear();
762
763 for (auto it = cells_.begin(); it != cells_.end(); ++it)
764 delete it->second;
765 cells_.clear();
766
767 for (auto it = processes.begin(); it != processes.end(); ++it)
768 delete it->second;
769 processes.clear();
770
771 remove(delwires);
772 set_bool_attribute(ID::blackbox);
773 }
774
775 void RTLIL::Module::reprocess_module(RTLIL::Design *, const dict<RTLIL::IdString, RTLIL::Module *> &)
776 {
777 log_error("Cannot reprocess_module module `%s' !\n", id2cstr(name));
778 }
779
780 RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, const dict<RTLIL::IdString, RTLIL::Const> &, bool mayfail)
781 {
782 if (mayfail)
783 return RTLIL::IdString();
784 log_error("Module `%s' is used with parameters but is not parametric!\n", id2cstr(name));
785 }
786
787
788 RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, const dict<RTLIL::IdString, RTLIL::Const> &, const dict<RTLIL::IdString, RTLIL::Module*> &, const dict<RTLIL::IdString, RTLIL::IdString> &, bool mayfail)
789 {
790 if (mayfail)
791 return RTLIL::IdString();
792 log_error("Module `%s' is used with parameters but is not parametric!\n", id2cstr(name));
793 }
794
795 size_t RTLIL::Module::count_id(RTLIL::IdString id)
796 {
797 return wires_.count(id) + memories.count(id) + cells_.count(id) + processes.count(id);
798 }
799
800 #ifndef NDEBUG
801 namespace {
802 struct InternalCellChecker
803 {
804 RTLIL::Module *module;
805 RTLIL::Cell *cell;
806 pool<RTLIL::IdString> expected_params, expected_ports;
807
808 InternalCellChecker(RTLIL::Module *module, RTLIL::Cell *cell) : module(module), cell(cell) { }
809
810 void error(int linenr)
811 {
812 std::stringstream buf;
813 ILANG_BACKEND::dump_cell(buf, " ", cell);
814
815 log_error("Found error in internal cell %s%s%s (%s) at %s:%d:\n%s",
816 module ? module->name.c_str() : "", module ? "." : "",
817 cell->name.c_str(), cell->type.c_str(), __FILE__, linenr, buf.str().c_str());
818 }
819
820 int param(RTLIL::IdString name)
821 {
822 auto it = cell->parameters.find(name);
823 if (it == cell->parameters.end())
824 error(__LINE__);
825 expected_params.insert(name);
826 return it->second.as_int();
827 }
828
829 int param_bool(RTLIL::IdString name)
830 {
831 int v = param(name);
832 if (GetSize(cell->parameters.at(name)) > 32)
833 error(__LINE__);
834 if (v != 0 && v != 1)
835 error(__LINE__);
836 return v;
837 }
838
839 int param_bool(RTLIL::IdString name, bool expected)
840 {
841 int v = param_bool(name);
842 if (v != expected)
843 error(__LINE__);
844 return v;
845 }
846
847 void param_bits(RTLIL::IdString name, int width)
848 {
849 param(name);
850 if (GetSize(cell->parameters.at(name).bits) != width)
851 error(__LINE__);
852 }
853
854 void port(RTLIL::IdString name, int width)
855 {
856 auto it = cell->connections_.find(name);
857 if (it == cell->connections_.end())
858 error(__LINE__);
859 if (GetSize(it->second) != width)
860 error(__LINE__);
861 expected_ports.insert(name);
862 }
863
864 void check_expected(bool check_matched_sign = false)
865 {
866 for (auto &para : cell->parameters)
867 if (expected_params.count(para.first) == 0)
868 error(__LINE__);
869 for (auto &conn : cell->connections())
870 if (expected_ports.count(conn.first) == 0)
871 error(__LINE__);
872
873 if (check_matched_sign) {
874 log_assert(expected_params.count(ID::A_SIGNED) != 0 && expected_params.count(ID::B_SIGNED) != 0);
875 bool a_is_signed = cell->parameters.at(ID::A_SIGNED).as_bool();
876 bool b_is_signed = cell->parameters.at(ID::B_SIGNED).as_bool();
877 if (a_is_signed != b_is_signed)
878 error(__LINE__);
879 }
880 }
881
882 void check()
883 {
884 if (!cell->type.begins_with("$") || cell->type.begins_with("$__") || cell->type.begins_with("$paramod") || cell->type.begins_with("$fmcombine") ||
885 cell->type.begins_with("$verific$") || cell->type.begins_with("$array:") || cell->type.begins_with("$extern:"))
886 return;
887
888 if (cell->type.in(ID($not), ID($pos), ID($neg))) {
889 param_bool(ID::A_SIGNED);
890 port(ID::A, param(ID::A_WIDTH));
891 port(ID::Y, param(ID::Y_WIDTH));
892 check_expected();
893 return;
894 }
895
896 if (cell->type.in(ID($and), ID($or), ID($xor), ID($xnor))) {
897 param_bool(ID::A_SIGNED);
898 param_bool(ID::B_SIGNED);
899 port(ID::A, param(ID::A_WIDTH));
900 port(ID::B, param(ID::B_WIDTH));
901 port(ID::Y, param(ID::Y_WIDTH));
902 check_expected(true);
903 return;
904 }
905
906 if (cell->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor), ID($reduce_bool))) {
907 param_bool(ID::A_SIGNED);
908 port(ID::A, param(ID::A_WIDTH));
909 port(ID::Y, param(ID::Y_WIDTH));
910 check_expected();
911 return;
912 }
913
914 if (cell->type.in(ID($shl), ID($shr), ID($sshl), ID($sshr))) {
915 param_bool(ID::A_SIGNED);
916 param_bool(ID::B_SIGNED, /*expected=*/false);
917 port(ID::A, param(ID::A_WIDTH));
918 port(ID::B, param(ID::B_WIDTH));
919 port(ID::Y, param(ID::Y_WIDTH));
920 check_expected(/*check_matched_sign=*/false);
921 return;
922 }
923
924 if (cell->type.in(ID($shift), ID($shiftx))) {
925 param_bool(ID::A_SIGNED);
926 param_bool(ID::B_SIGNED);
927 port(ID::A, param(ID::A_WIDTH));
928 port(ID::B, param(ID::B_WIDTH));
929 port(ID::Y, param(ID::Y_WIDTH));
930 check_expected(/*check_matched_sign=*/false);
931 return;
932 }
933
934 if (cell->type.in(ID($lt), ID($le), ID($eq), ID($ne), ID($eqx), ID($nex), ID($ge), ID($gt))) {
935 param_bool(ID::A_SIGNED);
936 param_bool(ID::B_SIGNED);
937 port(ID::A, param(ID::A_WIDTH));
938 port(ID::B, param(ID::B_WIDTH));
939 port(ID::Y, param(ID::Y_WIDTH));
940 check_expected(true);
941 return;
942 }
943
944 if (cell->type.in(ID($add), ID($sub), ID($mul), ID($div), ID($mod), ID($pow))) {
945 param_bool(ID::A_SIGNED);
946 param_bool(ID::B_SIGNED);
947 port(ID::A, param(ID::A_WIDTH));
948 port(ID::B, param(ID::B_WIDTH));
949 port(ID::Y, param(ID::Y_WIDTH));
950 check_expected(cell->type != ID($pow));
951 return;
952 }
953
954 if (cell->type == ID($fa)) {
955 port(ID::A, param(ID::WIDTH));
956 port(ID::B, param(ID::WIDTH));
957 port(ID::C, param(ID::WIDTH));
958 port(ID::X, param(ID::WIDTH));
959 port(ID::Y, param(ID::WIDTH));
960 check_expected();
961 return;
962 }
963
964 if (cell->type == ID($lcu)) {
965 port(ID::P, param(ID::WIDTH));
966 port(ID::G, param(ID::WIDTH));
967 port(ID::CI, 1);
968 port(ID::CO, param(ID::WIDTH));
969 check_expected();
970 return;
971 }
972
973 if (cell->type == ID($alu)) {
974 param_bool(ID::A_SIGNED);
975 param_bool(ID::B_SIGNED);
976 port(ID::A, param(ID::A_WIDTH));
977 port(ID::B, param(ID::B_WIDTH));
978 port(ID::CI, 1);
979 port(ID::BI, 1);
980 port(ID::X, param(ID::Y_WIDTH));
981 port(ID::Y, param(ID::Y_WIDTH));
982 port(ID::CO, param(ID::Y_WIDTH));
983 check_expected(true);
984 return;
985 }
986
987 if (cell->type == ID($macc)) {
988 param(ID::CONFIG);
989 param(ID::CONFIG_WIDTH);
990 port(ID::A, param(ID::A_WIDTH));
991 port(ID::B, param(ID::B_WIDTH));
992 port(ID::Y, param(ID::Y_WIDTH));
993 check_expected();
994 Macc().from_cell(cell);
995 return;
996 }
997
998 if (cell->type == ID($logic_not)) {
999 param_bool(ID::A_SIGNED);
1000 port(ID::A, param(ID::A_WIDTH));
1001 port(ID::Y, param(ID::Y_WIDTH));
1002 check_expected();
1003 return;
1004 }
1005
1006 if (cell->type.in(ID($logic_and), ID($logic_or))) {
1007 param_bool(ID::A_SIGNED);
1008 param_bool(ID::B_SIGNED);
1009 port(ID::A, param(ID::A_WIDTH));
1010 port(ID::B, param(ID::B_WIDTH));
1011 port(ID::Y, param(ID::Y_WIDTH));
1012 check_expected(/*check_matched_sign=*/false);
1013 return;
1014 }
1015
1016 if (cell->type == ID($slice)) {
1017 param(ID::OFFSET);
1018 port(ID::A, param(ID::A_WIDTH));
1019 port(ID::Y, param(ID::Y_WIDTH));
1020 if (param(ID::OFFSET) + param(ID::Y_WIDTH) > param(ID::A_WIDTH))
1021 error(__LINE__);
1022 check_expected();
1023 return;
1024 }
1025
1026 if (cell->type == ID($concat)) {
1027 port(ID::A, param(ID::A_WIDTH));
1028 port(ID::B, param(ID::B_WIDTH));
1029 port(ID::Y, param(ID::A_WIDTH) + param(ID::B_WIDTH));
1030 check_expected();
1031 return;
1032 }
1033
1034 if (cell->type == ID($mux)) {
1035 port(ID::A, param(ID::WIDTH));
1036 port(ID::B, param(ID::WIDTH));
1037 port(ID::S, 1);
1038 port(ID::Y, param(ID::WIDTH));
1039 check_expected();
1040 return;
1041 }
1042
1043 if (cell->type == ID($pmux)) {
1044 port(ID::A, param(ID::WIDTH));
1045 port(ID::B, param(ID::WIDTH) * param(ID::S_WIDTH));
1046 port(ID::S, param(ID::S_WIDTH));
1047 port(ID::Y, param(ID::WIDTH));
1048 check_expected();
1049 return;
1050 }
1051
1052 if (cell->type == ID($lut)) {
1053 param(ID::LUT);
1054 port(ID::A, param(ID::WIDTH));
1055 port(ID::Y, 1);
1056 check_expected();
1057 return;
1058 }
1059
1060 if (cell->type == ID($sop)) {
1061 param(ID::DEPTH);
1062 param(ID::TABLE);
1063 port(ID::A, param(ID::WIDTH));
1064 port(ID::Y, 1);
1065 check_expected();
1066 return;
1067 }
1068
1069 if (cell->type == ID($sr)) {
1070 param_bool(ID::SET_POLARITY);
1071 param_bool(ID::CLR_POLARITY);
1072 port(ID::SET, param(ID::WIDTH));
1073 port(ID::CLR, param(ID::WIDTH));
1074 port(ID::Q, param(ID::WIDTH));
1075 check_expected();
1076 return;
1077 }
1078
1079 if (cell->type == ID($ff)) {
1080 port(ID::D, param(ID::WIDTH));
1081 port(ID::Q, param(ID::WIDTH));
1082 check_expected();
1083 return;
1084 }
1085
1086 if (cell->type == ID($dff)) {
1087 param_bool(ID::CLK_POLARITY);
1088 port(ID::CLK, 1);
1089 port(ID::D, param(ID::WIDTH));
1090 port(ID::Q, param(ID::WIDTH));
1091 check_expected();
1092 return;
1093 }
1094
1095 if (cell->type == ID($dffe)) {
1096 param_bool(ID::CLK_POLARITY);
1097 param_bool(ID::EN_POLARITY);
1098 port(ID::CLK, 1);
1099 port(ID::EN, 1);
1100 port(ID::D, param(ID::WIDTH));
1101 port(ID::Q, param(ID::WIDTH));
1102 check_expected();
1103 return;
1104 }
1105
1106 if (cell->type == ID($dffsr)) {
1107 param_bool(ID::CLK_POLARITY);
1108 param_bool(ID::SET_POLARITY);
1109 param_bool(ID::CLR_POLARITY);
1110 port(ID::CLK, 1);
1111 port(ID::SET, param(ID::WIDTH));
1112 port(ID::CLR, param(ID::WIDTH));
1113 port(ID::D, param(ID::WIDTH));
1114 port(ID::Q, param(ID::WIDTH));
1115 check_expected();
1116 return;
1117 }
1118
1119 if (cell->type == ID($adff)) {
1120 param_bool(ID::CLK_POLARITY);
1121 param_bool(ID::ARST_POLARITY);
1122 param_bits(ID::ARST_VALUE, param(ID::WIDTH));
1123 port(ID::CLK, 1);
1124 port(ID::ARST, 1);
1125 port(ID::D, param(ID::WIDTH));
1126 port(ID::Q, param(ID::WIDTH));
1127 check_expected();
1128 return;
1129 }
1130
1131 if (cell->type == ID($dlatch)) {
1132 param_bool(ID::EN_POLARITY);
1133 port(ID::EN, 1);
1134 port(ID::D, param(ID::WIDTH));
1135 port(ID::Q, param(ID::WIDTH));
1136 check_expected();
1137 return;
1138 }
1139
1140 if (cell->type == ID($dlatchsr)) {
1141 param_bool(ID::EN_POLARITY);
1142 param_bool(ID::SET_POLARITY);
1143 param_bool(ID::CLR_POLARITY);
1144 port(ID::EN, 1);
1145 port(ID::SET, param(ID::WIDTH));
1146 port(ID::CLR, param(ID::WIDTH));
1147 port(ID::D, param(ID::WIDTH));
1148 port(ID::Q, param(ID::WIDTH));
1149 check_expected();
1150 return;
1151 }
1152
1153 if (cell->type == ID($fsm)) {
1154 param(ID::NAME);
1155 param_bool(ID::CLK_POLARITY);
1156 param_bool(ID::ARST_POLARITY);
1157 param(ID::STATE_BITS);
1158 param(ID::STATE_NUM);
1159 param(ID::STATE_NUM_LOG2);
1160 param(ID::STATE_RST);
1161 param_bits(ID::STATE_TABLE, param(ID::STATE_BITS) * param(ID::STATE_NUM));
1162 param(ID::TRANS_NUM);
1163 param_bits(ID::TRANS_TABLE, param(ID::TRANS_NUM) * (2*param(ID::STATE_NUM_LOG2) + param(ID::CTRL_IN_WIDTH) + param(ID::CTRL_OUT_WIDTH)));
1164 port(ID::CLK, 1);
1165 port(ID::ARST, 1);
1166 port(ID::CTRL_IN, param(ID::CTRL_IN_WIDTH));
1167 port(ID::CTRL_OUT, param(ID::CTRL_OUT_WIDTH));
1168 check_expected();
1169 return;
1170 }
1171
1172 if (cell->type == ID($memrd)) {
1173 param(ID::MEMID);
1174 param_bool(ID::CLK_ENABLE);
1175 param_bool(ID::CLK_POLARITY);
1176 param_bool(ID::TRANSPARENT);
1177 port(ID::CLK, 1);
1178 port(ID::EN, 1);
1179 port(ID::ADDR, param(ID::ABITS));
1180 port(ID::DATA, param(ID::WIDTH));
1181 check_expected();
1182 return;
1183 }
1184
1185 if (cell->type == ID($memwr)) {
1186 param(ID::MEMID);
1187 param_bool(ID::CLK_ENABLE);
1188 param_bool(ID::CLK_POLARITY);
1189 param(ID::PRIORITY);
1190 port(ID::CLK, 1);
1191 port(ID::EN, param(ID::WIDTH));
1192 port(ID::ADDR, param(ID::ABITS));
1193 port(ID::DATA, param(ID::WIDTH));
1194 check_expected();
1195 return;
1196 }
1197
1198 if (cell->type == ID($meminit)) {
1199 param(ID::MEMID);
1200 param(ID::PRIORITY);
1201 port(ID::ADDR, param(ID::ABITS));
1202 port(ID::DATA, param(ID::WIDTH) * param(ID::WORDS));
1203 check_expected();
1204 return;
1205 }
1206
1207 if (cell->type == ID($mem)) {
1208 param(ID::MEMID);
1209 param(ID::SIZE);
1210 param(ID::OFFSET);
1211 param(ID::INIT);
1212 param_bits(ID::RD_CLK_ENABLE, max(1, param(ID::RD_PORTS)));
1213 param_bits(ID::RD_CLK_POLARITY, max(1, param(ID::RD_PORTS)));
1214 param_bits(ID::RD_TRANSPARENT, max(1, param(ID::RD_PORTS)));
1215 param_bits(ID::WR_CLK_ENABLE, max(1, param(ID::WR_PORTS)));
1216 param_bits(ID::WR_CLK_POLARITY, max(1, param(ID::WR_PORTS)));
1217 port(ID::RD_CLK, param(ID::RD_PORTS));
1218 port(ID::RD_EN, param(ID::RD_PORTS));
1219 port(ID::RD_ADDR, param(ID::RD_PORTS) * param(ID::ABITS));
1220 port(ID::RD_DATA, param(ID::RD_PORTS) * param(ID::WIDTH));
1221 port(ID::WR_CLK, param(ID::WR_PORTS));
1222 port(ID::WR_EN, param(ID::WR_PORTS) * param(ID::WIDTH));
1223 port(ID::WR_ADDR, param(ID::WR_PORTS) * param(ID::ABITS));
1224 port(ID::WR_DATA, param(ID::WR_PORTS) * param(ID::WIDTH));
1225 check_expected();
1226 return;
1227 }
1228
1229 if (cell->type == ID($tribuf)) {
1230 port(ID::A, param(ID::WIDTH));
1231 port(ID::Y, param(ID::WIDTH));
1232 port(ID::EN, 1);
1233 check_expected();
1234 return;
1235 }
1236
1237 if (cell->type.in(ID($assert), ID($assume), ID($live), ID($fair), ID($cover))) {
1238 port(ID::A, 1);
1239 port(ID::EN, 1);
1240 check_expected();
1241 return;
1242 }
1243
1244 if (cell->type == ID($initstate)) {
1245 port(ID::Y, 1);
1246 check_expected();
1247 return;
1248 }
1249
1250 if (cell->type.in(ID($anyconst), ID($anyseq), ID($allconst), ID($allseq))) {
1251 port(ID::Y, param(ID::WIDTH));
1252 check_expected();
1253 return;
1254 }
1255
1256 if (cell->type == ID($equiv)) {
1257 port(ID::A, 1);
1258 port(ID::B, 1);
1259 port(ID::Y, 1);
1260 check_expected();
1261 return;
1262 }
1263
1264 if (cell->type.in(ID($specify2), ID($specify3))) {
1265 param_bool(ID::FULL);
1266 param_bool(ID::SRC_DST_PEN);
1267 param_bool(ID::SRC_DST_POL);
1268 param(ID::T_RISE_MIN);
1269 param(ID::T_RISE_TYP);
1270 param(ID::T_RISE_MAX);
1271 param(ID::T_FALL_MIN);
1272 param(ID::T_FALL_TYP);
1273 param(ID::T_FALL_MAX);
1274 port(ID::EN, 1);
1275 port(ID::SRC, param(ID::SRC_WIDTH));
1276 port(ID::DST, param(ID::DST_WIDTH));
1277 if (cell->type == ID($specify3)) {
1278 param_bool(ID::EDGE_EN);
1279 param_bool(ID::EDGE_POL);
1280 param_bool(ID::DAT_DST_PEN);
1281 param_bool(ID::DAT_DST_POL);
1282 port(ID::DAT, param(ID::DST_WIDTH));
1283 }
1284 check_expected();
1285 return;
1286 }
1287
1288 if (cell->type == ID($specrule)) {
1289 param(ID::TYPE);
1290 param_bool(ID::SRC_PEN);
1291 param_bool(ID::SRC_POL);
1292 param_bool(ID::DST_PEN);
1293 param_bool(ID::DST_POL);
1294 param(ID::T_LIMIT_MIN);
1295 param(ID::T_LIMIT_TYP);
1296 param(ID::T_LIMIT_MAX);
1297 param(ID::T_LIMIT2_MIN);
1298 param(ID::T_LIMIT2_TYP);
1299 param(ID::T_LIMIT2_MAX);
1300 port(ID::SRC_EN, 1);
1301 port(ID::DST_EN, 1);
1302 port(ID::SRC, param(ID::SRC_WIDTH));
1303 port(ID::DST, param(ID::DST_WIDTH));
1304 check_expected();
1305 return;
1306 }
1307
1308 if (cell->type == ID($_BUF_)) { port(ID::A,1); port(ID::Y,1); check_expected(); return; }
1309 if (cell->type == ID($_NOT_)) { port(ID::A,1); port(ID::Y,1); check_expected(); return; }
1310 if (cell->type == ID($_AND_)) { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; }
1311 if (cell->type == ID($_NAND_)) { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; }
1312 if (cell->type == ID($_OR_)) { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; }
1313 if (cell->type == ID($_NOR_)) { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; }
1314 if (cell->type == ID($_XOR_)) { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; }
1315 if (cell->type == ID($_XNOR_)) { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; }
1316 if (cell->type == ID($_ANDNOT_)) { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; }
1317 if (cell->type == ID($_ORNOT_)) { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; }
1318 if (cell->type == ID($_MUX_)) { port(ID::A,1); port(ID::B,1); port(ID::S,1); port(ID::Y,1); check_expected(); return; }
1319 if (cell->type == ID($_NMUX_)) { port(ID::A,1); port(ID::B,1); port(ID::S,1); port(ID::Y,1); check_expected(); return; }
1320 if (cell->type == ID($_AOI3_)) { port(ID::A,1); port(ID::B,1); port(ID::C,1); port(ID::Y,1); check_expected(); return; }
1321 if (cell->type == ID($_OAI3_)) { port(ID::A,1); port(ID::B,1); port(ID::C,1); port(ID::Y,1); check_expected(); return; }
1322 if (cell->type == ID($_AOI4_)) { port(ID::A,1); port(ID::B,1); port(ID::C,1); port(ID::D,1); port(ID::Y,1); check_expected(); return; }
1323 if (cell->type == ID($_OAI4_)) { port(ID::A,1); port(ID::B,1); port(ID::C,1); port(ID::D,1); port(ID::Y,1); check_expected(); return; }
1324
1325 if (cell->type == ID($_TBUF_)) { port(ID::A,1); port(ID::Y,1); port(ID::E,1); check_expected(); return; }
1326
1327 if (cell->type == ID($_MUX4_)) { port(ID::A,1); port(ID::B,1); port(ID::C,1); port(ID::D,1); port(ID::S,1); port(ID::T,1); port(ID::Y,1); check_expected(); return; }
1328 if (cell->type == ID($_MUX8_)) { port(ID::A,1); port(ID::B,1); port(ID::C,1); port(ID::D,1); port(ID::E,1); port(ID::F,1); port(ID::G,1); port(ID::H,1); port(ID::S,1); port(ID::T,1); port(ID::U,1); port(ID::Y,1); check_expected(); return; }
1329 if (cell->type == ID($_MUX16_)) { port(ID::A,1); port(ID::B,1); port(ID::C,1); port(ID::D,1); port(ID::E,1); port(ID::F,1); port(ID::G,1); port(ID::H,1); port(ID::I,1); port(ID::J,1); port(ID::K,1); port(ID::L,1); port(ID::M,1); port(ID::N,1); port(ID::O,1); port(ID::P,1); port(ID::S,1); port(ID::T,1); port(ID::U,1); port(ID::V,1); port(ID::Y,1); check_expected(); return; }
1330
1331 if (cell->type == ID($_SR_NN_)) { port(ID::S,1); port(ID::R,1); port(ID::Q,1); check_expected(); return; }
1332 if (cell->type == ID($_SR_NP_)) { port(ID::S,1); port(ID::R,1); port(ID::Q,1); check_expected(); return; }
1333 if (cell->type == ID($_SR_PN_)) { port(ID::S,1); port(ID::R,1); port(ID::Q,1); check_expected(); return; }
1334 if (cell->type == ID($_SR_PP_)) { port(ID::S,1); port(ID::R,1); port(ID::Q,1); check_expected(); return; }
1335
1336 if (cell->type == ID($_FF_)) { port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1337 if (cell->type == ID($_DFF_N_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); check_expected(); return; }
1338 if (cell->type == ID($_DFF_P_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); check_expected(); return; }
1339
1340 if (cell->type == ID($_DFFE_NN_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::E,1); check_expected(); return; }
1341 if (cell->type == ID($_DFFE_NP_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::E,1); check_expected(); return; }
1342 if (cell->type == ID($_DFFE_PN_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::E,1); check_expected(); return; }
1343 if (cell->type == ID($_DFFE_PP_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::E,1); check_expected(); return; }
1344
1345 if (cell->type == ID($_DFF_NN0_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::R,1); check_expected(); return; }
1346 if (cell->type == ID($_DFF_NN1_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::R,1); check_expected(); return; }
1347 if (cell->type == ID($_DFF_NP0_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::R,1); check_expected(); return; }
1348 if (cell->type == ID($_DFF_NP1_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::R,1); check_expected(); return; }
1349 if (cell->type == ID($_DFF_PN0_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::R,1); check_expected(); return; }
1350 if (cell->type == ID($_DFF_PN1_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::R,1); check_expected(); return; }
1351 if (cell->type == ID($_DFF_PP0_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::R,1); check_expected(); return; }
1352 if (cell->type == ID($_DFF_PP1_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::R,1); check_expected(); return; }
1353
1354 if (cell->type == ID($_DFFSR_NNN_)) { port(ID::C,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1355 if (cell->type == ID($_DFFSR_NNP_)) { port(ID::C,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1356 if (cell->type == ID($_DFFSR_NPN_)) { port(ID::C,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1357 if (cell->type == ID($_DFFSR_NPP_)) { port(ID::C,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1358 if (cell->type == ID($_DFFSR_PNN_)) { port(ID::C,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1359 if (cell->type == ID($_DFFSR_PNP_)) { port(ID::C,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1360 if (cell->type == ID($_DFFSR_PPN_)) { port(ID::C,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1361 if (cell->type == ID($_DFFSR_PPP_)) { port(ID::C,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1362
1363 if (cell->type == ID($_DLATCH_N_)) { port(ID::E,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1364 if (cell->type == ID($_DLATCH_P_)) { port(ID::E,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1365
1366 if (cell->type == ID($_DLATCHSR_NNN_)) { port(ID::E,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1367 if (cell->type == ID($_DLATCHSR_NNP_)) { port(ID::E,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1368 if (cell->type == ID($_DLATCHSR_NPN_)) { port(ID::E,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1369 if (cell->type == ID($_DLATCHSR_NPP_)) { port(ID::E,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1370 if (cell->type == ID($_DLATCHSR_PNN_)) { port(ID::E,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1371 if (cell->type == ID($_DLATCHSR_PNP_)) { port(ID::E,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1372 if (cell->type == ID($_DLATCHSR_PPN_)) { port(ID::E,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1373 if (cell->type == ID($_DLATCHSR_PPP_)) { port(ID::E,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1374
1375 error(__LINE__);
1376 }
1377 };
1378 }
1379 #endif
1380
1381 void RTLIL::Module::sort()
1382 {
1383 wires_.sort(sort_by_id_str());
1384 cells_.sort(sort_by_id_str());
1385 avail_parameters.sort(sort_by_id_str());
1386 memories.sort(sort_by_id_str());
1387 processes.sort(sort_by_id_str());
1388 for (auto &it : cells_)
1389 it.second->sort();
1390 for (auto &it : wires_)
1391 it.second->attributes.sort(sort_by_id_str());
1392 for (auto &it : memories)
1393 it.second->attributes.sort(sort_by_id_str());
1394 }
1395
1396 void RTLIL::Module::check()
1397 {
1398 #ifndef NDEBUG
1399 std::vector<bool> ports_declared;
1400 for (auto &it : wires_) {
1401 log_assert(this == it.second->module);
1402 log_assert(it.first == it.second->name);
1403 log_assert(!it.first.empty());
1404 log_assert(it.second->width >= 0);
1405 log_assert(it.second->port_id >= 0);
1406 for (auto &it2 : it.second->attributes)
1407 log_assert(!it2.first.empty());
1408 if (it.second->port_id) {
1409 log_assert(GetSize(ports) >= it.second->port_id);
1410 log_assert(ports.at(it.second->port_id-1) == it.first);
1411 log_assert(it.second->port_input || it.second->port_output);
1412 if (GetSize(ports_declared) < it.second->port_id)
1413 ports_declared.resize(it.second->port_id);
1414 log_assert(ports_declared[it.second->port_id-1] == false);
1415 ports_declared[it.second->port_id-1] = true;
1416 } else
1417 log_assert(!it.second->port_input && !it.second->port_output);
1418 }
1419 for (auto port_declared : ports_declared)
1420 log_assert(port_declared == true);
1421 log_assert(GetSize(ports) == GetSize(ports_declared));
1422
1423 for (auto &it : memories) {
1424 log_assert(it.first == it.second->name);
1425 log_assert(!it.first.empty());
1426 log_assert(it.second->width >= 0);
1427 log_assert(it.second->size >= 0);
1428 for (auto &it2 : it.second->attributes)
1429 log_assert(!it2.first.empty());
1430 }
1431
1432 for (auto &it : cells_) {
1433 log_assert(this == it.second->module);
1434 log_assert(it.first == it.second->name);
1435 log_assert(!it.first.empty());
1436 log_assert(!it.second->type.empty());
1437 for (auto &it2 : it.second->connections()) {
1438 log_assert(!it2.first.empty());
1439 it2.second.check();
1440 }
1441 for (auto &it2 : it.second->attributes)
1442 log_assert(!it2.first.empty());
1443 for (auto &it2 : it.second->parameters)
1444 log_assert(!it2.first.empty());
1445 InternalCellChecker checker(this, it.second);
1446 checker.check();
1447 }
1448
1449 for (auto &it : processes) {
1450 log_assert(it.first == it.second->name);
1451 log_assert(!it.first.empty());
1452 log_assert(it.second->root_case.compare.empty());
1453 std::vector<CaseRule*> all_cases = {&it.second->root_case};
1454 for (size_t i = 0; i < all_cases.size(); i++) {
1455 for (auto &switch_it : all_cases[i]->switches) {
1456 for (auto &case_it : switch_it->cases) {
1457 for (auto &compare_it : case_it->compare) {
1458 log_assert(switch_it->signal.size() == compare_it.size());
1459 }
1460 all_cases.push_back(case_it);
1461 }
1462 }
1463 }
1464 for (auto &sync_it : it.second->syncs) {
1465 switch (sync_it->type) {
1466 case SyncType::ST0:
1467 case SyncType::ST1:
1468 case SyncType::STp:
1469 case SyncType::STn:
1470 case SyncType::STe:
1471 log_assert(!sync_it->signal.empty());
1472 break;
1473 case SyncType::STa:
1474 case SyncType::STg:
1475 case SyncType::STi:
1476 log_assert(sync_it->signal.empty());
1477 break;
1478 }
1479 }
1480 }
1481
1482 for (auto &it : connections_) {
1483 log_assert(it.first.size() == it.second.size());
1484 log_assert(!it.first.has_const());
1485 it.first.check();
1486 it.second.check();
1487 }
1488
1489 for (auto &it : attributes)
1490 log_assert(!it.first.empty());
1491 #endif
1492 }
1493
1494 void RTLIL::Module::optimize()
1495 {
1496 }
1497
1498 void RTLIL::Module::cloneInto(RTLIL::Module *new_mod) const
1499 {
1500 log_assert(new_mod->refcount_wires_ == 0);
1501 log_assert(new_mod->refcount_cells_ == 0);
1502
1503 new_mod->avail_parameters = avail_parameters;
1504
1505 for (auto &conn : connections_)
1506 new_mod->connect(conn);
1507
1508 for (auto &attr : attributes)
1509 new_mod->attributes[attr.first] = attr.second;
1510
1511 for (auto &it : wires_)
1512 new_mod->addWire(it.first, it.second);
1513
1514 for (auto &it : memories)
1515 new_mod->memories[it.first] = new RTLIL::Memory(*it.second);
1516
1517 for (auto &it : cells_)
1518 new_mod->addCell(it.first, it.second);
1519
1520 for (auto &it : processes)
1521 new_mod->processes[it.first] = it.second->clone();
1522
1523 struct RewriteSigSpecWorker
1524 {
1525 RTLIL::Module *mod;
1526 void operator()(RTLIL::SigSpec &sig)
1527 {
1528 sig.pack();
1529 for (auto &c : sig.chunks_)
1530 if (c.wire != NULL)
1531 c.wire = mod->wires_.at(c.wire->name);
1532 }
1533 };
1534
1535 RewriteSigSpecWorker rewriteSigSpecWorker;
1536 rewriteSigSpecWorker.mod = new_mod;
1537 new_mod->rewrite_sigspecs(rewriteSigSpecWorker);
1538 new_mod->fixup_ports();
1539 }
1540
1541 RTLIL::Module *RTLIL::Module::clone() const
1542 {
1543 RTLIL::Module *new_mod = new RTLIL::Module;
1544 new_mod->name = name;
1545 cloneInto(new_mod);
1546 return new_mod;
1547 }
1548
1549 bool RTLIL::Module::has_memories() const
1550 {
1551 return !memories.empty();
1552 }
1553
1554 bool RTLIL::Module::has_processes() const
1555 {
1556 return !processes.empty();
1557 }
1558
1559 bool RTLIL::Module::has_memories_warn() const
1560 {
1561 if (!memories.empty())
1562 log_warning("Ignoring module %s because it contains memories (run 'memory' command first).\n", log_id(this));
1563 return !memories.empty();
1564 }
1565
1566 bool RTLIL::Module::has_processes_warn() const
1567 {
1568 if (!processes.empty())
1569 log_warning("Ignoring module %s because it contains processes (run 'proc' command first).\n", log_id(this));
1570 return !processes.empty();
1571 }
1572
1573 std::vector<RTLIL::Wire*> RTLIL::Module::selected_wires() const
1574 {
1575 std::vector<RTLIL::Wire*> result;
1576 result.reserve(wires_.size());
1577 for (auto &it : wires_)
1578 if (design->selected(this, it.second))
1579 result.push_back(it.second);
1580 return result;
1581 }
1582
1583 std::vector<RTLIL::Cell*> RTLIL::Module::selected_cells() const
1584 {
1585 std::vector<RTLIL::Cell*> result;
1586 result.reserve(cells_.size());
1587 for (auto &it : cells_)
1588 if (design->selected(this, it.second))
1589 result.push_back(it.second);
1590 return result;
1591 }
1592
1593 void RTLIL::Module::add(RTLIL::Wire *wire)
1594 {
1595 log_assert(!wire->name.empty());
1596 log_assert(count_id(wire->name) == 0);
1597 log_assert(refcount_wires_ == 0);
1598 wires_[wire->name] = wire;
1599 wire->module = this;
1600 }
1601
1602 void RTLIL::Module::add(RTLIL::Cell *cell)
1603 {
1604 log_assert(!cell->name.empty());
1605 log_assert(count_id(cell->name) == 0);
1606 log_assert(refcount_cells_ == 0);
1607 cells_[cell->name] = cell;
1608 cell->module = this;
1609 }
1610
1611 void RTLIL::Module::remove(const pool<RTLIL::Wire*> &wires)
1612 {
1613 log_assert(refcount_wires_ == 0);
1614
1615 struct DeleteWireWorker
1616 {
1617 RTLIL::Module *module;
1618 const pool<RTLIL::Wire*> *wires_p;
1619
1620 void operator()(RTLIL::SigSpec &sig) {
1621 sig.pack();
1622 for (auto &c : sig.chunks_)
1623 if (c.wire != NULL && wires_p->count(c.wire)) {
1624 c.wire = module->addWire(NEW_ID, c.width);
1625 c.offset = 0;
1626 }
1627 }
1628
1629 void operator()(RTLIL::SigSpec &lhs, RTLIL::SigSpec &rhs) {
1630 log_assert(GetSize(lhs) == GetSize(rhs));
1631 lhs.unpack();
1632 rhs.unpack();
1633 for (int i = 0; i < GetSize(lhs); i++) {
1634 RTLIL::SigBit &lhs_bit = lhs.bits_[i];
1635 RTLIL::SigBit &rhs_bit = rhs.bits_[i];
1636 if ((lhs_bit.wire != nullptr && wires_p->count(lhs_bit.wire)) || (rhs_bit.wire != nullptr && wires_p->count(rhs_bit.wire))) {
1637 lhs_bit = State::Sx;
1638 rhs_bit = State::Sx;
1639 }
1640 }
1641 }
1642 };
1643
1644 DeleteWireWorker delete_wire_worker;
1645 delete_wire_worker.module = this;
1646 delete_wire_worker.wires_p = &wires;
1647 rewrite_sigspecs2(delete_wire_worker);
1648
1649 for (auto &it : wires) {
1650 log_assert(wires_.count(it->name) != 0);
1651 wires_.erase(it->name);
1652 delete it;
1653 }
1654 }
1655
1656 void RTLIL::Module::remove(RTLIL::Cell *cell)
1657 {
1658 while (!cell->connections_.empty())
1659 cell->unsetPort(cell->connections_.begin()->first);
1660
1661 log_assert(cells_.count(cell->name) != 0);
1662 log_assert(refcount_cells_ == 0);
1663 cells_.erase(cell->name);
1664 delete cell;
1665 }
1666
1667 void RTLIL::Module::rename(RTLIL::Wire *wire, RTLIL::IdString new_name)
1668 {
1669 log_assert(wires_[wire->name] == wire);
1670 log_assert(refcount_wires_ == 0);
1671 wires_.erase(wire->name);
1672 wire->name = new_name;
1673 add(wire);
1674 }
1675
1676 void RTLIL::Module::rename(RTLIL::Cell *cell, RTLIL::IdString new_name)
1677 {
1678 log_assert(cells_[cell->name] == cell);
1679 log_assert(refcount_wires_ == 0);
1680 cells_.erase(cell->name);
1681 cell->name = new_name;
1682 add(cell);
1683 }
1684
1685 void RTLIL::Module::rename(RTLIL::IdString old_name, RTLIL::IdString new_name)
1686 {
1687 log_assert(count_id(old_name) != 0);
1688 if (wires_.count(old_name))
1689 rename(wires_.at(old_name), new_name);
1690 else if (cells_.count(old_name))
1691 rename(cells_.at(old_name), new_name);
1692 else
1693 log_abort();
1694 }
1695
1696 void RTLIL::Module::swap_names(RTLIL::Wire *w1, RTLIL::Wire *w2)
1697 {
1698 log_assert(wires_[w1->name] == w1);
1699 log_assert(wires_[w2->name] == w2);
1700 log_assert(refcount_wires_ == 0);
1701
1702 wires_.erase(w1->name);
1703 wires_.erase(w2->name);
1704
1705 std::swap(w1->name, w2->name);
1706
1707 wires_[w1->name] = w1;
1708 wires_[w2->name] = w2;
1709 }
1710
1711 void RTLIL::Module::swap_names(RTLIL::Cell *c1, RTLIL::Cell *c2)
1712 {
1713 log_assert(cells_[c1->name] == c1);
1714 log_assert(cells_[c2->name] == c2);
1715 log_assert(refcount_cells_ == 0);
1716
1717 cells_.erase(c1->name);
1718 cells_.erase(c2->name);
1719
1720 std::swap(c1->name, c2->name);
1721
1722 cells_[c1->name] = c1;
1723 cells_[c2->name] = c2;
1724 }
1725
1726 RTLIL::IdString RTLIL::Module::uniquify(RTLIL::IdString name)
1727 {
1728 int index = 0;
1729 return uniquify(name, index);
1730 }
1731
1732 RTLIL::IdString RTLIL::Module::uniquify(RTLIL::IdString name, int &index)
1733 {
1734 if (index == 0) {
1735 if (count_id(name) == 0)
1736 return name;
1737 index++;
1738 }
1739
1740 while (1) {
1741 RTLIL::IdString new_name = stringf("%s_%d", name.c_str(), index);
1742 if (count_id(new_name) == 0)
1743 return new_name;
1744 index++;
1745 }
1746 }
1747
1748 static bool fixup_ports_compare(const RTLIL::Wire *a, const RTLIL::Wire *b)
1749 {
1750 if (a->port_id && !b->port_id)
1751 return true;
1752 if (!a->port_id && b->port_id)
1753 return false;
1754
1755 if (a->port_id == b->port_id)
1756 return a->name < b->name;
1757 return a->port_id < b->port_id;
1758 }
1759
1760 void RTLIL::Module::connect(const RTLIL::SigSig &conn)
1761 {
1762 for (auto mon : monitors)
1763 mon->notify_connect(this, conn);
1764
1765 if (design)
1766 for (auto mon : design->monitors)
1767 mon->notify_connect(this, conn);
1768
1769 // ignore all attempts to assign constants to other constants
1770 if (conn.first.has_const()) {
1771 RTLIL::SigSig new_conn;
1772 for (int i = 0; i < GetSize(conn.first); i++)
1773 if (conn.first[i].wire) {
1774 new_conn.first.append(conn.first[i]);
1775 new_conn.second.append(conn.second[i]);
1776 }
1777 if (GetSize(new_conn.first))
1778 connect(new_conn);
1779 return;
1780 }
1781
1782 if (yosys_xtrace) {
1783 log("#X# Connect (SigSig) in %s: %s = %s (%d bits)\n", log_id(this), log_signal(conn.first), log_signal(conn.second), GetSize(conn.first));
1784 log_backtrace("-X- ", yosys_xtrace-1);
1785 }
1786
1787 log_assert(GetSize(conn.first) == GetSize(conn.second));
1788 connections_.push_back(conn);
1789 }
1790
1791 void RTLIL::Module::connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs)
1792 {
1793 connect(RTLIL::SigSig(lhs, rhs));
1794 }
1795
1796 void RTLIL::Module::new_connections(const std::vector<RTLIL::SigSig> &new_conn)
1797 {
1798 for (auto mon : monitors)
1799 mon->notify_connect(this, new_conn);
1800
1801 if (design)
1802 for (auto mon : design->monitors)
1803 mon->notify_connect(this, new_conn);
1804
1805 if (yosys_xtrace) {
1806 log("#X# New connections vector in %s:\n", log_id(this));
1807 for (auto &conn: new_conn)
1808 log("#X# %s = %s (%d bits)\n", log_signal(conn.first), log_signal(conn.second), GetSize(conn.first));
1809 log_backtrace("-X- ", yosys_xtrace-1);
1810 }
1811
1812 connections_ = new_conn;
1813 }
1814
1815 const std::vector<RTLIL::SigSig> &RTLIL::Module::connections() const
1816 {
1817 return connections_;
1818 }
1819
1820 void RTLIL::Module::fixup_ports()
1821 {
1822 std::vector<RTLIL::Wire*> all_ports;
1823
1824 for (auto &w : wires_)
1825 if (w.second->port_input || w.second->port_output)
1826 all_ports.push_back(w.second);
1827 else
1828 w.second->port_id = 0;
1829
1830 std::sort(all_ports.begin(), all_ports.end(), fixup_ports_compare);
1831
1832 ports.clear();
1833 for (size_t i = 0; i < all_ports.size(); i++) {
1834 ports.push_back(all_ports[i]->name);
1835 all_ports[i]->port_id = i+1;
1836 }
1837 }
1838
1839 RTLIL::Wire *RTLIL::Module::addWire(RTLIL::IdString name, int width)
1840 {
1841 RTLIL::Wire *wire = new RTLIL::Wire;
1842 wire->name = name;
1843 wire->width = width;
1844 add(wire);
1845 return wire;
1846 }
1847
1848 RTLIL::Wire *RTLIL::Module::addWire(RTLIL::IdString name, const RTLIL::Wire *other)
1849 {
1850 RTLIL::Wire *wire = addWire(name);
1851 wire->width = other->width;
1852 wire->start_offset = other->start_offset;
1853 wire->port_id = other->port_id;
1854 wire->port_input = other->port_input;
1855 wire->port_output = other->port_output;
1856 wire->upto = other->upto;
1857 wire->attributes = other->attributes;
1858 return wire;
1859 }
1860
1861 RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, RTLIL::IdString type)
1862 {
1863 RTLIL::Cell *cell = new RTLIL::Cell;
1864 cell->name = name;
1865 cell->type = type;
1866 add(cell);
1867 return cell;
1868 }
1869
1870 RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, const RTLIL::Cell *other)
1871 {
1872 RTLIL::Cell *cell = addCell(name, other->type);
1873 cell->connections_ = other->connections_;
1874 cell->parameters = other->parameters;
1875 cell->attributes = other->attributes;
1876 return cell;
1877 }
1878
1879 #define DEF_METHOD(_func, _y_size, _type) \
1880 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed, const std::string &src) { \
1881 RTLIL::Cell *cell = addCell(name, _type); \
1882 cell->parameters[ID::A_SIGNED] = is_signed; \
1883 cell->parameters[ID::A_WIDTH] = sig_a.size(); \
1884 cell->parameters[ID::Y_WIDTH] = sig_y.size(); \
1885 cell->setPort(ID::A, sig_a); \
1886 cell->setPort(ID::Y, sig_y); \
1887 cell->set_src_attribute(src); \
1888 return cell; \
1889 } \
1890 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed, const std::string &src) { \
1891 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
1892 add ## _func(name, sig_a, sig_y, is_signed, src); \
1893 return sig_y; \
1894 }
1895 DEF_METHOD(Not, sig_a.size(), ID($not))
1896 DEF_METHOD(Pos, sig_a.size(), ID($pos))
1897 DEF_METHOD(Neg, sig_a.size(), ID($neg))
1898 DEF_METHOD(ReduceAnd, 1, ID($reduce_and))
1899 DEF_METHOD(ReduceOr, 1, ID($reduce_or))
1900 DEF_METHOD(ReduceXor, 1, ID($reduce_xor))
1901 DEF_METHOD(ReduceXnor, 1, ID($reduce_xnor))
1902 DEF_METHOD(ReduceBool, 1, ID($reduce_bool))
1903 DEF_METHOD(LogicNot, 1, ID($logic_not))
1904 #undef DEF_METHOD
1905
1906 #define DEF_METHOD(_func, _y_size, _type) \
1907 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed, const std::string &src) { \
1908 RTLIL::Cell *cell = addCell(name, _type); \
1909 cell->parameters[ID::A_SIGNED] = is_signed; \
1910 cell->parameters[ID::B_SIGNED] = is_signed; \
1911 cell->parameters[ID::A_WIDTH] = sig_a.size(); \
1912 cell->parameters[ID::B_WIDTH] = sig_b.size(); \
1913 cell->parameters[ID::Y_WIDTH] = sig_y.size(); \
1914 cell->setPort(ID::A, sig_a); \
1915 cell->setPort(ID::B, sig_b); \
1916 cell->setPort(ID::Y, sig_y); \
1917 cell->set_src_attribute(src); \
1918 return cell; \
1919 } \
1920 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed, const std::string &src) { \
1921 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
1922 add ## _func(name, sig_a, sig_b, sig_y, is_signed, src); \
1923 return sig_y; \
1924 }
1925 DEF_METHOD(And, max(sig_a.size(), sig_b.size()), ID($and))
1926 DEF_METHOD(Or, max(sig_a.size(), sig_b.size()), ID($or))
1927 DEF_METHOD(Xor, max(sig_a.size(), sig_b.size()), ID($xor))
1928 DEF_METHOD(Xnor, max(sig_a.size(), sig_b.size()), ID($xnor))
1929 DEF_METHOD(Shift, sig_a.size(), ID($shift))
1930 DEF_METHOD(Shiftx, sig_a.size(), ID($shiftx))
1931 DEF_METHOD(Lt, 1, ID($lt))
1932 DEF_METHOD(Le, 1, ID($le))
1933 DEF_METHOD(Eq, 1, ID($eq))
1934 DEF_METHOD(Ne, 1, ID($ne))
1935 DEF_METHOD(Eqx, 1, ID($eqx))
1936 DEF_METHOD(Nex, 1, ID($nex))
1937 DEF_METHOD(Ge, 1, ID($ge))
1938 DEF_METHOD(Gt, 1, ID($gt))
1939 DEF_METHOD(Add, max(sig_a.size(), sig_b.size()), ID($add))
1940 DEF_METHOD(Sub, max(sig_a.size(), sig_b.size()), ID($sub))
1941 DEF_METHOD(Mul, max(sig_a.size(), sig_b.size()), ID($mul))
1942 DEF_METHOD(Div, max(sig_a.size(), sig_b.size()), ID($div))
1943 DEF_METHOD(Mod, max(sig_a.size(), sig_b.size()), ID($mod))
1944 DEF_METHOD(LogicAnd, 1, ID($logic_and))
1945 DEF_METHOD(LogicOr, 1, ID($logic_or))
1946 #undef DEF_METHOD
1947
1948 #define DEF_METHOD(_func, _y_size, _type) \
1949 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed, const std::string &src) { \
1950 RTLIL::Cell *cell = addCell(name, _type); \
1951 cell->parameters[ID::A_SIGNED] = is_signed; \
1952 cell->parameters[ID::B_SIGNED] = false; \
1953 cell->parameters[ID::A_WIDTH] = sig_a.size(); \
1954 cell->parameters[ID::B_WIDTH] = sig_b.size(); \
1955 cell->parameters[ID::Y_WIDTH] = sig_y.size(); \
1956 cell->setPort(ID::A, sig_a); \
1957 cell->setPort(ID::B, sig_b); \
1958 cell->setPort(ID::Y, sig_y); \
1959 cell->set_src_attribute(src); \
1960 return cell; \
1961 } \
1962 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed, const std::string &src) { \
1963 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
1964 add ## _func(name, sig_a, sig_b, sig_y, is_signed, src); \
1965 return sig_y; \
1966 }
1967 DEF_METHOD(Shl, sig_a.size(), ID($shl))
1968 DEF_METHOD(Shr, sig_a.size(), ID($shr))
1969 DEF_METHOD(Sshl, sig_a.size(), ID($sshl))
1970 DEF_METHOD(Sshr, sig_a.size(), ID($sshr))
1971 #undef DEF_METHOD
1972
1973 #define DEF_METHOD(_func, _type, _pmux) \
1974 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, const std::string &src) { \
1975 RTLIL::Cell *cell = addCell(name, _type); \
1976 cell->parameters[ID::WIDTH] = sig_a.size(); \
1977 if (_pmux) cell->parameters[ID::S_WIDTH] = sig_s.size(); \
1978 cell->setPort(ID::A, sig_a); \
1979 cell->setPort(ID::B, sig_b); \
1980 cell->setPort(ID::S, sig_s); \
1981 cell->setPort(ID::Y, sig_y); \
1982 cell->set_src_attribute(src); \
1983 return cell; \
1984 } \
1985 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const std::string &src) { \
1986 RTLIL::SigSpec sig_y = addWire(NEW_ID, sig_a.size()); \
1987 add ## _func(name, sig_a, sig_b, sig_s, sig_y, src); \
1988 return sig_y; \
1989 }
1990 DEF_METHOD(Mux, ID($mux), 0)
1991 DEF_METHOD(Pmux, ID($pmux), 1)
1992 #undef DEF_METHOD
1993
1994 #define DEF_METHOD_2(_func, _type, _P1, _P2) \
1995 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const std::string &src) { \
1996 RTLIL::Cell *cell = addCell(name, _type); \
1997 cell->setPort("\\" #_P1, sig1); \
1998 cell->setPort("\\" #_P2, sig2); \
1999 cell->set_src_attribute(src); \
2000 return cell; \
2001 } \
2002 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const std::string &src) { \
2003 RTLIL::SigBit sig2 = addWire(NEW_ID); \
2004 add ## _func(name, sig1, sig2, src); \
2005 return sig2; \
2006 }
2007 #define DEF_METHOD_3(_func, _type, _P1, _P2, _P3) \
2008 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const RTLIL::SigBit &sig3, const std::string &src) { \
2009 RTLIL::Cell *cell = addCell(name, _type); \
2010 cell->setPort("\\" #_P1, sig1); \
2011 cell->setPort("\\" #_P2, sig2); \
2012 cell->setPort("\\" #_P3, sig3); \
2013 cell->set_src_attribute(src); \
2014 return cell; \
2015 } \
2016 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const std::string &src) { \
2017 RTLIL::SigBit sig3 = addWire(NEW_ID); \
2018 add ## _func(name, sig1, sig2, sig3, src); \
2019 return sig3; \
2020 }
2021 #define DEF_METHOD_4(_func, _type, _P1, _P2, _P3, _P4) \
2022 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const RTLIL::SigBit &sig3, const RTLIL::SigBit &sig4, const std::string &src) { \
2023 RTLIL::Cell *cell = addCell(name, _type); \
2024 cell->setPort("\\" #_P1, sig1); \
2025 cell->setPort("\\" #_P2, sig2); \
2026 cell->setPort("\\" #_P3, sig3); \
2027 cell->setPort("\\" #_P4, sig4); \
2028 cell->set_src_attribute(src); \
2029 return cell; \
2030 } \
2031 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const RTLIL::SigBit &sig3, const std::string &src) { \
2032 RTLIL::SigBit sig4 = addWire(NEW_ID); \
2033 add ## _func(name, sig1, sig2, sig3, sig4, src); \
2034 return sig4; \
2035 }
2036 #define DEF_METHOD_5(_func, _type, _P1, _P2, _P3, _P4, _P5) \
2037 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const RTLIL::SigBit &sig3, const RTLIL::SigBit &sig4, const RTLIL::SigBit &sig5, const std::string &src) { \
2038 RTLIL::Cell *cell = addCell(name, _type); \
2039 cell->setPort("\\" #_P1, sig1); \
2040 cell->setPort("\\" #_P2, sig2); \
2041 cell->setPort("\\" #_P3, sig3); \
2042 cell->setPort("\\" #_P4, sig4); \
2043 cell->setPort("\\" #_P5, sig5); \
2044 cell->set_src_attribute(src); \
2045 return cell; \
2046 } \
2047 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const RTLIL::SigBit &sig3, const RTLIL::SigBit &sig4, const std::string &src) { \
2048 RTLIL::SigBit sig5 = addWire(NEW_ID); \
2049 add ## _func(name, sig1, sig2, sig3, sig4, sig5, src); \
2050 return sig5; \
2051 }
2052 DEF_METHOD_2(BufGate, ID($_BUF_), A, Y)
2053 DEF_METHOD_2(NotGate, ID($_NOT_), A, Y)
2054 DEF_METHOD_3(AndGate, ID($_AND_), A, B, Y)
2055 DEF_METHOD_3(NandGate, ID($_NAND_), A, B, Y)
2056 DEF_METHOD_3(OrGate, ID($_OR_), A, B, Y)
2057 DEF_METHOD_3(NorGate, ID($_NOR_), A, B, Y)
2058 DEF_METHOD_3(XorGate, ID($_XOR_), A, B, Y)
2059 DEF_METHOD_3(XnorGate, ID($_XNOR_), A, B, Y)
2060 DEF_METHOD_3(AndnotGate, ID($_ANDNOT_), A, B, Y)
2061 DEF_METHOD_3(OrnotGate, ID($_ORNOT_), A, B, Y)
2062 DEF_METHOD_4(MuxGate, ID($_MUX_), A, B, S, Y)
2063 DEF_METHOD_4(NmuxGate, ID($_NMUX_), A, B, S, Y)
2064 DEF_METHOD_4(Aoi3Gate, ID($_AOI3_), A, B, C, Y)
2065 DEF_METHOD_4(Oai3Gate, ID($_OAI3_), A, B, C, Y)
2066 DEF_METHOD_5(Aoi4Gate, ID($_AOI4_), A, B, C, D, Y)
2067 DEF_METHOD_5(Oai4Gate, ID($_OAI4_), A, B, C, D, Y)
2068 #undef DEF_METHOD_2
2069 #undef DEF_METHOD_3
2070 #undef DEF_METHOD_4
2071 #undef DEF_METHOD_5
2072
2073 RTLIL::Cell* RTLIL::Module::addPow(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool a_signed, bool b_signed, const std::string &src)
2074 {
2075 RTLIL::Cell *cell = addCell(name, ID($pow));
2076 cell->parameters[ID::A_SIGNED] = a_signed;
2077 cell->parameters[ID::B_SIGNED] = b_signed;
2078 cell->parameters[ID::A_WIDTH] = sig_a.size();
2079 cell->parameters[ID::B_WIDTH] = sig_b.size();
2080 cell->parameters[ID::Y_WIDTH] = sig_y.size();
2081 cell->setPort(ID::A, sig_a);
2082 cell->setPort(ID::B, sig_b);
2083 cell->setPort(ID::Y, sig_y);
2084 cell->set_src_attribute(src);
2085 return cell;
2086 }
2087
2088 RTLIL::Cell* RTLIL::Module::addSlice(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, RTLIL::Const offset, const std::string &src)
2089 {
2090 RTLIL::Cell *cell = addCell(name, ID($slice));
2091 cell->parameters[ID::A_WIDTH] = sig_a.size();
2092 cell->parameters[ID::Y_WIDTH] = sig_y.size();
2093 cell->parameters[ID::OFFSET] = offset;
2094 cell->setPort(ID::A, sig_a);
2095 cell->setPort(ID::Y, sig_y);
2096 cell->set_src_attribute(src);
2097 return cell;
2098 }
2099
2100 RTLIL::Cell* RTLIL::Module::addConcat(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, const std::string &src)
2101 {
2102 RTLIL::Cell *cell = addCell(name, ID($concat));
2103 cell->parameters[ID::A_WIDTH] = sig_a.size();
2104 cell->parameters[ID::B_WIDTH] = sig_b.size();
2105 cell->setPort(ID::A, sig_a);
2106 cell->setPort(ID::B, sig_b);
2107 cell->setPort(ID::Y, sig_y);
2108 cell->set_src_attribute(src);
2109 return cell;
2110 }
2111
2112 RTLIL::Cell* RTLIL::Module::addLut(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, RTLIL::Const lut, const std::string &src)
2113 {
2114 RTLIL::Cell *cell = addCell(name, ID($lut));
2115 cell->parameters[ID::LUT] = lut;
2116 cell->parameters[ID::WIDTH] = sig_a.size();
2117 cell->setPort(ID::A, sig_a);
2118 cell->setPort(ID::Y, sig_y);
2119 cell->set_src_attribute(src);
2120 return cell;
2121 }
2122
2123 RTLIL::Cell* RTLIL::Module::addTribuf(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_y, const std::string &src)
2124 {
2125 RTLIL::Cell *cell = addCell(name, ID($tribuf));
2126 cell->parameters[ID::WIDTH] = sig_a.size();
2127 cell->setPort(ID::A, sig_a);
2128 cell->setPort(ID::EN, sig_en);
2129 cell->setPort(ID::Y, sig_y);
2130 cell->set_src_attribute(src);
2131 return cell;
2132 }
2133
2134 RTLIL::Cell* RTLIL::Module::addAssert(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src)
2135 {
2136 RTLIL::Cell *cell = addCell(name, ID($assert));
2137 cell->setPort(ID::A, sig_a);
2138 cell->setPort(ID::EN, sig_en);
2139 cell->set_src_attribute(src);
2140 return cell;
2141 }
2142
2143 RTLIL::Cell* RTLIL::Module::addAssume(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src)
2144 {
2145 RTLIL::Cell *cell = addCell(name, ID($assume));
2146 cell->setPort(ID::A, sig_a);
2147 cell->setPort(ID::EN, sig_en);
2148 cell->set_src_attribute(src);
2149 return cell;
2150 }
2151
2152 RTLIL::Cell* RTLIL::Module::addLive(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src)
2153 {
2154 RTLIL::Cell *cell = addCell(name, ID($live));
2155 cell->setPort(ID::A, sig_a);
2156 cell->setPort(ID::EN, sig_en);
2157 cell->set_src_attribute(src);
2158 return cell;
2159 }
2160
2161 RTLIL::Cell* RTLIL::Module::addFair(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src)
2162 {
2163 RTLIL::Cell *cell = addCell(name, ID($fair));
2164 cell->setPort(ID::A, sig_a);
2165 cell->setPort(ID::EN, sig_en);
2166 cell->set_src_attribute(src);
2167 return cell;
2168 }
2169
2170 RTLIL::Cell* RTLIL::Module::addCover(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src)
2171 {
2172 RTLIL::Cell *cell = addCell(name, ID($cover));
2173 cell->setPort(ID::A, sig_a);
2174 cell->setPort(ID::EN, sig_en);
2175 cell->set_src_attribute(src);
2176 return cell;
2177 }
2178
2179 RTLIL::Cell* RTLIL::Module::addEquiv(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, const std::string &src)
2180 {
2181 RTLIL::Cell *cell = addCell(name, ID($equiv));
2182 cell->setPort(ID::A, sig_a);
2183 cell->setPort(ID::B, sig_b);
2184 cell->setPort(ID::Y, sig_y);
2185 cell->set_src_attribute(src);
2186 return cell;
2187 }
2188
2189 RTLIL::Cell* RTLIL::Module::addSr(RTLIL::IdString name, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, const RTLIL::SigSpec &sig_q, bool set_polarity, bool clr_polarity, const std::string &src)
2190 {
2191 RTLIL::Cell *cell = addCell(name, ID($sr));
2192 cell->parameters[ID::SET_POLARITY] = set_polarity;
2193 cell->parameters[ID::CLR_POLARITY] = clr_polarity;
2194 cell->parameters[ID::WIDTH] = sig_q.size();
2195 cell->setPort(ID::SET, sig_set);
2196 cell->setPort(ID::CLR, sig_clr);
2197 cell->setPort(ID::Q, sig_q);
2198 cell->set_src_attribute(src);
2199 return cell;
2200 }
2201
2202 RTLIL::Cell* RTLIL::Module::addFf(RTLIL::IdString name, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const std::string &src)
2203 {
2204 RTLIL::Cell *cell = addCell(name, ID($ff));
2205 cell->parameters[ID::WIDTH] = sig_q.size();
2206 cell->setPort(ID::D, sig_d);
2207 cell->setPort(ID::Q, sig_q);
2208 cell->set_src_attribute(src);
2209 return cell;
2210 }
2211
2212 RTLIL::Cell* RTLIL::Module::addDff(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, const std::string &src)
2213 {
2214 RTLIL::Cell *cell = addCell(name, ID($dff));
2215 cell->parameters[ID::CLK_POLARITY] = clk_polarity;
2216 cell->parameters[ID::WIDTH] = sig_q.size();
2217 cell->setPort(ID::CLK, sig_clk);
2218 cell->setPort(ID::D, sig_d);
2219 cell->setPort(ID::Q, sig_q);
2220 cell->set_src_attribute(src);
2221 return cell;
2222 }
2223
2224 RTLIL::Cell* RTLIL::Module::addDffe(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, bool en_polarity, const std::string &src)
2225 {
2226 RTLIL::Cell *cell = addCell(name, ID($dffe));
2227 cell->parameters[ID::CLK_POLARITY] = clk_polarity;
2228 cell->parameters[ID::EN_POLARITY] = en_polarity;
2229 cell->parameters[ID::WIDTH] = sig_q.size();
2230 cell->setPort(ID::CLK, sig_clk);
2231 cell->setPort(ID::EN, sig_en);
2232 cell->setPort(ID::D, sig_d);
2233 cell->setPort(ID::Q, sig_q);
2234 cell->set_src_attribute(src);
2235 return cell;
2236 }
2237
2238 RTLIL::Cell* RTLIL::Module::addDffsr(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,
2239 RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
2240 {
2241 RTLIL::Cell *cell = addCell(name, ID($dffsr));
2242 cell->parameters[ID::CLK_POLARITY] = clk_polarity;
2243 cell->parameters[ID::SET_POLARITY] = set_polarity;
2244 cell->parameters[ID::CLR_POLARITY] = clr_polarity;
2245 cell->parameters[ID::WIDTH] = sig_q.size();
2246 cell->setPort(ID::CLK, sig_clk);
2247 cell->setPort(ID::SET, sig_set);
2248 cell->setPort(ID::CLR, sig_clr);
2249 cell->setPort(ID::D, sig_d);
2250 cell->setPort(ID::Q, sig_q);
2251 cell->set_src_attribute(src);
2252 return cell;
2253 }
2254
2255 RTLIL::Cell* RTLIL::Module::addAdff(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
2256 RTLIL::Const arst_value, bool clk_polarity, bool arst_polarity, const std::string &src)
2257 {
2258 RTLIL::Cell *cell = addCell(name, ID($adff));
2259 cell->parameters[ID::CLK_POLARITY] = clk_polarity;
2260 cell->parameters[ID::ARST_POLARITY] = arst_polarity;
2261 cell->parameters[ID::ARST_VALUE] = arst_value;
2262 cell->parameters[ID::WIDTH] = sig_q.size();
2263 cell->setPort(ID::CLK, sig_clk);
2264 cell->setPort(ID::ARST, sig_arst);
2265 cell->setPort(ID::D, sig_d);
2266 cell->setPort(ID::Q, sig_q);
2267 cell->set_src_attribute(src);
2268 return cell;
2269 }
2270
2271 RTLIL::Cell* RTLIL::Module::addDlatch(RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity, const std::string &src)
2272 {
2273 RTLIL::Cell *cell = addCell(name, ID($dlatch));
2274 cell->parameters[ID::EN_POLARITY] = en_polarity;
2275 cell->parameters[ID::WIDTH] = sig_q.size();
2276 cell->setPort(ID::EN, sig_en);
2277 cell->setPort(ID::D, sig_d);
2278 cell->setPort(ID::Q, sig_q);
2279 cell->set_src_attribute(src);
2280 return cell;
2281 }
2282
2283 RTLIL::Cell* RTLIL::Module::addDlatchsr(RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,
2284 RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
2285 {
2286 RTLIL::Cell *cell = addCell(name, ID($dlatchsr));
2287 cell->parameters[ID::EN_POLARITY] = en_polarity;
2288 cell->parameters[ID::SET_POLARITY] = set_polarity;
2289 cell->parameters[ID::CLR_POLARITY] = clr_polarity;
2290 cell->parameters[ID::WIDTH] = sig_q.size();
2291 cell->setPort(ID::EN, sig_en);
2292 cell->setPort(ID::SET, sig_set);
2293 cell->setPort(ID::CLR, sig_clr);
2294 cell->setPort(ID::D, sig_d);
2295 cell->setPort(ID::Q, sig_q);
2296 cell->set_src_attribute(src);
2297 return cell;
2298 }
2299
2300 RTLIL::Cell* RTLIL::Module::addFfGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const std::string &src)
2301 {
2302 RTLIL::Cell *cell = addCell(name, ID($_FF_));
2303 cell->setPort(ID::D, sig_d);
2304 cell->setPort(ID::Q, sig_q);
2305 cell->set_src_attribute(src);
2306 return cell;
2307 }
2308
2309 RTLIL::Cell* RTLIL::Module::addDffGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, const std::string &src)
2310 {
2311 RTLIL::Cell *cell = addCell(name, stringf("$_DFF_%c_", clk_polarity ? 'P' : 'N'));
2312 cell->setPort(ID::C, sig_clk);
2313 cell->setPort(ID::D, sig_d);
2314 cell->setPort(ID::Q, sig_q);
2315 cell->set_src_attribute(src);
2316 return cell;
2317 }
2318
2319 RTLIL::Cell* RTLIL::Module::addDffeGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, bool en_polarity, const std::string &src)
2320 {
2321 RTLIL::Cell *cell = addCell(name, stringf("$_DFFE_%c%c_", clk_polarity ? 'P' : 'N', en_polarity ? 'P' : 'N'));
2322 cell->setPort(ID::C, sig_clk);
2323 cell->setPort(ID::E, sig_en);
2324 cell->setPort(ID::D, sig_d);
2325 cell->setPort(ID::Q, sig_q);
2326 cell->set_src_attribute(src);
2327 return cell;
2328 }
2329
2330 RTLIL::Cell* RTLIL::Module::addDffsrGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,
2331 RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
2332 {
2333 RTLIL::Cell *cell = addCell(name, stringf("$_DFFSR_%c%c%c_", clk_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N'));
2334 cell->setPort(ID::C, sig_clk);
2335 cell->setPort(ID::S, sig_set);
2336 cell->setPort(ID::R, sig_clr);
2337 cell->setPort(ID::D, sig_d);
2338 cell->setPort(ID::Q, sig_q);
2339 cell->set_src_attribute(src);
2340 return cell;
2341 }
2342
2343 RTLIL::Cell* RTLIL::Module::addAdffGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
2344 bool arst_value, bool clk_polarity, bool arst_polarity, const std::string &src)
2345 {
2346 RTLIL::Cell *cell = addCell(name, stringf("$_DFF_%c%c%c_", clk_polarity ? 'P' : 'N', arst_polarity ? 'P' : 'N', arst_value ? '1' : '0'));
2347 cell->setPort(ID::C, sig_clk);
2348 cell->setPort(ID::R, sig_arst);
2349 cell->setPort(ID::D, sig_d);
2350 cell->setPort(ID::Q, sig_q);
2351 cell->set_src_attribute(src);
2352 return cell;
2353 }
2354
2355 RTLIL::Cell* RTLIL::Module::addDlatchGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity, const std::string &src)
2356 {
2357 RTLIL::Cell *cell = addCell(name, stringf("$_DLATCH_%c_", en_polarity ? 'P' : 'N'));
2358 cell->setPort(ID::E, sig_en);
2359 cell->setPort(ID::D, sig_d);
2360 cell->setPort(ID::Q, sig_q);
2361 cell->set_src_attribute(src);
2362 return cell;
2363 }
2364
2365 RTLIL::Cell* RTLIL::Module::addDlatchsrGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,
2366 RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
2367 {
2368 RTLIL::Cell *cell = addCell(name, stringf("$_DLATCHSR_%c%c%c_", en_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N'));
2369 cell->setPort(ID::E, sig_en);
2370 cell->setPort(ID::S, sig_set);
2371 cell->setPort(ID::R, sig_clr);
2372 cell->setPort(ID::D, sig_d);
2373 cell->setPort(ID::Q, sig_q);
2374 cell->set_src_attribute(src);
2375 return cell;
2376 }
2377
2378 RTLIL::SigSpec RTLIL::Module::Anyconst(RTLIL::IdString name, int width, const std::string &src)
2379 {
2380 RTLIL::SigSpec sig = addWire(NEW_ID, width);
2381 Cell *cell = addCell(name, ID($anyconst));
2382 cell->setParam(ID::WIDTH, width);
2383 cell->setPort(ID::Y, sig);
2384 cell->set_src_attribute(src);
2385 return sig;
2386 }
2387
2388 RTLIL::SigSpec RTLIL::Module::Anyseq(RTLIL::IdString name, int width, const std::string &src)
2389 {
2390 RTLIL::SigSpec sig = addWire(NEW_ID, width);
2391 Cell *cell = addCell(name, ID($anyseq));
2392 cell->setParam(ID::WIDTH, width);
2393 cell->setPort(ID::Y, sig);
2394 cell->set_src_attribute(src);
2395 return sig;
2396 }
2397
2398 RTLIL::SigSpec RTLIL::Module::Allconst(RTLIL::IdString name, int width, const std::string &src)
2399 {
2400 RTLIL::SigSpec sig = addWire(NEW_ID, width);
2401 Cell *cell = addCell(name, ID($allconst));
2402 cell->setParam(ID::WIDTH, width);
2403 cell->setPort(ID::Y, sig);
2404 cell->set_src_attribute(src);
2405 return sig;
2406 }
2407
2408 RTLIL::SigSpec RTLIL::Module::Allseq(RTLIL::IdString name, int width, const std::string &src)
2409 {
2410 RTLIL::SigSpec sig = addWire(NEW_ID, width);
2411 Cell *cell = addCell(name, ID($allseq));
2412 cell->setParam(ID::WIDTH, width);
2413 cell->setPort(ID::Y, sig);
2414 cell->set_src_attribute(src);
2415 return sig;
2416 }
2417
2418 RTLIL::SigSpec RTLIL::Module::Initstate(RTLIL::IdString name, const std::string &src)
2419 {
2420 RTLIL::SigSpec sig = addWire(NEW_ID);
2421 Cell *cell = addCell(name, ID($initstate));
2422 cell->setPort(ID::Y, sig);
2423 cell->set_src_attribute(src);
2424 return sig;
2425 }
2426
2427 RTLIL::Wire::Wire()
2428 {
2429 static unsigned int hashidx_count = 123456789;
2430 hashidx_count = mkhash_xorshift(hashidx_count);
2431 hashidx_ = hashidx_count;
2432
2433 module = nullptr;
2434 width = 1;
2435 start_offset = 0;
2436 port_id = 0;
2437 port_input = false;
2438 port_output = false;
2439 upto = false;
2440
2441 #ifdef WITH_PYTHON
2442 RTLIL::Wire::get_all_wires()->insert(std::pair<unsigned int, RTLIL::Wire*>(hashidx_, this));
2443 #endif
2444 }
2445
2446 RTLIL::Wire::~Wire()
2447 {
2448 #ifdef WITH_PYTHON
2449 RTLIL::Wire::get_all_wires()->erase(hashidx_);
2450 #endif
2451 }
2452
2453 #ifdef WITH_PYTHON
2454 static std::map<unsigned int, RTLIL::Wire*> all_wires;
2455 std::map<unsigned int, RTLIL::Wire*> *RTLIL::Wire::get_all_wires(void)
2456 {
2457 return &all_wires;
2458 }
2459 #endif
2460
2461 RTLIL::Memory::Memory()
2462 {
2463 static unsigned int hashidx_count = 123456789;
2464 hashidx_count = mkhash_xorshift(hashidx_count);
2465 hashidx_ = hashidx_count;
2466
2467 width = 1;
2468 start_offset = 0;
2469 size = 0;
2470 #ifdef WITH_PYTHON
2471 RTLIL::Memory::get_all_memorys()->insert(std::pair<unsigned int, RTLIL::Memory*>(hashidx_, this));
2472 #endif
2473 }
2474
2475 RTLIL::Cell::Cell() : module(nullptr)
2476 {
2477 static unsigned int hashidx_count = 123456789;
2478 hashidx_count = mkhash_xorshift(hashidx_count);
2479 hashidx_ = hashidx_count;
2480
2481 // log("#memtrace# %p\n", this);
2482 memhasher();
2483
2484 #ifdef WITH_PYTHON
2485 RTLIL::Cell::get_all_cells()->insert(std::pair<unsigned int, RTLIL::Cell*>(hashidx_, this));
2486 #endif
2487 }
2488
2489 RTLIL::Cell::~Cell()
2490 {
2491 #ifdef WITH_PYTHON
2492 RTLIL::Cell::get_all_cells()->erase(hashidx_);
2493 #endif
2494 }
2495
2496 #ifdef WITH_PYTHON
2497 static std::map<unsigned int, RTLIL::Cell*> all_cells;
2498 std::map<unsigned int, RTLIL::Cell*> *RTLIL::Cell::get_all_cells(void)
2499 {
2500 return &all_cells;
2501 }
2502 #endif
2503
2504 bool RTLIL::Cell::hasPort(RTLIL::IdString portname) const
2505 {
2506 return connections_.count(portname) != 0;
2507 }
2508
2509 void RTLIL::Cell::unsetPort(RTLIL::IdString portname)
2510 {
2511 RTLIL::SigSpec signal;
2512 auto conn_it = connections_.find(portname);
2513
2514 if (conn_it != connections_.end())
2515 {
2516 for (auto mon : module->monitors)
2517 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
2518
2519 if (module->design)
2520 for (auto mon : module->design->monitors)
2521 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
2522
2523 if (yosys_xtrace) {
2524 log("#X# Unconnect %s.%s.%s\n", log_id(this->module), log_id(this), log_id(portname));
2525 log_backtrace("-X- ", yosys_xtrace-1);
2526 }
2527
2528 connections_.erase(conn_it);
2529 }
2530 }
2531
2532 void RTLIL::Cell::setPort(RTLIL::IdString portname, RTLIL::SigSpec signal)
2533 {
2534 auto r = connections_.insert(portname);
2535 auto conn_it = r.first;
2536 if (!r.second && conn_it->second == signal)
2537 return;
2538
2539 for (auto mon : module->monitors)
2540 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
2541
2542 if (module->design)
2543 for (auto mon : module->design->monitors)
2544 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
2545
2546 if (yosys_xtrace) {
2547 log("#X# Connect %s.%s.%s = %s (%d)\n", log_id(this->module), log_id(this), log_id(portname), log_signal(signal), GetSize(signal));
2548 log_backtrace("-X- ", yosys_xtrace-1);
2549 }
2550
2551 conn_it->second = std::move(signal);
2552 }
2553
2554 const RTLIL::SigSpec &RTLIL::Cell::getPort(RTLIL::IdString portname) const
2555 {
2556 return connections_.at(portname);
2557 }
2558
2559 const dict<RTLIL::IdString, RTLIL::SigSpec> &RTLIL::Cell::connections() const
2560 {
2561 return connections_;
2562 }
2563
2564 bool RTLIL::Cell::known() const
2565 {
2566 if (yosys_celltypes.cell_known(type))
2567 return true;
2568 if (module && module->design && module->design->module(type))
2569 return true;
2570 return false;
2571 }
2572
2573 bool RTLIL::Cell::input(RTLIL::IdString portname) const
2574 {
2575 if (yosys_celltypes.cell_known(type))
2576 return yosys_celltypes.cell_input(type, portname);
2577 if (module && module->design) {
2578 RTLIL::Module *m = module->design->module(type);
2579 RTLIL::Wire *w = m ? m->wire(portname) : nullptr;
2580 return w && w->port_input;
2581 }
2582 return false;
2583 }
2584
2585 bool RTLIL::Cell::output(RTLIL::IdString portname) const
2586 {
2587 if (yosys_celltypes.cell_known(type))
2588 return yosys_celltypes.cell_output(type, portname);
2589 if (module && module->design) {
2590 RTLIL::Module *m = module->design->module(type);
2591 RTLIL::Wire *w = m ? m->wire(portname) : nullptr;
2592 return w && w->port_output;
2593 }
2594 return false;
2595 }
2596
2597 bool RTLIL::Cell::hasParam(RTLIL::IdString paramname) const
2598 {
2599 return parameters.count(paramname) != 0;
2600 }
2601
2602 void RTLIL::Cell::unsetParam(RTLIL::IdString paramname)
2603 {
2604 parameters.erase(paramname);
2605 }
2606
2607 void RTLIL::Cell::setParam(RTLIL::IdString paramname, RTLIL::Const value)
2608 {
2609 parameters[paramname] = std::move(value);
2610 }
2611
2612 const RTLIL::Const &RTLIL::Cell::getParam(RTLIL::IdString paramname) const
2613 {
2614 return parameters.at(paramname);
2615 }
2616
2617 void RTLIL::Cell::sort()
2618 {
2619 connections_.sort(sort_by_id_str());
2620 parameters.sort(sort_by_id_str());
2621 attributes.sort(sort_by_id_str());
2622 }
2623
2624 void RTLIL::Cell::check()
2625 {
2626 #ifndef NDEBUG
2627 InternalCellChecker checker(NULL, this);
2628 checker.check();
2629 #endif
2630 }
2631
2632 void RTLIL::Cell::fixup_parameters(bool set_a_signed, bool set_b_signed)
2633 {
2634 if (!type.begins_with("$") || type.begins_with("$_") || type.begins_with("$paramod") || type.begins_with("$fmcombine") ||
2635 type.begins_with("$verific$") || type.begins_with("$array:") || type.begins_with("$extern:"))
2636 return;
2637
2638 if (type == ID($mux) || type == ID($pmux)) {
2639 parameters[ID::WIDTH] = GetSize(connections_[ID::Y]);
2640 if (type == ID($pmux))
2641 parameters[ID::S_WIDTH] = GetSize(connections_[ID::S]);
2642 check();
2643 return;
2644 }
2645
2646 if (type == ID($lut) || type == ID($sop)) {
2647 parameters[ID::WIDTH] = GetSize(connections_[ID::A]);
2648 return;
2649 }
2650
2651 if (type == ID($fa)) {
2652 parameters[ID::WIDTH] = GetSize(connections_[ID::Y]);
2653 return;
2654 }
2655
2656 if (type == ID($lcu)) {
2657 parameters[ID::WIDTH] = GetSize(connections_[ID::CO]);
2658 return;
2659 }
2660
2661 bool signedness_ab = !type.in(ID($slice), ID($concat), ID($macc));
2662
2663 if (connections_.count(ID::A)) {
2664 if (signedness_ab) {
2665 if (set_a_signed)
2666 parameters[ID::A_SIGNED] = true;
2667 else if (parameters.count(ID::A_SIGNED) == 0)
2668 parameters[ID::A_SIGNED] = false;
2669 }
2670 parameters[ID::A_WIDTH] = GetSize(connections_[ID::A]);
2671 }
2672
2673 if (connections_.count(ID::B)) {
2674 if (signedness_ab) {
2675 if (set_b_signed)
2676 parameters[ID::B_SIGNED] = true;
2677 else if (parameters.count(ID::B_SIGNED) == 0)
2678 parameters[ID::B_SIGNED] = false;
2679 }
2680 parameters[ID::B_WIDTH] = GetSize(connections_[ID::B]);
2681 }
2682
2683 if (connections_.count(ID::Y))
2684 parameters[ID::Y_WIDTH] = GetSize(connections_[ID::Y]);
2685
2686 if (connections_.count(ID::Q))
2687 parameters[ID::WIDTH] = GetSize(connections_[ID::Q]);
2688
2689 check();
2690 }
2691
2692 RTLIL::SigChunk::SigChunk()
2693 {
2694 wire = NULL;
2695 width = 0;
2696 offset = 0;
2697 }
2698
2699 RTLIL::SigChunk::SigChunk(const RTLIL::Const &value)
2700 {
2701 wire = NULL;
2702 data = value.bits;
2703 width = GetSize(data);
2704 offset = 0;
2705 }
2706
2707 RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire)
2708 {
2709 log_assert(wire != nullptr);
2710 this->wire = wire;
2711 this->width = wire->width;
2712 this->offset = 0;
2713 }
2714
2715 RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire, int offset, int width)
2716 {
2717 log_assert(wire != nullptr);
2718 this->wire = wire;
2719 this->width = width;
2720 this->offset = offset;
2721 }
2722
2723 RTLIL::SigChunk::SigChunk(const std::string &str)
2724 {
2725 wire = NULL;
2726 data = RTLIL::Const(str).bits;
2727 width = GetSize(data);
2728 offset = 0;
2729 }
2730
2731 RTLIL::SigChunk::SigChunk(int val, int width)
2732 {
2733 wire = NULL;
2734 data = RTLIL::Const(val, width).bits;
2735 this->width = GetSize(data);
2736 offset = 0;
2737 }
2738
2739 RTLIL::SigChunk::SigChunk(RTLIL::State bit, int width)
2740 {
2741 wire = NULL;
2742 data = RTLIL::Const(bit, width).bits;
2743 this->width = GetSize(data);
2744 offset = 0;
2745 }
2746
2747 RTLIL::SigChunk::SigChunk(const RTLIL::SigBit &bit)
2748 {
2749 wire = bit.wire;
2750 offset = 0;
2751 if (wire == NULL)
2752 data = RTLIL::Const(bit.data).bits;
2753 else
2754 offset = bit.offset;
2755 width = 1;
2756 }
2757
2758 RTLIL::SigChunk::SigChunk(const RTLIL::SigChunk &sigchunk)
2759 {
2760 *this = sigchunk;
2761 }
2762
2763 RTLIL::SigChunk RTLIL::SigChunk::extract(int offset, int length) const
2764 {
2765 RTLIL::SigChunk ret;
2766 if (wire) {
2767 ret.wire = wire;
2768 ret.offset = this->offset + offset;
2769 ret.width = length;
2770 } else {
2771 for (int i = 0; i < length; i++)
2772 ret.data.push_back(data[offset+i]);
2773 ret.width = length;
2774 }
2775 return ret;
2776 }
2777
2778 bool RTLIL::SigChunk::operator <(const RTLIL::SigChunk &other) const
2779 {
2780 if (wire && other.wire)
2781 if (wire->name != other.wire->name)
2782 return wire->name < other.wire->name;
2783
2784 if (wire != other.wire)
2785 return wire < other.wire;
2786
2787 if (offset != other.offset)
2788 return offset < other.offset;
2789
2790 if (width != other.width)
2791 return width < other.width;
2792
2793 return data < other.data;
2794 }
2795
2796 bool RTLIL::SigChunk::operator ==(const RTLIL::SigChunk &other) const
2797 {
2798 return wire == other.wire && width == other.width && offset == other.offset && data == other.data;
2799 }
2800
2801 bool RTLIL::SigChunk::operator !=(const RTLIL::SigChunk &other) const
2802 {
2803 if (*this == other)
2804 return false;
2805 return true;
2806 }
2807
2808 RTLIL::SigSpec::SigSpec()
2809 {
2810 width_ = 0;
2811 hash_ = 0;
2812 }
2813
2814 RTLIL::SigSpec::SigSpec(const RTLIL::SigSpec &other)
2815 {
2816 *this = other;
2817 }
2818
2819 RTLIL::SigSpec::SigSpec(std::initializer_list<RTLIL::SigSpec> parts)
2820 {
2821 cover("kernel.rtlil.sigspec.init.list");
2822
2823 width_ = 0;
2824 hash_ = 0;
2825
2826 log_assert(parts.size() > 0);
2827 auto ie = parts.begin();
2828 auto it = ie + parts.size() - 1;
2829 while (it >= ie)
2830 append(*it--);
2831 }
2832
2833 RTLIL::SigSpec &RTLIL::SigSpec::operator=(const RTLIL::SigSpec &other)
2834 {
2835 cover("kernel.rtlil.sigspec.assign");
2836
2837 width_ = other.width_;
2838 hash_ = other.hash_;
2839 chunks_ = other.chunks_;
2840 bits_ = other.bits_;
2841 return *this;
2842 }
2843
2844 RTLIL::SigSpec::SigSpec(const RTLIL::Const &value)
2845 {
2846 cover("kernel.rtlil.sigspec.init.const");
2847
2848 chunks_.emplace_back(value);
2849 width_ = chunks_.back().width;
2850 hash_ = 0;
2851 check();
2852 }
2853
2854 RTLIL::SigSpec::SigSpec(const RTLIL::SigChunk &chunk)
2855 {
2856 cover("kernel.rtlil.sigspec.init.chunk");
2857
2858 chunks_.emplace_back(chunk);
2859 width_ = chunks_.back().width;
2860 hash_ = 0;
2861 check();
2862 }
2863
2864 RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire)
2865 {
2866 cover("kernel.rtlil.sigspec.init.wire");
2867
2868 chunks_.emplace_back(wire);
2869 width_ = chunks_.back().width;
2870 hash_ = 0;
2871 check();
2872 }
2873
2874 RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire, int offset, int width)
2875 {
2876 cover("kernel.rtlil.sigspec.init.wire_part");
2877
2878 chunks_.emplace_back(wire, offset, width);
2879 width_ = chunks_.back().width;
2880 hash_ = 0;
2881 check();
2882 }
2883
2884 RTLIL::SigSpec::SigSpec(const std::string &str)
2885 {
2886 cover("kernel.rtlil.sigspec.init.str");
2887
2888 chunks_.emplace_back(str);
2889 width_ = chunks_.back().width;
2890 hash_ = 0;
2891 check();
2892 }
2893
2894 RTLIL::SigSpec::SigSpec(int val, int width)
2895 {
2896 cover("kernel.rtlil.sigspec.init.int");
2897
2898 chunks_.emplace_back(val, width);
2899 width_ = width;
2900 hash_ = 0;
2901 check();
2902 }
2903
2904 RTLIL::SigSpec::SigSpec(RTLIL::State bit, int width)
2905 {
2906 cover("kernel.rtlil.sigspec.init.state");
2907
2908 chunks_.emplace_back(bit, width);
2909 width_ = width;
2910 hash_ = 0;
2911 check();
2912 }
2913
2914 RTLIL::SigSpec::SigSpec(const RTLIL::SigBit &bit, int width)
2915 {
2916 cover("kernel.rtlil.sigspec.init.bit");
2917
2918 if (bit.wire == NULL)
2919 chunks_.emplace_back(bit.data, width);
2920 else
2921 for (int i = 0; i < width; i++)
2922 chunks_.push_back(bit);
2923 width_ = width;
2924 hash_ = 0;
2925 check();
2926 }
2927
2928 RTLIL::SigSpec::SigSpec(const std::vector<RTLIL::SigChunk> &chunks)
2929 {
2930 cover("kernel.rtlil.sigspec.init.stdvec_chunks");
2931
2932 width_ = 0;
2933 hash_ = 0;
2934 for (const auto &c : chunks)
2935 append(c);
2936 check();
2937 }
2938
2939 RTLIL::SigSpec::SigSpec(const std::vector<RTLIL::SigBit> &bits)
2940 {
2941 cover("kernel.rtlil.sigspec.init.stdvec_bits");
2942
2943 width_ = 0;
2944 hash_ = 0;
2945 for (const auto &bit : bits)
2946 append(bit);
2947 check();
2948 }
2949
2950 RTLIL::SigSpec::SigSpec(const pool<RTLIL::SigBit> &bits)
2951 {
2952 cover("kernel.rtlil.sigspec.init.pool_bits");
2953
2954 width_ = 0;
2955 hash_ = 0;
2956 for (const auto &bit : bits)
2957 append(bit);
2958 check();
2959 }
2960
2961 RTLIL::SigSpec::SigSpec(const std::set<RTLIL::SigBit> &bits)
2962 {
2963 cover("kernel.rtlil.sigspec.init.stdset_bits");
2964
2965 width_ = 0;
2966 hash_ = 0;
2967 for (const auto &bit : bits)
2968 append(bit);
2969 check();
2970 }
2971
2972 RTLIL::SigSpec::SigSpec(bool bit)
2973 {
2974 cover("kernel.rtlil.sigspec.init.bool");
2975
2976 width_ = 0;
2977 hash_ = 0;
2978 append(SigBit(bit));
2979 check();
2980 }
2981
2982 void RTLIL::SigSpec::pack() const
2983 {
2984 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
2985
2986 if (that->bits_.empty())
2987 return;
2988
2989 cover("kernel.rtlil.sigspec.convert.pack");
2990 log_assert(that->chunks_.empty());
2991
2992 std::vector<RTLIL::SigBit> old_bits;
2993 old_bits.swap(that->bits_);
2994
2995 RTLIL::SigChunk *last = NULL;
2996 int last_end_offset = 0;
2997
2998 for (auto &bit : old_bits) {
2999 if (last && bit.wire == last->wire) {
3000 if (bit.wire == NULL) {
3001 last->data.push_back(bit.data);
3002 last->width++;
3003 continue;
3004 } else if (last_end_offset == bit.offset) {
3005 last_end_offset++;
3006 last->width++;
3007 continue;
3008 }
3009 }
3010 that->chunks_.push_back(bit);
3011 last = &that->chunks_.back();
3012 last_end_offset = bit.offset + 1;
3013 }
3014
3015 check();
3016 }
3017
3018 void RTLIL::SigSpec::unpack() const
3019 {
3020 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
3021
3022 if (that->chunks_.empty())
3023 return;
3024
3025 cover("kernel.rtlil.sigspec.convert.unpack");
3026 log_assert(that->bits_.empty());
3027
3028 that->bits_.reserve(that->width_);
3029 for (auto &c : that->chunks_)
3030 for (int i = 0; i < c.width; i++)
3031 that->bits_.emplace_back(c, i);
3032
3033 that->chunks_.clear();
3034 that->hash_ = 0;
3035 }
3036
3037 void RTLIL::SigSpec::updhash() const
3038 {
3039 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
3040
3041 if (that->hash_ != 0)
3042 return;
3043
3044 cover("kernel.rtlil.sigspec.hash");
3045 that->pack();
3046
3047 that->hash_ = mkhash_init;
3048 for (auto &c : that->chunks_)
3049 if (c.wire == NULL) {
3050 for (auto &v : c.data)
3051 that->hash_ = mkhash(that->hash_, v);
3052 } else {
3053 that->hash_ = mkhash(that->hash_, c.wire->name.index_);
3054 that->hash_ = mkhash(that->hash_, c.offset);
3055 that->hash_ = mkhash(that->hash_, c.width);
3056 }
3057
3058 if (that->hash_ == 0)
3059 that->hash_ = 1;
3060 }
3061
3062 void RTLIL::SigSpec::sort()
3063 {
3064 unpack();
3065 cover("kernel.rtlil.sigspec.sort");
3066 std::sort(bits_.begin(), bits_.end());
3067 }
3068
3069 void RTLIL::SigSpec::sort_and_unify()
3070 {
3071 unpack();
3072 cover("kernel.rtlil.sigspec.sort_and_unify");
3073
3074 // A copy of the bits vector is used to prevent duplicating the logic from
3075 // SigSpec::SigSpec(std::vector<SigBit>). This incurrs an extra copy but
3076 // that isn't showing up as significant in profiles.
3077 std::vector<SigBit> unique_bits = bits_;
3078 std::sort(unique_bits.begin(), unique_bits.end());
3079 auto last = std::unique(unique_bits.begin(), unique_bits.end());
3080 unique_bits.erase(last, unique_bits.end());
3081
3082 *this = unique_bits;
3083 }
3084
3085 void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with)
3086 {
3087 replace(pattern, with, this);
3088 }
3089
3090 void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with, RTLIL::SigSpec *other) const
3091 {
3092 log_assert(other != NULL);
3093 log_assert(width_ == other->width_);
3094 log_assert(pattern.width_ == with.width_);
3095
3096 pattern.unpack();
3097 with.unpack();
3098 unpack();
3099 other->unpack();
3100
3101 for (int i = 0; i < GetSize(pattern.bits_); i++) {
3102 if (pattern.bits_[i].wire != NULL) {
3103 for (int j = 0; j < GetSize(bits_); j++) {
3104 if (bits_[j] == pattern.bits_[i]) {
3105 other->bits_[j] = with.bits_[i];
3106 }
3107 }
3108 }
3109 }
3110
3111 other->check();
3112 }
3113
3114 void RTLIL::SigSpec::replace(const dict<RTLIL::SigBit, RTLIL::SigBit> &rules)
3115 {
3116 replace(rules, this);
3117 }
3118
3119 void RTLIL::SigSpec::replace(const dict<RTLIL::SigBit, RTLIL::SigBit> &rules, RTLIL::SigSpec *other) const
3120 {
3121 cover("kernel.rtlil.sigspec.replace_dict");
3122
3123 log_assert(other != NULL);
3124 log_assert(width_ == other->width_);
3125
3126 if (rules.empty()) return;
3127 unpack();
3128 other->unpack();
3129
3130 for (int i = 0; i < GetSize(bits_); i++) {
3131 auto it = rules.find(bits_[i]);
3132 if (it != rules.end())
3133 other->bits_[i] = it->second;
3134 }
3135
3136 other->check();
3137 }
3138
3139 void RTLIL::SigSpec::replace(const std::map<RTLIL::SigBit, RTLIL::SigBit> &rules)
3140 {
3141 replace(rules, this);
3142 }
3143
3144 void RTLIL::SigSpec::replace(const std::map<RTLIL::SigBit, RTLIL::SigBit> &rules, RTLIL::SigSpec *other) const
3145 {
3146 cover("kernel.rtlil.sigspec.replace_map");
3147
3148 log_assert(other != NULL);
3149 log_assert(width_ == other->width_);
3150
3151 if (rules.empty()) return;
3152 unpack();
3153 other->unpack();
3154
3155 for (int i = 0; i < GetSize(bits_); i++) {
3156 auto it = rules.find(bits_[i]);
3157 if (it != rules.end())
3158 other->bits_[i] = it->second;
3159 }
3160
3161 other->check();
3162 }
3163
3164 void RTLIL::SigSpec::remove(const RTLIL::SigSpec &pattern)
3165 {
3166 remove2(pattern, NULL);
3167 }
3168
3169 void RTLIL::SigSpec::remove(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other) const
3170 {
3171 RTLIL::SigSpec tmp = *this;
3172 tmp.remove2(pattern, other);
3173 }
3174
3175 void RTLIL::SigSpec::remove2(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other)
3176 {
3177 if (other)
3178 cover("kernel.rtlil.sigspec.remove_other");
3179 else
3180 cover("kernel.rtlil.sigspec.remove");
3181
3182 unpack();
3183 if (other != NULL) {
3184 log_assert(width_ == other->width_);
3185 other->unpack();
3186 }
3187
3188 for (int i = GetSize(bits_) - 1; i >= 0; i--)
3189 {
3190 if (bits_[i].wire == NULL) continue;
3191
3192 for (auto &pattern_chunk : pattern.chunks())
3193 if (bits_[i].wire == pattern_chunk.wire &&
3194 bits_[i].offset >= pattern_chunk.offset &&
3195 bits_[i].offset < pattern_chunk.offset + pattern_chunk.width) {
3196 bits_.erase(bits_.begin() + i);
3197 width_--;
3198 if (other != NULL) {
3199 other->bits_.erase(other->bits_.begin() + i);
3200 other->width_--;
3201 }
3202 break;
3203 }
3204 }
3205
3206 check();
3207 }
3208
3209 void RTLIL::SigSpec::remove(const pool<RTLIL::SigBit> &pattern)
3210 {
3211 remove2(pattern, NULL);
3212 }
3213
3214 void RTLIL::SigSpec::remove(const pool<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other) const
3215 {
3216 RTLIL::SigSpec tmp = *this;
3217 tmp.remove2(pattern, other);
3218 }
3219
3220 void RTLIL::SigSpec::remove2(const pool<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other)
3221 {
3222 if (other)
3223 cover("kernel.rtlil.sigspec.remove_other");
3224 else
3225 cover("kernel.rtlil.sigspec.remove");
3226
3227 unpack();
3228
3229 if (other != NULL) {
3230 log_assert(width_ == other->width_);
3231 other->unpack();
3232 }
3233
3234 for (int i = GetSize(bits_) - 1; i >= 0; i--) {
3235 if (bits_[i].wire != NULL && pattern.count(bits_[i])) {
3236 bits_.erase(bits_.begin() + i);
3237 width_--;
3238 if (other != NULL) {
3239 other->bits_.erase(other->bits_.begin() + i);
3240 other->width_--;
3241 }
3242 }
3243 }
3244
3245 check();
3246 }
3247
3248 void RTLIL::SigSpec::remove2(const std::set<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other)
3249 {
3250 if (other)
3251 cover("kernel.rtlil.sigspec.remove_other");
3252 else
3253 cover("kernel.rtlil.sigspec.remove");
3254
3255 unpack();
3256
3257 if (other != NULL) {
3258 log_assert(width_ == other->width_);
3259 other->unpack();
3260 }
3261
3262 for (int i = GetSize(bits_) - 1; i >= 0; i--) {
3263 if (bits_[i].wire != NULL && pattern.count(bits_[i])) {
3264 bits_.erase(bits_.begin() + i);
3265 width_--;
3266 if (other != NULL) {
3267 other->bits_.erase(other->bits_.begin() + i);
3268 other->width_--;
3269 }
3270 }
3271 }
3272
3273 check();
3274 }
3275
3276 RTLIL::SigSpec RTLIL::SigSpec::extract(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec *other) const
3277 {
3278 if (other)
3279 cover("kernel.rtlil.sigspec.extract_other");
3280 else
3281 cover("kernel.rtlil.sigspec.extract");
3282
3283 log_assert(other == NULL || width_ == other->width_);
3284
3285 RTLIL::SigSpec ret;
3286 std::vector<RTLIL::SigBit> bits_match = to_sigbit_vector();
3287
3288 for (auto& pattern_chunk : pattern.chunks()) {
3289 if (other) {
3290 std::vector<RTLIL::SigBit> bits_other = other->to_sigbit_vector();
3291 for (int i = 0; i < width_; i++)
3292 if (bits_match[i].wire &&
3293 bits_match[i].wire == pattern_chunk.wire &&
3294 bits_match[i].offset >= pattern_chunk.offset &&
3295 bits_match[i].offset < pattern_chunk.offset + pattern_chunk.width)
3296 ret.append(bits_other[i]);
3297 } else {
3298 for (int i = 0; i < width_; i++)
3299 if (bits_match[i].wire &&
3300 bits_match[i].wire == pattern_chunk.wire &&
3301 bits_match[i].offset >= pattern_chunk.offset &&
3302 bits_match[i].offset < pattern_chunk.offset + pattern_chunk.width)
3303 ret.append(bits_match[i]);
3304 }
3305 }
3306
3307 ret.check();
3308 return ret;
3309 }
3310
3311 RTLIL::SigSpec RTLIL::SigSpec::extract(const pool<RTLIL::SigBit> &pattern, const RTLIL::SigSpec *other) const
3312 {
3313 if (other)
3314 cover("kernel.rtlil.sigspec.extract_other");
3315 else
3316 cover("kernel.rtlil.sigspec.extract");
3317
3318 log_assert(other == NULL || width_ == other->width_);
3319
3320 std::vector<RTLIL::SigBit> bits_match = to_sigbit_vector();
3321 RTLIL::SigSpec ret;
3322
3323 if (other) {
3324 std::vector<RTLIL::SigBit> bits_other = other->to_sigbit_vector();
3325 for (int i = 0; i < width_; i++)
3326 if (bits_match[i].wire && pattern.count(bits_match[i]))
3327 ret.append(bits_other[i]);
3328 } else {
3329 for (int i = 0; i < width_; i++)
3330 if (bits_match[i].wire && pattern.count(bits_match[i]))
3331 ret.append(bits_match[i]);
3332 }
3333
3334 ret.check();
3335 return ret;
3336 }
3337
3338 void RTLIL::SigSpec::replace(int offset, const RTLIL::SigSpec &with)
3339 {
3340 cover("kernel.rtlil.sigspec.replace_pos");
3341
3342 unpack();
3343 with.unpack();
3344
3345 log_assert(offset >= 0);
3346 log_assert(with.width_ >= 0);
3347 log_assert(offset+with.width_ <= width_);
3348
3349 for (int i = 0; i < with.width_; i++)
3350 bits_.at(offset + i) = with.bits_.at(i);
3351
3352 check();
3353 }
3354
3355 void RTLIL::SigSpec::remove_const()
3356 {
3357 if (packed())
3358 {
3359 cover("kernel.rtlil.sigspec.remove_const.packed");
3360
3361 std::vector<RTLIL::SigChunk> new_chunks;
3362 new_chunks.reserve(GetSize(chunks_));
3363
3364 width_ = 0;
3365 for (auto &chunk : chunks_)
3366 if (chunk.wire != NULL) {
3367 new_chunks.push_back(chunk);
3368 width_ += chunk.width;
3369 }
3370
3371 chunks_.swap(new_chunks);
3372 }
3373 else
3374 {
3375 cover("kernel.rtlil.sigspec.remove_const.unpacked");
3376
3377 std::vector<RTLIL::SigBit> new_bits;
3378 new_bits.reserve(width_);
3379
3380 for (auto &bit : bits_)
3381 if (bit.wire != NULL)
3382 new_bits.push_back(bit);
3383
3384 bits_.swap(new_bits);
3385 width_ = bits_.size();
3386 }
3387
3388 check();
3389 }
3390
3391 void RTLIL::SigSpec::remove(int offset, int length)
3392 {
3393 cover("kernel.rtlil.sigspec.remove_pos");
3394
3395 unpack();
3396
3397 log_assert(offset >= 0);
3398 log_assert(length >= 0);
3399 log_assert(offset + length <= width_);
3400
3401 bits_.erase(bits_.begin() + offset, bits_.begin() + offset + length);
3402 width_ = bits_.size();
3403
3404 check();
3405 }
3406
3407 RTLIL::SigSpec RTLIL::SigSpec::extract(int offset, int length) const
3408 {
3409 unpack();
3410 cover("kernel.rtlil.sigspec.extract_pos");
3411 return std::vector<RTLIL::SigBit>(bits_.begin() + offset, bits_.begin() + offset + length);
3412 }
3413
3414 void RTLIL::SigSpec::append(const RTLIL::SigSpec &signal)
3415 {
3416 if (signal.width_ == 0)
3417 return;
3418
3419 if (width_ == 0) {
3420 *this = signal;
3421 return;
3422 }
3423
3424 cover("kernel.rtlil.sigspec.append");
3425
3426 if (packed() != signal.packed()) {
3427 pack();
3428 signal.pack();
3429 }
3430
3431 if (packed())
3432 for (auto &other_c : signal.chunks_)
3433 {
3434 auto &my_last_c = chunks_.back();
3435 if (my_last_c.wire == NULL && other_c.wire == NULL) {
3436 auto &this_data = my_last_c.data;
3437 auto &other_data = other_c.data;
3438 this_data.insert(this_data.end(), other_data.begin(), other_data.end());
3439 my_last_c.width += other_c.width;
3440 } else
3441 if (my_last_c.wire == other_c.wire && my_last_c.offset + my_last_c.width == other_c.offset) {
3442 my_last_c.width += other_c.width;
3443 } else
3444 chunks_.push_back(other_c);
3445 }
3446 else
3447 bits_.insert(bits_.end(), signal.bits_.begin(), signal.bits_.end());
3448
3449 width_ += signal.width_;
3450 check();
3451 }
3452
3453 void RTLIL::SigSpec::append(const RTLIL::SigBit &bit)
3454 {
3455 if (packed())
3456 {
3457 cover("kernel.rtlil.sigspec.append_bit.packed");
3458
3459 if (chunks_.size() == 0)
3460 chunks_.push_back(bit);
3461 else
3462 if (bit.wire == NULL)
3463 if (chunks_.back().wire == NULL) {
3464 chunks_.back().data.push_back(bit.data);
3465 chunks_.back().width++;
3466 } else
3467 chunks_.push_back(bit);
3468 else
3469 if (chunks_.back().wire == bit.wire && chunks_.back().offset + chunks_.back().width == bit.offset)
3470 chunks_.back().width++;
3471 else
3472 chunks_.push_back(bit);
3473 }
3474 else
3475 {
3476 cover("kernel.rtlil.sigspec.append_bit.unpacked");
3477 bits_.push_back(bit);
3478 }
3479
3480 width_++;
3481 check();
3482 }
3483
3484 void RTLIL::SigSpec::extend_u0(int width, bool is_signed)
3485 {
3486 cover("kernel.rtlil.sigspec.extend_u0");
3487
3488 pack();
3489
3490 if (width_ > width)
3491 remove(width, width_ - width);
3492
3493 if (width_ < width) {
3494 RTLIL::SigBit padding = width_ > 0 ? (*this)[width_ - 1] : RTLIL::State::Sx;
3495 if (!is_signed)
3496 padding = RTLIL::State::S0;
3497 while (width_ < width)
3498 append(padding);
3499 }
3500
3501 }
3502
3503 RTLIL::SigSpec RTLIL::SigSpec::repeat(int num) const
3504 {
3505 cover("kernel.rtlil.sigspec.repeat");
3506
3507 RTLIL::SigSpec sig;
3508 for (int i = 0; i < num; i++)
3509 sig.append(*this);
3510 return sig;
3511 }
3512
3513 #ifndef NDEBUG
3514 void RTLIL::SigSpec::check() const
3515 {
3516 if (width_ > 64)
3517 {
3518 cover("kernel.rtlil.sigspec.check.skip");
3519 }
3520 else if (packed())
3521 {
3522 cover("kernel.rtlil.sigspec.check.packed");
3523
3524 int w = 0;
3525 for (size_t i = 0; i < chunks_.size(); i++) {
3526 const RTLIL::SigChunk &chunk = chunks_[i];
3527 if (chunk.wire == NULL) {
3528 if (i > 0)
3529 log_assert(chunks_[i-1].wire != NULL);
3530 log_assert(chunk.offset == 0);
3531 log_assert(chunk.data.size() == (size_t)chunk.width);
3532 } else {
3533 if (i > 0 && chunks_[i-1].wire == chunk.wire)
3534 log_assert(chunk.offset != chunks_[i-1].offset + chunks_[i-1].width);
3535 log_assert(chunk.offset >= 0);
3536 log_assert(chunk.width >= 0);
3537 log_assert(chunk.offset + chunk.width <= chunk.wire->width);
3538 log_assert(chunk.data.size() == 0);
3539 }
3540 w += chunk.width;
3541 }
3542 log_assert(w == width_);
3543 log_assert(bits_.empty());
3544 }
3545 else
3546 {
3547 cover("kernel.rtlil.sigspec.check.unpacked");
3548
3549 log_assert(width_ == GetSize(bits_));
3550 log_assert(chunks_.empty());
3551 }
3552 }
3553 #endif
3554
3555 bool RTLIL::SigSpec::operator <(const RTLIL::SigSpec &other) const
3556 {
3557 cover("kernel.rtlil.sigspec.comp_lt");
3558
3559 if (this == &other)
3560 return false;
3561
3562 if (width_ != other.width_)
3563 return width_ < other.width_;
3564
3565 pack();
3566 other.pack();
3567
3568 if (chunks_.size() != other.chunks_.size())
3569 return chunks_.size() < other.chunks_.size();
3570
3571 updhash();
3572 other.updhash();
3573
3574 if (hash_ != other.hash_)
3575 return hash_ < other.hash_;
3576
3577 for (size_t i = 0; i < chunks_.size(); i++)
3578 if (chunks_[i] != other.chunks_[i]) {
3579 cover("kernel.rtlil.sigspec.comp_lt.hash_collision");
3580 return chunks_[i] < other.chunks_[i];
3581 }
3582
3583 cover("kernel.rtlil.sigspec.comp_lt.equal");
3584 return false;
3585 }
3586
3587 bool RTLIL::SigSpec::operator ==(const RTLIL::SigSpec &other) const
3588 {
3589 cover("kernel.rtlil.sigspec.comp_eq");
3590
3591 if (this == &other)
3592 return true;
3593
3594 if (width_ != other.width_)
3595 return false;
3596
3597 // Without this, SigSpec() == SigSpec(State::S0, 0) will fail
3598 // since the RHS will contain one SigChunk of width 0 causing
3599 // the size check below to fail
3600 if (width_ == 0)
3601 return true;
3602
3603 pack();
3604 other.pack();
3605
3606 if (chunks_.size() != other.chunks_.size())
3607 return false;
3608
3609 updhash();
3610 other.updhash();
3611
3612 if (hash_ != other.hash_)
3613 return false;
3614
3615 for (size_t i = 0; i < chunks_.size(); i++)
3616 if (chunks_[i] != other.chunks_[i]) {
3617 cover("kernel.rtlil.sigspec.comp_eq.hash_collision");
3618 return false;
3619 }
3620
3621 cover("kernel.rtlil.sigspec.comp_eq.equal");
3622 return true;
3623 }
3624
3625 bool RTLIL::SigSpec::is_wire() const
3626 {
3627 cover("kernel.rtlil.sigspec.is_wire");
3628
3629 pack();
3630 return GetSize(chunks_) == 1 && chunks_[0].wire && chunks_[0].wire->width == width_;
3631 }
3632
3633 bool RTLIL::SigSpec::is_chunk() const
3634 {
3635 cover("kernel.rtlil.sigspec.is_chunk");
3636
3637 pack();
3638 return GetSize(chunks_) == 1;
3639 }
3640
3641 bool RTLIL::SigSpec::is_fully_const() const
3642 {
3643 cover("kernel.rtlil.sigspec.is_fully_const");
3644
3645 pack();
3646 for (auto it = chunks_.begin(); it != chunks_.end(); it++)
3647 if (it->width > 0 && it->wire != NULL)
3648 return false;
3649 return true;
3650 }
3651
3652 bool RTLIL::SigSpec::is_fully_zero() const
3653 {
3654 cover("kernel.rtlil.sigspec.is_fully_zero");
3655
3656 pack();
3657 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
3658 if (it->width > 0 && it->wire != NULL)
3659 return false;
3660 for (size_t i = 0; i < it->data.size(); i++)
3661 if (it->data[i] != RTLIL::State::S0)
3662 return false;
3663 }
3664 return true;
3665 }
3666
3667 bool RTLIL::SigSpec::is_fully_ones() const
3668 {
3669 cover("kernel.rtlil.sigspec.is_fully_ones");
3670
3671 pack();
3672 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
3673 if (it->width > 0 && it->wire != NULL)
3674 return false;
3675 for (size_t i = 0; i < it->data.size(); i++)
3676 if (it->data[i] != RTLIL::State::S1)
3677 return false;
3678 }
3679 return true;
3680 }
3681
3682 bool RTLIL::SigSpec::is_fully_def() const
3683 {
3684 cover("kernel.rtlil.sigspec.is_fully_def");
3685
3686 pack();
3687 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
3688 if (it->width > 0 && it->wire != NULL)
3689 return false;
3690 for (size_t i = 0; i < it->data.size(); i++)
3691 if (it->data[i] != RTLIL::State::S0 && it->data[i] != RTLIL::State::S1)
3692 return false;
3693 }
3694 return true;
3695 }
3696
3697 bool RTLIL::SigSpec::is_fully_undef() const
3698 {
3699 cover("kernel.rtlil.sigspec.is_fully_undef");
3700
3701 pack();
3702 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
3703 if (it->width > 0 && it->wire != NULL)
3704 return false;
3705 for (size_t i = 0; i < it->data.size(); i++)
3706 if (it->data[i] != RTLIL::State::Sx && it->data[i] != RTLIL::State::Sz)
3707 return false;
3708 }
3709 return true;
3710 }
3711
3712 bool RTLIL::SigSpec::has_const() const
3713 {
3714 cover("kernel.rtlil.sigspec.has_const");
3715
3716 pack();
3717 for (auto it = chunks_.begin(); it != chunks_.end(); it++)
3718 if (it->width > 0 && it->wire == NULL)
3719 return true;
3720 return false;
3721 }
3722
3723 bool RTLIL::SigSpec::has_marked_bits() const
3724 {
3725 cover("kernel.rtlil.sigspec.has_marked_bits");
3726
3727 pack();
3728 for (auto it = chunks_.begin(); it != chunks_.end(); it++)
3729 if (it->width > 0 && it->wire == NULL) {
3730 for (size_t i = 0; i < it->data.size(); i++)
3731 if (it->data[i] == RTLIL::State::Sm)
3732 return true;
3733 }
3734 return false;
3735 }
3736
3737 bool RTLIL::SigSpec::as_bool() const
3738 {
3739 cover("kernel.rtlil.sigspec.as_bool");
3740
3741 pack();
3742 log_assert(is_fully_const() && GetSize(chunks_) <= 1);
3743 if (width_)
3744 return RTLIL::Const(chunks_[0].data).as_bool();
3745 return false;
3746 }
3747
3748 int RTLIL::SigSpec::as_int(bool is_signed) const
3749 {
3750 cover("kernel.rtlil.sigspec.as_int");
3751
3752 pack();
3753 log_assert(is_fully_const() && GetSize(chunks_) <= 1);
3754 if (width_)
3755 return RTLIL::Const(chunks_[0].data).as_int(is_signed);
3756 return 0;
3757 }
3758
3759 std::string RTLIL::SigSpec::as_string() const
3760 {
3761 cover("kernel.rtlil.sigspec.as_string");
3762
3763 pack();
3764 std::string str;
3765 str.reserve(size());
3766 for (size_t i = chunks_.size(); i > 0; i--) {
3767 const RTLIL::SigChunk &chunk = chunks_[i-1];
3768 if (chunk.wire != NULL)
3769 str.append(chunk.width, '?');
3770 else
3771 str += RTLIL::Const(chunk.data).as_string();
3772 }
3773 return str;
3774 }
3775
3776 RTLIL::Const RTLIL::SigSpec::as_const() const
3777 {
3778 cover("kernel.rtlil.sigspec.as_const");
3779
3780 pack();
3781 log_assert(is_fully_const() && GetSize(chunks_) <= 1);
3782 if (width_)
3783 return chunks_[0].data;
3784 return RTLIL::Const();
3785 }
3786
3787 RTLIL::Wire *RTLIL::SigSpec::as_wire() const
3788 {
3789 cover("kernel.rtlil.sigspec.as_wire");
3790
3791 pack();
3792 log_assert(is_wire());
3793 return chunks_[0].wire;
3794 }
3795
3796 RTLIL::SigChunk RTLIL::SigSpec::as_chunk() const
3797 {
3798 cover("kernel.rtlil.sigspec.as_chunk");
3799
3800 pack();
3801 log_assert(is_chunk());
3802 return chunks_[0];
3803 }
3804
3805 RTLIL::SigBit RTLIL::SigSpec::as_bit() const
3806 {
3807 cover("kernel.rtlil.sigspec.as_bit");
3808
3809 log_assert(width_ == 1);
3810 if (packed())
3811 return RTLIL::SigBit(*chunks_.begin());
3812 else
3813 return bits_[0];
3814 }
3815
3816 bool RTLIL::SigSpec::match(const char* pattern) const
3817 {
3818 cover("kernel.rtlil.sigspec.match");
3819
3820 unpack();
3821 log_assert(int(strlen(pattern)) == GetSize(bits_));
3822
3823 for (auto it = bits_.rbegin(); it != bits_.rend(); it++, pattern++) {
3824 if (*pattern == ' ')
3825 continue;
3826 if (*pattern == '*') {
3827 if (*it != State::Sz && *it != State::Sx)
3828 return false;
3829 continue;
3830 }
3831 if (*pattern == '0') {
3832 if (*it != State::S0)
3833 return false;
3834 } else
3835 if (*pattern == '1') {
3836 if (*it != State::S1)
3837 return false;
3838 } else
3839 log_abort();
3840 }
3841
3842 return true;
3843 }
3844
3845 std::set<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_set() const
3846 {
3847 cover("kernel.rtlil.sigspec.to_sigbit_set");
3848
3849 pack();
3850 std::set<RTLIL::SigBit> sigbits;
3851 for (auto &c : chunks_)
3852 for (int i = 0; i < c.width; i++)
3853 sigbits.insert(RTLIL::SigBit(c, i));
3854 return sigbits;
3855 }
3856
3857 pool<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_pool() const
3858 {
3859 cover("kernel.rtlil.sigspec.to_sigbit_pool");
3860
3861 pack();
3862 pool<RTLIL::SigBit> sigbits;
3863 sigbits.reserve(size());
3864 for (auto &c : chunks_)
3865 for (int i = 0; i < c.width; i++)
3866 sigbits.insert(RTLIL::SigBit(c, i));
3867 return sigbits;
3868 }
3869
3870 std::vector<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_vector() const
3871 {
3872 cover("kernel.rtlil.sigspec.to_sigbit_vector");
3873
3874 unpack();
3875 return bits_;
3876 }
3877
3878 std::map<RTLIL::SigBit, RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_map(const RTLIL::SigSpec &other) const
3879 {
3880 cover("kernel.rtlil.sigspec.to_sigbit_map");
3881
3882 unpack();
3883 other.unpack();
3884
3885 log_assert(width_ == other.width_);
3886
3887 std::map<RTLIL::SigBit, RTLIL::SigBit> new_map;
3888 for (int i = 0; i < width_; i++)
3889 new_map[bits_[i]] = other.bits_[i];
3890
3891 return new_map;
3892 }
3893
3894 dict<RTLIL::SigBit, RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_dict(const RTLIL::SigSpec &other) const
3895 {
3896 cover("kernel.rtlil.sigspec.to_sigbit_dict");
3897
3898 unpack();
3899 other.unpack();
3900
3901 log_assert(width_ == other.width_);
3902
3903 dict<RTLIL::SigBit, RTLIL::SigBit> new_map;
3904 new_map.reserve(size());
3905 for (int i = 0; i < width_; i++)
3906 new_map[bits_[i]] = other.bits_[i];
3907
3908 return new_map;
3909 }
3910
3911 static void sigspec_parse_split(std::vector<std::string> &tokens, const std::string &text, char sep)
3912 {
3913 size_t start = 0, end = 0;
3914 while ((end = text.find(sep, start)) != std::string::npos) {
3915 tokens.push_back(text.substr(start, end - start));
3916 start = end + 1;
3917 }
3918 tokens.push_back(text.substr(start));
3919 }
3920
3921 static int sigspec_parse_get_dummy_line_num()
3922 {
3923 return 0;
3924 }
3925
3926 bool RTLIL::SigSpec::parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str)
3927 {
3928 cover("kernel.rtlil.sigspec.parse");
3929
3930 AST::current_filename = "input";
3931
3932 std::vector<std::string> tokens;
3933 sigspec_parse_split(tokens, str, ',');
3934
3935 sig = RTLIL::SigSpec();
3936 for (int tokidx = int(tokens.size())-1; tokidx >= 0; tokidx--)
3937 {
3938 std::string netname = tokens[tokidx];
3939 std::string indices;
3940
3941 if (netname.size() == 0)
3942 continue;
3943
3944 if (('0' <= netname[0] && netname[0] <= '9') || netname[0] == '\'') {
3945 cover("kernel.rtlil.sigspec.parse.const");
3946 AST::get_line_num = sigspec_parse_get_dummy_line_num;
3947 AST::AstNode *ast = VERILOG_FRONTEND::const2ast(netname);
3948 if (ast == NULL)
3949 return false;
3950 sig.append(RTLIL::Const(ast->bits));
3951 delete ast;
3952 continue;
3953 }
3954
3955 if (module == NULL)
3956 return false;
3957
3958 cover("kernel.rtlil.sigspec.parse.net");
3959
3960 if (netname[0] != '$' && netname[0] != '\\')
3961 netname = "\\" + netname;
3962
3963 if (module->wires_.count(netname) == 0) {
3964 size_t indices_pos = netname.size()-1;
3965 if (indices_pos > 2 && netname[indices_pos] == ']')
3966 {
3967 indices_pos--;
3968 while (indices_pos > 0 && ('0' <= netname[indices_pos] && netname[indices_pos] <= '9')) indices_pos--;
3969 if (indices_pos > 0 && netname[indices_pos] == ':') {
3970 indices_pos--;
3971 while (indices_pos > 0 && ('0' <= netname[indices_pos] && netname[indices_pos] <= '9')) indices_pos--;
3972 }
3973 if (indices_pos > 0 && netname[indices_pos] == '[') {
3974 indices = netname.substr(indices_pos);
3975 netname = netname.substr(0, indices_pos);
3976 }
3977 }
3978 }
3979
3980 if (module->wires_.count(netname) == 0)
3981 return false;
3982
3983 RTLIL::Wire *wire = module->wires_.at(netname);
3984 if (!indices.empty()) {
3985 std::vector<std::string> index_tokens;
3986 sigspec_parse_split(index_tokens, indices.substr(1, indices.size()-2), ':');
3987 if (index_tokens.size() == 1) {
3988 cover("kernel.rtlil.sigspec.parse.bit_sel");
3989 int a = atoi(index_tokens.at(0).c_str());
3990 if (a < 0 || a >= wire->width)
3991 return false;
3992 sig.append(RTLIL::SigSpec(wire, a));
3993 } else {
3994 cover("kernel.rtlil.sigspec.parse.part_sel");
3995 int a = atoi(index_tokens.at(0).c_str());
3996 int b = atoi(index_tokens.at(1).c_str());
3997 if (a > b) {
3998 int tmp = a;
3999 a = b, b = tmp;
4000 }
4001 if (a < 0 || a >= wire->width)
4002 return false;
4003 if (b < 0 || b >= wire->width)
4004 return false;
4005 sig.append(RTLIL::SigSpec(wire, a, b-a+1));
4006 }
4007 } else
4008 sig.append(wire);
4009 }
4010
4011 return true;
4012 }
4013
4014 bool RTLIL::SigSpec::parse_sel(RTLIL::SigSpec &sig, RTLIL::Design *design, RTLIL::Module *module, std::string str)
4015 {
4016 if (str.empty() || str[0] != '@')
4017 return parse(sig, module, str);
4018
4019 cover("kernel.rtlil.sigspec.parse.sel");
4020
4021 str = RTLIL::escape_id(str.substr(1));
4022 if (design->selection_vars.count(str) == 0)
4023 return false;
4024
4025 sig = RTLIL::SigSpec();
4026 RTLIL::Selection &sel = design->selection_vars.at(str);
4027 for (auto &it : module->wires_)
4028 if (sel.selected_member(module->name, it.first))
4029 sig.append(it.second);
4030
4031 return true;
4032 }
4033
4034 bool RTLIL::SigSpec::parse_rhs(const RTLIL::SigSpec &lhs, RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str)
4035 {
4036 if (str == "0") {
4037 cover("kernel.rtlil.sigspec.parse.rhs_zeros");
4038 sig = RTLIL::SigSpec(RTLIL::State::S0, lhs.width_);
4039 return true;
4040 }
4041
4042 if (str == "~0") {
4043 cover("kernel.rtlil.sigspec.parse.rhs_ones");
4044 sig = RTLIL::SigSpec(RTLIL::State::S1, lhs.width_);
4045 return true;
4046 }
4047
4048 if (lhs.chunks_.size() == 1) {
4049 char *p = (char*)str.c_str(), *endptr;
4050 long int val = strtol(p, &endptr, 10);
4051 if (endptr && endptr != p && *endptr == 0) {
4052 sig = RTLIL::SigSpec(val, lhs.width_);
4053 cover("kernel.rtlil.sigspec.parse.rhs_dec");
4054 return true;
4055 }
4056 }
4057
4058 return parse(sig, module, str);
4059 }
4060
4061 RTLIL::CaseRule::~CaseRule()
4062 {
4063 for (auto it = switches.begin(); it != switches.end(); it++)
4064 delete *it;
4065 }
4066
4067 bool RTLIL::CaseRule::empty() const
4068 {
4069 return actions.empty() && switches.empty();
4070 }
4071
4072 RTLIL::CaseRule *RTLIL::CaseRule::clone() const
4073 {
4074 RTLIL::CaseRule *new_caserule = new RTLIL::CaseRule;
4075 new_caserule->compare = compare;
4076 new_caserule->actions = actions;
4077 for (auto &it : switches)
4078 new_caserule->switches.push_back(it->clone());
4079 return new_caserule;
4080 }
4081
4082 RTLIL::SwitchRule::~SwitchRule()
4083 {
4084 for (auto it = cases.begin(); it != cases.end(); it++)
4085 delete *it;
4086 }
4087
4088 bool RTLIL::SwitchRule::empty() const
4089 {
4090 return cases.empty();
4091 }
4092
4093 RTLIL::SwitchRule *RTLIL::SwitchRule::clone() const
4094 {
4095 RTLIL::SwitchRule *new_switchrule = new RTLIL::SwitchRule;
4096 new_switchrule->signal = signal;
4097 new_switchrule->attributes = attributes;
4098 for (auto &it : cases)
4099 new_switchrule->cases.push_back(it->clone());
4100 return new_switchrule;
4101
4102 }
4103
4104 RTLIL::SyncRule *RTLIL::SyncRule::clone() const
4105 {
4106 RTLIL::SyncRule *new_syncrule = new RTLIL::SyncRule;
4107 new_syncrule->type = type;
4108 new_syncrule->signal = signal;
4109 new_syncrule->actions = actions;
4110 return new_syncrule;
4111 }
4112
4113 RTLIL::Process::~Process()
4114 {
4115 for (auto it = syncs.begin(); it != syncs.end(); it++)
4116 delete *it;
4117 }
4118
4119 RTLIL::Process *RTLIL::Process::clone() const
4120 {
4121 RTLIL::Process *new_proc = new RTLIL::Process;
4122
4123 new_proc->name = name;
4124 new_proc->attributes = attributes;
4125
4126 RTLIL::CaseRule *rc_ptr = root_case.clone();
4127 new_proc->root_case = *rc_ptr;
4128 rc_ptr->switches.clear();
4129 delete rc_ptr;
4130
4131 for (auto &it : syncs)
4132 new_proc->syncs.push_back(it->clone());
4133
4134 return new_proc;
4135 }
4136
4137 #ifdef WITH_PYTHON
4138 RTLIL::Memory::~Memory()
4139 {
4140 RTLIL::Memory::get_all_memorys()->erase(hashidx_);
4141 }
4142 static std::map<unsigned int, RTLIL::Memory*> all_memorys;
4143 std::map<unsigned int, RTLIL::Memory*> *RTLIL::Memory::get_all_memorys(void)
4144 {
4145 return &all_memorys;
4146 }
4147 #endif
4148 YOSYS_NAMESPACE_END