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Add $specrule cells for $setup/$hold/$skew specify rules
[yosys.git] / kernel / rtlil.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 #include "kernel/yosys.h"
21 #include "kernel/macc.h"
22 #include "kernel/celltypes.h"
23 #include "frontends/verilog/verilog_frontend.h"
24 #include "backends/ilang/ilang_backend.h"
25
26 #include <string.h>
27 #include <algorithm>
28
29 YOSYS_NAMESPACE_BEGIN
30
31 RTLIL::IdString::destruct_guard_t RTLIL::IdString::destruct_guard;
32 std::vector<int> RTLIL::IdString::global_refcount_storage_;
33 std::vector<char*> RTLIL::IdString::global_id_storage_;
34 dict<char*, int, hash_cstr_ops> RTLIL::IdString::global_id_index_;
35 std::vector<int> RTLIL::IdString::global_free_idx_list_;
36 int RTLIL::IdString::last_created_idx_[8];
37 int RTLIL::IdString::last_created_idx_ptr_;
38
39 RTLIL::Const::Const()
40 {
41 flags = RTLIL::CONST_FLAG_NONE;
42 }
43
44 RTLIL::Const::Const(std::string str)
45 {
46 flags = RTLIL::CONST_FLAG_STRING;
47 for (int i = str.size()-1; i >= 0; i--) {
48 unsigned char ch = str[i];
49 for (int j = 0; j < 8; j++) {
50 bits.push_back((ch & 1) != 0 ? RTLIL::S1 : RTLIL::S0);
51 ch = ch >> 1;
52 }
53 }
54 }
55
56 RTLIL::Const::Const(int val, int width)
57 {
58 flags = RTLIL::CONST_FLAG_NONE;
59 for (int i = 0; i < width; i++) {
60 bits.push_back((val & 1) != 0 ? RTLIL::S1 : RTLIL::S0);
61 val = val >> 1;
62 }
63 }
64
65 RTLIL::Const::Const(RTLIL::State bit, int width)
66 {
67 flags = RTLIL::CONST_FLAG_NONE;
68 for (int i = 0; i < width; i++)
69 bits.push_back(bit);
70 }
71
72 RTLIL::Const::Const(const std::vector<bool> &bits)
73 {
74 flags = RTLIL::CONST_FLAG_NONE;
75 for (auto b : bits)
76 this->bits.push_back(b ? RTLIL::S1 : RTLIL::S0);
77 }
78
79 RTLIL::Const::Const(const RTLIL::Const &c)
80 {
81 flags = c.flags;
82 for (auto b : c.bits)
83 this->bits.push_back(b);
84 }
85
86 bool RTLIL::Const::operator <(const RTLIL::Const &other) const
87 {
88 if (bits.size() != other.bits.size())
89 return bits.size() < other.bits.size();
90 for (size_t i = 0; i < bits.size(); i++)
91 if (bits[i] != other.bits[i])
92 return bits[i] < other.bits[i];
93 return false;
94 }
95
96 bool RTLIL::Const::operator ==(const RTLIL::Const &other) const
97 {
98 return bits == other.bits;
99 }
100
101 bool RTLIL::Const::operator !=(const RTLIL::Const &other) const
102 {
103 return bits != other.bits;
104 }
105
106 bool RTLIL::Const::as_bool() const
107 {
108 for (size_t i = 0; i < bits.size(); i++)
109 if (bits[i] == RTLIL::S1)
110 return true;
111 return false;
112 }
113
114 int RTLIL::Const::as_int(bool is_signed) const
115 {
116 int32_t ret = 0;
117 for (size_t i = 0; i < bits.size() && i < 32; i++)
118 if (bits[i] == RTLIL::S1)
119 ret |= 1 << i;
120 if (is_signed && bits.back() == RTLIL::S1)
121 for (size_t i = bits.size(); i < 32; i++)
122 ret |= 1 << i;
123 return ret;
124 }
125
126 std::string RTLIL::Const::as_string() const
127 {
128 std::string ret;
129 for (size_t i = bits.size(); i > 0; i--)
130 switch (bits[i-1]) {
131 case S0: ret += "0"; break;
132 case S1: ret += "1"; break;
133 case Sx: ret += "x"; break;
134 case Sz: ret += "z"; break;
135 case Sa: ret += "-"; break;
136 case Sm: ret += "m"; break;
137 }
138 return ret;
139 }
140
141 RTLIL::Const RTLIL::Const::from_string(std::string str)
142 {
143 Const c;
144 for (auto it = str.rbegin(); it != str.rend(); it++)
145 switch (*it) {
146 case '0': c.bits.push_back(State::S0); break;
147 case '1': c.bits.push_back(State::S1); break;
148 case 'x': c.bits.push_back(State::Sx); break;
149 case 'z': c.bits.push_back(State::Sz); break;
150 case 'm': c.bits.push_back(State::Sm); break;
151 default: c.bits.push_back(State::Sa);
152 }
153 return c;
154 }
155
156 std::string RTLIL::Const::decode_string() const
157 {
158 std::string string;
159 std::vector<char> string_chars;
160 for (int i = 0; i < int (bits.size()); i += 8) {
161 char ch = 0;
162 for (int j = 0; j < 8 && i + j < int (bits.size()); j++)
163 if (bits[i + j] == RTLIL::State::S1)
164 ch |= 1 << j;
165 if (ch != 0)
166 string_chars.push_back(ch);
167 }
168 for (int i = int (string_chars.size()) - 1; i >= 0; i--)
169 string += string_chars[i];
170 return string;
171 }
172
173 bool RTLIL::Const::is_fully_zero() const
174 {
175 cover("kernel.rtlil.const.is_fully_zero");
176
177 for (auto bit : bits)
178 if (bit != RTLIL::State::S0)
179 return false;
180
181 return true;
182 }
183
184 bool RTLIL::Const::is_fully_ones() const
185 {
186 cover("kernel.rtlil.const.is_fully_ones");
187
188 for (auto bit : bits)
189 if (bit != RTLIL::State::S1)
190 return false;
191
192 return true;
193 }
194
195 bool RTLIL::Const::is_fully_def() const
196 {
197 cover("kernel.rtlil.const.is_fully_def");
198
199 for (auto bit : bits)
200 if (bit != RTLIL::State::S0 && bit != RTLIL::State::S1)
201 return false;
202
203 return true;
204 }
205
206 bool RTLIL::Const::is_fully_undef() const
207 {
208 cover("kernel.rtlil.const.is_fully_undef");
209
210 for (auto bit : bits)
211 if (bit != RTLIL::State::Sx && bit != RTLIL::State::Sz)
212 return false;
213
214 return true;
215 }
216
217 void RTLIL::AttrObject::set_bool_attribute(RTLIL::IdString id, bool value)
218 {
219 if (value)
220 attributes[id] = RTLIL::Const(1);
221 else if (attributes.count(id))
222 attributes.erase(id);
223 }
224
225 bool RTLIL::AttrObject::get_bool_attribute(RTLIL::IdString id) const
226 {
227 if (attributes.count(id) == 0)
228 return false;
229 return attributes.at(id).as_bool();
230 }
231
232 void RTLIL::AttrObject::set_strpool_attribute(RTLIL::IdString id, const pool<string> &data)
233 {
234 string attrval;
235 for (auto &s : data) {
236 if (!attrval.empty())
237 attrval += "|";
238 attrval += s;
239 }
240 attributes[id] = RTLIL::Const(attrval);
241 }
242
243 void RTLIL::AttrObject::add_strpool_attribute(RTLIL::IdString id, const pool<string> &data)
244 {
245 pool<string> union_data = get_strpool_attribute(id);
246 union_data.insert(data.begin(), data.end());
247 if (!union_data.empty())
248 set_strpool_attribute(id, union_data);
249 }
250
251 pool<string> RTLIL::AttrObject::get_strpool_attribute(RTLIL::IdString id) const
252 {
253 pool<string> data;
254 if (attributes.count(id) != 0)
255 for (auto s : split_tokens(attributes.at(id).decode_string(), "|"))
256 data.insert(s);
257 return data;
258 }
259
260 void RTLIL::AttrObject::set_src_attribute(const std::string &src)
261 {
262 if (src.empty())
263 attributes.erase("\\src");
264 else
265 attributes["\\src"] = src;
266 }
267
268 std::string RTLIL::AttrObject::get_src_attribute() const
269 {
270 std::string src;
271 if (attributes.count("\\src"))
272 src = attributes.at("\\src").decode_string();
273 return src;
274 }
275
276 bool RTLIL::Selection::selected_module(RTLIL::IdString mod_name) const
277 {
278 if (full_selection)
279 return true;
280 if (selected_modules.count(mod_name) > 0)
281 return true;
282 if (selected_members.count(mod_name) > 0)
283 return true;
284 return false;
285 }
286
287 bool RTLIL::Selection::selected_whole_module(RTLIL::IdString mod_name) const
288 {
289 if (full_selection)
290 return true;
291 if (selected_modules.count(mod_name) > 0)
292 return true;
293 return false;
294 }
295
296 bool RTLIL::Selection::selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const
297 {
298 if (full_selection)
299 return true;
300 if (selected_modules.count(mod_name) > 0)
301 return true;
302 if (selected_members.count(mod_name) > 0)
303 if (selected_members.at(mod_name).count(memb_name) > 0)
304 return true;
305 return false;
306 }
307
308 void RTLIL::Selection::optimize(RTLIL::Design *design)
309 {
310 if (full_selection) {
311 selected_modules.clear();
312 selected_members.clear();
313 return;
314 }
315
316 std::vector<RTLIL::IdString> del_list, add_list;
317
318 del_list.clear();
319 for (auto mod_name : selected_modules) {
320 if (design->modules_.count(mod_name) == 0)
321 del_list.push_back(mod_name);
322 selected_members.erase(mod_name);
323 }
324 for (auto mod_name : del_list)
325 selected_modules.erase(mod_name);
326
327 del_list.clear();
328 for (auto &it : selected_members)
329 if (design->modules_.count(it.first) == 0)
330 del_list.push_back(it.first);
331 for (auto mod_name : del_list)
332 selected_members.erase(mod_name);
333
334 for (auto &it : selected_members) {
335 del_list.clear();
336 for (auto memb_name : it.second)
337 if (design->modules_[it.first]->count_id(memb_name) == 0)
338 del_list.push_back(memb_name);
339 for (auto memb_name : del_list)
340 it.second.erase(memb_name);
341 }
342
343 del_list.clear();
344 add_list.clear();
345 for (auto &it : selected_members)
346 if (it.second.size() == 0)
347 del_list.push_back(it.first);
348 else if (it.second.size() == design->modules_[it.first]->wires_.size() + design->modules_[it.first]->memories.size() +
349 design->modules_[it.first]->cells_.size() + design->modules_[it.first]->processes.size())
350 add_list.push_back(it.first);
351 for (auto mod_name : del_list)
352 selected_members.erase(mod_name);
353 for (auto mod_name : add_list) {
354 selected_members.erase(mod_name);
355 selected_modules.insert(mod_name);
356 }
357
358 if (selected_modules.size() == design->modules_.size()) {
359 full_selection = true;
360 selected_modules.clear();
361 selected_members.clear();
362 }
363 }
364
365 RTLIL::Design::Design()
366 {
367 static unsigned int hashidx_count = 123456789;
368 hashidx_count = mkhash_xorshift(hashidx_count);
369 hashidx_ = hashidx_count;
370
371 refcount_modules_ = 0;
372 selection_stack.push_back(RTLIL::Selection());
373
374 #ifdef WITH_PYTHON
375 RTLIL::Design::get_all_designs()->insert(std::pair<unsigned int, RTLIL::Design*>(hashidx_, this));
376 #endif
377 }
378
379 RTLIL::Design::~Design()
380 {
381 for (auto it = modules_.begin(); it != modules_.end(); ++it)
382 delete it->second;
383 for (auto n : verilog_packages)
384 delete n;
385 for (auto n : verilog_globals)
386 delete n;
387 #ifdef WITH_PYTHON
388 RTLIL::Design::get_all_designs()->erase(hashidx_);
389 #endif
390 }
391
392 #ifdef WITH_PYTHON
393 static std::map<unsigned int, RTLIL::Design*> all_designs;
394 std::map<unsigned int, RTLIL::Design*> *RTLIL::Design::get_all_designs(void)
395 {
396 return &all_designs;
397 }
398 #endif
399
400 RTLIL::ObjRange<RTLIL::Module*> RTLIL::Design::modules()
401 {
402 return RTLIL::ObjRange<RTLIL::Module*>(&modules_, &refcount_modules_);
403 }
404
405 RTLIL::Module *RTLIL::Design::module(RTLIL::IdString name)
406 {
407 return modules_.count(name) ? modules_.at(name) : NULL;
408 }
409
410 RTLIL::Module *RTLIL::Design::top_module()
411 {
412 RTLIL::Module *module = nullptr;
413 int module_count = 0;
414
415 for (auto mod : selected_modules()) {
416 if (mod->get_bool_attribute("\\top"))
417 return mod;
418 module_count++;
419 module = mod;
420 }
421
422 return module_count == 1 ? module : nullptr;
423 }
424
425 void RTLIL::Design::add(RTLIL::Module *module)
426 {
427 log_assert(modules_.count(module->name) == 0);
428 log_assert(refcount_modules_ == 0);
429 modules_[module->name] = module;
430 module->design = this;
431
432 for (auto mon : monitors)
433 mon->notify_module_add(module);
434
435 if (yosys_xtrace) {
436 log("#X# New Module: %s\n", log_id(module));
437 log_backtrace("-X- ", yosys_xtrace-1);
438 }
439 }
440
441 RTLIL::Module *RTLIL::Design::addModule(RTLIL::IdString name)
442 {
443 log_assert(modules_.count(name) == 0);
444 log_assert(refcount_modules_ == 0);
445
446 RTLIL::Module *module = new RTLIL::Module;
447 modules_[name] = module;
448 module->design = this;
449 module->name = name;
450
451 for (auto mon : monitors)
452 mon->notify_module_add(module);
453
454 if (yosys_xtrace) {
455 log("#X# New Module: %s\n", log_id(module));
456 log_backtrace("-X- ", yosys_xtrace-1);
457 }
458
459 return module;
460 }
461
462 void RTLIL::Design::scratchpad_unset(std::string varname)
463 {
464 scratchpad.erase(varname);
465 }
466
467 void RTLIL::Design::scratchpad_set_int(std::string varname, int value)
468 {
469 scratchpad[varname] = stringf("%d", value);
470 }
471
472 void RTLIL::Design::scratchpad_set_bool(std::string varname, bool value)
473 {
474 scratchpad[varname] = value ? "true" : "false";
475 }
476
477 void RTLIL::Design::scratchpad_set_string(std::string varname, std::string value)
478 {
479 scratchpad[varname] = value;
480 }
481
482 int RTLIL::Design::scratchpad_get_int(std::string varname, int default_value) const
483 {
484 if (scratchpad.count(varname) == 0)
485 return default_value;
486
487 std::string str = scratchpad.at(varname);
488
489 if (str == "0" || str == "false")
490 return 0;
491
492 if (str == "1" || str == "true")
493 return 1;
494
495 char *endptr = nullptr;
496 long int parsed_value = strtol(str.c_str(), &endptr, 10);
497 return *endptr ? default_value : parsed_value;
498 }
499
500 bool RTLIL::Design::scratchpad_get_bool(std::string varname, bool default_value) const
501 {
502 if (scratchpad.count(varname) == 0)
503 return default_value;
504
505 std::string str = scratchpad.at(varname);
506
507 if (str == "0" || str == "false")
508 return false;
509
510 if (str == "1" || str == "true")
511 return true;
512
513 return default_value;
514 }
515
516 std::string RTLIL::Design::scratchpad_get_string(std::string varname, std::string default_value) const
517 {
518 if (scratchpad.count(varname) == 0)
519 return default_value;
520 return scratchpad.at(varname);
521 }
522
523 void RTLIL::Design::remove(RTLIL::Module *module)
524 {
525 for (auto mon : monitors)
526 mon->notify_module_del(module);
527
528 if (yosys_xtrace) {
529 log("#X# Remove Module: %s\n", log_id(module));
530 log_backtrace("-X- ", yosys_xtrace-1);
531 }
532
533 log_assert(modules_.at(module->name) == module);
534 modules_.erase(module->name);
535 delete module;
536 }
537
538 void RTLIL::Design::rename(RTLIL::Module *module, RTLIL::IdString new_name)
539 {
540 modules_.erase(module->name);
541 module->name = new_name;
542 add(module);
543 }
544
545 void RTLIL::Design::sort()
546 {
547 scratchpad.sort();
548 modules_.sort(sort_by_id_str());
549 for (auto &it : modules_)
550 it.second->sort();
551 }
552
553 void RTLIL::Design::check()
554 {
555 #ifndef NDEBUG
556 for (auto &it : modules_) {
557 log_assert(this == it.second->design);
558 log_assert(it.first == it.second->name);
559 log_assert(!it.first.empty());
560 it.second->check();
561 }
562 #endif
563 }
564
565 void RTLIL::Design::optimize()
566 {
567 for (auto &it : modules_)
568 it.second->optimize();
569 for (auto &it : selection_stack)
570 it.optimize(this);
571 for (auto &it : selection_vars)
572 it.second.optimize(this);
573 }
574
575 bool RTLIL::Design::selected_module(RTLIL::IdString mod_name) const
576 {
577 if (!selected_active_module.empty() && mod_name != selected_active_module)
578 return false;
579 if (selection_stack.size() == 0)
580 return true;
581 return selection_stack.back().selected_module(mod_name);
582 }
583
584 bool RTLIL::Design::selected_whole_module(RTLIL::IdString mod_name) const
585 {
586 if (!selected_active_module.empty() && mod_name != selected_active_module)
587 return false;
588 if (selection_stack.size() == 0)
589 return true;
590 return selection_stack.back().selected_whole_module(mod_name);
591 }
592
593 bool RTLIL::Design::selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const
594 {
595 if (!selected_active_module.empty() && mod_name != selected_active_module)
596 return false;
597 if (selection_stack.size() == 0)
598 return true;
599 return selection_stack.back().selected_member(mod_name, memb_name);
600 }
601
602 bool RTLIL::Design::selected_module(RTLIL::Module *mod) const
603 {
604 return selected_module(mod->name);
605 }
606
607 bool RTLIL::Design::selected_whole_module(RTLIL::Module *mod) const
608 {
609 return selected_whole_module(mod->name);
610 }
611
612 std::vector<RTLIL::Module*> RTLIL::Design::selected_modules() const
613 {
614 std::vector<RTLIL::Module*> result;
615 result.reserve(modules_.size());
616 for (auto &it : modules_)
617 if (selected_module(it.first) && !it.second->get_blackbox_attribute())
618 result.push_back(it.second);
619 return result;
620 }
621
622 std::vector<RTLIL::Module*> RTLIL::Design::selected_whole_modules() const
623 {
624 std::vector<RTLIL::Module*> result;
625 result.reserve(modules_.size());
626 for (auto &it : modules_)
627 if (selected_whole_module(it.first) && !it.second->get_blackbox_attribute())
628 result.push_back(it.second);
629 return result;
630 }
631
632 std::vector<RTLIL::Module*> RTLIL::Design::selected_whole_modules_warn() const
633 {
634 std::vector<RTLIL::Module*> result;
635 result.reserve(modules_.size());
636 for (auto &it : modules_)
637 if (it.second->get_blackbox_attribute())
638 continue;
639 else if (selected_whole_module(it.first))
640 result.push_back(it.second);
641 else if (selected_module(it.first))
642 log_warning("Ignoring partially selected module %s.\n", log_id(it.first));
643 return result;
644 }
645
646 RTLIL::Module::Module()
647 {
648 static unsigned int hashidx_count = 123456789;
649 hashidx_count = mkhash_xorshift(hashidx_count);
650 hashidx_ = hashidx_count;
651
652 design = nullptr;
653 refcount_wires_ = 0;
654 refcount_cells_ = 0;
655
656 #ifdef WITH_PYTHON
657 RTLIL::Module::get_all_modules()->insert(std::pair<unsigned int, RTLIL::Module*>(hashidx_, this));
658 #endif
659 }
660
661 RTLIL::Module::~Module()
662 {
663 for (auto it = wires_.begin(); it != wires_.end(); ++it)
664 delete it->second;
665 for (auto it = memories.begin(); it != memories.end(); ++it)
666 delete it->second;
667 for (auto it = cells_.begin(); it != cells_.end(); ++it)
668 delete it->second;
669 for (auto it = processes.begin(); it != processes.end(); ++it)
670 delete it->second;
671 #ifdef WITH_PYTHON
672 RTLIL::Module::get_all_modules()->erase(hashidx_);
673 #endif
674 }
675
676 #ifdef WITH_PYTHON
677 static std::map<unsigned int, RTLIL::Module*> all_modules;
678 std::map<unsigned int, RTLIL::Module*> *RTLIL::Module::get_all_modules(void)
679 {
680 return &all_modules;
681 }
682 #endif
683
684 void RTLIL::Module::makeblackbox()
685 {
686 pool<RTLIL::Wire*> delwires;
687
688 for (auto it = wires_.begin(); it != wires_.end(); ++it)
689 if (!it->second->port_input && !it->second->port_output)
690 delwires.insert(it->second);
691
692 for (auto it = memories.begin(); it != memories.end(); ++it)
693 delete it->second;
694 memories.clear();
695
696 for (auto it = cells_.begin(); it != cells_.end(); ++it)
697 delete it->second;
698 cells_.clear();
699
700 for (auto it = processes.begin(); it != processes.end(); ++it)
701 delete it->second;
702 processes.clear();
703
704 remove(delwires);
705 set_bool_attribute("\\blackbox");
706 }
707
708 void RTLIL::Module::reprocess_module(RTLIL::Design *, dict<RTLIL::IdString, RTLIL::Module *>)
709 {
710 log_error("Cannot reprocess_module module `%s' !\n", id2cstr(name));
711 }
712
713 RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, dict<RTLIL::IdString, RTLIL::Const>, bool mayfail)
714 {
715 if (mayfail)
716 return RTLIL::IdString();
717 log_error("Module `%s' is used with parameters but is not parametric!\n", id2cstr(name));
718 }
719
720
721 RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, dict<RTLIL::IdString, RTLIL::Const>, dict<RTLIL::IdString, RTLIL::Module*>, dict<RTLIL::IdString, RTLIL::IdString>, bool mayfail)
722 {
723 if (mayfail)
724 return RTLIL::IdString();
725 log_error("Module `%s' is used with parameters but is not parametric!\n", id2cstr(name));
726 }
727
728 size_t RTLIL::Module::count_id(RTLIL::IdString id)
729 {
730 return wires_.count(id) + memories.count(id) + cells_.count(id) + processes.count(id);
731 }
732
733 #ifndef NDEBUG
734 namespace {
735 struct InternalCellChecker
736 {
737 RTLIL::Module *module;
738 RTLIL::Cell *cell;
739 pool<RTLIL::IdString> expected_params, expected_ports;
740
741 InternalCellChecker(RTLIL::Module *module, RTLIL::Cell *cell) : module(module), cell(cell) { }
742
743 void error(int linenr)
744 {
745 std::stringstream buf;
746 ILANG_BACKEND::dump_cell(buf, " ", cell);
747
748 log_error("Found error in internal cell %s%s%s (%s) at %s:%d:\n%s",
749 module ? module->name.c_str() : "", module ? "." : "",
750 cell->name.c_str(), cell->type.c_str(), __FILE__, linenr, buf.str().c_str());
751 }
752
753 int param(const char *name)
754 {
755 if (cell->parameters.count(name) == 0)
756 error(__LINE__);
757 expected_params.insert(name);
758 return cell->parameters.at(name).as_int();
759 }
760
761 int param_bool(const char *name)
762 {
763 int v = param(name);
764 if (cell->parameters.at(name).bits.size() > 32)
765 error(__LINE__);
766 if (v != 0 && v != 1)
767 error(__LINE__);
768 return v;
769 }
770
771 void param_bits(const char *name, int width)
772 {
773 param(name);
774 if (int(cell->parameters.at(name).bits.size()) != width)
775 error(__LINE__);
776 }
777
778 void port(const char *name, int width)
779 {
780 if (!cell->hasPort(name))
781 error(__LINE__);
782 if (cell->getPort(name).size() != width)
783 error(__LINE__);
784 expected_ports.insert(name);
785 }
786
787 void check_expected(bool check_matched_sign = true)
788 {
789 for (auto &para : cell->parameters)
790 if (expected_params.count(para.first) == 0)
791 error(__LINE__);
792 for (auto &conn : cell->connections())
793 if (expected_ports.count(conn.first) == 0)
794 error(__LINE__);
795
796 if (expected_params.count("\\A_SIGNED") != 0 && expected_params.count("\\B_SIGNED") && check_matched_sign) {
797 bool a_is_signed = param("\\A_SIGNED") != 0;
798 bool b_is_signed = param("\\B_SIGNED") != 0;
799 if (a_is_signed != b_is_signed)
800 error(__LINE__);
801 }
802 }
803
804 void check_gate(const char *ports)
805 {
806 if (cell->parameters.size() != 0)
807 error(__LINE__);
808
809 for (const char *p = ports; *p; p++) {
810 char portname[3] = { '\\', *p, 0 };
811 if (!cell->hasPort(portname))
812 error(__LINE__);
813 if (cell->getPort(portname).size() != 1)
814 error(__LINE__);
815 }
816
817 for (auto &conn : cell->connections()) {
818 if (conn.first.size() != 2 || conn.first[0] != '\\')
819 error(__LINE__);
820 if (strchr(ports, conn.first[1]) == NULL)
821 error(__LINE__);
822 }
823 }
824
825 void check()
826 {
827 if (cell->type.substr(0, 1) != "$" || cell->type.substr(0, 3) == "$__" || cell->type.substr(0, 8) == "$paramod" || cell->type.substr(0,10) == "$fmcombine" ||
828 cell->type.substr(0, 9) == "$verific$" || cell->type.substr(0, 7) == "$array:" || cell->type.substr(0, 8) == "$extern:")
829 return;
830
831 if (cell->type.in("$not", "$pos", "$neg")) {
832 param_bool("\\A_SIGNED");
833 port("\\A", param("\\A_WIDTH"));
834 port("\\Y", param("\\Y_WIDTH"));
835 check_expected();
836 return;
837 }
838
839 if (cell->type.in("$and", "$or", "$xor", "$xnor")) {
840 param_bool("\\A_SIGNED");
841 param_bool("\\B_SIGNED");
842 port("\\A", param("\\A_WIDTH"));
843 port("\\B", param("\\B_WIDTH"));
844 port("\\Y", param("\\Y_WIDTH"));
845 check_expected();
846 return;
847 }
848
849 if (cell->type.in("$reduce_and", "$reduce_or", "$reduce_xor", "$reduce_xnor", "$reduce_bool")) {
850 param_bool("\\A_SIGNED");
851 port("\\A", param("\\A_WIDTH"));
852 port("\\Y", param("\\Y_WIDTH"));
853 check_expected();
854 return;
855 }
856
857 if (cell->type.in("$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx")) {
858 param_bool("\\A_SIGNED");
859 param_bool("\\B_SIGNED");
860 port("\\A", param("\\A_WIDTH"));
861 port("\\B", param("\\B_WIDTH"));
862 port("\\Y", param("\\Y_WIDTH"));
863 check_expected(false);
864 return;
865 }
866
867 if (cell->type.in("$lt", "$le", "$eq", "$ne", "$eqx", "$nex", "$ge", "$gt")) {
868 param_bool("\\A_SIGNED");
869 param_bool("\\B_SIGNED");
870 port("\\A", param("\\A_WIDTH"));
871 port("\\B", param("\\B_WIDTH"));
872 port("\\Y", param("\\Y_WIDTH"));
873 check_expected();
874 return;
875 }
876
877 if (cell->type.in("$add", "$sub", "$mul", "$div", "$mod", "$pow")) {
878 param_bool("\\A_SIGNED");
879 param_bool("\\B_SIGNED");
880 port("\\A", param("\\A_WIDTH"));
881 port("\\B", param("\\B_WIDTH"));
882 port("\\Y", param("\\Y_WIDTH"));
883 check_expected(cell->type != "$pow");
884 return;
885 }
886
887 if (cell->type == "$fa") {
888 port("\\A", param("\\WIDTH"));
889 port("\\B", param("\\WIDTH"));
890 port("\\C", param("\\WIDTH"));
891 port("\\X", param("\\WIDTH"));
892 port("\\Y", param("\\WIDTH"));
893 check_expected();
894 return;
895 }
896
897 if (cell->type == "$lcu") {
898 port("\\P", param("\\WIDTH"));
899 port("\\G", param("\\WIDTH"));
900 port("\\CI", 1);
901 port("\\CO", param("\\WIDTH"));
902 check_expected();
903 return;
904 }
905
906 if (cell->type == "$alu") {
907 param_bool("\\A_SIGNED");
908 param_bool("\\B_SIGNED");
909 port("\\A", param("\\A_WIDTH"));
910 port("\\B", param("\\B_WIDTH"));
911 port("\\CI", 1);
912 port("\\BI", 1);
913 port("\\X", param("\\Y_WIDTH"));
914 port("\\Y", param("\\Y_WIDTH"));
915 port("\\CO", param("\\Y_WIDTH"));
916 check_expected();
917 return;
918 }
919
920 if (cell->type == "$macc") {
921 param("\\CONFIG");
922 param("\\CONFIG_WIDTH");
923 port("\\A", param("\\A_WIDTH"));
924 port("\\B", param("\\B_WIDTH"));
925 port("\\Y", param("\\Y_WIDTH"));
926 check_expected();
927 Macc().from_cell(cell);
928 return;
929 }
930
931 if (cell->type == "$logic_not") {
932 param_bool("\\A_SIGNED");
933 port("\\A", param("\\A_WIDTH"));
934 port("\\Y", param("\\Y_WIDTH"));
935 check_expected();
936 return;
937 }
938
939 if (cell->type == "$logic_and" || cell->type == "$logic_or") {
940 param_bool("\\A_SIGNED");
941 param_bool("\\B_SIGNED");
942 port("\\A", param("\\A_WIDTH"));
943 port("\\B", param("\\B_WIDTH"));
944 port("\\Y", param("\\Y_WIDTH"));
945 check_expected(false);
946 return;
947 }
948
949 if (cell->type == "$slice") {
950 param("\\OFFSET");
951 port("\\A", param("\\A_WIDTH"));
952 port("\\Y", param("\\Y_WIDTH"));
953 if (param("\\OFFSET") + param("\\Y_WIDTH") > param("\\A_WIDTH"))
954 error(__LINE__);
955 check_expected();
956 return;
957 }
958
959 if (cell->type == "$concat") {
960 port("\\A", param("\\A_WIDTH"));
961 port("\\B", param("\\B_WIDTH"));
962 port("\\Y", param("\\A_WIDTH") + param("\\B_WIDTH"));
963 check_expected();
964 return;
965 }
966
967 if (cell->type == "$mux") {
968 port("\\A", param("\\WIDTH"));
969 port("\\B", param("\\WIDTH"));
970 port("\\S", 1);
971 port("\\Y", param("\\WIDTH"));
972 check_expected();
973 return;
974 }
975
976 if (cell->type == "$pmux") {
977 port("\\A", param("\\WIDTH"));
978 port("\\B", param("\\WIDTH") * param("\\S_WIDTH"));
979 port("\\S", param("\\S_WIDTH"));
980 port("\\Y", param("\\WIDTH"));
981 check_expected();
982 return;
983 }
984
985 if (cell->type == "$lut") {
986 param("\\LUT");
987 port("\\A", param("\\WIDTH"));
988 port("\\Y", 1);
989 check_expected();
990 return;
991 }
992
993 if (cell->type == "$sop") {
994 param("\\DEPTH");
995 param("\\TABLE");
996 port("\\A", param("\\WIDTH"));
997 port("\\Y", 1);
998 check_expected();
999 return;
1000 }
1001
1002 if (cell->type == "$sr") {
1003 param_bool("\\SET_POLARITY");
1004 param_bool("\\CLR_POLARITY");
1005 port("\\SET", param("\\WIDTH"));
1006 port("\\CLR", param("\\WIDTH"));
1007 port("\\Q", param("\\WIDTH"));
1008 check_expected();
1009 return;
1010 }
1011
1012 if (cell->type == "$ff") {
1013 port("\\D", param("\\WIDTH"));
1014 port("\\Q", param("\\WIDTH"));
1015 check_expected();
1016 return;
1017 }
1018
1019 if (cell->type == "$dff") {
1020 param_bool("\\CLK_POLARITY");
1021 port("\\CLK", 1);
1022 port("\\D", param("\\WIDTH"));
1023 port("\\Q", param("\\WIDTH"));
1024 check_expected();
1025 return;
1026 }
1027
1028 if (cell->type == "$dffe") {
1029 param_bool("\\CLK_POLARITY");
1030 param_bool("\\EN_POLARITY");
1031 port("\\CLK", 1);
1032 port("\\EN", 1);
1033 port("\\D", param("\\WIDTH"));
1034 port("\\Q", param("\\WIDTH"));
1035 check_expected();
1036 return;
1037 }
1038
1039 if (cell->type == "$dffsr") {
1040 param_bool("\\CLK_POLARITY");
1041 param_bool("\\SET_POLARITY");
1042 param_bool("\\CLR_POLARITY");
1043 port("\\CLK", 1);
1044 port("\\SET", param("\\WIDTH"));
1045 port("\\CLR", param("\\WIDTH"));
1046 port("\\D", param("\\WIDTH"));
1047 port("\\Q", param("\\WIDTH"));
1048 check_expected();
1049 return;
1050 }
1051
1052 if (cell->type == "$adff") {
1053 param_bool("\\CLK_POLARITY");
1054 param_bool("\\ARST_POLARITY");
1055 param_bits("\\ARST_VALUE", param("\\WIDTH"));
1056 port("\\CLK", 1);
1057 port("\\ARST", 1);
1058 port("\\D", param("\\WIDTH"));
1059 port("\\Q", param("\\WIDTH"));
1060 check_expected();
1061 return;
1062 }
1063
1064 if (cell->type == "$dlatch") {
1065 param_bool("\\EN_POLARITY");
1066 port("\\EN", 1);
1067 port("\\D", param("\\WIDTH"));
1068 port("\\Q", param("\\WIDTH"));
1069 check_expected();
1070 return;
1071 }
1072
1073 if (cell->type == "$dlatchsr") {
1074 param_bool("\\EN_POLARITY");
1075 param_bool("\\SET_POLARITY");
1076 param_bool("\\CLR_POLARITY");
1077 port("\\EN", 1);
1078 port("\\SET", param("\\WIDTH"));
1079 port("\\CLR", param("\\WIDTH"));
1080 port("\\D", param("\\WIDTH"));
1081 port("\\Q", param("\\WIDTH"));
1082 check_expected();
1083 return;
1084 }
1085
1086 if (cell->type == "$fsm") {
1087 param("\\NAME");
1088 param_bool("\\CLK_POLARITY");
1089 param_bool("\\ARST_POLARITY");
1090 param("\\STATE_BITS");
1091 param("\\STATE_NUM");
1092 param("\\STATE_NUM_LOG2");
1093 param("\\STATE_RST");
1094 param_bits("\\STATE_TABLE", param("\\STATE_BITS") * param("\\STATE_NUM"));
1095 param("\\TRANS_NUM");
1096 param_bits("\\TRANS_TABLE", param("\\TRANS_NUM") * (2*param("\\STATE_NUM_LOG2") + param("\\CTRL_IN_WIDTH") + param("\\CTRL_OUT_WIDTH")));
1097 port("\\CLK", 1);
1098 port("\\ARST", 1);
1099 port("\\CTRL_IN", param("\\CTRL_IN_WIDTH"));
1100 port("\\CTRL_OUT", param("\\CTRL_OUT_WIDTH"));
1101 check_expected();
1102 return;
1103 }
1104
1105 if (cell->type == "$memrd") {
1106 param("\\MEMID");
1107 param_bool("\\CLK_ENABLE");
1108 param_bool("\\CLK_POLARITY");
1109 param_bool("\\TRANSPARENT");
1110 port("\\CLK", 1);
1111 port("\\EN", 1);
1112 port("\\ADDR", param("\\ABITS"));
1113 port("\\DATA", param("\\WIDTH"));
1114 check_expected();
1115 return;
1116 }
1117
1118 if (cell->type == "$memwr") {
1119 param("\\MEMID");
1120 param_bool("\\CLK_ENABLE");
1121 param_bool("\\CLK_POLARITY");
1122 param("\\PRIORITY");
1123 port("\\CLK", 1);
1124 port("\\EN", param("\\WIDTH"));
1125 port("\\ADDR", param("\\ABITS"));
1126 port("\\DATA", param("\\WIDTH"));
1127 check_expected();
1128 return;
1129 }
1130
1131 if (cell->type == "$meminit") {
1132 param("\\MEMID");
1133 param("\\PRIORITY");
1134 port("\\ADDR", param("\\ABITS"));
1135 port("\\DATA", param("\\WIDTH") * param("\\WORDS"));
1136 check_expected();
1137 return;
1138 }
1139
1140 if (cell->type == "$mem") {
1141 param("\\MEMID");
1142 param("\\SIZE");
1143 param("\\OFFSET");
1144 param("\\INIT");
1145 param_bits("\\RD_CLK_ENABLE", max(1, param("\\RD_PORTS")));
1146 param_bits("\\RD_CLK_POLARITY", max(1, param("\\RD_PORTS")));
1147 param_bits("\\RD_TRANSPARENT", max(1, param("\\RD_PORTS")));
1148 param_bits("\\WR_CLK_ENABLE", max(1, param("\\WR_PORTS")));
1149 param_bits("\\WR_CLK_POLARITY", max(1, param("\\WR_PORTS")));
1150 port("\\RD_CLK", param("\\RD_PORTS"));
1151 port("\\RD_EN", param("\\RD_PORTS"));
1152 port("\\RD_ADDR", param("\\RD_PORTS") * param("\\ABITS"));
1153 port("\\RD_DATA", param("\\RD_PORTS") * param("\\WIDTH"));
1154 port("\\WR_CLK", param("\\WR_PORTS"));
1155 port("\\WR_EN", param("\\WR_PORTS") * param("\\WIDTH"));
1156 port("\\WR_ADDR", param("\\WR_PORTS") * param("\\ABITS"));
1157 port("\\WR_DATA", param("\\WR_PORTS") * param("\\WIDTH"));
1158 check_expected();
1159 return;
1160 }
1161
1162 if (cell->type == "$tribuf") {
1163 port("\\A", param("\\WIDTH"));
1164 port("\\Y", param("\\WIDTH"));
1165 port("\\EN", 1);
1166 check_expected();
1167 return;
1168 }
1169
1170 if (cell->type.in("$assert", "$assume", "$live", "$fair", "$cover")) {
1171 port("\\A", 1);
1172 port("\\EN", 1);
1173 check_expected();
1174 return;
1175 }
1176
1177 if (cell->type == "$initstate") {
1178 port("\\Y", 1);
1179 check_expected();
1180 return;
1181 }
1182
1183 if (cell->type.in("$anyconst", "$anyseq", "$allconst", "$allseq")) {
1184 port("\\Y", param("\\WIDTH"));
1185 check_expected();
1186 return;
1187 }
1188
1189 if (cell->type == "$equiv") {
1190 port("\\A", 1);
1191 port("\\B", 1);
1192 port("\\Y", 1);
1193 check_expected();
1194 return;
1195 }
1196
1197 if (cell->type.in("$specify2", "$specify3")) {
1198 param_bool("\\FULL");
1199 param_bool("\\SRC_DST_PEN");
1200 param_bool("\\SRC_DST_POL");
1201 param("\\T_RISE_MIN");
1202 param("\\T_RISE_TYP");
1203 param("\\T_RISE_MAX");
1204 param("\\T_FALL_MIN");
1205 param("\\T_FALL_TYP");
1206 param("\\T_FALL_MAX");
1207 port("\\EN", 1);
1208 port("\\SRC", param("\\SRC_WIDTH"));
1209 port("\\DST", param("\\DST_WIDTH"));
1210 if (cell->type == "$specify3") {
1211 param_bool("\\EDGE_EN");
1212 param_bool("\\EDGE_POL");
1213 param_bool("\\DAT_DST_PEN");
1214 param_bool("\\DAT_DST_POL");
1215 port("\\DAT", param("\\DST_WIDTH"));
1216 }
1217 check_expected();
1218 return;
1219 }
1220
1221 if (cell->type == "$specrule") {
1222 param_bool("\\SRC_PEN");
1223 param_bool("\\SRC_POL");
1224 param_bool("\\DST_PEN");
1225 param_bool("\\DST_POL");
1226 param_bool("\\LIMIT_GT");
1227 param("\\T_LIMIT");
1228 port("\\SRC_EN", 1);
1229 port("\\DST_EN", 1);
1230 port("\\SRC", param("\\SRC_WIDTH"));
1231 port("\\DST", param("\\DST_WIDTH"));
1232 check_expected();
1233 return;
1234 }
1235
1236 if (cell->type == "$_BUF_") { check_gate("AY"); return; }
1237 if (cell->type == "$_NOT_") { check_gate("AY"); return; }
1238 if (cell->type == "$_AND_") { check_gate("ABY"); return; }
1239 if (cell->type == "$_NAND_") { check_gate("ABY"); return; }
1240 if (cell->type == "$_OR_") { check_gate("ABY"); return; }
1241 if (cell->type == "$_NOR_") { check_gate("ABY"); return; }
1242 if (cell->type == "$_XOR_") { check_gate("ABY"); return; }
1243 if (cell->type == "$_XNOR_") { check_gate("ABY"); return; }
1244 if (cell->type == "$_ANDNOT_") { check_gate("ABY"); return; }
1245 if (cell->type == "$_ORNOT_") { check_gate("ABY"); return; }
1246 if (cell->type == "$_MUX_") { check_gate("ABSY"); return; }
1247 if (cell->type == "$_AOI3_") { check_gate("ABCY"); return; }
1248 if (cell->type == "$_OAI3_") { check_gate("ABCY"); return; }
1249 if (cell->type == "$_AOI4_") { check_gate("ABCDY"); return; }
1250 if (cell->type == "$_OAI4_") { check_gate("ABCDY"); return; }
1251
1252 if (cell->type == "$_TBUF_") { check_gate("AYE"); return; }
1253
1254 if (cell->type == "$_MUX4_") { check_gate("ABCDSTY"); return; }
1255 if (cell->type == "$_MUX8_") { check_gate("ABCDEFGHSTUY"); return; }
1256 if (cell->type == "$_MUX16_") { check_gate("ABCDEFGHIJKLMNOPSTUVY"); return; }
1257
1258 if (cell->type == "$_SR_NN_") { check_gate("SRQ"); return; }
1259 if (cell->type == "$_SR_NP_") { check_gate("SRQ"); return; }
1260 if (cell->type == "$_SR_PN_") { check_gate("SRQ"); return; }
1261 if (cell->type == "$_SR_PP_") { check_gate("SRQ"); return; }
1262
1263 if (cell->type == "$_FF_") { check_gate("DQ"); return; }
1264 if (cell->type == "$_DFF_N_") { check_gate("DQC"); return; }
1265 if (cell->type == "$_DFF_P_") { check_gate("DQC"); return; }
1266
1267 if (cell->type == "$_DFFE_NN_") { check_gate("DQCE"); return; }
1268 if (cell->type == "$_DFFE_NP_") { check_gate("DQCE"); return; }
1269 if (cell->type == "$_DFFE_PN_") { check_gate("DQCE"); return; }
1270 if (cell->type == "$_DFFE_PP_") { check_gate("DQCE"); return; }
1271
1272 if (cell->type == "$_DFF_NN0_") { check_gate("DQCR"); return; }
1273 if (cell->type == "$_DFF_NN1_") { check_gate("DQCR"); return; }
1274 if (cell->type == "$_DFF_NP0_") { check_gate("DQCR"); return; }
1275 if (cell->type == "$_DFF_NP1_") { check_gate("DQCR"); return; }
1276 if (cell->type == "$_DFF_PN0_") { check_gate("DQCR"); return; }
1277 if (cell->type == "$_DFF_PN1_") { check_gate("DQCR"); return; }
1278 if (cell->type == "$_DFF_PP0_") { check_gate("DQCR"); return; }
1279 if (cell->type == "$_DFF_PP1_") { check_gate("DQCR"); return; }
1280
1281 if (cell->type == "$_DFFSR_NNN_") { check_gate("CSRDQ"); return; }
1282 if (cell->type == "$_DFFSR_NNP_") { check_gate("CSRDQ"); return; }
1283 if (cell->type == "$_DFFSR_NPN_") { check_gate("CSRDQ"); return; }
1284 if (cell->type == "$_DFFSR_NPP_") { check_gate("CSRDQ"); return; }
1285 if (cell->type == "$_DFFSR_PNN_") { check_gate("CSRDQ"); return; }
1286 if (cell->type == "$_DFFSR_PNP_") { check_gate("CSRDQ"); return; }
1287 if (cell->type == "$_DFFSR_PPN_") { check_gate("CSRDQ"); return; }
1288 if (cell->type == "$_DFFSR_PPP_") { check_gate("CSRDQ"); return; }
1289
1290 if (cell->type == "$_DLATCH_N_") { check_gate("EDQ"); return; }
1291 if (cell->type == "$_DLATCH_P_") { check_gate("EDQ"); return; }
1292
1293 if (cell->type == "$_DLATCHSR_NNN_") { check_gate("ESRDQ"); return; }
1294 if (cell->type == "$_DLATCHSR_NNP_") { check_gate("ESRDQ"); return; }
1295 if (cell->type == "$_DLATCHSR_NPN_") { check_gate("ESRDQ"); return; }
1296 if (cell->type == "$_DLATCHSR_NPP_") { check_gate("ESRDQ"); return; }
1297 if (cell->type == "$_DLATCHSR_PNN_") { check_gate("ESRDQ"); return; }
1298 if (cell->type == "$_DLATCHSR_PNP_") { check_gate("ESRDQ"); return; }
1299 if (cell->type == "$_DLATCHSR_PPN_") { check_gate("ESRDQ"); return; }
1300 if (cell->type == "$_DLATCHSR_PPP_") { check_gate("ESRDQ"); return; }
1301
1302 error(__LINE__);
1303 }
1304 };
1305 }
1306 #endif
1307
1308 void RTLIL::Module::sort()
1309 {
1310 wires_.sort(sort_by_id_str());
1311 cells_.sort(sort_by_id_str());
1312 avail_parameters.sort(sort_by_id_str());
1313 memories.sort(sort_by_id_str());
1314 processes.sort(sort_by_id_str());
1315 for (auto &it : cells_)
1316 it.second->sort();
1317 for (auto &it : wires_)
1318 it.second->attributes.sort(sort_by_id_str());
1319 for (auto &it : memories)
1320 it.second->attributes.sort(sort_by_id_str());
1321 }
1322
1323 void RTLIL::Module::check()
1324 {
1325 #ifndef NDEBUG
1326 std::vector<bool> ports_declared;
1327 for (auto &it : wires_) {
1328 log_assert(this == it.second->module);
1329 log_assert(it.first == it.second->name);
1330 log_assert(!it.first.empty());
1331 log_assert(it.second->width >= 0);
1332 log_assert(it.second->port_id >= 0);
1333 for (auto &it2 : it.second->attributes)
1334 log_assert(!it2.first.empty());
1335 if (it.second->port_id) {
1336 log_assert(GetSize(ports) >= it.second->port_id);
1337 log_assert(ports.at(it.second->port_id-1) == it.first);
1338 log_assert(it.second->port_input || it.second->port_output);
1339 if (GetSize(ports_declared) < it.second->port_id)
1340 ports_declared.resize(it.second->port_id);
1341 log_assert(ports_declared[it.second->port_id-1] == false);
1342 ports_declared[it.second->port_id-1] = true;
1343 } else
1344 log_assert(!it.second->port_input && !it.second->port_output);
1345 }
1346 for (auto port_declared : ports_declared)
1347 log_assert(port_declared == true);
1348 log_assert(GetSize(ports) == GetSize(ports_declared));
1349
1350 for (auto &it : memories) {
1351 log_assert(it.first == it.second->name);
1352 log_assert(!it.first.empty());
1353 log_assert(it.second->width >= 0);
1354 log_assert(it.second->size >= 0);
1355 for (auto &it2 : it.second->attributes)
1356 log_assert(!it2.first.empty());
1357 }
1358
1359 for (auto &it : cells_) {
1360 log_assert(this == it.second->module);
1361 log_assert(it.first == it.second->name);
1362 log_assert(!it.first.empty());
1363 log_assert(!it.second->type.empty());
1364 for (auto &it2 : it.second->connections()) {
1365 log_assert(!it2.first.empty());
1366 it2.second.check();
1367 }
1368 for (auto &it2 : it.second->attributes)
1369 log_assert(!it2.first.empty());
1370 for (auto &it2 : it.second->parameters)
1371 log_assert(!it2.first.empty());
1372 InternalCellChecker checker(this, it.second);
1373 checker.check();
1374 }
1375
1376 for (auto &it : processes) {
1377 log_assert(it.first == it.second->name);
1378 log_assert(!it.first.empty());
1379 // FIXME: More checks here..
1380 }
1381
1382 for (auto &it : connections_) {
1383 log_assert(it.first.size() == it.second.size());
1384 log_assert(!it.first.has_const());
1385 it.first.check();
1386 it.second.check();
1387 }
1388
1389 for (auto &it : attributes)
1390 log_assert(!it.first.empty());
1391 #endif
1392 }
1393
1394 void RTLIL::Module::optimize()
1395 {
1396 }
1397
1398 void RTLIL::Module::cloneInto(RTLIL::Module *new_mod) const
1399 {
1400 log_assert(new_mod->refcount_wires_ == 0);
1401 log_assert(new_mod->refcount_cells_ == 0);
1402
1403 new_mod->avail_parameters = avail_parameters;
1404
1405 for (auto &conn : connections_)
1406 new_mod->connect(conn);
1407
1408 for (auto &attr : attributes)
1409 new_mod->attributes[attr.first] = attr.second;
1410
1411 for (auto &it : wires_)
1412 new_mod->addWire(it.first, it.second);
1413
1414 for (auto &it : memories)
1415 new_mod->memories[it.first] = new RTLIL::Memory(*it.second);
1416
1417 for (auto &it : cells_)
1418 new_mod->addCell(it.first, it.second);
1419
1420 for (auto &it : processes)
1421 new_mod->processes[it.first] = it.second->clone();
1422
1423 struct RewriteSigSpecWorker
1424 {
1425 RTLIL::Module *mod;
1426 void operator()(RTLIL::SigSpec &sig)
1427 {
1428 std::vector<RTLIL::SigChunk> chunks = sig.chunks();
1429 for (auto &c : chunks)
1430 if (c.wire != NULL)
1431 c.wire = mod->wires_.at(c.wire->name);
1432 sig = chunks;
1433 }
1434 };
1435
1436 RewriteSigSpecWorker rewriteSigSpecWorker;
1437 rewriteSigSpecWorker.mod = new_mod;
1438 new_mod->rewrite_sigspecs(rewriteSigSpecWorker);
1439 new_mod->fixup_ports();
1440 }
1441
1442 RTLIL::Module *RTLIL::Module::clone() const
1443 {
1444 RTLIL::Module *new_mod = new RTLIL::Module;
1445 new_mod->name = name;
1446 cloneInto(new_mod);
1447 return new_mod;
1448 }
1449
1450 bool RTLIL::Module::has_memories() const
1451 {
1452 return !memories.empty();
1453 }
1454
1455 bool RTLIL::Module::has_processes() const
1456 {
1457 return !processes.empty();
1458 }
1459
1460 bool RTLIL::Module::has_memories_warn() const
1461 {
1462 if (!memories.empty())
1463 log_warning("Ignoring module %s because it contains memories (run 'memory' command first).\n", log_id(this));
1464 return !memories.empty();
1465 }
1466
1467 bool RTLIL::Module::has_processes_warn() const
1468 {
1469 if (!processes.empty())
1470 log_warning("Ignoring module %s because it contains processes (run 'proc' command first).\n", log_id(this));
1471 return !processes.empty();
1472 }
1473
1474 std::vector<RTLIL::Wire*> RTLIL::Module::selected_wires() const
1475 {
1476 std::vector<RTLIL::Wire*> result;
1477 result.reserve(wires_.size());
1478 for (auto &it : wires_)
1479 if (design->selected(this, it.second))
1480 result.push_back(it.second);
1481 return result;
1482 }
1483
1484 std::vector<RTLIL::Cell*> RTLIL::Module::selected_cells() const
1485 {
1486 std::vector<RTLIL::Cell*> result;
1487 result.reserve(wires_.size());
1488 for (auto &it : cells_)
1489 if (design->selected(this, it.second))
1490 result.push_back(it.second);
1491 return result;
1492 }
1493
1494 void RTLIL::Module::add(RTLIL::Wire *wire)
1495 {
1496 log_assert(!wire->name.empty());
1497 log_assert(count_id(wire->name) == 0);
1498 log_assert(refcount_wires_ == 0);
1499 wires_[wire->name] = wire;
1500 wire->module = this;
1501 }
1502
1503 void RTLIL::Module::add(RTLIL::Cell *cell)
1504 {
1505 log_assert(!cell->name.empty());
1506 log_assert(count_id(cell->name) == 0);
1507 log_assert(refcount_cells_ == 0);
1508 cells_[cell->name] = cell;
1509 cell->module = this;
1510 }
1511
1512 namespace {
1513 struct DeleteWireWorker
1514 {
1515 RTLIL::Module *module;
1516 const pool<RTLIL::Wire*> *wires_p;
1517
1518 void operator()(RTLIL::SigSpec &sig) {
1519 std::vector<RTLIL::SigChunk> chunks = sig;
1520 for (auto &c : chunks)
1521 if (c.wire != NULL && wires_p->count(c.wire)) {
1522 c.wire = module->addWire(NEW_ID, c.width);
1523 c.offset = 0;
1524 }
1525 sig = chunks;
1526 }
1527 };
1528 }
1529
1530 void RTLIL::Module::remove(const pool<RTLIL::Wire*> &wires)
1531 {
1532 log_assert(refcount_wires_ == 0);
1533
1534 DeleteWireWorker delete_wire_worker;
1535 delete_wire_worker.module = this;
1536 delete_wire_worker.wires_p = &wires;
1537 rewrite_sigspecs(delete_wire_worker);
1538
1539 for (auto &it : wires) {
1540 log_assert(wires_.count(it->name) != 0);
1541 wires_.erase(it->name);
1542 delete it;
1543 }
1544 }
1545
1546 void RTLIL::Module::remove(RTLIL::Cell *cell)
1547 {
1548 while (!cell->connections_.empty())
1549 cell->unsetPort(cell->connections_.begin()->first);
1550
1551 log_assert(cells_.count(cell->name) != 0);
1552 log_assert(refcount_cells_ == 0);
1553 cells_.erase(cell->name);
1554 delete cell;
1555 }
1556
1557 void RTLIL::Module::rename(RTLIL::Wire *wire, RTLIL::IdString new_name)
1558 {
1559 log_assert(wires_[wire->name] == wire);
1560 log_assert(refcount_wires_ == 0);
1561 wires_.erase(wire->name);
1562 wire->name = new_name;
1563 add(wire);
1564 }
1565
1566 void RTLIL::Module::rename(RTLIL::Cell *cell, RTLIL::IdString new_name)
1567 {
1568 log_assert(cells_[cell->name] == cell);
1569 log_assert(refcount_wires_ == 0);
1570 cells_.erase(cell->name);
1571 cell->name = new_name;
1572 add(cell);
1573 }
1574
1575 void RTLIL::Module::rename(RTLIL::IdString old_name, RTLIL::IdString new_name)
1576 {
1577 log_assert(count_id(old_name) != 0);
1578 if (wires_.count(old_name))
1579 rename(wires_.at(old_name), new_name);
1580 else if (cells_.count(old_name))
1581 rename(cells_.at(old_name), new_name);
1582 else
1583 log_abort();
1584 }
1585
1586 void RTLIL::Module::swap_names(RTLIL::Wire *w1, RTLIL::Wire *w2)
1587 {
1588 log_assert(wires_[w1->name] == w1);
1589 log_assert(wires_[w2->name] == w2);
1590 log_assert(refcount_wires_ == 0);
1591
1592 wires_.erase(w1->name);
1593 wires_.erase(w2->name);
1594
1595 std::swap(w1->name, w2->name);
1596
1597 wires_[w1->name] = w1;
1598 wires_[w2->name] = w2;
1599 }
1600
1601 void RTLIL::Module::swap_names(RTLIL::Cell *c1, RTLIL::Cell *c2)
1602 {
1603 log_assert(cells_[c1->name] == c1);
1604 log_assert(cells_[c2->name] == c2);
1605 log_assert(refcount_cells_ == 0);
1606
1607 cells_.erase(c1->name);
1608 cells_.erase(c2->name);
1609
1610 std::swap(c1->name, c2->name);
1611
1612 cells_[c1->name] = c1;
1613 cells_[c2->name] = c2;
1614 }
1615
1616 RTLIL::IdString RTLIL::Module::uniquify(RTLIL::IdString name)
1617 {
1618 int index = 0;
1619 return uniquify(name, index);
1620 }
1621
1622 RTLIL::IdString RTLIL::Module::uniquify(RTLIL::IdString name, int &index)
1623 {
1624 if (index == 0) {
1625 if (count_id(name) == 0)
1626 return name;
1627 index++;
1628 }
1629
1630 while (1) {
1631 RTLIL::IdString new_name = stringf("%s_%d", name.c_str(), index);
1632 if (count_id(new_name) == 0)
1633 return new_name;
1634 index++;
1635 }
1636 }
1637
1638 static bool fixup_ports_compare(const RTLIL::Wire *a, const RTLIL::Wire *b)
1639 {
1640 if (a->port_id && !b->port_id)
1641 return true;
1642 if (!a->port_id && b->port_id)
1643 return false;
1644
1645 if (a->port_id == b->port_id)
1646 return a->name < b->name;
1647 return a->port_id < b->port_id;
1648 }
1649
1650 void RTLIL::Module::connect(const RTLIL::SigSig &conn)
1651 {
1652 for (auto mon : monitors)
1653 mon->notify_connect(this, conn);
1654
1655 if (design)
1656 for (auto mon : design->monitors)
1657 mon->notify_connect(this, conn);
1658
1659 // ignore all attempts to assign constants to other constants
1660 if (conn.first.has_const()) {
1661 RTLIL::SigSig new_conn;
1662 for (int i = 0; i < GetSize(conn.first); i++)
1663 if (conn.first[i].wire) {
1664 new_conn.first.append(conn.first[i]);
1665 new_conn.second.append(conn.second[i]);
1666 }
1667 if (GetSize(new_conn.first))
1668 connect(new_conn);
1669 return;
1670 }
1671
1672 if (yosys_xtrace) {
1673 log("#X# Connect (SigSig) in %s: %s = %s (%d bits)\n", log_id(this), log_signal(conn.first), log_signal(conn.second), GetSize(conn.first));
1674 log_backtrace("-X- ", yosys_xtrace-1);
1675 }
1676
1677 log_assert(GetSize(conn.first) == GetSize(conn.second));
1678 connections_.push_back(conn);
1679 }
1680
1681 void RTLIL::Module::connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs)
1682 {
1683 connect(RTLIL::SigSig(lhs, rhs));
1684 }
1685
1686 void RTLIL::Module::new_connections(const std::vector<RTLIL::SigSig> &new_conn)
1687 {
1688 for (auto mon : monitors)
1689 mon->notify_connect(this, new_conn);
1690
1691 if (design)
1692 for (auto mon : design->monitors)
1693 mon->notify_connect(this, new_conn);
1694
1695 if (yosys_xtrace) {
1696 log("#X# New connections vector in %s:\n", log_id(this));
1697 for (auto &conn: new_conn)
1698 log("#X# %s = %s (%d bits)\n", log_signal(conn.first), log_signal(conn.second), GetSize(conn.first));
1699 log_backtrace("-X- ", yosys_xtrace-1);
1700 }
1701
1702 connections_ = new_conn;
1703 }
1704
1705 const std::vector<RTLIL::SigSig> &RTLIL::Module::connections() const
1706 {
1707 return connections_;
1708 }
1709
1710 void RTLIL::Module::fixup_ports()
1711 {
1712 std::vector<RTLIL::Wire*> all_ports;
1713
1714 for (auto &w : wires_)
1715 if (w.second->port_input || w.second->port_output)
1716 all_ports.push_back(w.second);
1717 else
1718 w.second->port_id = 0;
1719
1720 std::sort(all_ports.begin(), all_ports.end(), fixup_ports_compare);
1721
1722 ports.clear();
1723 for (size_t i = 0; i < all_ports.size(); i++) {
1724 ports.push_back(all_ports[i]->name);
1725 all_ports[i]->port_id = i+1;
1726 }
1727 }
1728
1729 RTLIL::Wire *RTLIL::Module::addWire(RTLIL::IdString name, int width)
1730 {
1731 RTLIL::Wire *wire = new RTLIL::Wire;
1732 wire->name = name;
1733 wire->width = width;
1734 add(wire);
1735 return wire;
1736 }
1737
1738 RTLIL::Wire *RTLIL::Module::addWire(RTLIL::IdString name, const RTLIL::Wire *other)
1739 {
1740 RTLIL::Wire *wire = addWire(name);
1741 wire->width = other->width;
1742 wire->start_offset = other->start_offset;
1743 wire->port_id = other->port_id;
1744 wire->port_input = other->port_input;
1745 wire->port_output = other->port_output;
1746 wire->upto = other->upto;
1747 wire->attributes = other->attributes;
1748 return wire;
1749 }
1750
1751 RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, RTLIL::IdString type)
1752 {
1753 RTLIL::Cell *cell = new RTLIL::Cell;
1754 cell->name = name;
1755 cell->type = type;
1756 add(cell);
1757 return cell;
1758 }
1759
1760 RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, const RTLIL::Cell *other)
1761 {
1762 RTLIL::Cell *cell = addCell(name, other->type);
1763 cell->connections_ = other->connections_;
1764 cell->parameters = other->parameters;
1765 cell->attributes = other->attributes;
1766 return cell;
1767 }
1768
1769 #define DEF_METHOD(_func, _y_size, _type) \
1770 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed, const std::string &src) { \
1771 RTLIL::Cell *cell = addCell(name, _type); \
1772 cell->parameters["\\A_SIGNED"] = is_signed; \
1773 cell->parameters["\\A_WIDTH"] = sig_a.size(); \
1774 cell->parameters["\\Y_WIDTH"] = sig_y.size(); \
1775 cell->setPort("\\A", sig_a); \
1776 cell->setPort("\\Y", sig_y); \
1777 cell->set_src_attribute(src); \
1778 return cell; \
1779 } \
1780 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed, const std::string &src) { \
1781 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
1782 add ## _func(name, sig_a, sig_y, is_signed, src); \
1783 return sig_y; \
1784 }
1785 DEF_METHOD(Not, sig_a.size(), "$not")
1786 DEF_METHOD(Pos, sig_a.size(), "$pos")
1787 DEF_METHOD(Neg, sig_a.size(), "$neg")
1788 DEF_METHOD(ReduceAnd, 1, "$reduce_and")
1789 DEF_METHOD(ReduceOr, 1, "$reduce_or")
1790 DEF_METHOD(ReduceXor, 1, "$reduce_xor")
1791 DEF_METHOD(ReduceXnor, 1, "$reduce_xnor")
1792 DEF_METHOD(ReduceBool, 1, "$reduce_bool")
1793 DEF_METHOD(LogicNot, 1, "$logic_not")
1794 #undef DEF_METHOD
1795
1796 #define DEF_METHOD(_func, _y_size, _type) \
1797 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed, const std::string &src) { \
1798 RTLIL::Cell *cell = addCell(name, _type); \
1799 cell->parameters["\\A_SIGNED"] = is_signed; \
1800 cell->parameters["\\B_SIGNED"] = is_signed; \
1801 cell->parameters["\\A_WIDTH"] = sig_a.size(); \
1802 cell->parameters["\\B_WIDTH"] = sig_b.size(); \
1803 cell->parameters["\\Y_WIDTH"] = sig_y.size(); \
1804 cell->setPort("\\A", sig_a); \
1805 cell->setPort("\\B", sig_b); \
1806 cell->setPort("\\Y", sig_y); \
1807 cell->set_src_attribute(src); \
1808 return cell; \
1809 } \
1810 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed, const std::string &src) { \
1811 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
1812 add ## _func(name, sig_a, sig_b, sig_y, is_signed, src); \
1813 return sig_y; \
1814 }
1815 DEF_METHOD(And, max(sig_a.size(), sig_b.size()), "$and")
1816 DEF_METHOD(Or, max(sig_a.size(), sig_b.size()), "$or")
1817 DEF_METHOD(Xor, max(sig_a.size(), sig_b.size()), "$xor")
1818 DEF_METHOD(Xnor, max(sig_a.size(), sig_b.size()), "$xnor")
1819 DEF_METHOD(Shl, sig_a.size(), "$shl")
1820 DEF_METHOD(Shr, sig_a.size(), "$shr")
1821 DEF_METHOD(Sshl, sig_a.size(), "$sshl")
1822 DEF_METHOD(Sshr, sig_a.size(), "$sshr")
1823 DEF_METHOD(Shift, sig_a.size(), "$shift")
1824 DEF_METHOD(Shiftx, sig_a.size(), "$shiftx")
1825 DEF_METHOD(Lt, 1, "$lt")
1826 DEF_METHOD(Le, 1, "$le")
1827 DEF_METHOD(Eq, 1, "$eq")
1828 DEF_METHOD(Ne, 1, "$ne")
1829 DEF_METHOD(Eqx, 1, "$eqx")
1830 DEF_METHOD(Nex, 1, "$nex")
1831 DEF_METHOD(Ge, 1, "$ge")
1832 DEF_METHOD(Gt, 1, "$gt")
1833 DEF_METHOD(Add, max(sig_a.size(), sig_b.size()), "$add")
1834 DEF_METHOD(Sub, max(sig_a.size(), sig_b.size()), "$sub")
1835 DEF_METHOD(Mul, max(sig_a.size(), sig_b.size()), "$mul")
1836 DEF_METHOD(Div, max(sig_a.size(), sig_b.size()), "$div")
1837 DEF_METHOD(Mod, max(sig_a.size(), sig_b.size()), "$mod")
1838 DEF_METHOD(LogicAnd, 1, "$logic_and")
1839 DEF_METHOD(LogicOr, 1, "$logic_or")
1840 #undef DEF_METHOD
1841
1842 #define DEF_METHOD(_func, _type, _pmux) \
1843 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, RTLIL::SigSpec sig_y, const std::string &src) { \
1844 RTLIL::Cell *cell = addCell(name, _type); \
1845 cell->parameters["\\WIDTH"] = sig_a.size(); \
1846 if (_pmux) cell->parameters["\\S_WIDTH"] = sig_s.size(); \
1847 cell->setPort("\\A", sig_a); \
1848 cell->setPort("\\B", sig_b); \
1849 cell->setPort("\\S", sig_s); \
1850 cell->setPort("\\Y", sig_y); \
1851 cell->set_src_attribute(src); \
1852 return cell; \
1853 } \
1854 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, const std::string &src) { \
1855 RTLIL::SigSpec sig_y = addWire(NEW_ID, sig_a.size()); \
1856 add ## _func(name, sig_a, sig_b, sig_s, sig_y, src); \
1857 return sig_y; \
1858 }
1859 DEF_METHOD(Mux, "$mux", 0)
1860 DEF_METHOD(Pmux, "$pmux", 1)
1861 #undef DEF_METHOD
1862
1863 #define DEF_METHOD_2(_func, _type, _P1, _P2) \
1864 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, const std::string &src) { \
1865 RTLIL::Cell *cell = addCell(name, _type); \
1866 cell->setPort("\\" #_P1, sig1); \
1867 cell->setPort("\\" #_P2, sig2); \
1868 cell->set_src_attribute(src); \
1869 return cell; \
1870 } \
1871 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, const std::string &src) { \
1872 RTLIL::SigBit sig2 = addWire(NEW_ID); \
1873 add ## _func(name, sig1, sig2, src); \
1874 return sig2; \
1875 }
1876 #define DEF_METHOD_3(_func, _type, _P1, _P2, _P3) \
1877 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, const std::string &src) { \
1878 RTLIL::Cell *cell = addCell(name, _type); \
1879 cell->setPort("\\" #_P1, sig1); \
1880 cell->setPort("\\" #_P2, sig2); \
1881 cell->setPort("\\" #_P3, sig3); \
1882 cell->set_src_attribute(src); \
1883 return cell; \
1884 } \
1885 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, const std::string &src) { \
1886 RTLIL::SigBit sig3 = addWire(NEW_ID); \
1887 add ## _func(name, sig1, sig2, sig3, src); \
1888 return sig3; \
1889 }
1890 #define DEF_METHOD_4(_func, _type, _P1, _P2, _P3, _P4) \
1891 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, RTLIL::SigBit sig4, const std::string &src) { \
1892 RTLIL::Cell *cell = addCell(name, _type); \
1893 cell->setPort("\\" #_P1, sig1); \
1894 cell->setPort("\\" #_P2, sig2); \
1895 cell->setPort("\\" #_P3, sig3); \
1896 cell->setPort("\\" #_P4, sig4); \
1897 cell->set_src_attribute(src); \
1898 return cell; \
1899 } \
1900 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, const std::string &src) { \
1901 RTLIL::SigBit sig4 = addWire(NEW_ID); \
1902 add ## _func(name, sig1, sig2, sig3, sig4, src); \
1903 return sig4; \
1904 }
1905 #define DEF_METHOD_5(_func, _type, _P1, _P2, _P3, _P4, _P5) \
1906 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, RTLIL::SigBit sig4, RTLIL::SigBit sig5, const std::string &src) { \
1907 RTLIL::Cell *cell = addCell(name, _type); \
1908 cell->setPort("\\" #_P1, sig1); \
1909 cell->setPort("\\" #_P2, sig2); \
1910 cell->setPort("\\" #_P3, sig3); \
1911 cell->setPort("\\" #_P4, sig4); \
1912 cell->setPort("\\" #_P5, sig5); \
1913 cell->set_src_attribute(src); \
1914 return cell; \
1915 } \
1916 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, RTLIL::SigBit sig4, const std::string &src) { \
1917 RTLIL::SigBit sig5 = addWire(NEW_ID); \
1918 add ## _func(name, sig1, sig2, sig3, sig4, sig5, src); \
1919 return sig5; \
1920 }
1921 DEF_METHOD_2(BufGate, "$_BUF_", A, Y)
1922 DEF_METHOD_2(NotGate, "$_NOT_", A, Y)
1923 DEF_METHOD_3(AndGate, "$_AND_", A, B, Y)
1924 DEF_METHOD_3(NandGate, "$_NAND_", A, B, Y)
1925 DEF_METHOD_3(OrGate, "$_OR_", A, B, Y)
1926 DEF_METHOD_3(NorGate, "$_NOR_", A, B, Y)
1927 DEF_METHOD_3(XorGate, "$_XOR_", A, B, Y)
1928 DEF_METHOD_3(XnorGate, "$_XNOR_", A, B, Y)
1929 DEF_METHOD_3(AndnotGate, "$_ANDNOT_", A, B, Y)
1930 DEF_METHOD_3(OrnotGate, "$_ORNOT_", A, B, Y)
1931 DEF_METHOD_4(MuxGate, "$_MUX_", A, B, S, Y)
1932 DEF_METHOD_4(Aoi3Gate, "$_AOI3_", A, B, C, Y)
1933 DEF_METHOD_4(Oai3Gate, "$_OAI3_", A, B, C, Y)
1934 DEF_METHOD_5(Aoi4Gate, "$_AOI4_", A, B, C, D, Y)
1935 DEF_METHOD_5(Oai4Gate, "$_OAI4_", A, B, C, D, Y)
1936 #undef DEF_METHOD_2
1937 #undef DEF_METHOD_3
1938 #undef DEF_METHOD_4
1939 #undef DEF_METHOD_5
1940
1941 RTLIL::Cell* RTLIL::Module::addPow(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool a_signed, bool b_signed, const std::string &src)
1942 {
1943 RTLIL::Cell *cell = addCell(name, "$pow");
1944 cell->parameters["\\A_SIGNED"] = a_signed;
1945 cell->parameters["\\B_SIGNED"] = b_signed;
1946 cell->parameters["\\A_WIDTH"] = sig_a.size();
1947 cell->parameters["\\B_WIDTH"] = sig_b.size();
1948 cell->parameters["\\Y_WIDTH"] = sig_y.size();
1949 cell->setPort("\\A", sig_a);
1950 cell->setPort("\\B", sig_b);
1951 cell->setPort("\\Y", sig_y);
1952 cell->set_src_attribute(src);
1953 return cell;
1954 }
1955
1956 RTLIL::Cell* RTLIL::Module::addSlice(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, RTLIL::Const offset, const std::string &src)
1957 {
1958 RTLIL::Cell *cell = addCell(name, "$slice");
1959 cell->parameters["\\A_WIDTH"] = sig_a.size();
1960 cell->parameters["\\Y_WIDTH"] = sig_y.size();
1961 cell->parameters["\\OFFSET"] = offset;
1962 cell->setPort("\\A", sig_a);
1963 cell->setPort("\\Y", sig_y);
1964 cell->set_src_attribute(src);
1965 return cell;
1966 }
1967
1968 RTLIL::Cell* RTLIL::Module::addConcat(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, const std::string &src)
1969 {
1970 RTLIL::Cell *cell = addCell(name, "$concat");
1971 cell->parameters["\\A_WIDTH"] = sig_a.size();
1972 cell->parameters["\\B_WIDTH"] = sig_b.size();
1973 cell->setPort("\\A", sig_a);
1974 cell->setPort("\\B", sig_b);
1975 cell->setPort("\\Y", sig_y);
1976 cell->set_src_attribute(src);
1977 return cell;
1978 }
1979
1980 RTLIL::Cell* RTLIL::Module::addLut(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, RTLIL::Const lut, const std::string &src)
1981 {
1982 RTLIL::Cell *cell = addCell(name, "$lut");
1983 cell->parameters["\\LUT"] = lut;
1984 cell->parameters["\\WIDTH"] = sig_a.size();
1985 cell->setPort("\\A", sig_a);
1986 cell->setPort("\\Y", sig_y);
1987 cell->set_src_attribute(src);
1988 return cell;
1989 }
1990
1991 RTLIL::Cell* RTLIL::Module::addTribuf(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_y, const std::string &src)
1992 {
1993 RTLIL::Cell *cell = addCell(name, "$tribuf");
1994 cell->parameters["\\WIDTH"] = sig_a.size();
1995 cell->setPort("\\A", sig_a);
1996 cell->setPort("\\EN", sig_en);
1997 cell->setPort("\\Y", sig_y);
1998 cell->set_src_attribute(src);
1999 return cell;
2000 }
2001
2002 RTLIL::Cell* RTLIL::Module::addAssert(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src)
2003 {
2004 RTLIL::Cell *cell = addCell(name, "$assert");
2005 cell->setPort("\\A", sig_a);
2006 cell->setPort("\\EN", sig_en);
2007 cell->set_src_attribute(src);
2008 return cell;
2009 }
2010
2011 RTLIL::Cell* RTLIL::Module::addAssume(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src)
2012 {
2013 RTLIL::Cell *cell = addCell(name, "$assume");
2014 cell->setPort("\\A", sig_a);
2015 cell->setPort("\\EN", sig_en);
2016 cell->set_src_attribute(src);
2017 return cell;
2018 }
2019
2020 RTLIL::Cell* RTLIL::Module::addLive(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src)
2021 {
2022 RTLIL::Cell *cell = addCell(name, "$live");
2023 cell->setPort("\\A", sig_a);
2024 cell->setPort("\\EN", sig_en);
2025 cell->set_src_attribute(src);
2026 return cell;
2027 }
2028
2029 RTLIL::Cell* RTLIL::Module::addFair(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src)
2030 {
2031 RTLIL::Cell *cell = addCell(name, "$fair");
2032 cell->setPort("\\A", sig_a);
2033 cell->setPort("\\EN", sig_en);
2034 cell->set_src_attribute(src);
2035 return cell;
2036 }
2037
2038 RTLIL::Cell* RTLIL::Module::addCover(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src)
2039 {
2040 RTLIL::Cell *cell = addCell(name, "$cover");
2041 cell->setPort("\\A", sig_a);
2042 cell->setPort("\\EN", sig_en);
2043 cell->set_src_attribute(src);
2044 return cell;
2045 }
2046
2047 RTLIL::Cell* RTLIL::Module::addEquiv(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, const std::string &src)
2048 {
2049 RTLIL::Cell *cell = addCell(name, "$equiv");
2050 cell->setPort("\\A", sig_a);
2051 cell->setPort("\\B", sig_b);
2052 cell->setPort("\\Y", sig_y);
2053 cell->set_src_attribute(src);
2054 return cell;
2055 }
2056
2057 RTLIL::Cell* RTLIL::Module::addSr(RTLIL::IdString name, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr, RTLIL::SigSpec sig_q, bool set_polarity, bool clr_polarity, const std::string &src)
2058 {
2059 RTLIL::Cell *cell = addCell(name, "$sr");
2060 cell->parameters["\\SET_POLARITY"] = set_polarity;
2061 cell->parameters["\\CLR_POLARITY"] = clr_polarity;
2062 cell->parameters["\\WIDTH"] = sig_q.size();
2063 cell->setPort("\\SET", sig_set);
2064 cell->setPort("\\CLR", sig_clr);
2065 cell->setPort("\\Q", sig_q);
2066 cell->set_src_attribute(src);
2067 return cell;
2068 }
2069
2070 RTLIL::Cell* RTLIL::Module::addFf(RTLIL::IdString name, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, const std::string &src)
2071 {
2072 RTLIL::Cell *cell = addCell(name, "$ff");
2073 cell->parameters["\\WIDTH"] = sig_q.size();
2074 cell->setPort("\\D", sig_d);
2075 cell->setPort("\\Q", sig_q);
2076 cell->set_src_attribute(src);
2077 return cell;
2078 }
2079
2080 RTLIL::Cell* RTLIL::Module::addDff(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, const std::string &src)
2081 {
2082 RTLIL::Cell *cell = addCell(name, "$dff");
2083 cell->parameters["\\CLK_POLARITY"] = clk_polarity;
2084 cell->parameters["\\WIDTH"] = sig_q.size();
2085 cell->setPort("\\CLK", sig_clk);
2086 cell->setPort("\\D", sig_d);
2087 cell->setPort("\\Q", sig_q);
2088 cell->set_src_attribute(src);
2089 return cell;
2090 }
2091
2092 RTLIL::Cell* RTLIL::Module::addDffe(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, bool en_polarity, const std::string &src)
2093 {
2094 RTLIL::Cell *cell = addCell(name, "$dffe");
2095 cell->parameters["\\CLK_POLARITY"] = clk_polarity;
2096 cell->parameters["\\EN_POLARITY"] = en_polarity;
2097 cell->parameters["\\WIDTH"] = sig_q.size();
2098 cell->setPort("\\CLK", sig_clk);
2099 cell->setPort("\\EN", sig_en);
2100 cell->setPort("\\D", sig_d);
2101 cell->setPort("\\Q", sig_q);
2102 cell->set_src_attribute(src);
2103 return cell;
2104 }
2105
2106 RTLIL::Cell* RTLIL::Module::addDffsr(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
2107 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
2108 {
2109 RTLIL::Cell *cell = addCell(name, "$dffsr");
2110 cell->parameters["\\CLK_POLARITY"] = clk_polarity;
2111 cell->parameters["\\SET_POLARITY"] = set_polarity;
2112 cell->parameters["\\CLR_POLARITY"] = clr_polarity;
2113 cell->parameters["\\WIDTH"] = sig_q.size();
2114 cell->setPort("\\CLK", sig_clk);
2115 cell->setPort("\\SET", sig_set);
2116 cell->setPort("\\CLR", sig_clr);
2117 cell->setPort("\\D", sig_d);
2118 cell->setPort("\\Q", sig_q);
2119 cell->set_src_attribute(src);
2120 return cell;
2121 }
2122
2123 RTLIL::Cell* RTLIL::Module::addAdff(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_arst, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q,
2124 RTLIL::Const arst_value, bool clk_polarity, bool arst_polarity, const std::string &src)
2125 {
2126 RTLIL::Cell *cell = addCell(name, "$adff");
2127 cell->parameters["\\CLK_POLARITY"] = clk_polarity;
2128 cell->parameters["\\ARST_POLARITY"] = arst_polarity;
2129 cell->parameters["\\ARST_VALUE"] = arst_value;
2130 cell->parameters["\\WIDTH"] = sig_q.size();
2131 cell->setPort("\\CLK", sig_clk);
2132 cell->setPort("\\ARST", sig_arst);
2133 cell->setPort("\\D", sig_d);
2134 cell->setPort("\\Q", sig_q);
2135 cell->set_src_attribute(src);
2136 return cell;
2137 }
2138
2139 RTLIL::Cell* RTLIL::Module::addDlatch(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity, const std::string &src)
2140 {
2141 RTLIL::Cell *cell = addCell(name, "$dlatch");
2142 cell->parameters["\\EN_POLARITY"] = en_polarity;
2143 cell->parameters["\\WIDTH"] = sig_q.size();
2144 cell->setPort("\\EN", sig_en);
2145 cell->setPort("\\D", sig_d);
2146 cell->setPort("\\Q", sig_q);
2147 cell->set_src_attribute(src);
2148 return cell;
2149 }
2150
2151 RTLIL::Cell* RTLIL::Module::addDlatchsr(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
2152 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
2153 {
2154 RTLIL::Cell *cell = addCell(name, "$dlatchsr");
2155 cell->parameters["\\EN_POLARITY"] = en_polarity;
2156 cell->parameters["\\SET_POLARITY"] = set_polarity;
2157 cell->parameters["\\CLR_POLARITY"] = clr_polarity;
2158 cell->parameters["\\WIDTH"] = sig_q.size();
2159 cell->setPort("\\EN", sig_en);
2160 cell->setPort("\\SET", sig_set);
2161 cell->setPort("\\CLR", sig_clr);
2162 cell->setPort("\\D", sig_d);
2163 cell->setPort("\\Q", sig_q);
2164 cell->set_src_attribute(src);
2165 return cell;
2166 }
2167
2168 RTLIL::Cell* RTLIL::Module::addFfGate(RTLIL::IdString name, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, const std::string &src)
2169 {
2170 RTLIL::Cell *cell = addCell(name, "$_FF_");
2171 cell->setPort("\\D", sig_d);
2172 cell->setPort("\\Q", sig_q);
2173 cell->set_src_attribute(src);
2174 return cell;
2175 }
2176
2177 RTLIL::Cell* RTLIL::Module::addDffGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, const std::string &src)
2178 {
2179 RTLIL::Cell *cell = addCell(name, stringf("$_DFF_%c_", clk_polarity ? 'P' : 'N'));
2180 cell->setPort("\\C", sig_clk);
2181 cell->setPort("\\D", sig_d);
2182 cell->setPort("\\Q", sig_q);
2183 cell->set_src_attribute(src);
2184 return cell;
2185 }
2186
2187 RTLIL::Cell* RTLIL::Module::addDffeGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, bool en_polarity, const std::string &src)
2188 {
2189 RTLIL::Cell *cell = addCell(name, stringf("$_DFFE_%c%c_", clk_polarity ? 'P' : 'N', en_polarity ? 'P' : 'N'));
2190 cell->setPort("\\C", sig_clk);
2191 cell->setPort("\\E", sig_en);
2192 cell->setPort("\\D", sig_d);
2193 cell->setPort("\\Q", sig_q);
2194 cell->set_src_attribute(src);
2195 return cell;
2196 }
2197
2198 RTLIL::Cell* RTLIL::Module::addDffsrGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
2199 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
2200 {
2201 RTLIL::Cell *cell = addCell(name, stringf("$_DFFSR_%c%c%c_", clk_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N'));
2202 cell->setPort("\\C", sig_clk);
2203 cell->setPort("\\S", sig_set);
2204 cell->setPort("\\R", sig_clr);
2205 cell->setPort("\\D", sig_d);
2206 cell->setPort("\\Q", sig_q);
2207 cell->set_src_attribute(src);
2208 return cell;
2209 }
2210
2211 RTLIL::Cell* RTLIL::Module::addAdffGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_arst, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q,
2212 bool arst_value, bool clk_polarity, bool arst_polarity, const std::string &src)
2213 {
2214 RTLIL::Cell *cell = addCell(name, stringf("$_DFF_%c%c%c_", clk_polarity ? 'P' : 'N', arst_polarity ? 'P' : 'N', arst_value ? '1' : '0'));
2215 cell->setPort("\\C", sig_clk);
2216 cell->setPort("\\R", sig_arst);
2217 cell->setPort("\\D", sig_d);
2218 cell->setPort("\\Q", sig_q);
2219 cell->set_src_attribute(src);
2220 return cell;
2221 }
2222
2223 RTLIL::Cell* RTLIL::Module::addDlatchGate(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity, const std::string &src)
2224 {
2225 RTLIL::Cell *cell = addCell(name, stringf("$_DLATCH_%c_", en_polarity ? 'P' : 'N'));
2226 cell->setPort("\\E", sig_en);
2227 cell->setPort("\\D", sig_d);
2228 cell->setPort("\\Q", sig_q);
2229 cell->set_src_attribute(src);
2230 return cell;
2231 }
2232
2233 RTLIL::Cell* RTLIL::Module::addDlatchsrGate(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
2234 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
2235 {
2236 RTLIL::Cell *cell = addCell(name, stringf("$_DLATCHSR_%c%c%c_", en_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N'));
2237 cell->setPort("\\E", sig_en);
2238 cell->setPort("\\S", sig_set);
2239 cell->setPort("\\R", sig_clr);
2240 cell->setPort("\\D", sig_d);
2241 cell->setPort("\\Q", sig_q);
2242 cell->set_src_attribute(src);
2243 return cell;
2244 }
2245
2246 RTLIL::SigSpec RTLIL::Module::Anyconst(RTLIL::IdString name, int width, const std::string &src)
2247 {
2248 RTLIL::SigSpec sig = addWire(NEW_ID, width);
2249 Cell *cell = addCell(name, "$anyconst");
2250 cell->setParam("\\WIDTH", width);
2251 cell->setPort("\\Y", sig);
2252 cell->set_src_attribute(src);
2253 return sig;
2254 }
2255
2256 RTLIL::SigSpec RTLIL::Module::Anyseq(RTLIL::IdString name, int width, const std::string &src)
2257 {
2258 RTLIL::SigSpec sig = addWire(NEW_ID, width);
2259 Cell *cell = addCell(name, "$anyseq");
2260 cell->setParam("\\WIDTH", width);
2261 cell->setPort("\\Y", sig);
2262 cell->set_src_attribute(src);
2263 return sig;
2264 }
2265
2266 RTLIL::SigSpec RTLIL::Module::Allconst(RTLIL::IdString name, int width, const std::string &src)
2267 {
2268 RTLIL::SigSpec sig = addWire(NEW_ID, width);
2269 Cell *cell = addCell(name, "$allconst");
2270 cell->setParam("\\WIDTH", width);
2271 cell->setPort("\\Y", sig);
2272 cell->set_src_attribute(src);
2273 return sig;
2274 }
2275
2276 RTLIL::SigSpec RTLIL::Module::Allseq(RTLIL::IdString name, int width, const std::string &src)
2277 {
2278 RTLIL::SigSpec sig = addWire(NEW_ID, width);
2279 Cell *cell = addCell(name, "$allseq");
2280 cell->setParam("\\WIDTH", width);
2281 cell->setPort("\\Y", sig);
2282 cell->set_src_attribute(src);
2283 return sig;
2284 }
2285
2286 RTLIL::SigSpec RTLIL::Module::Initstate(RTLIL::IdString name, const std::string &src)
2287 {
2288 RTLIL::SigSpec sig = addWire(NEW_ID);
2289 Cell *cell = addCell(name, "$initstate");
2290 cell->setPort("\\Y", sig);
2291 cell->set_src_attribute(src);
2292 return sig;
2293 }
2294
2295 RTLIL::Wire::Wire()
2296 {
2297 static unsigned int hashidx_count = 123456789;
2298 hashidx_count = mkhash_xorshift(hashidx_count);
2299 hashidx_ = hashidx_count;
2300
2301 module = nullptr;
2302 width = 1;
2303 start_offset = 0;
2304 port_id = 0;
2305 port_input = false;
2306 port_output = false;
2307 upto = false;
2308
2309 #ifdef WITH_PYTHON
2310 RTLIL::Wire::get_all_wires()->insert(std::pair<unsigned int, RTLIL::Wire*>(hashidx_, this));
2311 #endif
2312 }
2313
2314 RTLIL::Wire::~Wire()
2315 {
2316 #ifdef WITH_PYTHON
2317 RTLIL::Wire::get_all_wires()->erase(hashidx_);
2318 #endif
2319 }
2320
2321 #ifdef WITH_PYTHON
2322 static std::map<unsigned int, RTLIL::Wire*> all_wires;
2323 std::map<unsigned int, RTLIL::Wire*> *RTLIL::Wire::get_all_wires(void)
2324 {
2325 return &all_wires;
2326 }
2327 #endif
2328
2329 RTLIL::Memory::Memory()
2330 {
2331 static unsigned int hashidx_count = 123456789;
2332 hashidx_count = mkhash_xorshift(hashidx_count);
2333 hashidx_ = hashidx_count;
2334
2335 width = 1;
2336 start_offset = 0;
2337 size = 0;
2338 #ifdef WITH_PYTHON
2339 RTLIL::Memory::get_all_memorys()->insert(std::pair<unsigned int, RTLIL::Memory*>(hashidx_, this));
2340 #endif
2341 }
2342
2343 RTLIL::Cell::Cell() : module(nullptr)
2344 {
2345 static unsigned int hashidx_count = 123456789;
2346 hashidx_count = mkhash_xorshift(hashidx_count);
2347 hashidx_ = hashidx_count;
2348
2349 // log("#memtrace# %p\n", this);
2350 memhasher();
2351
2352 #ifdef WITH_PYTHON
2353 RTLIL::Cell::get_all_cells()->insert(std::pair<unsigned int, RTLIL::Cell*>(hashidx_, this));
2354 #endif
2355 }
2356
2357 RTLIL::Cell::~Cell()
2358 {
2359 #ifdef WITH_PYTHON
2360 RTLIL::Cell::get_all_cells()->erase(hashidx_);
2361 #endif
2362 }
2363
2364 #ifdef WITH_PYTHON
2365 static std::map<unsigned int, RTLIL::Cell*> all_cells;
2366 std::map<unsigned int, RTLIL::Cell*> *RTLIL::Cell::get_all_cells(void)
2367 {
2368 return &all_cells;
2369 }
2370 #endif
2371
2372 bool RTLIL::Cell::hasPort(RTLIL::IdString portname) const
2373 {
2374 return connections_.count(portname) != 0;
2375 }
2376
2377 void RTLIL::Cell::unsetPort(RTLIL::IdString portname)
2378 {
2379 RTLIL::SigSpec signal;
2380 auto conn_it = connections_.find(portname);
2381
2382 if (conn_it != connections_.end())
2383 {
2384 for (auto mon : module->monitors)
2385 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
2386
2387 if (module->design)
2388 for (auto mon : module->design->monitors)
2389 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
2390
2391 if (yosys_xtrace) {
2392 log("#X# Unconnect %s.%s.%s\n", log_id(this->module), log_id(this), log_id(portname));
2393 log_backtrace("-X- ", yosys_xtrace-1);
2394 }
2395
2396 connections_.erase(conn_it);
2397 }
2398 }
2399
2400 void RTLIL::Cell::setPort(RTLIL::IdString portname, RTLIL::SigSpec signal)
2401 {
2402 auto conn_it = connections_.find(portname);
2403
2404 if (conn_it == connections_.end()) {
2405 connections_[portname] = RTLIL::SigSpec();
2406 conn_it = connections_.find(portname);
2407 log_assert(conn_it != connections_.end());
2408 } else
2409 if (conn_it->second == signal)
2410 return;
2411
2412 for (auto mon : module->monitors)
2413 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
2414
2415 if (module->design)
2416 for (auto mon : module->design->monitors)
2417 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
2418
2419 if (yosys_xtrace) {
2420 log("#X# Connect %s.%s.%s = %s (%d)\n", log_id(this->module), log_id(this), log_id(portname), log_signal(signal), GetSize(signal));
2421 log_backtrace("-X- ", yosys_xtrace-1);
2422 }
2423
2424 conn_it->second = signal;
2425 }
2426
2427 const RTLIL::SigSpec &RTLIL::Cell::getPort(RTLIL::IdString portname) const
2428 {
2429 return connections_.at(portname);
2430 }
2431
2432 const dict<RTLIL::IdString, RTLIL::SigSpec> &RTLIL::Cell::connections() const
2433 {
2434 return connections_;
2435 }
2436
2437 bool RTLIL::Cell::known() const
2438 {
2439 if (yosys_celltypes.cell_known(type))
2440 return true;
2441 if (module && module->design && module->design->module(type))
2442 return true;
2443 return false;
2444 }
2445
2446 bool RTLIL::Cell::input(RTLIL::IdString portname) const
2447 {
2448 if (yosys_celltypes.cell_known(type))
2449 return yosys_celltypes.cell_input(type, portname);
2450 if (module && module->design) {
2451 RTLIL::Module *m = module->design->module(type);
2452 RTLIL::Wire *w = m ? m->wire(portname) : nullptr;
2453 return w && w->port_input;
2454 }
2455 return false;
2456 }
2457
2458 bool RTLIL::Cell::output(RTLIL::IdString portname) const
2459 {
2460 if (yosys_celltypes.cell_known(type))
2461 return yosys_celltypes.cell_output(type, portname);
2462 if (module && module->design) {
2463 RTLIL::Module *m = module->design->module(type);
2464 RTLIL::Wire *w = m ? m->wire(portname) : nullptr;
2465 return w && w->port_output;
2466 }
2467 return false;
2468 }
2469
2470 bool RTLIL::Cell::hasParam(RTLIL::IdString paramname) const
2471 {
2472 return parameters.count(paramname) != 0;
2473 }
2474
2475 void RTLIL::Cell::unsetParam(RTLIL::IdString paramname)
2476 {
2477 parameters.erase(paramname);
2478 }
2479
2480 void RTLIL::Cell::setParam(RTLIL::IdString paramname, RTLIL::Const value)
2481 {
2482 parameters[paramname] = value;
2483 }
2484
2485 const RTLIL::Const &RTLIL::Cell::getParam(RTLIL::IdString paramname) const
2486 {
2487 return parameters.at(paramname);
2488 }
2489
2490 void RTLIL::Cell::sort()
2491 {
2492 connections_.sort(sort_by_id_str());
2493 parameters.sort(sort_by_id_str());
2494 attributes.sort(sort_by_id_str());
2495 }
2496
2497 void RTLIL::Cell::check()
2498 {
2499 #ifndef NDEBUG
2500 InternalCellChecker checker(NULL, this);
2501 checker.check();
2502 #endif
2503 }
2504
2505 void RTLIL::Cell::fixup_parameters(bool set_a_signed, bool set_b_signed)
2506 {
2507 if (type.substr(0, 1) != "$" || type.substr(0, 2) == "$_" || type.substr(0, 8) == "$paramod" || type.substr(0,10) == "$fmcombine" ||
2508 type.substr(0, 9) == "$verific$" || type.substr(0, 7) == "$array:" || type.substr(0, 8) == "$extern:")
2509 return;
2510
2511 if (type == "$mux" || type == "$pmux") {
2512 parameters["\\WIDTH"] = GetSize(connections_["\\Y"]);
2513 if (type == "$pmux")
2514 parameters["\\S_WIDTH"] = GetSize(connections_["\\S"]);
2515 check();
2516 return;
2517 }
2518
2519 if (type == "$lut" || type == "$sop") {
2520 parameters["\\WIDTH"] = GetSize(connections_["\\A"]);
2521 return;
2522 }
2523
2524 if (type == "$fa") {
2525 parameters["\\WIDTH"] = GetSize(connections_["\\Y"]);
2526 return;
2527 }
2528
2529 if (type == "$lcu") {
2530 parameters["\\WIDTH"] = GetSize(connections_["\\CO"]);
2531 return;
2532 }
2533
2534 bool signedness_ab = !type.in("$slice", "$concat", "$macc");
2535
2536 if (connections_.count("\\A")) {
2537 if (signedness_ab) {
2538 if (set_a_signed)
2539 parameters["\\A_SIGNED"] = true;
2540 else if (parameters.count("\\A_SIGNED") == 0)
2541 parameters["\\A_SIGNED"] = false;
2542 }
2543 parameters["\\A_WIDTH"] = GetSize(connections_["\\A"]);
2544 }
2545
2546 if (connections_.count("\\B")) {
2547 if (signedness_ab) {
2548 if (set_b_signed)
2549 parameters["\\B_SIGNED"] = true;
2550 else if (parameters.count("\\B_SIGNED") == 0)
2551 parameters["\\B_SIGNED"] = false;
2552 }
2553 parameters["\\B_WIDTH"] = GetSize(connections_["\\B"]);
2554 }
2555
2556 if (connections_.count("\\Y"))
2557 parameters["\\Y_WIDTH"] = GetSize(connections_["\\Y"]);
2558
2559 if (connections_.count("\\Q"))
2560 parameters["\\WIDTH"] = GetSize(connections_["\\Q"]);
2561
2562 check();
2563 }
2564
2565 RTLIL::SigChunk::SigChunk()
2566 {
2567 wire = NULL;
2568 width = 0;
2569 offset = 0;
2570 }
2571
2572 RTLIL::SigChunk::SigChunk(const RTLIL::Const &value)
2573 {
2574 wire = NULL;
2575 data = value.bits;
2576 width = GetSize(data);
2577 offset = 0;
2578 }
2579
2580 RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire)
2581 {
2582 log_assert(wire != nullptr);
2583 this->wire = wire;
2584 this->width = wire->width;
2585 this->offset = 0;
2586 }
2587
2588 RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire, int offset, int width)
2589 {
2590 log_assert(wire != nullptr);
2591 this->wire = wire;
2592 this->width = width;
2593 this->offset = offset;
2594 }
2595
2596 RTLIL::SigChunk::SigChunk(const std::string &str)
2597 {
2598 wire = NULL;
2599 data = RTLIL::Const(str).bits;
2600 width = GetSize(data);
2601 offset = 0;
2602 }
2603
2604 RTLIL::SigChunk::SigChunk(int val, int width)
2605 {
2606 wire = NULL;
2607 data = RTLIL::Const(val, width).bits;
2608 this->width = GetSize(data);
2609 offset = 0;
2610 }
2611
2612 RTLIL::SigChunk::SigChunk(RTLIL::State bit, int width)
2613 {
2614 wire = NULL;
2615 data = RTLIL::Const(bit, width).bits;
2616 this->width = GetSize(data);
2617 offset = 0;
2618 }
2619
2620 RTLIL::SigChunk::SigChunk(RTLIL::SigBit bit)
2621 {
2622 wire = bit.wire;
2623 offset = 0;
2624 if (wire == NULL)
2625 data = RTLIL::Const(bit.data).bits;
2626 else
2627 offset = bit.offset;
2628 width = 1;
2629 }
2630
2631 RTLIL::SigChunk::SigChunk(const RTLIL::SigChunk &sigchunk) : data(sigchunk.data)
2632 {
2633 wire = sigchunk.wire;
2634 data = sigchunk.data;
2635 width = sigchunk.width;
2636 offset = sigchunk.offset;
2637 }
2638
2639 RTLIL::SigChunk RTLIL::SigChunk::extract(int offset, int length) const
2640 {
2641 RTLIL::SigChunk ret;
2642 if (wire) {
2643 ret.wire = wire;
2644 ret.offset = this->offset + offset;
2645 ret.width = length;
2646 } else {
2647 for (int i = 0; i < length; i++)
2648 ret.data.push_back(data[offset+i]);
2649 ret.width = length;
2650 }
2651 return ret;
2652 }
2653
2654 bool RTLIL::SigChunk::operator <(const RTLIL::SigChunk &other) const
2655 {
2656 if (wire && other.wire)
2657 if (wire->name != other.wire->name)
2658 return wire->name < other.wire->name;
2659
2660 if (wire != other.wire)
2661 return wire < other.wire;
2662
2663 if (offset != other.offset)
2664 return offset < other.offset;
2665
2666 if (width != other.width)
2667 return width < other.width;
2668
2669 return data < other.data;
2670 }
2671
2672 bool RTLIL::SigChunk::operator ==(const RTLIL::SigChunk &other) const
2673 {
2674 return wire == other.wire && width == other.width && offset == other.offset && data == other.data;
2675 }
2676
2677 bool RTLIL::SigChunk::operator !=(const RTLIL::SigChunk &other) const
2678 {
2679 if (*this == other)
2680 return false;
2681 return true;
2682 }
2683
2684 RTLIL::SigSpec::SigSpec()
2685 {
2686 width_ = 0;
2687 hash_ = 0;
2688 }
2689
2690 RTLIL::SigSpec::SigSpec(const RTLIL::SigSpec &other)
2691 {
2692 *this = other;
2693 }
2694
2695 RTLIL::SigSpec::SigSpec(std::initializer_list<RTLIL::SigSpec> parts)
2696 {
2697 cover("kernel.rtlil.sigspec.init.list");
2698
2699 width_ = 0;
2700 hash_ = 0;
2701
2702 std::vector<RTLIL::SigSpec> parts_vec(parts.begin(), parts.end());
2703 for (auto it = parts_vec.rbegin(); it != parts_vec.rend(); it++)
2704 append(*it);
2705 }
2706
2707 const RTLIL::SigSpec &RTLIL::SigSpec::operator=(const RTLIL::SigSpec &other)
2708 {
2709 cover("kernel.rtlil.sigspec.assign");
2710
2711 width_ = other.width_;
2712 hash_ = other.hash_;
2713 chunks_ = other.chunks_;
2714 bits_.clear();
2715
2716 if (!other.bits_.empty())
2717 {
2718 RTLIL::SigChunk *last = NULL;
2719 int last_end_offset = 0;
2720
2721 for (auto &bit : other.bits_) {
2722 if (last && bit.wire == last->wire) {
2723 if (bit.wire == NULL) {
2724 last->data.push_back(bit.data);
2725 last->width++;
2726 continue;
2727 } else if (last_end_offset == bit.offset) {
2728 last_end_offset++;
2729 last->width++;
2730 continue;
2731 }
2732 }
2733 chunks_.push_back(bit);
2734 last = &chunks_.back();
2735 last_end_offset = bit.offset + 1;
2736 }
2737
2738 check();
2739 }
2740
2741 return *this;
2742 }
2743
2744 RTLIL::SigSpec::SigSpec(const RTLIL::Const &value)
2745 {
2746 cover("kernel.rtlil.sigspec.init.const");
2747
2748 chunks_.push_back(RTLIL::SigChunk(value));
2749 width_ = chunks_.back().width;
2750 hash_ = 0;
2751 check();
2752 }
2753
2754 RTLIL::SigSpec::SigSpec(const RTLIL::SigChunk &chunk)
2755 {
2756 cover("kernel.rtlil.sigspec.init.chunk");
2757
2758 chunks_.push_back(chunk);
2759 width_ = chunks_.back().width;
2760 hash_ = 0;
2761 check();
2762 }
2763
2764 RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire)
2765 {
2766 cover("kernel.rtlil.sigspec.init.wire");
2767
2768 chunks_.push_back(RTLIL::SigChunk(wire));
2769 width_ = chunks_.back().width;
2770 hash_ = 0;
2771 check();
2772 }
2773
2774 RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire, int offset, int width)
2775 {
2776 cover("kernel.rtlil.sigspec.init.wire_part");
2777
2778 chunks_.push_back(RTLIL::SigChunk(wire, offset, width));
2779 width_ = chunks_.back().width;
2780 hash_ = 0;
2781 check();
2782 }
2783
2784 RTLIL::SigSpec::SigSpec(const std::string &str)
2785 {
2786 cover("kernel.rtlil.sigspec.init.str");
2787
2788 chunks_.push_back(RTLIL::SigChunk(str));
2789 width_ = chunks_.back().width;
2790 hash_ = 0;
2791 check();
2792 }
2793
2794 RTLIL::SigSpec::SigSpec(int val, int width)
2795 {
2796 cover("kernel.rtlil.sigspec.init.int");
2797
2798 chunks_.push_back(RTLIL::SigChunk(val, width));
2799 width_ = width;
2800 hash_ = 0;
2801 check();
2802 }
2803
2804 RTLIL::SigSpec::SigSpec(RTLIL::State bit, int width)
2805 {
2806 cover("kernel.rtlil.sigspec.init.state");
2807
2808 chunks_.push_back(RTLIL::SigChunk(bit, width));
2809 width_ = width;
2810 hash_ = 0;
2811 check();
2812 }
2813
2814 RTLIL::SigSpec::SigSpec(RTLIL::SigBit bit, int width)
2815 {
2816 cover("kernel.rtlil.sigspec.init.bit");
2817
2818 if (bit.wire == NULL)
2819 chunks_.push_back(RTLIL::SigChunk(bit.data, width));
2820 else
2821 for (int i = 0; i < width; i++)
2822 chunks_.push_back(bit);
2823 width_ = width;
2824 hash_ = 0;
2825 check();
2826 }
2827
2828 RTLIL::SigSpec::SigSpec(std::vector<RTLIL::SigChunk> chunks)
2829 {
2830 cover("kernel.rtlil.sigspec.init.stdvec_chunks");
2831
2832 width_ = 0;
2833 hash_ = 0;
2834 for (auto &c : chunks)
2835 append(c);
2836 check();
2837 }
2838
2839 RTLIL::SigSpec::SigSpec(std::vector<RTLIL::SigBit> bits)
2840 {
2841 cover("kernel.rtlil.sigspec.init.stdvec_bits");
2842
2843 width_ = 0;
2844 hash_ = 0;
2845 for (auto &bit : bits)
2846 append_bit(bit);
2847 check();
2848 }
2849
2850 RTLIL::SigSpec::SigSpec(pool<RTLIL::SigBit> bits)
2851 {
2852 cover("kernel.rtlil.sigspec.init.pool_bits");
2853
2854 width_ = 0;
2855 hash_ = 0;
2856 for (auto &bit : bits)
2857 append_bit(bit);
2858 check();
2859 }
2860
2861 RTLIL::SigSpec::SigSpec(std::set<RTLIL::SigBit> bits)
2862 {
2863 cover("kernel.rtlil.sigspec.init.stdset_bits");
2864
2865 width_ = 0;
2866 hash_ = 0;
2867 for (auto &bit : bits)
2868 append_bit(bit);
2869 check();
2870 }
2871
2872 RTLIL::SigSpec::SigSpec(bool bit)
2873 {
2874 cover("kernel.rtlil.sigspec.init.bool");
2875
2876 width_ = 0;
2877 hash_ = 0;
2878 append_bit(bit);
2879 check();
2880 }
2881
2882 void RTLIL::SigSpec::pack() const
2883 {
2884 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
2885
2886 if (that->bits_.empty())
2887 return;
2888
2889 cover("kernel.rtlil.sigspec.convert.pack");
2890 log_assert(that->chunks_.empty());
2891
2892 std::vector<RTLIL::SigBit> old_bits;
2893 old_bits.swap(that->bits_);
2894
2895 RTLIL::SigChunk *last = NULL;
2896 int last_end_offset = 0;
2897
2898 for (auto &bit : old_bits) {
2899 if (last && bit.wire == last->wire) {
2900 if (bit.wire == NULL) {
2901 last->data.push_back(bit.data);
2902 last->width++;
2903 continue;
2904 } else if (last_end_offset == bit.offset) {
2905 last_end_offset++;
2906 last->width++;
2907 continue;
2908 }
2909 }
2910 that->chunks_.push_back(bit);
2911 last = &that->chunks_.back();
2912 last_end_offset = bit.offset + 1;
2913 }
2914
2915 check();
2916 }
2917
2918 void RTLIL::SigSpec::unpack() const
2919 {
2920 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
2921
2922 if (that->chunks_.empty())
2923 return;
2924
2925 cover("kernel.rtlil.sigspec.convert.unpack");
2926 log_assert(that->bits_.empty());
2927
2928 that->bits_.reserve(that->width_);
2929 for (auto &c : that->chunks_)
2930 for (int i = 0; i < c.width; i++)
2931 that->bits_.push_back(RTLIL::SigBit(c, i));
2932
2933 that->chunks_.clear();
2934 that->hash_ = 0;
2935 }
2936
2937 void RTLIL::SigSpec::updhash() const
2938 {
2939 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
2940
2941 if (that->hash_ != 0)
2942 return;
2943
2944 cover("kernel.rtlil.sigspec.hash");
2945 that->pack();
2946
2947 that->hash_ = mkhash_init;
2948 for (auto &c : that->chunks_)
2949 if (c.wire == NULL) {
2950 for (auto &v : c.data)
2951 that->hash_ = mkhash(that->hash_, v);
2952 } else {
2953 that->hash_ = mkhash(that->hash_, c.wire->name.index_);
2954 that->hash_ = mkhash(that->hash_, c.offset);
2955 that->hash_ = mkhash(that->hash_, c.width);
2956 }
2957
2958 if (that->hash_ == 0)
2959 that->hash_ = 1;
2960 }
2961
2962 void RTLIL::SigSpec::sort()
2963 {
2964 unpack();
2965 cover("kernel.rtlil.sigspec.sort");
2966 std::sort(bits_.begin(), bits_.end());
2967 }
2968
2969 void RTLIL::SigSpec::sort_and_unify()
2970 {
2971 unpack();
2972 cover("kernel.rtlil.sigspec.sort_and_unify");
2973
2974 // A copy of the bits vector is used to prevent duplicating the logic from
2975 // SigSpec::SigSpec(std::vector<SigBit>). This incurrs an extra copy but
2976 // that isn't showing up as significant in profiles.
2977 std::vector<SigBit> unique_bits = bits_;
2978 std::sort(unique_bits.begin(), unique_bits.end());
2979 auto last = std::unique(unique_bits.begin(), unique_bits.end());
2980 unique_bits.erase(last, unique_bits.end());
2981
2982 *this = unique_bits;
2983 }
2984
2985 void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with)
2986 {
2987 replace(pattern, with, this);
2988 }
2989
2990 void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with, RTLIL::SigSpec *other) const
2991 {
2992 log_assert(other != NULL);
2993 log_assert(width_ == other->width_);
2994 log_assert(pattern.width_ == with.width_);
2995
2996 pattern.unpack();
2997 with.unpack();
2998 unpack();
2999 other->unpack();
3000
3001 for (int i = 0; i < GetSize(pattern.bits_); i++) {
3002 if (pattern.bits_[i].wire != NULL) {
3003 for (int j = 0; j < GetSize(bits_); j++) {
3004 if (bits_[j] == pattern.bits_[i]) {
3005 other->bits_[j] = with.bits_[i];
3006 }
3007 }
3008 }
3009 }
3010
3011 other->check();
3012 }
3013
3014 void RTLIL::SigSpec::replace(const dict<RTLIL::SigBit, RTLIL::SigBit> &rules)
3015 {
3016 replace(rules, this);
3017 }
3018
3019 void RTLIL::SigSpec::replace(const dict<RTLIL::SigBit, RTLIL::SigBit> &rules, RTLIL::SigSpec *other) const
3020 {
3021 cover("kernel.rtlil.sigspec.replace_dict");
3022
3023 log_assert(other != NULL);
3024 log_assert(width_ == other->width_);
3025
3026 unpack();
3027 other->unpack();
3028
3029 for (int i = 0; i < GetSize(bits_); i++) {
3030 auto it = rules.find(bits_[i]);
3031 if (it != rules.end())
3032 other->bits_[i] = it->second;
3033 }
3034
3035 other->check();
3036 }
3037
3038 void RTLIL::SigSpec::replace(const std::map<RTLIL::SigBit, RTLIL::SigBit> &rules)
3039 {
3040 replace(rules, this);
3041 }
3042
3043 void RTLIL::SigSpec::replace(const std::map<RTLIL::SigBit, RTLIL::SigBit> &rules, RTLIL::SigSpec *other) const
3044 {
3045 cover("kernel.rtlil.sigspec.replace_map");
3046
3047 log_assert(other != NULL);
3048 log_assert(width_ == other->width_);
3049
3050 unpack();
3051 other->unpack();
3052
3053 for (int i = 0; i < GetSize(bits_); i++) {
3054 auto it = rules.find(bits_[i]);
3055 if (it != rules.end())
3056 other->bits_[i] = it->second;
3057 }
3058
3059 other->check();
3060 }
3061
3062 void RTLIL::SigSpec::remove(const RTLIL::SigSpec &pattern)
3063 {
3064 remove2(pattern, NULL);
3065 }
3066
3067 void RTLIL::SigSpec::remove(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other) const
3068 {
3069 RTLIL::SigSpec tmp = *this;
3070 tmp.remove2(pattern, other);
3071 }
3072
3073 void RTLIL::SigSpec::remove2(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other)
3074 {
3075 if (other)
3076 cover("kernel.rtlil.sigspec.remove_other");
3077 else
3078 cover("kernel.rtlil.sigspec.remove");
3079
3080 unpack();
3081 if (other != NULL) {
3082 log_assert(width_ == other->width_);
3083 other->unpack();
3084 }
3085
3086 for (int i = GetSize(bits_) - 1; i >= 0; i--)
3087 {
3088 if (bits_[i].wire == NULL) continue;
3089
3090 for (auto &pattern_chunk : pattern.chunks())
3091 if (bits_[i].wire == pattern_chunk.wire &&
3092 bits_[i].offset >= pattern_chunk.offset &&
3093 bits_[i].offset < pattern_chunk.offset + pattern_chunk.width) {
3094 bits_.erase(bits_.begin() + i);
3095 width_--;
3096 if (other != NULL) {
3097 other->bits_.erase(other->bits_.begin() + i);
3098 other->width_--;
3099 }
3100 break;
3101 }
3102 }
3103
3104 check();
3105 }
3106
3107 void RTLIL::SigSpec::remove(const pool<RTLIL::SigBit> &pattern)
3108 {
3109 remove2(pattern, NULL);
3110 }
3111
3112 void RTLIL::SigSpec::remove(const pool<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other) const
3113 {
3114 RTLIL::SigSpec tmp = *this;
3115 tmp.remove2(pattern, other);
3116 }
3117
3118 void RTLIL::SigSpec::remove2(const pool<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other)
3119 {
3120 if (other)
3121 cover("kernel.rtlil.sigspec.remove_other");
3122 else
3123 cover("kernel.rtlil.sigspec.remove");
3124
3125 unpack();
3126
3127 if (other != NULL) {
3128 log_assert(width_ == other->width_);
3129 other->unpack();
3130 }
3131
3132 for (int i = GetSize(bits_) - 1; i >= 0; i--) {
3133 if (bits_[i].wire != NULL && pattern.count(bits_[i])) {
3134 bits_.erase(bits_.begin() + i);
3135 width_--;
3136 if (other != NULL) {
3137 other->bits_.erase(other->bits_.begin() + i);
3138 other->width_--;
3139 }
3140 }
3141 }
3142
3143 check();
3144 }
3145
3146 void RTLIL::SigSpec::remove2(const std::set<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other)
3147 {
3148 if (other)
3149 cover("kernel.rtlil.sigspec.remove_other");
3150 else
3151 cover("kernel.rtlil.sigspec.remove");
3152
3153 unpack();
3154
3155 if (other != NULL) {
3156 log_assert(width_ == other->width_);
3157 other->unpack();
3158 }
3159
3160 for (int i = GetSize(bits_) - 1; i >= 0; i--) {
3161 if (bits_[i].wire != NULL && pattern.count(bits_[i])) {
3162 bits_.erase(bits_.begin() + i);
3163 width_--;
3164 if (other != NULL) {
3165 other->bits_.erase(other->bits_.begin() + i);
3166 other->width_--;
3167 }
3168 }
3169 }
3170
3171 check();
3172 }
3173
3174 RTLIL::SigSpec RTLIL::SigSpec::extract(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec *other) const
3175 {
3176 if (other)
3177 cover("kernel.rtlil.sigspec.extract_other");
3178 else
3179 cover("kernel.rtlil.sigspec.extract");
3180
3181 log_assert(other == NULL || width_ == other->width_);
3182
3183 RTLIL::SigSpec ret;
3184 std::vector<RTLIL::SigBit> bits_match = to_sigbit_vector();
3185
3186 for (auto& pattern_chunk : pattern.chunks()) {
3187 if (other) {
3188 std::vector<RTLIL::SigBit> bits_other = other->to_sigbit_vector();
3189 for (int i = 0; i < width_; i++)
3190 if (bits_match[i].wire &&
3191 bits_match[i].wire == pattern_chunk.wire &&
3192 bits_match[i].offset >= pattern_chunk.offset &&
3193 bits_match[i].offset < pattern_chunk.offset + pattern_chunk.width)
3194 ret.append_bit(bits_other[i]);
3195 } else {
3196 for (int i = 0; i < width_; i++)
3197 if (bits_match[i].wire &&
3198 bits_match[i].wire == pattern_chunk.wire &&
3199 bits_match[i].offset >= pattern_chunk.offset &&
3200 bits_match[i].offset < pattern_chunk.offset + pattern_chunk.width)
3201 ret.append_bit(bits_match[i]);
3202 }
3203 }
3204
3205 ret.check();
3206 return ret;
3207 }
3208
3209 RTLIL::SigSpec RTLIL::SigSpec::extract(const pool<RTLIL::SigBit> &pattern, const RTLIL::SigSpec *other) const
3210 {
3211 if (other)
3212 cover("kernel.rtlil.sigspec.extract_other");
3213 else
3214 cover("kernel.rtlil.sigspec.extract");
3215
3216 log_assert(other == NULL || width_ == other->width_);
3217
3218 std::vector<RTLIL::SigBit> bits_match = to_sigbit_vector();
3219 RTLIL::SigSpec ret;
3220
3221 if (other) {
3222 std::vector<RTLIL::SigBit> bits_other = other->to_sigbit_vector();
3223 for (int i = 0; i < width_; i++)
3224 if (bits_match[i].wire && pattern.count(bits_match[i]))
3225 ret.append_bit(bits_other[i]);
3226 } else {
3227 for (int i = 0; i < width_; i++)
3228 if (bits_match[i].wire && pattern.count(bits_match[i]))
3229 ret.append_bit(bits_match[i]);
3230 }
3231
3232 ret.check();
3233 return ret;
3234 }
3235
3236 void RTLIL::SigSpec::replace(int offset, const RTLIL::SigSpec &with)
3237 {
3238 cover("kernel.rtlil.sigspec.replace_pos");
3239
3240 unpack();
3241 with.unpack();
3242
3243 log_assert(offset >= 0);
3244 log_assert(with.width_ >= 0);
3245 log_assert(offset+with.width_ <= width_);
3246
3247 for (int i = 0; i < with.width_; i++)
3248 bits_.at(offset + i) = with.bits_.at(i);
3249
3250 check();
3251 }
3252
3253 void RTLIL::SigSpec::remove_const()
3254 {
3255 if (packed())
3256 {
3257 cover("kernel.rtlil.sigspec.remove_const.packed");
3258
3259 std::vector<RTLIL::SigChunk> new_chunks;
3260 new_chunks.reserve(GetSize(chunks_));
3261
3262 width_ = 0;
3263 for (auto &chunk : chunks_)
3264 if (chunk.wire != NULL) {
3265 new_chunks.push_back(chunk);
3266 width_ += chunk.width;
3267 }
3268
3269 chunks_.swap(new_chunks);
3270 }
3271 else
3272 {
3273 cover("kernel.rtlil.sigspec.remove_const.unpacked");
3274
3275 std::vector<RTLIL::SigBit> new_bits;
3276 new_bits.reserve(width_);
3277
3278 for (auto &bit : bits_)
3279 if (bit.wire != NULL)
3280 new_bits.push_back(bit);
3281
3282 bits_.swap(new_bits);
3283 width_ = bits_.size();
3284 }
3285
3286 check();
3287 }
3288
3289 void RTLIL::SigSpec::remove(int offset, int length)
3290 {
3291 cover("kernel.rtlil.sigspec.remove_pos");
3292
3293 unpack();
3294
3295 log_assert(offset >= 0);
3296 log_assert(length >= 0);
3297 log_assert(offset + length <= width_);
3298
3299 bits_.erase(bits_.begin() + offset, bits_.begin() + offset + length);
3300 width_ = bits_.size();
3301
3302 check();
3303 }
3304
3305 RTLIL::SigSpec RTLIL::SigSpec::extract(int offset, int length) const
3306 {
3307 unpack();
3308 cover("kernel.rtlil.sigspec.extract_pos");
3309 return std::vector<RTLIL::SigBit>(bits_.begin() + offset, bits_.begin() + offset + length);
3310 }
3311
3312 void RTLIL::SigSpec::append(const RTLIL::SigSpec &signal)
3313 {
3314 if (signal.width_ == 0)
3315 return;
3316
3317 if (width_ == 0) {
3318 *this = signal;
3319 return;
3320 }
3321
3322 cover("kernel.rtlil.sigspec.append");
3323
3324 if (packed() != signal.packed()) {
3325 pack();
3326 signal.pack();
3327 }
3328
3329 if (packed())
3330 for (auto &other_c : signal.chunks_)
3331 {
3332 auto &my_last_c = chunks_.back();
3333 if (my_last_c.wire == NULL && other_c.wire == NULL) {
3334 auto &this_data = my_last_c.data;
3335 auto &other_data = other_c.data;
3336 this_data.insert(this_data.end(), other_data.begin(), other_data.end());
3337 my_last_c.width += other_c.width;
3338 } else
3339 if (my_last_c.wire == other_c.wire && my_last_c.offset + my_last_c.width == other_c.offset) {
3340 my_last_c.width += other_c.width;
3341 } else
3342 chunks_.push_back(other_c);
3343 }
3344 else
3345 bits_.insert(bits_.end(), signal.bits_.begin(), signal.bits_.end());
3346
3347 width_ += signal.width_;
3348 check();
3349 }
3350
3351 void RTLIL::SigSpec::append_bit(const RTLIL::SigBit &bit)
3352 {
3353 if (packed())
3354 {
3355 cover("kernel.rtlil.sigspec.append_bit.packed");
3356
3357 if (chunks_.size() == 0)
3358 chunks_.push_back(bit);
3359 else
3360 if (bit.wire == NULL)
3361 if (chunks_.back().wire == NULL) {
3362 chunks_.back().data.push_back(bit.data);
3363 chunks_.back().width++;
3364 } else
3365 chunks_.push_back(bit);
3366 else
3367 if (chunks_.back().wire == bit.wire && chunks_.back().offset + chunks_.back().width == bit.offset)
3368 chunks_.back().width++;
3369 else
3370 chunks_.push_back(bit);
3371 }
3372 else
3373 {
3374 cover("kernel.rtlil.sigspec.append_bit.unpacked");
3375 bits_.push_back(bit);
3376 }
3377
3378 width_++;
3379 check();
3380 }
3381
3382 void RTLIL::SigSpec::extend_u0(int width, bool is_signed)
3383 {
3384 cover("kernel.rtlil.sigspec.extend_u0");
3385
3386 pack();
3387
3388 if (width_ > width)
3389 remove(width, width_ - width);
3390
3391 if (width_ < width) {
3392 RTLIL::SigBit padding = width_ > 0 ? (*this)[width_ - 1] : RTLIL::State::Sx;
3393 if (!is_signed)
3394 padding = RTLIL::State::S0;
3395 while (width_ < width)
3396 append(padding);
3397 }
3398
3399 }
3400
3401 RTLIL::SigSpec RTLIL::SigSpec::repeat(int num) const
3402 {
3403 cover("kernel.rtlil.sigspec.repeat");
3404
3405 RTLIL::SigSpec sig;
3406 for (int i = 0; i < num; i++)
3407 sig.append(*this);
3408 return sig;
3409 }
3410
3411 #ifndef NDEBUG
3412 void RTLIL::SigSpec::check() const
3413 {
3414 if (width_ > 64)
3415 {
3416 cover("kernel.rtlil.sigspec.check.skip");
3417 }
3418 else if (packed())
3419 {
3420 cover("kernel.rtlil.sigspec.check.packed");
3421
3422 int w = 0;
3423 for (size_t i = 0; i < chunks_.size(); i++) {
3424 const RTLIL::SigChunk chunk = chunks_[i];
3425 if (chunk.wire == NULL) {
3426 if (i > 0)
3427 log_assert(chunks_[i-1].wire != NULL);
3428 log_assert(chunk.offset == 0);
3429 log_assert(chunk.data.size() == (size_t)chunk.width);
3430 } else {
3431 if (i > 0 && chunks_[i-1].wire == chunk.wire)
3432 log_assert(chunk.offset != chunks_[i-1].offset + chunks_[i-1].width);
3433 log_assert(chunk.offset >= 0);
3434 log_assert(chunk.width >= 0);
3435 log_assert(chunk.offset + chunk.width <= chunk.wire->width);
3436 log_assert(chunk.data.size() == 0);
3437 }
3438 w += chunk.width;
3439 }
3440 log_assert(w == width_);
3441 log_assert(bits_.empty());
3442 }
3443 else
3444 {
3445 cover("kernel.rtlil.sigspec.check.unpacked");
3446
3447 log_assert(width_ == GetSize(bits_));
3448 log_assert(chunks_.empty());
3449 }
3450 }
3451 #endif
3452
3453 bool RTLIL::SigSpec::operator <(const RTLIL::SigSpec &other) const
3454 {
3455 cover("kernel.rtlil.sigspec.comp_lt");
3456
3457 if (this == &other)
3458 return false;
3459
3460 if (width_ != other.width_)
3461 return width_ < other.width_;
3462
3463 pack();
3464 other.pack();
3465
3466 if (chunks_.size() != other.chunks_.size())
3467 return chunks_.size() < other.chunks_.size();
3468
3469 updhash();
3470 other.updhash();
3471
3472 if (hash_ != other.hash_)
3473 return hash_ < other.hash_;
3474
3475 for (size_t i = 0; i < chunks_.size(); i++)
3476 if (chunks_[i] != other.chunks_[i]) {
3477 cover("kernel.rtlil.sigspec.comp_lt.hash_collision");
3478 return chunks_[i] < other.chunks_[i];
3479 }
3480
3481 cover("kernel.rtlil.sigspec.comp_lt.equal");
3482 return false;
3483 }
3484
3485 bool RTLIL::SigSpec::operator ==(const RTLIL::SigSpec &other) const
3486 {
3487 cover("kernel.rtlil.sigspec.comp_eq");
3488
3489 if (this == &other)
3490 return true;
3491
3492 if (width_ != other.width_)
3493 return false;
3494
3495 pack();
3496 other.pack();
3497
3498 if (chunks_.size() != chunks_.size())
3499 return false;
3500
3501 updhash();
3502 other.updhash();
3503
3504 if (hash_ != other.hash_)
3505 return false;
3506
3507 for (size_t i = 0; i < chunks_.size(); i++)
3508 if (chunks_[i] != other.chunks_[i]) {
3509 cover("kernel.rtlil.sigspec.comp_eq.hash_collision");
3510 return false;
3511 }
3512
3513 cover("kernel.rtlil.sigspec.comp_eq.equal");
3514 return true;
3515 }
3516
3517 bool RTLIL::SigSpec::is_wire() const
3518 {
3519 cover("kernel.rtlil.sigspec.is_wire");
3520
3521 pack();
3522 return GetSize(chunks_) == 1 && chunks_[0].wire && chunks_[0].wire->width == width_;
3523 }
3524
3525 bool RTLIL::SigSpec::is_chunk() const
3526 {
3527 cover("kernel.rtlil.sigspec.is_chunk");
3528
3529 pack();
3530 return GetSize(chunks_) == 1;
3531 }
3532
3533 bool RTLIL::SigSpec::is_fully_const() const
3534 {
3535 cover("kernel.rtlil.sigspec.is_fully_const");
3536
3537 pack();
3538 for (auto it = chunks_.begin(); it != chunks_.end(); it++)
3539 if (it->width > 0 && it->wire != NULL)
3540 return false;
3541 return true;
3542 }
3543
3544 bool RTLIL::SigSpec::is_fully_zero() const
3545 {
3546 cover("kernel.rtlil.sigspec.is_fully_zero");
3547
3548 pack();
3549 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
3550 if (it->width > 0 && it->wire != NULL)
3551 return false;
3552 for (size_t i = 0; i < it->data.size(); i++)
3553 if (it->data[i] != RTLIL::State::S0)
3554 return false;
3555 }
3556 return true;
3557 }
3558
3559 bool RTLIL::SigSpec::is_fully_ones() const
3560 {
3561 cover("kernel.rtlil.sigspec.is_fully_ones");
3562
3563 pack();
3564 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
3565 if (it->width > 0 && it->wire != NULL)
3566 return false;
3567 for (size_t i = 0; i < it->data.size(); i++)
3568 if (it->data[i] != RTLIL::State::S1)
3569 return false;
3570 }
3571 return true;
3572 }
3573
3574 bool RTLIL::SigSpec::is_fully_def() const
3575 {
3576 cover("kernel.rtlil.sigspec.is_fully_def");
3577
3578 pack();
3579 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
3580 if (it->width > 0 && it->wire != NULL)
3581 return false;
3582 for (size_t i = 0; i < it->data.size(); i++)
3583 if (it->data[i] != RTLIL::State::S0 && it->data[i] != RTLIL::State::S1)
3584 return false;
3585 }
3586 return true;
3587 }
3588
3589 bool RTLIL::SigSpec::is_fully_undef() const
3590 {
3591 cover("kernel.rtlil.sigspec.is_fully_undef");
3592
3593 pack();
3594 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
3595 if (it->width > 0 && it->wire != NULL)
3596 return false;
3597 for (size_t i = 0; i < it->data.size(); i++)
3598 if (it->data[i] != RTLIL::State::Sx && it->data[i] != RTLIL::State::Sz)
3599 return false;
3600 }
3601 return true;
3602 }
3603
3604 bool RTLIL::SigSpec::has_const() const
3605 {
3606 cover("kernel.rtlil.sigspec.has_const");
3607
3608 pack();
3609 for (auto it = chunks_.begin(); it != chunks_.end(); it++)
3610 if (it->width > 0 && it->wire == NULL)
3611 return true;
3612 return false;
3613 }
3614
3615 bool RTLIL::SigSpec::has_marked_bits() const
3616 {
3617 cover("kernel.rtlil.sigspec.has_marked_bits");
3618
3619 pack();
3620 for (auto it = chunks_.begin(); it != chunks_.end(); it++)
3621 if (it->width > 0 && it->wire == NULL) {
3622 for (size_t i = 0; i < it->data.size(); i++)
3623 if (it->data[i] == RTLIL::State::Sm)
3624 return true;
3625 }
3626 return false;
3627 }
3628
3629 bool RTLIL::SigSpec::as_bool() const
3630 {
3631 cover("kernel.rtlil.sigspec.as_bool");
3632
3633 pack();
3634 log_assert(is_fully_const() && GetSize(chunks_) <= 1);
3635 if (width_)
3636 return RTLIL::Const(chunks_[0].data).as_bool();
3637 return false;
3638 }
3639
3640 int RTLIL::SigSpec::as_int(bool is_signed) const
3641 {
3642 cover("kernel.rtlil.sigspec.as_int");
3643
3644 pack();
3645 log_assert(is_fully_const() && GetSize(chunks_) <= 1);
3646 if (width_)
3647 return RTLIL::Const(chunks_[0].data).as_int(is_signed);
3648 return 0;
3649 }
3650
3651 std::string RTLIL::SigSpec::as_string() const
3652 {
3653 cover("kernel.rtlil.sigspec.as_string");
3654
3655 pack();
3656 std::string str;
3657 for (size_t i = chunks_.size(); i > 0; i--) {
3658 const RTLIL::SigChunk &chunk = chunks_[i-1];
3659 if (chunk.wire != NULL)
3660 for (int j = 0; j < chunk.width; j++)
3661 str += "?";
3662 else
3663 str += RTLIL::Const(chunk.data).as_string();
3664 }
3665 return str;
3666 }
3667
3668 RTLIL::Const RTLIL::SigSpec::as_const() const
3669 {
3670 cover("kernel.rtlil.sigspec.as_const");
3671
3672 pack();
3673 log_assert(is_fully_const() && GetSize(chunks_) <= 1);
3674 if (width_)
3675 return chunks_[0].data;
3676 return RTLIL::Const();
3677 }
3678
3679 RTLIL::Wire *RTLIL::SigSpec::as_wire() const
3680 {
3681 cover("kernel.rtlil.sigspec.as_wire");
3682
3683 pack();
3684 log_assert(is_wire());
3685 return chunks_[0].wire;
3686 }
3687
3688 RTLIL::SigChunk RTLIL::SigSpec::as_chunk() const
3689 {
3690 cover("kernel.rtlil.sigspec.as_chunk");
3691
3692 pack();
3693 log_assert(is_chunk());
3694 return chunks_[0];
3695 }
3696
3697 RTLIL::SigBit RTLIL::SigSpec::as_bit() const
3698 {
3699 cover("kernel.rtlil.sigspec.as_bit");
3700
3701 log_assert(width_ == 1);
3702 if (packed())
3703 return RTLIL::SigBit(*chunks_.begin());
3704 else
3705 return bits_[0];
3706 }
3707
3708 bool RTLIL::SigSpec::match(std::string pattern) const
3709 {
3710 cover("kernel.rtlil.sigspec.match");
3711
3712 pack();
3713 std::string str = as_string();
3714 log_assert(pattern.size() == str.size());
3715
3716 for (size_t i = 0; i < pattern.size(); i++) {
3717 if (pattern[i] == ' ')
3718 continue;
3719 if (pattern[i] == '*') {
3720 if (str[i] != 'z' && str[i] != 'x')
3721 return false;
3722 continue;
3723 }
3724 if (pattern[i] != str[i])
3725 return false;
3726 }
3727
3728 return true;
3729 }
3730
3731 std::set<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_set() const
3732 {
3733 cover("kernel.rtlil.sigspec.to_sigbit_set");
3734
3735 pack();
3736 std::set<RTLIL::SigBit> sigbits;
3737 for (auto &c : chunks_)
3738 for (int i = 0; i < c.width; i++)
3739 sigbits.insert(RTLIL::SigBit(c, i));
3740 return sigbits;
3741 }
3742
3743 pool<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_pool() const
3744 {
3745 cover("kernel.rtlil.sigspec.to_sigbit_pool");
3746
3747 pack();
3748 pool<RTLIL::SigBit> sigbits;
3749 for (auto &c : chunks_)
3750 for (int i = 0; i < c.width; i++)
3751 sigbits.insert(RTLIL::SigBit(c, i));
3752 return sigbits;
3753 }
3754
3755 std::vector<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_vector() const
3756 {
3757 cover("kernel.rtlil.sigspec.to_sigbit_vector");
3758
3759 unpack();
3760 return bits_;
3761 }
3762
3763 std::map<RTLIL::SigBit, RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_map(const RTLIL::SigSpec &other) const
3764 {
3765 cover("kernel.rtlil.sigspec.to_sigbit_map");
3766
3767 unpack();
3768 other.unpack();
3769
3770 log_assert(width_ == other.width_);
3771
3772 std::map<RTLIL::SigBit, RTLIL::SigBit> new_map;
3773 for (int i = 0; i < width_; i++)
3774 new_map[bits_[i]] = other.bits_[i];
3775
3776 return new_map;
3777 }
3778
3779 dict<RTLIL::SigBit, RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_dict(const RTLIL::SigSpec &other) const
3780 {
3781 cover("kernel.rtlil.sigspec.to_sigbit_dict");
3782
3783 unpack();
3784 other.unpack();
3785
3786 log_assert(width_ == other.width_);
3787
3788 dict<RTLIL::SigBit, RTLIL::SigBit> new_map;
3789 for (int i = 0; i < width_; i++)
3790 new_map[bits_[i]] = other.bits_[i];
3791
3792 return new_map;
3793 }
3794
3795 static void sigspec_parse_split(std::vector<std::string> &tokens, const std::string &text, char sep)
3796 {
3797 size_t start = 0, end = 0;
3798 while ((end = text.find(sep, start)) != std::string::npos) {
3799 tokens.push_back(text.substr(start, end - start));
3800 start = end + 1;
3801 }
3802 tokens.push_back(text.substr(start));
3803 }
3804
3805 static int sigspec_parse_get_dummy_line_num()
3806 {
3807 return 0;
3808 }
3809
3810 bool RTLIL::SigSpec::parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str)
3811 {
3812 cover("kernel.rtlil.sigspec.parse");
3813
3814 AST::current_filename = "input";
3815 AST::use_internal_line_num();
3816 AST::set_line_num(0);
3817
3818 std::vector<std::string> tokens;
3819 sigspec_parse_split(tokens, str, ',');
3820
3821 sig = RTLIL::SigSpec();
3822 for (int tokidx = int(tokens.size())-1; tokidx >= 0; tokidx--)
3823 {
3824 std::string netname = tokens[tokidx];
3825 std::string indices;
3826
3827 if (netname.size() == 0)
3828 continue;
3829
3830 if (('0' <= netname[0] && netname[0] <= '9') || netname[0] == '\'') {
3831 cover("kernel.rtlil.sigspec.parse.const");
3832 AST::get_line_num = sigspec_parse_get_dummy_line_num;
3833 AST::AstNode *ast = VERILOG_FRONTEND::const2ast(netname);
3834 if (ast == NULL)
3835 return false;
3836 sig.append(RTLIL::Const(ast->bits));
3837 delete ast;
3838 continue;
3839 }
3840
3841 if (module == NULL)
3842 return false;
3843
3844 cover("kernel.rtlil.sigspec.parse.net");
3845
3846 if (netname[0] != '$' && netname[0] != '\\')
3847 netname = "\\" + netname;
3848
3849 if (module->wires_.count(netname) == 0) {
3850 size_t indices_pos = netname.size()-1;
3851 if (indices_pos > 2 && netname[indices_pos] == ']')
3852 {
3853 indices_pos--;
3854 while (indices_pos > 0 && ('0' <= netname[indices_pos] && netname[indices_pos] <= '9')) indices_pos--;
3855 if (indices_pos > 0 && netname[indices_pos] == ':') {
3856 indices_pos--;
3857 while (indices_pos > 0 && ('0' <= netname[indices_pos] && netname[indices_pos] <= '9')) indices_pos--;
3858 }
3859 if (indices_pos > 0 && netname[indices_pos] == '[') {
3860 indices = netname.substr(indices_pos);
3861 netname = netname.substr(0, indices_pos);
3862 }
3863 }
3864 }
3865
3866 if (module->wires_.count(netname) == 0)
3867 return false;
3868
3869 RTLIL::Wire *wire = module->wires_.at(netname);
3870 if (!indices.empty()) {
3871 std::vector<std::string> index_tokens;
3872 sigspec_parse_split(index_tokens, indices.substr(1, indices.size()-2), ':');
3873 if (index_tokens.size() == 1) {
3874 cover("kernel.rtlil.sigspec.parse.bit_sel");
3875 int a = atoi(index_tokens.at(0).c_str());
3876 if (a < 0 || a >= wire->width)
3877 return false;
3878 sig.append(RTLIL::SigSpec(wire, a));
3879 } else {
3880 cover("kernel.rtlil.sigspec.parse.part_sel");
3881 int a = atoi(index_tokens.at(0).c_str());
3882 int b = atoi(index_tokens.at(1).c_str());
3883 if (a > b) {
3884 int tmp = a;
3885 a = b, b = tmp;
3886 }
3887 if (a < 0 || a >= wire->width)
3888 return false;
3889 if (b < 0 || b >= wire->width)
3890 return false;
3891 sig.append(RTLIL::SigSpec(wire, a, b-a+1));
3892 }
3893 } else
3894 sig.append(wire);
3895 }
3896
3897 return true;
3898 }
3899
3900 bool RTLIL::SigSpec::parse_sel(RTLIL::SigSpec &sig, RTLIL::Design *design, RTLIL::Module *module, std::string str)
3901 {
3902 if (str.empty() || str[0] != '@')
3903 return parse(sig, module, str);
3904
3905 cover("kernel.rtlil.sigspec.parse.sel");
3906
3907 str = RTLIL::escape_id(str.substr(1));
3908 if (design->selection_vars.count(str) == 0)
3909 return false;
3910
3911 sig = RTLIL::SigSpec();
3912 RTLIL::Selection &sel = design->selection_vars.at(str);
3913 for (auto &it : module->wires_)
3914 if (sel.selected_member(module->name, it.first))
3915 sig.append(it.second);
3916
3917 return true;
3918 }
3919
3920 bool RTLIL::SigSpec::parse_rhs(const RTLIL::SigSpec &lhs, RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str)
3921 {
3922 if (str == "0") {
3923 cover("kernel.rtlil.sigspec.parse.rhs_zeros");
3924 sig = RTLIL::SigSpec(RTLIL::State::S0, lhs.width_);
3925 return true;
3926 }
3927
3928 if (str == "~0") {
3929 cover("kernel.rtlil.sigspec.parse.rhs_ones");
3930 sig = RTLIL::SigSpec(RTLIL::State::S1, lhs.width_);
3931 return true;
3932 }
3933
3934 if (lhs.chunks_.size() == 1) {
3935 char *p = (char*)str.c_str(), *endptr;
3936 long int val = strtol(p, &endptr, 10);
3937 if (endptr && endptr != p && *endptr == 0) {
3938 sig = RTLIL::SigSpec(val, lhs.width_);
3939 cover("kernel.rtlil.sigspec.parse.rhs_dec");
3940 return true;
3941 }
3942 }
3943
3944 return parse(sig, module, str);
3945 }
3946
3947 RTLIL::CaseRule::~CaseRule()
3948 {
3949 for (auto it = switches.begin(); it != switches.end(); it++)
3950 delete *it;
3951 }
3952
3953 bool RTLIL::CaseRule::empty() const
3954 {
3955 return actions.empty() && switches.empty();
3956 }
3957
3958 RTLIL::CaseRule *RTLIL::CaseRule::clone() const
3959 {
3960 RTLIL::CaseRule *new_caserule = new RTLIL::CaseRule;
3961 new_caserule->compare = compare;
3962 new_caserule->actions = actions;
3963 for (auto &it : switches)
3964 new_caserule->switches.push_back(it->clone());
3965 return new_caserule;
3966 }
3967
3968 RTLIL::SwitchRule::~SwitchRule()
3969 {
3970 for (auto it = cases.begin(); it != cases.end(); it++)
3971 delete *it;
3972 }
3973
3974 bool RTLIL::SwitchRule::empty() const
3975 {
3976 return cases.empty();
3977 }
3978
3979 RTLIL::SwitchRule *RTLIL::SwitchRule::clone() const
3980 {
3981 RTLIL::SwitchRule *new_switchrule = new RTLIL::SwitchRule;
3982 new_switchrule->signal = signal;
3983 new_switchrule->attributes = attributes;
3984 for (auto &it : cases)
3985 new_switchrule->cases.push_back(it->clone());
3986 return new_switchrule;
3987
3988 }
3989
3990 RTLIL::SyncRule *RTLIL::SyncRule::clone() const
3991 {
3992 RTLIL::SyncRule *new_syncrule = new RTLIL::SyncRule;
3993 new_syncrule->type = type;
3994 new_syncrule->signal = signal;
3995 new_syncrule->actions = actions;
3996 return new_syncrule;
3997 }
3998
3999 RTLIL::Process::~Process()
4000 {
4001 for (auto it = syncs.begin(); it != syncs.end(); it++)
4002 delete *it;
4003 }
4004
4005 RTLIL::Process *RTLIL::Process::clone() const
4006 {
4007 RTLIL::Process *new_proc = new RTLIL::Process;
4008
4009 new_proc->name = name;
4010 new_proc->attributes = attributes;
4011
4012 RTLIL::CaseRule *rc_ptr = root_case.clone();
4013 new_proc->root_case = *rc_ptr;
4014 rc_ptr->switches.clear();
4015 delete rc_ptr;
4016
4017 for (auto &it : syncs)
4018 new_proc->syncs.push_back(it->clone());
4019
4020 return new_proc;
4021 }
4022
4023 #ifdef WITH_PYTHON
4024 RTLIL::Memory::~Memory()
4025 {
4026 RTLIL::Memory::get_all_memorys()->erase(hashidx_);
4027 }
4028 static std::map<unsigned int, RTLIL::Memory*> all_memorys;
4029 std::map<unsigned int, RTLIL::Memory*> *RTLIL::Memory::get_all_memorys(void)
4030 {
4031 return &all_memorys;
4032 }
4033 #endif
4034 YOSYS_NAMESPACE_END