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Merge pull request #946 from YosysHQ/clifford/specify
[yosys.git] / kernel / rtlil.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 #include "kernel/yosys.h"
21 #include "kernel/macc.h"
22 #include "kernel/celltypes.h"
23 #include "frontends/verilog/verilog_frontend.h"
24 #include "backends/ilang/ilang_backend.h"
25
26 #include <string.h>
27 #include <algorithm>
28
29 YOSYS_NAMESPACE_BEGIN
30
31 RTLIL::IdString::destruct_guard_t RTLIL::IdString::destruct_guard;
32 std::vector<int> RTLIL::IdString::global_refcount_storage_;
33 std::vector<char*> RTLIL::IdString::global_id_storage_;
34 dict<char*, int, hash_cstr_ops> RTLIL::IdString::global_id_index_;
35 std::vector<int> RTLIL::IdString::global_free_idx_list_;
36 int RTLIL::IdString::last_created_idx_[8];
37 int RTLIL::IdString::last_created_idx_ptr_;
38
39 RTLIL::Const::Const()
40 {
41 flags = RTLIL::CONST_FLAG_NONE;
42 }
43
44 RTLIL::Const::Const(std::string str)
45 {
46 flags = RTLIL::CONST_FLAG_STRING;
47 for (int i = str.size()-1; i >= 0; i--) {
48 unsigned char ch = str[i];
49 for (int j = 0; j < 8; j++) {
50 bits.push_back((ch & 1) != 0 ? RTLIL::S1 : RTLIL::S0);
51 ch = ch >> 1;
52 }
53 }
54 }
55
56 RTLIL::Const::Const(int val, int width)
57 {
58 flags = RTLIL::CONST_FLAG_NONE;
59 for (int i = 0; i < width; i++) {
60 bits.push_back((val & 1) != 0 ? RTLIL::S1 : RTLIL::S0);
61 val = val >> 1;
62 }
63 }
64
65 RTLIL::Const::Const(RTLIL::State bit, int width)
66 {
67 flags = RTLIL::CONST_FLAG_NONE;
68 for (int i = 0; i < width; i++)
69 bits.push_back(bit);
70 }
71
72 RTLIL::Const::Const(const std::vector<bool> &bits)
73 {
74 flags = RTLIL::CONST_FLAG_NONE;
75 for (auto b : bits)
76 this->bits.push_back(b ? RTLIL::S1 : RTLIL::S0);
77 }
78
79 RTLIL::Const::Const(const RTLIL::Const &c)
80 {
81 flags = c.flags;
82 for (auto b : c.bits)
83 this->bits.push_back(b);
84 }
85
86 bool RTLIL::Const::operator <(const RTLIL::Const &other) const
87 {
88 if (bits.size() != other.bits.size())
89 return bits.size() < other.bits.size();
90 for (size_t i = 0; i < bits.size(); i++)
91 if (bits[i] != other.bits[i])
92 return bits[i] < other.bits[i];
93 return false;
94 }
95
96 bool RTLIL::Const::operator ==(const RTLIL::Const &other) const
97 {
98 return bits == other.bits;
99 }
100
101 bool RTLIL::Const::operator !=(const RTLIL::Const &other) const
102 {
103 return bits != other.bits;
104 }
105
106 bool RTLIL::Const::as_bool() const
107 {
108 for (size_t i = 0; i < bits.size(); i++)
109 if (bits[i] == RTLIL::S1)
110 return true;
111 return false;
112 }
113
114 int RTLIL::Const::as_int(bool is_signed) const
115 {
116 int32_t ret = 0;
117 for (size_t i = 0; i < bits.size() && i < 32; i++)
118 if (bits[i] == RTLIL::S1)
119 ret |= 1 << i;
120 if (is_signed && bits.back() == RTLIL::S1)
121 for (size_t i = bits.size(); i < 32; i++)
122 ret |= 1 << i;
123 return ret;
124 }
125
126 std::string RTLIL::Const::as_string() const
127 {
128 std::string ret;
129 for (size_t i = bits.size(); i > 0; i--)
130 switch (bits[i-1]) {
131 case S0: ret += "0"; break;
132 case S1: ret += "1"; break;
133 case Sx: ret += "x"; break;
134 case Sz: ret += "z"; break;
135 case Sa: ret += "-"; break;
136 case Sm: ret += "m"; break;
137 }
138 return ret;
139 }
140
141 RTLIL::Const RTLIL::Const::from_string(std::string str)
142 {
143 Const c;
144 for (auto it = str.rbegin(); it != str.rend(); it++)
145 switch (*it) {
146 case '0': c.bits.push_back(State::S0); break;
147 case '1': c.bits.push_back(State::S1); break;
148 case 'x': c.bits.push_back(State::Sx); break;
149 case 'z': c.bits.push_back(State::Sz); break;
150 case 'm': c.bits.push_back(State::Sm); break;
151 default: c.bits.push_back(State::Sa);
152 }
153 return c;
154 }
155
156 std::string RTLIL::Const::decode_string() const
157 {
158 std::string string;
159 std::vector<char> string_chars;
160 for (int i = 0; i < int (bits.size()); i += 8) {
161 char ch = 0;
162 for (int j = 0; j < 8 && i + j < int (bits.size()); j++)
163 if (bits[i + j] == RTLIL::State::S1)
164 ch |= 1 << j;
165 if (ch != 0)
166 string_chars.push_back(ch);
167 }
168 for (int i = int (string_chars.size()) - 1; i >= 0; i--)
169 string += string_chars[i];
170 return string;
171 }
172
173 bool RTLIL::Const::is_fully_zero() const
174 {
175 cover("kernel.rtlil.const.is_fully_zero");
176
177 for (auto bit : bits)
178 if (bit != RTLIL::State::S0)
179 return false;
180
181 return true;
182 }
183
184 bool RTLIL::Const::is_fully_ones() const
185 {
186 cover("kernel.rtlil.const.is_fully_ones");
187
188 for (auto bit : bits)
189 if (bit != RTLIL::State::S1)
190 return false;
191
192 return true;
193 }
194
195 bool RTLIL::Const::is_fully_def() const
196 {
197 cover("kernel.rtlil.const.is_fully_def");
198
199 for (auto bit : bits)
200 if (bit != RTLIL::State::S0 && bit != RTLIL::State::S1)
201 return false;
202
203 return true;
204 }
205
206 bool RTLIL::Const::is_fully_undef() const
207 {
208 cover("kernel.rtlil.const.is_fully_undef");
209
210 for (auto bit : bits)
211 if (bit != RTLIL::State::Sx && bit != RTLIL::State::Sz)
212 return false;
213
214 return true;
215 }
216
217 void RTLIL::AttrObject::set_bool_attribute(RTLIL::IdString id, bool value)
218 {
219 if (value)
220 attributes[id] = RTLIL::Const(1);
221 else if (attributes.count(id))
222 attributes.erase(id);
223 }
224
225 bool RTLIL::AttrObject::get_bool_attribute(RTLIL::IdString id) const
226 {
227 if (attributes.count(id) == 0)
228 return false;
229 return attributes.at(id).as_bool();
230 }
231
232 void RTLIL::AttrObject::set_strpool_attribute(RTLIL::IdString id, const pool<string> &data)
233 {
234 string attrval;
235 for (auto &s : data) {
236 if (!attrval.empty())
237 attrval += "|";
238 attrval += s;
239 }
240 attributes[id] = RTLIL::Const(attrval);
241 }
242
243 void RTLIL::AttrObject::add_strpool_attribute(RTLIL::IdString id, const pool<string> &data)
244 {
245 pool<string> union_data = get_strpool_attribute(id);
246 union_data.insert(data.begin(), data.end());
247 if (!union_data.empty())
248 set_strpool_attribute(id, union_data);
249 }
250
251 pool<string> RTLIL::AttrObject::get_strpool_attribute(RTLIL::IdString id) const
252 {
253 pool<string> data;
254 if (attributes.count(id) != 0)
255 for (auto s : split_tokens(attributes.at(id).decode_string(), "|"))
256 data.insert(s);
257 return data;
258 }
259
260 void RTLIL::AttrObject::set_src_attribute(const std::string &src)
261 {
262 if (src.empty())
263 attributes.erase("\\src");
264 else
265 attributes["\\src"] = src;
266 }
267
268 std::string RTLIL::AttrObject::get_src_attribute() const
269 {
270 std::string src;
271 if (attributes.count("\\src"))
272 src = attributes.at("\\src").decode_string();
273 return src;
274 }
275
276 bool RTLIL::Selection::selected_module(RTLIL::IdString mod_name) const
277 {
278 if (full_selection)
279 return true;
280 if (selected_modules.count(mod_name) > 0)
281 return true;
282 if (selected_members.count(mod_name) > 0)
283 return true;
284 return false;
285 }
286
287 bool RTLIL::Selection::selected_whole_module(RTLIL::IdString mod_name) const
288 {
289 if (full_selection)
290 return true;
291 if (selected_modules.count(mod_name) > 0)
292 return true;
293 return false;
294 }
295
296 bool RTLIL::Selection::selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const
297 {
298 if (full_selection)
299 return true;
300 if (selected_modules.count(mod_name) > 0)
301 return true;
302 if (selected_members.count(mod_name) > 0)
303 if (selected_members.at(mod_name).count(memb_name) > 0)
304 return true;
305 return false;
306 }
307
308 void RTLIL::Selection::optimize(RTLIL::Design *design)
309 {
310 if (full_selection) {
311 selected_modules.clear();
312 selected_members.clear();
313 return;
314 }
315
316 std::vector<RTLIL::IdString> del_list, add_list;
317
318 del_list.clear();
319 for (auto mod_name : selected_modules) {
320 if (design->modules_.count(mod_name) == 0)
321 del_list.push_back(mod_name);
322 selected_members.erase(mod_name);
323 }
324 for (auto mod_name : del_list)
325 selected_modules.erase(mod_name);
326
327 del_list.clear();
328 for (auto &it : selected_members)
329 if (design->modules_.count(it.first) == 0)
330 del_list.push_back(it.first);
331 for (auto mod_name : del_list)
332 selected_members.erase(mod_name);
333
334 for (auto &it : selected_members) {
335 del_list.clear();
336 for (auto memb_name : it.second)
337 if (design->modules_[it.first]->count_id(memb_name) == 0)
338 del_list.push_back(memb_name);
339 for (auto memb_name : del_list)
340 it.second.erase(memb_name);
341 }
342
343 del_list.clear();
344 add_list.clear();
345 for (auto &it : selected_members)
346 if (it.second.size() == 0)
347 del_list.push_back(it.first);
348 else if (it.second.size() == design->modules_[it.first]->wires_.size() + design->modules_[it.first]->memories.size() +
349 design->modules_[it.first]->cells_.size() + design->modules_[it.first]->processes.size())
350 add_list.push_back(it.first);
351 for (auto mod_name : del_list)
352 selected_members.erase(mod_name);
353 for (auto mod_name : add_list) {
354 selected_members.erase(mod_name);
355 selected_modules.insert(mod_name);
356 }
357
358 if (selected_modules.size() == design->modules_.size()) {
359 full_selection = true;
360 selected_modules.clear();
361 selected_members.clear();
362 }
363 }
364
365 RTLIL::Design::Design()
366 {
367 static unsigned int hashidx_count = 123456789;
368 hashidx_count = mkhash_xorshift(hashidx_count);
369 hashidx_ = hashidx_count;
370
371 refcount_modules_ = 0;
372 selection_stack.push_back(RTLIL::Selection());
373
374 #ifdef WITH_PYTHON
375 RTLIL::Design::get_all_designs()->insert(std::pair<unsigned int, RTLIL::Design*>(hashidx_, this));
376 #endif
377 }
378
379 RTLIL::Design::~Design()
380 {
381 for (auto it = modules_.begin(); it != modules_.end(); ++it)
382 delete it->second;
383 for (auto n : verilog_packages)
384 delete n;
385 for (auto n : verilog_globals)
386 delete n;
387 #ifdef WITH_PYTHON
388 RTLIL::Design::get_all_designs()->erase(hashidx_);
389 #endif
390 }
391
392 #ifdef WITH_PYTHON
393 static std::map<unsigned int, RTLIL::Design*> all_designs;
394 std::map<unsigned int, RTLIL::Design*> *RTLIL::Design::get_all_designs(void)
395 {
396 return &all_designs;
397 }
398 #endif
399
400 RTLIL::ObjRange<RTLIL::Module*> RTLIL::Design::modules()
401 {
402 return RTLIL::ObjRange<RTLIL::Module*>(&modules_, &refcount_modules_);
403 }
404
405 RTLIL::Module *RTLIL::Design::module(RTLIL::IdString name)
406 {
407 return modules_.count(name) ? modules_.at(name) : NULL;
408 }
409
410 RTLIL::Module *RTLIL::Design::top_module()
411 {
412 RTLIL::Module *module = nullptr;
413 int module_count = 0;
414
415 for (auto mod : selected_modules()) {
416 if (mod->get_bool_attribute("\\top"))
417 return mod;
418 module_count++;
419 module = mod;
420 }
421
422 return module_count == 1 ? module : nullptr;
423 }
424
425 void RTLIL::Design::add(RTLIL::Module *module)
426 {
427 log_assert(modules_.count(module->name) == 0);
428 log_assert(refcount_modules_ == 0);
429 modules_[module->name] = module;
430 module->design = this;
431
432 for (auto mon : monitors)
433 mon->notify_module_add(module);
434
435 if (yosys_xtrace) {
436 log("#X# New Module: %s\n", log_id(module));
437 log_backtrace("-X- ", yosys_xtrace-1);
438 }
439 }
440
441 RTLIL::Module *RTLIL::Design::addModule(RTLIL::IdString name)
442 {
443 log_assert(modules_.count(name) == 0);
444 log_assert(refcount_modules_ == 0);
445
446 RTLIL::Module *module = new RTLIL::Module;
447 modules_[name] = module;
448 module->design = this;
449 module->name = name;
450
451 for (auto mon : monitors)
452 mon->notify_module_add(module);
453
454 if (yosys_xtrace) {
455 log("#X# New Module: %s\n", log_id(module));
456 log_backtrace("-X- ", yosys_xtrace-1);
457 }
458
459 return module;
460 }
461
462 void RTLIL::Design::scratchpad_unset(std::string varname)
463 {
464 scratchpad.erase(varname);
465 }
466
467 void RTLIL::Design::scratchpad_set_int(std::string varname, int value)
468 {
469 scratchpad[varname] = stringf("%d", value);
470 }
471
472 void RTLIL::Design::scratchpad_set_bool(std::string varname, bool value)
473 {
474 scratchpad[varname] = value ? "true" : "false";
475 }
476
477 void RTLIL::Design::scratchpad_set_string(std::string varname, std::string value)
478 {
479 scratchpad[varname] = value;
480 }
481
482 int RTLIL::Design::scratchpad_get_int(std::string varname, int default_value) const
483 {
484 if (scratchpad.count(varname) == 0)
485 return default_value;
486
487 std::string str = scratchpad.at(varname);
488
489 if (str == "0" || str == "false")
490 return 0;
491
492 if (str == "1" || str == "true")
493 return 1;
494
495 char *endptr = nullptr;
496 long int parsed_value = strtol(str.c_str(), &endptr, 10);
497 return *endptr ? default_value : parsed_value;
498 }
499
500 bool RTLIL::Design::scratchpad_get_bool(std::string varname, bool default_value) const
501 {
502 if (scratchpad.count(varname) == 0)
503 return default_value;
504
505 std::string str = scratchpad.at(varname);
506
507 if (str == "0" || str == "false")
508 return false;
509
510 if (str == "1" || str == "true")
511 return true;
512
513 return default_value;
514 }
515
516 std::string RTLIL::Design::scratchpad_get_string(std::string varname, std::string default_value) const
517 {
518 if (scratchpad.count(varname) == 0)
519 return default_value;
520 return scratchpad.at(varname);
521 }
522
523 void RTLIL::Design::remove(RTLIL::Module *module)
524 {
525 for (auto mon : monitors)
526 mon->notify_module_del(module);
527
528 if (yosys_xtrace) {
529 log("#X# Remove Module: %s\n", log_id(module));
530 log_backtrace("-X- ", yosys_xtrace-1);
531 }
532
533 log_assert(modules_.at(module->name) == module);
534 modules_.erase(module->name);
535 delete module;
536 }
537
538 void RTLIL::Design::rename(RTLIL::Module *module, RTLIL::IdString new_name)
539 {
540 modules_.erase(module->name);
541 module->name = new_name;
542 add(module);
543 }
544
545 void RTLIL::Design::sort()
546 {
547 scratchpad.sort();
548 modules_.sort(sort_by_id_str());
549 for (auto &it : modules_)
550 it.second->sort();
551 }
552
553 void RTLIL::Design::check()
554 {
555 #ifndef NDEBUG
556 for (auto &it : modules_) {
557 log_assert(this == it.second->design);
558 log_assert(it.first == it.second->name);
559 log_assert(!it.first.empty());
560 it.second->check();
561 }
562 #endif
563 }
564
565 void RTLIL::Design::optimize()
566 {
567 for (auto &it : modules_)
568 it.second->optimize();
569 for (auto &it : selection_stack)
570 it.optimize(this);
571 for (auto &it : selection_vars)
572 it.second.optimize(this);
573 }
574
575 bool RTLIL::Design::selected_module(RTLIL::IdString mod_name) const
576 {
577 if (!selected_active_module.empty() && mod_name != selected_active_module)
578 return false;
579 if (selection_stack.size() == 0)
580 return true;
581 return selection_stack.back().selected_module(mod_name);
582 }
583
584 bool RTLIL::Design::selected_whole_module(RTLIL::IdString mod_name) const
585 {
586 if (!selected_active_module.empty() && mod_name != selected_active_module)
587 return false;
588 if (selection_stack.size() == 0)
589 return true;
590 return selection_stack.back().selected_whole_module(mod_name);
591 }
592
593 bool RTLIL::Design::selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const
594 {
595 if (!selected_active_module.empty() && mod_name != selected_active_module)
596 return false;
597 if (selection_stack.size() == 0)
598 return true;
599 return selection_stack.back().selected_member(mod_name, memb_name);
600 }
601
602 bool RTLIL::Design::selected_module(RTLIL::Module *mod) const
603 {
604 return selected_module(mod->name);
605 }
606
607 bool RTLIL::Design::selected_whole_module(RTLIL::Module *mod) const
608 {
609 return selected_whole_module(mod->name);
610 }
611
612 std::vector<RTLIL::Module*> RTLIL::Design::selected_modules() const
613 {
614 std::vector<RTLIL::Module*> result;
615 result.reserve(modules_.size());
616 for (auto &it : modules_)
617 if (selected_module(it.first) && !it.second->get_blackbox_attribute())
618 result.push_back(it.second);
619 return result;
620 }
621
622 std::vector<RTLIL::Module*> RTLIL::Design::selected_whole_modules() const
623 {
624 std::vector<RTLIL::Module*> result;
625 result.reserve(modules_.size());
626 for (auto &it : modules_)
627 if (selected_whole_module(it.first) && !it.second->get_blackbox_attribute())
628 result.push_back(it.second);
629 return result;
630 }
631
632 std::vector<RTLIL::Module*> RTLIL::Design::selected_whole_modules_warn() const
633 {
634 std::vector<RTLIL::Module*> result;
635 result.reserve(modules_.size());
636 for (auto &it : modules_)
637 if (it.second->get_blackbox_attribute())
638 continue;
639 else if (selected_whole_module(it.first))
640 result.push_back(it.second);
641 else if (selected_module(it.first))
642 log_warning("Ignoring partially selected module %s.\n", log_id(it.first));
643 return result;
644 }
645
646 RTLIL::Module::Module()
647 {
648 static unsigned int hashidx_count = 123456789;
649 hashidx_count = mkhash_xorshift(hashidx_count);
650 hashidx_ = hashidx_count;
651
652 design = nullptr;
653 refcount_wires_ = 0;
654 refcount_cells_ = 0;
655
656 #ifdef WITH_PYTHON
657 RTLIL::Module::get_all_modules()->insert(std::pair<unsigned int, RTLIL::Module*>(hashidx_, this));
658 #endif
659 }
660
661 RTLIL::Module::~Module()
662 {
663 for (auto it = wires_.begin(); it != wires_.end(); ++it)
664 delete it->second;
665 for (auto it = memories.begin(); it != memories.end(); ++it)
666 delete it->second;
667 for (auto it = cells_.begin(); it != cells_.end(); ++it)
668 delete it->second;
669 for (auto it = processes.begin(); it != processes.end(); ++it)
670 delete it->second;
671 #ifdef WITH_PYTHON
672 RTLIL::Module::get_all_modules()->erase(hashidx_);
673 #endif
674 }
675
676 #ifdef WITH_PYTHON
677 static std::map<unsigned int, RTLIL::Module*> all_modules;
678 std::map<unsigned int, RTLIL::Module*> *RTLIL::Module::get_all_modules(void)
679 {
680 return &all_modules;
681 }
682 #endif
683
684 void RTLIL::Module::makeblackbox()
685 {
686 pool<RTLIL::Wire*> delwires;
687
688 for (auto it = wires_.begin(); it != wires_.end(); ++it)
689 if (!it->second->port_input && !it->second->port_output)
690 delwires.insert(it->second);
691
692 for (auto it = memories.begin(); it != memories.end(); ++it)
693 delete it->second;
694 memories.clear();
695
696 for (auto it = cells_.begin(); it != cells_.end(); ++it)
697 delete it->second;
698 cells_.clear();
699
700 for (auto it = processes.begin(); it != processes.end(); ++it)
701 delete it->second;
702 processes.clear();
703
704 remove(delwires);
705 set_bool_attribute("\\blackbox");
706 }
707
708 void RTLIL::Module::reprocess_module(RTLIL::Design *, dict<RTLIL::IdString, RTLIL::Module *>)
709 {
710 log_error("Cannot reprocess_module module `%s' !\n", id2cstr(name));
711 }
712
713 RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, dict<RTLIL::IdString, RTLIL::Const>, bool mayfail)
714 {
715 if (mayfail)
716 return RTLIL::IdString();
717 log_error("Module `%s' is used with parameters but is not parametric!\n", id2cstr(name));
718 }
719
720
721 RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, dict<RTLIL::IdString, RTLIL::Const>, dict<RTLIL::IdString, RTLIL::Module*>, dict<RTLIL::IdString, RTLIL::IdString>, bool mayfail)
722 {
723 if (mayfail)
724 return RTLIL::IdString();
725 log_error("Module `%s' is used with parameters but is not parametric!\n", id2cstr(name));
726 }
727
728 size_t RTLIL::Module::count_id(RTLIL::IdString id)
729 {
730 return wires_.count(id) + memories.count(id) + cells_.count(id) + processes.count(id);
731 }
732
733 #ifndef NDEBUG
734 namespace {
735 struct InternalCellChecker
736 {
737 RTLIL::Module *module;
738 RTLIL::Cell *cell;
739 pool<RTLIL::IdString> expected_params, expected_ports;
740
741 InternalCellChecker(RTLIL::Module *module, RTLIL::Cell *cell) : module(module), cell(cell) { }
742
743 void error(int linenr)
744 {
745 std::stringstream buf;
746 ILANG_BACKEND::dump_cell(buf, " ", cell);
747
748 log_error("Found error in internal cell %s%s%s (%s) at %s:%d:\n%s",
749 module ? module->name.c_str() : "", module ? "." : "",
750 cell->name.c_str(), cell->type.c_str(), __FILE__, linenr, buf.str().c_str());
751 }
752
753 int param(const char *name)
754 {
755 if (cell->parameters.count(name) == 0)
756 error(__LINE__);
757 expected_params.insert(name);
758 return cell->parameters.at(name).as_int();
759 }
760
761 int param_bool(const char *name)
762 {
763 int v = param(name);
764 if (cell->parameters.at(name).bits.size() > 32)
765 error(__LINE__);
766 if (v != 0 && v != 1)
767 error(__LINE__);
768 return v;
769 }
770
771 void param_bits(const char *name, int width)
772 {
773 param(name);
774 if (int(cell->parameters.at(name).bits.size()) != width)
775 error(__LINE__);
776 }
777
778 void port(const char *name, int width)
779 {
780 if (!cell->hasPort(name))
781 error(__LINE__);
782 if (cell->getPort(name).size() != width)
783 error(__LINE__);
784 expected_ports.insert(name);
785 }
786
787 void check_expected(bool check_matched_sign = true)
788 {
789 for (auto &para : cell->parameters)
790 if (expected_params.count(para.first) == 0)
791 error(__LINE__);
792 for (auto &conn : cell->connections())
793 if (expected_ports.count(conn.first) == 0)
794 error(__LINE__);
795
796 if (expected_params.count("\\A_SIGNED") != 0 && expected_params.count("\\B_SIGNED") && check_matched_sign) {
797 bool a_is_signed = param("\\A_SIGNED") != 0;
798 bool b_is_signed = param("\\B_SIGNED") != 0;
799 if (a_is_signed != b_is_signed)
800 error(__LINE__);
801 }
802 }
803
804 void check_gate(const char *ports)
805 {
806 if (cell->parameters.size() != 0)
807 error(__LINE__);
808
809 for (const char *p = ports; *p; p++) {
810 char portname[3] = { '\\', *p, 0 };
811 if (!cell->hasPort(portname))
812 error(__LINE__);
813 if (cell->getPort(portname).size() != 1)
814 error(__LINE__);
815 }
816
817 for (auto &conn : cell->connections()) {
818 if (conn.first.size() != 2 || conn.first[0] != '\\')
819 error(__LINE__);
820 if (strchr(ports, conn.first[1]) == NULL)
821 error(__LINE__);
822 }
823 }
824
825 void check()
826 {
827 if (cell->type.substr(0, 1) != "$" || cell->type.substr(0, 3) == "$__" || cell->type.substr(0, 8) == "$paramod" || cell->type.substr(0,10) == "$fmcombine" ||
828 cell->type.substr(0, 9) == "$verific$" || cell->type.substr(0, 7) == "$array:" || cell->type.substr(0, 8) == "$extern:")
829 return;
830
831 if (cell->type.in("$not", "$pos", "$neg")) {
832 param_bool("\\A_SIGNED");
833 port("\\A", param("\\A_WIDTH"));
834 port("\\Y", param("\\Y_WIDTH"));
835 check_expected();
836 return;
837 }
838
839 if (cell->type.in("$and", "$or", "$xor", "$xnor")) {
840 param_bool("\\A_SIGNED");
841 param_bool("\\B_SIGNED");
842 port("\\A", param("\\A_WIDTH"));
843 port("\\B", param("\\B_WIDTH"));
844 port("\\Y", param("\\Y_WIDTH"));
845 check_expected();
846 return;
847 }
848
849 if (cell->type.in("$reduce_and", "$reduce_or", "$reduce_xor", "$reduce_xnor", "$reduce_bool")) {
850 param_bool("\\A_SIGNED");
851 port("\\A", param("\\A_WIDTH"));
852 port("\\Y", param("\\Y_WIDTH"));
853 check_expected();
854 return;
855 }
856
857 if (cell->type.in("$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx")) {
858 param_bool("\\A_SIGNED");
859 param_bool("\\B_SIGNED");
860 port("\\A", param("\\A_WIDTH"));
861 port("\\B", param("\\B_WIDTH"));
862 port("\\Y", param("\\Y_WIDTH"));
863 check_expected(false);
864 return;
865 }
866
867 if (cell->type.in("$lt", "$le", "$eq", "$ne", "$eqx", "$nex", "$ge", "$gt")) {
868 param_bool("\\A_SIGNED");
869 param_bool("\\B_SIGNED");
870 port("\\A", param("\\A_WIDTH"));
871 port("\\B", param("\\B_WIDTH"));
872 port("\\Y", param("\\Y_WIDTH"));
873 check_expected();
874 return;
875 }
876
877 if (cell->type.in("$add", "$sub", "$mul", "$div", "$mod", "$pow")) {
878 param_bool("\\A_SIGNED");
879 param_bool("\\B_SIGNED");
880 port("\\A", param("\\A_WIDTH"));
881 port("\\B", param("\\B_WIDTH"));
882 port("\\Y", param("\\Y_WIDTH"));
883 check_expected(cell->type != "$pow");
884 return;
885 }
886
887 if (cell->type == "$fa") {
888 port("\\A", param("\\WIDTH"));
889 port("\\B", param("\\WIDTH"));
890 port("\\C", param("\\WIDTH"));
891 port("\\X", param("\\WIDTH"));
892 port("\\Y", param("\\WIDTH"));
893 check_expected();
894 return;
895 }
896
897 if (cell->type == "$lcu") {
898 port("\\P", param("\\WIDTH"));
899 port("\\G", param("\\WIDTH"));
900 port("\\CI", 1);
901 port("\\CO", param("\\WIDTH"));
902 check_expected();
903 return;
904 }
905
906 if (cell->type == "$alu") {
907 param_bool("\\A_SIGNED");
908 param_bool("\\B_SIGNED");
909 port("\\A", param("\\A_WIDTH"));
910 port("\\B", param("\\B_WIDTH"));
911 port("\\CI", 1);
912 port("\\BI", 1);
913 port("\\X", param("\\Y_WIDTH"));
914 port("\\Y", param("\\Y_WIDTH"));
915 port("\\CO", param("\\Y_WIDTH"));
916 check_expected();
917 return;
918 }
919
920 if (cell->type == "$macc") {
921 param("\\CONFIG");
922 param("\\CONFIG_WIDTH");
923 port("\\A", param("\\A_WIDTH"));
924 port("\\B", param("\\B_WIDTH"));
925 port("\\Y", param("\\Y_WIDTH"));
926 check_expected();
927 Macc().from_cell(cell);
928 return;
929 }
930
931 if (cell->type == "$logic_not") {
932 param_bool("\\A_SIGNED");
933 port("\\A", param("\\A_WIDTH"));
934 port("\\Y", param("\\Y_WIDTH"));
935 check_expected();
936 return;
937 }
938
939 if (cell->type == "$logic_and" || cell->type == "$logic_or") {
940 param_bool("\\A_SIGNED");
941 param_bool("\\B_SIGNED");
942 port("\\A", param("\\A_WIDTH"));
943 port("\\B", param("\\B_WIDTH"));
944 port("\\Y", param("\\Y_WIDTH"));
945 check_expected(false);
946 return;
947 }
948
949 if (cell->type == "$slice") {
950 param("\\OFFSET");
951 port("\\A", param("\\A_WIDTH"));
952 port("\\Y", param("\\Y_WIDTH"));
953 if (param("\\OFFSET") + param("\\Y_WIDTH") > param("\\A_WIDTH"))
954 error(__LINE__);
955 check_expected();
956 return;
957 }
958
959 if (cell->type == "$concat") {
960 port("\\A", param("\\A_WIDTH"));
961 port("\\B", param("\\B_WIDTH"));
962 port("\\Y", param("\\A_WIDTH") + param("\\B_WIDTH"));
963 check_expected();
964 return;
965 }
966
967 if (cell->type == "$mux") {
968 port("\\A", param("\\WIDTH"));
969 port("\\B", param("\\WIDTH"));
970 port("\\S", 1);
971 port("\\Y", param("\\WIDTH"));
972 check_expected();
973 return;
974 }
975
976 if (cell->type == "$pmux") {
977 port("\\A", param("\\WIDTH"));
978 port("\\B", param("\\WIDTH") * param("\\S_WIDTH"));
979 port("\\S", param("\\S_WIDTH"));
980 port("\\Y", param("\\WIDTH"));
981 check_expected();
982 return;
983 }
984
985 if (cell->type == "$lut") {
986 param("\\LUT");
987 port("\\A", param("\\WIDTH"));
988 port("\\Y", 1);
989 check_expected();
990 return;
991 }
992
993 if (cell->type == "$sop") {
994 param("\\DEPTH");
995 param("\\TABLE");
996 port("\\A", param("\\WIDTH"));
997 port("\\Y", 1);
998 check_expected();
999 return;
1000 }
1001
1002 if (cell->type == "$sr") {
1003 param_bool("\\SET_POLARITY");
1004 param_bool("\\CLR_POLARITY");
1005 port("\\SET", param("\\WIDTH"));
1006 port("\\CLR", param("\\WIDTH"));
1007 port("\\Q", param("\\WIDTH"));
1008 check_expected();
1009 return;
1010 }
1011
1012 if (cell->type == "$ff") {
1013 port("\\D", param("\\WIDTH"));
1014 port("\\Q", param("\\WIDTH"));
1015 check_expected();
1016 return;
1017 }
1018
1019 if (cell->type == "$dff") {
1020 param_bool("\\CLK_POLARITY");
1021 port("\\CLK", 1);
1022 port("\\D", param("\\WIDTH"));
1023 port("\\Q", param("\\WIDTH"));
1024 check_expected();
1025 return;
1026 }
1027
1028 if (cell->type == "$dffe") {
1029 param_bool("\\CLK_POLARITY");
1030 param_bool("\\EN_POLARITY");
1031 port("\\CLK", 1);
1032 port("\\EN", 1);
1033 port("\\D", param("\\WIDTH"));
1034 port("\\Q", param("\\WIDTH"));
1035 check_expected();
1036 return;
1037 }
1038
1039 if (cell->type == "$dffsr") {
1040 param_bool("\\CLK_POLARITY");
1041 param_bool("\\SET_POLARITY");
1042 param_bool("\\CLR_POLARITY");
1043 port("\\CLK", 1);
1044 port("\\SET", param("\\WIDTH"));
1045 port("\\CLR", param("\\WIDTH"));
1046 port("\\D", param("\\WIDTH"));
1047 port("\\Q", param("\\WIDTH"));
1048 check_expected();
1049 return;
1050 }
1051
1052 if (cell->type == "$adff") {
1053 param_bool("\\CLK_POLARITY");
1054 param_bool("\\ARST_POLARITY");
1055 param_bits("\\ARST_VALUE", param("\\WIDTH"));
1056 port("\\CLK", 1);
1057 port("\\ARST", 1);
1058 port("\\D", param("\\WIDTH"));
1059 port("\\Q", param("\\WIDTH"));
1060 check_expected();
1061 return;
1062 }
1063
1064 if (cell->type == "$dlatch") {
1065 param_bool("\\EN_POLARITY");
1066 port("\\EN", 1);
1067 port("\\D", param("\\WIDTH"));
1068 port("\\Q", param("\\WIDTH"));
1069 check_expected();
1070 return;
1071 }
1072
1073 if (cell->type == "$dlatchsr") {
1074 param_bool("\\EN_POLARITY");
1075 param_bool("\\SET_POLARITY");
1076 param_bool("\\CLR_POLARITY");
1077 port("\\EN", 1);
1078 port("\\SET", param("\\WIDTH"));
1079 port("\\CLR", param("\\WIDTH"));
1080 port("\\D", param("\\WIDTH"));
1081 port("\\Q", param("\\WIDTH"));
1082 check_expected();
1083 return;
1084 }
1085
1086 if (cell->type == "$fsm") {
1087 param("\\NAME");
1088 param_bool("\\CLK_POLARITY");
1089 param_bool("\\ARST_POLARITY");
1090 param("\\STATE_BITS");
1091 param("\\STATE_NUM");
1092 param("\\STATE_NUM_LOG2");
1093 param("\\STATE_RST");
1094 param_bits("\\STATE_TABLE", param("\\STATE_BITS") * param("\\STATE_NUM"));
1095 param("\\TRANS_NUM");
1096 param_bits("\\TRANS_TABLE", param("\\TRANS_NUM") * (2*param("\\STATE_NUM_LOG2") + param("\\CTRL_IN_WIDTH") + param("\\CTRL_OUT_WIDTH")));
1097 port("\\CLK", 1);
1098 port("\\ARST", 1);
1099 port("\\CTRL_IN", param("\\CTRL_IN_WIDTH"));
1100 port("\\CTRL_OUT", param("\\CTRL_OUT_WIDTH"));
1101 check_expected();
1102 return;
1103 }
1104
1105 if (cell->type == "$memrd") {
1106 param("\\MEMID");
1107 param_bool("\\CLK_ENABLE");
1108 param_bool("\\CLK_POLARITY");
1109 param_bool("\\TRANSPARENT");
1110 port("\\CLK", 1);
1111 port("\\EN", 1);
1112 port("\\ADDR", param("\\ABITS"));
1113 port("\\DATA", param("\\WIDTH"));
1114 check_expected();
1115 return;
1116 }
1117
1118 if (cell->type == "$memwr") {
1119 param("\\MEMID");
1120 param_bool("\\CLK_ENABLE");
1121 param_bool("\\CLK_POLARITY");
1122 param("\\PRIORITY");
1123 port("\\CLK", 1);
1124 port("\\EN", param("\\WIDTH"));
1125 port("\\ADDR", param("\\ABITS"));
1126 port("\\DATA", param("\\WIDTH"));
1127 check_expected();
1128 return;
1129 }
1130
1131 if (cell->type == "$meminit") {
1132 param("\\MEMID");
1133 param("\\PRIORITY");
1134 port("\\ADDR", param("\\ABITS"));
1135 port("\\DATA", param("\\WIDTH") * param("\\WORDS"));
1136 check_expected();
1137 return;
1138 }
1139
1140 if (cell->type == "$mem") {
1141 param("\\MEMID");
1142 param("\\SIZE");
1143 param("\\OFFSET");
1144 param("\\INIT");
1145 param_bits("\\RD_CLK_ENABLE", max(1, param("\\RD_PORTS")));
1146 param_bits("\\RD_CLK_POLARITY", max(1, param("\\RD_PORTS")));
1147 param_bits("\\RD_TRANSPARENT", max(1, param("\\RD_PORTS")));
1148 param_bits("\\WR_CLK_ENABLE", max(1, param("\\WR_PORTS")));
1149 param_bits("\\WR_CLK_POLARITY", max(1, param("\\WR_PORTS")));
1150 port("\\RD_CLK", param("\\RD_PORTS"));
1151 port("\\RD_EN", param("\\RD_PORTS"));
1152 port("\\RD_ADDR", param("\\RD_PORTS") * param("\\ABITS"));
1153 port("\\RD_DATA", param("\\RD_PORTS") * param("\\WIDTH"));
1154 port("\\WR_CLK", param("\\WR_PORTS"));
1155 port("\\WR_EN", param("\\WR_PORTS") * param("\\WIDTH"));
1156 port("\\WR_ADDR", param("\\WR_PORTS") * param("\\ABITS"));
1157 port("\\WR_DATA", param("\\WR_PORTS") * param("\\WIDTH"));
1158 check_expected();
1159 return;
1160 }
1161
1162 if (cell->type == "$tribuf") {
1163 port("\\A", param("\\WIDTH"));
1164 port("\\Y", param("\\WIDTH"));
1165 port("\\EN", 1);
1166 check_expected();
1167 return;
1168 }
1169
1170 if (cell->type.in("$assert", "$assume", "$live", "$fair", "$cover")) {
1171 port("\\A", 1);
1172 port("\\EN", 1);
1173 check_expected();
1174 return;
1175 }
1176
1177 if (cell->type == "$initstate") {
1178 port("\\Y", 1);
1179 check_expected();
1180 return;
1181 }
1182
1183 if (cell->type.in("$anyconst", "$anyseq", "$allconst", "$allseq")) {
1184 port("\\Y", param("\\WIDTH"));
1185 check_expected();
1186 return;
1187 }
1188
1189 if (cell->type == "$equiv") {
1190 port("\\A", 1);
1191 port("\\B", 1);
1192 port("\\Y", 1);
1193 check_expected();
1194 return;
1195 }
1196
1197 if (cell->type.in("$specify2", "$specify3")) {
1198 param_bool("\\FULL");
1199 param_bool("\\SRC_DST_PEN");
1200 param_bool("\\SRC_DST_POL");
1201 param("\\T_RISE_MIN");
1202 param("\\T_RISE_TYP");
1203 param("\\T_RISE_MAX");
1204 param("\\T_FALL_MIN");
1205 param("\\T_FALL_TYP");
1206 param("\\T_FALL_MAX");
1207 port("\\EN", 1);
1208 port("\\SRC", param("\\SRC_WIDTH"));
1209 port("\\DST", param("\\DST_WIDTH"));
1210 if (cell->type == "$specify3") {
1211 param_bool("\\EDGE_EN");
1212 param_bool("\\EDGE_POL");
1213 param_bool("\\DAT_DST_PEN");
1214 param_bool("\\DAT_DST_POL");
1215 port("\\DAT", param("\\DST_WIDTH"));
1216 }
1217 check_expected();
1218 return;
1219 }
1220
1221 if (cell->type == "$specrule") {
1222 param("\\TYPE");
1223 param_bool("\\SRC_PEN");
1224 param_bool("\\SRC_POL");
1225 param_bool("\\DST_PEN");
1226 param_bool("\\DST_POL");
1227 param("\\T_LIMIT");
1228 param("\\T_LIMIT2");
1229 port("\\SRC_EN", 1);
1230 port("\\DST_EN", 1);
1231 port("\\SRC", param("\\SRC_WIDTH"));
1232 port("\\DST", param("\\DST_WIDTH"));
1233 check_expected();
1234 return;
1235 }
1236
1237 if (cell->type == "$_BUF_") { check_gate("AY"); return; }
1238 if (cell->type == "$_NOT_") { check_gate("AY"); return; }
1239 if (cell->type == "$_AND_") { check_gate("ABY"); return; }
1240 if (cell->type == "$_NAND_") { check_gate("ABY"); return; }
1241 if (cell->type == "$_OR_") { check_gate("ABY"); return; }
1242 if (cell->type == "$_NOR_") { check_gate("ABY"); return; }
1243 if (cell->type == "$_XOR_") { check_gate("ABY"); return; }
1244 if (cell->type == "$_XNOR_") { check_gate("ABY"); return; }
1245 if (cell->type == "$_ANDNOT_") { check_gate("ABY"); return; }
1246 if (cell->type == "$_ORNOT_") { check_gate("ABY"); return; }
1247 if (cell->type == "$_MUX_") { check_gate("ABSY"); return; }
1248 if (cell->type == "$_AOI3_") { check_gate("ABCY"); return; }
1249 if (cell->type == "$_OAI3_") { check_gate("ABCY"); return; }
1250 if (cell->type == "$_AOI4_") { check_gate("ABCDY"); return; }
1251 if (cell->type == "$_OAI4_") { check_gate("ABCDY"); return; }
1252
1253 if (cell->type == "$_TBUF_") { check_gate("AYE"); return; }
1254
1255 if (cell->type == "$_MUX4_") { check_gate("ABCDSTY"); return; }
1256 if (cell->type == "$_MUX8_") { check_gate("ABCDEFGHSTUY"); return; }
1257 if (cell->type == "$_MUX16_") { check_gate("ABCDEFGHIJKLMNOPSTUVY"); return; }
1258
1259 if (cell->type == "$_SR_NN_") { check_gate("SRQ"); return; }
1260 if (cell->type == "$_SR_NP_") { check_gate("SRQ"); return; }
1261 if (cell->type == "$_SR_PN_") { check_gate("SRQ"); return; }
1262 if (cell->type == "$_SR_PP_") { check_gate("SRQ"); return; }
1263
1264 if (cell->type == "$_FF_") { check_gate("DQ"); return; }
1265 if (cell->type == "$_DFF_N_") { check_gate("DQC"); return; }
1266 if (cell->type == "$_DFF_P_") { check_gate("DQC"); return; }
1267
1268 if (cell->type == "$_DFFE_NN_") { check_gate("DQCE"); return; }
1269 if (cell->type == "$_DFFE_NP_") { check_gate("DQCE"); return; }
1270 if (cell->type == "$_DFFE_PN_") { check_gate("DQCE"); return; }
1271 if (cell->type == "$_DFFE_PP_") { check_gate("DQCE"); return; }
1272
1273 if (cell->type == "$_DFF_NN0_") { check_gate("DQCR"); return; }
1274 if (cell->type == "$_DFF_NN1_") { check_gate("DQCR"); return; }
1275 if (cell->type == "$_DFF_NP0_") { check_gate("DQCR"); return; }
1276 if (cell->type == "$_DFF_NP1_") { check_gate("DQCR"); return; }
1277 if (cell->type == "$_DFF_PN0_") { check_gate("DQCR"); return; }
1278 if (cell->type == "$_DFF_PN1_") { check_gate("DQCR"); return; }
1279 if (cell->type == "$_DFF_PP0_") { check_gate("DQCR"); return; }
1280 if (cell->type == "$_DFF_PP1_") { check_gate("DQCR"); return; }
1281
1282 if (cell->type == "$_DFFSR_NNN_") { check_gate("CSRDQ"); return; }
1283 if (cell->type == "$_DFFSR_NNP_") { check_gate("CSRDQ"); return; }
1284 if (cell->type == "$_DFFSR_NPN_") { check_gate("CSRDQ"); return; }
1285 if (cell->type == "$_DFFSR_NPP_") { check_gate("CSRDQ"); return; }
1286 if (cell->type == "$_DFFSR_PNN_") { check_gate("CSRDQ"); return; }
1287 if (cell->type == "$_DFFSR_PNP_") { check_gate("CSRDQ"); return; }
1288 if (cell->type == "$_DFFSR_PPN_") { check_gate("CSRDQ"); return; }
1289 if (cell->type == "$_DFFSR_PPP_") { check_gate("CSRDQ"); return; }
1290
1291 if (cell->type == "$_DLATCH_N_") { check_gate("EDQ"); return; }
1292 if (cell->type == "$_DLATCH_P_") { check_gate("EDQ"); return; }
1293
1294 if (cell->type == "$_DLATCHSR_NNN_") { check_gate("ESRDQ"); return; }
1295 if (cell->type == "$_DLATCHSR_NNP_") { check_gate("ESRDQ"); return; }
1296 if (cell->type == "$_DLATCHSR_NPN_") { check_gate("ESRDQ"); return; }
1297 if (cell->type == "$_DLATCHSR_NPP_") { check_gate("ESRDQ"); return; }
1298 if (cell->type == "$_DLATCHSR_PNN_") { check_gate("ESRDQ"); return; }
1299 if (cell->type == "$_DLATCHSR_PNP_") { check_gate("ESRDQ"); return; }
1300 if (cell->type == "$_DLATCHSR_PPN_") { check_gate("ESRDQ"); return; }
1301 if (cell->type == "$_DLATCHSR_PPP_") { check_gate("ESRDQ"); return; }
1302
1303 error(__LINE__);
1304 }
1305 };
1306 }
1307 #endif
1308
1309 void RTLIL::Module::sort()
1310 {
1311 wires_.sort(sort_by_id_str());
1312 cells_.sort(sort_by_id_str());
1313 avail_parameters.sort(sort_by_id_str());
1314 memories.sort(sort_by_id_str());
1315 processes.sort(sort_by_id_str());
1316 for (auto &it : cells_)
1317 it.second->sort();
1318 for (auto &it : wires_)
1319 it.second->attributes.sort(sort_by_id_str());
1320 for (auto &it : memories)
1321 it.second->attributes.sort(sort_by_id_str());
1322 }
1323
1324 void RTLIL::Module::check()
1325 {
1326 #ifndef NDEBUG
1327 std::vector<bool> ports_declared;
1328 for (auto &it : wires_) {
1329 log_assert(this == it.second->module);
1330 log_assert(it.first == it.second->name);
1331 log_assert(!it.first.empty());
1332 log_assert(it.second->width >= 0);
1333 log_assert(it.second->port_id >= 0);
1334 for (auto &it2 : it.second->attributes)
1335 log_assert(!it2.first.empty());
1336 if (it.second->port_id) {
1337 log_assert(GetSize(ports) >= it.second->port_id);
1338 log_assert(ports.at(it.second->port_id-1) == it.first);
1339 log_assert(it.second->port_input || it.second->port_output);
1340 if (GetSize(ports_declared) < it.second->port_id)
1341 ports_declared.resize(it.second->port_id);
1342 log_assert(ports_declared[it.second->port_id-1] == false);
1343 ports_declared[it.second->port_id-1] = true;
1344 } else
1345 log_assert(!it.second->port_input && !it.second->port_output);
1346 }
1347 for (auto port_declared : ports_declared)
1348 log_assert(port_declared == true);
1349 log_assert(GetSize(ports) == GetSize(ports_declared));
1350
1351 for (auto &it : memories) {
1352 log_assert(it.first == it.second->name);
1353 log_assert(!it.first.empty());
1354 log_assert(it.second->width >= 0);
1355 log_assert(it.second->size >= 0);
1356 for (auto &it2 : it.second->attributes)
1357 log_assert(!it2.first.empty());
1358 }
1359
1360 for (auto &it : cells_) {
1361 log_assert(this == it.second->module);
1362 log_assert(it.first == it.second->name);
1363 log_assert(!it.first.empty());
1364 log_assert(!it.second->type.empty());
1365 for (auto &it2 : it.second->connections()) {
1366 log_assert(!it2.first.empty());
1367 it2.second.check();
1368 }
1369 for (auto &it2 : it.second->attributes)
1370 log_assert(!it2.first.empty());
1371 for (auto &it2 : it.second->parameters)
1372 log_assert(!it2.first.empty());
1373 InternalCellChecker checker(this, it.second);
1374 checker.check();
1375 }
1376
1377 for (auto &it : processes) {
1378 log_assert(it.first == it.second->name);
1379 log_assert(!it.first.empty());
1380 // FIXME: More checks here..
1381 }
1382
1383 for (auto &it : connections_) {
1384 log_assert(it.first.size() == it.second.size());
1385 log_assert(!it.first.has_const());
1386 it.first.check();
1387 it.second.check();
1388 }
1389
1390 for (auto &it : attributes)
1391 log_assert(!it.first.empty());
1392 #endif
1393 }
1394
1395 void RTLIL::Module::optimize()
1396 {
1397 }
1398
1399 void RTLIL::Module::cloneInto(RTLIL::Module *new_mod) const
1400 {
1401 log_assert(new_mod->refcount_wires_ == 0);
1402 log_assert(new_mod->refcount_cells_ == 0);
1403
1404 new_mod->avail_parameters = avail_parameters;
1405
1406 for (auto &conn : connections_)
1407 new_mod->connect(conn);
1408
1409 for (auto &attr : attributes)
1410 new_mod->attributes[attr.first] = attr.second;
1411
1412 for (auto &it : wires_)
1413 new_mod->addWire(it.first, it.second);
1414
1415 for (auto &it : memories)
1416 new_mod->memories[it.first] = new RTLIL::Memory(*it.second);
1417
1418 for (auto &it : cells_)
1419 new_mod->addCell(it.first, it.second);
1420
1421 for (auto &it : processes)
1422 new_mod->processes[it.first] = it.second->clone();
1423
1424 struct RewriteSigSpecWorker
1425 {
1426 RTLIL::Module *mod;
1427 void operator()(RTLIL::SigSpec &sig)
1428 {
1429 std::vector<RTLIL::SigChunk> chunks = sig.chunks();
1430 for (auto &c : chunks)
1431 if (c.wire != NULL)
1432 c.wire = mod->wires_.at(c.wire->name);
1433 sig = chunks;
1434 }
1435 };
1436
1437 RewriteSigSpecWorker rewriteSigSpecWorker;
1438 rewriteSigSpecWorker.mod = new_mod;
1439 new_mod->rewrite_sigspecs(rewriteSigSpecWorker);
1440 new_mod->fixup_ports();
1441 }
1442
1443 RTLIL::Module *RTLIL::Module::clone() const
1444 {
1445 RTLIL::Module *new_mod = new RTLIL::Module;
1446 new_mod->name = name;
1447 cloneInto(new_mod);
1448 return new_mod;
1449 }
1450
1451 bool RTLIL::Module::has_memories() const
1452 {
1453 return !memories.empty();
1454 }
1455
1456 bool RTLIL::Module::has_processes() const
1457 {
1458 return !processes.empty();
1459 }
1460
1461 bool RTLIL::Module::has_memories_warn() const
1462 {
1463 if (!memories.empty())
1464 log_warning("Ignoring module %s because it contains memories (run 'memory' command first).\n", log_id(this));
1465 return !memories.empty();
1466 }
1467
1468 bool RTLIL::Module::has_processes_warn() const
1469 {
1470 if (!processes.empty())
1471 log_warning("Ignoring module %s because it contains processes (run 'proc' command first).\n", log_id(this));
1472 return !processes.empty();
1473 }
1474
1475 std::vector<RTLIL::Wire*> RTLIL::Module::selected_wires() const
1476 {
1477 std::vector<RTLIL::Wire*> result;
1478 result.reserve(wires_.size());
1479 for (auto &it : wires_)
1480 if (design->selected(this, it.second))
1481 result.push_back(it.second);
1482 return result;
1483 }
1484
1485 std::vector<RTLIL::Cell*> RTLIL::Module::selected_cells() const
1486 {
1487 std::vector<RTLIL::Cell*> result;
1488 result.reserve(wires_.size());
1489 for (auto &it : cells_)
1490 if (design->selected(this, it.second))
1491 result.push_back(it.second);
1492 return result;
1493 }
1494
1495 void RTLIL::Module::add(RTLIL::Wire *wire)
1496 {
1497 log_assert(!wire->name.empty());
1498 log_assert(count_id(wire->name) == 0);
1499 log_assert(refcount_wires_ == 0);
1500 wires_[wire->name] = wire;
1501 wire->module = this;
1502 }
1503
1504 void RTLIL::Module::add(RTLIL::Cell *cell)
1505 {
1506 log_assert(!cell->name.empty());
1507 log_assert(count_id(cell->name) == 0);
1508 log_assert(refcount_cells_ == 0);
1509 cells_[cell->name] = cell;
1510 cell->module = this;
1511 }
1512
1513 namespace {
1514 struct DeleteWireWorker
1515 {
1516 RTLIL::Module *module;
1517 const pool<RTLIL::Wire*> *wires_p;
1518
1519 void operator()(RTLIL::SigSpec &sig) {
1520 std::vector<RTLIL::SigChunk> chunks = sig;
1521 for (auto &c : chunks)
1522 if (c.wire != NULL && wires_p->count(c.wire)) {
1523 c.wire = module->addWire(NEW_ID, c.width);
1524 c.offset = 0;
1525 }
1526 sig = chunks;
1527 }
1528 };
1529 }
1530
1531 void RTLIL::Module::remove(const pool<RTLIL::Wire*> &wires)
1532 {
1533 log_assert(refcount_wires_ == 0);
1534
1535 DeleteWireWorker delete_wire_worker;
1536 delete_wire_worker.module = this;
1537 delete_wire_worker.wires_p = &wires;
1538 rewrite_sigspecs(delete_wire_worker);
1539
1540 for (auto &it : wires) {
1541 log_assert(wires_.count(it->name) != 0);
1542 wires_.erase(it->name);
1543 delete it;
1544 }
1545 }
1546
1547 void RTLIL::Module::remove(RTLIL::Cell *cell)
1548 {
1549 while (!cell->connections_.empty())
1550 cell->unsetPort(cell->connections_.begin()->first);
1551
1552 log_assert(cells_.count(cell->name) != 0);
1553 log_assert(refcount_cells_ == 0);
1554 cells_.erase(cell->name);
1555 delete cell;
1556 }
1557
1558 void RTLIL::Module::rename(RTLIL::Wire *wire, RTLIL::IdString new_name)
1559 {
1560 log_assert(wires_[wire->name] == wire);
1561 log_assert(refcount_wires_ == 0);
1562 wires_.erase(wire->name);
1563 wire->name = new_name;
1564 add(wire);
1565 }
1566
1567 void RTLIL::Module::rename(RTLIL::Cell *cell, RTLIL::IdString new_name)
1568 {
1569 log_assert(cells_[cell->name] == cell);
1570 log_assert(refcount_wires_ == 0);
1571 cells_.erase(cell->name);
1572 cell->name = new_name;
1573 add(cell);
1574 }
1575
1576 void RTLIL::Module::rename(RTLIL::IdString old_name, RTLIL::IdString new_name)
1577 {
1578 log_assert(count_id(old_name) != 0);
1579 if (wires_.count(old_name))
1580 rename(wires_.at(old_name), new_name);
1581 else if (cells_.count(old_name))
1582 rename(cells_.at(old_name), new_name);
1583 else
1584 log_abort();
1585 }
1586
1587 void RTLIL::Module::swap_names(RTLIL::Wire *w1, RTLIL::Wire *w2)
1588 {
1589 log_assert(wires_[w1->name] == w1);
1590 log_assert(wires_[w2->name] == w2);
1591 log_assert(refcount_wires_ == 0);
1592
1593 wires_.erase(w1->name);
1594 wires_.erase(w2->name);
1595
1596 std::swap(w1->name, w2->name);
1597
1598 wires_[w1->name] = w1;
1599 wires_[w2->name] = w2;
1600 }
1601
1602 void RTLIL::Module::swap_names(RTLIL::Cell *c1, RTLIL::Cell *c2)
1603 {
1604 log_assert(cells_[c1->name] == c1);
1605 log_assert(cells_[c2->name] == c2);
1606 log_assert(refcount_cells_ == 0);
1607
1608 cells_.erase(c1->name);
1609 cells_.erase(c2->name);
1610
1611 std::swap(c1->name, c2->name);
1612
1613 cells_[c1->name] = c1;
1614 cells_[c2->name] = c2;
1615 }
1616
1617 RTLIL::IdString RTLIL::Module::uniquify(RTLIL::IdString name)
1618 {
1619 int index = 0;
1620 return uniquify(name, index);
1621 }
1622
1623 RTLIL::IdString RTLIL::Module::uniquify(RTLIL::IdString name, int &index)
1624 {
1625 if (index == 0) {
1626 if (count_id(name) == 0)
1627 return name;
1628 index++;
1629 }
1630
1631 while (1) {
1632 RTLIL::IdString new_name = stringf("%s_%d", name.c_str(), index);
1633 if (count_id(new_name) == 0)
1634 return new_name;
1635 index++;
1636 }
1637 }
1638
1639 static bool fixup_ports_compare(const RTLIL::Wire *a, const RTLIL::Wire *b)
1640 {
1641 if (a->port_id && !b->port_id)
1642 return true;
1643 if (!a->port_id && b->port_id)
1644 return false;
1645
1646 if (a->port_id == b->port_id)
1647 return a->name < b->name;
1648 return a->port_id < b->port_id;
1649 }
1650
1651 void RTLIL::Module::connect(const RTLIL::SigSig &conn)
1652 {
1653 for (auto mon : monitors)
1654 mon->notify_connect(this, conn);
1655
1656 if (design)
1657 for (auto mon : design->monitors)
1658 mon->notify_connect(this, conn);
1659
1660 // ignore all attempts to assign constants to other constants
1661 if (conn.first.has_const()) {
1662 RTLIL::SigSig new_conn;
1663 for (int i = 0; i < GetSize(conn.first); i++)
1664 if (conn.first[i].wire) {
1665 new_conn.first.append(conn.first[i]);
1666 new_conn.second.append(conn.second[i]);
1667 }
1668 if (GetSize(new_conn.first))
1669 connect(new_conn);
1670 return;
1671 }
1672
1673 if (yosys_xtrace) {
1674 log("#X# Connect (SigSig) in %s: %s = %s (%d bits)\n", log_id(this), log_signal(conn.first), log_signal(conn.second), GetSize(conn.first));
1675 log_backtrace("-X- ", yosys_xtrace-1);
1676 }
1677
1678 log_assert(GetSize(conn.first) == GetSize(conn.second));
1679 connections_.push_back(conn);
1680 }
1681
1682 void RTLIL::Module::connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs)
1683 {
1684 connect(RTLIL::SigSig(lhs, rhs));
1685 }
1686
1687 void RTLIL::Module::new_connections(const std::vector<RTLIL::SigSig> &new_conn)
1688 {
1689 for (auto mon : monitors)
1690 mon->notify_connect(this, new_conn);
1691
1692 if (design)
1693 for (auto mon : design->monitors)
1694 mon->notify_connect(this, new_conn);
1695
1696 if (yosys_xtrace) {
1697 log("#X# New connections vector in %s:\n", log_id(this));
1698 for (auto &conn: new_conn)
1699 log("#X# %s = %s (%d bits)\n", log_signal(conn.first), log_signal(conn.second), GetSize(conn.first));
1700 log_backtrace("-X- ", yosys_xtrace-1);
1701 }
1702
1703 connections_ = new_conn;
1704 }
1705
1706 const std::vector<RTLIL::SigSig> &RTLIL::Module::connections() const
1707 {
1708 return connections_;
1709 }
1710
1711 void RTLIL::Module::fixup_ports()
1712 {
1713 std::vector<RTLIL::Wire*> all_ports;
1714
1715 for (auto &w : wires_)
1716 if (w.second->port_input || w.second->port_output)
1717 all_ports.push_back(w.second);
1718 else
1719 w.second->port_id = 0;
1720
1721 std::sort(all_ports.begin(), all_ports.end(), fixup_ports_compare);
1722
1723 ports.clear();
1724 for (size_t i = 0; i < all_ports.size(); i++) {
1725 ports.push_back(all_ports[i]->name);
1726 all_ports[i]->port_id = i+1;
1727 }
1728 }
1729
1730 RTLIL::Wire *RTLIL::Module::addWire(RTLIL::IdString name, int width)
1731 {
1732 RTLIL::Wire *wire = new RTLIL::Wire;
1733 wire->name = name;
1734 wire->width = width;
1735 add(wire);
1736 return wire;
1737 }
1738
1739 RTLIL::Wire *RTLIL::Module::addWire(RTLIL::IdString name, const RTLIL::Wire *other)
1740 {
1741 RTLIL::Wire *wire = addWire(name);
1742 wire->width = other->width;
1743 wire->start_offset = other->start_offset;
1744 wire->port_id = other->port_id;
1745 wire->port_input = other->port_input;
1746 wire->port_output = other->port_output;
1747 wire->upto = other->upto;
1748 wire->attributes = other->attributes;
1749 return wire;
1750 }
1751
1752 RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, RTLIL::IdString type)
1753 {
1754 RTLIL::Cell *cell = new RTLIL::Cell;
1755 cell->name = name;
1756 cell->type = type;
1757 add(cell);
1758 return cell;
1759 }
1760
1761 RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, const RTLIL::Cell *other)
1762 {
1763 RTLIL::Cell *cell = addCell(name, other->type);
1764 cell->connections_ = other->connections_;
1765 cell->parameters = other->parameters;
1766 cell->attributes = other->attributes;
1767 return cell;
1768 }
1769
1770 #define DEF_METHOD(_func, _y_size, _type) \
1771 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed, const std::string &src) { \
1772 RTLIL::Cell *cell = addCell(name, _type); \
1773 cell->parameters["\\A_SIGNED"] = is_signed; \
1774 cell->parameters["\\A_WIDTH"] = sig_a.size(); \
1775 cell->parameters["\\Y_WIDTH"] = sig_y.size(); \
1776 cell->setPort("\\A", sig_a); \
1777 cell->setPort("\\Y", sig_y); \
1778 cell->set_src_attribute(src); \
1779 return cell; \
1780 } \
1781 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed, const std::string &src) { \
1782 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
1783 add ## _func(name, sig_a, sig_y, is_signed, src); \
1784 return sig_y; \
1785 }
1786 DEF_METHOD(Not, sig_a.size(), "$not")
1787 DEF_METHOD(Pos, sig_a.size(), "$pos")
1788 DEF_METHOD(Neg, sig_a.size(), "$neg")
1789 DEF_METHOD(ReduceAnd, 1, "$reduce_and")
1790 DEF_METHOD(ReduceOr, 1, "$reduce_or")
1791 DEF_METHOD(ReduceXor, 1, "$reduce_xor")
1792 DEF_METHOD(ReduceXnor, 1, "$reduce_xnor")
1793 DEF_METHOD(ReduceBool, 1, "$reduce_bool")
1794 DEF_METHOD(LogicNot, 1, "$logic_not")
1795 #undef DEF_METHOD
1796
1797 #define DEF_METHOD(_func, _y_size, _type) \
1798 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed, const std::string &src) { \
1799 RTLIL::Cell *cell = addCell(name, _type); \
1800 cell->parameters["\\A_SIGNED"] = is_signed; \
1801 cell->parameters["\\B_SIGNED"] = is_signed; \
1802 cell->parameters["\\A_WIDTH"] = sig_a.size(); \
1803 cell->parameters["\\B_WIDTH"] = sig_b.size(); \
1804 cell->parameters["\\Y_WIDTH"] = sig_y.size(); \
1805 cell->setPort("\\A", sig_a); \
1806 cell->setPort("\\B", sig_b); \
1807 cell->setPort("\\Y", sig_y); \
1808 cell->set_src_attribute(src); \
1809 return cell; \
1810 } \
1811 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed, const std::string &src) { \
1812 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
1813 add ## _func(name, sig_a, sig_b, sig_y, is_signed, src); \
1814 return sig_y; \
1815 }
1816 DEF_METHOD(And, max(sig_a.size(), sig_b.size()), "$and")
1817 DEF_METHOD(Or, max(sig_a.size(), sig_b.size()), "$or")
1818 DEF_METHOD(Xor, max(sig_a.size(), sig_b.size()), "$xor")
1819 DEF_METHOD(Xnor, max(sig_a.size(), sig_b.size()), "$xnor")
1820 DEF_METHOD(Shl, sig_a.size(), "$shl")
1821 DEF_METHOD(Shr, sig_a.size(), "$shr")
1822 DEF_METHOD(Sshl, sig_a.size(), "$sshl")
1823 DEF_METHOD(Sshr, sig_a.size(), "$sshr")
1824 DEF_METHOD(Shift, sig_a.size(), "$shift")
1825 DEF_METHOD(Shiftx, sig_a.size(), "$shiftx")
1826 DEF_METHOD(Lt, 1, "$lt")
1827 DEF_METHOD(Le, 1, "$le")
1828 DEF_METHOD(Eq, 1, "$eq")
1829 DEF_METHOD(Ne, 1, "$ne")
1830 DEF_METHOD(Eqx, 1, "$eqx")
1831 DEF_METHOD(Nex, 1, "$nex")
1832 DEF_METHOD(Ge, 1, "$ge")
1833 DEF_METHOD(Gt, 1, "$gt")
1834 DEF_METHOD(Add, max(sig_a.size(), sig_b.size()), "$add")
1835 DEF_METHOD(Sub, max(sig_a.size(), sig_b.size()), "$sub")
1836 DEF_METHOD(Mul, max(sig_a.size(), sig_b.size()), "$mul")
1837 DEF_METHOD(Div, max(sig_a.size(), sig_b.size()), "$div")
1838 DEF_METHOD(Mod, max(sig_a.size(), sig_b.size()), "$mod")
1839 DEF_METHOD(LogicAnd, 1, "$logic_and")
1840 DEF_METHOD(LogicOr, 1, "$logic_or")
1841 #undef DEF_METHOD
1842
1843 #define DEF_METHOD(_func, _type, _pmux) \
1844 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, RTLIL::SigSpec sig_y, const std::string &src) { \
1845 RTLIL::Cell *cell = addCell(name, _type); \
1846 cell->parameters["\\WIDTH"] = sig_a.size(); \
1847 if (_pmux) cell->parameters["\\S_WIDTH"] = sig_s.size(); \
1848 cell->setPort("\\A", sig_a); \
1849 cell->setPort("\\B", sig_b); \
1850 cell->setPort("\\S", sig_s); \
1851 cell->setPort("\\Y", sig_y); \
1852 cell->set_src_attribute(src); \
1853 return cell; \
1854 } \
1855 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, const std::string &src) { \
1856 RTLIL::SigSpec sig_y = addWire(NEW_ID, sig_a.size()); \
1857 add ## _func(name, sig_a, sig_b, sig_s, sig_y, src); \
1858 return sig_y; \
1859 }
1860 DEF_METHOD(Mux, "$mux", 0)
1861 DEF_METHOD(Pmux, "$pmux", 1)
1862 #undef DEF_METHOD
1863
1864 #define DEF_METHOD_2(_func, _type, _P1, _P2) \
1865 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, const std::string &src) { \
1866 RTLIL::Cell *cell = addCell(name, _type); \
1867 cell->setPort("\\" #_P1, sig1); \
1868 cell->setPort("\\" #_P2, sig2); \
1869 cell->set_src_attribute(src); \
1870 return cell; \
1871 } \
1872 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, const std::string &src) { \
1873 RTLIL::SigBit sig2 = addWire(NEW_ID); \
1874 add ## _func(name, sig1, sig2, src); \
1875 return sig2; \
1876 }
1877 #define DEF_METHOD_3(_func, _type, _P1, _P2, _P3) \
1878 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, const std::string &src) { \
1879 RTLIL::Cell *cell = addCell(name, _type); \
1880 cell->setPort("\\" #_P1, sig1); \
1881 cell->setPort("\\" #_P2, sig2); \
1882 cell->setPort("\\" #_P3, sig3); \
1883 cell->set_src_attribute(src); \
1884 return cell; \
1885 } \
1886 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, const std::string &src) { \
1887 RTLIL::SigBit sig3 = addWire(NEW_ID); \
1888 add ## _func(name, sig1, sig2, sig3, src); \
1889 return sig3; \
1890 }
1891 #define DEF_METHOD_4(_func, _type, _P1, _P2, _P3, _P4) \
1892 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, RTLIL::SigBit sig4, const std::string &src) { \
1893 RTLIL::Cell *cell = addCell(name, _type); \
1894 cell->setPort("\\" #_P1, sig1); \
1895 cell->setPort("\\" #_P2, sig2); \
1896 cell->setPort("\\" #_P3, sig3); \
1897 cell->setPort("\\" #_P4, sig4); \
1898 cell->set_src_attribute(src); \
1899 return cell; \
1900 } \
1901 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, const std::string &src) { \
1902 RTLIL::SigBit sig4 = addWire(NEW_ID); \
1903 add ## _func(name, sig1, sig2, sig3, sig4, src); \
1904 return sig4; \
1905 }
1906 #define DEF_METHOD_5(_func, _type, _P1, _P2, _P3, _P4, _P5) \
1907 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, RTLIL::SigBit sig4, RTLIL::SigBit sig5, const std::string &src) { \
1908 RTLIL::Cell *cell = addCell(name, _type); \
1909 cell->setPort("\\" #_P1, sig1); \
1910 cell->setPort("\\" #_P2, sig2); \
1911 cell->setPort("\\" #_P3, sig3); \
1912 cell->setPort("\\" #_P4, sig4); \
1913 cell->setPort("\\" #_P5, sig5); \
1914 cell->set_src_attribute(src); \
1915 return cell; \
1916 } \
1917 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, RTLIL::SigBit sig4, const std::string &src) { \
1918 RTLIL::SigBit sig5 = addWire(NEW_ID); \
1919 add ## _func(name, sig1, sig2, sig3, sig4, sig5, src); \
1920 return sig5; \
1921 }
1922 DEF_METHOD_2(BufGate, "$_BUF_", A, Y)
1923 DEF_METHOD_2(NotGate, "$_NOT_", A, Y)
1924 DEF_METHOD_3(AndGate, "$_AND_", A, B, Y)
1925 DEF_METHOD_3(NandGate, "$_NAND_", A, B, Y)
1926 DEF_METHOD_3(OrGate, "$_OR_", A, B, Y)
1927 DEF_METHOD_3(NorGate, "$_NOR_", A, B, Y)
1928 DEF_METHOD_3(XorGate, "$_XOR_", A, B, Y)
1929 DEF_METHOD_3(XnorGate, "$_XNOR_", A, B, Y)
1930 DEF_METHOD_3(AndnotGate, "$_ANDNOT_", A, B, Y)
1931 DEF_METHOD_3(OrnotGate, "$_ORNOT_", A, B, Y)
1932 DEF_METHOD_4(MuxGate, "$_MUX_", A, B, S, Y)
1933 DEF_METHOD_4(Aoi3Gate, "$_AOI3_", A, B, C, Y)
1934 DEF_METHOD_4(Oai3Gate, "$_OAI3_", A, B, C, Y)
1935 DEF_METHOD_5(Aoi4Gate, "$_AOI4_", A, B, C, D, Y)
1936 DEF_METHOD_5(Oai4Gate, "$_OAI4_", A, B, C, D, Y)
1937 #undef DEF_METHOD_2
1938 #undef DEF_METHOD_3
1939 #undef DEF_METHOD_4
1940 #undef DEF_METHOD_5
1941
1942 RTLIL::Cell* RTLIL::Module::addPow(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool a_signed, bool b_signed, const std::string &src)
1943 {
1944 RTLIL::Cell *cell = addCell(name, "$pow");
1945 cell->parameters["\\A_SIGNED"] = a_signed;
1946 cell->parameters["\\B_SIGNED"] = b_signed;
1947 cell->parameters["\\A_WIDTH"] = sig_a.size();
1948 cell->parameters["\\B_WIDTH"] = sig_b.size();
1949 cell->parameters["\\Y_WIDTH"] = sig_y.size();
1950 cell->setPort("\\A", sig_a);
1951 cell->setPort("\\B", sig_b);
1952 cell->setPort("\\Y", sig_y);
1953 cell->set_src_attribute(src);
1954 return cell;
1955 }
1956
1957 RTLIL::Cell* RTLIL::Module::addSlice(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, RTLIL::Const offset, const std::string &src)
1958 {
1959 RTLIL::Cell *cell = addCell(name, "$slice");
1960 cell->parameters["\\A_WIDTH"] = sig_a.size();
1961 cell->parameters["\\Y_WIDTH"] = sig_y.size();
1962 cell->parameters["\\OFFSET"] = offset;
1963 cell->setPort("\\A", sig_a);
1964 cell->setPort("\\Y", sig_y);
1965 cell->set_src_attribute(src);
1966 return cell;
1967 }
1968
1969 RTLIL::Cell* RTLIL::Module::addConcat(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, const std::string &src)
1970 {
1971 RTLIL::Cell *cell = addCell(name, "$concat");
1972 cell->parameters["\\A_WIDTH"] = sig_a.size();
1973 cell->parameters["\\B_WIDTH"] = sig_b.size();
1974 cell->setPort("\\A", sig_a);
1975 cell->setPort("\\B", sig_b);
1976 cell->setPort("\\Y", sig_y);
1977 cell->set_src_attribute(src);
1978 return cell;
1979 }
1980
1981 RTLIL::Cell* RTLIL::Module::addLut(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, RTLIL::Const lut, const std::string &src)
1982 {
1983 RTLIL::Cell *cell = addCell(name, "$lut");
1984 cell->parameters["\\LUT"] = lut;
1985 cell->parameters["\\WIDTH"] = sig_a.size();
1986 cell->setPort("\\A", sig_a);
1987 cell->setPort("\\Y", sig_y);
1988 cell->set_src_attribute(src);
1989 return cell;
1990 }
1991
1992 RTLIL::Cell* RTLIL::Module::addTribuf(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_y, const std::string &src)
1993 {
1994 RTLIL::Cell *cell = addCell(name, "$tribuf");
1995 cell->parameters["\\WIDTH"] = sig_a.size();
1996 cell->setPort("\\A", sig_a);
1997 cell->setPort("\\EN", sig_en);
1998 cell->setPort("\\Y", sig_y);
1999 cell->set_src_attribute(src);
2000 return cell;
2001 }
2002
2003 RTLIL::Cell* RTLIL::Module::addAssert(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src)
2004 {
2005 RTLIL::Cell *cell = addCell(name, "$assert");
2006 cell->setPort("\\A", sig_a);
2007 cell->setPort("\\EN", sig_en);
2008 cell->set_src_attribute(src);
2009 return cell;
2010 }
2011
2012 RTLIL::Cell* RTLIL::Module::addAssume(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src)
2013 {
2014 RTLIL::Cell *cell = addCell(name, "$assume");
2015 cell->setPort("\\A", sig_a);
2016 cell->setPort("\\EN", sig_en);
2017 cell->set_src_attribute(src);
2018 return cell;
2019 }
2020
2021 RTLIL::Cell* RTLIL::Module::addLive(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src)
2022 {
2023 RTLIL::Cell *cell = addCell(name, "$live");
2024 cell->setPort("\\A", sig_a);
2025 cell->setPort("\\EN", sig_en);
2026 cell->set_src_attribute(src);
2027 return cell;
2028 }
2029
2030 RTLIL::Cell* RTLIL::Module::addFair(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src)
2031 {
2032 RTLIL::Cell *cell = addCell(name, "$fair");
2033 cell->setPort("\\A", sig_a);
2034 cell->setPort("\\EN", sig_en);
2035 cell->set_src_attribute(src);
2036 return cell;
2037 }
2038
2039 RTLIL::Cell* RTLIL::Module::addCover(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src)
2040 {
2041 RTLIL::Cell *cell = addCell(name, "$cover");
2042 cell->setPort("\\A", sig_a);
2043 cell->setPort("\\EN", sig_en);
2044 cell->set_src_attribute(src);
2045 return cell;
2046 }
2047
2048 RTLIL::Cell* RTLIL::Module::addEquiv(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, const std::string &src)
2049 {
2050 RTLIL::Cell *cell = addCell(name, "$equiv");
2051 cell->setPort("\\A", sig_a);
2052 cell->setPort("\\B", sig_b);
2053 cell->setPort("\\Y", sig_y);
2054 cell->set_src_attribute(src);
2055 return cell;
2056 }
2057
2058 RTLIL::Cell* RTLIL::Module::addSr(RTLIL::IdString name, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr, RTLIL::SigSpec sig_q, bool set_polarity, bool clr_polarity, const std::string &src)
2059 {
2060 RTLIL::Cell *cell = addCell(name, "$sr");
2061 cell->parameters["\\SET_POLARITY"] = set_polarity;
2062 cell->parameters["\\CLR_POLARITY"] = clr_polarity;
2063 cell->parameters["\\WIDTH"] = sig_q.size();
2064 cell->setPort("\\SET", sig_set);
2065 cell->setPort("\\CLR", sig_clr);
2066 cell->setPort("\\Q", sig_q);
2067 cell->set_src_attribute(src);
2068 return cell;
2069 }
2070
2071 RTLIL::Cell* RTLIL::Module::addFf(RTLIL::IdString name, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, const std::string &src)
2072 {
2073 RTLIL::Cell *cell = addCell(name, "$ff");
2074 cell->parameters["\\WIDTH"] = sig_q.size();
2075 cell->setPort("\\D", sig_d);
2076 cell->setPort("\\Q", sig_q);
2077 cell->set_src_attribute(src);
2078 return cell;
2079 }
2080
2081 RTLIL::Cell* RTLIL::Module::addDff(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, const std::string &src)
2082 {
2083 RTLIL::Cell *cell = addCell(name, "$dff");
2084 cell->parameters["\\CLK_POLARITY"] = clk_polarity;
2085 cell->parameters["\\WIDTH"] = sig_q.size();
2086 cell->setPort("\\CLK", sig_clk);
2087 cell->setPort("\\D", sig_d);
2088 cell->setPort("\\Q", sig_q);
2089 cell->set_src_attribute(src);
2090 return cell;
2091 }
2092
2093 RTLIL::Cell* RTLIL::Module::addDffe(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, bool en_polarity, const std::string &src)
2094 {
2095 RTLIL::Cell *cell = addCell(name, "$dffe");
2096 cell->parameters["\\CLK_POLARITY"] = clk_polarity;
2097 cell->parameters["\\EN_POLARITY"] = en_polarity;
2098 cell->parameters["\\WIDTH"] = sig_q.size();
2099 cell->setPort("\\CLK", sig_clk);
2100 cell->setPort("\\EN", sig_en);
2101 cell->setPort("\\D", sig_d);
2102 cell->setPort("\\Q", sig_q);
2103 cell->set_src_attribute(src);
2104 return cell;
2105 }
2106
2107 RTLIL::Cell* RTLIL::Module::addDffsr(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
2108 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
2109 {
2110 RTLIL::Cell *cell = addCell(name, "$dffsr");
2111 cell->parameters["\\CLK_POLARITY"] = clk_polarity;
2112 cell->parameters["\\SET_POLARITY"] = set_polarity;
2113 cell->parameters["\\CLR_POLARITY"] = clr_polarity;
2114 cell->parameters["\\WIDTH"] = sig_q.size();
2115 cell->setPort("\\CLK", sig_clk);
2116 cell->setPort("\\SET", sig_set);
2117 cell->setPort("\\CLR", sig_clr);
2118 cell->setPort("\\D", sig_d);
2119 cell->setPort("\\Q", sig_q);
2120 cell->set_src_attribute(src);
2121 return cell;
2122 }
2123
2124 RTLIL::Cell* RTLIL::Module::addAdff(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_arst, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q,
2125 RTLIL::Const arst_value, bool clk_polarity, bool arst_polarity, const std::string &src)
2126 {
2127 RTLIL::Cell *cell = addCell(name, "$adff");
2128 cell->parameters["\\CLK_POLARITY"] = clk_polarity;
2129 cell->parameters["\\ARST_POLARITY"] = arst_polarity;
2130 cell->parameters["\\ARST_VALUE"] = arst_value;
2131 cell->parameters["\\WIDTH"] = sig_q.size();
2132 cell->setPort("\\CLK", sig_clk);
2133 cell->setPort("\\ARST", sig_arst);
2134 cell->setPort("\\D", sig_d);
2135 cell->setPort("\\Q", sig_q);
2136 cell->set_src_attribute(src);
2137 return cell;
2138 }
2139
2140 RTLIL::Cell* RTLIL::Module::addDlatch(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity, const std::string &src)
2141 {
2142 RTLIL::Cell *cell = addCell(name, "$dlatch");
2143 cell->parameters["\\EN_POLARITY"] = en_polarity;
2144 cell->parameters["\\WIDTH"] = sig_q.size();
2145 cell->setPort("\\EN", sig_en);
2146 cell->setPort("\\D", sig_d);
2147 cell->setPort("\\Q", sig_q);
2148 cell->set_src_attribute(src);
2149 return cell;
2150 }
2151
2152 RTLIL::Cell* RTLIL::Module::addDlatchsr(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
2153 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
2154 {
2155 RTLIL::Cell *cell = addCell(name, "$dlatchsr");
2156 cell->parameters["\\EN_POLARITY"] = en_polarity;
2157 cell->parameters["\\SET_POLARITY"] = set_polarity;
2158 cell->parameters["\\CLR_POLARITY"] = clr_polarity;
2159 cell->parameters["\\WIDTH"] = sig_q.size();
2160 cell->setPort("\\EN", sig_en);
2161 cell->setPort("\\SET", sig_set);
2162 cell->setPort("\\CLR", sig_clr);
2163 cell->setPort("\\D", sig_d);
2164 cell->setPort("\\Q", sig_q);
2165 cell->set_src_attribute(src);
2166 return cell;
2167 }
2168
2169 RTLIL::Cell* RTLIL::Module::addFfGate(RTLIL::IdString name, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, const std::string &src)
2170 {
2171 RTLIL::Cell *cell = addCell(name, "$_FF_");
2172 cell->setPort("\\D", sig_d);
2173 cell->setPort("\\Q", sig_q);
2174 cell->set_src_attribute(src);
2175 return cell;
2176 }
2177
2178 RTLIL::Cell* RTLIL::Module::addDffGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, const std::string &src)
2179 {
2180 RTLIL::Cell *cell = addCell(name, stringf("$_DFF_%c_", clk_polarity ? 'P' : 'N'));
2181 cell->setPort("\\C", sig_clk);
2182 cell->setPort("\\D", sig_d);
2183 cell->setPort("\\Q", sig_q);
2184 cell->set_src_attribute(src);
2185 return cell;
2186 }
2187
2188 RTLIL::Cell* RTLIL::Module::addDffeGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, bool en_polarity, const std::string &src)
2189 {
2190 RTLIL::Cell *cell = addCell(name, stringf("$_DFFE_%c%c_", clk_polarity ? 'P' : 'N', en_polarity ? 'P' : 'N'));
2191 cell->setPort("\\C", sig_clk);
2192 cell->setPort("\\E", sig_en);
2193 cell->setPort("\\D", sig_d);
2194 cell->setPort("\\Q", sig_q);
2195 cell->set_src_attribute(src);
2196 return cell;
2197 }
2198
2199 RTLIL::Cell* RTLIL::Module::addDffsrGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
2200 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
2201 {
2202 RTLIL::Cell *cell = addCell(name, stringf("$_DFFSR_%c%c%c_", clk_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N'));
2203 cell->setPort("\\C", sig_clk);
2204 cell->setPort("\\S", sig_set);
2205 cell->setPort("\\R", sig_clr);
2206 cell->setPort("\\D", sig_d);
2207 cell->setPort("\\Q", sig_q);
2208 cell->set_src_attribute(src);
2209 return cell;
2210 }
2211
2212 RTLIL::Cell* RTLIL::Module::addAdffGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_arst, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q,
2213 bool arst_value, bool clk_polarity, bool arst_polarity, const std::string &src)
2214 {
2215 RTLIL::Cell *cell = addCell(name, stringf("$_DFF_%c%c%c_", clk_polarity ? 'P' : 'N', arst_polarity ? 'P' : 'N', arst_value ? '1' : '0'));
2216 cell->setPort("\\C", sig_clk);
2217 cell->setPort("\\R", sig_arst);
2218 cell->setPort("\\D", sig_d);
2219 cell->setPort("\\Q", sig_q);
2220 cell->set_src_attribute(src);
2221 return cell;
2222 }
2223
2224 RTLIL::Cell* RTLIL::Module::addDlatchGate(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity, const std::string &src)
2225 {
2226 RTLIL::Cell *cell = addCell(name, stringf("$_DLATCH_%c_", en_polarity ? 'P' : 'N'));
2227 cell->setPort("\\E", sig_en);
2228 cell->setPort("\\D", sig_d);
2229 cell->setPort("\\Q", sig_q);
2230 cell->set_src_attribute(src);
2231 return cell;
2232 }
2233
2234 RTLIL::Cell* RTLIL::Module::addDlatchsrGate(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
2235 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
2236 {
2237 RTLIL::Cell *cell = addCell(name, stringf("$_DLATCHSR_%c%c%c_", en_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N'));
2238 cell->setPort("\\E", sig_en);
2239 cell->setPort("\\S", sig_set);
2240 cell->setPort("\\R", sig_clr);
2241 cell->setPort("\\D", sig_d);
2242 cell->setPort("\\Q", sig_q);
2243 cell->set_src_attribute(src);
2244 return cell;
2245 }
2246
2247 RTLIL::SigSpec RTLIL::Module::Anyconst(RTLIL::IdString name, int width, const std::string &src)
2248 {
2249 RTLIL::SigSpec sig = addWire(NEW_ID, width);
2250 Cell *cell = addCell(name, "$anyconst");
2251 cell->setParam("\\WIDTH", width);
2252 cell->setPort("\\Y", sig);
2253 cell->set_src_attribute(src);
2254 return sig;
2255 }
2256
2257 RTLIL::SigSpec RTLIL::Module::Anyseq(RTLIL::IdString name, int width, const std::string &src)
2258 {
2259 RTLIL::SigSpec sig = addWire(NEW_ID, width);
2260 Cell *cell = addCell(name, "$anyseq");
2261 cell->setParam("\\WIDTH", width);
2262 cell->setPort("\\Y", sig);
2263 cell->set_src_attribute(src);
2264 return sig;
2265 }
2266
2267 RTLIL::SigSpec RTLIL::Module::Allconst(RTLIL::IdString name, int width, const std::string &src)
2268 {
2269 RTLIL::SigSpec sig = addWire(NEW_ID, width);
2270 Cell *cell = addCell(name, "$allconst");
2271 cell->setParam("\\WIDTH", width);
2272 cell->setPort("\\Y", sig);
2273 cell->set_src_attribute(src);
2274 return sig;
2275 }
2276
2277 RTLIL::SigSpec RTLIL::Module::Allseq(RTLIL::IdString name, int width, const std::string &src)
2278 {
2279 RTLIL::SigSpec sig = addWire(NEW_ID, width);
2280 Cell *cell = addCell(name, "$allseq");
2281 cell->setParam("\\WIDTH", width);
2282 cell->setPort("\\Y", sig);
2283 cell->set_src_attribute(src);
2284 return sig;
2285 }
2286
2287 RTLIL::SigSpec RTLIL::Module::Initstate(RTLIL::IdString name, const std::string &src)
2288 {
2289 RTLIL::SigSpec sig = addWire(NEW_ID);
2290 Cell *cell = addCell(name, "$initstate");
2291 cell->setPort("\\Y", sig);
2292 cell->set_src_attribute(src);
2293 return sig;
2294 }
2295
2296 RTLIL::Wire::Wire()
2297 {
2298 static unsigned int hashidx_count = 123456789;
2299 hashidx_count = mkhash_xorshift(hashidx_count);
2300 hashidx_ = hashidx_count;
2301
2302 module = nullptr;
2303 width = 1;
2304 start_offset = 0;
2305 port_id = 0;
2306 port_input = false;
2307 port_output = false;
2308 upto = false;
2309
2310 #ifdef WITH_PYTHON
2311 RTLIL::Wire::get_all_wires()->insert(std::pair<unsigned int, RTLIL::Wire*>(hashidx_, this));
2312 #endif
2313 }
2314
2315 RTLIL::Wire::~Wire()
2316 {
2317 #ifdef WITH_PYTHON
2318 RTLIL::Wire::get_all_wires()->erase(hashidx_);
2319 #endif
2320 }
2321
2322 #ifdef WITH_PYTHON
2323 static std::map<unsigned int, RTLIL::Wire*> all_wires;
2324 std::map<unsigned int, RTLIL::Wire*> *RTLIL::Wire::get_all_wires(void)
2325 {
2326 return &all_wires;
2327 }
2328 #endif
2329
2330 RTLIL::Memory::Memory()
2331 {
2332 static unsigned int hashidx_count = 123456789;
2333 hashidx_count = mkhash_xorshift(hashidx_count);
2334 hashidx_ = hashidx_count;
2335
2336 width = 1;
2337 start_offset = 0;
2338 size = 0;
2339 #ifdef WITH_PYTHON
2340 RTLIL::Memory::get_all_memorys()->insert(std::pair<unsigned int, RTLIL::Memory*>(hashidx_, this));
2341 #endif
2342 }
2343
2344 RTLIL::Cell::Cell() : module(nullptr)
2345 {
2346 static unsigned int hashidx_count = 123456789;
2347 hashidx_count = mkhash_xorshift(hashidx_count);
2348 hashidx_ = hashidx_count;
2349
2350 // log("#memtrace# %p\n", this);
2351 memhasher();
2352
2353 #ifdef WITH_PYTHON
2354 RTLIL::Cell::get_all_cells()->insert(std::pair<unsigned int, RTLIL::Cell*>(hashidx_, this));
2355 #endif
2356 }
2357
2358 RTLIL::Cell::~Cell()
2359 {
2360 #ifdef WITH_PYTHON
2361 RTLIL::Cell::get_all_cells()->erase(hashidx_);
2362 #endif
2363 }
2364
2365 #ifdef WITH_PYTHON
2366 static std::map<unsigned int, RTLIL::Cell*> all_cells;
2367 std::map<unsigned int, RTLIL::Cell*> *RTLIL::Cell::get_all_cells(void)
2368 {
2369 return &all_cells;
2370 }
2371 #endif
2372
2373 bool RTLIL::Cell::hasPort(RTLIL::IdString portname) const
2374 {
2375 return connections_.count(portname) != 0;
2376 }
2377
2378 void RTLIL::Cell::unsetPort(RTLIL::IdString portname)
2379 {
2380 RTLIL::SigSpec signal;
2381 auto conn_it = connections_.find(portname);
2382
2383 if (conn_it != connections_.end())
2384 {
2385 for (auto mon : module->monitors)
2386 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
2387
2388 if (module->design)
2389 for (auto mon : module->design->monitors)
2390 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
2391
2392 if (yosys_xtrace) {
2393 log("#X# Unconnect %s.%s.%s\n", log_id(this->module), log_id(this), log_id(portname));
2394 log_backtrace("-X- ", yosys_xtrace-1);
2395 }
2396
2397 connections_.erase(conn_it);
2398 }
2399 }
2400
2401 void RTLIL::Cell::setPort(RTLIL::IdString portname, RTLIL::SigSpec signal)
2402 {
2403 auto conn_it = connections_.find(portname);
2404
2405 if (conn_it == connections_.end()) {
2406 connections_[portname] = RTLIL::SigSpec();
2407 conn_it = connections_.find(portname);
2408 log_assert(conn_it != connections_.end());
2409 } else
2410 if (conn_it->second == signal)
2411 return;
2412
2413 for (auto mon : module->monitors)
2414 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
2415
2416 if (module->design)
2417 for (auto mon : module->design->monitors)
2418 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
2419
2420 if (yosys_xtrace) {
2421 log("#X# Connect %s.%s.%s = %s (%d)\n", log_id(this->module), log_id(this), log_id(portname), log_signal(signal), GetSize(signal));
2422 log_backtrace("-X- ", yosys_xtrace-1);
2423 }
2424
2425 conn_it->second = signal;
2426 }
2427
2428 const RTLIL::SigSpec &RTLIL::Cell::getPort(RTLIL::IdString portname) const
2429 {
2430 return connections_.at(portname);
2431 }
2432
2433 const dict<RTLIL::IdString, RTLIL::SigSpec> &RTLIL::Cell::connections() const
2434 {
2435 return connections_;
2436 }
2437
2438 bool RTLIL::Cell::known() const
2439 {
2440 if (yosys_celltypes.cell_known(type))
2441 return true;
2442 if (module && module->design && module->design->module(type))
2443 return true;
2444 return false;
2445 }
2446
2447 bool RTLIL::Cell::input(RTLIL::IdString portname) const
2448 {
2449 if (yosys_celltypes.cell_known(type))
2450 return yosys_celltypes.cell_input(type, portname);
2451 if (module && module->design) {
2452 RTLIL::Module *m = module->design->module(type);
2453 RTLIL::Wire *w = m ? m->wire(portname) : nullptr;
2454 return w && w->port_input;
2455 }
2456 return false;
2457 }
2458
2459 bool RTLIL::Cell::output(RTLIL::IdString portname) const
2460 {
2461 if (yosys_celltypes.cell_known(type))
2462 return yosys_celltypes.cell_output(type, portname);
2463 if (module && module->design) {
2464 RTLIL::Module *m = module->design->module(type);
2465 RTLIL::Wire *w = m ? m->wire(portname) : nullptr;
2466 return w && w->port_output;
2467 }
2468 return false;
2469 }
2470
2471 bool RTLIL::Cell::hasParam(RTLIL::IdString paramname) const
2472 {
2473 return parameters.count(paramname) != 0;
2474 }
2475
2476 void RTLIL::Cell::unsetParam(RTLIL::IdString paramname)
2477 {
2478 parameters.erase(paramname);
2479 }
2480
2481 void RTLIL::Cell::setParam(RTLIL::IdString paramname, RTLIL::Const value)
2482 {
2483 parameters[paramname] = value;
2484 }
2485
2486 const RTLIL::Const &RTLIL::Cell::getParam(RTLIL::IdString paramname) const
2487 {
2488 return parameters.at(paramname);
2489 }
2490
2491 void RTLIL::Cell::sort()
2492 {
2493 connections_.sort(sort_by_id_str());
2494 parameters.sort(sort_by_id_str());
2495 attributes.sort(sort_by_id_str());
2496 }
2497
2498 void RTLIL::Cell::check()
2499 {
2500 #ifndef NDEBUG
2501 InternalCellChecker checker(NULL, this);
2502 checker.check();
2503 #endif
2504 }
2505
2506 void RTLIL::Cell::fixup_parameters(bool set_a_signed, bool set_b_signed)
2507 {
2508 if (type.substr(0, 1) != "$" || type.substr(0, 2) == "$_" || type.substr(0, 8) == "$paramod" || type.substr(0,10) == "$fmcombine" ||
2509 type.substr(0, 9) == "$verific$" || type.substr(0, 7) == "$array:" || type.substr(0, 8) == "$extern:")
2510 return;
2511
2512 if (type == "$mux" || type == "$pmux") {
2513 parameters["\\WIDTH"] = GetSize(connections_["\\Y"]);
2514 if (type == "$pmux")
2515 parameters["\\S_WIDTH"] = GetSize(connections_["\\S"]);
2516 check();
2517 return;
2518 }
2519
2520 if (type == "$lut" || type == "$sop") {
2521 parameters["\\WIDTH"] = GetSize(connections_["\\A"]);
2522 return;
2523 }
2524
2525 if (type == "$fa") {
2526 parameters["\\WIDTH"] = GetSize(connections_["\\Y"]);
2527 return;
2528 }
2529
2530 if (type == "$lcu") {
2531 parameters["\\WIDTH"] = GetSize(connections_["\\CO"]);
2532 return;
2533 }
2534
2535 bool signedness_ab = !type.in("$slice", "$concat", "$macc");
2536
2537 if (connections_.count("\\A")) {
2538 if (signedness_ab) {
2539 if (set_a_signed)
2540 parameters["\\A_SIGNED"] = true;
2541 else if (parameters.count("\\A_SIGNED") == 0)
2542 parameters["\\A_SIGNED"] = false;
2543 }
2544 parameters["\\A_WIDTH"] = GetSize(connections_["\\A"]);
2545 }
2546
2547 if (connections_.count("\\B")) {
2548 if (signedness_ab) {
2549 if (set_b_signed)
2550 parameters["\\B_SIGNED"] = true;
2551 else if (parameters.count("\\B_SIGNED") == 0)
2552 parameters["\\B_SIGNED"] = false;
2553 }
2554 parameters["\\B_WIDTH"] = GetSize(connections_["\\B"]);
2555 }
2556
2557 if (connections_.count("\\Y"))
2558 parameters["\\Y_WIDTH"] = GetSize(connections_["\\Y"]);
2559
2560 if (connections_.count("\\Q"))
2561 parameters["\\WIDTH"] = GetSize(connections_["\\Q"]);
2562
2563 check();
2564 }
2565
2566 RTLIL::SigChunk::SigChunk()
2567 {
2568 wire = NULL;
2569 width = 0;
2570 offset = 0;
2571 }
2572
2573 RTLIL::SigChunk::SigChunk(const RTLIL::Const &value)
2574 {
2575 wire = NULL;
2576 data = value.bits;
2577 width = GetSize(data);
2578 offset = 0;
2579 }
2580
2581 RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire)
2582 {
2583 log_assert(wire != nullptr);
2584 this->wire = wire;
2585 this->width = wire->width;
2586 this->offset = 0;
2587 }
2588
2589 RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire, int offset, int width)
2590 {
2591 log_assert(wire != nullptr);
2592 this->wire = wire;
2593 this->width = width;
2594 this->offset = offset;
2595 }
2596
2597 RTLIL::SigChunk::SigChunk(const std::string &str)
2598 {
2599 wire = NULL;
2600 data = RTLIL::Const(str).bits;
2601 width = GetSize(data);
2602 offset = 0;
2603 }
2604
2605 RTLIL::SigChunk::SigChunk(int val, int width)
2606 {
2607 wire = NULL;
2608 data = RTLIL::Const(val, width).bits;
2609 this->width = GetSize(data);
2610 offset = 0;
2611 }
2612
2613 RTLIL::SigChunk::SigChunk(RTLIL::State bit, int width)
2614 {
2615 wire = NULL;
2616 data = RTLIL::Const(bit, width).bits;
2617 this->width = GetSize(data);
2618 offset = 0;
2619 }
2620
2621 RTLIL::SigChunk::SigChunk(RTLIL::SigBit bit)
2622 {
2623 wire = bit.wire;
2624 offset = 0;
2625 if (wire == NULL)
2626 data = RTLIL::Const(bit.data).bits;
2627 else
2628 offset = bit.offset;
2629 width = 1;
2630 }
2631
2632 RTLIL::SigChunk::SigChunk(const RTLIL::SigChunk &sigchunk) : data(sigchunk.data)
2633 {
2634 wire = sigchunk.wire;
2635 data = sigchunk.data;
2636 width = sigchunk.width;
2637 offset = sigchunk.offset;
2638 }
2639
2640 RTLIL::SigChunk RTLIL::SigChunk::extract(int offset, int length) const
2641 {
2642 RTLIL::SigChunk ret;
2643 if (wire) {
2644 ret.wire = wire;
2645 ret.offset = this->offset + offset;
2646 ret.width = length;
2647 } else {
2648 for (int i = 0; i < length; i++)
2649 ret.data.push_back(data[offset+i]);
2650 ret.width = length;
2651 }
2652 return ret;
2653 }
2654
2655 bool RTLIL::SigChunk::operator <(const RTLIL::SigChunk &other) const
2656 {
2657 if (wire && other.wire)
2658 if (wire->name != other.wire->name)
2659 return wire->name < other.wire->name;
2660
2661 if (wire != other.wire)
2662 return wire < other.wire;
2663
2664 if (offset != other.offset)
2665 return offset < other.offset;
2666
2667 if (width != other.width)
2668 return width < other.width;
2669
2670 return data < other.data;
2671 }
2672
2673 bool RTLIL::SigChunk::operator ==(const RTLIL::SigChunk &other) const
2674 {
2675 return wire == other.wire && width == other.width && offset == other.offset && data == other.data;
2676 }
2677
2678 bool RTLIL::SigChunk::operator !=(const RTLIL::SigChunk &other) const
2679 {
2680 if (*this == other)
2681 return false;
2682 return true;
2683 }
2684
2685 RTLIL::SigSpec::SigSpec()
2686 {
2687 width_ = 0;
2688 hash_ = 0;
2689 }
2690
2691 RTLIL::SigSpec::SigSpec(const RTLIL::SigSpec &other)
2692 {
2693 *this = other;
2694 }
2695
2696 RTLIL::SigSpec::SigSpec(std::initializer_list<RTLIL::SigSpec> parts)
2697 {
2698 cover("kernel.rtlil.sigspec.init.list");
2699
2700 width_ = 0;
2701 hash_ = 0;
2702
2703 std::vector<RTLIL::SigSpec> parts_vec(parts.begin(), parts.end());
2704 for (auto it = parts_vec.rbegin(); it != parts_vec.rend(); it++)
2705 append(*it);
2706 }
2707
2708 const RTLIL::SigSpec &RTLIL::SigSpec::operator=(const RTLIL::SigSpec &other)
2709 {
2710 cover("kernel.rtlil.sigspec.assign");
2711
2712 width_ = other.width_;
2713 hash_ = other.hash_;
2714 chunks_ = other.chunks_;
2715 bits_.clear();
2716
2717 if (!other.bits_.empty())
2718 {
2719 RTLIL::SigChunk *last = NULL;
2720 int last_end_offset = 0;
2721
2722 for (auto &bit : other.bits_) {
2723 if (last && bit.wire == last->wire) {
2724 if (bit.wire == NULL) {
2725 last->data.push_back(bit.data);
2726 last->width++;
2727 continue;
2728 } else if (last_end_offset == bit.offset) {
2729 last_end_offset++;
2730 last->width++;
2731 continue;
2732 }
2733 }
2734 chunks_.push_back(bit);
2735 last = &chunks_.back();
2736 last_end_offset = bit.offset + 1;
2737 }
2738
2739 check();
2740 }
2741
2742 return *this;
2743 }
2744
2745 RTLIL::SigSpec::SigSpec(const RTLIL::Const &value)
2746 {
2747 cover("kernel.rtlil.sigspec.init.const");
2748
2749 chunks_.push_back(RTLIL::SigChunk(value));
2750 width_ = chunks_.back().width;
2751 hash_ = 0;
2752 check();
2753 }
2754
2755 RTLIL::SigSpec::SigSpec(const RTLIL::SigChunk &chunk)
2756 {
2757 cover("kernel.rtlil.sigspec.init.chunk");
2758
2759 chunks_.push_back(chunk);
2760 width_ = chunks_.back().width;
2761 hash_ = 0;
2762 check();
2763 }
2764
2765 RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire)
2766 {
2767 cover("kernel.rtlil.sigspec.init.wire");
2768
2769 chunks_.push_back(RTLIL::SigChunk(wire));
2770 width_ = chunks_.back().width;
2771 hash_ = 0;
2772 check();
2773 }
2774
2775 RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire, int offset, int width)
2776 {
2777 cover("kernel.rtlil.sigspec.init.wire_part");
2778
2779 chunks_.push_back(RTLIL::SigChunk(wire, offset, width));
2780 width_ = chunks_.back().width;
2781 hash_ = 0;
2782 check();
2783 }
2784
2785 RTLIL::SigSpec::SigSpec(const std::string &str)
2786 {
2787 cover("kernel.rtlil.sigspec.init.str");
2788
2789 chunks_.push_back(RTLIL::SigChunk(str));
2790 width_ = chunks_.back().width;
2791 hash_ = 0;
2792 check();
2793 }
2794
2795 RTLIL::SigSpec::SigSpec(int val, int width)
2796 {
2797 cover("kernel.rtlil.sigspec.init.int");
2798
2799 chunks_.push_back(RTLIL::SigChunk(val, width));
2800 width_ = width;
2801 hash_ = 0;
2802 check();
2803 }
2804
2805 RTLIL::SigSpec::SigSpec(RTLIL::State bit, int width)
2806 {
2807 cover("kernel.rtlil.sigspec.init.state");
2808
2809 chunks_.push_back(RTLIL::SigChunk(bit, width));
2810 width_ = width;
2811 hash_ = 0;
2812 check();
2813 }
2814
2815 RTLIL::SigSpec::SigSpec(RTLIL::SigBit bit, int width)
2816 {
2817 cover("kernel.rtlil.sigspec.init.bit");
2818
2819 if (bit.wire == NULL)
2820 chunks_.push_back(RTLIL::SigChunk(bit.data, width));
2821 else
2822 for (int i = 0; i < width; i++)
2823 chunks_.push_back(bit);
2824 width_ = width;
2825 hash_ = 0;
2826 check();
2827 }
2828
2829 RTLIL::SigSpec::SigSpec(std::vector<RTLIL::SigChunk> chunks)
2830 {
2831 cover("kernel.rtlil.sigspec.init.stdvec_chunks");
2832
2833 width_ = 0;
2834 hash_ = 0;
2835 for (auto &c : chunks)
2836 append(c);
2837 check();
2838 }
2839
2840 RTLIL::SigSpec::SigSpec(std::vector<RTLIL::SigBit> bits)
2841 {
2842 cover("kernel.rtlil.sigspec.init.stdvec_bits");
2843
2844 width_ = 0;
2845 hash_ = 0;
2846 for (auto &bit : bits)
2847 append_bit(bit);
2848 check();
2849 }
2850
2851 RTLIL::SigSpec::SigSpec(pool<RTLIL::SigBit> bits)
2852 {
2853 cover("kernel.rtlil.sigspec.init.pool_bits");
2854
2855 width_ = 0;
2856 hash_ = 0;
2857 for (auto &bit : bits)
2858 append_bit(bit);
2859 check();
2860 }
2861
2862 RTLIL::SigSpec::SigSpec(std::set<RTLIL::SigBit> bits)
2863 {
2864 cover("kernel.rtlil.sigspec.init.stdset_bits");
2865
2866 width_ = 0;
2867 hash_ = 0;
2868 for (auto &bit : bits)
2869 append_bit(bit);
2870 check();
2871 }
2872
2873 RTLIL::SigSpec::SigSpec(bool bit)
2874 {
2875 cover("kernel.rtlil.sigspec.init.bool");
2876
2877 width_ = 0;
2878 hash_ = 0;
2879 append_bit(bit);
2880 check();
2881 }
2882
2883 void RTLIL::SigSpec::pack() const
2884 {
2885 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
2886
2887 if (that->bits_.empty())
2888 return;
2889
2890 cover("kernel.rtlil.sigspec.convert.pack");
2891 log_assert(that->chunks_.empty());
2892
2893 std::vector<RTLIL::SigBit> old_bits;
2894 old_bits.swap(that->bits_);
2895
2896 RTLIL::SigChunk *last = NULL;
2897 int last_end_offset = 0;
2898
2899 for (auto &bit : old_bits) {
2900 if (last && bit.wire == last->wire) {
2901 if (bit.wire == NULL) {
2902 last->data.push_back(bit.data);
2903 last->width++;
2904 continue;
2905 } else if (last_end_offset == bit.offset) {
2906 last_end_offset++;
2907 last->width++;
2908 continue;
2909 }
2910 }
2911 that->chunks_.push_back(bit);
2912 last = &that->chunks_.back();
2913 last_end_offset = bit.offset + 1;
2914 }
2915
2916 check();
2917 }
2918
2919 void RTLIL::SigSpec::unpack() const
2920 {
2921 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
2922
2923 if (that->chunks_.empty())
2924 return;
2925
2926 cover("kernel.rtlil.sigspec.convert.unpack");
2927 log_assert(that->bits_.empty());
2928
2929 that->bits_.reserve(that->width_);
2930 for (auto &c : that->chunks_)
2931 for (int i = 0; i < c.width; i++)
2932 that->bits_.push_back(RTLIL::SigBit(c, i));
2933
2934 that->chunks_.clear();
2935 that->hash_ = 0;
2936 }
2937
2938 void RTLIL::SigSpec::updhash() const
2939 {
2940 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
2941
2942 if (that->hash_ != 0)
2943 return;
2944
2945 cover("kernel.rtlil.sigspec.hash");
2946 that->pack();
2947
2948 that->hash_ = mkhash_init;
2949 for (auto &c : that->chunks_)
2950 if (c.wire == NULL) {
2951 for (auto &v : c.data)
2952 that->hash_ = mkhash(that->hash_, v);
2953 } else {
2954 that->hash_ = mkhash(that->hash_, c.wire->name.index_);
2955 that->hash_ = mkhash(that->hash_, c.offset);
2956 that->hash_ = mkhash(that->hash_, c.width);
2957 }
2958
2959 if (that->hash_ == 0)
2960 that->hash_ = 1;
2961 }
2962
2963 void RTLIL::SigSpec::sort()
2964 {
2965 unpack();
2966 cover("kernel.rtlil.sigspec.sort");
2967 std::sort(bits_.begin(), bits_.end());
2968 }
2969
2970 void RTLIL::SigSpec::sort_and_unify()
2971 {
2972 unpack();
2973 cover("kernel.rtlil.sigspec.sort_and_unify");
2974
2975 // A copy of the bits vector is used to prevent duplicating the logic from
2976 // SigSpec::SigSpec(std::vector<SigBit>). This incurrs an extra copy but
2977 // that isn't showing up as significant in profiles.
2978 std::vector<SigBit> unique_bits = bits_;
2979 std::sort(unique_bits.begin(), unique_bits.end());
2980 auto last = std::unique(unique_bits.begin(), unique_bits.end());
2981 unique_bits.erase(last, unique_bits.end());
2982
2983 *this = unique_bits;
2984 }
2985
2986 void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with)
2987 {
2988 replace(pattern, with, this);
2989 }
2990
2991 void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with, RTLIL::SigSpec *other) const
2992 {
2993 log_assert(other != NULL);
2994 log_assert(width_ == other->width_);
2995 log_assert(pattern.width_ == with.width_);
2996
2997 pattern.unpack();
2998 with.unpack();
2999 unpack();
3000 other->unpack();
3001
3002 for (int i = 0; i < GetSize(pattern.bits_); i++) {
3003 if (pattern.bits_[i].wire != NULL) {
3004 for (int j = 0; j < GetSize(bits_); j++) {
3005 if (bits_[j] == pattern.bits_[i]) {
3006 other->bits_[j] = with.bits_[i];
3007 }
3008 }
3009 }
3010 }
3011
3012 other->check();
3013 }
3014
3015 void RTLIL::SigSpec::replace(const dict<RTLIL::SigBit, RTLIL::SigBit> &rules)
3016 {
3017 replace(rules, this);
3018 }
3019
3020 void RTLIL::SigSpec::replace(const dict<RTLIL::SigBit, RTLIL::SigBit> &rules, RTLIL::SigSpec *other) const
3021 {
3022 cover("kernel.rtlil.sigspec.replace_dict");
3023
3024 log_assert(other != NULL);
3025 log_assert(width_ == other->width_);
3026
3027 unpack();
3028 other->unpack();
3029
3030 for (int i = 0; i < GetSize(bits_); i++) {
3031 auto it = rules.find(bits_[i]);
3032 if (it != rules.end())
3033 other->bits_[i] = it->second;
3034 }
3035
3036 other->check();
3037 }
3038
3039 void RTLIL::SigSpec::replace(const std::map<RTLIL::SigBit, RTLIL::SigBit> &rules)
3040 {
3041 replace(rules, this);
3042 }
3043
3044 void RTLIL::SigSpec::replace(const std::map<RTLIL::SigBit, RTLIL::SigBit> &rules, RTLIL::SigSpec *other) const
3045 {
3046 cover("kernel.rtlil.sigspec.replace_map");
3047
3048 log_assert(other != NULL);
3049 log_assert(width_ == other->width_);
3050
3051 unpack();
3052 other->unpack();
3053
3054 for (int i = 0; i < GetSize(bits_); i++) {
3055 auto it = rules.find(bits_[i]);
3056 if (it != rules.end())
3057 other->bits_[i] = it->second;
3058 }
3059
3060 other->check();
3061 }
3062
3063 void RTLIL::SigSpec::remove(const RTLIL::SigSpec &pattern)
3064 {
3065 remove2(pattern, NULL);
3066 }
3067
3068 void RTLIL::SigSpec::remove(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other) const
3069 {
3070 RTLIL::SigSpec tmp = *this;
3071 tmp.remove2(pattern, other);
3072 }
3073
3074 void RTLIL::SigSpec::remove2(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other)
3075 {
3076 if (other)
3077 cover("kernel.rtlil.sigspec.remove_other");
3078 else
3079 cover("kernel.rtlil.sigspec.remove");
3080
3081 unpack();
3082 if (other != NULL) {
3083 log_assert(width_ == other->width_);
3084 other->unpack();
3085 }
3086
3087 for (int i = GetSize(bits_) - 1; i >= 0; i--)
3088 {
3089 if (bits_[i].wire == NULL) continue;
3090
3091 for (auto &pattern_chunk : pattern.chunks())
3092 if (bits_[i].wire == pattern_chunk.wire &&
3093 bits_[i].offset >= pattern_chunk.offset &&
3094 bits_[i].offset < pattern_chunk.offset + pattern_chunk.width) {
3095 bits_.erase(bits_.begin() + i);
3096 width_--;
3097 if (other != NULL) {
3098 other->bits_.erase(other->bits_.begin() + i);
3099 other->width_--;
3100 }
3101 break;
3102 }
3103 }
3104
3105 check();
3106 }
3107
3108 void RTLIL::SigSpec::remove(const pool<RTLIL::SigBit> &pattern)
3109 {
3110 remove2(pattern, NULL);
3111 }
3112
3113 void RTLIL::SigSpec::remove(const pool<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other) const
3114 {
3115 RTLIL::SigSpec tmp = *this;
3116 tmp.remove2(pattern, other);
3117 }
3118
3119 void RTLIL::SigSpec::remove2(const pool<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other)
3120 {
3121 if (other)
3122 cover("kernel.rtlil.sigspec.remove_other");
3123 else
3124 cover("kernel.rtlil.sigspec.remove");
3125
3126 unpack();
3127
3128 if (other != NULL) {
3129 log_assert(width_ == other->width_);
3130 other->unpack();
3131 }
3132
3133 for (int i = GetSize(bits_) - 1; i >= 0; i--) {
3134 if (bits_[i].wire != NULL && pattern.count(bits_[i])) {
3135 bits_.erase(bits_.begin() + i);
3136 width_--;
3137 if (other != NULL) {
3138 other->bits_.erase(other->bits_.begin() + i);
3139 other->width_--;
3140 }
3141 }
3142 }
3143
3144 check();
3145 }
3146
3147 void RTLIL::SigSpec::remove2(const std::set<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other)
3148 {
3149 if (other)
3150 cover("kernel.rtlil.sigspec.remove_other");
3151 else
3152 cover("kernel.rtlil.sigspec.remove");
3153
3154 unpack();
3155
3156 if (other != NULL) {
3157 log_assert(width_ == other->width_);
3158 other->unpack();
3159 }
3160
3161 for (int i = GetSize(bits_) - 1; i >= 0; i--) {
3162 if (bits_[i].wire != NULL && pattern.count(bits_[i])) {
3163 bits_.erase(bits_.begin() + i);
3164 width_--;
3165 if (other != NULL) {
3166 other->bits_.erase(other->bits_.begin() + i);
3167 other->width_--;
3168 }
3169 }
3170 }
3171
3172 check();
3173 }
3174
3175 RTLIL::SigSpec RTLIL::SigSpec::extract(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec *other) const
3176 {
3177 if (other)
3178 cover("kernel.rtlil.sigspec.extract_other");
3179 else
3180 cover("kernel.rtlil.sigspec.extract");
3181
3182 log_assert(other == NULL || width_ == other->width_);
3183
3184 RTLIL::SigSpec ret;
3185 std::vector<RTLIL::SigBit> bits_match = to_sigbit_vector();
3186
3187 for (auto& pattern_chunk : pattern.chunks()) {
3188 if (other) {
3189 std::vector<RTLIL::SigBit> bits_other = other->to_sigbit_vector();
3190 for (int i = 0; i < width_; i++)
3191 if (bits_match[i].wire &&
3192 bits_match[i].wire == pattern_chunk.wire &&
3193 bits_match[i].offset >= pattern_chunk.offset &&
3194 bits_match[i].offset < pattern_chunk.offset + pattern_chunk.width)
3195 ret.append_bit(bits_other[i]);
3196 } else {
3197 for (int i = 0; i < width_; i++)
3198 if (bits_match[i].wire &&
3199 bits_match[i].wire == pattern_chunk.wire &&
3200 bits_match[i].offset >= pattern_chunk.offset &&
3201 bits_match[i].offset < pattern_chunk.offset + pattern_chunk.width)
3202 ret.append_bit(bits_match[i]);
3203 }
3204 }
3205
3206 ret.check();
3207 return ret;
3208 }
3209
3210 RTLIL::SigSpec RTLIL::SigSpec::extract(const pool<RTLIL::SigBit> &pattern, const RTLIL::SigSpec *other) const
3211 {
3212 if (other)
3213 cover("kernel.rtlil.sigspec.extract_other");
3214 else
3215 cover("kernel.rtlil.sigspec.extract");
3216
3217 log_assert(other == NULL || width_ == other->width_);
3218
3219 std::vector<RTLIL::SigBit> bits_match = to_sigbit_vector();
3220 RTLIL::SigSpec ret;
3221
3222 if (other) {
3223 std::vector<RTLIL::SigBit> bits_other = other->to_sigbit_vector();
3224 for (int i = 0; i < width_; i++)
3225 if (bits_match[i].wire && pattern.count(bits_match[i]))
3226 ret.append_bit(bits_other[i]);
3227 } else {
3228 for (int i = 0; i < width_; i++)
3229 if (bits_match[i].wire && pattern.count(bits_match[i]))
3230 ret.append_bit(bits_match[i]);
3231 }
3232
3233 ret.check();
3234 return ret;
3235 }
3236
3237 void RTLIL::SigSpec::replace(int offset, const RTLIL::SigSpec &with)
3238 {
3239 cover("kernel.rtlil.sigspec.replace_pos");
3240
3241 unpack();
3242 with.unpack();
3243
3244 log_assert(offset >= 0);
3245 log_assert(with.width_ >= 0);
3246 log_assert(offset+with.width_ <= width_);
3247
3248 for (int i = 0; i < with.width_; i++)
3249 bits_.at(offset + i) = with.bits_.at(i);
3250
3251 check();
3252 }
3253
3254 void RTLIL::SigSpec::remove_const()
3255 {
3256 if (packed())
3257 {
3258 cover("kernel.rtlil.sigspec.remove_const.packed");
3259
3260 std::vector<RTLIL::SigChunk> new_chunks;
3261 new_chunks.reserve(GetSize(chunks_));
3262
3263 width_ = 0;
3264 for (auto &chunk : chunks_)
3265 if (chunk.wire != NULL) {
3266 new_chunks.push_back(chunk);
3267 width_ += chunk.width;
3268 }
3269
3270 chunks_.swap(new_chunks);
3271 }
3272 else
3273 {
3274 cover("kernel.rtlil.sigspec.remove_const.unpacked");
3275
3276 std::vector<RTLIL::SigBit> new_bits;
3277 new_bits.reserve(width_);
3278
3279 for (auto &bit : bits_)
3280 if (bit.wire != NULL)
3281 new_bits.push_back(bit);
3282
3283 bits_.swap(new_bits);
3284 width_ = bits_.size();
3285 }
3286
3287 check();
3288 }
3289
3290 void RTLIL::SigSpec::remove(int offset, int length)
3291 {
3292 cover("kernel.rtlil.sigspec.remove_pos");
3293
3294 unpack();
3295
3296 log_assert(offset >= 0);
3297 log_assert(length >= 0);
3298 log_assert(offset + length <= width_);
3299
3300 bits_.erase(bits_.begin() + offset, bits_.begin() + offset + length);
3301 width_ = bits_.size();
3302
3303 check();
3304 }
3305
3306 RTLIL::SigSpec RTLIL::SigSpec::extract(int offset, int length) const
3307 {
3308 unpack();
3309 cover("kernel.rtlil.sigspec.extract_pos");
3310 return std::vector<RTLIL::SigBit>(bits_.begin() + offset, bits_.begin() + offset + length);
3311 }
3312
3313 void RTLIL::SigSpec::append(const RTLIL::SigSpec &signal)
3314 {
3315 if (signal.width_ == 0)
3316 return;
3317
3318 if (width_ == 0) {
3319 *this = signal;
3320 return;
3321 }
3322
3323 cover("kernel.rtlil.sigspec.append");
3324
3325 if (packed() != signal.packed()) {
3326 pack();
3327 signal.pack();
3328 }
3329
3330 if (packed())
3331 for (auto &other_c : signal.chunks_)
3332 {
3333 auto &my_last_c = chunks_.back();
3334 if (my_last_c.wire == NULL && other_c.wire == NULL) {
3335 auto &this_data = my_last_c.data;
3336 auto &other_data = other_c.data;
3337 this_data.insert(this_data.end(), other_data.begin(), other_data.end());
3338 my_last_c.width += other_c.width;
3339 } else
3340 if (my_last_c.wire == other_c.wire && my_last_c.offset + my_last_c.width == other_c.offset) {
3341 my_last_c.width += other_c.width;
3342 } else
3343 chunks_.push_back(other_c);
3344 }
3345 else
3346 bits_.insert(bits_.end(), signal.bits_.begin(), signal.bits_.end());
3347
3348 width_ += signal.width_;
3349 check();
3350 }
3351
3352 void RTLIL::SigSpec::append_bit(const RTLIL::SigBit &bit)
3353 {
3354 if (packed())
3355 {
3356 cover("kernel.rtlil.sigspec.append_bit.packed");
3357
3358 if (chunks_.size() == 0)
3359 chunks_.push_back(bit);
3360 else
3361 if (bit.wire == NULL)
3362 if (chunks_.back().wire == NULL) {
3363 chunks_.back().data.push_back(bit.data);
3364 chunks_.back().width++;
3365 } else
3366 chunks_.push_back(bit);
3367 else
3368 if (chunks_.back().wire == bit.wire && chunks_.back().offset + chunks_.back().width == bit.offset)
3369 chunks_.back().width++;
3370 else
3371 chunks_.push_back(bit);
3372 }
3373 else
3374 {
3375 cover("kernel.rtlil.sigspec.append_bit.unpacked");
3376 bits_.push_back(bit);
3377 }
3378
3379 width_++;
3380 check();
3381 }
3382
3383 void RTLIL::SigSpec::extend_u0(int width, bool is_signed)
3384 {
3385 cover("kernel.rtlil.sigspec.extend_u0");
3386
3387 pack();
3388
3389 if (width_ > width)
3390 remove(width, width_ - width);
3391
3392 if (width_ < width) {
3393 RTLIL::SigBit padding = width_ > 0 ? (*this)[width_ - 1] : RTLIL::State::Sx;
3394 if (!is_signed)
3395 padding = RTLIL::State::S0;
3396 while (width_ < width)
3397 append(padding);
3398 }
3399
3400 }
3401
3402 RTLIL::SigSpec RTLIL::SigSpec::repeat(int num) const
3403 {
3404 cover("kernel.rtlil.sigspec.repeat");
3405
3406 RTLIL::SigSpec sig;
3407 for (int i = 0; i < num; i++)
3408 sig.append(*this);
3409 return sig;
3410 }
3411
3412 #ifndef NDEBUG
3413 void RTLIL::SigSpec::check() const
3414 {
3415 if (width_ > 64)
3416 {
3417 cover("kernel.rtlil.sigspec.check.skip");
3418 }
3419 else if (packed())
3420 {
3421 cover("kernel.rtlil.sigspec.check.packed");
3422
3423 int w = 0;
3424 for (size_t i = 0; i < chunks_.size(); i++) {
3425 const RTLIL::SigChunk chunk = chunks_[i];
3426 if (chunk.wire == NULL) {
3427 if (i > 0)
3428 log_assert(chunks_[i-1].wire != NULL);
3429 log_assert(chunk.offset == 0);
3430 log_assert(chunk.data.size() == (size_t)chunk.width);
3431 } else {
3432 if (i > 0 && chunks_[i-1].wire == chunk.wire)
3433 log_assert(chunk.offset != chunks_[i-1].offset + chunks_[i-1].width);
3434 log_assert(chunk.offset >= 0);
3435 log_assert(chunk.width >= 0);
3436 log_assert(chunk.offset + chunk.width <= chunk.wire->width);
3437 log_assert(chunk.data.size() == 0);
3438 }
3439 w += chunk.width;
3440 }
3441 log_assert(w == width_);
3442 log_assert(bits_.empty());
3443 }
3444 else
3445 {
3446 cover("kernel.rtlil.sigspec.check.unpacked");
3447
3448 log_assert(width_ == GetSize(bits_));
3449 log_assert(chunks_.empty());
3450 }
3451 }
3452 #endif
3453
3454 bool RTLIL::SigSpec::operator <(const RTLIL::SigSpec &other) const
3455 {
3456 cover("kernel.rtlil.sigspec.comp_lt");
3457
3458 if (this == &other)
3459 return false;
3460
3461 if (width_ != other.width_)
3462 return width_ < other.width_;
3463
3464 pack();
3465 other.pack();
3466
3467 if (chunks_.size() != other.chunks_.size())
3468 return chunks_.size() < other.chunks_.size();
3469
3470 updhash();
3471 other.updhash();
3472
3473 if (hash_ != other.hash_)
3474 return hash_ < other.hash_;
3475
3476 for (size_t i = 0; i < chunks_.size(); i++)
3477 if (chunks_[i] != other.chunks_[i]) {
3478 cover("kernel.rtlil.sigspec.comp_lt.hash_collision");
3479 return chunks_[i] < other.chunks_[i];
3480 }
3481
3482 cover("kernel.rtlil.sigspec.comp_lt.equal");
3483 return false;
3484 }
3485
3486 bool RTLIL::SigSpec::operator ==(const RTLIL::SigSpec &other) const
3487 {
3488 cover("kernel.rtlil.sigspec.comp_eq");
3489
3490 if (this == &other)
3491 return true;
3492
3493 if (width_ != other.width_)
3494 return false;
3495
3496 pack();
3497 other.pack();
3498
3499 if (chunks_.size() != other.chunks_.size())
3500 return false;
3501
3502 updhash();
3503 other.updhash();
3504
3505 if (hash_ != other.hash_)
3506 return false;
3507
3508 for (size_t i = 0; i < chunks_.size(); i++)
3509 if (chunks_[i] != other.chunks_[i]) {
3510 cover("kernel.rtlil.sigspec.comp_eq.hash_collision");
3511 return false;
3512 }
3513
3514 cover("kernel.rtlil.sigspec.comp_eq.equal");
3515 return true;
3516 }
3517
3518 bool RTLIL::SigSpec::is_wire() const
3519 {
3520 cover("kernel.rtlil.sigspec.is_wire");
3521
3522 pack();
3523 return GetSize(chunks_) == 1 && chunks_[0].wire && chunks_[0].wire->width == width_;
3524 }
3525
3526 bool RTLIL::SigSpec::is_chunk() const
3527 {
3528 cover("kernel.rtlil.sigspec.is_chunk");
3529
3530 pack();
3531 return GetSize(chunks_) == 1;
3532 }
3533
3534 bool RTLIL::SigSpec::is_fully_const() const
3535 {
3536 cover("kernel.rtlil.sigspec.is_fully_const");
3537
3538 pack();
3539 for (auto it = chunks_.begin(); it != chunks_.end(); it++)
3540 if (it->width > 0 && it->wire != NULL)
3541 return false;
3542 return true;
3543 }
3544
3545 bool RTLIL::SigSpec::is_fully_zero() const
3546 {
3547 cover("kernel.rtlil.sigspec.is_fully_zero");
3548
3549 pack();
3550 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
3551 if (it->width > 0 && it->wire != NULL)
3552 return false;
3553 for (size_t i = 0; i < it->data.size(); i++)
3554 if (it->data[i] != RTLIL::State::S0)
3555 return false;
3556 }
3557 return true;
3558 }
3559
3560 bool RTLIL::SigSpec::is_fully_ones() const
3561 {
3562 cover("kernel.rtlil.sigspec.is_fully_ones");
3563
3564 pack();
3565 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
3566 if (it->width > 0 && it->wire != NULL)
3567 return false;
3568 for (size_t i = 0; i < it->data.size(); i++)
3569 if (it->data[i] != RTLIL::State::S1)
3570 return false;
3571 }
3572 return true;
3573 }
3574
3575 bool RTLIL::SigSpec::is_fully_def() const
3576 {
3577 cover("kernel.rtlil.sigspec.is_fully_def");
3578
3579 pack();
3580 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
3581 if (it->width > 0 && it->wire != NULL)
3582 return false;
3583 for (size_t i = 0; i < it->data.size(); i++)
3584 if (it->data[i] != RTLIL::State::S0 && it->data[i] != RTLIL::State::S1)
3585 return false;
3586 }
3587 return true;
3588 }
3589
3590 bool RTLIL::SigSpec::is_fully_undef() const
3591 {
3592 cover("kernel.rtlil.sigspec.is_fully_undef");
3593
3594 pack();
3595 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
3596 if (it->width > 0 && it->wire != NULL)
3597 return false;
3598 for (size_t i = 0; i < it->data.size(); i++)
3599 if (it->data[i] != RTLIL::State::Sx && it->data[i] != RTLIL::State::Sz)
3600 return false;
3601 }
3602 return true;
3603 }
3604
3605 bool RTLIL::SigSpec::has_const() const
3606 {
3607 cover("kernel.rtlil.sigspec.has_const");
3608
3609 pack();
3610 for (auto it = chunks_.begin(); it != chunks_.end(); it++)
3611 if (it->width > 0 && it->wire == NULL)
3612 return true;
3613 return false;
3614 }
3615
3616 bool RTLIL::SigSpec::has_marked_bits() const
3617 {
3618 cover("kernel.rtlil.sigspec.has_marked_bits");
3619
3620 pack();
3621 for (auto it = chunks_.begin(); it != chunks_.end(); it++)
3622 if (it->width > 0 && it->wire == NULL) {
3623 for (size_t i = 0; i < it->data.size(); i++)
3624 if (it->data[i] == RTLIL::State::Sm)
3625 return true;
3626 }
3627 return false;
3628 }
3629
3630 bool RTLIL::SigSpec::as_bool() const
3631 {
3632 cover("kernel.rtlil.sigspec.as_bool");
3633
3634 pack();
3635 log_assert(is_fully_const() && GetSize(chunks_) <= 1);
3636 if (width_)
3637 return RTLIL::Const(chunks_[0].data).as_bool();
3638 return false;
3639 }
3640
3641 int RTLIL::SigSpec::as_int(bool is_signed) const
3642 {
3643 cover("kernel.rtlil.sigspec.as_int");
3644
3645 pack();
3646 log_assert(is_fully_const() && GetSize(chunks_) <= 1);
3647 if (width_)
3648 return RTLIL::Const(chunks_[0].data).as_int(is_signed);
3649 return 0;
3650 }
3651
3652 std::string RTLIL::SigSpec::as_string() const
3653 {
3654 cover("kernel.rtlil.sigspec.as_string");
3655
3656 pack();
3657 std::string str;
3658 for (size_t i = chunks_.size(); i > 0; i--) {
3659 const RTLIL::SigChunk &chunk = chunks_[i-1];
3660 if (chunk.wire != NULL)
3661 for (int j = 0; j < chunk.width; j++)
3662 str += "?";
3663 else
3664 str += RTLIL::Const(chunk.data).as_string();
3665 }
3666 return str;
3667 }
3668
3669 RTLIL::Const RTLIL::SigSpec::as_const() const
3670 {
3671 cover("kernel.rtlil.sigspec.as_const");
3672
3673 pack();
3674 log_assert(is_fully_const() && GetSize(chunks_) <= 1);
3675 if (width_)
3676 return chunks_[0].data;
3677 return RTLIL::Const();
3678 }
3679
3680 RTLIL::Wire *RTLIL::SigSpec::as_wire() const
3681 {
3682 cover("kernel.rtlil.sigspec.as_wire");
3683
3684 pack();
3685 log_assert(is_wire());
3686 return chunks_[0].wire;
3687 }
3688
3689 RTLIL::SigChunk RTLIL::SigSpec::as_chunk() const
3690 {
3691 cover("kernel.rtlil.sigspec.as_chunk");
3692
3693 pack();
3694 log_assert(is_chunk());
3695 return chunks_[0];
3696 }
3697
3698 RTLIL::SigBit RTLIL::SigSpec::as_bit() const
3699 {
3700 cover("kernel.rtlil.sigspec.as_bit");
3701
3702 log_assert(width_ == 1);
3703 if (packed())
3704 return RTLIL::SigBit(*chunks_.begin());
3705 else
3706 return bits_[0];
3707 }
3708
3709 bool RTLIL::SigSpec::match(std::string pattern) const
3710 {
3711 cover("kernel.rtlil.sigspec.match");
3712
3713 pack();
3714 std::string str = as_string();
3715 log_assert(pattern.size() == str.size());
3716
3717 for (size_t i = 0; i < pattern.size(); i++) {
3718 if (pattern[i] == ' ')
3719 continue;
3720 if (pattern[i] == '*') {
3721 if (str[i] != 'z' && str[i] != 'x')
3722 return false;
3723 continue;
3724 }
3725 if (pattern[i] != str[i])
3726 return false;
3727 }
3728
3729 return true;
3730 }
3731
3732 std::set<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_set() const
3733 {
3734 cover("kernel.rtlil.sigspec.to_sigbit_set");
3735
3736 pack();
3737 std::set<RTLIL::SigBit> sigbits;
3738 for (auto &c : chunks_)
3739 for (int i = 0; i < c.width; i++)
3740 sigbits.insert(RTLIL::SigBit(c, i));
3741 return sigbits;
3742 }
3743
3744 pool<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_pool() const
3745 {
3746 cover("kernel.rtlil.sigspec.to_sigbit_pool");
3747
3748 pack();
3749 pool<RTLIL::SigBit> sigbits;
3750 for (auto &c : chunks_)
3751 for (int i = 0; i < c.width; i++)
3752 sigbits.insert(RTLIL::SigBit(c, i));
3753 return sigbits;
3754 }
3755
3756 std::vector<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_vector() const
3757 {
3758 cover("kernel.rtlil.sigspec.to_sigbit_vector");
3759
3760 unpack();
3761 return bits_;
3762 }
3763
3764 std::map<RTLIL::SigBit, RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_map(const RTLIL::SigSpec &other) const
3765 {
3766 cover("kernel.rtlil.sigspec.to_sigbit_map");
3767
3768 unpack();
3769 other.unpack();
3770
3771 log_assert(width_ == other.width_);
3772
3773 std::map<RTLIL::SigBit, RTLIL::SigBit> new_map;
3774 for (int i = 0; i < width_; i++)
3775 new_map[bits_[i]] = other.bits_[i];
3776
3777 return new_map;
3778 }
3779
3780 dict<RTLIL::SigBit, RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_dict(const RTLIL::SigSpec &other) const
3781 {
3782 cover("kernel.rtlil.sigspec.to_sigbit_dict");
3783
3784 unpack();
3785 other.unpack();
3786
3787 log_assert(width_ == other.width_);
3788
3789 dict<RTLIL::SigBit, RTLIL::SigBit> new_map;
3790 for (int i = 0; i < width_; i++)
3791 new_map[bits_[i]] = other.bits_[i];
3792
3793 return new_map;
3794 }
3795
3796 static void sigspec_parse_split(std::vector<std::string> &tokens, const std::string &text, char sep)
3797 {
3798 size_t start = 0, end = 0;
3799 while ((end = text.find(sep, start)) != std::string::npos) {
3800 tokens.push_back(text.substr(start, end - start));
3801 start = end + 1;
3802 }
3803 tokens.push_back(text.substr(start));
3804 }
3805
3806 static int sigspec_parse_get_dummy_line_num()
3807 {
3808 return 0;
3809 }
3810
3811 bool RTLIL::SigSpec::parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str)
3812 {
3813 cover("kernel.rtlil.sigspec.parse");
3814
3815 AST::current_filename = "input";
3816 AST::use_internal_line_num();
3817 AST::set_line_num(0);
3818
3819 std::vector<std::string> tokens;
3820 sigspec_parse_split(tokens, str, ',');
3821
3822 sig = RTLIL::SigSpec();
3823 for (int tokidx = int(tokens.size())-1; tokidx >= 0; tokidx--)
3824 {
3825 std::string netname = tokens[tokidx];
3826 std::string indices;
3827
3828 if (netname.size() == 0)
3829 continue;
3830
3831 if (('0' <= netname[0] && netname[0] <= '9') || netname[0] == '\'') {
3832 cover("kernel.rtlil.sigspec.parse.const");
3833 AST::get_line_num = sigspec_parse_get_dummy_line_num;
3834 AST::AstNode *ast = VERILOG_FRONTEND::const2ast(netname);
3835 if (ast == NULL)
3836 return false;
3837 sig.append(RTLIL::Const(ast->bits));
3838 delete ast;
3839 continue;
3840 }
3841
3842 if (module == NULL)
3843 return false;
3844
3845 cover("kernel.rtlil.sigspec.parse.net");
3846
3847 if (netname[0] != '$' && netname[0] != '\\')
3848 netname = "\\" + netname;
3849
3850 if (module->wires_.count(netname) == 0) {
3851 size_t indices_pos = netname.size()-1;
3852 if (indices_pos > 2 && netname[indices_pos] == ']')
3853 {
3854 indices_pos--;
3855 while (indices_pos > 0 && ('0' <= netname[indices_pos] && netname[indices_pos] <= '9')) indices_pos--;
3856 if (indices_pos > 0 && netname[indices_pos] == ':') {
3857 indices_pos--;
3858 while (indices_pos > 0 && ('0' <= netname[indices_pos] && netname[indices_pos] <= '9')) indices_pos--;
3859 }
3860 if (indices_pos > 0 && netname[indices_pos] == '[') {
3861 indices = netname.substr(indices_pos);
3862 netname = netname.substr(0, indices_pos);
3863 }
3864 }
3865 }
3866
3867 if (module->wires_.count(netname) == 0)
3868 return false;
3869
3870 RTLIL::Wire *wire = module->wires_.at(netname);
3871 if (!indices.empty()) {
3872 std::vector<std::string> index_tokens;
3873 sigspec_parse_split(index_tokens, indices.substr(1, indices.size()-2), ':');
3874 if (index_tokens.size() == 1) {
3875 cover("kernel.rtlil.sigspec.parse.bit_sel");
3876 int a = atoi(index_tokens.at(0).c_str());
3877 if (a < 0 || a >= wire->width)
3878 return false;
3879 sig.append(RTLIL::SigSpec(wire, a));
3880 } else {
3881 cover("kernel.rtlil.sigspec.parse.part_sel");
3882 int a = atoi(index_tokens.at(0).c_str());
3883 int b = atoi(index_tokens.at(1).c_str());
3884 if (a > b) {
3885 int tmp = a;
3886 a = b, b = tmp;
3887 }
3888 if (a < 0 || a >= wire->width)
3889 return false;
3890 if (b < 0 || b >= wire->width)
3891 return false;
3892 sig.append(RTLIL::SigSpec(wire, a, b-a+1));
3893 }
3894 } else
3895 sig.append(wire);
3896 }
3897
3898 return true;
3899 }
3900
3901 bool RTLIL::SigSpec::parse_sel(RTLIL::SigSpec &sig, RTLIL::Design *design, RTLIL::Module *module, std::string str)
3902 {
3903 if (str.empty() || str[0] != '@')
3904 return parse(sig, module, str);
3905
3906 cover("kernel.rtlil.sigspec.parse.sel");
3907
3908 str = RTLIL::escape_id(str.substr(1));
3909 if (design->selection_vars.count(str) == 0)
3910 return false;
3911
3912 sig = RTLIL::SigSpec();
3913 RTLIL::Selection &sel = design->selection_vars.at(str);
3914 for (auto &it : module->wires_)
3915 if (sel.selected_member(module->name, it.first))
3916 sig.append(it.second);
3917
3918 return true;
3919 }
3920
3921 bool RTLIL::SigSpec::parse_rhs(const RTLIL::SigSpec &lhs, RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str)
3922 {
3923 if (str == "0") {
3924 cover("kernel.rtlil.sigspec.parse.rhs_zeros");
3925 sig = RTLIL::SigSpec(RTLIL::State::S0, lhs.width_);
3926 return true;
3927 }
3928
3929 if (str == "~0") {
3930 cover("kernel.rtlil.sigspec.parse.rhs_ones");
3931 sig = RTLIL::SigSpec(RTLIL::State::S1, lhs.width_);
3932 return true;
3933 }
3934
3935 if (lhs.chunks_.size() == 1) {
3936 char *p = (char*)str.c_str(), *endptr;
3937 long int val = strtol(p, &endptr, 10);
3938 if (endptr && endptr != p && *endptr == 0) {
3939 sig = RTLIL::SigSpec(val, lhs.width_);
3940 cover("kernel.rtlil.sigspec.parse.rhs_dec");
3941 return true;
3942 }
3943 }
3944
3945 return parse(sig, module, str);
3946 }
3947
3948 RTLIL::CaseRule::~CaseRule()
3949 {
3950 for (auto it = switches.begin(); it != switches.end(); it++)
3951 delete *it;
3952 }
3953
3954 bool RTLIL::CaseRule::empty() const
3955 {
3956 return actions.empty() && switches.empty();
3957 }
3958
3959 RTLIL::CaseRule *RTLIL::CaseRule::clone() const
3960 {
3961 RTLIL::CaseRule *new_caserule = new RTLIL::CaseRule;
3962 new_caserule->compare = compare;
3963 new_caserule->actions = actions;
3964 for (auto &it : switches)
3965 new_caserule->switches.push_back(it->clone());
3966 return new_caserule;
3967 }
3968
3969 RTLIL::SwitchRule::~SwitchRule()
3970 {
3971 for (auto it = cases.begin(); it != cases.end(); it++)
3972 delete *it;
3973 }
3974
3975 bool RTLIL::SwitchRule::empty() const
3976 {
3977 return cases.empty();
3978 }
3979
3980 RTLIL::SwitchRule *RTLIL::SwitchRule::clone() const
3981 {
3982 RTLIL::SwitchRule *new_switchrule = new RTLIL::SwitchRule;
3983 new_switchrule->signal = signal;
3984 new_switchrule->attributes = attributes;
3985 for (auto &it : cases)
3986 new_switchrule->cases.push_back(it->clone());
3987 return new_switchrule;
3988
3989 }
3990
3991 RTLIL::SyncRule *RTLIL::SyncRule::clone() const
3992 {
3993 RTLIL::SyncRule *new_syncrule = new RTLIL::SyncRule;
3994 new_syncrule->type = type;
3995 new_syncrule->signal = signal;
3996 new_syncrule->actions = actions;
3997 return new_syncrule;
3998 }
3999
4000 RTLIL::Process::~Process()
4001 {
4002 for (auto it = syncs.begin(); it != syncs.end(); it++)
4003 delete *it;
4004 }
4005
4006 RTLIL::Process *RTLIL::Process::clone() const
4007 {
4008 RTLIL::Process *new_proc = new RTLIL::Process;
4009
4010 new_proc->name = name;
4011 new_proc->attributes = attributes;
4012
4013 RTLIL::CaseRule *rc_ptr = root_case.clone();
4014 new_proc->root_case = *rc_ptr;
4015 rc_ptr->switches.clear();
4016 delete rc_ptr;
4017
4018 for (auto &it : syncs)
4019 new_proc->syncs.push_back(it->clone());
4020
4021 return new_proc;
4022 }
4023
4024 #ifdef WITH_PYTHON
4025 RTLIL::Memory::~Memory()
4026 {
4027 RTLIL::Memory::get_all_memorys()->erase(hashidx_);
4028 }
4029 static std::map<unsigned int, RTLIL::Memory*> all_memorys;
4030 std::map<unsigned int, RTLIL::Memory*> *RTLIL::Memory::get_all_memorys(void)
4031 {
4032 return &all_memorys;
4033 }
4034 #endif
4035 YOSYS_NAMESPACE_END