2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include "kernel/yosys.h"
21 #include "kernel/macc.h"
22 #include "frontends/verilog/verilog_frontend.h"
23 #include "backends/ilang/ilang_backend.h"
30 std::vector
<int> RTLIL::IdString::global_refcount_storage_
;
31 std::vector
<char*> RTLIL::IdString::global_id_storage_
;
32 std::map
<char*, int, RTLIL::IdString::char_ptr_cmp
> RTLIL::IdString::global_id_index_
;
33 std::vector
<int> RTLIL::IdString::global_free_idx_list_
;
37 flags
= RTLIL::CONST_FLAG_NONE
;
40 RTLIL::Const::Const(std::string str
)
42 flags
= RTLIL::CONST_FLAG_STRING
;
43 for (int i
= str
.size()-1; i
>= 0; i
--) {
44 unsigned char ch
= str
[i
];
45 for (int j
= 0; j
< 8; j
++) {
46 bits
.push_back((ch
& 1) != 0 ? RTLIL::S1
: RTLIL::S0
);
52 RTLIL::Const::Const(int val
, int width
)
54 flags
= RTLIL::CONST_FLAG_NONE
;
55 for (int i
= 0; i
< width
; i
++) {
56 bits
.push_back((val
& 1) != 0 ? RTLIL::S1
: RTLIL::S0
);
61 RTLIL::Const::Const(RTLIL::State bit
, int width
)
63 flags
= RTLIL::CONST_FLAG_NONE
;
64 for (int i
= 0; i
< width
; i
++)
68 RTLIL::Const::Const(const std::vector
<bool> &bits
)
70 flags
= RTLIL::CONST_FLAG_NONE
;
72 this->bits
.push_back(b
? RTLIL::S1
: RTLIL::S0
);
75 bool RTLIL::Const::operator <(const RTLIL::Const
&other
) const
77 if (bits
.size() != other
.bits
.size())
78 return bits
.size() < other
.bits
.size();
79 for (size_t i
= 0; i
< bits
.size(); i
++)
80 if (bits
[i
] != other
.bits
[i
])
81 return bits
[i
] < other
.bits
[i
];
85 bool RTLIL::Const::operator ==(const RTLIL::Const
&other
) const
87 return bits
== other
.bits
;
90 bool RTLIL::Const::operator !=(const RTLIL::Const
&other
) const
92 return bits
!= other
.bits
;
95 bool RTLIL::Const::as_bool() const
97 for (size_t i
= 0; i
< bits
.size(); i
++)
98 if (bits
[i
] == RTLIL::S1
)
103 int RTLIL::Const::as_int(bool is_signed
) const
106 for (size_t i
= 0; i
< bits
.size() && i
< 32; i
++)
107 if (bits
[i
] == RTLIL::S1
)
109 if (is_signed
&& bits
.back() == RTLIL::S1
)
110 for (size_t i
= bits
.size(); i
< 32; i
++)
115 std::string
RTLIL::Const::as_string() const
118 for (size_t i
= bits
.size(); i
> 0; i
--)
120 case S0
: ret
+= "0"; break;
121 case S1
: ret
+= "1"; break;
122 case Sx
: ret
+= "x"; break;
123 case Sz
: ret
+= "z"; break;
124 case Sa
: ret
+= "-"; break;
125 case Sm
: ret
+= "m"; break;
130 std::string
RTLIL::Const::decode_string() const
133 std::vector
<char> string_chars
;
134 for (int i
= 0; i
< int (bits
.size()); i
+= 8) {
136 for (int j
= 0; j
< 8 && i
+ j
< int (bits
.size()); j
++)
137 if (bits
[i
+ j
] == RTLIL::State::S1
)
140 string_chars
.push_back(ch
);
142 for (int i
= int (string_chars
.size()) - 1; i
>= 0; i
--)
143 string
+= string_chars
[i
];
147 bool RTLIL::Selection::selected_module(RTLIL::IdString mod_name
) const
151 if (selected_modules
.count(mod_name
) > 0)
153 if (selected_members
.count(mod_name
) > 0)
158 bool RTLIL::Selection::selected_whole_module(RTLIL::IdString mod_name
) const
162 if (selected_modules
.count(mod_name
) > 0)
167 bool RTLIL::Selection::selected_member(RTLIL::IdString mod_name
, RTLIL::IdString memb_name
) const
171 if (selected_modules
.count(mod_name
) > 0)
173 if (selected_members
.count(mod_name
) > 0)
174 if (selected_members
.at(mod_name
).count(memb_name
) > 0)
179 void RTLIL::Selection::optimize(RTLIL::Design
*design
)
181 if (full_selection
) {
182 selected_modules
.clear();
183 selected_members
.clear();
187 std::vector
<RTLIL::IdString
> del_list
, add_list
;
190 for (auto mod_name
: selected_modules
) {
191 if (design
->modules_
.count(mod_name
) == 0)
192 del_list
.push_back(mod_name
);
193 selected_members
.erase(mod_name
);
195 for (auto mod_name
: del_list
)
196 selected_modules
.erase(mod_name
);
199 for (auto &it
: selected_members
)
200 if (design
->modules_
.count(it
.first
) == 0)
201 del_list
.push_back(it
.first
);
202 for (auto mod_name
: del_list
)
203 selected_members
.erase(mod_name
);
205 for (auto &it
: selected_members
) {
207 for (auto memb_name
: it
.second
)
208 if (design
->modules_
[it
.first
]->count_id(memb_name
) == 0)
209 del_list
.push_back(memb_name
);
210 for (auto memb_name
: del_list
)
211 it
.second
.erase(memb_name
);
216 for (auto &it
: selected_members
)
217 if (it
.second
.size() == 0)
218 del_list
.push_back(it
.first
);
219 else if (it
.second
.size() == design
->modules_
[it
.first
]->wires_
.size() + design
->modules_
[it
.first
]->memories
.size() +
220 design
->modules_
[it
.first
]->cells_
.size() + design
->modules_
[it
.first
]->processes
.size())
221 add_list
.push_back(it
.first
);
222 for (auto mod_name
: del_list
)
223 selected_members
.erase(mod_name
);
224 for (auto mod_name
: add_list
) {
225 selected_members
.erase(mod_name
);
226 selected_modules
.insert(mod_name
);
229 if (selected_modules
.size() == design
->modules_
.size()) {
230 full_selection
= true;
231 selected_modules
.clear();
232 selected_members
.clear();
236 RTLIL::Design::Design()
238 refcount_modules_
= 0;
239 selection_stack
.push_back(RTLIL::Selection());
242 RTLIL::Design::~Design()
244 for (auto it
= modules_
.begin(); it
!= modules_
.end(); it
++)
248 RTLIL::ObjRange
<RTLIL::Module
*> RTLIL::Design::modules()
250 return RTLIL::ObjRange
<RTLIL::Module
*>(&modules_
, &refcount_modules_
);
253 RTLIL::Module
*RTLIL::Design::module(RTLIL::IdString name
)
255 return modules_
.count(name
) ? modules_
.at(name
) : NULL
;
258 void RTLIL::Design::add(RTLIL::Module
*module
)
260 log_assert(modules_
.count(module
->name
) == 0);
261 log_assert(refcount_modules_
== 0);
262 modules_
[module
->name
] = module
;
263 module
->design
= this;
265 for (auto mon
: monitors
)
266 mon
->notify_module_add(module
);
269 RTLIL::Module
*RTLIL::Design::addModule(RTLIL::IdString name
)
271 log_assert(modules_
.count(name
) == 0);
272 log_assert(refcount_modules_
== 0);
274 RTLIL::Module
*module
= new RTLIL::Module
;
275 modules_
[name
] = module
;
276 module
->design
= this;
279 for (auto mon
: monitors
)
280 mon
->notify_module_add(module
);
285 void RTLIL::Design::scratchpad_unset(std::string varname
)
287 scratchpad
.erase(varname
);
290 void RTLIL::Design::scratchpad_set_int(std::string varname
, int value
)
292 scratchpad
[varname
] = stringf("%d", value
);
295 void RTLIL::Design::scratchpad_set_bool(std::string varname
, bool value
)
297 scratchpad
[varname
] = value
? "true" : "false";
300 void RTLIL::Design::scratchpad_set_string(std::string varname
, std::string value
)
302 scratchpad
[varname
] = value
;
305 int RTLIL::Design::scratchpad_get_int(std::string varname
, int default_value
) const
307 if (scratchpad
.count(varname
) == 0)
308 return default_value
;
310 std::string str
= scratchpad
.at(varname
);
312 if (str
== "0" || str
== "false")
315 if (str
== "1" || str
== "true")
318 char *endptr
= nullptr;
319 long int parsed_value
= strtol(str
.c_str(), &endptr
, 10);
320 return *endptr
? default_value
: parsed_value
;
323 bool RTLIL::Design::scratchpad_get_bool(std::string varname
, bool default_value
) const
325 if (scratchpad
.count(varname
) == 0)
326 return default_value
;
328 std::string str
= scratchpad
.at(varname
);
330 if (str
== "0" || str
== "false")
333 if (str
== "1" || str
== "true")
336 return default_value
;
339 std::string
RTLIL::Design::scratchpad_get_string(std::string varname
, std::string default_value
) const
341 if (scratchpad
.count(varname
) == 0)
342 return default_value
;
343 return scratchpad
.at(varname
);
346 void RTLIL::Design::remove(RTLIL::Module
*module
)
348 for (auto mon
: monitors
)
349 mon
->notify_module_del(module
);
351 log_assert(modules_
.at(module
->name
) == module
);
352 modules_
.erase(module
->name
);
356 void RTLIL::Design::check()
359 for (auto &it
: modules_
) {
360 log_assert(this == it
.second
->design
);
361 log_assert(it
.first
== it
.second
->name
);
362 log_assert(!it
.first
.empty());
368 void RTLIL::Design::optimize()
370 for (auto &it
: modules_
)
371 it
.second
->optimize();
372 for (auto &it
: selection_stack
)
374 for (auto &it
: selection_vars
)
375 it
.second
.optimize(this);
378 bool RTLIL::Design::selected_module(RTLIL::IdString mod_name
) const
380 if (!selected_active_module
.empty() && mod_name
!= selected_active_module
)
382 if (selection_stack
.size() == 0)
384 return selection_stack
.back().selected_module(mod_name
);
387 bool RTLIL::Design::selected_whole_module(RTLIL::IdString mod_name
) const
389 if (!selected_active_module
.empty() && mod_name
!= selected_active_module
)
391 if (selection_stack
.size() == 0)
393 return selection_stack
.back().selected_whole_module(mod_name
);
396 bool RTLIL::Design::selected_member(RTLIL::IdString mod_name
, RTLIL::IdString memb_name
) const
398 if (!selected_active_module
.empty() && mod_name
!= selected_active_module
)
400 if (selection_stack
.size() == 0)
402 return selection_stack
.back().selected_member(mod_name
, memb_name
);
405 bool RTLIL::Design::selected_module(RTLIL::Module
*mod
) const
407 return selected_module(mod
->name
);
410 bool RTLIL::Design::selected_whole_module(RTLIL::Module
*mod
) const
412 return selected_whole_module(mod
->name
);
415 std::vector
<RTLIL::Module
*> RTLIL::Design::selected_modules() const
417 std::vector
<RTLIL::Module
*> result
;
418 result
.reserve(modules_
.size());
419 for (auto &it
: modules_
)
420 if (selected_module(it
.first
))
421 result
.push_back(it
.second
);
425 std::vector
<RTLIL::Module
*> RTLIL::Design::selected_whole_modules() const
427 std::vector
<RTLIL::Module
*> result
;
428 result
.reserve(modules_
.size());
429 for (auto &it
: modules_
)
430 if (selected_whole_module(it
.first
))
431 result
.push_back(it
.second
);
435 std::vector
<RTLIL::Module
*> RTLIL::Design::selected_whole_modules_warn() const
437 std::vector
<RTLIL::Module
*> result
;
438 result
.reserve(modules_
.size());
439 for (auto &it
: modules_
)
440 if (selected_whole_module(it
.first
))
441 result
.push_back(it
.second
);
442 else if (selected_module(it
.first
))
443 log_warning("Ignoring partially selected module %s.\n", log_id(it
.first
));
447 RTLIL::Module::Module()
454 RTLIL::Module::~Module()
456 for (auto it
= wires_
.begin(); it
!= wires_
.end(); it
++)
458 for (auto it
= memories
.begin(); it
!= memories
.end(); it
++)
460 for (auto it
= cells_
.begin(); it
!= cells_
.end(); it
++)
462 for (auto it
= processes
.begin(); it
!= processes
.end(); it
++)
466 RTLIL::IdString
RTLIL::Module::derive(RTLIL::Design
*, std::map
<RTLIL::IdString
, RTLIL::Const
>)
468 log_error("Module `%s' is used with parameters but is not parametric!\n", id2cstr(name
));
471 size_t RTLIL::Module::count_id(RTLIL::IdString id
)
473 return wires_
.count(id
) + memories
.count(id
) + cells_
.count(id
) + processes
.count(id
);
478 struct InternalCellChecker
480 RTLIL::Module
*module
;
482 std::set
<RTLIL::IdString
> expected_params
, expected_ports
;
484 InternalCellChecker(RTLIL::Module
*module
, RTLIL::Cell
*cell
) : module(module
), cell(cell
) { }
486 void error(int linenr
)
488 std::stringstream buf
;
489 ILANG_BACKEND::dump_cell(buf
, " ", cell
);
491 log_error("Found error in internal cell %s%s%s (%s) at %s:%d:\n%s",
492 module
? module
->name
.c_str() : "", module
? "." : "",
493 cell
->name
.c_str(), cell
->type
.c_str(), __FILE__
, linenr
, buf
.str().c_str());
496 int param(const char *name
)
498 if (cell
->parameters
.count(name
) == 0)
500 expected_params
.insert(name
);
501 return cell
->parameters
.at(name
).as_int();
504 int param_bool(const char *name
)
507 if (cell
->parameters
.at(name
).bits
.size() > 32)
509 if (v
!= 0 && v
!= 1)
514 void param_bits(const char *name
, int width
)
517 if (int(cell
->parameters
.at(name
).bits
.size()) != width
)
521 void port(const char *name
, int width
)
523 if (!cell
->hasPort(name
))
525 if (cell
->getPort(name
).size() != width
)
527 expected_ports
.insert(name
);
530 void check_expected(bool check_matched_sign
= true)
532 for (auto ¶
: cell
->parameters
)
533 if (expected_params
.count(para
.first
) == 0)
535 for (auto &conn
: cell
->connections())
536 if (expected_ports
.count(conn
.first
) == 0)
539 if (expected_params
.count("\\A_SIGNED") != 0 && expected_params
.count("\\B_SIGNED") && check_matched_sign
) {
540 bool a_is_signed
= param("\\A_SIGNED") != 0;
541 bool b_is_signed
= param("\\B_SIGNED") != 0;
542 if (a_is_signed
!= b_is_signed
)
547 void check_gate(const char *ports
)
549 if (cell
->parameters
.size() != 0)
552 for (const char *p
= ports
; *p
; p
++) {
553 char portname
[3] = { '\\', *p
, 0 };
554 if (!cell
->hasPort(portname
))
556 if (cell
->getPort(portname
).size() != 1)
560 for (auto &conn
: cell
->connections()) {
561 if (conn
.first
.size() != 2 || conn
.first
[0] != '\\')
563 if (strchr(ports
, conn
.first
[1]) == NULL
)
570 if (cell
->type
.substr(0, 1) != "$" || cell
->type
.substr(0, 3) == "$__" || cell
->type
.substr(0, 8) == "$paramod" ||
571 cell
->type
.substr(0, 9) == "$verific$" || cell
->type
.substr(0, 7) == "$array:" || cell
->type
.substr(0, 8) == "$extern:")
574 if (cell
->type
.in("$not", "$pos", "$neg")) {
575 param_bool("\\A_SIGNED");
576 port("\\A", param("\\A_WIDTH"));
577 port("\\Y", param("\\Y_WIDTH"));
582 if (cell
->type
.in("$and", "$or", "$xor", "$xnor")) {
583 param_bool("\\A_SIGNED");
584 param_bool("\\B_SIGNED");
585 port("\\A", param("\\A_WIDTH"));
586 port("\\B", param("\\B_WIDTH"));
587 port("\\Y", param("\\Y_WIDTH"));
592 if (cell
->type
.in("$reduce_and", "$reduce_or", "$reduce_xor", "$reduce_xnor", "$reduce_bool")) {
593 param_bool("\\A_SIGNED");
594 port("\\A", param("\\A_WIDTH"));
595 port("\\Y", param("\\Y_WIDTH"));
600 if (cell
->type
.in("$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx")) {
601 param_bool("\\A_SIGNED");
602 param_bool("\\B_SIGNED");
603 port("\\A", param("\\A_WIDTH"));
604 port("\\B", param("\\B_WIDTH"));
605 port("\\Y", param("\\Y_WIDTH"));
606 check_expected(false);
610 if (cell
->type
.in("$lt", "$le", "$eq", "$ne", "$eqx", "$nex", "$ge", "$gt")) {
611 param_bool("\\A_SIGNED");
612 param_bool("\\B_SIGNED");
613 port("\\A", param("\\A_WIDTH"));
614 port("\\B", param("\\B_WIDTH"));
615 port("\\Y", param("\\Y_WIDTH"));
620 if (cell
->type
.in("$add", "$sub", "$mul", "$div", "$mod", "$pow")) {
621 param_bool("\\A_SIGNED");
622 param_bool("\\B_SIGNED");
623 port("\\A", param("\\A_WIDTH"));
624 port("\\B", param("\\B_WIDTH"));
625 port("\\Y", param("\\Y_WIDTH"));
626 check_expected(cell
->type
!= "$pow");
630 if (cell
->type
== "$fa") {
631 port("\\A", param("\\WIDTH"));
632 port("\\B", param("\\WIDTH"));
633 port("\\C", param("\\WIDTH"));
634 port("\\X", param("\\WIDTH"));
635 port("\\Y", param("\\WIDTH"));
640 if (cell
->type
== "$lcu") {
641 port("\\P", param("\\WIDTH"));
642 port("\\G", param("\\WIDTH"));
644 port("\\CO", param("\\WIDTH"));
649 if (cell
->type
== "$alu") {
650 param_bool("\\A_SIGNED");
651 param_bool("\\B_SIGNED");
652 port("\\A", param("\\A_WIDTH"));
653 port("\\B", param("\\B_WIDTH"));
656 port("\\X", param("\\Y_WIDTH"));
657 port("\\Y", param("\\Y_WIDTH"));
658 port("\\CO", param("\\Y_WIDTH"));
663 if (cell
->type
== "$macc") {
665 param("\\CONFIG_WIDTH");
666 port("\\A", param("\\A_WIDTH"));
667 port("\\B", param("\\B_WIDTH"));
668 port("\\Y", param("\\Y_WIDTH"));
670 Macc().from_cell(cell
);
674 if (cell
->type
== "$logic_not") {
675 param_bool("\\A_SIGNED");
676 port("\\A", param("\\A_WIDTH"));
677 port("\\Y", param("\\Y_WIDTH"));
682 if (cell
->type
== "$logic_and" || cell
->type
== "$logic_or") {
683 param_bool("\\A_SIGNED");
684 param_bool("\\B_SIGNED");
685 port("\\A", param("\\A_WIDTH"));
686 port("\\B", param("\\B_WIDTH"));
687 port("\\Y", param("\\Y_WIDTH"));
688 check_expected(false);
692 if (cell
->type
== "$slice") {
694 port("\\A", param("\\A_WIDTH"));
695 port("\\Y", param("\\Y_WIDTH"));
696 if (param("\\OFFSET") + param("\\Y_WIDTH") > param("\\A_WIDTH"))
702 if (cell
->type
== "$concat") {
703 port("\\A", param("\\A_WIDTH"));
704 port("\\B", param("\\B_WIDTH"));
705 port("\\Y", param("\\A_WIDTH") + param("\\B_WIDTH"));
710 if (cell
->type
== "$mux") {
711 port("\\A", param("\\WIDTH"));
712 port("\\B", param("\\WIDTH"));
714 port("\\Y", param("\\WIDTH"));
719 if (cell
->type
== "$pmux") {
720 port("\\A", param("\\WIDTH"));
721 port("\\B", param("\\WIDTH") * param("\\S_WIDTH"));
722 port("\\S", param("\\S_WIDTH"));
723 port("\\Y", param("\\WIDTH"));
728 if (cell
->type
== "$lut") {
730 port("\\A", param("\\WIDTH"));
736 if (cell
->type
== "$sr") {
737 param_bool("\\SET_POLARITY");
738 param_bool("\\CLR_POLARITY");
739 port("\\SET", param("\\WIDTH"));
740 port("\\CLR", param("\\WIDTH"));
741 port("\\Q", param("\\WIDTH"));
746 if (cell
->type
== "$dff") {
747 param_bool("\\CLK_POLARITY");
749 port("\\D", param("\\WIDTH"));
750 port("\\Q", param("\\WIDTH"));
755 if (cell
->type
== "$dffe") {
756 param_bool("\\CLK_POLARITY");
757 param_bool("\\EN_POLARITY");
760 port("\\D", param("\\WIDTH"));
761 port("\\Q", param("\\WIDTH"));
766 if (cell
->type
== "$dffsr") {
767 param_bool("\\CLK_POLARITY");
768 param_bool("\\SET_POLARITY");
769 param_bool("\\CLR_POLARITY");
771 port("\\SET", param("\\WIDTH"));
772 port("\\CLR", param("\\WIDTH"));
773 port("\\D", param("\\WIDTH"));
774 port("\\Q", param("\\WIDTH"));
779 if (cell
->type
== "$adff") {
780 param_bool("\\CLK_POLARITY");
781 param_bool("\\ARST_POLARITY");
782 param_bits("\\ARST_VALUE", param("\\WIDTH"));
785 port("\\D", param("\\WIDTH"));
786 port("\\Q", param("\\WIDTH"));
791 if (cell
->type
== "$dlatch") {
792 param_bool("\\EN_POLARITY");
794 port("\\D", param("\\WIDTH"));
795 port("\\Q", param("\\WIDTH"));
800 if (cell
->type
== "$dlatchsr") {
801 param_bool("\\EN_POLARITY");
802 param_bool("\\SET_POLARITY");
803 param_bool("\\CLR_POLARITY");
805 port("\\SET", param("\\WIDTH"));
806 port("\\CLR", param("\\WIDTH"));
807 port("\\D", param("\\WIDTH"));
808 port("\\Q", param("\\WIDTH"));
813 if (cell
->type
== "$fsm") {
815 param_bool("\\CLK_POLARITY");
816 param_bool("\\ARST_POLARITY");
817 param("\\STATE_BITS");
818 param("\\STATE_NUM");
819 param("\\STATE_NUM_LOG2");
820 param("\\STATE_RST");
821 param_bits("\\STATE_TABLE", param("\\STATE_BITS") * param("\\STATE_NUM"));
822 param("\\TRANS_NUM");
823 param_bits("\\TRANS_TABLE", param("\\TRANS_NUM") * (2*param("\\STATE_NUM_LOG2") + param("\\CTRL_IN_WIDTH") + param("\\CTRL_OUT_WIDTH")));
826 port("\\CTRL_IN", param("\\CTRL_IN_WIDTH"));
827 port("\\CTRL_OUT", param("\\CTRL_OUT_WIDTH"));
832 if (cell
->type
== "$memrd") {
834 param_bool("\\CLK_ENABLE");
835 param_bool("\\CLK_POLARITY");
836 param_bool("\\TRANSPARENT");
838 port("\\ADDR", param("\\ABITS"));
839 port("\\DATA", param("\\WIDTH"));
844 if (cell
->type
== "$memwr") {
846 param_bool("\\CLK_ENABLE");
847 param_bool("\\CLK_POLARITY");
850 port("\\EN", param("\\WIDTH"));
851 port("\\ADDR", param("\\ABITS"));
852 port("\\DATA", param("\\WIDTH"));
857 if (cell
->type
== "$mem") {
861 param_bits("\\RD_CLK_ENABLE", param("\\RD_PORTS"));
862 param_bits("\\RD_CLK_POLARITY", param("\\RD_PORTS"));
863 param_bits("\\RD_TRANSPARENT", param("\\RD_PORTS"));
864 param_bits("\\WR_CLK_ENABLE", param("\\WR_PORTS"));
865 param_bits("\\WR_CLK_POLARITY", param("\\WR_PORTS"));
866 port("\\RD_CLK", param("\\RD_PORTS"));
867 port("\\RD_ADDR", param("\\RD_PORTS") * param("\\ABITS"));
868 port("\\RD_DATA", param("\\RD_PORTS") * param("\\WIDTH"));
869 port("\\WR_CLK", param("\\WR_PORTS"));
870 port("\\WR_EN", param("\\WR_PORTS") * param("\\WIDTH"));
871 port("\\WR_ADDR", param("\\WR_PORTS") * param("\\ABITS"));
872 port("\\WR_DATA", param("\\WR_PORTS") * param("\\WIDTH"));
877 if (cell
->type
== "$assert") {
884 if (cell
->type
== "$_BUF_") { check_gate("AY"); return; }
885 if (cell
->type
== "$_NOT_") { check_gate("AY"); return; }
886 if (cell
->type
== "$_AND_") { check_gate("ABY"); return; }
887 if (cell
->type
== "$_NAND_") { check_gate("ABY"); return; }
888 if (cell
->type
== "$_OR_") { check_gate("ABY"); return; }
889 if (cell
->type
== "$_NOR_") { check_gate("ABY"); return; }
890 if (cell
->type
== "$_XOR_") { check_gate("ABY"); return; }
891 if (cell
->type
== "$_XNOR_") { check_gate("ABY"); return; }
892 if (cell
->type
== "$_MUX_") { check_gate("ABSY"); return; }
893 if (cell
->type
== "$_AOI3_") { check_gate("ABCY"); return; }
894 if (cell
->type
== "$_OAI3_") { check_gate("ABCY"); return; }
895 if (cell
->type
== "$_AOI4_") { check_gate("ABCDY"); return; }
896 if (cell
->type
== "$_OAI4_") { check_gate("ABCDY"); return; }
898 if (cell
->type
== "$_SR_NN_") { check_gate("SRQ"); return; }
899 if (cell
->type
== "$_SR_NP_") { check_gate("SRQ"); return; }
900 if (cell
->type
== "$_SR_PN_") { check_gate("SRQ"); return; }
901 if (cell
->type
== "$_SR_PP_") { check_gate("SRQ"); return; }
903 if (cell
->type
== "$_DFF_N_") { check_gate("DQC"); return; }
904 if (cell
->type
== "$_DFF_P_") { check_gate("DQC"); return; }
906 if (cell
->type
== "$_DFFE_NN_") { check_gate("DQCE"); return; }
907 if (cell
->type
== "$_DFFE_NP_") { check_gate("DQCE"); return; }
908 if (cell
->type
== "$_DFFE_PN_") { check_gate("DQCE"); return; }
909 if (cell
->type
== "$_DFFE_PP_") { check_gate("DQCE"); return; }
911 if (cell
->type
== "$_DFF_NN0_") { check_gate("DQCR"); return; }
912 if (cell
->type
== "$_DFF_NN1_") { check_gate("DQCR"); return; }
913 if (cell
->type
== "$_DFF_NP0_") { check_gate("DQCR"); return; }
914 if (cell
->type
== "$_DFF_NP1_") { check_gate("DQCR"); return; }
915 if (cell
->type
== "$_DFF_PN0_") { check_gate("DQCR"); return; }
916 if (cell
->type
== "$_DFF_PN1_") { check_gate("DQCR"); return; }
917 if (cell
->type
== "$_DFF_PP0_") { check_gate("DQCR"); return; }
918 if (cell
->type
== "$_DFF_PP1_") { check_gate("DQCR"); return; }
920 if (cell
->type
== "$_DFFSR_NNN_") { check_gate("CSRDQ"); return; }
921 if (cell
->type
== "$_DFFSR_NNP_") { check_gate("CSRDQ"); return; }
922 if (cell
->type
== "$_DFFSR_NPN_") { check_gate("CSRDQ"); return; }
923 if (cell
->type
== "$_DFFSR_NPP_") { check_gate("CSRDQ"); return; }
924 if (cell
->type
== "$_DFFSR_PNN_") { check_gate("CSRDQ"); return; }
925 if (cell
->type
== "$_DFFSR_PNP_") { check_gate("CSRDQ"); return; }
926 if (cell
->type
== "$_DFFSR_PPN_") { check_gate("CSRDQ"); return; }
927 if (cell
->type
== "$_DFFSR_PPP_") { check_gate("CSRDQ"); return; }
929 if (cell
->type
== "$_DLATCH_N_") { check_gate("EDQ"); return; }
930 if (cell
->type
== "$_DLATCH_P_") { check_gate("EDQ"); return; }
932 if (cell
->type
== "$_DLATCHSR_NNN_") { check_gate("ESRDQ"); return; }
933 if (cell
->type
== "$_DLATCHSR_NNP_") { check_gate("ESRDQ"); return; }
934 if (cell
->type
== "$_DLATCHSR_NPN_") { check_gate("ESRDQ"); return; }
935 if (cell
->type
== "$_DLATCHSR_NPP_") { check_gate("ESRDQ"); return; }
936 if (cell
->type
== "$_DLATCHSR_PNN_") { check_gate("ESRDQ"); return; }
937 if (cell
->type
== "$_DLATCHSR_PNP_") { check_gate("ESRDQ"); return; }
938 if (cell
->type
== "$_DLATCHSR_PPN_") { check_gate("ESRDQ"); return; }
939 if (cell
->type
== "$_DLATCHSR_PPP_") { check_gate("ESRDQ"); return; }
947 void RTLIL::Module::check()
950 std::vector
<bool> ports_declared
;
951 for (auto &it
: wires_
) {
952 log_assert(this == it
.second
->module
);
953 log_assert(it
.first
== it
.second
->name
);
954 log_assert(!it
.first
.empty());
955 log_assert(it
.second
->width
>= 0);
956 log_assert(it
.second
->port_id
>= 0);
957 for (auto &it2
: it
.second
->attributes
)
958 log_assert(!it2
.first
.empty());
959 if (it
.second
->port_id
) {
960 log_assert(GetSize(ports
) >= it
.second
->port_id
);
961 log_assert(ports
.at(it
.second
->port_id
-1) == it
.first
);
962 log_assert(it
.second
->port_input
|| it
.second
->port_output
);
963 if (GetSize(ports_declared
) < it
.second
->port_id
)
964 ports_declared
.resize(it
.second
->port_id
);
965 log_assert(ports_declared
[it
.second
->port_id
-1] == false);
966 ports_declared
[it
.second
->port_id
-1] = true;
968 log_assert(!it
.second
->port_input
&& !it
.second
->port_output
);
970 for (auto port_declared
: ports_declared
)
971 log_assert(port_declared
== true);
972 log_assert(GetSize(ports
) == GetSize(ports_declared
));
974 for (auto &it
: memories
) {
975 log_assert(it
.first
== it
.second
->name
);
976 log_assert(!it
.first
.empty());
977 log_assert(it
.second
->width
>= 0);
978 log_assert(it
.second
->size
>= 0);
979 for (auto &it2
: it
.second
->attributes
)
980 log_assert(!it2
.first
.empty());
983 for (auto &it
: cells_
) {
984 log_assert(this == it
.second
->module
);
985 log_assert(it
.first
== it
.second
->name
);
986 log_assert(!it
.first
.empty());
987 log_assert(!it
.second
->type
.empty());
988 for (auto &it2
: it
.second
->connections()) {
989 log_assert(!it2
.first
.empty());
992 for (auto &it2
: it
.second
->attributes
)
993 log_assert(!it2
.first
.empty());
994 for (auto &it2
: it
.second
->parameters
)
995 log_assert(!it2
.first
.empty());
996 InternalCellChecker
checker(this, it
.second
);
1000 for (auto &it
: processes
) {
1001 log_assert(it
.first
== it
.second
->name
);
1002 log_assert(!it
.first
.empty());
1003 // FIXME: More checks here..
1006 for (auto &it
: connections_
) {
1007 log_assert(it
.first
.size() == it
.second
.size());
1012 for (auto &it
: attributes
)
1013 log_assert(!it
.first
.empty());
1017 void RTLIL::Module::optimize()
1021 void RTLIL::Module::cloneInto(RTLIL::Module
*new_mod
) const
1023 log_assert(new_mod
->refcount_wires_
== 0);
1024 log_assert(new_mod
->refcount_cells_
== 0);
1026 new_mod
->connections_
= connections_
;
1027 new_mod
->attributes
= attributes
;
1029 for (auto &it
: wires_
)
1030 new_mod
->addWire(it
.first
, it
.second
);
1032 for (auto &it
: memories
)
1033 new_mod
->memories
[it
.first
] = new RTLIL::Memory(*it
.second
);
1035 for (auto &it
: cells_
)
1036 new_mod
->addCell(it
.first
, it
.second
);
1038 for (auto &it
: processes
)
1039 new_mod
->processes
[it
.first
] = it
.second
->clone();
1041 struct RewriteSigSpecWorker
1044 void operator()(RTLIL::SigSpec
&sig
)
1046 std::vector
<RTLIL::SigChunk
> chunks
= sig
.chunks();
1047 for (auto &c
: chunks
)
1049 c
.wire
= mod
->wires_
.at(c
.wire
->name
);
1054 RewriteSigSpecWorker rewriteSigSpecWorker
;
1055 rewriteSigSpecWorker
.mod
= new_mod
;
1056 new_mod
->rewrite_sigspecs(rewriteSigSpecWorker
);
1057 new_mod
->fixup_ports();
1060 RTLIL::Module
*RTLIL::Module::clone() const
1062 RTLIL::Module
*new_mod
= new RTLIL::Module
;
1063 new_mod
->name
= name
;
1068 bool RTLIL::Module::has_memories() const
1070 return !memories
.empty();
1073 bool RTLIL::Module::has_processes() const
1075 return !processes
.empty();
1078 bool RTLIL::Module::has_memories_warn() const
1080 if (!memories
.empty())
1081 log_warning("Ignoring module %s because it contains memories (run 'memory' command first).\n", log_id(this));
1082 return !memories
.empty();
1085 bool RTLIL::Module::has_processes_warn() const
1087 if (!processes
.empty())
1088 log_warning("Ignoring module %s because it contains processes (run 'proc' command first).\n", log_id(this));
1089 return !processes
.empty();
1092 std::vector
<RTLIL::Wire
*> RTLIL::Module::selected_wires() const
1094 std::vector
<RTLIL::Wire
*> result
;
1095 result
.reserve(wires_
.size());
1096 for (auto &it
: wires_
)
1097 if (design
->selected(this, it
.second
))
1098 result
.push_back(it
.second
);
1102 std::vector
<RTLIL::Cell
*> RTLIL::Module::selected_cells() const
1104 std::vector
<RTLIL::Cell
*> result
;
1105 result
.reserve(wires_
.size());
1106 for (auto &it
: cells_
)
1107 if (design
->selected(this, it
.second
))
1108 result
.push_back(it
.second
);
1112 void RTLIL::Module::add(RTLIL::Wire
*wire
)
1114 log_assert(!wire
->name
.empty());
1115 log_assert(count_id(wire
->name
) == 0);
1116 log_assert(refcount_wires_
== 0);
1117 wires_
[wire
->name
] = wire
;
1118 wire
->module
= this;
1121 void RTLIL::Module::add(RTLIL::Cell
*cell
)
1123 log_assert(!cell
->name
.empty());
1124 log_assert(count_id(cell
->name
) == 0);
1125 log_assert(refcount_cells_
== 0);
1126 cells_
[cell
->name
] = cell
;
1127 cell
->module
= this;
1131 struct DeleteWireWorker
1133 RTLIL::Module
*module
;
1134 const std::set
<RTLIL::Wire
*> *wires_p
;
1136 void operator()(RTLIL::SigSpec
&sig
) {
1137 std::vector
<RTLIL::SigChunk
> chunks
= sig
;
1138 for (auto &c
: chunks
)
1139 if (c
.wire
!= NULL
&& wires_p
->count(c
.wire
)) {
1140 c
.wire
= module
->addWire(NEW_ID
, c
.width
);
1149 void RTLIL::Module::remove(RTLIL::Wire
*wire
)
1151 std::setPort
<RTLIL::Wire
*> wires_
;
1152 wires_
.insert(wire
);
1157 void RTLIL::Module::remove(const std::set
<RTLIL::Wire
*> &wires
)
1159 log_assert(refcount_wires_
== 0);
1161 DeleteWireWorker delete_wire_worker
;
1162 delete_wire_worker
.module
= this;
1163 delete_wire_worker
.wires_p
= &wires
;
1164 rewrite_sigspecs(delete_wire_worker
);
1166 for (auto &it
: wires
) {
1167 log_assert(wires_
.count(it
->name
) != 0);
1168 wires_
.erase(it
->name
);
1173 void RTLIL::Module::remove(RTLIL::Cell
*cell
)
1175 while (!cell
->connections_
.empty())
1176 cell
->unsetPort(cell
->connections_
.begin()->first
);
1178 log_assert(cells_
.count(cell
->name
) != 0);
1179 log_assert(refcount_cells_
== 0);
1180 cells_
.erase(cell
->name
);
1184 void RTLIL::Module::rename(RTLIL::Wire
*wire
, RTLIL::IdString new_name
)
1186 log_assert(wires_
[wire
->name
] == wire
);
1187 log_assert(refcount_wires_
== 0);
1188 wires_
.erase(wire
->name
);
1189 wire
->name
= new_name
;
1193 void RTLIL::Module::rename(RTLIL::Cell
*cell
, RTLIL::IdString new_name
)
1195 log_assert(cells_
[cell
->name
] == cell
);
1196 log_assert(refcount_wires_
== 0);
1197 cells_
.erase(cell
->name
);
1198 cell
->name
= new_name
;
1202 void RTLIL::Module::rename(RTLIL::IdString old_name
, RTLIL::IdString new_name
)
1204 log_assert(count_id(old_name
) != 0);
1205 if (wires_
.count(old_name
))
1206 rename(wires_
.at(old_name
), new_name
);
1207 else if (cells_
.count(old_name
))
1208 rename(cells_
.at(old_name
), new_name
);
1213 void RTLIL::Module::swap_names(RTLIL::Wire
*w1
, RTLIL::Wire
*w2
)
1215 log_assert(wires_
[w1
->name
] == w1
);
1216 log_assert(wires_
[w2
->name
] == w2
);
1217 log_assert(refcount_wires_
== 0);
1219 wires_
.erase(w1
->name
);
1220 wires_
.erase(w2
->name
);
1222 std::swap(w1
->name
, w2
->name
);
1224 wires_
[w1
->name
] = w1
;
1225 wires_
[w2
->name
] = w2
;
1228 void RTLIL::Module::swap_names(RTLIL::Cell
*c1
, RTLIL::Cell
*c2
)
1230 log_assert(cells_
[c1
->name
] == c1
);
1231 log_assert(cells_
[c2
->name
] == c2
);
1232 log_assert(refcount_cells_
== 0);
1234 cells_
.erase(c1
->name
);
1235 cells_
.erase(c2
->name
);
1237 std::swap(c1
->name
, c2
->name
);
1239 cells_
[c1
->name
] = c1
;
1240 cells_
[c2
->name
] = c2
;
1243 RTLIL::IdString
RTLIL::Module::uniquify(RTLIL::IdString name
)
1246 return uniquify(name
, index
);
1249 RTLIL::IdString
RTLIL::Module::uniquify(RTLIL::IdString name
, int &index
)
1252 if (count_id(name
) == 0)
1258 RTLIL::IdString new_name
= stringf("%s_%d", name
.c_str(), index
);
1259 if (count_id(new_name
) == 0)
1265 static bool fixup_ports_compare(const RTLIL::Wire
*a
, const RTLIL::Wire
*b
)
1267 if (a
->port_id
&& !b
->port_id
)
1269 if (!a
->port_id
&& b
->port_id
)
1272 if (a
->port_id
== b
->port_id
)
1273 return a
->name
< b
->name
;
1274 return a
->port_id
< b
->port_id
;
1277 void RTLIL::Module::connect(const RTLIL::SigSig
&conn
)
1279 for (auto mon
: monitors
)
1280 mon
->notify_connect(this, conn
);
1283 for (auto mon
: design
->monitors
)
1284 mon
->notify_connect(this, conn
);
1286 connections_
.push_back(conn
);
1289 void RTLIL::Module::connect(const RTLIL::SigSpec
&lhs
, const RTLIL::SigSpec
&rhs
)
1291 connect(RTLIL::SigSig(lhs
, rhs
));
1294 void RTLIL::Module::new_connections(const std::vector
<RTLIL::SigSig
> &new_conn
)
1296 for (auto mon
: monitors
)
1297 mon
->notify_connect(this, new_conn
);
1300 for (auto mon
: design
->monitors
)
1301 mon
->notify_connect(this, new_conn
);
1303 connections_
= new_conn
;
1306 const std::vector
<RTLIL::SigSig
> &RTLIL::Module::connections() const
1308 return connections_
;
1311 void RTLIL::Module::fixup_ports()
1313 std::vector
<RTLIL::Wire
*> all_ports
;
1315 for (auto &w
: wires_
)
1316 if (w
.second
->port_input
|| w
.second
->port_output
)
1317 all_ports
.push_back(w
.second
);
1319 w
.second
->port_id
= 0;
1321 std::sort(all_ports
.begin(), all_ports
.end(), fixup_ports_compare
);
1324 for (size_t i
= 0; i
< all_ports
.size(); i
++) {
1325 ports
.push_back(all_ports
[i
]->name
);
1326 all_ports
[i
]->port_id
= i
+1;
1330 RTLIL::Wire
*RTLIL::Module::addWire(RTLIL::IdString name
, int width
)
1332 RTLIL::Wire
*wire
= new RTLIL::Wire
;
1334 wire
->width
= width
;
1339 RTLIL::Wire
*RTLIL::Module::addWire(RTLIL::IdString name
, const RTLIL::Wire
*other
)
1341 RTLIL::Wire
*wire
= addWire(name
);
1342 wire
->width
= other
->width
;
1343 wire
->start_offset
= other
->start_offset
;
1344 wire
->port_id
= other
->port_id
;
1345 wire
->port_input
= other
->port_input
;
1346 wire
->port_output
= other
->port_output
;
1347 wire
->upto
= other
->upto
;
1348 wire
->attributes
= other
->attributes
;
1352 RTLIL::Cell
*RTLIL::Module::addCell(RTLIL::IdString name
, RTLIL::IdString type
)
1354 RTLIL::Cell
*cell
= new RTLIL::Cell
;
1361 RTLIL::Cell
*RTLIL::Module::addCell(RTLIL::IdString name
, const RTLIL::Cell
*other
)
1363 RTLIL::Cell
*cell
= addCell(name
, other
->type
);
1364 cell
->connections_
= other
->connections_
;
1365 cell
->parameters
= other
->parameters
;
1366 cell
->attributes
= other
->attributes
;
1370 #define DEF_METHOD(_func, _y_size, _type) \
1371 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed) { \
1372 RTLIL::Cell *cell = addCell(name, _type); \
1373 cell->parameters["\\A_SIGNED"] = is_signed; \
1374 cell->parameters["\\A_WIDTH"] = sig_a.size(); \
1375 cell->parameters["\\Y_WIDTH"] = sig_y.size(); \
1376 cell->setPort("\\A", sig_a); \
1377 cell->setPort("\\Y", sig_y); \
1380 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed) { \
1381 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
1382 add ## _func(name, sig_a, sig_y, is_signed); \
1385 DEF_METHOD(Not
, sig_a
.size(), "$not")
1386 DEF_METHOD(Pos
, sig_a
.size(), "$pos")
1387 DEF_METHOD(Neg
, sig_a
.size(), "$neg")
1388 DEF_METHOD(ReduceAnd
, 1, "$reduce_and")
1389 DEF_METHOD(ReduceOr
, 1, "$reduce_or")
1390 DEF_METHOD(ReduceXor
, 1, "$reduce_xor")
1391 DEF_METHOD(ReduceXnor
, 1, "$reduce_xnor")
1392 DEF_METHOD(ReduceBool
, 1, "$reduce_bool")
1393 DEF_METHOD(LogicNot
, 1, "$logic_not")
1396 #define DEF_METHOD(_func, _y_size, _type) \
1397 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed) { \
1398 RTLIL::Cell *cell = addCell(name, _type); \
1399 cell->parameters["\\A_SIGNED"] = is_signed; \
1400 cell->parameters["\\B_SIGNED"] = is_signed; \
1401 cell->parameters["\\A_WIDTH"] = sig_a.size(); \
1402 cell->parameters["\\B_WIDTH"] = sig_b.size(); \
1403 cell->parameters["\\Y_WIDTH"] = sig_y.size(); \
1404 cell->setPort("\\A", sig_a); \
1405 cell->setPort("\\B", sig_b); \
1406 cell->setPort("\\Y", sig_y); \
1409 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed) { \
1410 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
1411 add ## _func(name, sig_a, sig_b, sig_y, is_signed); \
1414 DEF_METHOD(And
, std::max(sig_a
.size(), sig_b
.size()), "$and")
1415 DEF_METHOD(Or
, std::max(sig_a
.size(), sig_b
.size()), "$or")
1416 DEF_METHOD(Xor
, std::max(sig_a
.size(), sig_b
.size()), "$xor")
1417 DEF_METHOD(Xnor
, std::max(sig_a
.size(), sig_b
.size()), "$xnor")
1418 DEF_METHOD(Shl
, sig_a
.size(), "$shl")
1419 DEF_METHOD(Shr
, sig_a
.size(), "$shr")
1420 DEF_METHOD(Sshl
, sig_a
.size(), "$sshl")
1421 DEF_METHOD(Sshr
, sig_a
.size(), "$sshr")
1422 DEF_METHOD(Shift
, sig_a
.size(), "$shift")
1423 DEF_METHOD(Shiftx
, sig_a
.size(), "$shiftx")
1424 DEF_METHOD(Lt
, 1, "$lt")
1425 DEF_METHOD(Le
, 1, "$le")
1426 DEF_METHOD(Eq
, 1, "$eq")
1427 DEF_METHOD(Ne
, 1, "$ne")
1428 DEF_METHOD(Eqx
, 1, "$eqx")
1429 DEF_METHOD(Nex
, 1, "$nex")
1430 DEF_METHOD(Ge
, 1, "$ge")
1431 DEF_METHOD(Gt
, 1, "$gt")
1432 DEF_METHOD(Add
, std::max(sig_a
.size(), sig_b
.size()), "$add")
1433 DEF_METHOD(Sub
, std::max(sig_a
.size(), sig_b
.size()), "$sub")
1434 DEF_METHOD(Mul
, std::max(sig_a
.size(), sig_b
.size()), "$mul")
1435 DEF_METHOD(Div
, std::max(sig_a
.size(), sig_b
.size()), "$div")
1436 DEF_METHOD(Mod
, std::max(sig_a
.size(), sig_b
.size()), "$mod")
1437 DEF_METHOD(LogicAnd
, 1, "$logic_and")
1438 DEF_METHOD(LogicOr
, 1, "$logic_or")
1441 #define DEF_METHOD(_func, _type, _pmux) \
1442 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, RTLIL::SigSpec sig_y) { \
1443 RTLIL::Cell *cell = addCell(name, _type); \
1444 cell->parameters["\\WIDTH"] = sig_a.size(); \
1445 if (_pmux) cell->parameters["\\S_WIDTH"] = sig_s.size(); \
1446 cell->setPort("\\A", sig_a); \
1447 cell->setPort("\\B", sig_b); \
1448 cell->setPort("\\S", sig_s); \
1449 cell->setPort("\\Y", sig_y); \
1452 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s) { \
1453 RTLIL::SigSpec sig_y = addWire(NEW_ID, sig_a.size()); \
1454 add ## _func(name, sig_a, sig_b, sig_s, sig_y); \
1457 DEF_METHOD(Mux
, "$mux", 0)
1458 DEF_METHOD(Pmux
, "$pmux", 1)
1461 #define DEF_METHOD_2(_func, _type, _P1, _P2) \
1462 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2) { \
1463 RTLIL::Cell *cell = addCell(name, _type); \
1464 cell->setPort("\\" #_P1, sig1); \
1465 cell->setPort("\\" #_P2, sig2); \
1468 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1) { \
1469 RTLIL::SigBit sig2 = addWire(NEW_ID); \
1470 add ## _func(name, sig1, sig2); \
1473 #define DEF_METHOD_3(_func, _type, _P1, _P2, _P3) \
1474 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3) { \
1475 RTLIL::Cell *cell = addCell(name, _type); \
1476 cell->setPort("\\" #_P1, sig1); \
1477 cell->setPort("\\" #_P2, sig2); \
1478 cell->setPort("\\" #_P3, sig3); \
1481 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2) { \
1482 RTLIL::SigBit sig3 = addWire(NEW_ID); \
1483 add ## _func(name, sig1, sig2, sig3); \
1486 #define DEF_METHOD_4(_func, _type, _P1, _P2, _P3, _P4) \
1487 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, RTLIL::SigBit sig4) { \
1488 RTLIL::Cell *cell = addCell(name, _type); \
1489 cell->setPort("\\" #_P1, sig1); \
1490 cell->setPort("\\" #_P2, sig2); \
1491 cell->setPort("\\" #_P3, sig3); \
1492 cell->setPort("\\" #_P4, sig4); \
1495 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3) { \
1496 RTLIL::SigBit sig4 = addWire(NEW_ID); \
1497 add ## _func(name, sig1, sig2, sig3, sig4); \
1500 #define DEF_METHOD_5(_func, _type, _P1, _P2, _P3, _P4, _P5) \
1501 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, RTLIL::SigBit sig4, RTLIL::SigBit sig5) { \
1502 RTLIL::Cell *cell = addCell(name, _type); \
1503 cell->setPort("\\" #_P1, sig1); \
1504 cell->setPort("\\" #_P2, sig2); \
1505 cell->setPort("\\" #_P3, sig3); \
1506 cell->setPort("\\" #_P4, sig4); \
1507 cell->setPort("\\" #_P5, sig5); \
1510 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, RTLIL::SigBit sig4) { \
1511 RTLIL::SigBit sig5 = addWire(NEW_ID); \
1512 add ## _func(name, sig1, sig2, sig3, sig4, sig5); \
1515 DEF_METHOD_2(NotGate
, "$_NOT_", A
, Y
)
1516 DEF_METHOD_3(AndGate
, "$_AND_", A
, B
, Y
)
1517 DEF_METHOD_3(NandGate
, "$_NAND_", A
, B
, Y
)
1518 DEF_METHOD_3(OrGate
, "$_OR_", A
, B
, Y
)
1519 DEF_METHOD_3(NorGate
, "$_NOR_", A
, B
, Y
)
1520 DEF_METHOD_3(XorGate
, "$_XOR_", A
, B
, Y
)
1521 DEF_METHOD_3(XnorGate
, "$_XNOR_", A
, B
, Y
)
1522 DEF_METHOD_4(MuxGate
, "$_MUX_", A
, B
, S
, Y
)
1523 DEF_METHOD_4(Aoi3Gate
, "$_AOI3_", A
, B
, C
, Y
)
1524 DEF_METHOD_4(Oai3Gate
, "$_OAI3_", A
, B
, C
, Y
)
1525 DEF_METHOD_5(Aoi4Gate
, "$_AOI4_", A
, B
, C
, D
, Y
)
1526 DEF_METHOD_5(Oai4Gate
, "$_OAI4_", A
, B
, C
, D
, Y
)
1532 RTLIL::Cell
* RTLIL::Module::addPow(RTLIL::IdString name
, RTLIL::SigSpec sig_a
, RTLIL::SigSpec sig_b
, RTLIL::SigSpec sig_y
, bool a_signed
, bool b_signed
)
1534 RTLIL::Cell
*cell
= addCell(name
, "$pow");
1535 cell
->parameters
["\\A_SIGNED"] = a_signed
;
1536 cell
->parameters
["\\B_SIGNED"] = b_signed
;
1537 cell
->parameters
["\\A_WIDTH"] = sig_a
.size();
1538 cell
->parameters
["\\B_WIDTH"] = sig_b
.size();
1539 cell
->parameters
["\\Y_WIDTH"] = sig_y
.size();
1540 cell
->setPort("\\A", sig_a
);
1541 cell
->setPort("\\B", sig_b
);
1542 cell
->setPort("\\Y", sig_y
);
1546 RTLIL::Cell
* RTLIL::Module::addSlice(RTLIL::IdString name
, RTLIL::SigSpec sig_a
, RTLIL::SigSpec sig_y
, RTLIL::Const offset
)
1548 RTLIL::Cell
*cell
= addCell(name
, "$slice");
1549 cell
->parameters
["\\A_WIDTH"] = sig_a
.size();
1550 cell
->parameters
["\\Y_WIDTH"] = sig_y
.size();
1551 cell
->parameters
["\\OFFSET"] = offset
;
1552 cell
->setPort("\\A", sig_a
);
1553 cell
->setPort("\\Y", sig_y
);
1557 RTLIL::Cell
* RTLIL::Module::addConcat(RTLIL::IdString name
, RTLIL::SigSpec sig_a
, RTLIL::SigSpec sig_b
, RTLIL::SigSpec sig_y
)
1559 RTLIL::Cell
*cell
= addCell(name
, "$concat");
1560 cell
->parameters
["\\A_WIDTH"] = sig_a
.size();
1561 cell
->parameters
["\\B_WIDTH"] = sig_b
.size();
1562 cell
->setPort("\\A", sig_a
);
1563 cell
->setPort("\\B", sig_b
);
1564 cell
->setPort("\\Y", sig_y
);
1568 RTLIL::Cell
* RTLIL::Module::addLut(RTLIL::IdString name
, RTLIL::SigSpec sig_i
, RTLIL::SigSpec sig_o
, RTLIL::Const lut
)
1570 RTLIL::Cell
*cell
= addCell(name
, "$lut");
1571 cell
->parameters
["\\LUT"] = lut
;
1572 cell
->parameters
["\\WIDTH"] = sig_i
.size();
1573 cell
->setPort("\\A", sig_i
);
1574 cell
->setPort("\\Y", sig_o
);
1578 RTLIL::Cell
* RTLIL::Module::addAssert(RTLIL::IdString name
, RTLIL::SigSpec sig_a
, RTLIL::SigSpec sig_en
)
1580 RTLIL::Cell
*cell
= addCell(name
, "$assert");
1581 cell
->setPort("\\A", sig_a
);
1582 cell
->setPort("\\EN", sig_en
);
1586 RTLIL::Cell
* RTLIL::Module::addSr(RTLIL::IdString name
, RTLIL::SigSpec sig_set
, RTLIL::SigSpec sig_clr
, RTLIL::SigSpec sig_q
, bool set_polarity
, bool clr_polarity
)
1588 RTLIL::Cell
*cell
= addCell(name
, "$sr");
1589 cell
->parameters
["\\SET_POLARITY"] = set_polarity
;
1590 cell
->parameters
["\\CLR_POLARITY"] = clr_polarity
;
1591 cell
->parameters
["\\WIDTH"] = sig_q
.size();
1592 cell
->setPort("\\SET", sig_set
);
1593 cell
->setPort("\\CLR", sig_clr
);
1594 cell
->setPort("\\Q", sig_q
);
1598 RTLIL::Cell
* RTLIL::Module::addDff(RTLIL::IdString name
, RTLIL::SigSpec sig_clk
, RTLIL::SigSpec sig_d
, RTLIL::SigSpec sig_q
, bool clk_polarity
)
1600 RTLIL::Cell
*cell
= addCell(name
, "$dff");
1601 cell
->parameters
["\\CLK_POLARITY"] = clk_polarity
;
1602 cell
->parameters
["\\WIDTH"] = sig_q
.size();
1603 cell
->setPort("\\CLK", sig_clk
);
1604 cell
->setPort("\\D", sig_d
);
1605 cell
->setPort("\\Q", sig_q
);
1609 RTLIL::Cell
* RTLIL::Module::addDffe(RTLIL::IdString name
, RTLIL::SigSpec sig_clk
, RTLIL::SigSpec sig_en
, RTLIL::SigSpec sig_d
, RTLIL::SigSpec sig_q
, bool clk_polarity
, bool en_polarity
)
1611 RTLIL::Cell
*cell
= addCell(name
, "$dffe");
1612 cell
->parameters
["\\CLK_POLARITY"] = clk_polarity
;
1613 cell
->parameters
["\\EN_POLARITY"] = en_polarity
;
1614 cell
->parameters
["\\WIDTH"] = sig_q
.size();
1615 cell
->setPort("\\CLK", sig_clk
);
1616 cell
->setPort("\\EN", sig_en
);
1617 cell
->setPort("\\D", sig_d
);
1618 cell
->setPort("\\Q", sig_q
);
1622 RTLIL::Cell
* RTLIL::Module::addDffsr(RTLIL::IdString name
, RTLIL::SigSpec sig_clk
, RTLIL::SigSpec sig_set
, RTLIL::SigSpec sig_clr
,
1623 RTLIL::SigSpec sig_d
, RTLIL::SigSpec sig_q
, bool clk_polarity
, bool set_polarity
, bool clr_polarity
)
1625 RTLIL::Cell
*cell
= addCell(name
, "$dffsr");
1626 cell
->parameters
["\\CLK_POLARITY"] = clk_polarity
;
1627 cell
->parameters
["\\SET_POLARITY"] = set_polarity
;
1628 cell
->parameters
["\\CLR_POLARITY"] = clr_polarity
;
1629 cell
->parameters
["\\WIDTH"] = sig_q
.size();
1630 cell
->setPort("\\CLK", sig_clk
);
1631 cell
->setPort("\\SET", sig_set
);
1632 cell
->setPort("\\CLR", sig_clr
);
1633 cell
->setPort("\\D", sig_d
);
1634 cell
->setPort("\\Q", sig_q
);
1638 RTLIL::Cell
* RTLIL::Module::addAdff(RTLIL::IdString name
, RTLIL::SigSpec sig_clk
, RTLIL::SigSpec sig_arst
, RTLIL::SigSpec sig_d
, RTLIL::SigSpec sig_q
,
1639 RTLIL::Const arst_value
, bool clk_polarity
, bool arst_polarity
)
1641 RTLIL::Cell
*cell
= addCell(name
, "$adff");
1642 cell
->parameters
["\\CLK_POLARITY"] = clk_polarity
;
1643 cell
->parameters
["\\ARST_POLARITY"] = arst_polarity
;
1644 cell
->parameters
["\\ARST_VALUE"] = arst_value
;
1645 cell
->parameters
["\\WIDTH"] = sig_q
.size();
1646 cell
->setPort("\\CLK", sig_clk
);
1647 cell
->setPort("\\ARST", sig_arst
);
1648 cell
->setPort("\\D", sig_d
);
1649 cell
->setPort("\\Q", sig_q
);
1653 RTLIL::Cell
* RTLIL::Module::addDlatch(RTLIL::IdString name
, RTLIL::SigSpec sig_en
, RTLIL::SigSpec sig_d
, RTLIL::SigSpec sig_q
, bool en_polarity
)
1655 RTLIL::Cell
*cell
= addCell(name
, "$dlatch");
1656 cell
->parameters
["\\EN_POLARITY"] = en_polarity
;
1657 cell
->parameters
["\\WIDTH"] = sig_q
.size();
1658 cell
->setPort("\\EN", sig_en
);
1659 cell
->setPort("\\D", sig_d
);
1660 cell
->setPort("\\Q", sig_q
);
1664 RTLIL::Cell
* RTLIL::Module::addDlatchsr(RTLIL::IdString name
, RTLIL::SigSpec sig_en
, RTLIL::SigSpec sig_set
, RTLIL::SigSpec sig_clr
,
1665 RTLIL::SigSpec sig_d
, RTLIL::SigSpec sig_q
, bool en_polarity
, bool set_polarity
, bool clr_polarity
)
1667 RTLIL::Cell
*cell
= addCell(name
, "$dlatchsr");
1668 cell
->parameters
["\\EN_POLARITY"] = en_polarity
;
1669 cell
->parameters
["\\SET_POLARITY"] = set_polarity
;
1670 cell
->parameters
["\\CLR_POLARITY"] = clr_polarity
;
1671 cell
->parameters
["\\WIDTH"] = sig_q
.size();
1672 cell
->setPort("\\EN", sig_en
);
1673 cell
->setPort("\\SET", sig_set
);
1674 cell
->setPort("\\CLR", sig_clr
);
1675 cell
->setPort("\\D", sig_d
);
1676 cell
->setPort("\\Q", sig_q
);
1680 RTLIL::Cell
* RTLIL::Module::addDffGate(RTLIL::IdString name
, RTLIL::SigSpec sig_clk
, RTLIL::SigSpec sig_d
, RTLIL::SigSpec sig_q
, bool clk_polarity
)
1682 RTLIL::Cell
*cell
= addCell(name
, stringf("$_DFF_%c_", clk_polarity
? 'P' : 'N'));
1683 cell
->setPort("\\C", sig_clk
);
1684 cell
->setPort("\\D", sig_d
);
1685 cell
->setPort("\\Q", sig_q
);
1689 RTLIL::Cell
* RTLIL::Module::addDffeGate(RTLIL::IdString name
, RTLIL::SigSpec sig_clk
, RTLIL::SigSpec sig_en
, RTLIL::SigSpec sig_d
, RTLIL::SigSpec sig_q
, bool clk_polarity
, bool en_polarity
)
1691 RTLIL::Cell
*cell
= addCell(name
, stringf("$_DFFE_%c%c_", clk_polarity
? 'P' : 'N', en_polarity
? 'P' : 'N'));
1692 cell
->setPort("\\C", sig_clk
);
1693 cell
->setPort("\\E", sig_en
);
1694 cell
->setPort("\\D", sig_d
);
1695 cell
->setPort("\\Q", sig_q
);
1699 RTLIL::Cell
* RTLIL::Module::addDffsrGate(RTLIL::IdString name
, RTLIL::SigSpec sig_clk
, RTLIL::SigSpec sig_set
, RTLIL::SigSpec sig_clr
,
1700 RTLIL::SigSpec sig_d
, RTLIL::SigSpec sig_q
, bool clk_polarity
, bool set_polarity
, bool clr_polarity
)
1702 RTLIL::Cell
*cell
= addCell(name
, stringf("$_DFFSR_%c%c%c_", clk_polarity
? 'P' : 'N', set_polarity
? 'P' : 'N', clr_polarity
? 'P' : 'N'));
1703 cell
->setPort("\\C", sig_clk
);
1704 cell
->setPort("\\S", sig_set
);
1705 cell
->setPort("\\R", sig_clr
);
1706 cell
->setPort("\\D", sig_d
);
1707 cell
->setPort("\\Q", sig_q
);
1711 RTLIL::Cell
* RTLIL::Module::addAdffGate(RTLIL::IdString name
, RTLIL::SigSpec sig_clk
, RTLIL::SigSpec sig_arst
, RTLIL::SigSpec sig_d
, RTLIL::SigSpec sig_q
,
1712 bool arst_value
, bool clk_polarity
, bool arst_polarity
)
1714 RTLIL::Cell
*cell
= addCell(name
, stringf("$_DFF_%c%c%c_", clk_polarity
? 'P' : 'N', arst_polarity
? 'P' : 'N', arst_value
? '1' : '0'));
1715 cell
->setPort("\\C", sig_clk
);
1716 cell
->setPort("\\R", sig_arst
);
1717 cell
->setPort("\\D", sig_d
);
1718 cell
->setPort("\\Q", sig_q
);
1722 RTLIL::Cell
* RTLIL::Module::addDlatchGate(RTLIL::IdString name
, RTLIL::SigSpec sig_en
, RTLIL::SigSpec sig_d
, RTLIL::SigSpec sig_q
, bool en_polarity
)
1724 RTLIL::Cell
*cell
= addCell(name
, stringf("$_DLATCH_%c_", en_polarity
? 'P' : 'N'));
1725 cell
->setPort("\\E", sig_en
);
1726 cell
->setPort("\\D", sig_d
);
1727 cell
->setPort("\\Q", sig_q
);
1731 RTLIL::Cell
* RTLIL::Module::addDlatchsrGate(RTLIL::IdString name
, RTLIL::SigSpec sig_en
, RTLIL::SigSpec sig_set
, RTLIL::SigSpec sig_clr
,
1732 RTLIL::SigSpec sig_d
, RTLIL::SigSpec sig_q
, bool en_polarity
, bool set_polarity
, bool clr_polarity
)
1734 RTLIL::Cell
*cell
= addCell(name
, stringf("$_DLATCHSR_%c%c%c_", en_polarity
? 'P' : 'N', set_polarity
? 'P' : 'N', clr_polarity
? 'P' : 'N'));
1735 cell
->setPort("\\E", sig_en
);
1736 cell
->setPort("\\S", sig_set
);
1737 cell
->setPort("\\R", sig_clr
);
1738 cell
->setPort("\\D", sig_d
);
1739 cell
->setPort("\\Q", sig_q
);
1751 port_output
= false;
1755 RTLIL::Memory::Memory()
1761 RTLIL::Cell::Cell() : module(nullptr)
1765 bool RTLIL::Cell::hasPort(RTLIL::IdString portname
) const
1767 return connections_
.count(portname
) != 0;
1770 void RTLIL::Cell::unsetPort(RTLIL::IdString portname
)
1772 RTLIL::SigSpec signal
;
1773 auto conn_it
= connections_
.find(portname
);
1775 if (conn_it
!= connections_
.end())
1777 for (auto mon
: module
->monitors
)
1778 mon
->notify_connect(this, conn_it
->first
, conn_it
->second
, signal
);
1781 for (auto mon
: module
->design
->monitors
)
1782 mon
->notify_connect(this, conn_it
->first
, conn_it
->second
, signal
);
1784 connections_
.erase(conn_it
);
1788 void RTLIL::Cell::setPort(RTLIL::IdString portname
, RTLIL::SigSpec signal
)
1790 auto conn_it
= connections_
.find(portname
);
1792 if (conn_it
== connections_
.end()) {
1793 connections_
[portname
] = RTLIL::SigSpec();
1794 conn_it
= connections_
.find(portname
);
1795 log_assert(conn_it
!= connections_
.end());
1798 for (auto mon
: module
->monitors
)
1799 mon
->notify_connect(this, conn_it
->first
, conn_it
->second
, signal
);
1802 for (auto mon
: module
->design
->monitors
)
1803 mon
->notify_connect(this, conn_it
->first
, conn_it
->second
, signal
);
1805 conn_it
->second
= signal
;
1808 const RTLIL::SigSpec
&RTLIL::Cell::getPort(RTLIL::IdString portname
) const
1810 return connections_
.at(portname
);
1813 const std::map
<RTLIL::IdString
, RTLIL::SigSpec
> &RTLIL::Cell::connections() const
1815 return connections_
;
1818 bool RTLIL::Cell::hasParam(RTLIL::IdString paramname
) const
1820 return parameters
.count(paramname
) != 0;
1823 void RTLIL::Cell::unsetParam(RTLIL::IdString paramname
)
1825 parameters
.erase(paramname
);
1828 void RTLIL::Cell::setParam(RTLIL::IdString paramname
, RTLIL::Const value
)
1830 parameters
[paramname
] = value
;
1833 const RTLIL::Const
&RTLIL::Cell::getParam(RTLIL::IdString paramname
) const
1835 return parameters
.at(paramname
);
1838 void RTLIL::Cell::check()
1841 InternalCellChecker
checker(NULL
, this);
1846 void RTLIL::Cell::fixup_parameters(bool set_a_signed
, bool set_b_signed
)
1848 if (type
.substr(0, 1) != "$" || type
.substr(0, 2) == "$_" || type
.substr(0, 8) == "$paramod" ||
1849 type
.substr(0, 9) == "$verific$" || type
.substr(0, 7) == "$array:" || type
.substr(0, 8) == "$extern:")
1852 if (type
== "$mux" || type
== "$pmux") {
1853 parameters
["\\WIDTH"] = GetSize(connections_
["\\Y"]);
1854 if (type
== "$pmux")
1855 parameters
["\\S_WIDTH"] = GetSize(connections_
["\\S"]);
1860 if (type
== "$lut") {
1861 parameters
["\\WIDTH"] = GetSize(connections_
["\\A"]);
1865 if (type
== "$fa") {
1866 parameters
["\\WIDTH"] = GetSize(connections_
["\\Y"]);
1870 if (type
== "$lcu") {
1871 parameters
["\\WIDTH"] = GetSize(connections_
["\\CO"]);
1875 bool signedness_ab
= !type
.in("$slice", "$concat", "$macc");
1877 if (connections_
.count("\\A")) {
1878 if (signedness_ab
) {
1880 parameters
["\\A_SIGNED"] = true;
1881 else if (parameters
.count("\\A_SIGNED") == 0)
1882 parameters
["\\A_SIGNED"] = false;
1884 parameters
["\\A_WIDTH"] = GetSize(connections_
["\\A"]);
1887 if (connections_
.count("\\B")) {
1888 if (signedness_ab
) {
1890 parameters
["\\B_SIGNED"] = true;
1891 else if (parameters
.count("\\B_SIGNED") == 0)
1892 parameters
["\\B_SIGNED"] = false;
1894 parameters
["\\B_WIDTH"] = GetSize(connections_
["\\B"]);
1897 if (connections_
.count("\\Y"))
1898 parameters
["\\Y_WIDTH"] = GetSize(connections_
["\\Y"]);
1903 RTLIL::SigChunk::SigChunk()
1910 RTLIL::SigChunk::SigChunk(const RTLIL::Const
&value
)
1914 width
= GetSize(data
);
1918 RTLIL::SigChunk::SigChunk(RTLIL::Wire
*wire
)
1920 log_assert(wire
!= nullptr);
1922 this->width
= wire
->width
;
1926 RTLIL::SigChunk::SigChunk(RTLIL::Wire
*wire
, int offset
, int width
)
1928 log_assert(wire
!= nullptr);
1930 this->width
= width
;
1931 this->offset
= offset
;
1934 RTLIL::SigChunk::SigChunk(const std::string
&str
)
1937 data
= RTLIL::Const(str
).bits
;
1938 width
= GetSize(data
);
1942 RTLIL::SigChunk::SigChunk(int val
, int width
)
1945 data
= RTLIL::Const(val
, width
).bits
;
1946 this->width
= GetSize(data
);
1950 RTLIL::SigChunk::SigChunk(RTLIL::State bit
, int width
)
1953 data
= RTLIL::Const(bit
, width
).bits
;
1954 this->width
= GetSize(data
);
1958 RTLIL::SigChunk::SigChunk(RTLIL::SigBit bit
)
1963 data
= RTLIL::Const(bit
.data
).bits
;
1965 offset
= bit
.offset
;
1969 RTLIL::SigChunk
RTLIL::SigChunk::extract(int offset
, int length
) const
1971 RTLIL::SigChunk ret
;
1974 ret
.offset
= this->offset
+ offset
;
1977 for (int i
= 0; i
< length
; i
++)
1978 ret
.data
.push_back(data
[offset
+i
]);
1984 bool RTLIL::SigChunk::operator <(const RTLIL::SigChunk
&other
) const
1986 if (wire
&& other
.wire
)
1987 if (wire
->name
!= other
.wire
->name
)
1988 return wire
->name
< other
.wire
->name
;
1990 if (wire
!= other
.wire
)
1991 return wire
< other
.wire
;
1993 if (offset
!= other
.offset
)
1994 return offset
< other
.offset
;
1996 if (width
!= other
.width
)
1997 return width
< other
.width
;
1999 return data
< other
.data
;
2002 bool RTLIL::SigChunk::operator ==(const RTLIL::SigChunk
&other
) const
2004 return wire
== other
.wire
&& width
== other
.width
&& offset
== other
.offset
&& data
== other
.data
;
2007 bool RTLIL::SigChunk::operator !=(const RTLIL::SigChunk
&other
) const
2014 RTLIL::SigSpec::SigSpec()
2020 RTLIL::SigSpec::SigSpec(const RTLIL::SigSpec
&other
)
2025 RTLIL::SigSpec::SigSpec(std::initializer_list
<RTLIL::SigSpec
> parts
)
2027 cover("kernel.rtlil.sigspec.init.list");
2032 std::vector
<RTLIL::SigSpec
> parts_vec(parts
.begin(), parts
.end());
2033 for (auto it
= parts_vec
.rbegin(); it
!= parts_vec
.rend(); it
++)
2037 const RTLIL::SigSpec
&RTLIL::SigSpec::operator=(const RTLIL::SigSpec
&other
)
2039 cover("kernel.rtlil.sigspec.assign");
2041 width_
= other
.width_
;
2042 hash_
= other
.hash_
;
2043 chunks_
= other
.chunks_
;
2046 if (!other
.bits_
.empty())
2048 RTLIL::SigChunk
*last
= NULL
;
2049 int last_end_offset
= 0;
2051 for (auto &bit
: other
.bits_
) {
2052 if (last
&& bit
.wire
== last
->wire
) {
2053 if (bit
.wire
== NULL
) {
2054 last
->data
.push_back(bit
.data
);
2057 } else if (last_end_offset
== bit
.offset
) {
2063 chunks_
.push_back(bit
);
2064 last
= &chunks_
.back();
2065 last_end_offset
= bit
.offset
+ 1;
2074 RTLIL::SigSpec::SigSpec(const RTLIL::Const
&value
)
2076 cover("kernel.rtlil.sigspec.init.const");
2078 chunks_
.push_back(RTLIL::SigChunk(value
));
2079 width_
= chunks_
.back().width
;
2084 RTLIL::SigSpec::SigSpec(const RTLIL::SigChunk
&chunk
)
2086 cover("kernel.rtlil.sigspec.init.chunk");
2088 chunks_
.push_back(chunk
);
2089 width_
= chunks_
.back().width
;
2094 RTLIL::SigSpec::SigSpec(RTLIL::Wire
*wire
)
2096 cover("kernel.rtlil.sigspec.init.wire");
2098 chunks_
.push_back(RTLIL::SigChunk(wire
));
2099 width_
= chunks_
.back().width
;
2104 RTLIL::SigSpec::SigSpec(RTLIL::Wire
*wire
, int offset
, int width
)
2106 cover("kernel.rtlil.sigspec.init.wire_part");
2108 chunks_
.push_back(RTLIL::SigChunk(wire
, offset
, width
));
2109 width_
= chunks_
.back().width
;
2114 RTLIL::SigSpec::SigSpec(const std::string
&str
)
2116 cover("kernel.rtlil.sigspec.init.str");
2118 chunks_
.push_back(RTLIL::SigChunk(str
));
2119 width_
= chunks_
.back().width
;
2124 RTLIL::SigSpec::SigSpec(int val
, int width
)
2126 cover("kernel.rtlil.sigspec.init.int");
2128 chunks_
.push_back(RTLIL::SigChunk(val
, width
));
2134 RTLIL::SigSpec::SigSpec(RTLIL::State bit
, int width
)
2136 cover("kernel.rtlil.sigspec.init.state");
2138 chunks_
.push_back(RTLIL::SigChunk(bit
, width
));
2144 RTLIL::SigSpec::SigSpec(RTLIL::SigBit bit
, int width
)
2146 cover("kernel.rtlil.sigspec.init.bit");
2148 if (bit
.wire
== NULL
)
2149 chunks_
.push_back(RTLIL::SigChunk(bit
.data
, width
));
2151 for (int i
= 0; i
< width
; i
++)
2152 chunks_
.push_back(bit
);
2158 RTLIL::SigSpec::SigSpec(std::vector
<RTLIL::SigChunk
> chunks
)
2160 cover("kernel.rtlil.sigspec.init.stdvec_chunks");
2164 for (auto &c
: chunks
)
2169 RTLIL::SigSpec::SigSpec(std::vector
<RTLIL::SigBit
> bits
)
2171 cover("kernel.rtlil.sigspec.init.stdvec_bits");
2175 for (auto &bit
: bits
)
2180 RTLIL::SigSpec::SigSpec(std::set
<RTLIL::SigBit
> bits
)
2182 cover("kernel.rtlil.sigspec.init.stdset_bits");
2186 for (auto &bit
: bits
)
2191 RTLIL::SigSpec::SigSpec(bool bit
)
2193 cover("kernel.rtlil.sigspec.init.bool");
2201 void RTLIL::SigSpec::pack() const
2203 RTLIL::SigSpec
*that
= (RTLIL::SigSpec
*)this;
2205 if (that
->bits_
.empty())
2208 cover("kernel.rtlil.sigspec.convert.pack");
2209 log_assert(that
->chunks_
.empty());
2211 std::vector
<RTLIL::SigBit
> old_bits
;
2212 old_bits
.swap(that
->bits_
);
2214 RTLIL::SigChunk
*last
= NULL
;
2215 int last_end_offset
= 0;
2217 for (auto &bit
: old_bits
) {
2218 if (last
&& bit
.wire
== last
->wire
) {
2219 if (bit
.wire
== NULL
) {
2220 last
->data
.push_back(bit
.data
);
2223 } else if (last_end_offset
== bit
.offset
) {
2229 that
->chunks_
.push_back(bit
);
2230 last
= &that
->chunks_
.back();
2231 last_end_offset
= bit
.offset
+ 1;
2237 void RTLIL::SigSpec::unpack() const
2239 RTLIL::SigSpec
*that
= (RTLIL::SigSpec
*)this;
2241 if (that
->chunks_
.empty())
2244 cover("kernel.rtlil.sigspec.convert.unpack");
2245 log_assert(that
->bits_
.empty());
2247 that
->bits_
.reserve(that
->width_
);
2248 for (auto &c
: that
->chunks_
)
2249 for (int i
= 0; i
< c
.width
; i
++)
2250 that
->bits_
.push_back(RTLIL::SigBit(c
, i
));
2252 that
->chunks_
.clear();
2256 #define DJB2(_hash, _value) (_hash) = (((_hash) << 5) + (_hash)) + (_value)
2258 void RTLIL::SigSpec::hash() const
2260 RTLIL::SigSpec
*that
= (RTLIL::SigSpec
*)this;
2262 if (that
->hash_
!= 0)
2265 cover("kernel.rtlil.sigspec.hash");
2269 for (auto &c
: that
->chunks_
)
2270 if (c
.wire
== NULL
) {
2271 for (auto &v
: c
.data
)
2272 DJB2(that
->hash_
, v
);
2274 DJB2(that
->hash_
, c
.wire
->name
.index_
);
2275 DJB2(that
->hash_
, c
.offset
);
2276 DJB2(that
->hash_
, c
.width
);
2279 if (that
->hash_
== 0)
2283 void RTLIL::SigSpec::sort()
2286 cover("kernel.rtlil.sigspec.sort");
2287 std::sort(bits_
.begin(), bits_
.end());
2290 void RTLIL::SigSpec::sort_and_unify()
2292 cover("kernel.rtlil.sigspec.sort_and_unify");
2293 *this = this->to_sigbit_set();
2296 void RTLIL::SigSpec::replace(const RTLIL::SigSpec
&pattern
, const RTLIL::SigSpec
&with
)
2298 replace(pattern
, with
, this);
2301 void RTLIL::SigSpec::replace(const RTLIL::SigSpec
&pattern
, const RTLIL::SigSpec
&with
, RTLIL::SigSpec
*other
) const
2303 log_assert(pattern
.width_
== with
.width_
);
2308 std::map
<RTLIL::SigBit
, RTLIL::SigBit
> rules
;
2310 for (int i
= 0; i
< GetSize(pattern
.bits_
); i
++)
2311 if (pattern
.bits_
[i
].wire
!= NULL
)
2312 rules
[pattern
.bits_
[i
]] = with
.bits_
[i
];
2314 replace(rules
, other
);
2317 void RTLIL::SigSpec::replace(const std::map
<RTLIL::SigBit
, RTLIL::SigBit
> &rules
)
2319 replace(rules
, this);
2322 void RTLIL::SigSpec::replace(const std::map
<RTLIL::SigBit
, RTLIL::SigBit
> &rules
, RTLIL::SigSpec
*other
) const
2324 cover("kernel.rtlil.sigspec.replace");
2326 log_assert(other
!= NULL
);
2327 log_assert(width_
== other
->width_
);
2332 for (int i
= 0; i
< GetSize(bits_
); i
++) {
2333 auto it
= rules
.find(bits_
[i
]);
2334 if (it
!= rules
.end())
2335 other
->bits_
[i
] = it
->second
;
2341 void RTLIL::SigSpec::remove(const RTLIL::SigSpec
&pattern
)
2343 remove2(pattern
, NULL
);
2346 void RTLIL::SigSpec::remove(const RTLIL::SigSpec
&pattern
, RTLIL::SigSpec
*other
) const
2348 RTLIL::SigSpec tmp
= *this;
2349 tmp
.remove2(pattern
, other
);
2352 void RTLIL::SigSpec::remove2(const RTLIL::SigSpec
&pattern
, RTLIL::SigSpec
*other
)
2354 std::set
<RTLIL::SigBit
> pattern_bits
= pattern
.to_sigbit_set();
2355 remove2(pattern_bits
, other
);
2358 void RTLIL::SigSpec::remove(const std::set
<RTLIL::SigBit
> &pattern
)
2360 remove2(pattern
, NULL
);
2363 void RTLIL::SigSpec::remove(const std::set
<RTLIL::SigBit
> &pattern
, RTLIL::SigSpec
*other
) const
2365 RTLIL::SigSpec tmp
= *this;
2366 tmp
.remove2(pattern
, other
);
2369 void RTLIL::SigSpec::remove2(const std::set
<RTLIL::SigBit
> &pattern
, RTLIL::SigSpec
*other
)
2372 cover("kernel.rtlil.sigspec.remove_other");
2374 cover("kernel.rtlil.sigspec.remove");
2378 if (other
!= NULL
) {
2379 log_assert(width_
== other
->width_
);
2383 std::vector
<RTLIL::SigBit
> new_bits
, new_other_bits
;
2385 new_bits
.resize(GetSize(bits_
));
2387 new_other_bits
.resize(GetSize(bits_
));
2390 for (int i
= 0; i
< GetSize(bits_
); i
++) {
2391 if (bits_
[i
].wire
!= NULL
&& pattern
.count(bits_
[i
]))
2394 new_other_bits
[k
] = other
->bits_
[i
];
2395 new_bits
[k
++] = bits_
[i
];
2400 new_other_bits
.resize(k
);
2402 bits_
.swap(new_bits
);
2403 width_
= GetSize(bits_
);
2405 if (other
!= NULL
) {
2406 other
->bits_
.swap(new_other_bits
);
2407 other
->width_
= GetSize(other
->bits_
);
2413 RTLIL::SigSpec
RTLIL::SigSpec::extract(const RTLIL::SigSpec
&pattern
, const RTLIL::SigSpec
*other
) const
2415 std::set
<RTLIL::SigBit
> pattern_bits
= pattern
.to_sigbit_set();
2416 return extract(pattern_bits
, other
);
2419 RTLIL::SigSpec
RTLIL::SigSpec::extract(const std::set
<RTLIL::SigBit
> &pattern
, const RTLIL::SigSpec
*other
) const
2422 cover("kernel.rtlil.sigspec.extract_other");
2424 cover("kernel.rtlil.sigspec.extract");
2426 log_assert(other
== NULL
|| width_
== other
->width_
);
2428 std::vector
<RTLIL::SigBit
> bits_match
= to_sigbit_vector();
2432 std::vector
<RTLIL::SigBit
> bits_other
= other
->to_sigbit_vector();
2433 for (int i
= 0; i
< width_
; i
++)
2434 if (bits_match
[i
].wire
&& pattern
.count(bits_match
[i
]))
2435 ret
.append_bit(bits_other
[i
]);
2437 for (int i
= 0; i
< width_
; i
++)
2438 if (bits_match
[i
].wire
&& pattern
.count(bits_match
[i
]))
2439 ret
.append_bit(bits_match
[i
]);
2446 void RTLIL::SigSpec::replace(int offset
, const RTLIL::SigSpec
&with
)
2448 cover("kernel.rtlil.sigspec.replace_pos");
2453 log_assert(offset
>= 0);
2454 log_assert(with
.width_
>= 0);
2455 log_assert(offset
+with
.width_
<= width_
);
2457 for (int i
= 0; i
< with
.width_
; i
++)
2458 bits_
.at(offset
+ i
) = with
.bits_
.at(i
);
2463 void RTLIL::SigSpec::remove_const()
2467 cover("kernel.rtlil.sigspec.remove_const.packed");
2469 std::vector
<RTLIL::SigChunk
> new_chunks
;
2470 new_chunks
.reserve(GetSize(chunks_
));
2473 for (auto &chunk
: chunks_
)
2474 if (chunk
.wire
!= NULL
) {
2475 new_chunks
.push_back(chunk
);
2476 width_
+= chunk
.width
;
2479 chunks_
.swap(new_chunks
);
2483 cover("kernel.rtlil.sigspec.remove_const.unpacked");
2485 std::vector
<RTLIL::SigBit
> new_bits
;
2486 new_bits
.reserve(width_
);
2488 for (auto &bit
: bits_
)
2489 if (bit
.wire
!= NULL
)
2490 new_bits
.push_back(bit
);
2492 bits_
.swap(new_bits
);
2493 width_
= bits_
.size();
2499 void RTLIL::SigSpec::remove(int offset
, int length
)
2501 cover("kernel.rtlil.sigspec.remove_pos");
2505 log_assert(offset
>= 0);
2506 log_assert(length
>= 0);
2507 log_assert(offset
+ length
<= width_
);
2509 bits_
.erase(bits_
.begin() + offset
, bits_
.begin() + offset
+ length
);
2510 width_
= bits_
.size();
2515 RTLIL::SigSpec
RTLIL::SigSpec::extract(int offset
, int length
) const
2518 cover("kernel.rtlil.sigspec.extract_pos");
2519 return std::vector
<RTLIL::SigBit
>(bits_
.begin() + offset
, bits_
.begin() + offset
+ length
);
2522 void RTLIL::SigSpec::append(const RTLIL::SigSpec
&signal
)
2524 if (signal
.width_
== 0)
2532 cover("kernel.rtlil.sigspec.append");
2534 if (packed() != signal
.packed()) {
2540 for (auto &other_c
: signal
.chunks_
)
2542 auto &my_last_c
= chunks_
.back();
2543 if (my_last_c
.wire
== NULL
&& other_c
.wire
== NULL
) {
2544 auto &this_data
= my_last_c
.data
;
2545 auto &other_data
= other_c
.data
;
2546 this_data
.insert(this_data
.end(), other_data
.begin(), other_data
.end());
2547 my_last_c
.width
+= other_c
.width
;
2549 if (my_last_c
.wire
== other_c
.wire
&& my_last_c
.offset
+ my_last_c
.width
== other_c
.offset
) {
2550 my_last_c
.width
+= other_c
.width
;
2552 chunks_
.push_back(other_c
);
2555 bits_
.insert(bits_
.end(), signal
.bits_
.begin(), signal
.bits_
.end());
2557 width_
+= signal
.width_
;
2561 void RTLIL::SigSpec::append_bit(const RTLIL::SigBit
&bit
)
2565 cover("kernel.rtlil.sigspec.append_bit.packed");
2567 if (chunks_
.size() == 0)
2568 chunks_
.push_back(bit
);
2570 if (bit
.wire
== NULL
)
2571 if (chunks_
.back().wire
== NULL
) {
2572 chunks_
.back().data
.push_back(bit
.data
);
2573 chunks_
.back().width
++;
2575 chunks_
.push_back(bit
);
2577 if (chunks_
.back().wire
== bit
.wire
&& chunks_
.back().offset
+ chunks_
.back().width
== bit
.offset
)
2578 chunks_
.back().width
++;
2580 chunks_
.push_back(bit
);
2584 cover("kernel.rtlil.sigspec.append_bit.unpacked");
2585 bits_
.push_back(bit
);
2592 void RTLIL::SigSpec::extend(int width
, bool is_signed
)
2594 cover("kernel.rtlil.sigspec.extend");
2599 remove(width
, width_
- width
);
2601 if (width_
< width
) {
2602 RTLIL::SigSpec padding
= width_
> 0 ? extract(width_
- 1, 1) : RTLIL::SigSpec(RTLIL::State::S0
);
2603 if (!is_signed
&& padding
!= RTLIL::SigSpec(RTLIL::State::Sx
) && padding
!= RTLIL::SigSpec(RTLIL::State::Sz
) &&
2604 padding
!= RTLIL::SigSpec(RTLIL::State::Sa
) && padding
!= RTLIL::SigSpec(RTLIL::State::Sm
))
2605 padding
= RTLIL::SigSpec(RTLIL::State::S0
);
2606 while (width_
< width
)
2611 void RTLIL::SigSpec::extend_u0(int width
, bool is_signed
)
2613 cover("kernel.rtlil.sigspec.extend_u0");
2618 remove(width
, width_
- width
);
2620 if (width_
< width
) {
2621 RTLIL::SigSpec padding
= width_
> 0 ? extract(width_
- 1, 1) : RTLIL::SigSpec(RTLIL::State::S0
);
2623 padding
= RTLIL::SigSpec(RTLIL::State::S0
);
2624 while (width_
< width
)
2630 RTLIL::SigSpec
RTLIL::SigSpec::repeat(int num
) const
2632 cover("kernel.rtlil.sigspec.repeat");
2635 for (int i
= 0; i
< num
; i
++)
2641 void RTLIL::SigSpec::check() const
2645 cover("kernel.rtlil.sigspec.check.skip");
2649 cover("kernel.rtlil.sigspec.check.packed");
2652 for (size_t i
= 0; i
< chunks_
.size(); i
++) {
2653 const RTLIL::SigChunk chunk
= chunks_
[i
];
2654 if (chunk
.wire
== NULL
) {
2656 log_assert(chunks_
[i
-1].wire
!= NULL
);
2657 log_assert(chunk
.offset
== 0);
2658 log_assert(chunk
.data
.size() == (size_t)chunk
.width
);
2660 if (i
> 0 && chunks_
[i
-1].wire
== chunk
.wire
)
2661 log_assert(chunk
.offset
!= chunks_
[i
-1].offset
+ chunks_
[i
-1].width
);
2662 log_assert(chunk
.offset
>= 0);
2663 log_assert(chunk
.width
>= 0);
2664 log_assert(chunk
.offset
+ chunk
.width
<= chunk
.wire
->width
);
2665 log_assert(chunk
.data
.size() == 0);
2669 log_assert(w
== width_
);
2670 log_assert(bits_
.empty());
2674 cover("kernel.rtlil.sigspec.check.unpacked");
2676 log_assert(width_
== GetSize(bits_
));
2677 log_assert(chunks_
.empty());
2682 bool RTLIL::SigSpec::operator <(const RTLIL::SigSpec
&other
) const
2684 cover("kernel.rtlil.sigspec.comp_lt");
2689 if (width_
!= other
.width_
)
2690 return width_
< other
.width_
;
2695 if (chunks_
.size() != other
.chunks_
.size())
2696 return chunks_
.size() < other
.chunks_
.size();
2701 if (hash_
!= other
.hash_
)
2702 return hash_
< other
.hash_
;
2704 for (size_t i
= 0; i
< chunks_
.size(); i
++)
2705 if (chunks_
[i
] != other
.chunks_
[i
]) {
2706 cover("kernel.rtlil.sigspec.comp_lt.hash_collision");
2707 return chunks_
[i
] < other
.chunks_
[i
];
2710 cover("kernel.rtlil.sigspec.comp_lt.equal");
2714 bool RTLIL::SigSpec::operator ==(const RTLIL::SigSpec
&other
) const
2716 cover("kernel.rtlil.sigspec.comp_eq");
2721 if (width_
!= other
.width_
)
2727 if (chunks_
.size() != chunks_
.size())
2733 if (hash_
!= other
.hash_
)
2736 for (size_t i
= 0; i
< chunks_
.size(); i
++)
2737 if (chunks_
[i
] != other
.chunks_
[i
]) {
2738 cover("kernel.rtlil.sigspec.comp_eq.hash_collision");
2742 cover("kernel.rtlil.sigspec.comp_eq.equal");
2746 bool RTLIL::SigSpec::is_wire() const
2748 cover("kernel.rtlil.sigspec.is_wire");
2751 return GetSize(chunks_
) == 1 && chunks_
[0].wire
&& chunks_
[0].wire
->width
== width_
;
2754 bool RTLIL::SigSpec::is_chunk() const
2756 cover("kernel.rtlil.sigspec.is_chunk");
2759 return GetSize(chunks_
) == 1;
2762 bool RTLIL::SigSpec::is_fully_const() const
2764 cover("kernel.rtlil.sigspec.is_fully_const");
2767 for (auto it
= chunks_
.begin(); it
!= chunks_
.end(); it
++)
2768 if (it
->width
> 0 && it
->wire
!= NULL
)
2773 bool RTLIL::SigSpec::is_fully_def() const
2775 cover("kernel.rtlil.sigspec.is_fully_def");
2778 for (auto it
= chunks_
.begin(); it
!= chunks_
.end(); it
++) {
2779 if (it
->width
> 0 && it
->wire
!= NULL
)
2781 for (size_t i
= 0; i
< it
->data
.size(); i
++)
2782 if (it
->data
[i
] != RTLIL::State::S0
&& it
->data
[i
] != RTLIL::State::S1
)
2788 bool RTLIL::SigSpec::is_fully_undef() const
2790 cover("kernel.rtlil.sigspec.is_fully_undef");
2793 for (auto it
= chunks_
.begin(); it
!= chunks_
.end(); it
++) {
2794 if (it
->width
> 0 && it
->wire
!= NULL
)
2796 for (size_t i
= 0; i
< it
->data
.size(); i
++)
2797 if (it
->data
[i
] != RTLIL::State::Sx
&& it
->data
[i
] != RTLIL::State::Sz
)
2803 bool RTLIL::SigSpec::has_marked_bits() const
2805 cover("kernel.rtlil.sigspec.has_marked_bits");
2808 for (auto it
= chunks_
.begin(); it
!= chunks_
.end(); it
++)
2809 if (it
->width
> 0 && it
->wire
== NULL
) {
2810 for (size_t i
= 0; i
< it
->data
.size(); i
++)
2811 if (it
->data
[i
] == RTLIL::State::Sm
)
2817 bool RTLIL::SigSpec::as_bool() const
2819 cover("kernel.rtlil.sigspec.as_bool");
2822 log_assert(is_fully_const() && GetSize(chunks_
) <= 1);
2824 return RTLIL::Const(chunks_
[0].data
).as_bool();
2828 int RTLIL::SigSpec::as_int(bool is_signed
) const
2830 cover("kernel.rtlil.sigspec.as_int");
2833 log_assert(is_fully_const() && GetSize(chunks_
) <= 1);
2835 return RTLIL::Const(chunks_
[0].data
).as_int(is_signed
);
2839 std::string
RTLIL::SigSpec::as_string() const
2841 cover("kernel.rtlil.sigspec.as_string");
2845 for (size_t i
= chunks_
.size(); i
> 0; i
--) {
2846 const RTLIL::SigChunk
&chunk
= chunks_
[i
-1];
2847 if (chunk
.wire
!= NULL
)
2848 for (int j
= 0; j
< chunk
.width
; j
++)
2851 str
+= RTLIL::Const(chunk
.data
).as_string();
2856 RTLIL::Const
RTLIL::SigSpec::as_const() const
2858 cover("kernel.rtlil.sigspec.as_const");
2861 log_assert(is_fully_const() && GetSize(chunks_
) <= 1);
2863 return chunks_
[0].data
;
2864 return RTLIL::Const();
2867 RTLIL::Wire
*RTLIL::SigSpec::as_wire() const
2869 cover("kernel.rtlil.sigspec.as_wire");
2872 log_assert(is_wire());
2873 return chunks_
[0].wire
;
2876 RTLIL::SigChunk
RTLIL::SigSpec::as_chunk() const
2878 cover("kernel.rtlil.sigspec.as_chunk");
2881 log_assert(is_chunk());
2885 bool RTLIL::SigSpec::match(std::string pattern
) const
2887 cover("kernel.rtlil.sigspec.match");
2890 std::string str
= as_string();
2891 log_assert(pattern
.size() == str
.size());
2893 for (size_t i
= 0; i
< pattern
.size(); i
++) {
2894 if (pattern
[i
] == ' ')
2896 if (pattern
[i
] == '*') {
2897 if (str
[i
] != 'z' && str
[i
] != 'x')
2901 if (pattern
[i
] != str
[i
])
2908 std::set
<RTLIL::SigBit
> RTLIL::SigSpec::to_sigbit_set() const
2910 cover("kernel.rtlil.sigspec.to_sigbit_set");
2913 std::set
<RTLIL::SigBit
> sigbits
;
2914 for (auto &c
: chunks_
)
2915 for (int i
= 0; i
< c
.width
; i
++)
2916 sigbits
.insert(RTLIL::SigBit(c
, i
));
2920 std::vector
<RTLIL::SigBit
> RTLIL::SigSpec::to_sigbit_vector() const
2922 cover("kernel.rtlil.sigspec.to_sigbit_vector");
2928 std::map
<RTLIL::SigBit
, RTLIL::SigBit
> RTLIL::SigSpec::to_sigbit_map(const RTLIL::SigSpec
&other
) const
2930 cover("kernel.rtlil.sigspec.to_sigbit_map");
2935 log_assert(width_
== other
.width_
);
2937 std::map
<RTLIL::SigBit
, RTLIL::SigBit
> new_map
;
2938 for (int i
= 0; i
< width_
; i
++)
2939 new_map
[bits_
[i
]] = other
.bits_
[i
];
2944 RTLIL::SigBit
RTLIL::SigSpec::to_single_sigbit() const
2946 cover("kernel.rtlil.sigspec.to_single_sigbit");
2949 log_assert(width_
== 1);
2950 for (auto &c
: chunks_
)
2952 return RTLIL::SigBit(c
);
2956 static void sigspec_parse_split(std::vector
<std::string
> &tokens
, const std::string
&text
, char sep
)
2958 size_t start
= 0, end
= 0;
2959 while ((end
= text
.find(sep
, start
)) != std::string::npos
) {
2960 tokens
.push_back(text
.substr(start
, end
- start
));
2963 tokens
.push_back(text
.substr(start
));
2966 static int sigspec_parse_get_dummy_line_num()
2971 bool RTLIL::SigSpec::parse(RTLIL::SigSpec
&sig
, RTLIL::Module
*module
, std::string str
)
2973 cover("kernel.rtlil.sigspec.parse");
2975 std::vector
<std::string
> tokens
;
2976 sigspec_parse_split(tokens
, str
, ',');
2978 sig
= RTLIL::SigSpec();
2979 for (int tokidx
= int(tokens
.size())-1; tokidx
>= 0; tokidx
--)
2981 std::string netname
= tokens
[tokidx
];
2982 std::string indices
;
2984 if (netname
.size() == 0)
2987 if (('0' <= netname
[0] && netname
[0] <= '9') || netname
[0] == '\'') {
2988 cover("kernel.rtlil.sigspec.parse.const");
2989 AST::get_line_num
= sigspec_parse_get_dummy_line_num
;
2990 AST::AstNode
*ast
= VERILOG_FRONTEND::const2ast(netname
);
2993 sig
.append(RTLIL::Const(ast
->bits
));
3001 cover("kernel.rtlil.sigspec.parse.net");
3003 if (netname
[0] != '$' && netname
[0] != '\\')
3004 netname
= "\\" + netname
;
3006 if (module
->wires_
.count(netname
) == 0) {
3007 size_t indices_pos
= netname
.size()-1;
3008 if (indices_pos
> 2 && netname
[indices_pos
] == ']')
3011 while (indices_pos
> 0 && ('0' <= netname
[indices_pos
] && netname
[indices_pos
] <= '9')) indices_pos
--;
3012 if (indices_pos
> 0 && netname
[indices_pos
] == ':') {
3014 while (indices_pos
> 0 && ('0' <= netname
[indices_pos
] && netname
[indices_pos
] <= '9')) indices_pos
--;
3016 if (indices_pos
> 0 && netname
[indices_pos
] == '[') {
3017 indices
= netname
.substr(indices_pos
);
3018 netname
= netname
.substr(0, indices_pos
);
3023 if (module
->wires_
.count(netname
) == 0)
3026 RTLIL::Wire
*wire
= module
->wires_
.at(netname
);
3027 if (!indices
.empty()) {
3028 std::vector
<std::string
> index_tokens
;
3029 sigspec_parse_split(index_tokens
, indices
.substr(1, indices
.size()-2), ':');
3030 if (index_tokens
.size() == 1) {
3031 cover("kernel.rtlil.sigspec.parse.bit_sel");
3032 int a
= atoi(index_tokens
.at(0).c_str());
3033 if (a
< 0 || a
>= wire
->width
)
3035 sig
.append(RTLIL::SigSpec(wire
, a
));
3037 cover("kernel.rtlil.sigspec.parse.part_sel");
3038 int a
= atoi(index_tokens
.at(0).c_str());
3039 int b
= atoi(index_tokens
.at(1).c_str());
3044 if (a
< 0 || a
>= wire
->width
)
3046 if (b
< 0 || b
>= wire
->width
)
3048 sig
.append(RTLIL::SigSpec(wire
, a
, b
-a
+1));
3057 bool RTLIL::SigSpec::parse_sel(RTLIL::SigSpec
&sig
, RTLIL::Design
*design
, RTLIL::Module
*module
, std::string str
)
3059 if (str
.empty() || str
[0] != '@')
3060 return parse(sig
, module
, str
);
3062 cover("kernel.rtlil.sigspec.parse.sel");
3064 str
= RTLIL::escape_id(str
.substr(1));
3065 if (design
->selection_vars
.count(str
) == 0)
3068 sig
= RTLIL::SigSpec();
3069 RTLIL::Selection
&sel
= design
->selection_vars
.at(str
);
3070 for (auto &it
: module
->wires_
)
3071 if (sel
.selected_member(module
->name
, it
.first
))
3072 sig
.append(it
.second
);
3077 bool RTLIL::SigSpec::parse_rhs(const RTLIL::SigSpec
&lhs
, RTLIL::SigSpec
&sig
, RTLIL::Module
*module
, std::string str
)
3080 cover("kernel.rtlil.sigspec.parse.rhs_zeros");
3081 sig
= RTLIL::SigSpec(RTLIL::State::S0
, lhs
.width_
);
3086 cover("kernel.rtlil.sigspec.parse.rhs_ones");
3087 sig
= RTLIL::SigSpec(RTLIL::State::S1
, lhs
.width_
);
3091 if (lhs
.chunks_
.size() == 1) {
3092 char *p
= (char*)str
.c_str(), *endptr
;
3093 long int val
= strtol(p
, &endptr
, 10);
3094 if (endptr
&& endptr
!= p
&& *endptr
== 0) {
3095 sig
= RTLIL::SigSpec(val
, lhs
.width_
);
3096 cover("kernel.rtlil.sigspec.parse.rhs_dec");
3101 return parse(sig
, module
, str
);
3104 RTLIL::CaseRule::~CaseRule()
3106 for (auto it
= switches
.begin(); it
!= switches
.end(); it
++)
3110 RTLIL::CaseRule
*RTLIL::CaseRule::clone() const
3112 RTLIL::CaseRule
*new_caserule
= new RTLIL::CaseRule
;
3113 new_caserule
->compare
= compare
;
3114 new_caserule
->actions
= actions
;
3115 for (auto &it
: switches
)
3116 new_caserule
->switches
.push_back(it
->clone());
3117 return new_caserule
;
3120 RTLIL::SwitchRule::~SwitchRule()
3122 for (auto it
= cases
.begin(); it
!= cases
.end(); it
++)
3126 RTLIL::SwitchRule
*RTLIL::SwitchRule::clone() const
3128 RTLIL::SwitchRule
*new_switchrule
= new RTLIL::SwitchRule
;
3129 new_switchrule
->signal
= signal
;
3130 new_switchrule
->attributes
= attributes
;
3131 for (auto &it
: cases
)
3132 new_switchrule
->cases
.push_back(it
->clone());
3133 return new_switchrule
;
3137 RTLIL::SyncRule
*RTLIL::SyncRule::clone() const
3139 RTLIL::SyncRule
*new_syncrule
= new RTLIL::SyncRule
;
3140 new_syncrule
->type
= type
;
3141 new_syncrule
->signal
= signal
;
3142 new_syncrule
->actions
= actions
;
3143 return new_syncrule
;
3146 RTLIL::Process::~Process()
3148 for (auto it
= syncs
.begin(); it
!= syncs
.end(); it
++)
3152 RTLIL::Process
*RTLIL::Process::clone() const
3154 RTLIL::Process
*new_proc
= new RTLIL::Process
;
3156 new_proc
->name
= name
;
3157 new_proc
->attributes
= attributes
;
3159 RTLIL::CaseRule
*rc_ptr
= root_case
.clone();
3160 new_proc
->root_case
= *rc_ptr
;
3161 rc_ptr
->switches
.clear();
3164 for (auto &it
: syncs
)
3165 new_proc
->syncs
.push_back(it
->clone());