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Added $lut support in test_cell, techmap, satgen
[yosys.git] / kernel / rtlil.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 #include "kernel/yosys.h"
21 #include "frontends/verilog/verilog_frontend.h"
22 #include "backends/ilang/ilang_backend.h"
23
24 #include <string.h>
25 #include <algorithm>
26
27 YOSYS_NAMESPACE_BEGIN
28
29 std::vector<int> RTLIL::IdString::global_refcount_storage_;
30 std::vector<char*> RTLIL::IdString::global_id_storage_;
31 std::map<char*, int, RTLIL::IdString::char_ptr_cmp> RTLIL::IdString::global_id_index_;
32 std::vector<int> RTLIL::IdString::global_free_idx_list_;
33
34 RTLIL::Const::Const()
35 {
36 flags = RTLIL::CONST_FLAG_NONE;
37 }
38
39 RTLIL::Const::Const(std::string str)
40 {
41 flags = RTLIL::CONST_FLAG_STRING;
42 for (int i = str.size()-1; i >= 0; i--) {
43 unsigned char ch = str[i];
44 for (int j = 0; j < 8; j++) {
45 bits.push_back((ch & 1) != 0 ? RTLIL::S1 : RTLIL::S0);
46 ch = ch >> 1;
47 }
48 }
49 }
50
51 RTLIL::Const::Const(int val, int width)
52 {
53 flags = RTLIL::CONST_FLAG_NONE;
54 for (int i = 0; i < width; i++) {
55 bits.push_back((val & 1) != 0 ? RTLIL::S1 : RTLIL::S0);
56 val = val >> 1;
57 }
58 }
59
60 RTLIL::Const::Const(RTLIL::State bit, int width)
61 {
62 flags = RTLIL::CONST_FLAG_NONE;
63 for (int i = 0; i < width; i++)
64 bits.push_back(bit);
65 }
66
67 bool RTLIL::Const::operator <(const RTLIL::Const &other) const
68 {
69 if (bits.size() != other.bits.size())
70 return bits.size() < other.bits.size();
71 for (size_t i = 0; i < bits.size(); i++)
72 if (bits[i] != other.bits[i])
73 return bits[i] < other.bits[i];
74 return false;
75 }
76
77 bool RTLIL::Const::operator ==(const RTLIL::Const &other) const
78 {
79 return bits == other.bits;
80 }
81
82 bool RTLIL::Const::operator !=(const RTLIL::Const &other) const
83 {
84 return bits != other.bits;
85 }
86
87 bool RTLIL::Const::as_bool() const
88 {
89 for (size_t i = 0; i < bits.size(); i++)
90 if (bits[i] == RTLIL::S1)
91 return true;
92 return false;
93 }
94
95 int RTLIL::Const::as_int(bool is_signed) const
96 {
97 int32_t ret = 0;
98 for (size_t i = 0; i < bits.size() && i < 32; i++)
99 if (bits[i] == RTLIL::S1)
100 ret |= 1 << i;
101 if (is_signed && bits.back() == RTLIL::S1)
102 for (size_t i = bits.size(); i < 32; i++)
103 ret |= 1 << i;
104 return ret;
105 }
106
107 std::string RTLIL::Const::as_string() const
108 {
109 std::string ret;
110 for (size_t i = bits.size(); i > 0; i--)
111 switch (bits[i-1]) {
112 case S0: ret += "0"; break;
113 case S1: ret += "1"; break;
114 case Sx: ret += "x"; break;
115 case Sz: ret += "z"; break;
116 case Sa: ret += "-"; break;
117 case Sm: ret += "m"; break;
118 }
119 return ret;
120 }
121
122 std::string RTLIL::Const::decode_string() const
123 {
124 std::string string;
125 std::vector <char> string_chars;
126 for (int i = 0; i < int (bits.size()); i += 8) {
127 char ch = 0;
128 for (int j = 0; j < 8 && i + j < int (bits.size()); j++)
129 if (bits[i + j] == RTLIL::State::S1)
130 ch |= 1 << j;
131 if (ch != 0)
132 string_chars.push_back(ch);
133 }
134 for (int i = int (string_chars.size()) - 1; i >= 0; i--)
135 string += string_chars[i];
136 return string;
137 }
138
139 bool RTLIL::Selection::selected_module(RTLIL::IdString mod_name) const
140 {
141 if (full_selection)
142 return true;
143 if (selected_modules.count(mod_name) > 0)
144 return true;
145 if (selected_members.count(mod_name) > 0)
146 return true;
147 return false;
148 }
149
150 bool RTLIL::Selection::selected_whole_module(RTLIL::IdString mod_name) const
151 {
152 if (full_selection)
153 return true;
154 if (selected_modules.count(mod_name) > 0)
155 return true;
156 return false;
157 }
158
159 bool RTLIL::Selection::selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const
160 {
161 if (full_selection)
162 return true;
163 if (selected_modules.count(mod_name) > 0)
164 return true;
165 if (selected_members.count(mod_name) > 0)
166 if (selected_members.at(mod_name).count(memb_name) > 0)
167 return true;
168 return false;
169 }
170
171 void RTLIL::Selection::optimize(RTLIL::Design *design)
172 {
173 if (full_selection) {
174 selected_modules.clear();
175 selected_members.clear();
176 return;
177 }
178
179 std::vector<RTLIL::IdString> del_list, add_list;
180
181 del_list.clear();
182 for (auto mod_name : selected_modules) {
183 if (design->modules_.count(mod_name) == 0)
184 del_list.push_back(mod_name);
185 selected_members.erase(mod_name);
186 }
187 for (auto mod_name : del_list)
188 selected_modules.erase(mod_name);
189
190 del_list.clear();
191 for (auto &it : selected_members)
192 if (design->modules_.count(it.first) == 0)
193 del_list.push_back(it.first);
194 for (auto mod_name : del_list)
195 selected_members.erase(mod_name);
196
197 for (auto &it : selected_members) {
198 del_list.clear();
199 for (auto memb_name : it.second)
200 if (design->modules_[it.first]->count_id(memb_name) == 0)
201 del_list.push_back(memb_name);
202 for (auto memb_name : del_list)
203 it.second.erase(memb_name);
204 }
205
206 del_list.clear();
207 add_list.clear();
208 for (auto &it : selected_members)
209 if (it.second.size() == 0)
210 del_list.push_back(it.first);
211 else if (it.second.size() == design->modules_[it.first]->wires_.size() + design->modules_[it.first]->memories.size() +
212 design->modules_[it.first]->cells_.size() + design->modules_[it.first]->processes.size())
213 add_list.push_back(it.first);
214 for (auto mod_name : del_list)
215 selected_members.erase(mod_name);
216 for (auto mod_name : add_list) {
217 selected_members.erase(mod_name);
218 selected_modules.insert(mod_name);
219 }
220
221 if (selected_modules.size() == design->modules_.size()) {
222 full_selection = true;
223 selected_modules.clear();
224 selected_members.clear();
225 }
226 }
227
228 RTLIL::Design::Design()
229 {
230 refcount_modules_ = 0;
231 }
232
233 RTLIL::Design::~Design()
234 {
235 for (auto it = modules_.begin(); it != modules_.end(); it++)
236 delete it->second;
237 }
238
239 RTLIL::ObjRange<RTLIL::Module*> RTLIL::Design::modules()
240 {
241 return RTLIL::ObjRange<RTLIL::Module*>(&modules_, &refcount_modules_);
242 }
243
244 RTLIL::Module *RTLIL::Design::module(RTLIL::IdString name)
245 {
246 return modules_.count(name) ? modules_.at(name) : NULL;
247 }
248
249 void RTLIL::Design::add(RTLIL::Module *module)
250 {
251 log_assert(modules_.count(module->name) == 0);
252 log_assert(refcount_modules_ == 0);
253 modules_[module->name] = module;
254 module->design = this;
255
256 for (auto mon : monitors)
257 mon->notify_module_add(module);
258 }
259
260 RTLIL::Module *RTLIL::Design::addModule(RTLIL::IdString name)
261 {
262 log_assert(modules_.count(name) == 0);
263 log_assert(refcount_modules_ == 0);
264
265 RTLIL::Module *module = new RTLIL::Module;
266 modules_[name] = module;
267 module->design = this;
268 module->name = name;
269
270 for (auto mon : monitors)
271 mon->notify_module_add(module);
272
273 return module;
274 }
275
276 void RTLIL::Design::scratchpad_unset(std::string varname)
277 {
278 scratchpad.erase(varname);
279 }
280
281 void RTLIL::Design::scratchpad_set_int(std::string varname, int value)
282 {
283 scratchpad[varname] = stringf("%d", value);
284 }
285
286 void RTLIL::Design::scratchpad_set_bool(std::string varname, bool value)
287 {
288 scratchpad[varname] = value ? "true" : "false";
289 }
290
291 void RTLIL::Design::scratchpad_set_string(std::string varname, std::string value)
292 {
293 scratchpad[varname] = value;
294 }
295
296 int RTLIL::Design::scratchpad_get_int(std::string varname, int default_value) const
297 {
298 if (scratchpad.count(varname) == 0)
299 return default_value;
300
301 std::string str = scratchpad.at(varname);
302
303 if (str == "0" || str == "false")
304 return 0;
305
306 if (str == "1" || str == "true")
307 return 1;
308
309 char *endptr = nullptr;
310 long int parsed_value = strtol(str.c_str(), &endptr, 10);
311 return *endptr ? default_value : parsed_value;
312 }
313
314 bool RTLIL::Design::scratchpad_get_bool(std::string varname, bool default_value) const
315 {
316 if (scratchpad.count(varname) == 0)
317 return default_value;
318
319 std::string str = scratchpad.at(varname);
320
321 if (str == "0" || str == "false")
322 return false;
323
324 if (str == "1" || str == "true")
325 return true;
326
327 return default_value;
328 }
329
330 std::string RTLIL::Design::scratchpad_get_string(std::string varname, std::string default_value) const
331 {
332 if (scratchpad.count(varname) == 0)
333 return default_value;
334 return scratchpad.at(varname);
335 }
336
337 void RTLIL::Design::remove(RTLIL::Module *module)
338 {
339 for (auto mon : monitors)
340 mon->notify_module_del(module);
341
342 log_assert(modules_.at(module->name) == module);
343 modules_.erase(module->name);
344 delete module;
345 }
346
347 void RTLIL::Design::check()
348 {
349 #ifndef NDEBUG
350 for (auto &it : modules_) {
351 log_assert(this == it.second->design);
352 log_assert(it.first == it.second->name);
353 log_assert(!it.first.empty());
354 it.second->check();
355 }
356 #endif
357 }
358
359 void RTLIL::Design::optimize()
360 {
361 for (auto &it : modules_)
362 it.second->optimize();
363 for (auto &it : selection_stack)
364 it.optimize(this);
365 for (auto &it : selection_vars)
366 it.second.optimize(this);
367 }
368
369 bool RTLIL::Design::selected_module(RTLIL::IdString mod_name) const
370 {
371 if (!selected_active_module.empty() && mod_name != selected_active_module)
372 return false;
373 if (selection_stack.size() == 0)
374 return true;
375 return selection_stack.back().selected_module(mod_name);
376 }
377
378 bool RTLIL::Design::selected_whole_module(RTLIL::IdString mod_name) const
379 {
380 if (!selected_active_module.empty() && mod_name != selected_active_module)
381 return false;
382 if (selection_stack.size() == 0)
383 return true;
384 return selection_stack.back().selected_whole_module(mod_name);
385 }
386
387 bool RTLIL::Design::selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const
388 {
389 if (!selected_active_module.empty() && mod_name != selected_active_module)
390 return false;
391 if (selection_stack.size() == 0)
392 return true;
393 return selection_stack.back().selected_member(mod_name, memb_name);
394 }
395
396 bool RTLIL::Design::selected_module(RTLIL::Module *mod) const
397 {
398 return selected_module(mod->name);
399 }
400
401 bool RTLIL::Design::selected_whole_module(RTLIL::Module *mod) const
402 {
403 return selected_whole_module(mod->name);
404 }
405
406 std::vector<RTLIL::Module*> RTLIL::Design::selected_modules() const
407 {
408 std::vector<RTLIL::Module*> result;
409 result.reserve(modules_.size());
410 for (auto &it : modules_)
411 if (selected_module(it.first))
412 result.push_back(it.second);
413 return result;
414 }
415
416 std::vector<RTLIL::Module*> RTLIL::Design::selected_whole_modules() const
417 {
418 std::vector<RTLIL::Module*> result;
419 result.reserve(modules_.size());
420 for (auto &it : modules_)
421 if (selected_whole_module(it.first))
422 result.push_back(it.second);
423 return result;
424 }
425
426 std::vector<RTLIL::Module*> RTLIL::Design::selected_whole_modules_warn() const
427 {
428 std::vector<RTLIL::Module*> result;
429 result.reserve(modules_.size());
430 for (auto &it : modules_)
431 if (selected_whole_module(it.first))
432 result.push_back(it.second);
433 else if (selected_module(it.first))
434 log("Warning: Ignoring partially selected module %s.\n", log_id(it.first));
435 return result;
436 }
437
438 RTLIL::Module::Module()
439 {
440 design = nullptr;
441 refcount_wires_ = 0;
442 refcount_cells_ = 0;
443 }
444
445 RTLIL::Module::~Module()
446 {
447 for (auto it = wires_.begin(); it != wires_.end(); it++)
448 delete it->second;
449 for (auto it = memories.begin(); it != memories.end(); it++)
450 delete it->second;
451 for (auto it = cells_.begin(); it != cells_.end(); it++)
452 delete it->second;
453 for (auto it = processes.begin(); it != processes.end(); it++)
454 delete it->second;
455 }
456
457 RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, std::map<RTLIL::IdString, RTLIL::Const>)
458 {
459 log_error("Module `%s' is used with parameters but is not parametric!\n", id2cstr(name));
460 }
461
462 size_t RTLIL::Module::count_id(RTLIL::IdString id)
463 {
464 return wires_.count(id) + memories.count(id) + cells_.count(id) + processes.count(id);
465 }
466
467 #ifndef NDEBUG
468 namespace {
469 struct InternalCellChecker
470 {
471 RTLIL::Module *module;
472 RTLIL::Cell *cell;
473 std::set<RTLIL::IdString> expected_params, expected_ports;
474
475 InternalCellChecker(RTLIL::Module *module, RTLIL::Cell *cell) : module(module), cell(cell) { }
476
477 void error(int linenr)
478 {
479 std::stringstream buf;
480 ILANG_BACKEND::dump_cell(buf, " ", cell);
481
482 log_error("Found error in internal cell %s%s%s (%s) at %s:%d:\n%s",
483 module ? module->name.c_str() : "", module ? "." : "",
484 cell->name.c_str(), cell->type.c_str(), __FILE__, linenr, buf.str().c_str());
485 }
486
487 int param(const char *name)
488 {
489 if (cell->parameters.count(name) == 0)
490 error(__LINE__);
491 expected_params.insert(name);
492 return cell->parameters.at(name).as_int();
493 }
494
495 int param_bool(const char *name)
496 {
497 int v = param(name);
498 if (cell->parameters.at(name).bits.size() > 32)
499 error(__LINE__);
500 if (v != 0 && v != 1)
501 error(__LINE__);
502 return v;
503 }
504
505 void param_bits(const char *name, int width)
506 {
507 param(name);
508 if (int(cell->parameters.at(name).bits.size()) != width)
509 error(__LINE__);
510 }
511
512 void port(const char *name, int width)
513 {
514 if (!cell->hasPort(name))
515 error(__LINE__);
516 if (cell->getPort(name).size() != width)
517 error(__LINE__);
518 expected_ports.insert(name);
519 }
520
521 void check_expected(bool check_matched_sign = true)
522 {
523 for (auto &para : cell->parameters)
524 if (expected_params.count(para.first) == 0)
525 error(__LINE__);
526 for (auto &conn : cell->connections())
527 if (expected_ports.count(conn.first) == 0)
528 error(__LINE__);
529
530 if (expected_params.count("\\A_SIGNED") != 0 && expected_params.count("\\B_SIGNED") && check_matched_sign) {
531 bool a_is_signed = param("\\A_SIGNED") != 0;
532 bool b_is_signed = param("\\B_SIGNED") != 0;
533 if (a_is_signed != b_is_signed)
534 error(__LINE__);
535 }
536 }
537
538 void check_gate(const char *ports)
539 {
540 if (cell->parameters.size() != 0)
541 error(__LINE__);
542
543 for (const char *p = ports; *p; p++) {
544 char portname[3] = { '\\', *p, 0 };
545 if (!cell->hasPort(portname))
546 error(__LINE__);
547 if (cell->getPort(portname).size() != 1)
548 error(__LINE__);
549 }
550
551 for (auto &conn : cell->connections()) {
552 if (conn.first.size() != 2 || conn.first[0] != '\\')
553 error(__LINE__);
554 if (strchr(ports, conn.first[1]) == NULL)
555 error(__LINE__);
556 }
557 }
558
559 void check()
560 {
561 if (cell->type.substr(0, 1) != "$" || cell->type.substr(0, 3) == "$__" || cell->type.substr(0, 8) == "$paramod" ||
562 cell->type.substr(0, 9) == "$verific$" || cell->type.substr(0, 7) == "$array:" || cell->type.substr(0, 8) == "$extern:")
563 return;
564
565 if (cell->type.in("$not", "$pos", "$bu0", "$neg")) {
566 param_bool("\\A_SIGNED");
567 port("\\A", param("\\A_WIDTH"));
568 port("\\Y", param("\\Y_WIDTH"));
569 check_expected();
570 return;
571 }
572
573 if (cell->type.in("$and", "$or", "$xor", "$xnor")) {
574 param_bool("\\A_SIGNED");
575 param_bool("\\B_SIGNED");
576 port("\\A", param("\\A_WIDTH"));
577 port("\\B", param("\\B_WIDTH"));
578 port("\\Y", param("\\Y_WIDTH"));
579 check_expected();
580 return;
581 }
582
583 if (cell->type.in("$reduce_and", "$reduce_or", "$reduce_xor", "$reduce_xnor", "$reduce_bool")) {
584 param_bool("\\A_SIGNED");
585 port("\\A", param("\\A_WIDTH"));
586 port("\\Y", param("\\Y_WIDTH"));
587 check_expected();
588 return;
589 }
590
591 if (cell->type.in("$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx")) {
592 param_bool("\\A_SIGNED");
593 param_bool("\\B_SIGNED");
594 port("\\A", param("\\A_WIDTH"));
595 port("\\B", param("\\B_WIDTH"));
596 port("\\Y", param("\\Y_WIDTH"));
597 check_expected(false);
598 return;
599 }
600
601 if (cell->type.in("$lt", "$le", "$eq", "$ne", "$eqx", "$nex", "$ge", "$gt")) {
602 param_bool("\\A_SIGNED");
603 param_bool("\\B_SIGNED");
604 port("\\A", param("\\A_WIDTH"));
605 port("\\B", param("\\B_WIDTH"));
606 port("\\Y", param("\\Y_WIDTH"));
607 check_expected();
608 return;
609 }
610
611 if (cell->type.in("$add", "$sub", "$mul", "$div", "$mod", "$pow")) {
612 param_bool("\\A_SIGNED");
613 param_bool("\\B_SIGNED");
614 port("\\A", param("\\A_WIDTH"));
615 port("\\B", param("\\B_WIDTH"));
616 port("\\Y", param("\\Y_WIDTH"));
617 check_expected(cell->type != "$pow");
618 return;
619 }
620
621 if (cell->type == "$alu") {
622 param_bool("\\A_SIGNED");
623 param_bool("\\B_SIGNED");
624 port("\\A", param("\\A_WIDTH"));
625 port("\\B", param("\\B_WIDTH"));
626 port("\\CI", 1);
627 port("\\BI", 1);
628 port("\\X", param("\\Y_WIDTH"));
629 port("\\Y", param("\\Y_WIDTH"));
630 port("\\CO", param("\\Y_WIDTH"));
631 check_expected();
632 return;
633 }
634
635 if (cell->type == "$logic_not") {
636 param_bool("\\A_SIGNED");
637 port("\\A", param("\\A_WIDTH"));
638 port("\\Y", param("\\Y_WIDTH"));
639 check_expected();
640 return;
641 }
642
643 if (cell->type == "$logic_and" || cell->type == "$logic_or") {
644 param_bool("\\A_SIGNED");
645 param_bool("\\B_SIGNED");
646 port("\\A", param("\\A_WIDTH"));
647 port("\\B", param("\\B_WIDTH"));
648 port("\\Y", param("\\Y_WIDTH"));
649 check_expected(false);
650 return;
651 }
652
653 if (cell->type == "$slice") {
654 param("\\OFFSET");
655 port("\\A", param("\\A_WIDTH"));
656 port("\\Y", param("\\Y_WIDTH"));
657 if (param("\\OFFSET") + param("\\Y_WIDTH") > param("\\A_WIDTH"))
658 error(__LINE__);
659 check_expected();
660 return;
661 }
662
663 if (cell->type == "$concat") {
664 port("\\A", param("\\A_WIDTH"));
665 port("\\B", param("\\B_WIDTH"));
666 port("\\Y", param("\\A_WIDTH") + param("\\B_WIDTH"));
667 check_expected();
668 return;
669 }
670
671 if (cell->type == "$mux") {
672 port("\\A", param("\\WIDTH"));
673 port("\\B", param("\\WIDTH"));
674 port("\\S", 1);
675 port("\\Y", param("\\WIDTH"));
676 check_expected();
677 return;
678 }
679
680 if (cell->type == "$pmux") {
681 port("\\A", param("\\WIDTH"));
682 port("\\B", param("\\WIDTH") * param("\\S_WIDTH"));
683 port("\\S", param("\\S_WIDTH"));
684 port("\\Y", param("\\WIDTH"));
685 check_expected();
686 return;
687 }
688
689 if (cell->type == "$lut") {
690 param("\\LUT");
691 port("\\A", param("\\WIDTH"));
692 port("\\Y", 1);
693 check_expected();
694 return;
695 }
696
697 if (cell->type == "$sr") {
698 param_bool("\\SET_POLARITY");
699 param_bool("\\CLR_POLARITY");
700 port("\\SET", param("\\WIDTH"));
701 port("\\CLR", param("\\WIDTH"));
702 port("\\Q", param("\\WIDTH"));
703 check_expected();
704 return;
705 }
706
707 if (cell->type == "$dff") {
708 param_bool("\\CLK_POLARITY");
709 port("\\CLK", 1);
710 port("\\D", param("\\WIDTH"));
711 port("\\Q", param("\\WIDTH"));
712 check_expected();
713 return;
714 }
715
716 if (cell->type == "$dffsr") {
717 param_bool("\\CLK_POLARITY");
718 param_bool("\\SET_POLARITY");
719 param_bool("\\CLR_POLARITY");
720 port("\\CLK", 1);
721 port("\\SET", param("\\WIDTH"));
722 port("\\CLR", param("\\WIDTH"));
723 port("\\D", param("\\WIDTH"));
724 port("\\Q", param("\\WIDTH"));
725 check_expected();
726 return;
727 }
728
729 if (cell->type == "$adff") {
730 param_bool("\\CLK_POLARITY");
731 param_bool("\\ARST_POLARITY");
732 param_bits("\\ARST_VALUE", param("\\WIDTH"));
733 port("\\CLK", 1);
734 port("\\ARST", 1);
735 port("\\D", param("\\WIDTH"));
736 port("\\Q", param("\\WIDTH"));
737 check_expected();
738 return;
739 }
740
741 if (cell->type == "$dlatch") {
742 param_bool("\\EN_POLARITY");
743 port("\\EN", 1);
744 port("\\D", param("\\WIDTH"));
745 port("\\Q", param("\\WIDTH"));
746 check_expected();
747 return;
748 }
749
750 if (cell->type == "$dlatchsr") {
751 param_bool("\\EN_POLARITY");
752 param_bool("\\SET_POLARITY");
753 param_bool("\\CLR_POLARITY");
754 port("\\EN", 1);
755 port("\\SET", param("\\WIDTH"));
756 port("\\CLR", param("\\WIDTH"));
757 port("\\D", param("\\WIDTH"));
758 port("\\Q", param("\\WIDTH"));
759 check_expected();
760 return;
761 }
762
763 if (cell->type == "$fsm") {
764 param("\\NAME");
765 param_bool("\\CLK_POLARITY");
766 param_bool("\\ARST_POLARITY");
767 param("\\STATE_BITS");
768 param("\\STATE_NUM");
769 param("\\STATE_NUM_LOG2");
770 param("\\STATE_RST");
771 param_bits("\\STATE_TABLE", param("\\STATE_BITS") * param("\\STATE_NUM"));
772 param("\\TRANS_NUM");
773 param_bits("\\TRANS_TABLE", param("\\TRANS_NUM") * (2*param("\\STATE_NUM_LOG2") + param("\\CTRL_IN_WIDTH") + param("\\CTRL_OUT_WIDTH")));
774 port("\\CLK", 1);
775 port("\\ARST", 1);
776 port("\\CTRL_IN", param("\\CTRL_IN_WIDTH"));
777 port("\\CTRL_OUT", param("\\CTRL_OUT_WIDTH"));
778 check_expected();
779 return;
780 }
781
782 if (cell->type == "$memrd") {
783 param("\\MEMID");
784 param_bool("\\CLK_ENABLE");
785 param_bool("\\CLK_POLARITY");
786 param_bool("\\TRANSPARENT");
787 port("\\CLK", 1);
788 port("\\ADDR", param("\\ABITS"));
789 port("\\DATA", param("\\WIDTH"));
790 check_expected();
791 return;
792 }
793
794 if (cell->type == "$memwr") {
795 param("\\MEMID");
796 param_bool("\\CLK_ENABLE");
797 param_bool("\\CLK_POLARITY");
798 param("\\PRIORITY");
799 port("\\CLK", 1);
800 port("\\EN", param("\\WIDTH"));
801 port("\\ADDR", param("\\ABITS"));
802 port("\\DATA", param("\\WIDTH"));
803 check_expected();
804 return;
805 }
806
807 if (cell->type == "$mem") {
808 param("\\MEMID");
809 param("\\SIZE");
810 param("\\OFFSET");
811 param_bits("\\RD_CLK_ENABLE", param("\\RD_PORTS"));
812 param_bits("\\RD_CLK_POLARITY", param("\\RD_PORTS"));
813 param_bits("\\RD_TRANSPARENT", param("\\RD_PORTS"));
814 param_bits("\\WR_CLK_ENABLE", param("\\WR_PORTS"));
815 param_bits("\\WR_CLK_POLARITY", param("\\WR_PORTS"));
816 port("\\RD_CLK", param("\\RD_PORTS"));
817 port("\\RD_ADDR", param("\\RD_PORTS") * param("\\ABITS"));
818 port("\\RD_DATA", param("\\RD_PORTS") * param("\\WIDTH"));
819 port("\\WR_CLK", param("\\WR_PORTS"));
820 port("\\WR_EN", param("\\WR_PORTS") * param("\\WIDTH"));
821 port("\\WR_ADDR", param("\\WR_PORTS") * param("\\ABITS"));
822 port("\\WR_DATA", param("\\WR_PORTS") * param("\\WIDTH"));
823 check_expected();
824 return;
825 }
826
827 if (cell->type == "$assert") {
828 port("\\A", 1);
829 port("\\EN", 1);
830 check_expected();
831 return;
832 }
833
834 if (cell->type == "$_NOT_") { check_gate("AY"); return; }
835 if (cell->type == "$_AND_") { check_gate("ABY"); return; }
836 if (cell->type == "$_NAND_") { check_gate("ABY"); return; }
837 if (cell->type == "$_OR_") { check_gate("ABY"); return; }
838 if (cell->type == "$_NOR_") { check_gate("ABY"); return; }
839 if (cell->type == "$_XOR_") { check_gate("ABY"); return; }
840 if (cell->type == "$_XNOR_") { check_gate("ABY"); return; }
841 if (cell->type == "$_MUX_") { check_gate("ABSY"); return; }
842 if (cell->type == "$_AOI3_") { check_gate("ABCY"); return; }
843 if (cell->type == "$_OAI3_") { check_gate("ABCY"); return; }
844 if (cell->type == "$_AOI4_") { check_gate("ABCDY"); return; }
845 if (cell->type == "$_OAI4_") { check_gate("ABCDY"); return; }
846
847 if (cell->type == "$_SR_NN_") { check_gate("SRQ"); return; }
848 if (cell->type == "$_SR_NP_") { check_gate("SRQ"); return; }
849 if (cell->type == "$_SR_PN_") { check_gate("SRQ"); return; }
850 if (cell->type == "$_SR_PP_") { check_gate("SRQ"); return; }
851
852 if (cell->type == "$_DFF_N_") { check_gate("DQC"); return; }
853 if (cell->type == "$_DFF_P_") { check_gate("DQC"); return; }
854
855 if (cell->type == "$_DFF_NN0_") { check_gate("DQCR"); return; }
856 if (cell->type == "$_DFF_NN1_") { check_gate("DQCR"); return; }
857 if (cell->type == "$_DFF_NP0_") { check_gate("DQCR"); return; }
858 if (cell->type == "$_DFF_NP1_") { check_gate("DQCR"); return; }
859 if (cell->type == "$_DFF_PN0_") { check_gate("DQCR"); return; }
860 if (cell->type == "$_DFF_PN1_") { check_gate("DQCR"); return; }
861 if (cell->type == "$_DFF_PP0_") { check_gate("DQCR"); return; }
862 if (cell->type == "$_DFF_PP1_") { check_gate("DQCR"); return; }
863
864 if (cell->type == "$_DFFSR_NNN_") { check_gate("CSRDQ"); return; }
865 if (cell->type == "$_DFFSR_NNP_") { check_gate("CSRDQ"); return; }
866 if (cell->type == "$_DFFSR_NPN_") { check_gate("CSRDQ"); return; }
867 if (cell->type == "$_DFFSR_NPP_") { check_gate("CSRDQ"); return; }
868 if (cell->type == "$_DFFSR_PNN_") { check_gate("CSRDQ"); return; }
869 if (cell->type == "$_DFFSR_PNP_") { check_gate("CSRDQ"); return; }
870 if (cell->type == "$_DFFSR_PPN_") { check_gate("CSRDQ"); return; }
871 if (cell->type == "$_DFFSR_PPP_") { check_gate("CSRDQ"); return; }
872
873 if (cell->type == "$_DLATCH_N_") { check_gate("EDQ"); return; }
874 if (cell->type == "$_DLATCH_P_") { check_gate("EDQ"); return; }
875
876 if (cell->type == "$_DLATCHSR_NNN_") { check_gate("ESRDQ"); return; }
877 if (cell->type == "$_DLATCHSR_NNP_") { check_gate("ESRDQ"); return; }
878 if (cell->type == "$_DLATCHSR_NPN_") { check_gate("ESRDQ"); return; }
879 if (cell->type == "$_DLATCHSR_NPP_") { check_gate("ESRDQ"); return; }
880 if (cell->type == "$_DLATCHSR_PNN_") { check_gate("ESRDQ"); return; }
881 if (cell->type == "$_DLATCHSR_PNP_") { check_gate("ESRDQ"); return; }
882 if (cell->type == "$_DLATCHSR_PPN_") { check_gate("ESRDQ"); return; }
883 if (cell->type == "$_DLATCHSR_PPP_") { check_gate("ESRDQ"); return; }
884
885 error(__LINE__);
886 }
887 };
888 }
889 #endif
890
891 void RTLIL::Module::check()
892 {
893 #ifndef NDEBUG
894 std::vector<bool> ports_declared;
895 for (auto &it : wires_) {
896 log_assert(this == it.second->module);
897 log_assert(it.first == it.second->name);
898 log_assert(!it.first.empty());
899 log_assert(it.second->width >= 0);
900 log_assert(it.second->port_id >= 0);
901 for (auto &it2 : it.second->attributes)
902 log_assert(!it2.first.empty());
903 if (it.second->port_id) {
904 log_assert(SIZE(ports) >= it.second->port_id);
905 log_assert(ports.at(it.second->port_id-1) == it.first);
906 log_assert(it.second->port_input || it.second->port_output);
907 if (SIZE(ports_declared) < it.second->port_id)
908 ports_declared.resize(it.second->port_id);
909 log_assert(ports_declared[it.second->port_id-1] == false);
910 ports_declared[it.second->port_id-1] = true;
911 } else
912 log_assert(!it.second->port_input && !it.second->port_output);
913 }
914 for (auto port_declared : ports_declared)
915 log_assert(port_declared == true);
916 log_assert(SIZE(ports) == SIZE(ports_declared));
917
918 for (auto &it : memories) {
919 log_assert(it.first == it.second->name);
920 log_assert(!it.first.empty());
921 log_assert(it.second->width >= 0);
922 log_assert(it.second->size >= 0);
923 for (auto &it2 : it.second->attributes)
924 log_assert(!it2.first.empty());
925 }
926
927 for (auto &it : cells_) {
928 log_assert(this == it.second->module);
929 log_assert(it.first == it.second->name);
930 log_assert(!it.first.empty());
931 log_assert(!it.second->type.empty());
932 for (auto &it2 : it.second->connections()) {
933 log_assert(!it2.first.empty());
934 it2.second.check();
935 }
936 for (auto &it2 : it.second->attributes)
937 log_assert(!it2.first.empty());
938 for (auto &it2 : it.second->parameters)
939 log_assert(!it2.first.empty());
940 InternalCellChecker checker(this, it.second);
941 checker.check();
942 }
943
944 for (auto &it : processes) {
945 log_assert(it.first == it.second->name);
946 log_assert(!it.first.empty());
947 // FIXME: More checks here..
948 }
949
950 for (auto &it : connections_) {
951 log_assert(it.first.size() == it.second.size());
952 it.first.check();
953 it.second.check();
954 }
955
956 for (auto &it : attributes)
957 log_assert(!it.first.empty());
958 #endif
959 }
960
961 void RTLIL::Module::optimize()
962 {
963 }
964
965 void RTLIL::Module::cloneInto(RTLIL::Module *new_mod) const
966 {
967 log_assert(new_mod->refcount_wires_ == 0);
968 log_assert(new_mod->refcount_cells_ == 0);
969
970 new_mod->connections_ = connections_;
971 new_mod->attributes = attributes;
972
973 for (auto &it : wires_)
974 new_mod->addWire(it.first, it.second);
975
976 for (auto &it : memories)
977 new_mod->memories[it.first] = new RTLIL::Memory(*it.second);
978
979 for (auto &it : cells_)
980 new_mod->addCell(it.first, it.second);
981
982 for (auto &it : processes)
983 new_mod->processes[it.first] = it.second->clone();
984
985 struct RewriteSigSpecWorker
986 {
987 RTLIL::Module *mod;
988 void operator()(RTLIL::SigSpec &sig)
989 {
990 std::vector<RTLIL::SigChunk> chunks = sig.chunks();
991 for (auto &c : chunks)
992 if (c.wire != NULL)
993 c.wire = mod->wires_.at(c.wire->name);
994 sig = chunks;
995 }
996 };
997
998 RewriteSigSpecWorker rewriteSigSpecWorker;
999 rewriteSigSpecWorker.mod = new_mod;
1000 new_mod->rewrite_sigspecs(rewriteSigSpecWorker);
1001 new_mod->fixup_ports();
1002 }
1003
1004 RTLIL::Module *RTLIL::Module::clone() const
1005 {
1006 RTLIL::Module *new_mod = new RTLIL::Module;
1007 new_mod->name = name;
1008 cloneInto(new_mod);
1009 return new_mod;
1010 }
1011
1012 bool RTLIL::Module::has_memories() const
1013 {
1014 return !memories.empty();
1015 }
1016
1017 bool RTLIL::Module::has_processes() const
1018 {
1019 return !processes.empty();
1020 }
1021
1022 bool RTLIL::Module::has_memories_warn() const
1023 {
1024 if (!memories.empty())
1025 log("Warning: Ignoring module %s because it contains memories (run 'memory' command first).\n", log_id(this));
1026 return !memories.empty();
1027 }
1028
1029 bool RTLIL::Module::has_processes_warn() const
1030 {
1031 if (!processes.empty())
1032 log("Warning: Ignoring module %s because it contains processes (run 'proc' command first).\n", log_id(this));
1033 return !processes.empty();
1034 }
1035
1036 std::vector<RTLIL::Wire*> RTLIL::Module::selected_wires() const
1037 {
1038 std::vector<RTLIL::Wire*> result;
1039 result.reserve(wires_.size());
1040 for (auto &it : wires_)
1041 if (design->selected(this, it.second))
1042 result.push_back(it.second);
1043 return result;
1044 }
1045
1046 std::vector<RTLIL::Cell*> RTLIL::Module::selected_cells() const
1047 {
1048 std::vector<RTLIL::Cell*> result;
1049 result.reserve(wires_.size());
1050 for (auto &it : cells_)
1051 if (design->selected(this, it.second))
1052 result.push_back(it.second);
1053 return result;
1054 }
1055
1056 void RTLIL::Module::add(RTLIL::Wire *wire)
1057 {
1058 log_assert(!wire->name.empty());
1059 log_assert(count_id(wire->name) == 0);
1060 log_assert(refcount_wires_ == 0);
1061 wires_[wire->name] = wire;
1062 wire->module = this;
1063 }
1064
1065 void RTLIL::Module::add(RTLIL::Cell *cell)
1066 {
1067 log_assert(!cell->name.empty());
1068 log_assert(count_id(cell->name) == 0);
1069 log_assert(refcount_cells_ == 0);
1070 cells_[cell->name] = cell;
1071 cell->module = this;
1072 }
1073
1074 namespace {
1075 struct DeleteWireWorker
1076 {
1077 RTLIL::Module *module;
1078 const std::set<RTLIL::Wire*> *wires_p;
1079
1080 void operator()(RTLIL::SigSpec &sig) {
1081 std::vector<RTLIL::SigChunk> chunks = sig;
1082 for (auto &c : chunks)
1083 if (c.wire != NULL && wires_p->count(c.wire)) {
1084 c.wire = module->addWire(NEW_ID, c.width);
1085 c.offset = 0;
1086 }
1087 sig = chunks;
1088 }
1089 };
1090 }
1091
1092 #if 0
1093 void RTLIL::Module::remove(RTLIL::Wire *wire)
1094 {
1095 std::setPort<RTLIL::Wire*> wires_;
1096 wires_.insert(wire);
1097 remove(wires_);
1098 }
1099 #endif
1100
1101 void RTLIL::Module::remove(const std::set<RTLIL::Wire*> &wires)
1102 {
1103 log_assert(refcount_wires_ == 0);
1104
1105 DeleteWireWorker delete_wire_worker;
1106 delete_wire_worker.module = this;
1107 delete_wire_worker.wires_p = &wires;
1108 rewrite_sigspecs(delete_wire_worker);
1109
1110 for (auto &it : wires) {
1111 log_assert(wires_.count(it->name) != 0);
1112 wires_.erase(it->name);
1113 delete it;
1114 }
1115 }
1116
1117 void RTLIL::Module::remove(RTLIL::Cell *cell)
1118 {
1119 log_assert(cells_.count(cell->name) != 0);
1120 log_assert(refcount_cells_ == 0);
1121 cells_.erase(cell->name);
1122 delete cell;
1123 }
1124
1125 void RTLIL::Module::rename(RTLIL::Wire *wire, RTLIL::IdString new_name)
1126 {
1127 log_assert(wires_[wire->name] == wire);
1128 log_assert(refcount_wires_ == 0);
1129 wires_.erase(wire->name);
1130 wire->name = new_name;
1131 add(wire);
1132 }
1133
1134 void RTLIL::Module::rename(RTLIL::Cell *cell, RTLIL::IdString new_name)
1135 {
1136 log_assert(cells_[cell->name] == cell);
1137 log_assert(refcount_wires_ == 0);
1138 cells_.erase(cell->name);
1139 cell->name = new_name;
1140 add(cell);
1141 }
1142
1143 void RTLIL::Module::rename(RTLIL::IdString old_name, RTLIL::IdString new_name)
1144 {
1145 log_assert(count_id(old_name) != 0);
1146 if (wires_.count(old_name))
1147 rename(wires_.at(old_name), new_name);
1148 else if (cells_.count(old_name))
1149 rename(cells_.at(old_name), new_name);
1150 else
1151 log_abort();
1152 }
1153
1154 void RTLIL::Module::swap_names(RTLIL::Wire *w1, RTLIL::Wire *w2)
1155 {
1156 log_assert(wires_[w1->name] == w1);
1157 log_assert(wires_[w2->name] == w2);
1158 log_assert(refcount_wires_ == 0);
1159
1160 wires_.erase(w1->name);
1161 wires_.erase(w2->name);
1162
1163 std::swap(w1->name, w2->name);
1164
1165 wires_[w1->name] = w1;
1166 wires_[w2->name] = w2;
1167 }
1168
1169 void RTLIL::Module::swap_names(RTLIL::Cell *c1, RTLIL::Cell *c2)
1170 {
1171 log_assert(cells_[c1->name] == c1);
1172 log_assert(cells_[c2->name] == c2);
1173 log_assert(refcount_cells_ == 0);
1174
1175 cells_.erase(c1->name);
1176 cells_.erase(c2->name);
1177
1178 std::swap(c1->name, c2->name);
1179
1180 cells_[c1->name] = c1;
1181 cells_[c2->name] = c2;
1182 }
1183
1184 RTLIL::IdString RTLIL::Module::uniquify(RTLIL::IdString name)
1185 {
1186 int index = 0;
1187 return uniquify(name, index);
1188 }
1189
1190 RTLIL::IdString RTLIL::Module::uniquify(RTLIL::IdString name, int &index)
1191 {
1192 if (index == 0) {
1193 if (count_id(name) == 0)
1194 return name;
1195 index++;
1196 }
1197
1198 while (1) {
1199 RTLIL::IdString new_name = stringf("%s_%d", name.c_str(), index);
1200 if (count_id(new_name) == 0)
1201 return new_name;
1202 index++;
1203 }
1204 }
1205
1206 static bool fixup_ports_compare(const RTLIL::Wire *a, const RTLIL::Wire *b)
1207 {
1208 if (a->port_id && !b->port_id)
1209 return true;
1210 if (!a->port_id && b->port_id)
1211 return false;
1212
1213 if (a->port_id == b->port_id)
1214 return a->name < b->name;
1215 return a->port_id < b->port_id;
1216 }
1217
1218 void RTLIL::Module::connect(const RTLIL::SigSig &conn)
1219 {
1220 for (auto mon : monitors)
1221 mon->notify_connect(this, conn);
1222
1223 if (design)
1224 for (auto mon : design->monitors)
1225 mon->notify_connect(this, conn);
1226
1227 connections_.push_back(conn);
1228 }
1229
1230 void RTLIL::Module::connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs)
1231 {
1232 connect(RTLIL::SigSig(lhs, rhs));
1233 }
1234
1235 void RTLIL::Module::new_connections(const std::vector<RTLIL::SigSig> &new_conn)
1236 {
1237 for (auto mon : monitors)
1238 mon->notify_connect(this, new_conn);
1239
1240 if (design)
1241 for (auto mon : design->monitors)
1242 mon->notify_connect(this, new_conn);
1243
1244 connections_ = new_conn;
1245 }
1246
1247 const std::vector<RTLIL::SigSig> &RTLIL::Module::connections() const
1248 {
1249 return connections_;
1250 }
1251
1252 void RTLIL::Module::fixup_ports()
1253 {
1254 std::vector<RTLIL::Wire*> all_ports;
1255
1256 for (auto &w : wires_)
1257 if (w.second->port_input || w.second->port_output)
1258 all_ports.push_back(w.second);
1259 else
1260 w.second->port_id = 0;
1261
1262 std::sort(all_ports.begin(), all_ports.end(), fixup_ports_compare);
1263
1264 ports.clear();
1265 for (size_t i = 0; i < all_ports.size(); i++) {
1266 ports.push_back(all_ports[i]->name);
1267 all_ports[i]->port_id = i+1;
1268 }
1269 }
1270
1271 RTLIL::Wire *RTLIL::Module::addWire(RTLIL::IdString name, int width)
1272 {
1273 RTLIL::Wire *wire = new RTLIL::Wire;
1274 wire->name = name;
1275 wire->width = width;
1276 add(wire);
1277 return wire;
1278 }
1279
1280 RTLIL::Wire *RTLIL::Module::addWire(RTLIL::IdString name, const RTLIL::Wire *other)
1281 {
1282 RTLIL::Wire *wire = addWire(name);
1283 wire->width = other->width;
1284 wire->start_offset = other->start_offset;
1285 wire->port_id = other->port_id;
1286 wire->port_input = other->port_input;
1287 wire->port_output = other->port_output;
1288 wire->upto = other->upto;
1289 wire->attributes = other->attributes;
1290 return wire;
1291 }
1292
1293 RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, RTLIL::IdString type)
1294 {
1295 RTLIL::Cell *cell = new RTLIL::Cell;
1296 cell->name = name;
1297 cell->type = type;
1298 add(cell);
1299 return cell;
1300 }
1301
1302 RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, const RTLIL::Cell *other)
1303 {
1304 RTLIL::Cell *cell = addCell(name, other->type);
1305 cell->connections_ = other->connections_;
1306 cell->parameters = other->parameters;
1307 cell->attributes = other->attributes;
1308 return cell;
1309 }
1310
1311 #define DEF_METHOD(_func, _y_size, _type) \
1312 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed) { \
1313 RTLIL::Cell *cell = addCell(name, _type); \
1314 cell->parameters["\\A_SIGNED"] = is_signed; \
1315 cell->parameters["\\A_WIDTH"] = sig_a.size(); \
1316 cell->parameters["\\Y_WIDTH"] = sig_y.size(); \
1317 cell->setPort("\\A", sig_a); \
1318 cell->setPort("\\Y", sig_y); \
1319 return cell; \
1320 } \
1321 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed) { \
1322 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
1323 add ## _func(name, sig_a, sig_y, is_signed); \
1324 return sig_y; \
1325 }
1326 DEF_METHOD(Not, sig_a.size(), "$not")
1327 DEF_METHOD(Pos, sig_a.size(), "$pos")
1328 DEF_METHOD(Bu0, sig_a.size(), "$bu0")
1329 DEF_METHOD(Neg, sig_a.size(), "$neg")
1330 DEF_METHOD(ReduceAnd, 1, "$reduce_and")
1331 DEF_METHOD(ReduceOr, 1, "$reduce_or")
1332 DEF_METHOD(ReduceXor, 1, "$reduce_xor")
1333 DEF_METHOD(ReduceXnor, 1, "$reduce_xnor")
1334 DEF_METHOD(ReduceBool, 1, "$reduce_bool")
1335 DEF_METHOD(LogicNot, 1, "$logic_not")
1336 #undef DEF_METHOD
1337
1338 #define DEF_METHOD(_func, _y_size, _type) \
1339 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed) { \
1340 RTLIL::Cell *cell = addCell(name, _type); \
1341 cell->parameters["\\A_SIGNED"] = is_signed; \
1342 cell->parameters["\\B_SIGNED"] = is_signed; \
1343 cell->parameters["\\A_WIDTH"] = sig_a.size(); \
1344 cell->parameters["\\B_WIDTH"] = sig_b.size(); \
1345 cell->parameters["\\Y_WIDTH"] = sig_y.size(); \
1346 cell->setPort("\\A", sig_a); \
1347 cell->setPort("\\B", sig_b); \
1348 cell->setPort("\\Y", sig_y); \
1349 return cell; \
1350 } \
1351 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed) { \
1352 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
1353 add ## _func(name, sig_a, sig_b, sig_y, is_signed); \
1354 return sig_y; \
1355 }
1356 DEF_METHOD(And, std::max(sig_a.size(), sig_b.size()), "$and")
1357 DEF_METHOD(Or, std::max(sig_a.size(), sig_b.size()), "$or")
1358 DEF_METHOD(Xor, std::max(sig_a.size(), sig_b.size()), "$xor")
1359 DEF_METHOD(Xnor, std::max(sig_a.size(), sig_b.size()), "$xnor")
1360 DEF_METHOD(Shl, sig_a.size(), "$shl")
1361 DEF_METHOD(Shr, sig_a.size(), "$shr")
1362 DEF_METHOD(Sshl, sig_a.size(), "$sshl")
1363 DEF_METHOD(Sshr, sig_a.size(), "$sshr")
1364 DEF_METHOD(Shift, sig_a.size(), "$shift")
1365 DEF_METHOD(Shiftx, sig_a.size(), "$shiftx")
1366 DEF_METHOD(Lt, 1, "$lt")
1367 DEF_METHOD(Le, 1, "$le")
1368 DEF_METHOD(Eq, 1, "$eq")
1369 DEF_METHOD(Ne, 1, "$ne")
1370 DEF_METHOD(Eqx, 1, "$eqx")
1371 DEF_METHOD(Nex, 1, "$nex")
1372 DEF_METHOD(Ge, 1, "$ge")
1373 DEF_METHOD(Gt, 1, "$gt")
1374 DEF_METHOD(Add, std::max(sig_a.size(), sig_b.size()), "$add")
1375 DEF_METHOD(Sub, std::max(sig_a.size(), sig_b.size()), "$sub")
1376 DEF_METHOD(Mul, std::max(sig_a.size(), sig_b.size()), "$mul")
1377 DEF_METHOD(Div, std::max(sig_a.size(), sig_b.size()), "$div")
1378 DEF_METHOD(Mod, std::max(sig_a.size(), sig_b.size()), "$mod")
1379 DEF_METHOD(LogicAnd, 1, "$logic_and")
1380 DEF_METHOD(LogicOr, 1, "$logic_or")
1381 #undef DEF_METHOD
1382
1383 #define DEF_METHOD(_func, _type, _pmux) \
1384 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, RTLIL::SigSpec sig_y) { \
1385 RTLIL::Cell *cell = addCell(name, _type); \
1386 cell->parameters["\\WIDTH"] = sig_a.size(); \
1387 if (_pmux) cell->parameters["\\S_WIDTH"] = sig_s.size(); \
1388 cell->setPort("\\A", sig_a); \
1389 cell->setPort("\\B", sig_b); \
1390 cell->setPort("\\S", sig_s); \
1391 cell->setPort("\\Y", sig_y); \
1392 return cell; \
1393 } \
1394 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s) { \
1395 RTLIL::SigSpec sig_y = addWire(NEW_ID, sig_a.size()); \
1396 add ## _func(name, sig_a, sig_b, sig_s, sig_y); \
1397 return sig_y; \
1398 }
1399 DEF_METHOD(Mux, "$mux", 0)
1400 DEF_METHOD(Pmux, "$pmux", 1)
1401 #undef DEF_METHOD
1402
1403 #define DEF_METHOD_2(_func, _type, _P1, _P2) \
1404 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2) { \
1405 RTLIL::Cell *cell = addCell(name, _type); \
1406 cell->setPort("\\" #_P1, sig1); \
1407 cell->setPort("\\" #_P2, sig2); \
1408 return cell; \
1409 } \
1410 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1) { \
1411 RTLIL::SigBit sig2 = addWire(NEW_ID); \
1412 add ## _func(name, sig1, sig2); \
1413 return sig2; \
1414 }
1415 #define DEF_METHOD_3(_func, _type, _P1, _P2, _P3) \
1416 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3) { \
1417 RTLIL::Cell *cell = addCell(name, _type); \
1418 cell->setPort("\\" #_P1, sig1); \
1419 cell->setPort("\\" #_P2, sig2); \
1420 cell->setPort("\\" #_P3, sig3); \
1421 return cell; \
1422 } \
1423 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2) { \
1424 RTLIL::SigBit sig3 = addWire(NEW_ID); \
1425 add ## _func(name, sig1, sig2, sig3); \
1426 return sig3; \
1427 }
1428 #define DEF_METHOD_4(_func, _type, _P1, _P2, _P3, _P4) \
1429 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, RTLIL::SigBit sig4) { \
1430 RTLIL::Cell *cell = addCell(name, _type); \
1431 cell->setPort("\\" #_P1, sig1); \
1432 cell->setPort("\\" #_P2, sig2); \
1433 cell->setPort("\\" #_P3, sig3); \
1434 cell->setPort("\\" #_P4, sig4); \
1435 return cell; \
1436 } \
1437 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3) { \
1438 RTLIL::SigBit sig4 = addWire(NEW_ID); \
1439 add ## _func(name, sig1, sig2, sig3, sig4); \
1440 return sig4; \
1441 }
1442 #define DEF_METHOD_5(_func, _type, _P1, _P2, _P3, _P4, _P5) \
1443 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, RTLIL::SigBit sig4, RTLIL::SigBit sig5) { \
1444 RTLIL::Cell *cell = addCell(name, _type); \
1445 cell->setPort("\\" #_P1, sig1); \
1446 cell->setPort("\\" #_P2, sig2); \
1447 cell->setPort("\\" #_P3, sig3); \
1448 cell->setPort("\\" #_P4, sig4); \
1449 cell->setPort("\\" #_P5, sig5); \
1450 return cell; \
1451 } \
1452 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, RTLIL::SigBit sig4) { \
1453 RTLIL::SigBit sig5 = addWire(NEW_ID); \
1454 add ## _func(name, sig1, sig2, sig3, sig4, sig5); \
1455 return sig5; \
1456 }
1457 DEF_METHOD_2(NotGate, "$_NOT_", A, Y)
1458 DEF_METHOD_3(AndGate, "$_AND_", A, B, Y)
1459 DEF_METHOD_3(NandGate, "$_NAND_", A, B, Y)
1460 DEF_METHOD_3(OrGate, "$_OR_", A, B, Y)
1461 DEF_METHOD_3(NorGate, "$_NOR_", A, B, Y)
1462 DEF_METHOD_3(XorGate, "$_XOR_", A, B, Y)
1463 DEF_METHOD_3(XnorGate, "$_XNOR_", A, B, Y)
1464 DEF_METHOD_4(MuxGate, "$_MUX_", A, B, S, Y)
1465 DEF_METHOD_4(Aoi3Gate, "$_AOI3_", A, B, C, Y)
1466 DEF_METHOD_4(Oai3Gate, "$_OAI3_", A, B, C, Y)
1467 DEF_METHOD_5(Aoi4Gate, "$_AOI4_", A, B, C, D, Y)
1468 DEF_METHOD_5(Oai4Gate, "$_OAI4_", A, B, C, D, Y)
1469 #undef DEF_METHOD_2
1470 #undef DEF_METHOD_3
1471 #undef DEF_METHOD_4
1472 #undef DEF_METHOD_5
1473
1474 RTLIL::Cell* RTLIL::Module::addPow(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool a_signed, bool b_signed)
1475 {
1476 RTLIL::Cell *cell = addCell(name, "$pow");
1477 cell->parameters["\\A_SIGNED"] = a_signed;
1478 cell->parameters["\\B_SIGNED"] = b_signed;
1479 cell->parameters["\\A_WIDTH"] = sig_a.size();
1480 cell->parameters["\\B_WIDTH"] = sig_b.size();
1481 cell->parameters["\\Y_WIDTH"] = sig_y.size();
1482 cell->setPort("\\A", sig_a);
1483 cell->setPort("\\B", sig_b);
1484 cell->setPort("\\Y", sig_y);
1485 return cell;
1486 }
1487
1488 RTLIL::Cell* RTLIL::Module::addSlice(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, RTLIL::Const offset)
1489 {
1490 RTLIL::Cell *cell = addCell(name, "$slice");
1491 cell->parameters["\\A_WIDTH"] = sig_a.size();
1492 cell->parameters["\\Y_WIDTH"] = sig_y.size();
1493 cell->parameters["\\OFFSET"] = offset;
1494 cell->setPort("\\A", sig_a);
1495 cell->setPort("\\Y", sig_y);
1496 return cell;
1497 }
1498
1499 RTLIL::Cell* RTLIL::Module::addConcat(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y)
1500 {
1501 RTLIL::Cell *cell = addCell(name, "$concat");
1502 cell->parameters["\\A_WIDTH"] = sig_a.size();
1503 cell->parameters["\\B_WIDTH"] = sig_b.size();
1504 cell->setPort("\\A", sig_a);
1505 cell->setPort("\\B", sig_b);
1506 cell->setPort("\\Y", sig_y);
1507 return cell;
1508 }
1509
1510 RTLIL::Cell* RTLIL::Module::addLut(RTLIL::IdString name, RTLIL::SigSpec sig_i, RTLIL::SigSpec sig_o, RTLIL::Const lut)
1511 {
1512 RTLIL::Cell *cell = addCell(name, "$lut");
1513 cell->parameters["\\LUT"] = lut;
1514 cell->parameters["\\WIDTH"] = sig_i.size();
1515 cell->setPort("\\A", sig_i);
1516 cell->setPort("\\Y", sig_o);
1517 return cell;
1518 }
1519
1520 RTLIL::Cell* RTLIL::Module::addAssert(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en)
1521 {
1522 RTLIL::Cell *cell = addCell(name, "$assert");
1523 cell->setPort("\\A", sig_a);
1524 cell->setPort("\\EN", sig_en);
1525 return cell;
1526 }
1527
1528 RTLIL::Cell* RTLIL::Module::addSr(RTLIL::IdString name, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr, RTLIL::SigSpec sig_q, bool set_polarity, bool clr_polarity)
1529 {
1530 RTLIL::Cell *cell = addCell(name, "$sr");
1531 cell->parameters["\\SET_POLARITY"] = set_polarity;
1532 cell->parameters["\\CLR_POLARITY"] = clr_polarity;
1533 cell->parameters["\\WIDTH"] = sig_q.size();
1534 cell->setPort("\\SET", sig_set);
1535 cell->setPort("\\CLR", sig_clr);
1536 cell->setPort("\\Q", sig_q);
1537 return cell;
1538 }
1539
1540 RTLIL::Cell* RTLIL::Module::addDff(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity)
1541 {
1542 RTLIL::Cell *cell = addCell(name, "$dff");
1543 cell->parameters["\\CLK_POLARITY"] = clk_polarity;
1544 cell->parameters["\\WIDTH"] = sig_q.size();
1545 cell->setPort("\\CLK", sig_clk);
1546 cell->setPort("\\D", sig_d);
1547 cell->setPort("\\Q", sig_q);
1548 return cell;
1549 }
1550
1551 RTLIL::Cell* RTLIL::Module::addDffsr(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
1552 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity)
1553 {
1554 RTLIL::Cell *cell = addCell(name, "$dffsr");
1555 cell->parameters["\\CLK_POLARITY"] = clk_polarity;
1556 cell->parameters["\\SET_POLARITY"] = set_polarity;
1557 cell->parameters["\\CLR_POLARITY"] = clr_polarity;
1558 cell->parameters["\\WIDTH"] = sig_q.size();
1559 cell->setPort("\\CLK", sig_clk);
1560 cell->setPort("\\SET", sig_set);
1561 cell->setPort("\\CLR", sig_clr);
1562 cell->setPort("\\D", sig_d);
1563 cell->setPort("\\Q", sig_q);
1564 return cell;
1565 }
1566
1567 RTLIL::Cell* RTLIL::Module::addAdff(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_arst, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q,
1568 RTLIL::Const arst_value, bool clk_polarity, bool arst_polarity)
1569 {
1570 RTLIL::Cell *cell = addCell(name, "$adff");
1571 cell->parameters["\\CLK_POLARITY"] = clk_polarity;
1572 cell->parameters["\\ARST_POLARITY"] = arst_polarity;
1573 cell->parameters["\\ARST_VALUE"] = arst_value;
1574 cell->parameters["\\WIDTH"] = sig_q.size();
1575 cell->setPort("\\CLK", sig_clk);
1576 cell->setPort("\\ARST", sig_arst);
1577 cell->setPort("\\D", sig_d);
1578 cell->setPort("\\Q", sig_q);
1579 return cell;
1580 }
1581
1582 RTLIL::Cell* RTLIL::Module::addDlatch(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity)
1583 {
1584 RTLIL::Cell *cell = addCell(name, "$dlatch");
1585 cell->parameters["\\EN_POLARITY"] = en_polarity;
1586 cell->parameters["\\WIDTH"] = sig_q.size();
1587 cell->setPort("\\EN", sig_en);
1588 cell->setPort("\\D", sig_d);
1589 cell->setPort("\\Q", sig_q);
1590 return cell;
1591 }
1592
1593 RTLIL::Cell* RTLIL::Module::addDlatchsr(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
1594 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity, bool set_polarity, bool clr_polarity)
1595 {
1596 RTLIL::Cell *cell = addCell(name, "$dlatchsr");
1597 cell->parameters["\\EN_POLARITY"] = en_polarity;
1598 cell->parameters["\\SET_POLARITY"] = set_polarity;
1599 cell->parameters["\\CLR_POLARITY"] = clr_polarity;
1600 cell->parameters["\\WIDTH"] = sig_q.size();
1601 cell->setPort("\\EN", sig_en);
1602 cell->setPort("\\SET", sig_set);
1603 cell->setPort("\\CLR", sig_clr);
1604 cell->setPort("\\D", sig_d);
1605 cell->setPort("\\Q", sig_q);
1606 return cell;
1607 }
1608
1609 RTLIL::Cell* RTLIL::Module::addDffGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity)
1610 {
1611 RTLIL::Cell *cell = addCell(name, stringf("$_DFF_%c_", clk_polarity ? 'P' : 'N'));
1612 cell->setPort("\\C", sig_clk);
1613 cell->setPort("\\D", sig_d);
1614 cell->setPort("\\Q", sig_q);
1615 return cell;
1616 }
1617
1618 RTLIL::Cell* RTLIL::Module::addDffsrGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
1619 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity)
1620 {
1621 RTLIL::Cell *cell = addCell(name, stringf("$_DFFSR_%c%c%c_", clk_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N'));
1622 cell->setPort("\\C", sig_clk);
1623 cell->setPort("\\S", sig_set);
1624 cell->setPort("\\R", sig_clr);
1625 cell->setPort("\\D", sig_d);
1626 cell->setPort("\\Q", sig_q);
1627 return cell;
1628 }
1629
1630 RTLIL::Cell* RTLIL::Module::addAdffGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_arst, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q,
1631 bool arst_value, bool clk_polarity, bool arst_polarity)
1632 {
1633 RTLIL::Cell *cell = addCell(name, stringf("$_DFF_%c%c%c_", clk_polarity ? 'P' : 'N', arst_polarity ? 'P' : 'N', arst_value ? '1' : '0'));
1634 cell->setPort("\\C", sig_clk);
1635 cell->setPort("\\R", sig_arst);
1636 cell->setPort("\\D", sig_d);
1637 cell->setPort("\\Q", sig_q);
1638 return cell;
1639 }
1640
1641 RTLIL::Cell* RTLIL::Module::addDlatchGate(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity)
1642 {
1643 RTLIL::Cell *cell = addCell(name, stringf("$_DLATCH_%c_", en_polarity ? 'P' : 'N'));
1644 cell->setPort("\\E", sig_en);
1645 cell->setPort("\\D", sig_d);
1646 cell->setPort("\\Q", sig_q);
1647 return cell;
1648 }
1649
1650 RTLIL::Cell* RTLIL::Module::addDlatchsrGate(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
1651 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity, bool set_polarity, bool clr_polarity)
1652 {
1653 RTLIL::Cell *cell = addCell(name, stringf("$_DLATCHSR_%c%c%c_", en_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N'));
1654 cell->setPort("\\E", sig_en);
1655 cell->setPort("\\S", sig_set);
1656 cell->setPort("\\R", sig_clr);
1657 cell->setPort("\\D", sig_d);
1658 cell->setPort("\\Q", sig_q);
1659 return cell;
1660 }
1661
1662
1663 RTLIL::Wire::Wire()
1664 {
1665 module = nullptr;
1666 width = 1;
1667 start_offset = 0;
1668 port_id = 0;
1669 port_input = false;
1670 port_output = false;
1671 upto = false;
1672 }
1673
1674 RTLIL::Memory::Memory()
1675 {
1676 width = 1;
1677 size = 0;
1678 }
1679
1680 RTLIL::Cell::Cell() : module(nullptr)
1681 {
1682 }
1683
1684 bool RTLIL::Cell::hasPort(RTLIL::IdString portname) const
1685 {
1686 return connections_.count(portname) != 0;
1687 }
1688
1689 void RTLIL::Cell::unsetPort(RTLIL::IdString portname)
1690 {
1691 RTLIL::SigSpec signal;
1692 auto conn_it = connections_.find(portname);
1693
1694 if (conn_it != connections_.end())
1695 {
1696 for (auto mon : module->monitors)
1697 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
1698
1699 if (module->design)
1700 for (auto mon : module->design->monitors)
1701 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
1702
1703 connections_.erase(conn_it);
1704 }
1705 }
1706
1707 void RTLIL::Cell::setPort(RTLIL::IdString portname, RTLIL::SigSpec signal)
1708 {
1709 auto conn_it = connections_.find(portname);
1710
1711 if (conn_it == connections_.end()) {
1712 connections_[portname] = RTLIL::SigSpec();
1713 conn_it = connections_.find(portname);
1714 log_assert(conn_it != connections_.end());
1715 }
1716
1717 for (auto mon : module->monitors)
1718 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
1719
1720 if (module->design)
1721 for (auto mon : module->design->monitors)
1722 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
1723
1724 conn_it->second = signal;
1725 }
1726
1727 const RTLIL::SigSpec &RTLIL::Cell::getPort(RTLIL::IdString portname) const
1728 {
1729 return connections_.at(portname);
1730 }
1731
1732 const std::map<RTLIL::IdString, RTLIL::SigSpec> &RTLIL::Cell::connections() const
1733 {
1734 return connections_;
1735 }
1736
1737 bool RTLIL::Cell::hasParam(RTLIL::IdString paramname) const
1738 {
1739 return parameters.count(paramname);
1740 }
1741
1742 void RTLIL::Cell::unsetParam(RTLIL::IdString paramname)
1743 {
1744 parameters.erase(paramname);
1745 }
1746
1747 void RTLIL::Cell::setParam(RTLIL::IdString paramname, RTLIL::Const value)
1748 {
1749 parameters[paramname] = value;
1750 }
1751
1752 const RTLIL::Const &RTLIL::Cell::getParam(RTLIL::IdString paramname) const
1753 {
1754 return parameters.at(paramname);
1755 }
1756
1757 void RTLIL::Cell::check()
1758 {
1759 #ifndef NDEBUG
1760 InternalCellChecker checker(NULL, this);
1761 checker.check();
1762 #endif
1763 }
1764
1765 void RTLIL::Cell::fixup_parameters(bool set_a_signed, bool set_b_signed)
1766 {
1767 if (type.substr(0, 1) != "$" || type.substr(0, 2) == "$_" || type.substr(0, 8) == "$paramod" ||
1768 type.substr(0, 9) == "$verific$" || type.substr(0, 7) == "$array:" || type.substr(0, 8) == "$extern:")
1769 return;
1770
1771 if (type == "$mux" || type == "$pmux") {
1772 parameters["\\WIDTH"] = SIZE(connections_["\\Y"]);
1773 if (type == "$pmux")
1774 parameters["\\S_WIDTH"] = SIZE(connections_["\\S"]);
1775 check();
1776 return;
1777 }
1778
1779 if (type == "$lut") {
1780 parameters["\\WIDTH"] = SIZE(connections_["\\A"]);
1781 return;
1782 }
1783
1784 bool signedness_ab = !type.in("$slice", "$concat");
1785
1786 if (connections_.count("\\A")) {
1787 if (signedness_ab) {
1788 if (set_a_signed)
1789 parameters["\\A_SIGNED"] = true;
1790 else if (parameters.count("\\A_SIGNED") == 0)
1791 parameters["\\A_SIGNED"] = false;
1792 }
1793 parameters["\\A_WIDTH"] = SIZE(connections_["\\A"]);
1794 }
1795
1796 if (connections_.count("\\B")) {
1797 if (signedness_ab) {
1798 if (set_b_signed)
1799 parameters["\\B_SIGNED"] = true;
1800 else if (parameters.count("\\B_SIGNED") == 0)
1801 parameters["\\B_SIGNED"] = false;
1802 }
1803 parameters["\\B_WIDTH"] = SIZE(connections_["\\B"]);
1804 }
1805
1806 if (connections_.count("\\Y"))
1807 parameters["\\Y_WIDTH"] = SIZE(connections_["\\Y"]);
1808
1809 check();
1810 }
1811
1812 RTLIL::SigChunk::SigChunk()
1813 {
1814 wire = NULL;
1815 width = 0;
1816 offset = 0;
1817 }
1818
1819 RTLIL::SigChunk::SigChunk(const RTLIL::Const &value)
1820 {
1821 wire = NULL;
1822 data = value;
1823 width = data.bits.size();
1824 offset = 0;
1825 }
1826
1827 RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire)
1828 {
1829 log_assert(wire != nullptr);
1830 this->wire = wire;
1831 this->width = wire->width;
1832 this->offset = 0;
1833 }
1834
1835 RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire, int offset, int width)
1836 {
1837 log_assert(wire != nullptr);
1838 this->wire = wire;
1839 this->width = width;
1840 this->offset = offset;
1841 }
1842
1843 RTLIL::SigChunk::SigChunk(const std::string &str)
1844 {
1845 wire = NULL;
1846 data = RTLIL::Const(str);
1847 width = data.bits.size();
1848 offset = 0;
1849 }
1850
1851 RTLIL::SigChunk::SigChunk(int val, int width)
1852 {
1853 wire = NULL;
1854 data = RTLIL::Const(val, width);
1855 this->width = data.bits.size();
1856 offset = 0;
1857 }
1858
1859 RTLIL::SigChunk::SigChunk(RTLIL::State bit, int width)
1860 {
1861 wire = NULL;
1862 data = RTLIL::Const(bit, width);
1863 this->width = data.bits.size();
1864 offset = 0;
1865 }
1866
1867 RTLIL::SigChunk::SigChunk(RTLIL::SigBit bit)
1868 {
1869 wire = bit.wire;
1870 offset = 0;
1871 if (wire == NULL)
1872 data = RTLIL::Const(bit.data);
1873 else
1874 offset = bit.offset;
1875 width = 1;
1876 }
1877
1878 RTLIL::SigChunk RTLIL::SigChunk::extract(int offset, int length) const
1879 {
1880 RTLIL::SigChunk ret;
1881 if (wire) {
1882 ret.wire = wire;
1883 ret.offset = this->offset + offset;
1884 ret.width = length;
1885 } else {
1886 for (int i = 0; i < length; i++)
1887 ret.data.bits.push_back(data.bits[offset+i]);
1888 ret.width = length;
1889 }
1890 return ret;
1891 }
1892
1893 bool RTLIL::SigChunk::operator <(const RTLIL::SigChunk &other) const
1894 {
1895 if (wire && other.wire)
1896 if (wire->name != other.wire->name)
1897 return wire->name < other.wire->name;
1898
1899 if (wire != other.wire)
1900 return wire < other.wire;
1901
1902 if (offset != other.offset)
1903 return offset < other.offset;
1904
1905 if (width != other.width)
1906 return width < other.width;
1907
1908 return data.bits < other.data.bits;
1909 }
1910
1911 bool RTLIL::SigChunk::operator ==(const RTLIL::SigChunk &other) const
1912 {
1913 if (wire != other.wire || width != other.width || offset != other.offset)
1914 return false;
1915 if (data.bits != other.data.bits)
1916 return false;
1917 return true;
1918 }
1919
1920 bool RTLIL::SigChunk::operator !=(const RTLIL::SigChunk &other) const
1921 {
1922 if (*this == other)
1923 return false;
1924 return true;
1925 }
1926
1927 RTLIL::SigSpec::SigSpec()
1928 {
1929 width_ = 0;
1930 hash_ = 0;
1931 }
1932
1933 RTLIL::SigSpec::SigSpec(const RTLIL::SigSpec &other)
1934 {
1935 *this = other;
1936 }
1937
1938 RTLIL::SigSpec::SigSpec(std::initializer_list<RTLIL::SigSpec> parts)
1939 {
1940 cover("kernel.rtlil.sigspec.init.list");
1941
1942 width_ = 0;
1943 hash_ = 0;
1944
1945 std::vector<RTLIL::SigSpec> parts_vec(parts.begin(), parts.end());
1946 for (auto it = parts_vec.rbegin(); it != parts_vec.rend(); it++)
1947 append(*it);
1948 }
1949
1950 const RTLIL::SigSpec &RTLIL::SigSpec::operator=(const RTLIL::SigSpec &other)
1951 {
1952 cover("kernel.rtlil.sigspec.assign");
1953
1954 width_ = other.width_;
1955 hash_ = other.hash_;
1956 chunks_ = other.chunks_;
1957 bits_.clear();
1958
1959 if (!other.bits_.empty())
1960 {
1961 RTLIL::SigChunk *last = NULL;
1962 int last_end_offset = 0;
1963
1964 for (auto &bit : other.bits_) {
1965 if (last && bit.wire == last->wire) {
1966 if (bit.wire == NULL) {
1967 last->data.bits.push_back(bit.data);
1968 last->width++;
1969 continue;
1970 } else if (last_end_offset == bit.offset) {
1971 last_end_offset++;
1972 last->width++;
1973 continue;
1974 }
1975 }
1976 chunks_.push_back(bit);
1977 last = &chunks_.back();
1978 last_end_offset = bit.offset + 1;
1979 }
1980
1981 check();
1982 }
1983
1984 return *this;
1985 }
1986
1987 RTLIL::SigSpec::SigSpec(const RTLIL::Const &value)
1988 {
1989 cover("kernel.rtlil.sigspec.init.const");
1990
1991 chunks_.push_back(RTLIL::SigChunk(value));
1992 width_ = chunks_.back().width;
1993 hash_ = 0;
1994 check();
1995 }
1996
1997 RTLIL::SigSpec::SigSpec(const RTLIL::SigChunk &chunk)
1998 {
1999 cover("kernel.rtlil.sigspec.init.chunk");
2000
2001 chunks_.push_back(chunk);
2002 width_ = chunks_.back().width;
2003 hash_ = 0;
2004 check();
2005 }
2006
2007 RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire)
2008 {
2009 cover("kernel.rtlil.sigspec.init.wire");
2010
2011 chunks_.push_back(RTLIL::SigChunk(wire));
2012 width_ = chunks_.back().width;
2013 hash_ = 0;
2014 check();
2015 }
2016
2017 RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire, int offset, int width)
2018 {
2019 cover("kernel.rtlil.sigspec.init.wire_part");
2020
2021 chunks_.push_back(RTLIL::SigChunk(wire, offset, width));
2022 width_ = chunks_.back().width;
2023 hash_ = 0;
2024 check();
2025 }
2026
2027 RTLIL::SigSpec::SigSpec(const std::string &str)
2028 {
2029 cover("kernel.rtlil.sigspec.init.str");
2030
2031 chunks_.push_back(RTLIL::SigChunk(str));
2032 width_ = chunks_.back().width;
2033 hash_ = 0;
2034 check();
2035 }
2036
2037 RTLIL::SigSpec::SigSpec(int val, int width)
2038 {
2039 cover("kernel.rtlil.sigspec.init.int");
2040
2041 chunks_.push_back(RTLIL::SigChunk(val, width));
2042 width_ = width;
2043 hash_ = 0;
2044 check();
2045 }
2046
2047 RTLIL::SigSpec::SigSpec(RTLIL::State bit, int width)
2048 {
2049 cover("kernel.rtlil.sigspec.init.state");
2050
2051 chunks_.push_back(RTLIL::SigChunk(bit, width));
2052 width_ = width;
2053 hash_ = 0;
2054 check();
2055 }
2056
2057 RTLIL::SigSpec::SigSpec(RTLIL::SigBit bit, int width)
2058 {
2059 cover("kernel.rtlil.sigspec.init.bit");
2060
2061 if (bit.wire == NULL)
2062 chunks_.push_back(RTLIL::SigChunk(bit.data, width));
2063 else
2064 for (int i = 0; i < width; i++)
2065 chunks_.push_back(bit);
2066 width_ = width;
2067 hash_ = 0;
2068 check();
2069 }
2070
2071 RTLIL::SigSpec::SigSpec(std::vector<RTLIL::SigChunk> chunks)
2072 {
2073 cover("kernel.rtlil.sigspec.init.stdvec_chunks");
2074
2075 width_ = 0;
2076 hash_ = 0;
2077 for (auto &c : chunks)
2078 append(c);
2079 check();
2080 }
2081
2082 RTLIL::SigSpec::SigSpec(std::vector<RTLIL::SigBit> bits)
2083 {
2084 cover("kernel.rtlil.sigspec.init.stdvec_bits");
2085
2086 width_ = 0;
2087 hash_ = 0;
2088 for (auto &bit : bits)
2089 append_bit(bit);
2090 check();
2091 }
2092
2093 RTLIL::SigSpec::SigSpec(std::set<RTLIL::SigBit> bits)
2094 {
2095 cover("kernel.rtlil.sigspec.init.stdset_bits");
2096
2097 width_ = 0;
2098 hash_ = 0;
2099 for (auto &bit : bits)
2100 append_bit(bit);
2101 check();
2102 }
2103
2104 void RTLIL::SigSpec::pack() const
2105 {
2106 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
2107
2108 if (that->bits_.empty())
2109 return;
2110
2111 cover("kernel.rtlil.sigspec.convert.pack");
2112 log_assert(that->chunks_.empty());
2113
2114 std::vector<RTLIL::SigBit> old_bits;
2115 old_bits.swap(that->bits_);
2116
2117 RTLIL::SigChunk *last = NULL;
2118 int last_end_offset = 0;
2119
2120 for (auto &bit : old_bits) {
2121 if (last && bit.wire == last->wire) {
2122 if (bit.wire == NULL) {
2123 last->data.bits.push_back(bit.data);
2124 last->width++;
2125 continue;
2126 } else if (last_end_offset == bit.offset) {
2127 last_end_offset++;
2128 last->width++;
2129 continue;
2130 }
2131 }
2132 that->chunks_.push_back(bit);
2133 last = &that->chunks_.back();
2134 last_end_offset = bit.offset + 1;
2135 }
2136
2137 check();
2138 }
2139
2140 void RTLIL::SigSpec::unpack() const
2141 {
2142 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
2143
2144 if (that->chunks_.empty())
2145 return;
2146
2147 cover("kernel.rtlil.sigspec.convert.unpack");
2148 log_assert(that->bits_.empty());
2149
2150 that->bits_.reserve(that->width_);
2151 for (auto &c : that->chunks_)
2152 for (int i = 0; i < c.width; i++)
2153 that->bits_.push_back(RTLIL::SigBit(c, i));
2154
2155 that->chunks_.clear();
2156 that->hash_ = 0;
2157 }
2158
2159 #define DJB2(_hash, _value) do { (_hash) = (((_hash) << 5) + (_hash)) + (_value); } while (0)
2160
2161 void RTLIL::SigSpec::hash() const
2162 {
2163 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
2164
2165 if (that->hash_ != 0)
2166 return;
2167
2168 cover("kernel.rtlil.sigspec.hash");
2169 that->pack();
2170
2171 that->hash_ = 5381;
2172 for (auto &c : that->chunks_)
2173 if (c.wire == NULL) {
2174 for (auto &v : c.data.bits)
2175 DJB2(that->hash_, v);
2176 } else {
2177 DJB2(that->hash_, c.wire->name.index_);
2178 DJB2(that->hash_, c.offset);
2179 DJB2(that->hash_, c.width);
2180 }
2181
2182 if (that->hash_ == 0)
2183 that->hash_ = 1;
2184 }
2185
2186 void RTLIL::SigSpec::sort()
2187 {
2188 unpack();
2189 cover("kernel.rtlil.sigspec.sort");
2190 std::sort(bits_.begin(), bits_.end());
2191 }
2192
2193 void RTLIL::SigSpec::sort_and_unify()
2194 {
2195 cover("kernel.rtlil.sigspec.sort_and_unify");
2196 *this = this->to_sigbit_set();
2197 }
2198
2199 void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with)
2200 {
2201 replace(pattern, with, this);
2202 }
2203
2204 void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with, RTLIL::SigSpec *other) const
2205 {
2206 log_assert(pattern.width_ == with.width_);
2207
2208 pattern.unpack();
2209 with.unpack();
2210
2211 std::map<RTLIL::SigBit, RTLIL::SigBit> rules;
2212
2213 for (int i = 0; i < SIZE(pattern.bits_); i++)
2214 if (pattern.bits_[i].wire != NULL)
2215 rules[pattern.bits_[i]] = with.bits_[i];
2216
2217 replace(rules, other);
2218 }
2219
2220 void RTLIL::SigSpec::replace(const std::map<RTLIL::SigBit, RTLIL::SigBit> &rules)
2221 {
2222 replace(rules, this);
2223 }
2224
2225 void RTLIL::SigSpec::replace(const std::map<RTLIL::SigBit, RTLIL::SigBit> &rules, RTLIL::SigSpec *other) const
2226 {
2227 cover("kernel.rtlil.sigspec.replace");
2228
2229 log_assert(other != NULL);
2230 log_assert(width_ == other->width_);
2231
2232 unpack();
2233 other->unpack();
2234
2235 for (int i = 0; i < SIZE(bits_); i++) {
2236 auto it = rules.find(bits_[i]);
2237 if (it != rules.end())
2238 other->bits_[i] = it->second;
2239 }
2240
2241 other->check();
2242 }
2243
2244 void RTLIL::SigSpec::remove(const RTLIL::SigSpec &pattern)
2245 {
2246 remove2(pattern, NULL);
2247 }
2248
2249 void RTLIL::SigSpec::remove(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other) const
2250 {
2251 RTLIL::SigSpec tmp = *this;
2252 tmp.remove2(pattern, other);
2253 }
2254
2255 void RTLIL::SigSpec::remove2(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other)
2256 {
2257 std::set<RTLIL::SigBit> pattern_bits = pattern.to_sigbit_set();
2258 remove2(pattern_bits, other);
2259 }
2260
2261 void RTLIL::SigSpec::remove(const std::set<RTLIL::SigBit> &pattern)
2262 {
2263 remove2(pattern, NULL);
2264 }
2265
2266 void RTLIL::SigSpec::remove(const std::set<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other) const
2267 {
2268 RTLIL::SigSpec tmp = *this;
2269 tmp.remove2(pattern, other);
2270 }
2271
2272 void RTLIL::SigSpec::remove2(const std::set<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other)
2273 {
2274 if (other)
2275 cover("kernel.rtlil.sigspec.remove_other");
2276 else
2277 cover("kernel.rtlil.sigspec.remove");
2278
2279 unpack();
2280
2281 if (other != NULL) {
2282 log_assert(width_ == other->width_);
2283 other->unpack();
2284 }
2285
2286 std::vector<RTLIL::SigBit> new_bits, new_other_bits;
2287
2288 new_bits.resize(SIZE(bits_));
2289 if (other != NULL)
2290 new_other_bits.resize(SIZE(bits_));
2291
2292 int k = 0;
2293 for (int i = 0; i < SIZE(bits_); i++) {
2294 if (bits_[i].wire != NULL && pattern.count(bits_[i]))
2295 continue;
2296 if (other != NULL)
2297 new_other_bits[k] = other->bits_[i];
2298 new_bits[k++] = bits_[i];
2299 }
2300
2301 new_bits.resize(k);
2302 if (other != NULL)
2303 new_other_bits.resize(k);
2304
2305 bits_.swap(new_bits);
2306 width_ = SIZE(bits_);
2307
2308 if (other != NULL) {
2309 other->bits_.swap(new_other_bits);
2310 other->width_ = SIZE(other->bits_);
2311 }
2312
2313 check();
2314 }
2315
2316 RTLIL::SigSpec RTLIL::SigSpec::extract(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec *other) const
2317 {
2318 std::set<RTLIL::SigBit> pattern_bits = pattern.to_sigbit_set();
2319 return extract(pattern_bits, other);
2320 }
2321
2322 RTLIL::SigSpec RTLIL::SigSpec::extract(const std::set<RTLIL::SigBit> &pattern, const RTLIL::SigSpec *other) const
2323 {
2324 if (other)
2325 cover("kernel.rtlil.sigspec.extract_other");
2326 else
2327 cover("kernel.rtlil.sigspec.extract");
2328
2329 log_assert(other == NULL || width_ == other->width_);
2330
2331 std::vector<RTLIL::SigBit> bits_match = to_sigbit_vector();
2332 RTLIL::SigSpec ret;
2333
2334 if (other) {
2335 std::vector<RTLIL::SigBit> bits_other = other->to_sigbit_vector();
2336 for (int i = 0; i < width_; i++)
2337 if (bits_match[i].wire && pattern.count(bits_match[i]))
2338 ret.append_bit(bits_other[i]);
2339 } else {
2340 for (int i = 0; i < width_; i++)
2341 if (bits_match[i].wire && pattern.count(bits_match[i]))
2342 ret.append_bit(bits_match[i]);
2343 }
2344
2345 ret.check();
2346 return ret;
2347 }
2348
2349 void RTLIL::SigSpec::replace(int offset, const RTLIL::SigSpec &with)
2350 {
2351 cover("kernel.rtlil.sigspec.replace_pos");
2352
2353 unpack();
2354 with.unpack();
2355
2356 log_assert(offset >= 0);
2357 log_assert(with.width_ >= 0);
2358 log_assert(offset+with.width_ <= width_);
2359
2360 for (int i = 0; i < with.width_; i++)
2361 bits_.at(offset + i) = with.bits_.at(i);
2362
2363 check();
2364 }
2365
2366 void RTLIL::SigSpec::remove_const()
2367 {
2368 if (packed())
2369 {
2370 cover("kernel.rtlil.sigspec.remove_const.packed");
2371
2372 std::vector<RTLIL::SigChunk> new_chunks;
2373 new_chunks.reserve(SIZE(chunks_));
2374
2375 width_ = 0;
2376 for (auto &chunk : chunks_)
2377 if (chunk.wire != NULL) {
2378 new_chunks.push_back(chunk);
2379 width_ += chunk.width;
2380 }
2381
2382 chunks_.swap(new_chunks);
2383 }
2384 else
2385 {
2386 cover("kernel.rtlil.sigspec.remove_const.unpacked");
2387
2388 std::vector<RTLIL::SigBit> new_bits;
2389 new_bits.reserve(width_);
2390
2391 for (auto &bit : bits_)
2392 if (bit.wire != NULL)
2393 new_bits.push_back(bit);
2394
2395 bits_.swap(new_bits);
2396 width_ = bits_.size();
2397 }
2398
2399 check();
2400 }
2401
2402 void RTLIL::SigSpec::remove(int offset, int length)
2403 {
2404 cover("kernel.rtlil.sigspec.remove_pos");
2405
2406 unpack();
2407
2408 log_assert(offset >= 0);
2409 log_assert(length >= 0);
2410 log_assert(offset + length <= width_);
2411
2412 bits_.erase(bits_.begin() + offset, bits_.begin() + offset + length);
2413 width_ = bits_.size();
2414
2415 check();
2416 }
2417
2418 RTLIL::SigSpec RTLIL::SigSpec::extract(int offset, int length) const
2419 {
2420 unpack();
2421 cover("kernel.rtlil.sigspec.extract_pos");
2422 return std::vector<RTLIL::SigBit>(bits_.begin() + offset, bits_.begin() + offset + length);
2423 }
2424
2425 void RTLIL::SigSpec::append(const RTLIL::SigSpec &signal)
2426 {
2427 if (signal.width_ == 0)
2428 return;
2429
2430 if (width_ == 0) {
2431 *this = signal;
2432 return;
2433 }
2434
2435 cover("kernel.rtlil.sigspec.append");
2436
2437 if (packed() != signal.packed()) {
2438 pack();
2439 signal.pack();
2440 }
2441
2442 if (packed())
2443 for (auto &other_c : signal.chunks_)
2444 {
2445 auto &my_last_c = chunks_.back();
2446 if (my_last_c.wire == NULL && other_c.wire == NULL) {
2447 auto &this_data = my_last_c.data.bits;
2448 auto &other_data = other_c.data.bits;
2449 this_data.insert(this_data.end(), other_data.begin(), other_data.end());
2450 my_last_c.width += other_c.width;
2451 } else
2452 if (my_last_c.wire == other_c.wire && my_last_c.offset + my_last_c.width == other_c.offset) {
2453 my_last_c.width += other_c.width;
2454 } else
2455 chunks_.push_back(other_c);
2456 }
2457 else
2458 bits_.insert(bits_.end(), signal.bits_.begin(), signal.bits_.end());
2459
2460 width_ += signal.width_;
2461 check();
2462 }
2463
2464 void RTLIL::SigSpec::append_bit(const RTLIL::SigBit &bit)
2465 {
2466 if (packed())
2467 {
2468 cover("kernel.rtlil.sigspec.append_bit.packed");
2469
2470 if (chunks_.size() == 0)
2471 chunks_.push_back(bit);
2472 else
2473 if (bit.wire == NULL)
2474 if (chunks_.back().wire == NULL) {
2475 chunks_.back().data.bits.push_back(bit.data);
2476 chunks_.back().width++;
2477 } else
2478 chunks_.push_back(bit);
2479 else
2480 if (chunks_.back().wire == bit.wire && chunks_.back().offset + chunks_.back().width == bit.offset)
2481 chunks_.back().width++;
2482 else
2483 chunks_.push_back(bit);
2484 }
2485 else
2486 {
2487 cover("kernel.rtlil.sigspec.append_bit.unpacked");
2488 bits_.push_back(bit);
2489 }
2490
2491 width_++;
2492 check();
2493 }
2494
2495 void RTLIL::SigSpec::extend(int width, bool is_signed)
2496 {
2497 cover("kernel.rtlil.sigspec.extend");
2498
2499 pack();
2500
2501 if (width_ > width)
2502 remove(width, width_ - width);
2503
2504 if (width_ < width) {
2505 RTLIL::SigSpec padding = width_ > 0 ? extract(width_ - 1, 1) : RTLIL::SigSpec(RTLIL::State::S0);
2506 if (!is_signed && padding != RTLIL::SigSpec(RTLIL::State::Sx) && padding != RTLIL::SigSpec(RTLIL::State::Sz) &&
2507 padding != RTLIL::SigSpec(RTLIL::State::Sa) && padding != RTLIL::SigSpec(RTLIL::State::Sm))
2508 padding = RTLIL::SigSpec(RTLIL::State::S0);
2509 while (width_ < width)
2510 append(padding);
2511 }
2512 }
2513
2514 void RTLIL::SigSpec::extend_u0(int width, bool is_signed)
2515 {
2516 cover("kernel.rtlil.sigspec.extend_u0");
2517
2518 pack();
2519
2520 if (width_ > width)
2521 remove(width, width_ - width);
2522
2523 if (width_ < width) {
2524 RTLIL::SigSpec padding = width_ > 0 ? extract(width_ - 1, 1) : RTLIL::SigSpec(RTLIL::State::S0);
2525 if (!is_signed)
2526 padding = RTLIL::SigSpec(RTLIL::State::S0);
2527 while (width_ < width)
2528 append(padding);
2529 }
2530
2531 }
2532
2533 RTLIL::SigSpec RTLIL::SigSpec::repeat(int num) const
2534 {
2535 cover("kernel.rtlil.sigspec.repeat");
2536
2537 RTLIL::SigSpec sig;
2538 for (int i = 0; i < num; i++)
2539 sig.append(*this);
2540 return sig;
2541 }
2542
2543 #ifndef NDEBUG
2544 void RTLIL::SigSpec::check() const
2545 {
2546 if (width_ > 64)
2547 {
2548 cover("kernel.rtlil.sigspec.check.skip");
2549 }
2550 else if (packed())
2551 {
2552 cover("kernel.rtlil.sigspec.check.packed");
2553
2554 int w = 0;
2555 for (size_t i = 0; i < chunks_.size(); i++) {
2556 const RTLIL::SigChunk chunk = chunks_[i];
2557 if (chunk.wire == NULL) {
2558 if (i > 0)
2559 log_assert(chunks_[i-1].wire != NULL);
2560 log_assert(chunk.offset == 0);
2561 log_assert(chunk.data.bits.size() == (size_t)chunk.width);
2562 } else {
2563 if (i > 0 && chunks_[i-1].wire == chunk.wire)
2564 log_assert(chunk.offset != chunks_[i-1].offset + chunks_[i-1].width);
2565 log_assert(chunk.offset >= 0);
2566 log_assert(chunk.width >= 0);
2567 log_assert(chunk.offset + chunk.width <= chunk.wire->width);
2568 log_assert(chunk.data.bits.size() == 0);
2569 }
2570 w += chunk.width;
2571 }
2572 log_assert(w == width_);
2573 log_assert(bits_.empty());
2574 }
2575 else
2576 {
2577 cover("kernel.rtlil.sigspec.check.unpacked");
2578
2579 log_assert(width_ == SIZE(bits_));
2580 log_assert(chunks_.empty());
2581 }
2582 }
2583 #endif
2584
2585 bool RTLIL::SigSpec::operator <(const RTLIL::SigSpec &other) const
2586 {
2587 cover("kernel.rtlil.sigspec.comp_lt");
2588
2589 if (this == &other)
2590 return false;
2591
2592 if (width_ != other.width_)
2593 return width_ < other.width_;
2594
2595 pack();
2596 other.pack();
2597
2598 if (chunks_.size() != other.chunks_.size())
2599 return chunks_.size() < other.chunks_.size();
2600
2601 hash();
2602 other.hash();
2603
2604 if (hash_ != other.hash_)
2605 return hash_ < other.hash_;
2606
2607 for (size_t i = 0; i < chunks_.size(); i++)
2608 if (chunks_[i] != other.chunks_[i]) {
2609 cover("kernel.rtlil.sigspec.comp_lt.hash_collision");
2610 return chunks_[i] < other.chunks_[i];
2611 }
2612
2613 cover("kernel.rtlil.sigspec.comp_lt.equal");
2614 return false;
2615 }
2616
2617 bool RTLIL::SigSpec::operator ==(const RTLIL::SigSpec &other) const
2618 {
2619 cover("kernel.rtlil.sigspec.comp_eq");
2620
2621 if (this == &other)
2622 return true;
2623
2624 if (width_ != other.width_)
2625 return false;
2626
2627 pack();
2628 other.pack();
2629
2630 if (chunks_.size() != chunks_.size())
2631 return false;
2632
2633 hash();
2634 other.hash();
2635
2636 if (hash_ != other.hash_)
2637 return false;
2638
2639 for (size_t i = 0; i < chunks_.size(); i++)
2640 if (chunks_[i] != other.chunks_[i]) {
2641 cover("kernel.rtlil.sigspec.comp_eq.hash_collision");
2642 return false;
2643 }
2644
2645 cover("kernel.rtlil.sigspec.comp_eq.equal");
2646 return true;
2647 }
2648
2649 bool RTLIL::SigSpec::is_wire() const
2650 {
2651 cover("kernel.rtlil.sigspec.is_wire");
2652
2653 pack();
2654 return SIZE(chunks_) == 1 && chunks_[0].wire && chunks_[0].wire->width == width_;
2655 }
2656
2657 bool RTLIL::SigSpec::is_chunk() const
2658 {
2659 cover("kernel.rtlil.sigspec.is_chunk");
2660
2661 pack();
2662 return SIZE(chunks_) == 1;
2663 }
2664
2665 bool RTLIL::SigSpec::is_fully_const() const
2666 {
2667 cover("kernel.rtlil.sigspec.is_fully_const");
2668
2669 pack();
2670 for (auto it = chunks_.begin(); it != chunks_.end(); it++)
2671 if (it->width > 0 && it->wire != NULL)
2672 return false;
2673 return true;
2674 }
2675
2676 bool RTLIL::SigSpec::is_fully_def() const
2677 {
2678 cover("kernel.rtlil.sigspec.is_fully_def");
2679
2680 pack();
2681 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
2682 if (it->width > 0 && it->wire != NULL)
2683 return false;
2684 for (size_t i = 0; i < it->data.bits.size(); i++)
2685 if (it->data.bits[i] != RTLIL::State::S0 && it->data.bits[i] != RTLIL::State::S1)
2686 return false;
2687 }
2688 return true;
2689 }
2690
2691 bool RTLIL::SigSpec::is_fully_undef() const
2692 {
2693 cover("kernel.rtlil.sigspec.is_fully_undef");
2694
2695 pack();
2696 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
2697 if (it->width > 0 && it->wire != NULL)
2698 return false;
2699 for (size_t i = 0; i < it->data.bits.size(); i++)
2700 if (it->data.bits[i] != RTLIL::State::Sx && it->data.bits[i] != RTLIL::State::Sz)
2701 return false;
2702 }
2703 return true;
2704 }
2705
2706 bool RTLIL::SigSpec::has_marked_bits() const
2707 {
2708 cover("kernel.rtlil.sigspec.has_marked_bits");
2709
2710 pack();
2711 for (auto it = chunks_.begin(); it != chunks_.end(); it++)
2712 if (it->width > 0 && it->wire == NULL) {
2713 for (size_t i = 0; i < it->data.bits.size(); i++)
2714 if (it->data.bits[i] == RTLIL::State::Sm)
2715 return true;
2716 }
2717 return false;
2718 }
2719
2720 bool RTLIL::SigSpec::as_bool() const
2721 {
2722 cover("kernel.rtlil.sigspec.as_bool");
2723
2724 pack();
2725 log_assert(is_fully_const() && SIZE(chunks_) <= 1);
2726 if (width_)
2727 return chunks_[0].data.as_bool();
2728 return false;
2729 }
2730
2731 int RTLIL::SigSpec::as_int(bool is_signed) const
2732 {
2733 cover("kernel.rtlil.sigspec.as_int");
2734
2735 pack();
2736 log_assert(is_fully_const() && SIZE(chunks_) <= 1);
2737 if (width_)
2738 return chunks_[0].data.as_int(is_signed);
2739 return 0;
2740 }
2741
2742 std::string RTLIL::SigSpec::as_string() const
2743 {
2744 cover("kernel.rtlil.sigspec.as_string");
2745
2746 pack();
2747 std::string str;
2748 for (size_t i = chunks_.size(); i > 0; i--) {
2749 const RTLIL::SigChunk &chunk = chunks_[i-1];
2750 if (chunk.wire != NULL)
2751 for (int j = 0; j < chunk.width; j++)
2752 str += "?";
2753 else
2754 str += chunk.data.as_string();
2755 }
2756 return str;
2757 }
2758
2759 RTLIL::Const RTLIL::SigSpec::as_const() const
2760 {
2761 cover("kernel.rtlil.sigspec.as_const");
2762
2763 pack();
2764 log_assert(is_fully_const() && SIZE(chunks_) <= 1);
2765 if (width_)
2766 return chunks_[0].data;
2767 return RTLIL::Const();
2768 }
2769
2770 RTLIL::Wire *RTLIL::SigSpec::as_wire() const
2771 {
2772 cover("kernel.rtlil.sigspec.as_wire");
2773
2774 pack();
2775 log_assert(is_wire());
2776 return chunks_[0].wire;
2777 }
2778
2779 RTLIL::SigChunk RTLIL::SigSpec::as_chunk() const
2780 {
2781 cover("kernel.rtlil.sigspec.as_chunk");
2782
2783 pack();
2784 log_assert(is_chunk());
2785 return chunks_[0];
2786 }
2787
2788 bool RTLIL::SigSpec::match(std::string pattern) const
2789 {
2790 cover("kernel.rtlil.sigspec.match");
2791
2792 pack();
2793 std::string str = as_string();
2794 log_assert(pattern.size() == str.size());
2795
2796 for (size_t i = 0; i < pattern.size(); i++) {
2797 if (pattern[i] == ' ')
2798 continue;
2799 if (pattern[i] == '*') {
2800 if (str[i] != 'z' && str[i] != 'x')
2801 return false;
2802 continue;
2803 }
2804 if (pattern[i] != str[i])
2805 return false;
2806 }
2807
2808 return true;
2809 }
2810
2811 std::set<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_set() const
2812 {
2813 cover("kernel.rtlil.sigspec.to_sigbit_set");
2814
2815 pack();
2816 std::set<RTLIL::SigBit> sigbits;
2817 for (auto &c : chunks_)
2818 for (int i = 0; i < c.width; i++)
2819 sigbits.insert(RTLIL::SigBit(c, i));
2820 return sigbits;
2821 }
2822
2823 std::vector<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_vector() const
2824 {
2825 cover("kernel.rtlil.sigspec.to_sigbit_vector");
2826
2827 unpack();
2828 return bits_;
2829 }
2830
2831 std::map<RTLIL::SigBit, RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_map(const RTLIL::SigSpec &other) const
2832 {
2833 cover("kernel.rtlil.sigspec.to_sigbit_map");
2834
2835 unpack();
2836 other.unpack();
2837
2838 log_assert(width_ == other.width_);
2839
2840 std::map<RTLIL::SigBit, RTLIL::SigBit> new_map;
2841 for (int i = 0; i < width_; i++)
2842 new_map[bits_[i]] = other.bits_[i];
2843
2844 return new_map;
2845 }
2846
2847 RTLIL::SigBit RTLIL::SigSpec::to_single_sigbit() const
2848 {
2849 cover("kernel.rtlil.sigspec.to_single_sigbit");
2850
2851 pack();
2852 log_assert(width_ == 1);
2853 for (auto &c : chunks_)
2854 if (c.width)
2855 return RTLIL::SigBit(c);
2856 log_abort();
2857 }
2858
2859 static void sigspec_parse_split(std::vector<std::string> &tokens, const std::string &text, char sep)
2860 {
2861 size_t start = 0, end = 0;
2862 while ((end = text.find(sep, start)) != std::string::npos) {
2863 tokens.push_back(text.substr(start, end - start));
2864 start = end + 1;
2865 }
2866 tokens.push_back(text.substr(start));
2867 }
2868
2869 static int sigspec_parse_get_dummy_line_num()
2870 {
2871 return 0;
2872 }
2873
2874 bool RTLIL::SigSpec::parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str)
2875 {
2876 cover("kernel.rtlil.sigspec.parse");
2877
2878 std::vector<std::string> tokens;
2879 sigspec_parse_split(tokens, str, ',');
2880
2881 sig = RTLIL::SigSpec();
2882 for (int tokidx = int(tokens.size())-1; tokidx >= 0; tokidx--)
2883 {
2884 std::string netname = tokens[tokidx];
2885 std::string indices;
2886
2887 if (netname.size() == 0)
2888 continue;
2889
2890 if ('0' <= netname[0] && netname[0] <= '9') {
2891 cover("kernel.rtlil.sigspec.parse.const");
2892 AST::get_line_num = sigspec_parse_get_dummy_line_num;
2893 AST::AstNode *ast = VERILOG_FRONTEND::const2ast(netname);
2894 if (ast == NULL)
2895 return false;
2896 sig.append(RTLIL::Const(ast->bits));
2897 delete ast;
2898 continue;
2899 }
2900
2901 if (module == NULL)
2902 return false;
2903
2904 cover("kernel.rtlil.sigspec.parse.net");
2905
2906 if (netname[0] != '$' && netname[0] != '\\')
2907 netname = "\\" + netname;
2908
2909 if (module->wires_.count(netname) == 0) {
2910 size_t indices_pos = netname.size()-1;
2911 if (indices_pos > 2 && netname[indices_pos] == ']')
2912 {
2913 indices_pos--;
2914 while (indices_pos > 0 && ('0' <= netname[indices_pos] && netname[indices_pos] <= '9')) indices_pos--;
2915 if (indices_pos > 0 && netname[indices_pos] == ':') {
2916 indices_pos--;
2917 while (indices_pos > 0 && ('0' <= netname[indices_pos] && netname[indices_pos] <= '9')) indices_pos--;
2918 }
2919 if (indices_pos > 0 && netname[indices_pos] == '[') {
2920 indices = netname.substr(indices_pos);
2921 netname = netname.substr(0, indices_pos);
2922 }
2923 }
2924 }
2925
2926 if (module->wires_.count(netname) == 0)
2927 return false;
2928
2929 RTLIL::Wire *wire = module->wires_.at(netname);
2930 if (!indices.empty()) {
2931 std::vector<std::string> index_tokens;
2932 sigspec_parse_split(index_tokens, indices.substr(1, indices.size()-2), ':');
2933 if (index_tokens.size() == 1) {
2934 cover("kernel.rtlil.sigspec.parse.bit_sel");
2935 sig.append(RTLIL::SigSpec(wire, atoi(index_tokens.at(0).c_str())));
2936 } else {
2937 cover("kernel.rtlil.sigspec.parse.part_sel");
2938 int a = atoi(index_tokens.at(0).c_str());
2939 int b = atoi(index_tokens.at(1).c_str());
2940 if (a > b) {
2941 int tmp = a;
2942 a = b, b = tmp;
2943 }
2944 sig.append(RTLIL::SigSpec(wire, a, b-a+1));
2945 }
2946 } else
2947 sig.append(wire);
2948 }
2949
2950 return true;
2951 }
2952
2953 bool RTLIL::SigSpec::parse_sel(RTLIL::SigSpec &sig, RTLIL::Design *design, RTLIL::Module *module, std::string str)
2954 {
2955 if (str.empty() || str[0] != '@')
2956 return parse(sig, module, str);
2957
2958 cover("kernel.rtlil.sigspec.parse.sel");
2959
2960 str = RTLIL::escape_id(str.substr(1));
2961 if (design->selection_vars.count(str) == 0)
2962 return false;
2963
2964 sig = RTLIL::SigSpec();
2965 RTLIL::Selection &sel = design->selection_vars.at(str);
2966 for (auto &it : module->wires_)
2967 if (sel.selected_member(module->name, it.first))
2968 sig.append(it.second);
2969
2970 return true;
2971 }
2972
2973 bool RTLIL::SigSpec::parse_rhs(const RTLIL::SigSpec &lhs, RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str)
2974 {
2975 if (str == "0") {
2976 cover("kernel.rtlil.sigspec.parse.rhs_zeros");
2977 sig = RTLIL::SigSpec(RTLIL::State::S0, lhs.width_);
2978 return true;
2979 }
2980
2981 if (str == "~0") {
2982 cover("kernel.rtlil.sigspec.parse.rhs_ones");
2983 sig = RTLIL::SigSpec(RTLIL::State::S1, lhs.width_);
2984 return true;
2985 }
2986
2987 if (lhs.chunks_.size() == 1) {
2988 char *p = (char*)str.c_str(), *endptr;
2989 long long int val = strtoll(p, &endptr, 10);
2990 if (endptr && endptr != p && *endptr == 0) {
2991 sig = RTLIL::SigSpec(val, lhs.width_);
2992 cover("kernel.rtlil.sigspec.parse.rhs_dec");
2993 return true;
2994 }
2995 }
2996
2997 return parse(sig, module, str);
2998 }
2999
3000 RTLIL::CaseRule::~CaseRule()
3001 {
3002 for (auto it = switches.begin(); it != switches.end(); it++)
3003 delete *it;
3004 }
3005
3006 RTLIL::CaseRule *RTLIL::CaseRule::clone() const
3007 {
3008 RTLIL::CaseRule *new_caserule = new RTLIL::CaseRule;
3009 new_caserule->compare = compare;
3010 new_caserule->actions = actions;
3011 for (auto &it : switches)
3012 new_caserule->switches.push_back(it->clone());
3013 return new_caserule;
3014 }
3015
3016 RTLIL::SwitchRule::~SwitchRule()
3017 {
3018 for (auto it = cases.begin(); it != cases.end(); it++)
3019 delete *it;
3020 }
3021
3022 RTLIL::SwitchRule *RTLIL::SwitchRule::clone() const
3023 {
3024 RTLIL::SwitchRule *new_switchrule = new RTLIL::SwitchRule;
3025 new_switchrule->signal = signal;
3026 new_switchrule->attributes = attributes;
3027 for (auto &it : cases)
3028 new_switchrule->cases.push_back(it->clone());
3029 return new_switchrule;
3030
3031 }
3032
3033 RTLIL::SyncRule *RTLIL::SyncRule::clone() const
3034 {
3035 RTLIL::SyncRule *new_syncrule = new RTLIL::SyncRule;
3036 new_syncrule->type = type;
3037 new_syncrule->signal = signal;
3038 new_syncrule->actions = actions;
3039 return new_syncrule;
3040 }
3041
3042 RTLIL::Process::~Process()
3043 {
3044 for (auto it = syncs.begin(); it != syncs.end(); it++)
3045 delete *it;
3046 }
3047
3048 RTLIL::Process *RTLIL::Process::clone() const
3049 {
3050 RTLIL::Process *new_proc = new RTLIL::Process;
3051
3052 new_proc->name = name;
3053 new_proc->attributes = attributes;
3054
3055 RTLIL::CaseRule *rc_ptr = root_case.clone();
3056 new_proc->root_case = *rc_ptr;
3057 rc_ptr->switches.clear();
3058 delete rc_ptr;
3059
3060 for (auto &it : syncs)
3061 new_proc->syncs.push_back(it->clone());
3062
3063 return new_proc;
3064 }
3065
3066 YOSYS_NAMESPACE_END
3067