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Removed $bu0 cell type
[yosys.git] / kernel / rtlil.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 #include "kernel/yosys.h"
21 #include "frontends/verilog/verilog_frontend.h"
22 #include "backends/ilang/ilang_backend.h"
23
24 #include <string.h>
25 #include <algorithm>
26
27 YOSYS_NAMESPACE_BEGIN
28
29 std::vector<int> RTLIL::IdString::global_refcount_storage_;
30 std::vector<char*> RTLIL::IdString::global_id_storage_;
31 std::map<char*, int, RTLIL::IdString::char_ptr_cmp> RTLIL::IdString::global_id_index_;
32 std::vector<int> RTLIL::IdString::global_free_idx_list_;
33
34 RTLIL::Const::Const()
35 {
36 flags = RTLIL::CONST_FLAG_NONE;
37 }
38
39 RTLIL::Const::Const(std::string str)
40 {
41 flags = RTLIL::CONST_FLAG_STRING;
42 for (int i = str.size()-1; i >= 0; i--) {
43 unsigned char ch = str[i];
44 for (int j = 0; j < 8; j++) {
45 bits.push_back((ch & 1) != 0 ? RTLIL::S1 : RTLIL::S0);
46 ch = ch >> 1;
47 }
48 }
49 }
50
51 RTLIL::Const::Const(int val, int width)
52 {
53 flags = RTLIL::CONST_FLAG_NONE;
54 for (int i = 0; i < width; i++) {
55 bits.push_back((val & 1) != 0 ? RTLIL::S1 : RTLIL::S0);
56 val = val >> 1;
57 }
58 }
59
60 RTLIL::Const::Const(RTLIL::State bit, int width)
61 {
62 flags = RTLIL::CONST_FLAG_NONE;
63 for (int i = 0; i < width; i++)
64 bits.push_back(bit);
65 }
66
67 bool RTLIL::Const::operator <(const RTLIL::Const &other) const
68 {
69 if (bits.size() != other.bits.size())
70 return bits.size() < other.bits.size();
71 for (size_t i = 0; i < bits.size(); i++)
72 if (bits[i] != other.bits[i])
73 return bits[i] < other.bits[i];
74 return false;
75 }
76
77 bool RTLIL::Const::operator ==(const RTLIL::Const &other) const
78 {
79 return bits == other.bits;
80 }
81
82 bool RTLIL::Const::operator !=(const RTLIL::Const &other) const
83 {
84 return bits != other.bits;
85 }
86
87 bool RTLIL::Const::as_bool() const
88 {
89 for (size_t i = 0; i < bits.size(); i++)
90 if (bits[i] == RTLIL::S1)
91 return true;
92 return false;
93 }
94
95 int RTLIL::Const::as_int(bool is_signed) const
96 {
97 int32_t ret = 0;
98 for (size_t i = 0; i < bits.size() && i < 32; i++)
99 if (bits[i] == RTLIL::S1)
100 ret |= 1 << i;
101 if (is_signed && bits.back() == RTLIL::S1)
102 for (size_t i = bits.size(); i < 32; i++)
103 ret |= 1 << i;
104 return ret;
105 }
106
107 std::string RTLIL::Const::as_string() const
108 {
109 std::string ret;
110 for (size_t i = bits.size(); i > 0; i--)
111 switch (bits[i-1]) {
112 case S0: ret += "0"; break;
113 case S1: ret += "1"; break;
114 case Sx: ret += "x"; break;
115 case Sz: ret += "z"; break;
116 case Sa: ret += "-"; break;
117 case Sm: ret += "m"; break;
118 }
119 return ret;
120 }
121
122 std::string RTLIL::Const::decode_string() const
123 {
124 std::string string;
125 std::vector <char> string_chars;
126 for (int i = 0; i < int (bits.size()); i += 8) {
127 char ch = 0;
128 for (int j = 0; j < 8 && i + j < int (bits.size()); j++)
129 if (bits[i + j] == RTLIL::State::S1)
130 ch |= 1 << j;
131 if (ch != 0)
132 string_chars.push_back(ch);
133 }
134 for (int i = int (string_chars.size()) - 1; i >= 0; i--)
135 string += string_chars[i];
136 return string;
137 }
138
139 bool RTLIL::Selection::selected_module(RTLIL::IdString mod_name) const
140 {
141 if (full_selection)
142 return true;
143 if (selected_modules.count(mod_name) > 0)
144 return true;
145 if (selected_members.count(mod_name) > 0)
146 return true;
147 return false;
148 }
149
150 bool RTLIL::Selection::selected_whole_module(RTLIL::IdString mod_name) const
151 {
152 if (full_selection)
153 return true;
154 if (selected_modules.count(mod_name) > 0)
155 return true;
156 return false;
157 }
158
159 bool RTLIL::Selection::selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const
160 {
161 if (full_selection)
162 return true;
163 if (selected_modules.count(mod_name) > 0)
164 return true;
165 if (selected_members.count(mod_name) > 0)
166 if (selected_members.at(mod_name).count(memb_name) > 0)
167 return true;
168 return false;
169 }
170
171 void RTLIL::Selection::optimize(RTLIL::Design *design)
172 {
173 if (full_selection) {
174 selected_modules.clear();
175 selected_members.clear();
176 return;
177 }
178
179 std::vector<RTLIL::IdString> del_list, add_list;
180
181 del_list.clear();
182 for (auto mod_name : selected_modules) {
183 if (design->modules_.count(mod_name) == 0)
184 del_list.push_back(mod_name);
185 selected_members.erase(mod_name);
186 }
187 for (auto mod_name : del_list)
188 selected_modules.erase(mod_name);
189
190 del_list.clear();
191 for (auto &it : selected_members)
192 if (design->modules_.count(it.first) == 0)
193 del_list.push_back(it.first);
194 for (auto mod_name : del_list)
195 selected_members.erase(mod_name);
196
197 for (auto &it : selected_members) {
198 del_list.clear();
199 for (auto memb_name : it.second)
200 if (design->modules_[it.first]->count_id(memb_name) == 0)
201 del_list.push_back(memb_name);
202 for (auto memb_name : del_list)
203 it.second.erase(memb_name);
204 }
205
206 del_list.clear();
207 add_list.clear();
208 for (auto &it : selected_members)
209 if (it.second.size() == 0)
210 del_list.push_back(it.first);
211 else if (it.second.size() == design->modules_[it.first]->wires_.size() + design->modules_[it.first]->memories.size() +
212 design->modules_[it.first]->cells_.size() + design->modules_[it.first]->processes.size())
213 add_list.push_back(it.first);
214 for (auto mod_name : del_list)
215 selected_members.erase(mod_name);
216 for (auto mod_name : add_list) {
217 selected_members.erase(mod_name);
218 selected_modules.insert(mod_name);
219 }
220
221 if (selected_modules.size() == design->modules_.size()) {
222 full_selection = true;
223 selected_modules.clear();
224 selected_members.clear();
225 }
226 }
227
228 RTLIL::Design::Design()
229 {
230 refcount_modules_ = 0;
231 selection_stack.push_back(RTLIL::Selection());
232 }
233
234 RTLIL::Design::~Design()
235 {
236 for (auto it = modules_.begin(); it != modules_.end(); it++)
237 delete it->second;
238 }
239
240 RTLIL::ObjRange<RTLIL::Module*> RTLIL::Design::modules()
241 {
242 return RTLIL::ObjRange<RTLIL::Module*>(&modules_, &refcount_modules_);
243 }
244
245 RTLIL::Module *RTLIL::Design::module(RTLIL::IdString name)
246 {
247 return modules_.count(name) ? modules_.at(name) : NULL;
248 }
249
250 void RTLIL::Design::add(RTLIL::Module *module)
251 {
252 log_assert(modules_.count(module->name) == 0);
253 log_assert(refcount_modules_ == 0);
254 modules_[module->name] = module;
255 module->design = this;
256
257 for (auto mon : monitors)
258 mon->notify_module_add(module);
259 }
260
261 RTLIL::Module *RTLIL::Design::addModule(RTLIL::IdString name)
262 {
263 log_assert(modules_.count(name) == 0);
264 log_assert(refcount_modules_ == 0);
265
266 RTLIL::Module *module = new RTLIL::Module;
267 modules_[name] = module;
268 module->design = this;
269 module->name = name;
270
271 for (auto mon : monitors)
272 mon->notify_module_add(module);
273
274 return module;
275 }
276
277 void RTLIL::Design::scratchpad_unset(std::string varname)
278 {
279 scratchpad.erase(varname);
280 }
281
282 void RTLIL::Design::scratchpad_set_int(std::string varname, int value)
283 {
284 scratchpad[varname] = stringf("%d", value);
285 }
286
287 void RTLIL::Design::scratchpad_set_bool(std::string varname, bool value)
288 {
289 scratchpad[varname] = value ? "true" : "false";
290 }
291
292 void RTLIL::Design::scratchpad_set_string(std::string varname, std::string value)
293 {
294 scratchpad[varname] = value;
295 }
296
297 int RTLIL::Design::scratchpad_get_int(std::string varname, int default_value) const
298 {
299 if (scratchpad.count(varname) == 0)
300 return default_value;
301
302 std::string str = scratchpad.at(varname);
303
304 if (str == "0" || str == "false")
305 return 0;
306
307 if (str == "1" || str == "true")
308 return 1;
309
310 char *endptr = nullptr;
311 long int parsed_value = strtol(str.c_str(), &endptr, 10);
312 return *endptr ? default_value : parsed_value;
313 }
314
315 bool RTLIL::Design::scratchpad_get_bool(std::string varname, bool default_value) const
316 {
317 if (scratchpad.count(varname) == 0)
318 return default_value;
319
320 std::string str = scratchpad.at(varname);
321
322 if (str == "0" || str == "false")
323 return false;
324
325 if (str == "1" || str == "true")
326 return true;
327
328 return default_value;
329 }
330
331 std::string RTLIL::Design::scratchpad_get_string(std::string varname, std::string default_value) const
332 {
333 if (scratchpad.count(varname) == 0)
334 return default_value;
335 return scratchpad.at(varname);
336 }
337
338 void RTLIL::Design::remove(RTLIL::Module *module)
339 {
340 for (auto mon : monitors)
341 mon->notify_module_del(module);
342
343 log_assert(modules_.at(module->name) == module);
344 modules_.erase(module->name);
345 delete module;
346 }
347
348 void RTLIL::Design::check()
349 {
350 #ifndef NDEBUG
351 for (auto &it : modules_) {
352 log_assert(this == it.second->design);
353 log_assert(it.first == it.second->name);
354 log_assert(!it.first.empty());
355 it.second->check();
356 }
357 #endif
358 }
359
360 void RTLIL::Design::optimize()
361 {
362 for (auto &it : modules_)
363 it.second->optimize();
364 for (auto &it : selection_stack)
365 it.optimize(this);
366 for (auto &it : selection_vars)
367 it.second.optimize(this);
368 }
369
370 bool RTLIL::Design::selected_module(RTLIL::IdString mod_name) const
371 {
372 if (!selected_active_module.empty() && mod_name != selected_active_module)
373 return false;
374 if (selection_stack.size() == 0)
375 return true;
376 return selection_stack.back().selected_module(mod_name);
377 }
378
379 bool RTLIL::Design::selected_whole_module(RTLIL::IdString mod_name) const
380 {
381 if (!selected_active_module.empty() && mod_name != selected_active_module)
382 return false;
383 if (selection_stack.size() == 0)
384 return true;
385 return selection_stack.back().selected_whole_module(mod_name);
386 }
387
388 bool RTLIL::Design::selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const
389 {
390 if (!selected_active_module.empty() && mod_name != selected_active_module)
391 return false;
392 if (selection_stack.size() == 0)
393 return true;
394 return selection_stack.back().selected_member(mod_name, memb_name);
395 }
396
397 bool RTLIL::Design::selected_module(RTLIL::Module *mod) const
398 {
399 return selected_module(mod->name);
400 }
401
402 bool RTLIL::Design::selected_whole_module(RTLIL::Module *mod) const
403 {
404 return selected_whole_module(mod->name);
405 }
406
407 std::vector<RTLIL::Module*> RTLIL::Design::selected_modules() const
408 {
409 std::vector<RTLIL::Module*> result;
410 result.reserve(modules_.size());
411 for (auto &it : modules_)
412 if (selected_module(it.first))
413 result.push_back(it.second);
414 return result;
415 }
416
417 std::vector<RTLIL::Module*> RTLIL::Design::selected_whole_modules() const
418 {
419 std::vector<RTLIL::Module*> result;
420 result.reserve(modules_.size());
421 for (auto &it : modules_)
422 if (selected_whole_module(it.first))
423 result.push_back(it.second);
424 return result;
425 }
426
427 std::vector<RTLIL::Module*> RTLIL::Design::selected_whole_modules_warn() const
428 {
429 std::vector<RTLIL::Module*> result;
430 result.reserve(modules_.size());
431 for (auto &it : modules_)
432 if (selected_whole_module(it.first))
433 result.push_back(it.second);
434 else if (selected_module(it.first))
435 log("Warning: Ignoring partially selected module %s.\n", log_id(it.first));
436 return result;
437 }
438
439 RTLIL::Module::Module()
440 {
441 design = nullptr;
442 refcount_wires_ = 0;
443 refcount_cells_ = 0;
444 }
445
446 RTLIL::Module::~Module()
447 {
448 for (auto it = wires_.begin(); it != wires_.end(); it++)
449 delete it->second;
450 for (auto it = memories.begin(); it != memories.end(); it++)
451 delete it->second;
452 for (auto it = cells_.begin(); it != cells_.end(); it++)
453 delete it->second;
454 for (auto it = processes.begin(); it != processes.end(); it++)
455 delete it->second;
456 }
457
458 RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, std::map<RTLIL::IdString, RTLIL::Const>)
459 {
460 log_error("Module `%s' is used with parameters but is not parametric!\n", id2cstr(name));
461 }
462
463 size_t RTLIL::Module::count_id(RTLIL::IdString id)
464 {
465 return wires_.count(id) + memories.count(id) + cells_.count(id) + processes.count(id);
466 }
467
468 #ifndef NDEBUG
469 namespace {
470 struct InternalCellChecker
471 {
472 RTLIL::Module *module;
473 RTLIL::Cell *cell;
474 std::set<RTLIL::IdString> expected_params, expected_ports;
475
476 InternalCellChecker(RTLIL::Module *module, RTLIL::Cell *cell) : module(module), cell(cell) { }
477
478 void error(int linenr)
479 {
480 std::stringstream buf;
481 ILANG_BACKEND::dump_cell(buf, " ", cell);
482
483 log_error("Found error in internal cell %s%s%s (%s) at %s:%d:\n%s",
484 module ? module->name.c_str() : "", module ? "." : "",
485 cell->name.c_str(), cell->type.c_str(), __FILE__, linenr, buf.str().c_str());
486 }
487
488 int param(const char *name)
489 {
490 if (cell->parameters.count(name) == 0)
491 error(__LINE__);
492 expected_params.insert(name);
493 return cell->parameters.at(name).as_int();
494 }
495
496 int param_bool(const char *name)
497 {
498 int v = param(name);
499 if (cell->parameters.at(name).bits.size() > 32)
500 error(__LINE__);
501 if (v != 0 && v != 1)
502 error(__LINE__);
503 return v;
504 }
505
506 void param_bits(const char *name, int width)
507 {
508 param(name);
509 if (int(cell->parameters.at(name).bits.size()) != width)
510 error(__LINE__);
511 }
512
513 void port(const char *name, int width)
514 {
515 if (!cell->hasPort(name))
516 error(__LINE__);
517 if (cell->getPort(name).size() != width)
518 error(__LINE__);
519 expected_ports.insert(name);
520 }
521
522 void check_expected(bool check_matched_sign = true)
523 {
524 for (auto &para : cell->parameters)
525 if (expected_params.count(para.first) == 0)
526 error(__LINE__);
527 for (auto &conn : cell->connections())
528 if (expected_ports.count(conn.first) == 0)
529 error(__LINE__);
530
531 if (expected_params.count("\\A_SIGNED") != 0 && expected_params.count("\\B_SIGNED") && check_matched_sign) {
532 bool a_is_signed = param("\\A_SIGNED") != 0;
533 bool b_is_signed = param("\\B_SIGNED") != 0;
534 if (a_is_signed != b_is_signed)
535 error(__LINE__);
536 }
537 }
538
539 void check_gate(const char *ports)
540 {
541 if (cell->parameters.size() != 0)
542 error(__LINE__);
543
544 for (const char *p = ports; *p; p++) {
545 char portname[3] = { '\\', *p, 0 };
546 if (!cell->hasPort(portname))
547 error(__LINE__);
548 if (cell->getPort(portname).size() != 1)
549 error(__LINE__);
550 }
551
552 for (auto &conn : cell->connections()) {
553 if (conn.first.size() != 2 || conn.first[0] != '\\')
554 error(__LINE__);
555 if (strchr(ports, conn.first[1]) == NULL)
556 error(__LINE__);
557 }
558 }
559
560 void check()
561 {
562 if (cell->type.substr(0, 1) != "$" || cell->type.substr(0, 3) == "$__" || cell->type.substr(0, 8) == "$paramod" ||
563 cell->type.substr(0, 9) == "$verific$" || cell->type.substr(0, 7) == "$array:" || cell->type.substr(0, 8) == "$extern:")
564 return;
565
566 if (cell->type.in("$not", "$pos", "$neg")) {
567 param_bool("\\A_SIGNED");
568 port("\\A", param("\\A_WIDTH"));
569 port("\\Y", param("\\Y_WIDTH"));
570 check_expected();
571 return;
572 }
573
574 if (cell->type.in("$and", "$or", "$xor", "$xnor")) {
575 param_bool("\\A_SIGNED");
576 param_bool("\\B_SIGNED");
577 port("\\A", param("\\A_WIDTH"));
578 port("\\B", param("\\B_WIDTH"));
579 port("\\Y", param("\\Y_WIDTH"));
580 check_expected();
581 return;
582 }
583
584 if (cell->type.in("$reduce_and", "$reduce_or", "$reduce_xor", "$reduce_xnor", "$reduce_bool")) {
585 param_bool("\\A_SIGNED");
586 port("\\A", param("\\A_WIDTH"));
587 port("\\Y", param("\\Y_WIDTH"));
588 check_expected();
589 return;
590 }
591
592 if (cell->type.in("$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx")) {
593 param_bool("\\A_SIGNED");
594 param_bool("\\B_SIGNED");
595 port("\\A", param("\\A_WIDTH"));
596 port("\\B", param("\\B_WIDTH"));
597 port("\\Y", param("\\Y_WIDTH"));
598 check_expected(false);
599 return;
600 }
601
602 if (cell->type.in("$lt", "$le", "$eq", "$ne", "$eqx", "$nex", "$ge", "$gt")) {
603 param_bool("\\A_SIGNED");
604 param_bool("\\B_SIGNED");
605 port("\\A", param("\\A_WIDTH"));
606 port("\\B", param("\\B_WIDTH"));
607 port("\\Y", param("\\Y_WIDTH"));
608 check_expected();
609 return;
610 }
611
612 if (cell->type.in("$add", "$sub", "$mul", "$div", "$mod", "$pow")) {
613 param_bool("\\A_SIGNED");
614 param_bool("\\B_SIGNED");
615 port("\\A", param("\\A_WIDTH"));
616 port("\\B", param("\\B_WIDTH"));
617 port("\\Y", param("\\Y_WIDTH"));
618 check_expected(cell->type != "$pow");
619 return;
620 }
621
622 if (cell->type == "$alu") {
623 param_bool("\\A_SIGNED");
624 param_bool("\\B_SIGNED");
625 port("\\A", param("\\A_WIDTH"));
626 port("\\B", param("\\B_WIDTH"));
627 port("\\CI", 1);
628 port("\\BI", 1);
629 port("\\X", param("\\Y_WIDTH"));
630 port("\\Y", param("\\Y_WIDTH"));
631 port("\\CO", param("\\Y_WIDTH"));
632 check_expected();
633 return;
634 }
635
636 if (cell->type == "$logic_not") {
637 param_bool("\\A_SIGNED");
638 port("\\A", param("\\A_WIDTH"));
639 port("\\Y", param("\\Y_WIDTH"));
640 check_expected();
641 return;
642 }
643
644 if (cell->type == "$logic_and" || cell->type == "$logic_or") {
645 param_bool("\\A_SIGNED");
646 param_bool("\\B_SIGNED");
647 port("\\A", param("\\A_WIDTH"));
648 port("\\B", param("\\B_WIDTH"));
649 port("\\Y", param("\\Y_WIDTH"));
650 check_expected(false);
651 return;
652 }
653
654 if (cell->type == "$slice") {
655 param("\\OFFSET");
656 port("\\A", param("\\A_WIDTH"));
657 port("\\Y", param("\\Y_WIDTH"));
658 if (param("\\OFFSET") + param("\\Y_WIDTH") > param("\\A_WIDTH"))
659 error(__LINE__);
660 check_expected();
661 return;
662 }
663
664 if (cell->type == "$concat") {
665 port("\\A", param("\\A_WIDTH"));
666 port("\\B", param("\\B_WIDTH"));
667 port("\\Y", param("\\A_WIDTH") + param("\\B_WIDTH"));
668 check_expected();
669 return;
670 }
671
672 if (cell->type == "$mux") {
673 port("\\A", param("\\WIDTH"));
674 port("\\B", param("\\WIDTH"));
675 port("\\S", 1);
676 port("\\Y", param("\\WIDTH"));
677 check_expected();
678 return;
679 }
680
681 if (cell->type == "$pmux") {
682 port("\\A", param("\\WIDTH"));
683 port("\\B", param("\\WIDTH") * param("\\S_WIDTH"));
684 port("\\S", param("\\S_WIDTH"));
685 port("\\Y", param("\\WIDTH"));
686 check_expected();
687 return;
688 }
689
690 if (cell->type == "$lut") {
691 param("\\LUT");
692 port("\\A", param("\\WIDTH"));
693 port("\\Y", 1);
694 check_expected();
695 return;
696 }
697
698 if (cell->type == "$sr") {
699 param_bool("\\SET_POLARITY");
700 param_bool("\\CLR_POLARITY");
701 port("\\SET", param("\\WIDTH"));
702 port("\\CLR", param("\\WIDTH"));
703 port("\\Q", param("\\WIDTH"));
704 check_expected();
705 return;
706 }
707
708 if (cell->type == "$dff") {
709 param_bool("\\CLK_POLARITY");
710 port("\\CLK", 1);
711 port("\\D", param("\\WIDTH"));
712 port("\\Q", param("\\WIDTH"));
713 check_expected();
714 return;
715 }
716
717 if (cell->type == "$dffsr") {
718 param_bool("\\CLK_POLARITY");
719 param_bool("\\SET_POLARITY");
720 param_bool("\\CLR_POLARITY");
721 port("\\CLK", 1);
722 port("\\SET", param("\\WIDTH"));
723 port("\\CLR", param("\\WIDTH"));
724 port("\\D", param("\\WIDTH"));
725 port("\\Q", param("\\WIDTH"));
726 check_expected();
727 return;
728 }
729
730 if (cell->type == "$adff") {
731 param_bool("\\CLK_POLARITY");
732 param_bool("\\ARST_POLARITY");
733 param_bits("\\ARST_VALUE", param("\\WIDTH"));
734 port("\\CLK", 1);
735 port("\\ARST", 1);
736 port("\\D", param("\\WIDTH"));
737 port("\\Q", param("\\WIDTH"));
738 check_expected();
739 return;
740 }
741
742 if (cell->type == "$dlatch") {
743 param_bool("\\EN_POLARITY");
744 port("\\EN", 1);
745 port("\\D", param("\\WIDTH"));
746 port("\\Q", param("\\WIDTH"));
747 check_expected();
748 return;
749 }
750
751 if (cell->type == "$dlatchsr") {
752 param_bool("\\EN_POLARITY");
753 param_bool("\\SET_POLARITY");
754 param_bool("\\CLR_POLARITY");
755 port("\\EN", 1);
756 port("\\SET", param("\\WIDTH"));
757 port("\\CLR", param("\\WIDTH"));
758 port("\\D", param("\\WIDTH"));
759 port("\\Q", param("\\WIDTH"));
760 check_expected();
761 return;
762 }
763
764 if (cell->type == "$fsm") {
765 param("\\NAME");
766 param_bool("\\CLK_POLARITY");
767 param_bool("\\ARST_POLARITY");
768 param("\\STATE_BITS");
769 param("\\STATE_NUM");
770 param("\\STATE_NUM_LOG2");
771 param("\\STATE_RST");
772 param_bits("\\STATE_TABLE", param("\\STATE_BITS") * param("\\STATE_NUM"));
773 param("\\TRANS_NUM");
774 param_bits("\\TRANS_TABLE", param("\\TRANS_NUM") * (2*param("\\STATE_NUM_LOG2") + param("\\CTRL_IN_WIDTH") + param("\\CTRL_OUT_WIDTH")));
775 port("\\CLK", 1);
776 port("\\ARST", 1);
777 port("\\CTRL_IN", param("\\CTRL_IN_WIDTH"));
778 port("\\CTRL_OUT", param("\\CTRL_OUT_WIDTH"));
779 check_expected();
780 return;
781 }
782
783 if (cell->type == "$memrd") {
784 param("\\MEMID");
785 param_bool("\\CLK_ENABLE");
786 param_bool("\\CLK_POLARITY");
787 param_bool("\\TRANSPARENT");
788 port("\\CLK", 1);
789 port("\\ADDR", param("\\ABITS"));
790 port("\\DATA", param("\\WIDTH"));
791 check_expected();
792 return;
793 }
794
795 if (cell->type == "$memwr") {
796 param("\\MEMID");
797 param_bool("\\CLK_ENABLE");
798 param_bool("\\CLK_POLARITY");
799 param("\\PRIORITY");
800 port("\\CLK", 1);
801 port("\\EN", param("\\WIDTH"));
802 port("\\ADDR", param("\\ABITS"));
803 port("\\DATA", param("\\WIDTH"));
804 check_expected();
805 return;
806 }
807
808 if (cell->type == "$mem") {
809 param("\\MEMID");
810 param("\\SIZE");
811 param("\\OFFSET");
812 param_bits("\\RD_CLK_ENABLE", param("\\RD_PORTS"));
813 param_bits("\\RD_CLK_POLARITY", param("\\RD_PORTS"));
814 param_bits("\\RD_TRANSPARENT", param("\\RD_PORTS"));
815 param_bits("\\WR_CLK_ENABLE", param("\\WR_PORTS"));
816 param_bits("\\WR_CLK_POLARITY", param("\\WR_PORTS"));
817 port("\\RD_CLK", param("\\RD_PORTS"));
818 port("\\RD_ADDR", param("\\RD_PORTS") * param("\\ABITS"));
819 port("\\RD_DATA", param("\\RD_PORTS") * param("\\WIDTH"));
820 port("\\WR_CLK", param("\\WR_PORTS"));
821 port("\\WR_EN", param("\\WR_PORTS") * param("\\WIDTH"));
822 port("\\WR_ADDR", param("\\WR_PORTS") * param("\\ABITS"));
823 port("\\WR_DATA", param("\\WR_PORTS") * param("\\WIDTH"));
824 check_expected();
825 return;
826 }
827
828 if (cell->type == "$assert") {
829 port("\\A", 1);
830 port("\\EN", 1);
831 check_expected();
832 return;
833 }
834
835 if (cell->type == "$_NOT_") { check_gate("AY"); return; }
836 if (cell->type == "$_AND_") { check_gate("ABY"); return; }
837 if (cell->type == "$_NAND_") { check_gate("ABY"); return; }
838 if (cell->type == "$_OR_") { check_gate("ABY"); return; }
839 if (cell->type == "$_NOR_") { check_gate("ABY"); return; }
840 if (cell->type == "$_XOR_") { check_gate("ABY"); return; }
841 if (cell->type == "$_XNOR_") { check_gate("ABY"); return; }
842 if (cell->type == "$_MUX_") { check_gate("ABSY"); return; }
843 if (cell->type == "$_AOI3_") { check_gate("ABCY"); return; }
844 if (cell->type == "$_OAI3_") { check_gate("ABCY"); return; }
845 if (cell->type == "$_AOI4_") { check_gate("ABCDY"); return; }
846 if (cell->type == "$_OAI4_") { check_gate("ABCDY"); return; }
847
848 if (cell->type == "$_SR_NN_") { check_gate("SRQ"); return; }
849 if (cell->type == "$_SR_NP_") { check_gate("SRQ"); return; }
850 if (cell->type == "$_SR_PN_") { check_gate("SRQ"); return; }
851 if (cell->type == "$_SR_PP_") { check_gate("SRQ"); return; }
852
853 if (cell->type == "$_DFF_N_") { check_gate("DQC"); return; }
854 if (cell->type == "$_DFF_P_") { check_gate("DQC"); return; }
855
856 if (cell->type == "$_DFF_NN0_") { check_gate("DQCR"); return; }
857 if (cell->type == "$_DFF_NN1_") { check_gate("DQCR"); return; }
858 if (cell->type == "$_DFF_NP0_") { check_gate("DQCR"); return; }
859 if (cell->type == "$_DFF_NP1_") { check_gate("DQCR"); return; }
860 if (cell->type == "$_DFF_PN0_") { check_gate("DQCR"); return; }
861 if (cell->type == "$_DFF_PN1_") { check_gate("DQCR"); return; }
862 if (cell->type == "$_DFF_PP0_") { check_gate("DQCR"); return; }
863 if (cell->type == "$_DFF_PP1_") { check_gate("DQCR"); return; }
864
865 if (cell->type == "$_DFFSR_NNN_") { check_gate("CSRDQ"); return; }
866 if (cell->type == "$_DFFSR_NNP_") { check_gate("CSRDQ"); return; }
867 if (cell->type == "$_DFFSR_NPN_") { check_gate("CSRDQ"); return; }
868 if (cell->type == "$_DFFSR_NPP_") { check_gate("CSRDQ"); return; }
869 if (cell->type == "$_DFFSR_PNN_") { check_gate("CSRDQ"); return; }
870 if (cell->type == "$_DFFSR_PNP_") { check_gate("CSRDQ"); return; }
871 if (cell->type == "$_DFFSR_PPN_") { check_gate("CSRDQ"); return; }
872 if (cell->type == "$_DFFSR_PPP_") { check_gate("CSRDQ"); return; }
873
874 if (cell->type == "$_DLATCH_N_") { check_gate("EDQ"); return; }
875 if (cell->type == "$_DLATCH_P_") { check_gate("EDQ"); return; }
876
877 if (cell->type == "$_DLATCHSR_NNN_") { check_gate("ESRDQ"); return; }
878 if (cell->type == "$_DLATCHSR_NNP_") { check_gate("ESRDQ"); return; }
879 if (cell->type == "$_DLATCHSR_NPN_") { check_gate("ESRDQ"); return; }
880 if (cell->type == "$_DLATCHSR_NPP_") { check_gate("ESRDQ"); return; }
881 if (cell->type == "$_DLATCHSR_PNN_") { check_gate("ESRDQ"); return; }
882 if (cell->type == "$_DLATCHSR_PNP_") { check_gate("ESRDQ"); return; }
883 if (cell->type == "$_DLATCHSR_PPN_") { check_gate("ESRDQ"); return; }
884 if (cell->type == "$_DLATCHSR_PPP_") { check_gate("ESRDQ"); return; }
885
886 error(__LINE__);
887 }
888 };
889 }
890 #endif
891
892 void RTLIL::Module::check()
893 {
894 #ifndef NDEBUG
895 std::vector<bool> ports_declared;
896 for (auto &it : wires_) {
897 log_assert(this == it.second->module);
898 log_assert(it.first == it.second->name);
899 log_assert(!it.first.empty());
900 log_assert(it.second->width >= 0);
901 log_assert(it.second->port_id >= 0);
902 for (auto &it2 : it.second->attributes)
903 log_assert(!it2.first.empty());
904 if (it.second->port_id) {
905 log_assert(SIZE(ports) >= it.second->port_id);
906 log_assert(ports.at(it.second->port_id-1) == it.first);
907 log_assert(it.second->port_input || it.second->port_output);
908 if (SIZE(ports_declared) < it.second->port_id)
909 ports_declared.resize(it.second->port_id);
910 log_assert(ports_declared[it.second->port_id-1] == false);
911 ports_declared[it.second->port_id-1] = true;
912 } else
913 log_assert(!it.second->port_input && !it.second->port_output);
914 }
915 for (auto port_declared : ports_declared)
916 log_assert(port_declared == true);
917 log_assert(SIZE(ports) == SIZE(ports_declared));
918
919 for (auto &it : memories) {
920 log_assert(it.first == it.second->name);
921 log_assert(!it.first.empty());
922 log_assert(it.second->width >= 0);
923 log_assert(it.second->size >= 0);
924 for (auto &it2 : it.second->attributes)
925 log_assert(!it2.first.empty());
926 }
927
928 for (auto &it : cells_) {
929 log_assert(this == it.second->module);
930 log_assert(it.first == it.second->name);
931 log_assert(!it.first.empty());
932 log_assert(!it.second->type.empty());
933 for (auto &it2 : it.second->connections()) {
934 log_assert(!it2.first.empty());
935 it2.second.check();
936 }
937 for (auto &it2 : it.second->attributes)
938 log_assert(!it2.first.empty());
939 for (auto &it2 : it.second->parameters)
940 log_assert(!it2.first.empty());
941 InternalCellChecker checker(this, it.second);
942 checker.check();
943 }
944
945 for (auto &it : processes) {
946 log_assert(it.first == it.second->name);
947 log_assert(!it.first.empty());
948 // FIXME: More checks here..
949 }
950
951 for (auto &it : connections_) {
952 log_assert(it.first.size() == it.second.size());
953 it.first.check();
954 it.second.check();
955 }
956
957 for (auto &it : attributes)
958 log_assert(!it.first.empty());
959 #endif
960 }
961
962 void RTLIL::Module::optimize()
963 {
964 }
965
966 void RTLIL::Module::cloneInto(RTLIL::Module *new_mod) const
967 {
968 log_assert(new_mod->refcount_wires_ == 0);
969 log_assert(new_mod->refcount_cells_ == 0);
970
971 new_mod->connections_ = connections_;
972 new_mod->attributes = attributes;
973
974 for (auto &it : wires_)
975 new_mod->addWire(it.first, it.second);
976
977 for (auto &it : memories)
978 new_mod->memories[it.first] = new RTLIL::Memory(*it.second);
979
980 for (auto &it : cells_)
981 new_mod->addCell(it.first, it.second);
982
983 for (auto &it : processes)
984 new_mod->processes[it.first] = it.second->clone();
985
986 struct RewriteSigSpecWorker
987 {
988 RTLIL::Module *mod;
989 void operator()(RTLIL::SigSpec &sig)
990 {
991 std::vector<RTLIL::SigChunk> chunks = sig.chunks();
992 for (auto &c : chunks)
993 if (c.wire != NULL)
994 c.wire = mod->wires_.at(c.wire->name);
995 sig = chunks;
996 }
997 };
998
999 RewriteSigSpecWorker rewriteSigSpecWorker;
1000 rewriteSigSpecWorker.mod = new_mod;
1001 new_mod->rewrite_sigspecs(rewriteSigSpecWorker);
1002 new_mod->fixup_ports();
1003 }
1004
1005 RTLIL::Module *RTLIL::Module::clone() const
1006 {
1007 RTLIL::Module *new_mod = new RTLIL::Module;
1008 new_mod->name = name;
1009 cloneInto(new_mod);
1010 return new_mod;
1011 }
1012
1013 bool RTLIL::Module::has_memories() const
1014 {
1015 return !memories.empty();
1016 }
1017
1018 bool RTLIL::Module::has_processes() const
1019 {
1020 return !processes.empty();
1021 }
1022
1023 bool RTLIL::Module::has_memories_warn() const
1024 {
1025 if (!memories.empty())
1026 log("Warning: Ignoring module %s because it contains memories (run 'memory' command first).\n", log_id(this));
1027 return !memories.empty();
1028 }
1029
1030 bool RTLIL::Module::has_processes_warn() const
1031 {
1032 if (!processes.empty())
1033 log("Warning: Ignoring module %s because it contains processes (run 'proc' command first).\n", log_id(this));
1034 return !processes.empty();
1035 }
1036
1037 std::vector<RTLIL::Wire*> RTLIL::Module::selected_wires() const
1038 {
1039 std::vector<RTLIL::Wire*> result;
1040 result.reserve(wires_.size());
1041 for (auto &it : wires_)
1042 if (design->selected(this, it.second))
1043 result.push_back(it.second);
1044 return result;
1045 }
1046
1047 std::vector<RTLIL::Cell*> RTLIL::Module::selected_cells() const
1048 {
1049 std::vector<RTLIL::Cell*> result;
1050 result.reserve(wires_.size());
1051 for (auto &it : cells_)
1052 if (design->selected(this, it.second))
1053 result.push_back(it.second);
1054 return result;
1055 }
1056
1057 void RTLIL::Module::add(RTLIL::Wire *wire)
1058 {
1059 log_assert(!wire->name.empty());
1060 log_assert(count_id(wire->name) == 0);
1061 log_assert(refcount_wires_ == 0);
1062 wires_[wire->name] = wire;
1063 wire->module = this;
1064 }
1065
1066 void RTLIL::Module::add(RTLIL::Cell *cell)
1067 {
1068 log_assert(!cell->name.empty());
1069 log_assert(count_id(cell->name) == 0);
1070 log_assert(refcount_cells_ == 0);
1071 cells_[cell->name] = cell;
1072 cell->module = this;
1073 }
1074
1075 namespace {
1076 struct DeleteWireWorker
1077 {
1078 RTLIL::Module *module;
1079 const std::set<RTLIL::Wire*> *wires_p;
1080
1081 void operator()(RTLIL::SigSpec &sig) {
1082 std::vector<RTLIL::SigChunk> chunks = sig;
1083 for (auto &c : chunks)
1084 if (c.wire != NULL && wires_p->count(c.wire)) {
1085 c.wire = module->addWire(NEW_ID, c.width);
1086 c.offset = 0;
1087 }
1088 sig = chunks;
1089 }
1090 };
1091 }
1092
1093 #if 0
1094 void RTLIL::Module::remove(RTLIL::Wire *wire)
1095 {
1096 std::setPort<RTLIL::Wire*> wires_;
1097 wires_.insert(wire);
1098 remove(wires_);
1099 }
1100 #endif
1101
1102 void RTLIL::Module::remove(const std::set<RTLIL::Wire*> &wires)
1103 {
1104 log_assert(refcount_wires_ == 0);
1105
1106 DeleteWireWorker delete_wire_worker;
1107 delete_wire_worker.module = this;
1108 delete_wire_worker.wires_p = &wires;
1109 rewrite_sigspecs(delete_wire_worker);
1110
1111 for (auto &it : wires) {
1112 log_assert(wires_.count(it->name) != 0);
1113 wires_.erase(it->name);
1114 delete it;
1115 }
1116 }
1117
1118 void RTLIL::Module::remove(RTLIL::Cell *cell)
1119 {
1120 log_assert(cells_.count(cell->name) != 0);
1121 log_assert(refcount_cells_ == 0);
1122 cells_.erase(cell->name);
1123 delete cell;
1124 }
1125
1126 void RTLIL::Module::rename(RTLIL::Wire *wire, RTLIL::IdString new_name)
1127 {
1128 log_assert(wires_[wire->name] == wire);
1129 log_assert(refcount_wires_ == 0);
1130 wires_.erase(wire->name);
1131 wire->name = new_name;
1132 add(wire);
1133 }
1134
1135 void RTLIL::Module::rename(RTLIL::Cell *cell, RTLIL::IdString new_name)
1136 {
1137 log_assert(cells_[cell->name] == cell);
1138 log_assert(refcount_wires_ == 0);
1139 cells_.erase(cell->name);
1140 cell->name = new_name;
1141 add(cell);
1142 }
1143
1144 void RTLIL::Module::rename(RTLIL::IdString old_name, RTLIL::IdString new_name)
1145 {
1146 log_assert(count_id(old_name) != 0);
1147 if (wires_.count(old_name))
1148 rename(wires_.at(old_name), new_name);
1149 else if (cells_.count(old_name))
1150 rename(cells_.at(old_name), new_name);
1151 else
1152 log_abort();
1153 }
1154
1155 void RTLIL::Module::swap_names(RTLIL::Wire *w1, RTLIL::Wire *w2)
1156 {
1157 log_assert(wires_[w1->name] == w1);
1158 log_assert(wires_[w2->name] == w2);
1159 log_assert(refcount_wires_ == 0);
1160
1161 wires_.erase(w1->name);
1162 wires_.erase(w2->name);
1163
1164 std::swap(w1->name, w2->name);
1165
1166 wires_[w1->name] = w1;
1167 wires_[w2->name] = w2;
1168 }
1169
1170 void RTLIL::Module::swap_names(RTLIL::Cell *c1, RTLIL::Cell *c2)
1171 {
1172 log_assert(cells_[c1->name] == c1);
1173 log_assert(cells_[c2->name] == c2);
1174 log_assert(refcount_cells_ == 0);
1175
1176 cells_.erase(c1->name);
1177 cells_.erase(c2->name);
1178
1179 std::swap(c1->name, c2->name);
1180
1181 cells_[c1->name] = c1;
1182 cells_[c2->name] = c2;
1183 }
1184
1185 RTLIL::IdString RTLIL::Module::uniquify(RTLIL::IdString name)
1186 {
1187 int index = 0;
1188 return uniquify(name, index);
1189 }
1190
1191 RTLIL::IdString RTLIL::Module::uniquify(RTLIL::IdString name, int &index)
1192 {
1193 if (index == 0) {
1194 if (count_id(name) == 0)
1195 return name;
1196 index++;
1197 }
1198
1199 while (1) {
1200 RTLIL::IdString new_name = stringf("%s_%d", name.c_str(), index);
1201 if (count_id(new_name) == 0)
1202 return new_name;
1203 index++;
1204 }
1205 }
1206
1207 static bool fixup_ports_compare(const RTLIL::Wire *a, const RTLIL::Wire *b)
1208 {
1209 if (a->port_id && !b->port_id)
1210 return true;
1211 if (!a->port_id && b->port_id)
1212 return false;
1213
1214 if (a->port_id == b->port_id)
1215 return a->name < b->name;
1216 return a->port_id < b->port_id;
1217 }
1218
1219 void RTLIL::Module::connect(const RTLIL::SigSig &conn)
1220 {
1221 for (auto mon : monitors)
1222 mon->notify_connect(this, conn);
1223
1224 if (design)
1225 for (auto mon : design->monitors)
1226 mon->notify_connect(this, conn);
1227
1228 connections_.push_back(conn);
1229 }
1230
1231 void RTLIL::Module::connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs)
1232 {
1233 connect(RTLIL::SigSig(lhs, rhs));
1234 }
1235
1236 void RTLIL::Module::new_connections(const std::vector<RTLIL::SigSig> &new_conn)
1237 {
1238 for (auto mon : monitors)
1239 mon->notify_connect(this, new_conn);
1240
1241 if (design)
1242 for (auto mon : design->monitors)
1243 mon->notify_connect(this, new_conn);
1244
1245 connections_ = new_conn;
1246 }
1247
1248 const std::vector<RTLIL::SigSig> &RTLIL::Module::connections() const
1249 {
1250 return connections_;
1251 }
1252
1253 void RTLIL::Module::fixup_ports()
1254 {
1255 std::vector<RTLIL::Wire*> all_ports;
1256
1257 for (auto &w : wires_)
1258 if (w.second->port_input || w.second->port_output)
1259 all_ports.push_back(w.second);
1260 else
1261 w.second->port_id = 0;
1262
1263 std::sort(all_ports.begin(), all_ports.end(), fixup_ports_compare);
1264
1265 ports.clear();
1266 for (size_t i = 0; i < all_ports.size(); i++) {
1267 ports.push_back(all_ports[i]->name);
1268 all_ports[i]->port_id = i+1;
1269 }
1270 }
1271
1272 RTLIL::Wire *RTLIL::Module::addWire(RTLIL::IdString name, int width)
1273 {
1274 RTLIL::Wire *wire = new RTLIL::Wire;
1275 wire->name = name;
1276 wire->width = width;
1277 add(wire);
1278 return wire;
1279 }
1280
1281 RTLIL::Wire *RTLIL::Module::addWire(RTLIL::IdString name, const RTLIL::Wire *other)
1282 {
1283 RTLIL::Wire *wire = addWire(name);
1284 wire->width = other->width;
1285 wire->start_offset = other->start_offset;
1286 wire->port_id = other->port_id;
1287 wire->port_input = other->port_input;
1288 wire->port_output = other->port_output;
1289 wire->upto = other->upto;
1290 wire->attributes = other->attributes;
1291 return wire;
1292 }
1293
1294 RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, RTLIL::IdString type)
1295 {
1296 RTLIL::Cell *cell = new RTLIL::Cell;
1297 cell->name = name;
1298 cell->type = type;
1299 add(cell);
1300 return cell;
1301 }
1302
1303 RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, const RTLIL::Cell *other)
1304 {
1305 RTLIL::Cell *cell = addCell(name, other->type);
1306 cell->connections_ = other->connections_;
1307 cell->parameters = other->parameters;
1308 cell->attributes = other->attributes;
1309 return cell;
1310 }
1311
1312 #define DEF_METHOD(_func, _y_size, _type) \
1313 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed) { \
1314 RTLIL::Cell *cell = addCell(name, _type); \
1315 cell->parameters["\\A_SIGNED"] = is_signed; \
1316 cell->parameters["\\A_WIDTH"] = sig_a.size(); \
1317 cell->parameters["\\Y_WIDTH"] = sig_y.size(); \
1318 cell->setPort("\\A", sig_a); \
1319 cell->setPort("\\Y", sig_y); \
1320 return cell; \
1321 } \
1322 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed) { \
1323 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
1324 add ## _func(name, sig_a, sig_y, is_signed); \
1325 return sig_y; \
1326 }
1327 DEF_METHOD(Not, sig_a.size(), "$not")
1328 DEF_METHOD(Pos, sig_a.size(), "$pos")
1329 DEF_METHOD(Neg, sig_a.size(), "$neg")
1330 DEF_METHOD(ReduceAnd, 1, "$reduce_and")
1331 DEF_METHOD(ReduceOr, 1, "$reduce_or")
1332 DEF_METHOD(ReduceXor, 1, "$reduce_xor")
1333 DEF_METHOD(ReduceXnor, 1, "$reduce_xnor")
1334 DEF_METHOD(ReduceBool, 1, "$reduce_bool")
1335 DEF_METHOD(LogicNot, 1, "$logic_not")
1336 #undef DEF_METHOD
1337
1338 #define DEF_METHOD(_func, _y_size, _type) \
1339 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed) { \
1340 RTLIL::Cell *cell = addCell(name, _type); \
1341 cell->parameters["\\A_SIGNED"] = is_signed; \
1342 cell->parameters["\\B_SIGNED"] = is_signed; \
1343 cell->parameters["\\A_WIDTH"] = sig_a.size(); \
1344 cell->parameters["\\B_WIDTH"] = sig_b.size(); \
1345 cell->parameters["\\Y_WIDTH"] = sig_y.size(); \
1346 cell->setPort("\\A", sig_a); \
1347 cell->setPort("\\B", sig_b); \
1348 cell->setPort("\\Y", sig_y); \
1349 return cell; \
1350 } \
1351 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed) { \
1352 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
1353 add ## _func(name, sig_a, sig_b, sig_y, is_signed); \
1354 return sig_y; \
1355 }
1356 DEF_METHOD(And, std::max(sig_a.size(), sig_b.size()), "$and")
1357 DEF_METHOD(Or, std::max(sig_a.size(), sig_b.size()), "$or")
1358 DEF_METHOD(Xor, std::max(sig_a.size(), sig_b.size()), "$xor")
1359 DEF_METHOD(Xnor, std::max(sig_a.size(), sig_b.size()), "$xnor")
1360 DEF_METHOD(Shl, sig_a.size(), "$shl")
1361 DEF_METHOD(Shr, sig_a.size(), "$shr")
1362 DEF_METHOD(Sshl, sig_a.size(), "$sshl")
1363 DEF_METHOD(Sshr, sig_a.size(), "$sshr")
1364 DEF_METHOD(Shift, sig_a.size(), "$shift")
1365 DEF_METHOD(Shiftx, sig_a.size(), "$shiftx")
1366 DEF_METHOD(Lt, 1, "$lt")
1367 DEF_METHOD(Le, 1, "$le")
1368 DEF_METHOD(Eq, 1, "$eq")
1369 DEF_METHOD(Ne, 1, "$ne")
1370 DEF_METHOD(Eqx, 1, "$eqx")
1371 DEF_METHOD(Nex, 1, "$nex")
1372 DEF_METHOD(Ge, 1, "$ge")
1373 DEF_METHOD(Gt, 1, "$gt")
1374 DEF_METHOD(Add, std::max(sig_a.size(), sig_b.size()), "$add")
1375 DEF_METHOD(Sub, std::max(sig_a.size(), sig_b.size()), "$sub")
1376 DEF_METHOD(Mul, std::max(sig_a.size(), sig_b.size()), "$mul")
1377 DEF_METHOD(Div, std::max(sig_a.size(), sig_b.size()), "$div")
1378 DEF_METHOD(Mod, std::max(sig_a.size(), sig_b.size()), "$mod")
1379 DEF_METHOD(LogicAnd, 1, "$logic_and")
1380 DEF_METHOD(LogicOr, 1, "$logic_or")
1381 #undef DEF_METHOD
1382
1383 #define DEF_METHOD(_func, _type, _pmux) \
1384 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, RTLIL::SigSpec sig_y) { \
1385 RTLIL::Cell *cell = addCell(name, _type); \
1386 cell->parameters["\\WIDTH"] = sig_a.size(); \
1387 if (_pmux) cell->parameters["\\S_WIDTH"] = sig_s.size(); \
1388 cell->setPort("\\A", sig_a); \
1389 cell->setPort("\\B", sig_b); \
1390 cell->setPort("\\S", sig_s); \
1391 cell->setPort("\\Y", sig_y); \
1392 return cell; \
1393 } \
1394 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s) { \
1395 RTLIL::SigSpec sig_y = addWire(NEW_ID, sig_a.size()); \
1396 add ## _func(name, sig_a, sig_b, sig_s, sig_y); \
1397 return sig_y; \
1398 }
1399 DEF_METHOD(Mux, "$mux", 0)
1400 DEF_METHOD(Pmux, "$pmux", 1)
1401 #undef DEF_METHOD
1402
1403 #define DEF_METHOD_2(_func, _type, _P1, _P2) \
1404 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2) { \
1405 RTLIL::Cell *cell = addCell(name, _type); \
1406 cell->setPort("\\" #_P1, sig1); \
1407 cell->setPort("\\" #_P2, sig2); \
1408 return cell; \
1409 } \
1410 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1) { \
1411 RTLIL::SigBit sig2 = addWire(NEW_ID); \
1412 add ## _func(name, sig1, sig2); \
1413 return sig2; \
1414 }
1415 #define DEF_METHOD_3(_func, _type, _P1, _P2, _P3) \
1416 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3) { \
1417 RTLIL::Cell *cell = addCell(name, _type); \
1418 cell->setPort("\\" #_P1, sig1); \
1419 cell->setPort("\\" #_P2, sig2); \
1420 cell->setPort("\\" #_P3, sig3); \
1421 return cell; \
1422 } \
1423 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2) { \
1424 RTLIL::SigBit sig3 = addWire(NEW_ID); \
1425 add ## _func(name, sig1, sig2, sig3); \
1426 return sig3; \
1427 }
1428 #define DEF_METHOD_4(_func, _type, _P1, _P2, _P3, _P4) \
1429 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, RTLIL::SigBit sig4) { \
1430 RTLIL::Cell *cell = addCell(name, _type); \
1431 cell->setPort("\\" #_P1, sig1); \
1432 cell->setPort("\\" #_P2, sig2); \
1433 cell->setPort("\\" #_P3, sig3); \
1434 cell->setPort("\\" #_P4, sig4); \
1435 return cell; \
1436 } \
1437 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3) { \
1438 RTLIL::SigBit sig4 = addWire(NEW_ID); \
1439 add ## _func(name, sig1, sig2, sig3, sig4); \
1440 return sig4; \
1441 }
1442 #define DEF_METHOD_5(_func, _type, _P1, _P2, _P3, _P4, _P5) \
1443 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, RTLIL::SigBit sig4, RTLIL::SigBit sig5) { \
1444 RTLIL::Cell *cell = addCell(name, _type); \
1445 cell->setPort("\\" #_P1, sig1); \
1446 cell->setPort("\\" #_P2, sig2); \
1447 cell->setPort("\\" #_P3, sig3); \
1448 cell->setPort("\\" #_P4, sig4); \
1449 cell->setPort("\\" #_P5, sig5); \
1450 return cell; \
1451 } \
1452 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, RTLIL::SigBit sig4) { \
1453 RTLIL::SigBit sig5 = addWire(NEW_ID); \
1454 add ## _func(name, sig1, sig2, sig3, sig4, sig5); \
1455 return sig5; \
1456 }
1457 DEF_METHOD_2(NotGate, "$_NOT_", A, Y)
1458 DEF_METHOD_3(AndGate, "$_AND_", A, B, Y)
1459 DEF_METHOD_3(NandGate, "$_NAND_", A, B, Y)
1460 DEF_METHOD_3(OrGate, "$_OR_", A, B, Y)
1461 DEF_METHOD_3(NorGate, "$_NOR_", A, B, Y)
1462 DEF_METHOD_3(XorGate, "$_XOR_", A, B, Y)
1463 DEF_METHOD_3(XnorGate, "$_XNOR_", A, B, Y)
1464 DEF_METHOD_4(MuxGate, "$_MUX_", A, B, S, Y)
1465 DEF_METHOD_4(Aoi3Gate, "$_AOI3_", A, B, C, Y)
1466 DEF_METHOD_4(Oai3Gate, "$_OAI3_", A, B, C, Y)
1467 DEF_METHOD_5(Aoi4Gate, "$_AOI4_", A, B, C, D, Y)
1468 DEF_METHOD_5(Oai4Gate, "$_OAI4_", A, B, C, D, Y)
1469 #undef DEF_METHOD_2
1470 #undef DEF_METHOD_3
1471 #undef DEF_METHOD_4
1472 #undef DEF_METHOD_5
1473
1474 RTLIL::Cell* RTLIL::Module::addPow(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool a_signed, bool b_signed)
1475 {
1476 RTLIL::Cell *cell = addCell(name, "$pow");
1477 cell->parameters["\\A_SIGNED"] = a_signed;
1478 cell->parameters["\\B_SIGNED"] = b_signed;
1479 cell->parameters["\\A_WIDTH"] = sig_a.size();
1480 cell->parameters["\\B_WIDTH"] = sig_b.size();
1481 cell->parameters["\\Y_WIDTH"] = sig_y.size();
1482 cell->setPort("\\A", sig_a);
1483 cell->setPort("\\B", sig_b);
1484 cell->setPort("\\Y", sig_y);
1485 return cell;
1486 }
1487
1488 RTLIL::Cell* RTLIL::Module::addSlice(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, RTLIL::Const offset)
1489 {
1490 RTLIL::Cell *cell = addCell(name, "$slice");
1491 cell->parameters["\\A_WIDTH"] = sig_a.size();
1492 cell->parameters["\\Y_WIDTH"] = sig_y.size();
1493 cell->parameters["\\OFFSET"] = offset;
1494 cell->setPort("\\A", sig_a);
1495 cell->setPort("\\Y", sig_y);
1496 return cell;
1497 }
1498
1499 RTLIL::Cell* RTLIL::Module::addConcat(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y)
1500 {
1501 RTLIL::Cell *cell = addCell(name, "$concat");
1502 cell->parameters["\\A_WIDTH"] = sig_a.size();
1503 cell->parameters["\\B_WIDTH"] = sig_b.size();
1504 cell->setPort("\\A", sig_a);
1505 cell->setPort("\\B", sig_b);
1506 cell->setPort("\\Y", sig_y);
1507 return cell;
1508 }
1509
1510 RTLIL::Cell* RTLIL::Module::addLut(RTLIL::IdString name, RTLIL::SigSpec sig_i, RTLIL::SigSpec sig_o, RTLIL::Const lut)
1511 {
1512 RTLIL::Cell *cell = addCell(name, "$lut");
1513 cell->parameters["\\LUT"] = lut;
1514 cell->parameters["\\WIDTH"] = sig_i.size();
1515 cell->setPort("\\A", sig_i);
1516 cell->setPort("\\Y", sig_o);
1517 return cell;
1518 }
1519
1520 RTLIL::Cell* RTLIL::Module::addAssert(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en)
1521 {
1522 RTLIL::Cell *cell = addCell(name, "$assert");
1523 cell->setPort("\\A", sig_a);
1524 cell->setPort("\\EN", sig_en);
1525 return cell;
1526 }
1527
1528 RTLIL::Cell* RTLIL::Module::addSr(RTLIL::IdString name, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr, RTLIL::SigSpec sig_q, bool set_polarity, bool clr_polarity)
1529 {
1530 RTLIL::Cell *cell = addCell(name, "$sr");
1531 cell->parameters["\\SET_POLARITY"] = set_polarity;
1532 cell->parameters["\\CLR_POLARITY"] = clr_polarity;
1533 cell->parameters["\\WIDTH"] = sig_q.size();
1534 cell->setPort("\\SET", sig_set);
1535 cell->setPort("\\CLR", sig_clr);
1536 cell->setPort("\\Q", sig_q);
1537 return cell;
1538 }
1539
1540 RTLIL::Cell* RTLIL::Module::addDff(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity)
1541 {
1542 RTLIL::Cell *cell = addCell(name, "$dff");
1543 cell->parameters["\\CLK_POLARITY"] = clk_polarity;
1544 cell->parameters["\\WIDTH"] = sig_q.size();
1545 cell->setPort("\\CLK", sig_clk);
1546 cell->setPort("\\D", sig_d);
1547 cell->setPort("\\Q", sig_q);
1548 return cell;
1549 }
1550
1551 RTLIL::Cell* RTLIL::Module::addDffsr(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
1552 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity)
1553 {
1554 RTLIL::Cell *cell = addCell(name, "$dffsr");
1555 cell->parameters["\\CLK_POLARITY"] = clk_polarity;
1556 cell->parameters["\\SET_POLARITY"] = set_polarity;
1557 cell->parameters["\\CLR_POLARITY"] = clr_polarity;
1558 cell->parameters["\\WIDTH"] = sig_q.size();
1559 cell->setPort("\\CLK", sig_clk);
1560 cell->setPort("\\SET", sig_set);
1561 cell->setPort("\\CLR", sig_clr);
1562 cell->setPort("\\D", sig_d);
1563 cell->setPort("\\Q", sig_q);
1564 return cell;
1565 }
1566
1567 RTLIL::Cell* RTLIL::Module::addAdff(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_arst, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q,
1568 RTLIL::Const arst_value, bool clk_polarity, bool arst_polarity)
1569 {
1570 RTLIL::Cell *cell = addCell(name, "$adff");
1571 cell->parameters["\\CLK_POLARITY"] = clk_polarity;
1572 cell->parameters["\\ARST_POLARITY"] = arst_polarity;
1573 cell->parameters["\\ARST_VALUE"] = arst_value;
1574 cell->parameters["\\WIDTH"] = sig_q.size();
1575 cell->setPort("\\CLK", sig_clk);
1576 cell->setPort("\\ARST", sig_arst);
1577 cell->setPort("\\D", sig_d);
1578 cell->setPort("\\Q", sig_q);
1579 return cell;
1580 }
1581
1582 RTLIL::Cell* RTLIL::Module::addDlatch(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity)
1583 {
1584 RTLIL::Cell *cell = addCell(name, "$dlatch");
1585 cell->parameters["\\EN_POLARITY"] = en_polarity;
1586 cell->parameters["\\WIDTH"] = sig_q.size();
1587 cell->setPort("\\EN", sig_en);
1588 cell->setPort("\\D", sig_d);
1589 cell->setPort("\\Q", sig_q);
1590 return cell;
1591 }
1592
1593 RTLIL::Cell* RTLIL::Module::addDlatchsr(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
1594 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity, bool set_polarity, bool clr_polarity)
1595 {
1596 RTLIL::Cell *cell = addCell(name, "$dlatchsr");
1597 cell->parameters["\\EN_POLARITY"] = en_polarity;
1598 cell->parameters["\\SET_POLARITY"] = set_polarity;
1599 cell->parameters["\\CLR_POLARITY"] = clr_polarity;
1600 cell->parameters["\\WIDTH"] = sig_q.size();
1601 cell->setPort("\\EN", sig_en);
1602 cell->setPort("\\SET", sig_set);
1603 cell->setPort("\\CLR", sig_clr);
1604 cell->setPort("\\D", sig_d);
1605 cell->setPort("\\Q", sig_q);
1606 return cell;
1607 }
1608
1609 RTLIL::Cell* RTLIL::Module::addDffGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity)
1610 {
1611 RTLIL::Cell *cell = addCell(name, stringf("$_DFF_%c_", clk_polarity ? 'P' : 'N'));
1612 cell->setPort("\\C", sig_clk);
1613 cell->setPort("\\D", sig_d);
1614 cell->setPort("\\Q", sig_q);
1615 return cell;
1616 }
1617
1618 RTLIL::Cell* RTLIL::Module::addDffsrGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
1619 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity)
1620 {
1621 RTLIL::Cell *cell = addCell(name, stringf("$_DFFSR_%c%c%c_", clk_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N'));
1622 cell->setPort("\\C", sig_clk);
1623 cell->setPort("\\S", sig_set);
1624 cell->setPort("\\R", sig_clr);
1625 cell->setPort("\\D", sig_d);
1626 cell->setPort("\\Q", sig_q);
1627 return cell;
1628 }
1629
1630 RTLIL::Cell* RTLIL::Module::addAdffGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_arst, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q,
1631 bool arst_value, bool clk_polarity, bool arst_polarity)
1632 {
1633 RTLIL::Cell *cell = addCell(name, stringf("$_DFF_%c%c%c_", clk_polarity ? 'P' : 'N', arst_polarity ? 'P' : 'N', arst_value ? '1' : '0'));
1634 cell->setPort("\\C", sig_clk);
1635 cell->setPort("\\R", sig_arst);
1636 cell->setPort("\\D", sig_d);
1637 cell->setPort("\\Q", sig_q);
1638 return cell;
1639 }
1640
1641 RTLIL::Cell* RTLIL::Module::addDlatchGate(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity)
1642 {
1643 RTLIL::Cell *cell = addCell(name, stringf("$_DLATCH_%c_", en_polarity ? 'P' : 'N'));
1644 cell->setPort("\\E", sig_en);
1645 cell->setPort("\\D", sig_d);
1646 cell->setPort("\\Q", sig_q);
1647 return cell;
1648 }
1649
1650 RTLIL::Cell* RTLIL::Module::addDlatchsrGate(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
1651 RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity, bool set_polarity, bool clr_polarity)
1652 {
1653 RTLIL::Cell *cell = addCell(name, stringf("$_DLATCHSR_%c%c%c_", en_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N'));
1654 cell->setPort("\\E", sig_en);
1655 cell->setPort("\\S", sig_set);
1656 cell->setPort("\\R", sig_clr);
1657 cell->setPort("\\D", sig_d);
1658 cell->setPort("\\Q", sig_q);
1659 return cell;
1660 }
1661
1662
1663 RTLIL::Wire::Wire()
1664 {
1665 module = nullptr;
1666 width = 1;
1667 start_offset = 0;
1668 port_id = 0;
1669 port_input = false;
1670 port_output = false;
1671 upto = false;
1672 }
1673
1674 RTLIL::Memory::Memory()
1675 {
1676 width = 1;
1677 size = 0;
1678 }
1679
1680 RTLIL::Cell::Cell() : module(nullptr)
1681 {
1682 }
1683
1684 bool RTLIL::Cell::hasPort(RTLIL::IdString portname) const
1685 {
1686 return connections_.count(portname) != 0;
1687 }
1688
1689 void RTLIL::Cell::unsetPort(RTLIL::IdString portname)
1690 {
1691 RTLIL::SigSpec signal;
1692 auto conn_it = connections_.find(portname);
1693
1694 if (conn_it != connections_.end())
1695 {
1696 for (auto mon : module->monitors)
1697 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
1698
1699 if (module->design)
1700 for (auto mon : module->design->monitors)
1701 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
1702
1703 connections_.erase(conn_it);
1704 }
1705 }
1706
1707 void RTLIL::Cell::setPort(RTLIL::IdString portname, RTLIL::SigSpec signal)
1708 {
1709 auto conn_it = connections_.find(portname);
1710
1711 if (conn_it == connections_.end()) {
1712 connections_[portname] = RTLIL::SigSpec();
1713 conn_it = connections_.find(portname);
1714 log_assert(conn_it != connections_.end());
1715 }
1716
1717 for (auto mon : module->monitors)
1718 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
1719
1720 if (module->design)
1721 for (auto mon : module->design->monitors)
1722 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
1723
1724 conn_it->second = signal;
1725 }
1726
1727 const RTLIL::SigSpec &RTLIL::Cell::getPort(RTLIL::IdString portname) const
1728 {
1729 return connections_.at(portname);
1730 }
1731
1732 const std::map<RTLIL::IdString, RTLIL::SigSpec> &RTLIL::Cell::connections() const
1733 {
1734 return connections_;
1735 }
1736
1737 bool RTLIL::Cell::hasParam(RTLIL::IdString paramname) const
1738 {
1739 return parameters.count(paramname);
1740 }
1741
1742 void RTLIL::Cell::unsetParam(RTLIL::IdString paramname)
1743 {
1744 parameters.erase(paramname);
1745 }
1746
1747 void RTLIL::Cell::setParam(RTLIL::IdString paramname, RTLIL::Const value)
1748 {
1749 parameters[paramname] = value;
1750 }
1751
1752 const RTLIL::Const &RTLIL::Cell::getParam(RTLIL::IdString paramname) const
1753 {
1754 return parameters.at(paramname);
1755 }
1756
1757 void RTLIL::Cell::check()
1758 {
1759 #ifndef NDEBUG
1760 InternalCellChecker checker(NULL, this);
1761 checker.check();
1762 #endif
1763 }
1764
1765 void RTLIL::Cell::fixup_parameters(bool set_a_signed, bool set_b_signed)
1766 {
1767 if (type.substr(0, 1) != "$" || type.substr(0, 2) == "$_" || type.substr(0, 8) == "$paramod" ||
1768 type.substr(0, 9) == "$verific$" || type.substr(0, 7) == "$array:" || type.substr(0, 8) == "$extern:")
1769 return;
1770
1771 if (type == "$mux" || type == "$pmux") {
1772 parameters["\\WIDTH"] = SIZE(connections_["\\Y"]);
1773 if (type == "$pmux")
1774 parameters["\\S_WIDTH"] = SIZE(connections_["\\S"]);
1775 check();
1776 return;
1777 }
1778
1779 if (type == "$lut") {
1780 parameters["\\WIDTH"] = SIZE(connections_["\\A"]);
1781 return;
1782 }
1783
1784 bool signedness_ab = !type.in("$slice", "$concat");
1785
1786 if (connections_.count("\\A")) {
1787 if (signedness_ab) {
1788 if (set_a_signed)
1789 parameters["\\A_SIGNED"] = true;
1790 else if (parameters.count("\\A_SIGNED") == 0)
1791 parameters["\\A_SIGNED"] = false;
1792 }
1793 parameters["\\A_WIDTH"] = SIZE(connections_["\\A"]);
1794 }
1795
1796 if (connections_.count("\\B")) {
1797 if (signedness_ab) {
1798 if (set_b_signed)
1799 parameters["\\B_SIGNED"] = true;
1800 else if (parameters.count("\\B_SIGNED") == 0)
1801 parameters["\\B_SIGNED"] = false;
1802 }
1803 parameters["\\B_WIDTH"] = SIZE(connections_["\\B"]);
1804 }
1805
1806 if (connections_.count("\\Y"))
1807 parameters["\\Y_WIDTH"] = SIZE(connections_["\\Y"]);
1808
1809 check();
1810 }
1811
1812 RTLIL::SigChunk::SigChunk()
1813 {
1814 wire = NULL;
1815 width = 0;
1816 offset = 0;
1817 }
1818
1819 RTLIL::SigChunk::SigChunk(const RTLIL::Const &value)
1820 {
1821 wire = NULL;
1822 data = value.bits;
1823 width = SIZE(data);
1824 offset = 0;
1825 }
1826
1827 RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire)
1828 {
1829 log_assert(wire != nullptr);
1830 this->wire = wire;
1831 this->width = wire->width;
1832 this->offset = 0;
1833 }
1834
1835 RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire, int offset, int width)
1836 {
1837 log_assert(wire != nullptr);
1838 this->wire = wire;
1839 this->width = width;
1840 this->offset = offset;
1841 }
1842
1843 RTLIL::SigChunk::SigChunk(const std::string &str)
1844 {
1845 wire = NULL;
1846 data = RTLIL::Const(str).bits;
1847 width = SIZE(data);
1848 offset = 0;
1849 }
1850
1851 RTLIL::SigChunk::SigChunk(int val, int width)
1852 {
1853 wire = NULL;
1854 data = RTLIL::Const(val, width).bits;
1855 this->width = SIZE(data);
1856 offset = 0;
1857 }
1858
1859 RTLIL::SigChunk::SigChunk(RTLIL::State bit, int width)
1860 {
1861 wire = NULL;
1862 data = RTLIL::Const(bit, width).bits;
1863 this->width = SIZE(data);
1864 offset = 0;
1865 }
1866
1867 RTLIL::SigChunk::SigChunk(RTLIL::SigBit bit)
1868 {
1869 wire = bit.wire;
1870 offset = 0;
1871 if (wire == NULL)
1872 data = RTLIL::Const(bit.data).bits;
1873 else
1874 offset = bit.offset;
1875 width = 1;
1876 }
1877
1878 RTLIL::SigChunk RTLIL::SigChunk::extract(int offset, int length) const
1879 {
1880 RTLIL::SigChunk ret;
1881 if (wire) {
1882 ret.wire = wire;
1883 ret.offset = this->offset + offset;
1884 ret.width = length;
1885 } else {
1886 for (int i = 0; i < length; i++)
1887 ret.data.push_back(data[offset+i]);
1888 ret.width = length;
1889 }
1890 return ret;
1891 }
1892
1893 bool RTLIL::SigChunk::operator <(const RTLIL::SigChunk &other) const
1894 {
1895 if (wire && other.wire)
1896 if (wire->name != other.wire->name)
1897 return wire->name < other.wire->name;
1898
1899 if (wire != other.wire)
1900 return wire < other.wire;
1901
1902 if (offset != other.offset)
1903 return offset < other.offset;
1904
1905 if (width != other.width)
1906 return width < other.width;
1907
1908 return data < other.data;
1909 }
1910
1911 bool RTLIL::SigChunk::operator ==(const RTLIL::SigChunk &other) const
1912 {
1913 return wire == other.wire && width == other.width && offset == other.offset && data == other.data;
1914 }
1915
1916 bool RTLIL::SigChunk::operator !=(const RTLIL::SigChunk &other) const
1917 {
1918 if (*this == other)
1919 return false;
1920 return true;
1921 }
1922
1923 RTLIL::SigSpec::SigSpec()
1924 {
1925 width_ = 0;
1926 hash_ = 0;
1927 }
1928
1929 RTLIL::SigSpec::SigSpec(const RTLIL::SigSpec &other)
1930 {
1931 *this = other;
1932 }
1933
1934 RTLIL::SigSpec::SigSpec(std::initializer_list<RTLIL::SigSpec> parts)
1935 {
1936 cover("kernel.rtlil.sigspec.init.list");
1937
1938 width_ = 0;
1939 hash_ = 0;
1940
1941 std::vector<RTLIL::SigSpec> parts_vec(parts.begin(), parts.end());
1942 for (auto it = parts_vec.rbegin(); it != parts_vec.rend(); it++)
1943 append(*it);
1944 }
1945
1946 const RTLIL::SigSpec &RTLIL::SigSpec::operator=(const RTLIL::SigSpec &other)
1947 {
1948 cover("kernel.rtlil.sigspec.assign");
1949
1950 width_ = other.width_;
1951 hash_ = other.hash_;
1952 chunks_ = other.chunks_;
1953 bits_.clear();
1954
1955 if (!other.bits_.empty())
1956 {
1957 RTLIL::SigChunk *last = NULL;
1958 int last_end_offset = 0;
1959
1960 for (auto &bit : other.bits_) {
1961 if (last && bit.wire == last->wire) {
1962 if (bit.wire == NULL) {
1963 last->data.push_back(bit.data);
1964 last->width++;
1965 continue;
1966 } else if (last_end_offset == bit.offset) {
1967 last_end_offset++;
1968 last->width++;
1969 continue;
1970 }
1971 }
1972 chunks_.push_back(bit);
1973 last = &chunks_.back();
1974 last_end_offset = bit.offset + 1;
1975 }
1976
1977 check();
1978 }
1979
1980 return *this;
1981 }
1982
1983 RTLIL::SigSpec::SigSpec(const RTLIL::Const &value)
1984 {
1985 cover("kernel.rtlil.sigspec.init.const");
1986
1987 chunks_.push_back(RTLIL::SigChunk(value));
1988 width_ = chunks_.back().width;
1989 hash_ = 0;
1990 check();
1991 }
1992
1993 RTLIL::SigSpec::SigSpec(const RTLIL::SigChunk &chunk)
1994 {
1995 cover("kernel.rtlil.sigspec.init.chunk");
1996
1997 chunks_.push_back(chunk);
1998 width_ = chunks_.back().width;
1999 hash_ = 0;
2000 check();
2001 }
2002
2003 RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire)
2004 {
2005 cover("kernel.rtlil.sigspec.init.wire");
2006
2007 chunks_.push_back(RTLIL::SigChunk(wire));
2008 width_ = chunks_.back().width;
2009 hash_ = 0;
2010 check();
2011 }
2012
2013 RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire, int offset, int width)
2014 {
2015 cover("kernel.rtlil.sigspec.init.wire_part");
2016
2017 chunks_.push_back(RTLIL::SigChunk(wire, offset, width));
2018 width_ = chunks_.back().width;
2019 hash_ = 0;
2020 check();
2021 }
2022
2023 RTLIL::SigSpec::SigSpec(const std::string &str)
2024 {
2025 cover("kernel.rtlil.sigspec.init.str");
2026
2027 chunks_.push_back(RTLIL::SigChunk(str));
2028 width_ = chunks_.back().width;
2029 hash_ = 0;
2030 check();
2031 }
2032
2033 RTLIL::SigSpec::SigSpec(int val, int width)
2034 {
2035 cover("kernel.rtlil.sigspec.init.int");
2036
2037 chunks_.push_back(RTLIL::SigChunk(val, width));
2038 width_ = width;
2039 hash_ = 0;
2040 check();
2041 }
2042
2043 RTLIL::SigSpec::SigSpec(RTLIL::State bit, int width)
2044 {
2045 cover("kernel.rtlil.sigspec.init.state");
2046
2047 chunks_.push_back(RTLIL::SigChunk(bit, width));
2048 width_ = width;
2049 hash_ = 0;
2050 check();
2051 }
2052
2053 RTLIL::SigSpec::SigSpec(RTLIL::SigBit bit, int width)
2054 {
2055 cover("kernel.rtlil.sigspec.init.bit");
2056
2057 if (bit.wire == NULL)
2058 chunks_.push_back(RTLIL::SigChunk(bit.data, width));
2059 else
2060 for (int i = 0; i < width; i++)
2061 chunks_.push_back(bit);
2062 width_ = width;
2063 hash_ = 0;
2064 check();
2065 }
2066
2067 RTLIL::SigSpec::SigSpec(std::vector<RTLIL::SigChunk> chunks)
2068 {
2069 cover("kernel.rtlil.sigspec.init.stdvec_chunks");
2070
2071 width_ = 0;
2072 hash_ = 0;
2073 for (auto &c : chunks)
2074 append(c);
2075 check();
2076 }
2077
2078 RTLIL::SigSpec::SigSpec(std::vector<RTLIL::SigBit> bits)
2079 {
2080 cover("kernel.rtlil.sigspec.init.stdvec_bits");
2081
2082 width_ = 0;
2083 hash_ = 0;
2084 for (auto &bit : bits)
2085 append_bit(bit);
2086 check();
2087 }
2088
2089 RTLIL::SigSpec::SigSpec(std::set<RTLIL::SigBit> bits)
2090 {
2091 cover("kernel.rtlil.sigspec.init.stdset_bits");
2092
2093 width_ = 0;
2094 hash_ = 0;
2095 for (auto &bit : bits)
2096 append_bit(bit);
2097 check();
2098 }
2099
2100 void RTLIL::SigSpec::pack() const
2101 {
2102 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
2103
2104 if (that->bits_.empty())
2105 return;
2106
2107 cover("kernel.rtlil.sigspec.convert.pack");
2108 log_assert(that->chunks_.empty());
2109
2110 std::vector<RTLIL::SigBit> old_bits;
2111 old_bits.swap(that->bits_);
2112
2113 RTLIL::SigChunk *last = NULL;
2114 int last_end_offset = 0;
2115
2116 for (auto &bit : old_bits) {
2117 if (last && bit.wire == last->wire) {
2118 if (bit.wire == NULL) {
2119 last->data.push_back(bit.data);
2120 last->width++;
2121 continue;
2122 } else if (last_end_offset == bit.offset) {
2123 last_end_offset++;
2124 last->width++;
2125 continue;
2126 }
2127 }
2128 that->chunks_.push_back(bit);
2129 last = &that->chunks_.back();
2130 last_end_offset = bit.offset + 1;
2131 }
2132
2133 check();
2134 }
2135
2136 void RTLIL::SigSpec::unpack() const
2137 {
2138 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
2139
2140 if (that->chunks_.empty())
2141 return;
2142
2143 cover("kernel.rtlil.sigspec.convert.unpack");
2144 log_assert(that->bits_.empty());
2145
2146 that->bits_.reserve(that->width_);
2147 for (auto &c : that->chunks_)
2148 for (int i = 0; i < c.width; i++)
2149 that->bits_.push_back(RTLIL::SigBit(c, i));
2150
2151 that->chunks_.clear();
2152 that->hash_ = 0;
2153 }
2154
2155 #define DJB2(_hash, _value) do { (_hash) = (((_hash) << 5) + (_hash)) + (_value); } while (0)
2156
2157 void RTLIL::SigSpec::hash() const
2158 {
2159 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
2160
2161 if (that->hash_ != 0)
2162 return;
2163
2164 cover("kernel.rtlil.sigspec.hash");
2165 that->pack();
2166
2167 that->hash_ = 5381;
2168 for (auto &c : that->chunks_)
2169 if (c.wire == NULL) {
2170 for (auto &v : c.data)
2171 DJB2(that->hash_, v);
2172 } else {
2173 DJB2(that->hash_, c.wire->name.index_);
2174 DJB2(that->hash_, c.offset);
2175 DJB2(that->hash_, c.width);
2176 }
2177
2178 if (that->hash_ == 0)
2179 that->hash_ = 1;
2180 }
2181
2182 void RTLIL::SigSpec::sort()
2183 {
2184 unpack();
2185 cover("kernel.rtlil.sigspec.sort");
2186 std::sort(bits_.begin(), bits_.end());
2187 }
2188
2189 void RTLIL::SigSpec::sort_and_unify()
2190 {
2191 cover("kernel.rtlil.sigspec.sort_and_unify");
2192 *this = this->to_sigbit_set();
2193 }
2194
2195 void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with)
2196 {
2197 replace(pattern, with, this);
2198 }
2199
2200 void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with, RTLIL::SigSpec *other) const
2201 {
2202 log_assert(pattern.width_ == with.width_);
2203
2204 pattern.unpack();
2205 with.unpack();
2206
2207 std::map<RTLIL::SigBit, RTLIL::SigBit> rules;
2208
2209 for (int i = 0; i < SIZE(pattern.bits_); i++)
2210 if (pattern.bits_[i].wire != NULL)
2211 rules[pattern.bits_[i]] = with.bits_[i];
2212
2213 replace(rules, other);
2214 }
2215
2216 void RTLIL::SigSpec::replace(const std::map<RTLIL::SigBit, RTLIL::SigBit> &rules)
2217 {
2218 replace(rules, this);
2219 }
2220
2221 void RTLIL::SigSpec::replace(const std::map<RTLIL::SigBit, RTLIL::SigBit> &rules, RTLIL::SigSpec *other) const
2222 {
2223 cover("kernel.rtlil.sigspec.replace");
2224
2225 log_assert(other != NULL);
2226 log_assert(width_ == other->width_);
2227
2228 unpack();
2229 other->unpack();
2230
2231 for (int i = 0; i < SIZE(bits_); i++) {
2232 auto it = rules.find(bits_[i]);
2233 if (it != rules.end())
2234 other->bits_[i] = it->second;
2235 }
2236
2237 other->check();
2238 }
2239
2240 void RTLIL::SigSpec::remove(const RTLIL::SigSpec &pattern)
2241 {
2242 remove2(pattern, NULL);
2243 }
2244
2245 void RTLIL::SigSpec::remove(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other) const
2246 {
2247 RTLIL::SigSpec tmp = *this;
2248 tmp.remove2(pattern, other);
2249 }
2250
2251 void RTLIL::SigSpec::remove2(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other)
2252 {
2253 std::set<RTLIL::SigBit> pattern_bits = pattern.to_sigbit_set();
2254 remove2(pattern_bits, other);
2255 }
2256
2257 void RTLIL::SigSpec::remove(const std::set<RTLIL::SigBit> &pattern)
2258 {
2259 remove2(pattern, NULL);
2260 }
2261
2262 void RTLIL::SigSpec::remove(const std::set<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other) const
2263 {
2264 RTLIL::SigSpec tmp = *this;
2265 tmp.remove2(pattern, other);
2266 }
2267
2268 void RTLIL::SigSpec::remove2(const std::set<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other)
2269 {
2270 if (other)
2271 cover("kernel.rtlil.sigspec.remove_other");
2272 else
2273 cover("kernel.rtlil.sigspec.remove");
2274
2275 unpack();
2276
2277 if (other != NULL) {
2278 log_assert(width_ == other->width_);
2279 other->unpack();
2280 }
2281
2282 std::vector<RTLIL::SigBit> new_bits, new_other_bits;
2283
2284 new_bits.resize(SIZE(bits_));
2285 if (other != NULL)
2286 new_other_bits.resize(SIZE(bits_));
2287
2288 int k = 0;
2289 for (int i = 0; i < SIZE(bits_); i++) {
2290 if (bits_[i].wire != NULL && pattern.count(bits_[i]))
2291 continue;
2292 if (other != NULL)
2293 new_other_bits[k] = other->bits_[i];
2294 new_bits[k++] = bits_[i];
2295 }
2296
2297 new_bits.resize(k);
2298 if (other != NULL)
2299 new_other_bits.resize(k);
2300
2301 bits_.swap(new_bits);
2302 width_ = SIZE(bits_);
2303
2304 if (other != NULL) {
2305 other->bits_.swap(new_other_bits);
2306 other->width_ = SIZE(other->bits_);
2307 }
2308
2309 check();
2310 }
2311
2312 RTLIL::SigSpec RTLIL::SigSpec::extract(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec *other) const
2313 {
2314 std::set<RTLIL::SigBit> pattern_bits = pattern.to_sigbit_set();
2315 return extract(pattern_bits, other);
2316 }
2317
2318 RTLIL::SigSpec RTLIL::SigSpec::extract(const std::set<RTLIL::SigBit> &pattern, const RTLIL::SigSpec *other) const
2319 {
2320 if (other)
2321 cover("kernel.rtlil.sigspec.extract_other");
2322 else
2323 cover("kernel.rtlil.sigspec.extract");
2324
2325 log_assert(other == NULL || width_ == other->width_);
2326
2327 std::vector<RTLIL::SigBit> bits_match = to_sigbit_vector();
2328 RTLIL::SigSpec ret;
2329
2330 if (other) {
2331 std::vector<RTLIL::SigBit> bits_other = other->to_sigbit_vector();
2332 for (int i = 0; i < width_; i++)
2333 if (bits_match[i].wire && pattern.count(bits_match[i]))
2334 ret.append_bit(bits_other[i]);
2335 } else {
2336 for (int i = 0; i < width_; i++)
2337 if (bits_match[i].wire && pattern.count(bits_match[i]))
2338 ret.append_bit(bits_match[i]);
2339 }
2340
2341 ret.check();
2342 return ret;
2343 }
2344
2345 void RTLIL::SigSpec::replace(int offset, const RTLIL::SigSpec &with)
2346 {
2347 cover("kernel.rtlil.sigspec.replace_pos");
2348
2349 unpack();
2350 with.unpack();
2351
2352 log_assert(offset >= 0);
2353 log_assert(with.width_ >= 0);
2354 log_assert(offset+with.width_ <= width_);
2355
2356 for (int i = 0; i < with.width_; i++)
2357 bits_.at(offset + i) = with.bits_.at(i);
2358
2359 check();
2360 }
2361
2362 void RTLIL::SigSpec::remove_const()
2363 {
2364 if (packed())
2365 {
2366 cover("kernel.rtlil.sigspec.remove_const.packed");
2367
2368 std::vector<RTLIL::SigChunk> new_chunks;
2369 new_chunks.reserve(SIZE(chunks_));
2370
2371 width_ = 0;
2372 for (auto &chunk : chunks_)
2373 if (chunk.wire != NULL) {
2374 new_chunks.push_back(chunk);
2375 width_ += chunk.width;
2376 }
2377
2378 chunks_.swap(new_chunks);
2379 }
2380 else
2381 {
2382 cover("kernel.rtlil.sigspec.remove_const.unpacked");
2383
2384 std::vector<RTLIL::SigBit> new_bits;
2385 new_bits.reserve(width_);
2386
2387 for (auto &bit : bits_)
2388 if (bit.wire != NULL)
2389 new_bits.push_back(bit);
2390
2391 bits_.swap(new_bits);
2392 width_ = bits_.size();
2393 }
2394
2395 check();
2396 }
2397
2398 void RTLIL::SigSpec::remove(int offset, int length)
2399 {
2400 cover("kernel.rtlil.sigspec.remove_pos");
2401
2402 unpack();
2403
2404 log_assert(offset >= 0);
2405 log_assert(length >= 0);
2406 log_assert(offset + length <= width_);
2407
2408 bits_.erase(bits_.begin() + offset, bits_.begin() + offset + length);
2409 width_ = bits_.size();
2410
2411 check();
2412 }
2413
2414 RTLIL::SigSpec RTLIL::SigSpec::extract(int offset, int length) const
2415 {
2416 unpack();
2417 cover("kernel.rtlil.sigspec.extract_pos");
2418 return std::vector<RTLIL::SigBit>(bits_.begin() + offset, bits_.begin() + offset + length);
2419 }
2420
2421 void RTLIL::SigSpec::append(const RTLIL::SigSpec &signal)
2422 {
2423 if (signal.width_ == 0)
2424 return;
2425
2426 if (width_ == 0) {
2427 *this = signal;
2428 return;
2429 }
2430
2431 cover("kernel.rtlil.sigspec.append");
2432
2433 if (packed() != signal.packed()) {
2434 pack();
2435 signal.pack();
2436 }
2437
2438 if (packed())
2439 for (auto &other_c : signal.chunks_)
2440 {
2441 auto &my_last_c = chunks_.back();
2442 if (my_last_c.wire == NULL && other_c.wire == NULL) {
2443 auto &this_data = my_last_c.data;
2444 auto &other_data = other_c.data;
2445 this_data.insert(this_data.end(), other_data.begin(), other_data.end());
2446 my_last_c.width += other_c.width;
2447 } else
2448 if (my_last_c.wire == other_c.wire && my_last_c.offset + my_last_c.width == other_c.offset) {
2449 my_last_c.width += other_c.width;
2450 } else
2451 chunks_.push_back(other_c);
2452 }
2453 else
2454 bits_.insert(bits_.end(), signal.bits_.begin(), signal.bits_.end());
2455
2456 width_ += signal.width_;
2457 check();
2458 }
2459
2460 void RTLIL::SigSpec::append_bit(const RTLIL::SigBit &bit)
2461 {
2462 if (packed())
2463 {
2464 cover("kernel.rtlil.sigspec.append_bit.packed");
2465
2466 if (chunks_.size() == 0)
2467 chunks_.push_back(bit);
2468 else
2469 if (bit.wire == NULL)
2470 if (chunks_.back().wire == NULL) {
2471 chunks_.back().data.push_back(bit.data);
2472 chunks_.back().width++;
2473 } else
2474 chunks_.push_back(bit);
2475 else
2476 if (chunks_.back().wire == bit.wire && chunks_.back().offset + chunks_.back().width == bit.offset)
2477 chunks_.back().width++;
2478 else
2479 chunks_.push_back(bit);
2480 }
2481 else
2482 {
2483 cover("kernel.rtlil.sigspec.append_bit.unpacked");
2484 bits_.push_back(bit);
2485 }
2486
2487 width_++;
2488 check();
2489 }
2490
2491 void RTLIL::SigSpec::extend(int width, bool is_signed)
2492 {
2493 cover("kernel.rtlil.sigspec.extend");
2494
2495 pack();
2496
2497 if (width_ > width)
2498 remove(width, width_ - width);
2499
2500 if (width_ < width) {
2501 RTLIL::SigSpec padding = width_ > 0 ? extract(width_ - 1, 1) : RTLIL::SigSpec(RTLIL::State::S0);
2502 if (!is_signed && padding != RTLIL::SigSpec(RTLIL::State::Sx) && padding != RTLIL::SigSpec(RTLIL::State::Sz) &&
2503 padding != RTLIL::SigSpec(RTLIL::State::Sa) && padding != RTLIL::SigSpec(RTLIL::State::Sm))
2504 padding = RTLIL::SigSpec(RTLIL::State::S0);
2505 while (width_ < width)
2506 append(padding);
2507 }
2508 }
2509
2510 void RTLIL::SigSpec::extend_u0(int width, bool is_signed)
2511 {
2512 cover("kernel.rtlil.sigspec.extend_u0");
2513
2514 pack();
2515
2516 if (width_ > width)
2517 remove(width, width_ - width);
2518
2519 if (width_ < width) {
2520 RTLIL::SigSpec padding = width_ > 0 ? extract(width_ - 1, 1) : RTLIL::SigSpec(RTLIL::State::S0);
2521 if (!is_signed)
2522 padding = RTLIL::SigSpec(RTLIL::State::S0);
2523 while (width_ < width)
2524 append(padding);
2525 }
2526
2527 }
2528
2529 RTLIL::SigSpec RTLIL::SigSpec::repeat(int num) const
2530 {
2531 cover("kernel.rtlil.sigspec.repeat");
2532
2533 RTLIL::SigSpec sig;
2534 for (int i = 0; i < num; i++)
2535 sig.append(*this);
2536 return sig;
2537 }
2538
2539 #ifndef NDEBUG
2540 void RTLIL::SigSpec::check() const
2541 {
2542 if (width_ > 64)
2543 {
2544 cover("kernel.rtlil.sigspec.check.skip");
2545 }
2546 else if (packed())
2547 {
2548 cover("kernel.rtlil.sigspec.check.packed");
2549
2550 int w = 0;
2551 for (size_t i = 0; i < chunks_.size(); i++) {
2552 const RTLIL::SigChunk chunk = chunks_[i];
2553 if (chunk.wire == NULL) {
2554 if (i > 0)
2555 log_assert(chunks_[i-1].wire != NULL);
2556 log_assert(chunk.offset == 0);
2557 log_assert(chunk.data.size() == (size_t)chunk.width);
2558 } else {
2559 if (i > 0 && chunks_[i-1].wire == chunk.wire)
2560 log_assert(chunk.offset != chunks_[i-1].offset + chunks_[i-1].width);
2561 log_assert(chunk.offset >= 0);
2562 log_assert(chunk.width >= 0);
2563 log_assert(chunk.offset + chunk.width <= chunk.wire->width);
2564 log_assert(chunk.data.size() == 0);
2565 }
2566 w += chunk.width;
2567 }
2568 log_assert(w == width_);
2569 log_assert(bits_.empty());
2570 }
2571 else
2572 {
2573 cover("kernel.rtlil.sigspec.check.unpacked");
2574
2575 log_assert(width_ == SIZE(bits_));
2576 log_assert(chunks_.empty());
2577 }
2578 }
2579 #endif
2580
2581 bool RTLIL::SigSpec::operator <(const RTLIL::SigSpec &other) const
2582 {
2583 cover("kernel.rtlil.sigspec.comp_lt");
2584
2585 if (this == &other)
2586 return false;
2587
2588 if (width_ != other.width_)
2589 return width_ < other.width_;
2590
2591 pack();
2592 other.pack();
2593
2594 if (chunks_.size() != other.chunks_.size())
2595 return chunks_.size() < other.chunks_.size();
2596
2597 hash();
2598 other.hash();
2599
2600 if (hash_ != other.hash_)
2601 return hash_ < other.hash_;
2602
2603 for (size_t i = 0; i < chunks_.size(); i++)
2604 if (chunks_[i] != other.chunks_[i]) {
2605 cover("kernel.rtlil.sigspec.comp_lt.hash_collision");
2606 return chunks_[i] < other.chunks_[i];
2607 }
2608
2609 cover("kernel.rtlil.sigspec.comp_lt.equal");
2610 return false;
2611 }
2612
2613 bool RTLIL::SigSpec::operator ==(const RTLIL::SigSpec &other) const
2614 {
2615 cover("kernel.rtlil.sigspec.comp_eq");
2616
2617 if (this == &other)
2618 return true;
2619
2620 if (width_ != other.width_)
2621 return false;
2622
2623 pack();
2624 other.pack();
2625
2626 if (chunks_.size() != chunks_.size())
2627 return false;
2628
2629 hash();
2630 other.hash();
2631
2632 if (hash_ != other.hash_)
2633 return false;
2634
2635 for (size_t i = 0; i < chunks_.size(); i++)
2636 if (chunks_[i] != other.chunks_[i]) {
2637 cover("kernel.rtlil.sigspec.comp_eq.hash_collision");
2638 return false;
2639 }
2640
2641 cover("kernel.rtlil.sigspec.comp_eq.equal");
2642 return true;
2643 }
2644
2645 bool RTLIL::SigSpec::is_wire() const
2646 {
2647 cover("kernel.rtlil.sigspec.is_wire");
2648
2649 pack();
2650 return SIZE(chunks_) == 1 && chunks_[0].wire && chunks_[0].wire->width == width_;
2651 }
2652
2653 bool RTLIL::SigSpec::is_chunk() const
2654 {
2655 cover("kernel.rtlil.sigspec.is_chunk");
2656
2657 pack();
2658 return SIZE(chunks_) == 1;
2659 }
2660
2661 bool RTLIL::SigSpec::is_fully_const() const
2662 {
2663 cover("kernel.rtlil.sigspec.is_fully_const");
2664
2665 pack();
2666 for (auto it = chunks_.begin(); it != chunks_.end(); it++)
2667 if (it->width > 0 && it->wire != NULL)
2668 return false;
2669 return true;
2670 }
2671
2672 bool RTLIL::SigSpec::is_fully_def() const
2673 {
2674 cover("kernel.rtlil.sigspec.is_fully_def");
2675
2676 pack();
2677 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
2678 if (it->width > 0 && it->wire != NULL)
2679 return false;
2680 for (size_t i = 0; i < it->data.size(); i++)
2681 if (it->data[i] != RTLIL::State::S0 && it->data[i] != RTLIL::State::S1)
2682 return false;
2683 }
2684 return true;
2685 }
2686
2687 bool RTLIL::SigSpec::is_fully_undef() const
2688 {
2689 cover("kernel.rtlil.sigspec.is_fully_undef");
2690
2691 pack();
2692 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
2693 if (it->width > 0 && it->wire != NULL)
2694 return false;
2695 for (size_t i = 0; i < it->data.size(); i++)
2696 if (it->data[i] != RTLIL::State::Sx && it->data[i] != RTLIL::State::Sz)
2697 return false;
2698 }
2699 return true;
2700 }
2701
2702 bool RTLIL::SigSpec::has_marked_bits() const
2703 {
2704 cover("kernel.rtlil.sigspec.has_marked_bits");
2705
2706 pack();
2707 for (auto it = chunks_.begin(); it != chunks_.end(); it++)
2708 if (it->width > 0 && it->wire == NULL) {
2709 for (size_t i = 0; i < it->data.size(); i++)
2710 if (it->data[i] == RTLIL::State::Sm)
2711 return true;
2712 }
2713 return false;
2714 }
2715
2716 bool RTLIL::SigSpec::as_bool() const
2717 {
2718 cover("kernel.rtlil.sigspec.as_bool");
2719
2720 pack();
2721 log_assert(is_fully_const() && SIZE(chunks_) <= 1);
2722 if (width_)
2723 return RTLIL::Const(chunks_[0].data).as_bool();
2724 return false;
2725 }
2726
2727 int RTLIL::SigSpec::as_int(bool is_signed) const
2728 {
2729 cover("kernel.rtlil.sigspec.as_int");
2730
2731 pack();
2732 log_assert(is_fully_const() && SIZE(chunks_) <= 1);
2733 if (width_)
2734 return RTLIL::Const(chunks_[0].data).as_int(is_signed);
2735 return 0;
2736 }
2737
2738 std::string RTLIL::SigSpec::as_string() const
2739 {
2740 cover("kernel.rtlil.sigspec.as_string");
2741
2742 pack();
2743 std::string str;
2744 for (size_t i = chunks_.size(); i > 0; i--) {
2745 const RTLIL::SigChunk &chunk = chunks_[i-1];
2746 if (chunk.wire != NULL)
2747 for (int j = 0; j < chunk.width; j++)
2748 str += "?";
2749 else
2750 str += RTLIL::Const(chunk.data).as_string();
2751 }
2752 return str;
2753 }
2754
2755 RTLIL::Const RTLIL::SigSpec::as_const() const
2756 {
2757 cover("kernel.rtlil.sigspec.as_const");
2758
2759 pack();
2760 log_assert(is_fully_const() && SIZE(chunks_) <= 1);
2761 if (width_)
2762 return chunks_[0].data;
2763 return RTLIL::Const();
2764 }
2765
2766 RTLIL::Wire *RTLIL::SigSpec::as_wire() const
2767 {
2768 cover("kernel.rtlil.sigspec.as_wire");
2769
2770 pack();
2771 log_assert(is_wire());
2772 return chunks_[0].wire;
2773 }
2774
2775 RTLIL::SigChunk RTLIL::SigSpec::as_chunk() const
2776 {
2777 cover("kernel.rtlil.sigspec.as_chunk");
2778
2779 pack();
2780 log_assert(is_chunk());
2781 return chunks_[0];
2782 }
2783
2784 bool RTLIL::SigSpec::match(std::string pattern) const
2785 {
2786 cover("kernel.rtlil.sigspec.match");
2787
2788 pack();
2789 std::string str = as_string();
2790 log_assert(pattern.size() == str.size());
2791
2792 for (size_t i = 0; i < pattern.size(); i++) {
2793 if (pattern[i] == ' ')
2794 continue;
2795 if (pattern[i] == '*') {
2796 if (str[i] != 'z' && str[i] != 'x')
2797 return false;
2798 continue;
2799 }
2800 if (pattern[i] != str[i])
2801 return false;
2802 }
2803
2804 return true;
2805 }
2806
2807 std::set<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_set() const
2808 {
2809 cover("kernel.rtlil.sigspec.to_sigbit_set");
2810
2811 pack();
2812 std::set<RTLIL::SigBit> sigbits;
2813 for (auto &c : chunks_)
2814 for (int i = 0; i < c.width; i++)
2815 sigbits.insert(RTLIL::SigBit(c, i));
2816 return sigbits;
2817 }
2818
2819 std::vector<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_vector() const
2820 {
2821 cover("kernel.rtlil.sigspec.to_sigbit_vector");
2822
2823 unpack();
2824 return bits_;
2825 }
2826
2827 std::map<RTLIL::SigBit, RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_map(const RTLIL::SigSpec &other) const
2828 {
2829 cover("kernel.rtlil.sigspec.to_sigbit_map");
2830
2831 unpack();
2832 other.unpack();
2833
2834 log_assert(width_ == other.width_);
2835
2836 std::map<RTLIL::SigBit, RTLIL::SigBit> new_map;
2837 for (int i = 0; i < width_; i++)
2838 new_map[bits_[i]] = other.bits_[i];
2839
2840 return new_map;
2841 }
2842
2843 RTLIL::SigBit RTLIL::SigSpec::to_single_sigbit() const
2844 {
2845 cover("kernel.rtlil.sigspec.to_single_sigbit");
2846
2847 pack();
2848 log_assert(width_ == 1);
2849 for (auto &c : chunks_)
2850 if (c.width)
2851 return RTLIL::SigBit(c);
2852 log_abort();
2853 }
2854
2855 static void sigspec_parse_split(std::vector<std::string> &tokens, const std::string &text, char sep)
2856 {
2857 size_t start = 0, end = 0;
2858 while ((end = text.find(sep, start)) != std::string::npos) {
2859 tokens.push_back(text.substr(start, end - start));
2860 start = end + 1;
2861 }
2862 tokens.push_back(text.substr(start));
2863 }
2864
2865 static int sigspec_parse_get_dummy_line_num()
2866 {
2867 return 0;
2868 }
2869
2870 bool RTLIL::SigSpec::parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str)
2871 {
2872 cover("kernel.rtlil.sigspec.parse");
2873
2874 std::vector<std::string> tokens;
2875 sigspec_parse_split(tokens, str, ',');
2876
2877 sig = RTLIL::SigSpec();
2878 for (int tokidx = int(tokens.size())-1; tokidx >= 0; tokidx--)
2879 {
2880 std::string netname = tokens[tokidx];
2881 std::string indices;
2882
2883 if (netname.size() == 0)
2884 continue;
2885
2886 if ('0' <= netname[0] && netname[0] <= '9') {
2887 cover("kernel.rtlil.sigspec.parse.const");
2888 AST::get_line_num = sigspec_parse_get_dummy_line_num;
2889 AST::AstNode *ast = VERILOG_FRONTEND::const2ast(netname);
2890 if (ast == NULL)
2891 return false;
2892 sig.append(RTLIL::Const(ast->bits));
2893 delete ast;
2894 continue;
2895 }
2896
2897 if (module == NULL)
2898 return false;
2899
2900 cover("kernel.rtlil.sigspec.parse.net");
2901
2902 if (netname[0] != '$' && netname[0] != '\\')
2903 netname = "\\" + netname;
2904
2905 if (module->wires_.count(netname) == 0) {
2906 size_t indices_pos = netname.size()-1;
2907 if (indices_pos > 2 && netname[indices_pos] == ']')
2908 {
2909 indices_pos--;
2910 while (indices_pos > 0 && ('0' <= netname[indices_pos] && netname[indices_pos] <= '9')) indices_pos--;
2911 if (indices_pos > 0 && netname[indices_pos] == ':') {
2912 indices_pos--;
2913 while (indices_pos > 0 && ('0' <= netname[indices_pos] && netname[indices_pos] <= '9')) indices_pos--;
2914 }
2915 if (indices_pos > 0 && netname[indices_pos] == '[') {
2916 indices = netname.substr(indices_pos);
2917 netname = netname.substr(0, indices_pos);
2918 }
2919 }
2920 }
2921
2922 if (module->wires_.count(netname) == 0)
2923 return false;
2924
2925 RTLIL::Wire *wire = module->wires_.at(netname);
2926 if (!indices.empty()) {
2927 std::vector<std::string> index_tokens;
2928 sigspec_parse_split(index_tokens, indices.substr(1, indices.size()-2), ':');
2929 if (index_tokens.size() == 1) {
2930 cover("kernel.rtlil.sigspec.parse.bit_sel");
2931 sig.append(RTLIL::SigSpec(wire, atoi(index_tokens.at(0).c_str())));
2932 } else {
2933 cover("kernel.rtlil.sigspec.parse.part_sel");
2934 int a = atoi(index_tokens.at(0).c_str());
2935 int b = atoi(index_tokens.at(1).c_str());
2936 if (a > b) {
2937 int tmp = a;
2938 a = b, b = tmp;
2939 }
2940 sig.append(RTLIL::SigSpec(wire, a, b-a+1));
2941 }
2942 } else
2943 sig.append(wire);
2944 }
2945
2946 return true;
2947 }
2948
2949 bool RTLIL::SigSpec::parse_sel(RTLIL::SigSpec &sig, RTLIL::Design *design, RTLIL::Module *module, std::string str)
2950 {
2951 if (str.empty() || str[0] != '@')
2952 return parse(sig, module, str);
2953
2954 cover("kernel.rtlil.sigspec.parse.sel");
2955
2956 str = RTLIL::escape_id(str.substr(1));
2957 if (design->selection_vars.count(str) == 0)
2958 return false;
2959
2960 sig = RTLIL::SigSpec();
2961 RTLIL::Selection &sel = design->selection_vars.at(str);
2962 for (auto &it : module->wires_)
2963 if (sel.selected_member(module->name, it.first))
2964 sig.append(it.second);
2965
2966 return true;
2967 }
2968
2969 bool RTLIL::SigSpec::parse_rhs(const RTLIL::SigSpec &lhs, RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str)
2970 {
2971 if (str == "0") {
2972 cover("kernel.rtlil.sigspec.parse.rhs_zeros");
2973 sig = RTLIL::SigSpec(RTLIL::State::S0, lhs.width_);
2974 return true;
2975 }
2976
2977 if (str == "~0") {
2978 cover("kernel.rtlil.sigspec.parse.rhs_ones");
2979 sig = RTLIL::SigSpec(RTLIL::State::S1, lhs.width_);
2980 return true;
2981 }
2982
2983 if (lhs.chunks_.size() == 1) {
2984 char *p = (char*)str.c_str(), *endptr;
2985 long long int val = strtoll(p, &endptr, 10);
2986 if (endptr && endptr != p && *endptr == 0) {
2987 sig = RTLIL::SigSpec(val, lhs.width_);
2988 cover("kernel.rtlil.sigspec.parse.rhs_dec");
2989 return true;
2990 }
2991 }
2992
2993 return parse(sig, module, str);
2994 }
2995
2996 RTLIL::CaseRule::~CaseRule()
2997 {
2998 for (auto it = switches.begin(); it != switches.end(); it++)
2999 delete *it;
3000 }
3001
3002 RTLIL::CaseRule *RTLIL::CaseRule::clone() const
3003 {
3004 RTLIL::CaseRule *new_caserule = new RTLIL::CaseRule;
3005 new_caserule->compare = compare;
3006 new_caserule->actions = actions;
3007 for (auto &it : switches)
3008 new_caserule->switches.push_back(it->clone());
3009 return new_caserule;
3010 }
3011
3012 RTLIL::SwitchRule::~SwitchRule()
3013 {
3014 for (auto it = cases.begin(); it != cases.end(); it++)
3015 delete *it;
3016 }
3017
3018 RTLIL::SwitchRule *RTLIL::SwitchRule::clone() const
3019 {
3020 RTLIL::SwitchRule *new_switchrule = new RTLIL::SwitchRule;
3021 new_switchrule->signal = signal;
3022 new_switchrule->attributes = attributes;
3023 for (auto &it : cases)
3024 new_switchrule->cases.push_back(it->clone());
3025 return new_switchrule;
3026
3027 }
3028
3029 RTLIL::SyncRule *RTLIL::SyncRule::clone() const
3030 {
3031 RTLIL::SyncRule *new_syncrule = new RTLIL::SyncRule;
3032 new_syncrule->type = type;
3033 new_syncrule->signal = signal;
3034 new_syncrule->actions = actions;
3035 return new_syncrule;
3036 }
3037
3038 RTLIL::Process::~Process()
3039 {
3040 for (auto it = syncs.begin(); it != syncs.end(); it++)
3041 delete *it;
3042 }
3043
3044 RTLIL::Process *RTLIL::Process::clone() const
3045 {
3046 RTLIL::Process *new_proc = new RTLIL::Process;
3047
3048 new_proc->name = name;
3049 new_proc->attributes = attributes;
3050
3051 RTLIL::CaseRule *rc_ptr = root_case.clone();
3052 new_proc->root_case = *rc_ptr;
3053 rc_ptr->switches.clear();
3054 delete rc_ptr;
3055
3056 for (auto &it : syncs)
3057 new_proc->syncs.push_back(it->clone());
3058
3059 return new_proc;
3060 }
3061
3062 YOSYS_NAMESPACE_END
3063