kernel/rtlil.cc

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
   5  *
   6  *  Permission to use, copy, modify, and/or distribute this software for any
   7  *  purpose with or without fee is hereby granted, provided that the above
   8  *  copyright notice and this permission notice appear in all copies.
   9  *
  10  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  13  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  15  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  16  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  *
  18  */
  19
  20 #include "kernel/yosys.h"
  21 #include "kernel/macc.h"
  22 #include "kernel/celltypes.h"
  23 #include "frontends/verilog/verilog_frontend.h"
  24 #include "frontends/verilog/preproc.h"
  25 #include "backends/ilang/ilang_backend.h"
  26
  27 #include <string.h>
  28 #include <algorithm>
  29
  30 YOSYS_NAMESPACE_BEGIN
  31
  32 RTLIL::IdString::destruct_guard_t RTLIL::IdString::destruct_guard;
  33 std::vector<char*> RTLIL::IdString::global_id_storage_;
  34 dict<char*, int, hash_cstr_ops> RTLIL::IdString::global_id_index_;
  35 #ifndef YOSYS_NO_IDS_REFCNT
  36 std::vector<int> RTLIL::IdString::global_refcount_storage_;
  37 std::vector<int> RTLIL::IdString::global_free_idx_list_;
  38 #endif
  39 #ifdef YOSYS_USE_STICKY_IDS
  40 int RTLIL::IdString::last_created_idx_[8];
  41 int RTLIL::IdString::last_created_idx_ptr_;
  42 #endif
  43
  44 #define X(_id) IdString RTLIL::ID::_id;
  45 #include "kernel/constids.inc"
  46 #undef X
  47
  48 dict<std::string, std::string> RTLIL::constpad;
  49
  50 const pool<IdString> &RTLIL::builtin_ff_cell_types() {
  51         static const pool<IdString> res = {
  52                 ID($sr),
  53                 ID($ff),
  54                 ID($dff),
  55                 ID($dffe),
  56                 ID($dffsr),
  57                 ID($adff),
  58                 ID($dlatch),
  59                 ID($dlatchsr),
  60                 ID($_DFFE_NN_),
  61                 ID($_DFFE_NP_),
  62                 ID($_DFFE_PN_),
  63                 ID($_DFFE_PP_),
  64                 ID($_DFFSR_NNN_),
  65                 ID($_DFFSR_NNP_),
  66                 ID($_DFFSR_NPN_),
  67                 ID($_DFFSR_NPP_),
  68                 ID($_DFFSR_PNN_),
  69                 ID($_DFFSR_PNP_),
  70                 ID($_DFFSR_PPN_),
  71                 ID($_DFFSR_PPP_),
  72                 ID($_DFF_NN0_),
  73                 ID($_DFF_NN1_),
  74                 ID($_DFF_NP0_),
  75                 ID($_DFF_NP1_),
  76                 ID($_DFF_N_),
  77                 ID($_DFF_PN0_),
  78                 ID($_DFF_PN1_),
  79                 ID($_DFF_PP0_),
  80                 ID($_DFF_PP1_),
  81                 ID($_DFF_P_),
  82                 ID($_DLATCHSR_NNN_),
  83                 ID($_DLATCHSR_NNP_),
  84                 ID($_DLATCHSR_NPN_),
  85                 ID($_DLATCHSR_NPP_),
  86                 ID($_DLATCHSR_PNN_),
  87                 ID($_DLATCHSR_PNP_),
  88                 ID($_DLATCHSR_PPN_),
  89                 ID($_DLATCHSR_PPP_),
  90                 ID($_DLATCH_N_),
  91                 ID($_DLATCH_P_),
  92                 ID($_FF_),
  93         };
  94         return res;
  95 }
  96
  97 RTLIL::Const::Const()
  98 {
  99         flags = RTLIL::CONST_FLAG_NONE;
 100 }
 101
 102 RTLIL::Const::Const(std::string str)
 103 {
 104         flags = RTLIL::CONST_FLAG_STRING;
 105         for (int i = str.size()-1; i >= 0; i--) {
 106                 unsigned char ch = str[i];
 107                 for (int j = 0; j < 8; j++) {
 108                         bits.push_back((ch & 1) != 0 ? State::S1 : State::S0);
 109                         ch = ch >> 1;
 110                 }
 111         }
 112 }
 113
 114 RTLIL::Const::Const(int val, int width)
 115 {
 116         flags = RTLIL::CONST_FLAG_NONE;
 117         for (int i = 0; i < width; i++) {
 118                 bits.push_back((val & 1) != 0 ? State::S1 : State::S0);
 119                 val = val >> 1;
 120         }
 121 }
 122
 123 RTLIL::Const::Const(RTLIL::State bit, int width)
 124 {
 125         flags = RTLIL::CONST_FLAG_NONE;
 126         for (int i = 0; i < width; i++)
 127                 bits.push_back(bit);
 128 }
 129
 130 RTLIL::Const::Const(const std::vector<bool> &bits)
 131 {
 132         flags = RTLIL::CONST_FLAG_NONE;
 133         for (const auto &b : bits)
 134                 this->bits.emplace_back(b ? State::S1 : State::S0);
 135 }
 136
 137 RTLIL::Const::Const(const RTLIL::Const &c)
 138 {
 139         flags = c.flags;
 140         for (const auto &b : c.bits)
 141                 this->bits.push_back(b);
 142 }
 143
 144 bool RTLIL::Const::operator <(const RTLIL::Const &other) const
 145 {
 146         if (bits.size() != other.bits.size())
 147                 return bits.size() < other.bits.size();
 148         for (size_t i = 0; i < bits.size(); i++)
 149                 if (bits[i] != other.bits[i])
 150                         return bits[i] < other.bits[i];
 151         return false;
 152 }
 153
 154 bool RTLIL::Const::operator ==(const RTLIL::Const &other) const
 155 {
 156         return bits == other.bits;
 157 }
 158
 159 bool RTLIL::Const::operator !=(const RTLIL::Const &other) const
 160 {
 161         return bits != other.bits;
 162 }
 163
 164 bool RTLIL::Const::as_bool() const
 165 {
 166         for (size_t i = 0; i < bits.size(); i++)
 167                 if (bits[i] == State::S1)
 168                         return true;
 169         return false;
 170 }
 171
 172 int RTLIL::Const::as_int(bool is_signed) const
 173 {
 174         int32_t ret = 0;
 175         for (size_t i = 0; i < bits.size() && i < 32; i++)
 176                 if (bits[i] == State::S1)
 177                         ret |= 1 << i;
 178         if (is_signed && bits.back() == State::S1)
 179                 for (size_t i = bits.size(); i < 32; i++)
 180                         ret |= 1 << i;
 181         return ret;
 182 }
 183
 184 std::string RTLIL::Const::as_string() const
 185 {
 186         std::string ret;
 187         ret.reserve(bits.size());
 188         for (size_t i = bits.size(); i > 0; i--)
 189                 switch (bits[i-1]) {
 190                         case S0: ret += "0"; break;
 191                         case S1: ret += "1"; break;
 192                         case Sx: ret += "x"; break;
 193                         case Sz: ret += "z"; break;
 194                         case Sa: ret += "-"; break;
 195                         case Sm: ret += "m"; break;
 196                 }
 197         return ret;
 198 }
 199
 200 RTLIL::Const RTLIL::Const::from_string(const std::string &str)
 201 {
 202         Const c;
 203         c.bits.reserve(str.size());
 204         for (auto it = str.rbegin(); it != str.rend(); it++)
 205                 switch (*it) {
 206                         case '0': c.bits.push_back(State::S0); break;
 207                         case '1': c.bits.push_back(State::S1); break;
 208                         case 'x': c.bits.push_back(State::Sx); break;
 209                         case 'z': c.bits.push_back(State::Sz); break;
 210                         case 'm': c.bits.push_back(State::Sm); break;
 211                         default: c.bits.push_back(State::Sa);
 212                 }
 213         return c;
 214 }
 215
 216 std::string RTLIL::Const::decode_string() const
 217 {
 218         std::string string;
 219         string.reserve(GetSize(bits)/8);
 220         for (int i = 0; i < GetSize(bits); i += 8) {
 221                 char ch = 0;
 222                 for (int j = 0; j < 8 && i + j < int (bits.size()); j++)
 223                         if (bits[i + j] == RTLIL::State::S1)
 224                                 ch |= 1 << j;
 225                 if (ch != 0)
 226                         string.append({ch});
 227         }
 228         std::reverse(string.begin(), string.end());
 229         return string;
 230 }
 231
 232 bool RTLIL::Const::is_fully_zero() const
 233 {
 234         cover("kernel.rtlil.const.is_fully_zero");
 235
 236         for (const auto &bit : bits)
 237                 if (bit != RTLIL::State::S0)
 238                         return false;
 239
 240         return true;
 241 }
 242
 243 bool RTLIL::Const::is_fully_ones() const
 244 {
 245         cover("kernel.rtlil.const.is_fully_ones");
 246
 247         for (const auto &bit : bits)
 248                 if (bit != RTLIL::State::S1)
 249                         return false;
 250
 251         return true;
 252 }
 253
 254 bool RTLIL::Const::is_fully_def() const
 255 {
 256         cover("kernel.rtlil.const.is_fully_def");
 257
 258         for (const auto &bit : bits)
 259                 if (bit != RTLIL::State::S0 && bit != RTLIL::State::S1)
 260                         return false;
 261
 262         return true;
 263 }
 264
 265 bool RTLIL::Const::is_fully_undef() const
 266 {
 267         cover("kernel.rtlil.const.is_fully_undef");
 268
 269         for (const auto &bit : bits)
 270                 if (bit != RTLIL::State::Sx && bit != RTLIL::State::Sz)
 271                         return false;
 272
 273         return true;
 274 }
 275
 276 void RTLIL::AttrObject::set_bool_attribute(RTLIL::IdString id, bool value)
 277 {
 278         if (value)
 279                 attributes[id] = RTLIL::Const(1);
 280         else
 281                 attributes.erase(id);
 282 }
 283
 284 bool RTLIL::AttrObject::get_bool_attribute(RTLIL::IdString id) const
 285 {
 286         const auto it = attributes.find(id);
 287         if (it == attributes.end())
 288                 return false;
 289         return it->second.as_bool();
 290 }
 291
 292 void RTLIL::AttrObject::set_strpool_attribute(RTLIL::IdString id, const pool<string> &data)
 293 {
 294         string attrval;
 295         for (const auto &s : data) {
 296                 if (!attrval.empty())
 297                         attrval += "|";
 298                 attrval += s;
 299         }
 300         attributes[id] = RTLIL::Const(attrval);
 301 }
 302
 303 void RTLIL::AttrObject::add_strpool_attribute(RTLIL::IdString id, const pool<string> &data)
 304 {
 305         pool<string> union_data = get_strpool_attribute(id);
 306         union_data.insert(data.begin(), data.end());
 307         if (!union_data.empty())
 308                 set_strpool_attribute(id, union_data);
 309 }
 310
 311 pool<string> RTLIL::AttrObject::get_strpool_attribute(RTLIL::IdString id) const
 312 {
 313         pool<string> data;
 314         if (attributes.count(id) != 0)
 315                 for (auto s : split_tokens(attributes.at(id).decode_string(), "|"))
 316                         data.insert(s);
 317         return data;
 318 }
 319
 320 void RTLIL::AttrObject::set_src_attribute(const std::string &src)
 321 {
 322         if (src.empty())
 323                 attributes.erase(ID::src);
 324         else
 325                 attributes[ID::src] = src;
 326 }
 327
 328 std::string RTLIL::AttrObject::get_src_attribute() const
 329 {
 330         std::string src;
 331         const auto it = attributes.find(ID::src);
 332         if (it != attributes.end())
 333                 src = it->second.decode_string();
 334         return src;
 335 }
 336
 337 bool RTLIL::Selection::selected_module(RTLIL::IdString mod_name) const
 338 {
 339         if (full_selection)
 340                 return true;
 341         if (selected_modules.count(mod_name) > 0)
 342                 return true;
 343         if (selected_members.count(mod_name) > 0)
 344                 return true;
 345         return false;
 346 }
 347
 348 bool RTLIL::Selection::selected_whole_module(RTLIL::IdString mod_name) const
 349 {
 350         if (full_selection)
 351                 return true;
 352         if (selected_modules.count(mod_name) > 0)
 353                 return true;
 354         return false;
 355 }
 356
 357 bool RTLIL::Selection::selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const
 358 {
 359         if (full_selection)
 360                 return true;
 361         if (selected_modules.count(mod_name) > 0)
 362                 return true;
 363         if (selected_members.count(mod_name) > 0)
 364                 if (selected_members.at(mod_name).count(memb_name) > 0)
 365                         return true;
 366         return false;
 367 }
 368
 369 void RTLIL::Selection::optimize(RTLIL::Design *design)
 370 {
 371         if (full_selection) {
 372                 selected_modules.clear();
 373                 selected_members.clear();
 374                 return;
 375         }
 376
 377         std::vector<RTLIL::IdString> del_list, add_list;
 378
 379         del_list.clear();
 380         for (auto mod_name : selected_modules) {
 381                 if (design->modules_.count(mod_name) == 0)
 382                         del_list.push_back(mod_name);
 383                 selected_members.erase(mod_name);
 384         }
 385         for (auto mod_name : del_list)
 386                 selected_modules.erase(mod_name);
 387
 388         del_list.clear();
 389         for (auto &it : selected_members)
 390                 if (design->modules_.count(it.first) == 0)
 391                         del_list.push_back(it.first);
 392         for (auto mod_name : del_list)
 393                 selected_members.erase(mod_name);
 394
 395         for (auto &it : selected_members) {
 396                 del_list.clear();
 397                 for (auto memb_name : it.second)
 398                         if (design->modules_[it.first]->count_id(memb_name) == 0)
 399                                 del_list.push_back(memb_name);
 400                 for (auto memb_name : del_list)
 401                         it.second.erase(memb_name);
 402         }
 403
 404         del_list.clear();
 405         add_list.clear();
 406         for (auto &it : selected_members)
 407                 if (it.second.size() == 0)
 408                         del_list.push_back(it.first);
 409                 else if (it.second.size() == design->modules_[it.first]->wires_.size() + design->modules_[it.first]->memories.size() +
 410                                 design->modules_[it.first]->cells_.size() + design->modules_[it.first]->processes.size())
 411                         add_list.push_back(it.first);
 412         for (auto mod_name : del_list)
 413                 selected_members.erase(mod_name);
 414         for (auto mod_name : add_list) {
 415                 selected_members.erase(mod_name);
 416                 selected_modules.insert(mod_name);
 417         }
 418
 419         if (selected_modules.size() == design->modules_.size()) {
 420                 full_selection = true;
 421                 selected_modules.clear();
 422                 selected_members.clear();
 423         }
 424 }
 425
 426 RTLIL::Design::Design()
 427   : verilog_defines (new define_map_t)
 428 {
 429         static unsigned int hashidx_count = 123456789;
 430         hashidx_count = mkhash_xorshift(hashidx_count);
 431         hashidx_ = hashidx_count;
 432
 433         refcount_modules_ = 0;
 434         selection_stack.push_back(RTLIL::Selection());
 435
 436 #ifdef WITH_PYTHON
 437         RTLIL::Design::get_all_designs()->insert(std::pair<unsigned int, RTLIL::Design*>(hashidx_, this));
 438 #endif
 439 }
 440
 441 RTLIL::Design::~Design()
 442 {
 443         for (auto it = modules_.begin(); it != modules_.end(); ++it)
 444                 delete it->second;
 445         for (auto n : verilog_packages)
 446                 delete n;
 447         for (auto n : verilog_globals)
 448                 delete n;
 449 #ifdef WITH_PYTHON
 450         RTLIL::Design::get_all_designs()->erase(hashidx_);
 451 #endif
 452 }
 453
 454 #ifdef WITH_PYTHON
 455 static std::map<unsigned int, RTLIL::Design*> all_designs;
 456 std::map<unsigned int, RTLIL::Design*> *RTLIL::Design::get_all_designs(void)
 457 {
 458         return &all_designs;
 459 }
 460 #endif
 461
 462 RTLIL::ObjRange<RTLIL::Module*> RTLIL::Design::modules()
 463 {
 464         return RTLIL::ObjRange<RTLIL::Module*>(&modules_, &refcount_modules_);
 465 }
 466
 467 RTLIL::Module *RTLIL::Design::module(RTLIL::IdString name)
 468 {
 469         return modules_.count(name) ? modules_.at(name) : NULL;
 470 }
 471
 472 RTLIL::Module *RTLIL::Design::top_module()
 473 {
 474         RTLIL::Module *module = nullptr;
 475         int module_count = 0;
 476
 477         for (auto mod : selected_modules()) {
 478                 if (mod->get_bool_attribute(ID::top))
 479                         return mod;
 480                 module_count++;
 481                 module = mod;
 482         }
 483
 484         return module_count == 1 ? module : nullptr;
 485 }
 486
 487 void RTLIL::Design::add(RTLIL::Module *module)
 488 {
 489         log_assert(modules_.count(module->name) == 0);
 490         log_assert(refcount_modules_ == 0);
 491         modules_[module->name] = module;
 492         module->design = this;
 493
 494         for (auto mon : monitors)
 495                 mon->notify_module_add(module);
 496
 497         if (yosys_xtrace) {
 498                 log("#X# New Module: %s\n", log_id(module));
 499                 log_backtrace("-X- ", yosys_xtrace-1);
 500         }
 501 }
 502
 503 RTLIL::Module *RTLIL::Design::addModule(RTLIL::IdString name)
 504 {
 505         log_assert(modules_.count(name) == 0);
 506         log_assert(refcount_modules_ == 0);
 507
 508         RTLIL::Module *module = new RTLIL::Module;
 509         modules_[name] = module;
 510         module->design = this;
 511         module->name = name;
 512
 513         for (auto mon : monitors)
 514                 mon->notify_module_add(module);
 515
 516         if (yosys_xtrace) {
 517                 log("#X# New Module: %s\n", log_id(module));
 518                 log_backtrace("-X- ", yosys_xtrace-1);
 519         }
 520
 521         return module;
 522 }
 523
 524 void RTLIL::Design::scratchpad_unset(const std::string &varname)
 525 {
 526         scratchpad.erase(varname);
 527 }
 528
 529 void RTLIL::Design::scratchpad_set_int(const std::string &varname, int value)
 530 {
 531         scratchpad[varname] = stringf("%d", value);
 532 }
 533
 534 void RTLIL::Design::scratchpad_set_bool(const std::string &varname, bool value)
 535 {
 536         scratchpad[varname] = value ? "true" : "false";
 537 }
 538
 539 void RTLIL::Design::scratchpad_set_string(const std::string &varname, std::string value)
 540 {
 541         scratchpad[varname] = std::move(value);
 542 }
 543
 544 int RTLIL::Design::scratchpad_get_int(const std::string &varname, int default_value) const
 545 {
 546         auto it = scratchpad.find(varname);
 547         if (it == scratchpad.end())
 548                 return default_value;
 549
 550         const std::string &str = it->second;
 551
 552         if (str == "0" || str == "false")
 553                 return 0;
 554
 555         if (str == "1" || str == "true")
 556                 return 1;
 557
 558         char *endptr = nullptr;
 559         long int parsed_value = strtol(str.c_str(), &endptr, 10);
 560         return *endptr ? default_value : parsed_value;
 561 }
 562
 563 bool RTLIL::Design::scratchpad_get_bool(const std::string &varname, bool default_value) const
 564 {
 565         auto it = scratchpad.find(varname);
 566         if (it == scratchpad.end())
 567                 return default_value;
 568
 569         const std::string &str = it->second;
 570
 571         if (str == "0" || str == "false")
 572                 return false;
 573
 574         if (str == "1" || str == "true")
 575                 return true;
 576
 577         return default_value;
 578 }
 579
 580 std::string RTLIL::Design::scratchpad_get_string(const std::string &varname, const std::string &default_value) const
 581 {
 582         auto it = scratchpad.find(varname);
 583         if (it == scratchpad.end())
 584                 return default_value;
 585
 586         return it->second;
 587 }
 588
 589 void RTLIL::Design::remove(RTLIL::Module *module)
 590 {
 591         for (auto mon : monitors)
 592                 mon->notify_module_del(module);
 593
 594         if (yosys_xtrace) {
 595                 log("#X# Remove Module: %s\n", log_id(module));
 596                 log_backtrace("-X- ", yosys_xtrace-1);
 597         }
 598
 599         log_assert(modules_.at(module->name) == module);
 600         log_assert(refcount_modules_ == 0);
 601         modules_.erase(module->name);
 602         delete module;
 603 }
 604
 605 void RTLIL::Design::rename(RTLIL::Module *module, RTLIL::IdString new_name)
 606 {
 607         modules_.erase(module->name);
 608         module->name = new_name;
 609         add(module);
 610 }
 611
 612 void RTLIL::Design::sort()
 613 {
 614         scratchpad.sort();
 615         modules_.sort(sort_by_id_str());
 616         for (auto &it : modules_)
 617                 it.second->sort();
 618 }
 619
 620 void RTLIL::Design::check()
 621 {
 622 #ifndef NDEBUG
 623         for (auto &it : modules_) {
 624                 log_assert(this == it.second->design);
 625                 log_assert(it.first == it.second->name);
 626                 log_assert(!it.first.empty());
 627                 it.second->check();
 628         }
 629 #endif
 630 }
 631
 632 void RTLIL::Design::optimize()
 633 {
 634         for (auto &it : modules_)
 635                 it.second->optimize();
 636         for (auto &it : selection_stack)
 637                 it.optimize(this);
 638         for (auto &it : selection_vars)
 639                 it.second.optimize(this);
 640 }
 641
 642 bool RTLIL::Design::selected_module(RTLIL::IdString mod_name) const
 643 {
 644         if (!selected_active_module.empty() && mod_name != selected_active_module)
 645                 return false;
 646         if (selection_stack.size() == 0)
 647                 return true;
 648         return selection_stack.back().selected_module(mod_name);
 649 }
 650
 651 bool RTLIL::Design::selected_whole_module(RTLIL::IdString mod_name) const
 652 {
 653         if (!selected_active_module.empty() && mod_name != selected_active_module)
 654                 return false;
 655         if (selection_stack.size() == 0)
 656                 return true;
 657         return selection_stack.back().selected_whole_module(mod_name);
 658 }
 659
 660 bool RTLIL::Design::selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const
 661 {
 662         if (!selected_active_module.empty() && mod_name != selected_active_module)
 663                 return false;
 664         if (selection_stack.size() == 0)
 665                 return true;
 666         return selection_stack.back().selected_member(mod_name, memb_name);
 667 }
 668
 669 bool RTLIL::Design::selected_module(RTLIL::Module *mod) const
 670 {
 671         return selected_module(mod->name);
 672 }
 673
 674 bool RTLIL::Design::selected_whole_module(RTLIL::Module *mod) const
 675 {
 676         return selected_whole_module(mod->name);
 677 }
 678
 679 std::vector<RTLIL::Module*> RTLIL::Design::selected_modules() const
 680 {
 681         std::vector<RTLIL::Module*> result;
 682         result.reserve(modules_.size());
 683         for (auto &it : modules_)
 684                 if (selected_module(it.first) && !it.second->get_blackbox_attribute())
 685                         result.push_back(it.second);
 686         return result;
 687 }
 688
 689 std::vector<RTLIL::Module*> RTLIL::Design::selected_whole_modules() const
 690 {
 691         std::vector<RTLIL::Module*> result;
 692         result.reserve(modules_.size());
 693         for (auto &it : modules_)
 694                 if (selected_whole_module(it.first) && !it.second->get_blackbox_attribute())
 695                         result.push_back(it.second);
 696         return result;
 697 }
 698
 699 std::vector<RTLIL::Module*> RTLIL::Design::selected_whole_modules_warn() const
 700 {
 701         std::vector<RTLIL::Module*> result;
 702         result.reserve(modules_.size());
 703         for (auto &it : modules_)
 704                 if (it.second->get_blackbox_attribute())
 705                         continue;
 706                 else if (selected_whole_module(it.first))
 707                         result.push_back(it.second);
 708                 else if (selected_module(it.first))
 709                         log_warning("Ignoring partially selected module %s.\n", log_id(it.first));
 710         return result;
 711 }
 712
 713 RTLIL::Module::Module()
 714 {
 715         static unsigned int hashidx_count = 123456789;
 716         hashidx_count = mkhash_xorshift(hashidx_count);
 717         hashidx_ = hashidx_count;
 718
 719         design = nullptr;
 720         refcount_wires_ = 0;
 721         refcount_cells_ = 0;
 722
 723 #ifdef WITH_PYTHON
 724         RTLIL::Module::get_all_modules()->insert(std::pair<unsigned int, RTLIL::Module*>(hashidx_, this));
 725 #endif
 726 }
 727
 728 RTLIL::Module::~Module()
 729 {
 730         for (auto it = wires_.begin(); it != wires_.end(); ++it)
 731                 delete it->second;
 732         for (auto it = memories.begin(); it != memories.end(); ++it)
 733                 delete it->second;
 734         for (auto it = cells_.begin(); it != cells_.end(); ++it)
 735                 delete it->second;
 736         for (auto it = processes.begin(); it != processes.end(); ++it)
 737                 delete it->second;
 738 #ifdef WITH_PYTHON
 739         RTLIL::Module::get_all_modules()->erase(hashidx_);
 740 #endif
 741 }
 742
 743 #ifdef WITH_PYTHON
 744 static std::map<unsigned int, RTLIL::Module*> all_modules;
 745 std::map<unsigned int, RTLIL::Module*> *RTLIL::Module::get_all_modules(void)
 746 {
 747         return &all_modules;
 748 }
 749 #endif
 750
 751 void RTLIL::Module::makeblackbox()
 752 {
 753         pool<RTLIL::Wire*> delwires;
 754
 755         for (auto it = wires_.begin(); it != wires_.end(); ++it)
 756                 if (!it->second->port_input && !it->second->port_output)
 757                         delwires.insert(it->second);
 758
 759         for (auto it = memories.begin(); it != memories.end(); ++it)
 760                 delete it->second;
 761         memories.clear();
 762
 763         for (auto it = cells_.begin(); it != cells_.end(); ++it)
 764                 delete it->second;
 765         cells_.clear();
 766
 767         for (auto it = processes.begin(); it != processes.end(); ++it)
 768                 delete it->second;
 769         processes.clear();
 770
 771         connections_.clear();
 772
 773         remove(delwires);
 774         set_bool_attribute(ID::blackbox);
 775 }
 776
 777 void RTLIL::Module::reprocess_module(RTLIL::Design *, const dict<RTLIL::IdString, RTLIL::Module *> &)
 778 {
 779         log_error("Cannot reprocess_module module `%s' !\n", id2cstr(name));
 780 }
 781
 782 RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, const dict<RTLIL::IdString, RTLIL::Const> &, bool mayfail)
 783 {
 784         if (mayfail)
 785                 return RTLIL::IdString();
 786         log_error("Module `%s' is used with parameters but is not parametric!\n", id2cstr(name));
 787 }
 788
 789
 790 RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, const dict<RTLIL::IdString, RTLIL::Const> &, const dict<RTLIL::IdString, RTLIL::Module*> &, const dict<RTLIL::IdString, RTLIL::IdString> &, bool mayfail)
 791 {
 792         if (mayfail)
 793                 return RTLIL::IdString();
 794         log_error("Module `%s' is used with parameters but is not parametric!\n", id2cstr(name));
 795 }
 796
 797 size_t RTLIL::Module::count_id(RTLIL::IdString id)
 798 {
 799         return wires_.count(id) + memories.count(id) + cells_.count(id) + processes.count(id);
 800 }
 801
 802 #ifndef NDEBUG
 803 namespace {
 804         struct InternalCellChecker
 805         {
 806                 RTLIL::Module *module;
 807                 RTLIL::Cell *cell;
 808                 pool<RTLIL::IdString> expected_params, expected_ports;
 809
 810                 InternalCellChecker(RTLIL::Module *module, RTLIL::Cell *cell) : module(module), cell(cell) { }
 811
 812                 void error(int linenr)
 813                 {
 814                         std::stringstream buf;
 815                         ILANG_BACKEND::dump_cell(buf, "  ", cell);
 816
 817                         log_error("Found error in internal cell %s%s%s (%s) at %s:%d:\n%s",
 818                                         module ? module->name.c_str() : "", module ? "." : "",
 819                                         cell->name.c_str(), cell->type.c_str(), __FILE__, linenr, buf.str().c_str());
 820                 }
 821
 822                 int param(RTLIL::IdString name)
 823                 {
 824                         auto it = cell->parameters.find(name);
 825                         if (it == cell->parameters.end())
 826                                 error(__LINE__);
 827                         expected_params.insert(name);
 828                         return it->second.as_int();
 829                 }
 830
 831                 int param_bool(RTLIL::IdString name)
 832                 {
 833                         int v = param(name);
 834                         if (GetSize(cell->parameters.at(name)) > 32)
 835                                 error(__LINE__);
 836                         if (v != 0 && v != 1)
 837                                 error(__LINE__);
 838                         return v;
 839                 }
 840
 841                 int param_bool(RTLIL::IdString name, bool expected)
 842                 {
 843                         int v = param_bool(name);
 844                         if (v != expected)
 845                                 error(__LINE__);
 846                         return v;
 847                 }
 848
 849                 void param_bits(RTLIL::IdString name, int width)
 850                 {
 851                         param(name);
 852                         if (GetSize(cell->parameters.at(name).bits) != width)
 853                                 error(__LINE__);
 854                 }
 855
 856                 void port(RTLIL::IdString name, int width)
 857                 {
 858                         auto it = cell->connections_.find(name);
 859                         if (it == cell->connections_.end())
 860                                 error(__LINE__);
 861                         if (GetSize(it->second) != width)
 862                                 error(__LINE__);
 863                         expected_ports.insert(name);
 864                 }
 865
 866                 void check_expected(bool check_matched_sign = false)
 867                 {
 868                         for (auto &para : cell->parameters)
 869                                 if (expected_params.count(para.first) == 0)
 870                                         error(__LINE__);
 871                         for (auto &conn : cell->connections())
 872                                 if (expected_ports.count(conn.first) == 0)
 873                                         error(__LINE__);
 874
 875                         if (check_matched_sign) {
 876                                 log_assert(expected_params.count(ID::A_SIGNED) != 0 && expected_params.count(ID::B_SIGNED) != 0);
 877                                 bool a_is_signed = cell->parameters.at(ID::A_SIGNED).as_bool();
 878                                 bool b_is_signed = cell->parameters.at(ID::B_SIGNED).as_bool();
 879                                 if (a_is_signed != b_is_signed)
 880                                         error(__LINE__);
 881                         }
 882                 }
 883
 884                 void check()
 885                 {
 886                         if (!cell->type.begins_with("$") || cell->type.begins_with("$__") || cell->type.begins_with("$paramod") || cell->type.begins_with("$fmcombine") ||
 887                                         cell->type.begins_with("$verific$") || cell->type.begins_with("$array:") || cell->type.begins_with("$extern:"))
 888                                 return;
 889
 890                         if (cell->type.in(ID($not), ID($pos), ID($neg))) {
 891                                 param_bool(ID::A_SIGNED);
 892                                 port(ID::A, param(ID::A_WIDTH));
 893                                 port(ID::Y, param(ID::Y_WIDTH));
 894                                 check_expected();
 895                                 return;
 896                         }
 897
 898                         if (cell->type.in(ID($and), ID($or), ID($xor), ID($xnor))) {
 899                                 param_bool(ID::A_SIGNED);
 900                                 param_bool(ID::B_SIGNED);
 901                                 port(ID::A, param(ID::A_WIDTH));
 902                                 port(ID::B, param(ID::B_WIDTH));
 903                                 port(ID::Y, param(ID::Y_WIDTH));
 904                                 check_expected(true);
 905                                 return;
 906                         }
 907
 908                         if (cell->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor), ID($reduce_bool))) {
 909                                 param_bool(ID::A_SIGNED);
 910                                 port(ID::A, param(ID::A_WIDTH));
 911                                 port(ID::Y, param(ID::Y_WIDTH));
 912                                 check_expected();
 913                                 return;
 914                         }
 915
 916                         if (cell->type.in(ID($shl), ID($shr), ID($sshl), ID($sshr))) {
 917                                 param_bool(ID::A_SIGNED);
 918                                 param_bool(ID::B_SIGNED, /*expected=*/false);
 919                                 port(ID::A, param(ID::A_WIDTH));
 920                                 port(ID::B, param(ID::B_WIDTH));
 921                                 port(ID::Y, param(ID::Y_WIDTH));
 922                                 check_expected(/*check_matched_sign=*/false);
 923                                 return;
 924                         }
 925
 926                         if (cell->type.in(ID($shift), ID($shiftx))) {
 927                                 param_bool(ID::A_SIGNED);
 928                                 param_bool(ID::B_SIGNED);
 929                                 port(ID::A, param(ID::A_WIDTH));
 930                                 port(ID::B, param(ID::B_WIDTH));
 931                                 port(ID::Y, param(ID::Y_WIDTH));
 932                                 check_expected(/*check_matched_sign=*/false);
 933                                 return;
 934                         }
 935
 936                         if (cell->type.in(ID($lt), ID($le), ID($eq), ID($ne), ID($eqx), ID($nex), ID($ge), ID($gt))) {
 937                                 param_bool(ID::A_SIGNED);
 938                                 param_bool(ID::B_SIGNED);
 939                                 port(ID::A, param(ID::A_WIDTH));
 940                                 port(ID::B, param(ID::B_WIDTH));
 941                                 port(ID::Y, param(ID::Y_WIDTH));
 942                                 check_expected(true);
 943                                 return;
 944                         }
 945
 946                         if (cell->type.in(ID($add), ID($sub), ID($mul), ID($div), ID($mod), ID($pow))) {
 947                                 param_bool(ID::A_SIGNED);
 948                                 param_bool(ID::B_SIGNED);
 949                                 port(ID::A, param(ID::A_WIDTH));
 950                                 port(ID::B, param(ID::B_WIDTH));
 951                                 port(ID::Y, param(ID::Y_WIDTH));
 952                                 check_expected(cell->type != ID($pow));
 953                                 return;
 954                         }
 955
 956                         if (cell->type == ID($fa)) {
 957                                 port(ID::A, param(ID::WIDTH));
 958                                 port(ID::B, param(ID::WIDTH));
 959                                 port(ID::C, param(ID::WIDTH));
 960                                 port(ID::X, param(ID::WIDTH));
 961                                 port(ID::Y, param(ID::WIDTH));
 962                                 check_expected();
 963                                 return;
 964                         }
 965
 966                         if (cell->type == ID($lcu)) {
 967                                 port(ID::P, param(ID::WIDTH));
 968                                 port(ID::G, param(ID::WIDTH));
 969                                 port(ID::CI, 1);
 970                                 port(ID::CO, param(ID::WIDTH));
 971                                 check_expected();
 972                                 return;
 973                         }
 974
 975                         if (cell->type == ID($alu)) {
 976                                 param_bool(ID::A_SIGNED);
 977                                 param_bool(ID::B_SIGNED);
 978                                 port(ID::A, param(ID::A_WIDTH));
 979                                 port(ID::B, param(ID::B_WIDTH));
 980                                 port(ID::CI, 1);
 981                                 port(ID::BI, 1);
 982                                 port(ID::X, param(ID::Y_WIDTH));
 983                                 port(ID::Y, param(ID::Y_WIDTH));
 984                                 port(ID::CO, param(ID::Y_WIDTH));
 985                                 check_expected(true);
 986                                 return;
 987                         }
 988
 989                         if (cell->type == ID($macc)) {
 990                                 param(ID::CONFIG);
 991                                 param(ID::CONFIG_WIDTH);
 992                                 port(ID::A, param(ID::A_WIDTH));
 993                                 port(ID::B, param(ID::B_WIDTH));
 994                                 port(ID::Y, param(ID::Y_WIDTH));
 995                                 check_expected();
 996                                 Macc().from_cell(cell);
 997                                 return;
 998                         }
 999
1000                         if (cell->type == ID($logic_not)) {
1001                                 param_bool(ID::A_SIGNED);
1002                                 port(ID::A, param(ID::A_WIDTH));
1003                                 port(ID::Y, param(ID::Y_WIDTH));
1004                                 check_expected();
1005                                 return;
1006                         }
1007
1008                         if (cell->type.in(ID($logic_and), ID($logic_or))) {
1009                                 param_bool(ID::A_SIGNED);
1010                                 param_bool(ID::B_SIGNED);
1011                                 port(ID::A, param(ID::A_WIDTH));
1012                                 port(ID::B, param(ID::B_WIDTH));
1013                                 port(ID::Y, param(ID::Y_WIDTH));
1014                                 check_expected(/*check_matched_sign=*/false);
1015                                 return;
1016                         }
1017
1018                         if (cell->type == ID($slice)) {
1019                                 param(ID::OFFSET);
1020                                 port(ID::A, param(ID::A_WIDTH));
1021                                 port(ID::Y, param(ID::Y_WIDTH));
1022                                 if (param(ID::OFFSET) + param(ID::Y_WIDTH) > param(ID::A_WIDTH))
1023                                         error(__LINE__);
1024                                 check_expected();
1025                                 return;
1026                         }
1027
1028                         if (cell->type == ID($concat)) {
1029                                 port(ID::A, param(ID::A_WIDTH));
1030                                 port(ID::B, param(ID::B_WIDTH));
1031                                 port(ID::Y, param(ID::A_WIDTH) + param(ID::B_WIDTH));
1032                                 check_expected();
1033                                 return;
1034                         }
1035
1036                         if (cell->type == ID($mux)) {
1037                                 port(ID::A, param(ID::WIDTH));
1038                                 port(ID::B, param(ID::WIDTH));
1039                                 port(ID::S, 1);
1040                                 port(ID::Y, param(ID::WIDTH));
1041                                 check_expected();
1042                                 return;
1043                         }
1044
1045                         if (cell->type == ID($pmux)) {
1046                                 port(ID::A, param(ID::WIDTH));
1047                                 port(ID::B, param(ID::WIDTH) * param(ID::S_WIDTH));
1048                                 port(ID::S, param(ID::S_WIDTH));
1049                                 port(ID::Y, param(ID::WIDTH));
1050                                 check_expected();
1051                                 return;
1052                         }
1053
1054                         if (cell->type == ID($lut)) {
1055                                 param(ID::LUT);
1056                                 port(ID::A, param(ID::WIDTH));
1057                                 port(ID::Y, 1);
1058                                 check_expected();
1059                                 return;
1060                         }
1061
1062                         if (cell->type == ID($sop)) {
1063                                 param(ID::DEPTH);
1064                                 param(ID::TABLE);
1065                                 port(ID::A, param(ID::WIDTH));
1066                                 port(ID::Y, 1);
1067                                 check_expected();
1068                                 return;
1069                         }
1070
1071                         if (cell->type == ID($sr)) {
1072                                 param_bool(ID::SET_POLARITY);
1073                                 param_bool(ID::CLR_POLARITY);
1074                                 port(ID::SET, param(ID::WIDTH));
1075                                 port(ID::CLR, param(ID::WIDTH));
1076                                 port(ID::Q,   param(ID::WIDTH));
1077                                 check_expected();
1078                                 return;
1079                         }
1080
1081                         if (cell->type == ID($ff)) {
1082                                 port(ID::D, param(ID::WIDTH));
1083                                 port(ID::Q, param(ID::WIDTH));
1084                                 check_expected();
1085                                 return;
1086                         }
1087
1088                         if (cell->type == ID($dff)) {
1089                                 param_bool(ID::CLK_POLARITY);
1090                                 port(ID::CLK, 1);
1091                                 port(ID::D, param(ID::WIDTH));
1092                                 port(ID::Q, param(ID::WIDTH));
1093                                 check_expected();
1094                                 return;
1095                         }
1096
1097                         if (cell->type == ID($dffe)) {
1098                                 param_bool(ID::CLK_POLARITY);
1099                                 param_bool(ID::EN_POLARITY);
1100                                 port(ID::CLK, 1);
1101                                 port(ID::EN, 1);
1102                                 port(ID::D, param(ID::WIDTH));
1103                                 port(ID::Q, param(ID::WIDTH));
1104                                 check_expected();
1105                                 return;
1106                         }
1107
1108                         if (cell->type == ID($dffsr)) {
1109                                 param_bool(ID::CLK_POLARITY);
1110                                 param_bool(ID::SET_POLARITY);
1111                                 param_bool(ID::CLR_POLARITY);
1112                                 port(ID::CLK, 1);
1113                                 port(ID::SET, param(ID::WIDTH));
1114                                 port(ID::CLR, param(ID::WIDTH));
1115                                 port(ID::D, param(ID::WIDTH));
1116                                 port(ID::Q, param(ID::WIDTH));
1117                                 check_expected();
1118                                 return;
1119                         }
1120
1121                         if (cell->type == ID($adff)) {
1122                                 param_bool(ID::CLK_POLARITY);
1123                                 param_bool(ID::ARST_POLARITY);
1124                                 param_bits(ID::ARST_VALUE, param(ID::WIDTH));
1125                                 port(ID::CLK, 1);
1126                                 port(ID::ARST, 1);
1127                                 port(ID::D, param(ID::WIDTH));
1128                                 port(ID::Q, param(ID::WIDTH));
1129                                 check_expected();
1130                                 return;
1131                         }
1132
1133                         if (cell->type == ID($dlatch)) {
1134                                 param_bool(ID::EN_POLARITY);
1135                                 port(ID::EN, 1);
1136                                 port(ID::D, param(ID::WIDTH));
1137                                 port(ID::Q, param(ID::WIDTH));
1138                                 check_expected();
1139                                 return;
1140                         }
1141
1142                         if (cell->type == ID($dlatchsr)) {
1143                                 param_bool(ID::EN_POLARITY);
1144                                 param_bool(ID::SET_POLARITY);
1145                                 param_bool(ID::CLR_POLARITY);
1146                                 port(ID::EN, 1);
1147                                 port(ID::SET, param(ID::WIDTH));
1148                                 port(ID::CLR, param(ID::WIDTH));
1149                                 port(ID::D, param(ID::WIDTH));
1150                                 port(ID::Q, param(ID::WIDTH));
1151                                 check_expected();
1152                                 return;
1153                         }
1154
1155                         if (cell->type == ID($fsm)) {
1156                                 param(ID::NAME);
1157                                 param_bool(ID::CLK_POLARITY);
1158                                 param_bool(ID::ARST_POLARITY);
1159                                 param(ID::STATE_BITS);
1160                                 param(ID::STATE_NUM);
1161                                 param(ID::STATE_NUM_LOG2);
1162                                 param(ID::STATE_RST);
1163                                 param_bits(ID::STATE_TABLE, param(ID::STATE_BITS) * param(ID::STATE_NUM));
1164                                 param(ID::TRANS_NUM);
1165                                 param_bits(ID::TRANS_TABLE, param(ID::TRANS_NUM) * (2*param(ID::STATE_NUM_LOG2) + param(ID::CTRL_IN_WIDTH) + param(ID::CTRL_OUT_WIDTH)));
1166                                 port(ID::CLK, 1);
1167                                 port(ID::ARST, 1);
1168                                 port(ID::CTRL_IN, param(ID::CTRL_IN_WIDTH));
1169                                 port(ID::CTRL_OUT, param(ID::CTRL_OUT_WIDTH));
1170                                 check_expected();
1171                                 return;
1172                         }
1173
1174                         if (cell->type == ID($memrd)) {
1175                                 param(ID::MEMID);
1176                                 param_bool(ID::CLK_ENABLE);
1177                                 param_bool(ID::CLK_POLARITY);
1178                                 param_bool(ID::TRANSPARENT);
1179                                 port(ID::CLK, 1);
1180                                 port(ID::EN, 1);
1181                                 port(ID::ADDR, param(ID::ABITS));
1182                                 port(ID::DATA, param(ID::WIDTH));
1183                                 check_expected();
1184                                 return;
1185                         }
1186
1187                         if (cell->type == ID($memwr)) {
1188                                 param(ID::MEMID);
1189                                 param_bool(ID::CLK_ENABLE);
1190                                 param_bool(ID::CLK_POLARITY);
1191                                 param(ID::PRIORITY);
1192                                 port(ID::CLK, 1);
1193                                 port(ID::EN, param(ID::WIDTH));
1194                                 port(ID::ADDR, param(ID::ABITS));
1195                                 port(ID::DATA, param(ID::WIDTH));
1196                                 check_expected();
1197                                 return;
1198                         }
1199
1200                         if (cell->type == ID($meminit)) {
1201                                 param(ID::MEMID);
1202                                 param(ID::PRIORITY);
1203                                 port(ID::ADDR, param(ID::ABITS));
1204                                 port(ID::DATA, param(ID::WIDTH) * param(ID::WORDS));
1205                                 check_expected();
1206                                 return;
1207                         }
1208
1209                         if (cell->type == ID($mem)) {
1210                                 param(ID::MEMID);
1211                                 param(ID::SIZE);
1212                                 param(ID::OFFSET);
1213                                 param(ID::INIT);
1214                                 param_bits(ID::RD_CLK_ENABLE, max(1, param(ID::RD_PORTS)));
1215                                 param_bits(ID::RD_CLK_POLARITY, max(1, param(ID::RD_PORTS)));
1216                                 param_bits(ID::RD_TRANSPARENT, max(1, param(ID::RD_PORTS)));
1217                                 param_bits(ID::WR_CLK_ENABLE, max(1, param(ID::WR_PORTS)));
1218                                 param_bits(ID::WR_CLK_POLARITY, max(1, param(ID::WR_PORTS)));
1219                                 port(ID::RD_CLK, param(ID::RD_PORTS));
1220                                 port(ID::RD_EN, param(ID::RD_PORTS));
1221                                 port(ID::RD_ADDR, param(ID::RD_PORTS) * param(ID::ABITS));
1222                                 port(ID::RD_DATA, param(ID::RD_PORTS) * param(ID::WIDTH));
1223                                 port(ID::WR_CLK, param(ID::WR_PORTS));
1224                                 port(ID::WR_EN, param(ID::WR_PORTS) * param(ID::WIDTH));
1225                                 port(ID::WR_ADDR, param(ID::WR_PORTS) * param(ID::ABITS));
1226                                 port(ID::WR_DATA, param(ID::WR_PORTS) * param(ID::WIDTH));
1227                                 check_expected();
1228                                 return;
1229                         }
1230
1231                         if (cell->type == ID($tribuf)) {
1232                                 port(ID::A, param(ID::WIDTH));
1233                                 port(ID::Y, param(ID::WIDTH));
1234                                 port(ID::EN, 1);
1235                                 check_expected();
1236                                 return;
1237                         }
1238
1239                         if (cell->type.in(ID($assert), ID($assume), ID($live), ID($fair), ID($cover))) {
1240                                 port(ID::A, 1);
1241                                 port(ID::EN, 1);
1242                                 check_expected();
1243                                 return;
1244                         }
1245
1246                         if (cell->type == ID($initstate)) {
1247                                 port(ID::Y, 1);
1248                                 check_expected();
1249                                 return;
1250                         }
1251
1252                         if (cell->type.in(ID($anyconst), ID($anyseq), ID($allconst), ID($allseq))) {
1253                                 port(ID::Y, param(ID::WIDTH));
1254                                 check_expected();
1255                                 return;
1256                         }
1257
1258                         if (cell->type == ID($equiv)) {
1259                                 port(ID::A, 1);
1260                                 port(ID::B, 1);
1261                                 port(ID::Y, 1);
1262                                 check_expected();
1263                                 return;
1264                         }
1265
1266                         if (cell->type.in(ID($specify2), ID($specify3))) {
1267                                 param_bool(ID::FULL);
1268                                 param_bool(ID::SRC_DST_PEN);
1269                                 param_bool(ID::SRC_DST_POL);
1270                                 param(ID::T_RISE_MIN);
1271                                 param(ID::T_RISE_TYP);
1272                                 param(ID::T_RISE_MAX);
1273                                 param(ID::T_FALL_MIN);
1274                                 param(ID::T_FALL_TYP);
1275                                 param(ID::T_FALL_MAX);
1276                                 port(ID::EN, 1);
1277                                 port(ID::SRC, param(ID::SRC_WIDTH));
1278                                 port(ID::DST, param(ID::DST_WIDTH));
1279                                 if (cell->type == ID($specify3)) {
1280                                         param_bool(ID::EDGE_EN);
1281                                         param_bool(ID::EDGE_POL);
1282                                         param_bool(ID::DAT_DST_PEN);
1283                                         param_bool(ID::DAT_DST_POL);
1284                                         port(ID::DAT, param(ID::DST_WIDTH));
1285                                 }
1286                                 check_expected();
1287                                 return;
1288                         }
1289
1290                         if (cell->type == ID($specrule)) {
1291                                 param(ID::TYPE);
1292                                 param_bool(ID::SRC_PEN);
1293                                 param_bool(ID::SRC_POL);
1294                                 param_bool(ID::DST_PEN);
1295                                 param_bool(ID::DST_POL);
1296                                 param(ID::T_LIMIT_MIN);
1297                                 param(ID::T_LIMIT_TYP);
1298                                 param(ID::T_LIMIT_MAX);
1299                                 param(ID::T_LIMIT2_MIN);
1300                                 param(ID::T_LIMIT2_TYP);
1301                                 param(ID::T_LIMIT2_MAX);
1302                                 port(ID::SRC_EN, 1);
1303                                 port(ID::DST_EN, 1);
1304                                 port(ID::SRC, param(ID::SRC_WIDTH));
1305                                 port(ID::DST, param(ID::DST_WIDTH));
1306                                 check_expected();
1307                                 return;
1308                         }
1309
1310                         if (cell->type == ID($_BUF_))    { port(ID::A,1); port(ID::Y,1); check_expected(); return; }
1311                         if (cell->type == ID($_NOT_))    { port(ID::A,1); port(ID::Y,1); check_expected(); return; }
1312                         if (cell->type == ID($_AND_))    { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; }
1313                         if (cell->type == ID($_NAND_))   { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; }
1314                         if (cell->type == ID($_OR_))     { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; }
1315                         if (cell->type == ID($_NOR_))    { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; }
1316                         if (cell->type == ID($_XOR_))    { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; }
1317                         if (cell->type == ID($_XNOR_))   { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; }
1318                         if (cell->type == ID($_ANDNOT_)) { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; }
1319                         if (cell->type == ID($_ORNOT_))  { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; }
1320                         if (cell->type == ID($_MUX_))    { port(ID::A,1); port(ID::B,1); port(ID::S,1); port(ID::Y,1); check_expected(); return; }
1321                         if (cell->type == ID($_NMUX_))   { port(ID::A,1); port(ID::B,1); port(ID::S,1); port(ID::Y,1); check_expected(); return; }
1322                         if (cell->type == ID($_AOI3_))   { port(ID::A,1); port(ID::B,1); port(ID::C,1); port(ID::Y,1); check_expected(); return; }
1323                         if (cell->type == ID($_OAI3_))   { port(ID::A,1); port(ID::B,1); port(ID::C,1); port(ID::Y,1); check_expected(); return; }
1324                         if (cell->type == ID($_AOI4_))   { port(ID::A,1); port(ID::B,1); port(ID::C,1); port(ID::D,1); port(ID::Y,1); check_expected(); return; }
1325                         if (cell->type == ID($_OAI4_))   { port(ID::A,1); port(ID::B,1); port(ID::C,1); port(ID::D,1); port(ID::Y,1); check_expected(); return; }
1326
1327                         if (cell->type == ID($_TBUF_))  { port(ID::A,1); port(ID::Y,1); port(ID::E,1); check_expected(); return; }
1328
1329                         if (cell->type == ID($_MUX4_))  { port(ID::A,1); port(ID::B,1); port(ID::C,1); port(ID::D,1); port(ID::S,1); port(ID::T,1); port(ID::Y,1); check_expected(); return; }
1330                         if (cell->type == ID($_MUX8_))  { port(ID::A,1); port(ID::B,1); port(ID::C,1); port(ID::D,1); port(ID::E,1); port(ID::F,1); port(ID::G,1); port(ID::H,1); port(ID::S,1); port(ID::T,1); port(ID::U,1); port(ID::Y,1); check_expected(); return; }
1331                         if (cell->type == ID($_MUX16_)) { port(ID::A,1); port(ID::B,1); port(ID::C,1); port(ID::D,1); port(ID::E,1); port(ID::F,1); port(ID::G,1); port(ID::H,1); port(ID::I,1); port(ID::J,1); port(ID::K,1); port(ID::L,1); port(ID::M,1); port(ID::N,1); port(ID::O,1); port(ID::P,1); port(ID::S,1); port(ID::T,1); port(ID::U,1); port(ID::V,1); port(ID::Y,1); check_expected(); return; }
1332
1333                         if (cell->type == ID($_SR_NN_)) { port(ID::S,1); port(ID::R,1); port(ID::Q,1); check_expected(); return; }
1334                         if (cell->type == ID($_SR_NP_)) { port(ID::S,1); port(ID::R,1); port(ID::Q,1); check_expected(); return; }
1335                         if (cell->type == ID($_SR_PN_)) { port(ID::S,1); port(ID::R,1); port(ID::Q,1); check_expected(); return; }
1336                         if (cell->type == ID($_SR_PP_)) { port(ID::S,1); port(ID::R,1); port(ID::Q,1); check_expected(); return; }
1337
1338                         if (cell->type == ID($_FF_))    { port(ID::D,1); port(ID::Q,1); check_expected();  return; }
1339                         if (cell->type == ID($_DFF_N_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); check_expected(); return; }
1340                         if (cell->type == ID($_DFF_P_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); check_expected(); return; }
1341
1342                         if (cell->type == ID($_DFFE_NN_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::E,1); check_expected(); return; }
1343                         if (cell->type == ID($_DFFE_NP_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::E,1); check_expected(); return; }
1344                         if (cell->type == ID($_DFFE_PN_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::E,1); check_expected(); return; }
1345                         if (cell->type == ID($_DFFE_PP_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::E,1); check_expected(); return; }
1346
1347                         if (cell->type == ID($_DFF_NN0_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::R,1); check_expected(); return; }
1348                         if (cell->type == ID($_DFF_NN1_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::R,1); check_expected(); return; }
1349                         if (cell->type == ID($_DFF_NP0_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::R,1); check_expected(); return; }
1350                         if (cell->type == ID($_DFF_NP1_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::R,1); check_expected(); return; }
1351                         if (cell->type == ID($_DFF_PN0_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::R,1); check_expected(); return; }
1352                         if (cell->type == ID($_DFF_PN1_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::R,1); check_expected(); return; }
1353                         if (cell->type == ID($_DFF_PP0_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::R,1); check_expected(); return; }
1354                         if (cell->type == ID($_DFF_PP1_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::R,1); check_expected(); return; }
1355
1356                         if (cell->type == ID($_DFFSR_NNN_)) { port(ID::C,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1357                         if (cell->type == ID($_DFFSR_NNP_)) { port(ID::C,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1358                         if (cell->type == ID($_DFFSR_NPN_)) { port(ID::C,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1359                         if (cell->type == ID($_DFFSR_NPP_)) { port(ID::C,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1360                         if (cell->type == ID($_DFFSR_PNN_)) { port(ID::C,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1361                         if (cell->type == ID($_DFFSR_PNP_)) { port(ID::C,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1362                         if (cell->type == ID($_DFFSR_PPN_)) { port(ID::C,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1363                         if (cell->type == ID($_DFFSR_PPP_)) { port(ID::C,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1364
1365                         if (cell->type == ID($_DLATCH_N_)) { port(ID::E,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1366                         if (cell->type == ID($_DLATCH_P_)) { port(ID::E,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1367
1368                         if (cell->type == ID($_DLATCHSR_NNN_)) { port(ID::E,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1369                         if (cell->type == ID($_DLATCHSR_NNP_)) { port(ID::E,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1370                         if (cell->type == ID($_DLATCHSR_NPN_)) { port(ID::E,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1371                         if (cell->type == ID($_DLATCHSR_NPP_)) { port(ID::E,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1372                         if (cell->type == ID($_DLATCHSR_PNN_)) { port(ID::E,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1373                         if (cell->type == ID($_DLATCHSR_PNP_)) { port(ID::E,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1374                         if (cell->type == ID($_DLATCHSR_PPN_)) { port(ID::E,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1375                         if (cell->type == ID($_DLATCHSR_PPP_)) { port(ID::E,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1376
1377                         error(__LINE__);
1378                 }
1379         };
1380 }
1381 #endif
1382
1383 void RTLIL::Module::sort()
1384 {
1385         wires_.sort(sort_by_id_str());
1386         cells_.sort(sort_by_id_str());
1387         avail_parameters.sort(sort_by_id_str());
1388         memories.sort(sort_by_id_str());
1389         processes.sort(sort_by_id_str());
1390         for (auto &it : cells_)
1391                 it.second->sort();
1392         for (auto &it : wires_)
1393                 it.second->attributes.sort(sort_by_id_str());
1394         for (auto &it : memories)
1395                 it.second->attributes.sort(sort_by_id_str());
1396 }
1397
1398 void RTLIL::Module::check()
1399 {
1400 #ifndef NDEBUG
1401         std::vector<bool> ports_declared;
1402         for (auto &it : wires_) {
1403                 log_assert(this == it.second->module);
1404                 log_assert(it.first == it.second->name);
1405                 log_assert(!it.first.empty());
1406                 log_assert(it.second->width >= 0);
1407                 log_assert(it.second->port_id >= 0);
1408                 for (auto &it2 : it.second->attributes)
1409                         log_assert(!it2.first.empty());
1410                 if (it.second->port_id) {
1411                         log_assert(GetSize(ports) >= it.second->port_id);
1412                         log_assert(ports.at(it.second->port_id-1) == it.first);
1413                         log_assert(it.second->port_input || it.second->port_output);
1414                         if (GetSize(ports_declared) < it.second->port_id)
1415                                 ports_declared.resize(it.second->port_id);
1416                         log_assert(ports_declared[it.second->port_id-1] == false);
1417                         ports_declared[it.second->port_id-1] = true;
1418                 } else
1419                         log_assert(!it.second->port_input && !it.second->port_output);
1420         }
1421         for (auto port_declared : ports_declared)
1422                 log_assert(port_declared == true);
1423         log_assert(GetSize(ports) == GetSize(ports_declared));
1424
1425         for (auto &it : memories) {
1426                 log_assert(it.first == it.second->name);
1427                 log_assert(!it.first.empty());
1428                 log_assert(it.second->width >= 0);
1429                 log_assert(it.second->size >= 0);
1430                 for (auto &it2 : it.second->attributes)
1431                         log_assert(!it2.first.empty());
1432         }
1433
1434         for (auto &it : cells_) {
1435                 log_assert(this == it.second->module);
1436                 log_assert(it.first == it.second->name);
1437                 log_assert(!it.first.empty());
1438                 log_assert(!it.second->type.empty());
1439                 for (auto &it2 : it.second->connections()) {
1440                         log_assert(!it2.first.empty());
1441                         it2.second.check();
1442                 }
1443                 for (auto &it2 : it.second->attributes)
1444                         log_assert(!it2.first.empty());
1445                 for (auto &it2 : it.second->parameters)
1446                         log_assert(!it2.first.empty());
1447                 InternalCellChecker checker(this, it.second);
1448                 checker.check();
1449         }
1450
1451         for (auto &it : processes) {
1452                 log_assert(it.first == it.second->name);
1453                 log_assert(!it.first.empty());
1454                 log_assert(it.second->root_case.compare.empty());
1455                 std::vector<CaseRule*> all_cases = {&it.second->root_case};
1456                 for (size_t i = 0; i < all_cases.size(); i++) {
1457                         for (auto &switch_it : all_cases[i]->switches) {
1458                                 for (auto &case_it : switch_it->cases) {
1459                                         for (auto &compare_it : case_it->compare) {
1460                                                 log_assert(switch_it->signal.size() == compare_it.size());
1461                                         }
1462                                         all_cases.push_back(case_it);
1463                                 }
1464                         }
1465                 }
1466                 for (auto &sync_it : it.second->syncs) {
1467                         switch (sync_it->type) {
1468                                 case SyncType::ST0:
1469                                 case SyncType::ST1:
1470                                 case SyncType::STp:
1471                                 case SyncType::STn:
1472                                 case SyncType::STe:
1473                                         log_assert(!sync_it->signal.empty());
1474                                         break;
1475                                 case SyncType::STa:
1476                                 case SyncType::STg:
1477                                 case SyncType::STi:
1478                                         log_assert(sync_it->signal.empty());
1479                                         break;
1480                         }
1481                 }
1482         }
1483
1484         for (auto &it : connections_) {
1485                 log_assert(it.first.size() == it.second.size());
1486                 log_assert(!it.first.has_const());
1487                 it.first.check();
1488                 it.second.check();
1489         }
1490
1491         for (auto &it : attributes)
1492                 log_assert(!it.first.empty());
1493 #endif
1494 }
1495
1496 void RTLIL::Module::optimize()
1497 {
1498 }
1499
1500 void RTLIL::Module::cloneInto(RTLIL::Module *new_mod) const
1501 {
1502         log_assert(new_mod->refcount_wires_ == 0);
1503         log_assert(new_mod->refcount_cells_ == 0);
1504
1505         new_mod->avail_parameters = avail_parameters;
1506
1507         for (auto &conn : connections_)
1508                 new_mod->connect(conn);
1509
1510         for (auto &attr : attributes)
1511                 new_mod->attributes[attr.first] = attr.second;
1512
1513         for (auto &it : wires_)
1514                 new_mod->addWire(it.first, it.second);
1515
1516         for (auto &it : memories)
1517                 new_mod->memories[it.first] = new RTLIL::Memory(*it.second);
1518
1519         for (auto &it : cells_)
1520                 new_mod->addCell(it.first, it.second);
1521
1522         for (auto &it : processes)
1523                 new_mod->processes[it.first] = it.second->clone();
1524
1525         struct RewriteSigSpecWorker
1526         {
1527                 RTLIL::Module *mod;
1528                 void operator()(RTLIL::SigSpec &sig)
1529                 {
1530                         sig.pack();
1531                         for (auto &c : sig.chunks_)
1532                                 if (c.wire != NULL)
1533                                         c.wire = mod->wires_.at(c.wire->name);
1534                 }
1535         };
1536
1537         RewriteSigSpecWorker rewriteSigSpecWorker;
1538         rewriteSigSpecWorker.mod = new_mod;
1539         new_mod->rewrite_sigspecs(rewriteSigSpecWorker);
1540         new_mod->fixup_ports();
1541 }
1542
1543 RTLIL::Module *RTLIL::Module::clone() const
1544 {
1545         RTLIL::Module *new_mod = new RTLIL::Module;
1546         new_mod->name = name;
1547         cloneInto(new_mod);
1548         return new_mod;
1549 }
1550
1551 bool RTLIL::Module::has_memories() const
1552 {
1553         return !memories.empty();
1554 }
1555
1556 bool RTLIL::Module::has_processes() const
1557 {
1558         return !processes.empty();
1559 }
1560
1561 bool RTLIL::Module::has_memories_warn() const
1562 {
1563         if (!memories.empty())
1564                 log_warning("Ignoring module %s because it contains memories (run 'memory' command first).\n", log_id(this));
1565         return !memories.empty();
1566 }
1567
1568 bool RTLIL::Module::has_processes_warn() const
1569 {
1570         if (!processes.empty())
1571                 log_warning("Ignoring module %s because it contains processes (run 'proc' command first).\n", log_id(this));
1572         return !processes.empty();
1573 }
1574
1575 std::vector<RTLIL::Wire*> RTLIL::Module::selected_wires() const
1576 {
1577         std::vector<RTLIL::Wire*> result;
1578         result.reserve(wires_.size());
1579         for (auto &it : wires_)
1580                 if (design->selected(this, it.second))
1581                         result.push_back(it.second);
1582         return result;
1583 }
1584
1585 std::vector<RTLIL::Cell*> RTLIL::Module::selected_cells() const
1586 {
1587         std::vector<RTLIL::Cell*> result;
1588         result.reserve(cells_.size());
1589         for (auto &it : cells_)
1590                 if (design->selected(this, it.second))
1591                         result.push_back(it.second);
1592         return result;
1593 }
1594
1595 void RTLIL::Module::add(RTLIL::Wire *wire)
1596 {
1597         log_assert(!wire->name.empty());
1598         log_assert(count_id(wire->name) == 0);
1599         log_assert(refcount_wires_ == 0);
1600         wires_[wire->name] = wire;
1601         wire->module = this;
1602 }
1603
1604 void RTLIL::Module::add(RTLIL::Cell *cell)
1605 {
1606         log_assert(!cell->name.empty());
1607         log_assert(count_id(cell->name) == 0);
1608         log_assert(refcount_cells_ == 0);
1609         cells_[cell->name] = cell;
1610         cell->module = this;
1611 }
1612
1613 void RTLIL::Module::remove(const pool<RTLIL::Wire*> &wires)
1614 {
1615         log_assert(refcount_wires_ == 0);
1616
1617         struct DeleteWireWorker
1618         {
1619                 RTLIL::Module *module;
1620                 const pool<RTLIL::Wire*> *wires_p;
1621
1622                 void operator()(RTLIL::SigSpec &sig) {
1623                         sig.pack();
1624                         for (auto &c : sig.chunks_)
1625                                 if (c.wire != NULL && wires_p->count(c.wire)) {
1626                                         c.wire = module->addWire(NEW_ID, c.width);
1627                                         c.offset = 0;
1628                                 }
1629                 }
1630
1631                 void operator()(RTLIL::SigSpec &lhs, RTLIL::SigSpec &rhs) {
1632                         log_assert(GetSize(lhs) == GetSize(rhs));
1633                         lhs.unpack();
1634                         rhs.unpack();
1635                         for (int i = 0; i < GetSize(lhs); i++) {
1636                                 RTLIL::SigBit &lhs_bit = lhs.bits_[i];
1637                                 RTLIL::SigBit &rhs_bit = rhs.bits_[i];
1638                                 if ((lhs_bit.wire != nullptr && wires_p->count(lhs_bit.wire)) || (rhs_bit.wire != nullptr && wires_p->count(rhs_bit.wire))) {
1639                                         lhs_bit = State::Sx;
1640                                         rhs_bit = State::Sx;
1641                                 }
1642                         }
1643                 }
1644         };
1645
1646         DeleteWireWorker delete_wire_worker;
1647         delete_wire_worker.module = this;
1648         delete_wire_worker.wires_p = &wires;
1649         rewrite_sigspecs2(delete_wire_worker);
1650
1651         for (auto &it : wires) {
1652                 log_assert(wires_.count(it->name) != 0);
1653                 wires_.erase(it->name);
1654                 delete it;
1655         }
1656 }
1657
1658 void RTLIL::Module::remove(RTLIL::Cell *cell)
1659 {
1660         while (!cell->connections_.empty())
1661                 cell->unsetPort(cell->connections_.begin()->first);
1662
1663         log_assert(cells_.count(cell->name) != 0);
1664         log_assert(refcount_cells_ == 0);
1665         cells_.erase(cell->name);
1666         delete cell;
1667 }
1668
1669 void RTLIL::Module::rename(RTLIL::Wire *wire, RTLIL::IdString new_name)
1670 {
1671         log_assert(wires_[wire->name] == wire);
1672         log_assert(refcount_wires_ == 0);
1673         wires_.erase(wire->name);
1674         wire->name = new_name;
1675         add(wire);
1676 }
1677
1678 void RTLIL::Module::rename(RTLIL::Cell *cell, RTLIL::IdString new_name)
1679 {
1680         log_assert(cells_[cell->name] == cell);
1681         log_assert(refcount_wires_ == 0);
1682         cells_.erase(cell->name);
1683         cell->name = new_name;
1684         add(cell);
1685 }
1686
1687 void RTLIL::Module::rename(RTLIL::IdString old_name, RTLIL::IdString new_name)
1688 {
1689         log_assert(count_id(old_name) != 0);
1690         if (wires_.count(old_name))
1691                 rename(wires_.at(old_name), new_name);
1692         else if (cells_.count(old_name))
1693                 rename(cells_.at(old_name), new_name);
1694         else
1695                 log_abort();
1696 }
1697
1698 void RTLIL::Module::swap_names(RTLIL::Wire *w1, RTLIL::Wire *w2)
1699 {
1700         log_assert(wires_[w1->name] == w1);
1701         log_assert(wires_[w2->name] == w2);
1702         log_assert(refcount_wires_ == 0);
1703
1704         wires_.erase(w1->name);
1705         wires_.erase(w2->name);
1706
1707         std::swap(w1->name, w2->name);
1708
1709         wires_[w1->name] = w1;
1710         wires_[w2->name] = w2;
1711 }
1712
1713 void RTLIL::Module::swap_names(RTLIL::Cell *c1, RTLIL::Cell *c2)
1714 {
1715         log_assert(cells_[c1->name] == c1);
1716         log_assert(cells_[c2->name] == c2);
1717         log_assert(refcount_cells_ == 0);
1718
1719         cells_.erase(c1->name);
1720         cells_.erase(c2->name);
1721
1722         std::swap(c1->name, c2->name);
1723
1724         cells_[c1->name] = c1;
1725         cells_[c2->name] = c2;
1726 }
1727
1728 RTLIL::IdString RTLIL::Module::uniquify(RTLIL::IdString name)
1729 {
1730         int index = 0;
1731         return uniquify(name, index);
1732 }
1733
1734 RTLIL::IdString RTLIL::Module::uniquify(RTLIL::IdString name, int &index)
1735 {
1736         if (index == 0) {
1737                 if (count_id(name) == 0)
1738                         return name;
1739                 index++;
1740         }
1741
1742         while (1) {
1743                 RTLIL::IdString new_name = stringf("%s_%d", name.c_str(), index);
1744                 if (count_id(new_name) == 0)
1745                         return new_name;
1746                 index++;
1747         }
1748 }
1749
1750 static bool fixup_ports_compare(const RTLIL::Wire *a, const RTLIL::Wire *b)
1751 {
1752         if (a->port_id && !b->port_id)
1753                 return true;
1754         if (!a->port_id && b->port_id)
1755                 return false;
1756
1757         if (a->port_id == b->port_id)
1758                 return a->name < b->name;
1759         return a->port_id < b->port_id;
1760 }
1761
1762 void RTLIL::Module::connect(const RTLIL::SigSig &conn)
1763 {
1764         for (auto mon : monitors)
1765                 mon->notify_connect(this, conn);
1766
1767         if (design)
1768                 for (auto mon : design->monitors)
1769                         mon->notify_connect(this, conn);
1770
1771         // ignore all attempts to assign constants to other constants
1772         if (conn.first.has_const()) {
1773                 RTLIL::SigSig new_conn;
1774                 for (int i = 0; i < GetSize(conn.first); i++)
1775                         if (conn.first[i].wire) {
1776                                 new_conn.first.append(conn.first[i]);
1777                                 new_conn.second.append(conn.second[i]);
1778                         }
1779                 if (GetSize(new_conn.first))
1780                         connect(new_conn);
1781                 return;
1782         }
1783
1784         if (yosys_xtrace) {
1785                 log("#X# Connect (SigSig) in %s: %s = %s (%d bits)\n", log_id(this), log_signal(conn.first), log_signal(conn.second), GetSize(conn.first));
1786                 log_backtrace("-X- ", yosys_xtrace-1);
1787         }
1788
1789         log_assert(GetSize(conn.first) == GetSize(conn.second));
1790         connections_.push_back(conn);
1791 }
1792
1793 void RTLIL::Module::connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs)
1794 {
1795         connect(RTLIL::SigSig(lhs, rhs));
1796 }
1797
1798 void RTLIL::Module::new_connections(const std::vector<RTLIL::SigSig> &new_conn)
1799 {
1800         for (auto mon : monitors)
1801                 mon->notify_connect(this, new_conn);
1802
1803         if (design)
1804                 for (auto mon : design->monitors)
1805                         mon->notify_connect(this, new_conn);
1806
1807         if (yosys_xtrace) {
1808                 log("#X# New connections vector in %s:\n", log_id(this));
1809                 for (auto &conn: new_conn)
1810                         log("#X#    %s = %s (%d bits)\n", log_signal(conn.first), log_signal(conn.second), GetSize(conn.first));
1811                 log_backtrace("-X- ", yosys_xtrace-1);
1812         }
1813
1814         connections_ = new_conn;
1815 }
1816
1817 const std::vector<RTLIL::SigSig> &RTLIL::Module::connections() const
1818 {
1819         return connections_;
1820 }
1821
1822 void RTLIL::Module::fixup_ports()
1823 {
1824         std::vector<RTLIL::Wire*> all_ports;
1825
1826         for (auto &w : wires_)
1827                 if (w.second->port_input || w.second->port_output)
1828                         all_ports.push_back(w.second);
1829                 else
1830                         w.second->port_id = 0;
1831
1832         std::sort(all_ports.begin(), all_ports.end(), fixup_ports_compare);
1833
1834         ports.clear();
1835         for (size_t i = 0; i < all_ports.size(); i++) {
1836                 ports.push_back(all_ports[i]->name);
1837                 all_ports[i]->port_id = i+1;
1838         }
1839 }
1840
1841 RTLIL::Wire *RTLIL::Module::addWire(RTLIL::IdString name, int width)
1842 {
1843         RTLIL::Wire *wire = new RTLIL::Wire;
1844         wire->name = name;
1845         wire->width = width;
1846         add(wire);
1847         return wire;
1848 }
1849
1850 RTLIL::Wire *RTLIL::Module::addWire(RTLIL::IdString name, const RTLIL::Wire *other)
1851 {
1852         RTLIL::Wire *wire = addWire(name);
1853         wire->width = other->width;
1854         wire->start_offset = other->start_offset;
1855         wire->port_id = other->port_id;
1856         wire->port_input = other->port_input;
1857         wire->port_output = other->port_output;
1858         wire->upto = other->upto;
1859         wire->attributes = other->attributes;
1860         return wire;
1861 }
1862
1863 RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, RTLIL::IdString type)
1864 {
1865         RTLIL::Cell *cell = new RTLIL::Cell;
1866         cell->name = name;
1867         cell->type = type;
1868         add(cell);
1869         return cell;
1870 }
1871
1872 RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, const RTLIL::Cell *other)
1873 {
1874         RTLIL::Cell *cell = addCell(name, other->type);
1875         cell->connections_ = other->connections_;
1876         cell->parameters = other->parameters;
1877         cell->attributes = other->attributes;
1878         return cell;
1879 }
1880
1881 #define DEF_METHOD(_func, _y_size, _type) \
1882         RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed, const std::string &src) { \
1883                 RTLIL::Cell *cell = addCell(name, _type);           \
1884                 cell->parameters[ID::A_SIGNED] = is_signed;         \
1885                 cell->parameters[ID::A_WIDTH] = sig_a.size();       \
1886                 cell->parameters[ID::Y_WIDTH] = sig_y.size();       \
1887                 cell->setPort(ID::A, sig_a);                        \
1888                 cell->setPort(ID::Y, sig_y);                        \
1889                 cell->set_src_attribute(src);                       \
1890                 return cell;                                        \
1891         } \
1892         RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed, const std::string &src) { \
1893                 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size);    \
1894                 add ## _func(name, sig_a, sig_y, is_signed, src);   \
1895                 return sig_y;                                       \
1896         }
1897 DEF_METHOD(Not,        sig_a.size(), ID($not))
1898 DEF_METHOD(Pos,        sig_a.size(), ID($pos))
1899 DEF_METHOD(Neg,        sig_a.size(), ID($neg))
1900 DEF_METHOD(ReduceAnd,  1, ID($reduce_and))
1901 DEF_METHOD(ReduceOr,   1, ID($reduce_or))
1902 DEF_METHOD(ReduceXor,  1, ID($reduce_xor))
1903 DEF_METHOD(ReduceXnor, 1, ID($reduce_xnor))
1904 DEF_METHOD(ReduceBool, 1, ID($reduce_bool))
1905 DEF_METHOD(LogicNot,   1, ID($logic_not))
1906 #undef DEF_METHOD
1907
1908 #define DEF_METHOD(_func, _y_size, _type) \
1909         RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed, const std::string &src) { \
1910                 RTLIL::Cell *cell = addCell(name, _type);           \
1911                 cell->parameters[ID::A_SIGNED] = is_signed;         \
1912                 cell->parameters[ID::B_SIGNED] = is_signed;         \
1913                 cell->parameters[ID::A_WIDTH] = sig_a.size();       \
1914                 cell->parameters[ID::B_WIDTH] = sig_b.size();       \
1915                 cell->parameters[ID::Y_WIDTH] = sig_y.size();       \
1916                 cell->setPort(ID::A, sig_a);                        \
1917                 cell->setPort(ID::B, sig_b);                        \
1918                 cell->setPort(ID::Y, sig_y);                        \
1919                 cell->set_src_attribute(src);                       \
1920                 return cell;                                        \
1921         } \
1922         RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed, const std::string &src) { \
1923                 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size);         \
1924                 add ## _func(name, sig_a, sig_b, sig_y, is_signed, src); \
1925                 return sig_y;                                            \
1926         }
1927 DEF_METHOD(And,      max(sig_a.size(), sig_b.size()), ID($and))
1928 DEF_METHOD(Or,       max(sig_a.size(), sig_b.size()), ID($or))
1929 DEF_METHOD(Xor,      max(sig_a.size(), sig_b.size()), ID($xor))
1930 DEF_METHOD(Xnor,     max(sig_a.size(), sig_b.size()), ID($xnor))
1931 DEF_METHOD(Shift,    sig_a.size(), ID($shift))
1932 DEF_METHOD(Shiftx,   sig_a.size(), ID($shiftx))
1933 DEF_METHOD(Lt,       1, ID($lt))
1934 DEF_METHOD(Le,       1, ID($le))
1935 DEF_METHOD(Eq,       1, ID($eq))
1936 DEF_METHOD(Ne,       1, ID($ne))
1937 DEF_METHOD(Eqx,      1, ID($eqx))
1938 DEF_METHOD(Nex,      1, ID($nex))
1939 DEF_METHOD(Ge,       1, ID($ge))
1940 DEF_METHOD(Gt,       1, ID($gt))
1941 DEF_METHOD(Add,      max(sig_a.size(), sig_b.size()), ID($add))
1942 DEF_METHOD(Sub,      max(sig_a.size(), sig_b.size()), ID($sub))
1943 DEF_METHOD(Mul,      max(sig_a.size(), sig_b.size()), ID($mul))
1944 DEF_METHOD(Div,      max(sig_a.size(), sig_b.size()), ID($div))
1945 DEF_METHOD(Mod,      max(sig_a.size(), sig_b.size()), ID($mod))
1946 DEF_METHOD(LogicAnd, 1, ID($logic_and))
1947 DEF_METHOD(LogicOr,  1, ID($logic_or))
1948 #undef DEF_METHOD
1949
1950 #define DEF_METHOD(_func, _y_size, _type) \
1951         RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed, const std::string &src) { \
1952                 RTLIL::Cell *cell = addCell(name, _type);           \
1953                 cell->parameters[ID::A_SIGNED] = is_signed;         \
1954                 cell->parameters[ID::B_SIGNED] = false;             \
1955                 cell->parameters[ID::A_WIDTH] = sig_a.size();       \
1956                 cell->parameters[ID::B_WIDTH] = sig_b.size();       \
1957                 cell->parameters[ID::Y_WIDTH] = sig_y.size();       \
1958                 cell->setPort(ID::A, sig_a);                        \
1959                 cell->setPort(ID::B, sig_b);                        \
1960                 cell->setPort(ID::Y, sig_y);                        \
1961                 cell->set_src_attribute(src);                       \
1962                 return cell;                                        \
1963         } \
1964         RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed, const std::string &src) { \
1965                 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size);         \
1966                 add ## _func(name, sig_a, sig_b, sig_y, is_signed, src); \
1967                 return sig_y;                                            \
1968         }
1969 DEF_METHOD(Shl,      sig_a.size(), ID($shl))
1970 DEF_METHOD(Shr,      sig_a.size(), ID($shr))
1971 DEF_METHOD(Sshl,     sig_a.size(), ID($sshl))
1972 DEF_METHOD(Sshr,     sig_a.size(), ID($sshr))
1973 #undef DEF_METHOD
1974
1975 #define DEF_METHOD(_func, _type, _pmux) \
1976         RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, const std::string &src) { \
1977                 RTLIL::Cell *cell = addCell(name, _type);                 \
1978                 cell->parameters[ID::WIDTH] = sig_a.size();               \
1979                 if (_pmux) cell->parameters[ID::S_WIDTH] = sig_s.size();  \
1980                 cell->setPort(ID::A, sig_a);                              \
1981                 cell->setPort(ID::B, sig_b);                              \
1982                 cell->setPort(ID::S, sig_s);                              \
1983                 cell->setPort(ID::Y, sig_y);                              \
1984                 cell->set_src_attribute(src);                             \
1985                 return cell;                                              \
1986         } \
1987         RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const std::string &src) { \
1988                 RTLIL::SigSpec sig_y = addWire(NEW_ID, sig_a.size());     \
1989                 add ## _func(name, sig_a, sig_b, sig_s, sig_y, src);      \
1990                 return sig_y;                                             \
1991         }
1992 DEF_METHOD(Mux,      ID($mux),        0)
1993 DEF_METHOD(Pmux,     ID($pmux),       1)
1994 #undef DEF_METHOD
1995
1996 #define DEF_METHOD_2(_func, _type, _P1, _P2) \
1997         RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const std::string &src) { \
1998                 RTLIL::Cell *cell = addCell(name, _type);         \
1999                 cell->setPort("\\" #_P1, sig1);                   \
2000                 cell->setPort("\\" #_P2, sig2);                   \
2001                 cell->set_src_attribute(src);                     \
2002                 return cell;                                      \
2003         } \
2004         RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const std::string &src) { \
2005                 RTLIL::SigBit sig2 = addWire(NEW_ID);             \
2006                 add ## _func(name, sig1, sig2, src);              \
2007                 return sig2;                                      \
2008         }
2009 #define DEF_METHOD_3(_func, _type, _P1, _P2, _P3) \
2010         RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const RTLIL::SigBit &sig3, const std::string &src) { \
2011                 RTLIL::Cell *cell = addCell(name, _type);         \
2012                 cell->setPort("\\" #_P1, sig1);                   \
2013                 cell->setPort("\\" #_P2, sig2);                   \
2014                 cell->setPort("\\" #_P3, sig3);                   \
2015                 cell->set_src_attribute(src);                     \
2016                 return cell;                                      \
2017         } \
2018         RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const std::string &src) { \
2019                 RTLIL::SigBit sig3 = addWire(NEW_ID);             \
2020                 add ## _func(name, sig1, sig2, sig3, src);        \
2021                 return sig3;                                      \
2022         }
2023 #define DEF_METHOD_4(_func, _type, _P1, _P2, _P3, _P4) \
2024         RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const RTLIL::SigBit &sig3, const RTLIL::SigBit &sig4, const std::string &src) { \
2025                 RTLIL::Cell *cell = addCell(name, _type);         \
2026                 cell->setPort("\\" #_P1, sig1);                   \
2027                 cell->setPort("\\" #_P2, sig2);                   \
2028                 cell->setPort("\\" #_P3, sig3);                   \
2029                 cell->setPort("\\" #_P4, sig4);                   \
2030                 cell->set_src_attribute(src);                     \
2031                 return cell;                                      \
2032         } \
2033         RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const RTLIL::SigBit &sig3, const std::string &src) { \
2034                 RTLIL::SigBit sig4 = addWire(NEW_ID);             \
2035                 add ## _func(name, sig1, sig2, sig3, sig4, src);  \
2036                 return sig4;                                      \
2037         }
2038 #define DEF_METHOD_5(_func, _type, _P1, _P2, _P3, _P4, _P5) \
2039         RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const RTLIL::SigBit &sig3, const RTLIL::SigBit &sig4, const RTLIL::SigBit &sig5, const std::string &src) { \
2040                 RTLIL::Cell *cell = addCell(name, _type);         \
2041                 cell->setPort("\\" #_P1, sig1);                   \
2042                 cell->setPort("\\" #_P2, sig2);                   \
2043                 cell->setPort("\\" #_P3, sig3);                   \
2044                 cell->setPort("\\" #_P4, sig4);                   \
2045                 cell->setPort("\\" #_P5, sig5);                   \
2046                 cell->set_src_attribute(src);                     \
2047                 return cell;                                      \
2048         } \
2049         RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const RTLIL::SigBit &sig3, const RTLIL::SigBit &sig4, const std::string &src) { \
2050                 RTLIL::SigBit sig5 = addWire(NEW_ID);                  \
2051                 add ## _func(name, sig1, sig2, sig3, sig4, sig5, src); \
2052                 return sig5;                                           \
2053         }
2054 DEF_METHOD_2(BufGate,    ID($_BUF_),    A, Y)
2055 DEF_METHOD_2(NotGate,    ID($_NOT_),    A, Y)
2056 DEF_METHOD_3(AndGate,    ID($_AND_),    A, B, Y)
2057 DEF_METHOD_3(NandGate,   ID($_NAND_),   A, B, Y)
2058 DEF_METHOD_3(OrGate,     ID($_OR_),     A, B, Y)
2059 DEF_METHOD_3(NorGate,    ID($_NOR_),    A, B, Y)
2060 DEF_METHOD_3(XorGate,    ID($_XOR_),    A, B, Y)
2061 DEF_METHOD_3(XnorGate,   ID($_XNOR_),   A, B, Y)
2062 DEF_METHOD_3(AndnotGate, ID($_ANDNOT_), A, B, Y)
2063 DEF_METHOD_3(OrnotGate,  ID($_ORNOT_),  A, B, Y)
2064 DEF_METHOD_4(MuxGate,    ID($_MUX_),    A, B, S, Y)
2065 DEF_METHOD_4(NmuxGate,   ID($_NMUX_),   A, B, S, Y)
2066 DEF_METHOD_4(Aoi3Gate,   ID($_AOI3_),   A, B, C, Y)
2067 DEF_METHOD_4(Oai3Gate,   ID($_OAI3_),   A, B, C, Y)
2068 DEF_METHOD_5(Aoi4Gate,   ID($_AOI4_),   A, B, C, D, Y)
2069 DEF_METHOD_5(Oai4Gate,   ID($_OAI4_),   A, B, C, D, Y)
2070 #undef DEF_METHOD_2
2071 #undef DEF_METHOD_3
2072 #undef DEF_METHOD_4
2073 #undef DEF_METHOD_5
2074
2075 RTLIL::Cell* RTLIL::Module::addPow(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool a_signed, bool b_signed, const std::string &src)
2076 {
2077         RTLIL::Cell *cell = addCell(name, ID($pow));
2078         cell->parameters[ID::A_SIGNED] = a_signed;
2079         cell->parameters[ID::B_SIGNED] = b_signed;
2080         cell->parameters[ID::A_WIDTH] = sig_a.size();
2081         cell->parameters[ID::B_WIDTH] = sig_b.size();
2082         cell->parameters[ID::Y_WIDTH] = sig_y.size();
2083         cell->setPort(ID::A, sig_a);
2084         cell->setPort(ID::B, sig_b);
2085         cell->setPort(ID::Y, sig_y);
2086         cell->set_src_attribute(src);
2087         return cell;
2088 }
2089
2090 RTLIL::Cell* RTLIL::Module::addSlice(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, RTLIL::Const offset, const std::string &src)
2091 {
2092         RTLIL::Cell *cell = addCell(name, ID($slice));
2093         cell->parameters[ID::A_WIDTH] = sig_a.size();
2094         cell->parameters[ID::Y_WIDTH] = sig_y.size();
2095         cell->parameters[ID::OFFSET] = offset;
2096         cell->setPort(ID::A, sig_a);
2097         cell->setPort(ID::Y, sig_y);
2098         cell->set_src_attribute(src);
2099         return cell;
2100 }
2101
2102 RTLIL::Cell* RTLIL::Module::addConcat(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, const std::string &src)
2103 {
2104         RTLIL::Cell *cell = addCell(name, ID($concat));
2105         cell->parameters[ID::A_WIDTH] = sig_a.size();
2106         cell->parameters[ID::B_WIDTH] = sig_b.size();
2107         cell->setPort(ID::A, sig_a);
2108         cell->setPort(ID::B, sig_b);
2109         cell->setPort(ID::Y, sig_y);
2110         cell->set_src_attribute(src);
2111         return cell;
2112 }
2113
2114 RTLIL::Cell* RTLIL::Module::addLut(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, RTLIL::Const lut, const std::string &src)
2115 {
2116         RTLIL::Cell *cell = addCell(name, ID($lut));
2117         cell->parameters[ID::LUT] = lut;
2118         cell->parameters[ID::WIDTH] = sig_a.size();
2119         cell->setPort(ID::A, sig_a);
2120         cell->setPort(ID::Y, sig_y);
2121         cell->set_src_attribute(src);
2122         return cell;
2123 }
2124
2125 RTLIL::Cell* RTLIL::Module::addTribuf(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_y, const std::string &src)
2126 {
2127         RTLIL::Cell *cell = addCell(name, ID($tribuf));
2128         cell->parameters[ID::WIDTH] = sig_a.size();
2129         cell->setPort(ID::A, sig_a);
2130         cell->setPort(ID::EN, sig_en);
2131         cell->setPort(ID::Y, sig_y);
2132         cell->set_src_attribute(src);
2133         return cell;
2134 }
2135
2136 RTLIL::Cell* RTLIL::Module::addAssert(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src)
2137 {
2138         RTLIL::Cell *cell = addCell(name, ID($assert));
2139         cell->setPort(ID::A, sig_a);
2140         cell->setPort(ID::EN, sig_en);
2141         cell->set_src_attribute(src);
2142         return cell;
2143 }
2144
2145 RTLIL::Cell* RTLIL::Module::addAssume(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src)
2146 {
2147         RTLIL::Cell *cell = addCell(name, ID($assume));
2148         cell->setPort(ID::A, sig_a);
2149         cell->setPort(ID::EN, sig_en);
2150         cell->set_src_attribute(src);
2151         return cell;
2152 }
2153
2154 RTLIL::Cell* RTLIL::Module::addLive(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src)
2155 {
2156         RTLIL::Cell *cell = addCell(name, ID($live));
2157         cell->setPort(ID::A, sig_a);
2158         cell->setPort(ID::EN, sig_en);
2159         cell->set_src_attribute(src);
2160         return cell;
2161 }
2162
2163 RTLIL::Cell* RTLIL::Module::addFair(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src)
2164 {
2165         RTLIL::Cell *cell = addCell(name, ID($fair));
2166         cell->setPort(ID::A, sig_a);
2167         cell->setPort(ID::EN, sig_en);
2168         cell->set_src_attribute(src);
2169         return cell;
2170 }
2171
2172 RTLIL::Cell* RTLIL::Module::addCover(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src)
2173 {
2174         RTLIL::Cell *cell = addCell(name, ID($cover));
2175         cell->setPort(ID::A, sig_a);
2176         cell->setPort(ID::EN, sig_en);
2177         cell->set_src_attribute(src);
2178         return cell;
2179 }
2180
2181 RTLIL::Cell* RTLIL::Module::addEquiv(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, const std::string &src)
2182 {
2183         RTLIL::Cell *cell = addCell(name, ID($equiv));
2184         cell->setPort(ID::A, sig_a);
2185         cell->setPort(ID::B, sig_b);
2186         cell->setPort(ID::Y, sig_y);
2187         cell->set_src_attribute(src);
2188         return cell;
2189 }
2190
2191 RTLIL::Cell* RTLIL::Module::addSr(RTLIL::IdString name, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, const RTLIL::SigSpec &sig_q, bool set_polarity, bool clr_polarity, const std::string &src)
2192 {
2193         RTLIL::Cell *cell = addCell(name, ID($sr));
2194         cell->parameters[ID::SET_POLARITY] = set_polarity;
2195         cell->parameters[ID::CLR_POLARITY] = clr_polarity;
2196         cell->parameters[ID::WIDTH] = sig_q.size();
2197         cell->setPort(ID::SET, sig_set);
2198         cell->setPort(ID::CLR, sig_clr);
2199         cell->setPort(ID::Q, sig_q);
2200         cell->set_src_attribute(src);
2201         return cell;
2202 }
2203
2204 RTLIL::Cell* RTLIL::Module::addFf(RTLIL::IdString name, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const std::string &src)
2205 {
2206         RTLIL::Cell *cell = addCell(name, ID($ff));
2207         cell->parameters[ID::WIDTH] = sig_q.size();
2208         cell->setPort(ID::D, sig_d);
2209         cell->setPort(ID::Q, sig_q);
2210         cell->set_src_attribute(src);
2211         return cell;
2212 }
2213
2214 RTLIL::Cell* RTLIL::Module::addDff(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, const std::string &src)
2215 {
2216         RTLIL::Cell *cell = addCell(name, ID($dff));
2217         cell->parameters[ID::CLK_POLARITY] = clk_polarity;
2218         cell->parameters[ID::WIDTH] = sig_q.size();
2219         cell->setPort(ID::CLK, sig_clk);
2220         cell->setPort(ID::D, sig_d);
2221         cell->setPort(ID::Q, sig_q);
2222         cell->set_src_attribute(src);
2223         return cell;
2224 }
2225
2226 RTLIL::Cell* RTLIL::Module::addDffe(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, bool en_polarity, const std::string &src)
2227 {
2228         RTLIL::Cell *cell = addCell(name, ID($dffe));
2229         cell->parameters[ID::CLK_POLARITY] = clk_polarity;
2230         cell->parameters[ID::EN_POLARITY] = en_polarity;
2231         cell->parameters[ID::WIDTH] = sig_q.size();
2232         cell->setPort(ID::CLK, sig_clk);
2233         cell->setPort(ID::EN, sig_en);
2234         cell->setPort(ID::D, sig_d);
2235         cell->setPort(ID::Q, sig_q);
2236         cell->set_src_attribute(src);
2237         return cell;
2238 }
2239
2240 RTLIL::Cell* RTLIL::Module::addDffsr(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,
2241                 RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
2242 {
2243         RTLIL::Cell *cell = addCell(name, ID($dffsr));
2244         cell->parameters[ID::CLK_POLARITY] = clk_polarity;
2245         cell->parameters[ID::SET_POLARITY] = set_polarity;
2246         cell->parameters[ID::CLR_POLARITY] = clr_polarity;
2247         cell->parameters[ID::WIDTH] = sig_q.size();
2248         cell->setPort(ID::CLK, sig_clk);
2249         cell->setPort(ID::SET, sig_set);
2250         cell->setPort(ID::CLR, sig_clr);
2251         cell->setPort(ID::D, sig_d);
2252         cell->setPort(ID::Q, sig_q);
2253         cell->set_src_attribute(src);
2254         return cell;
2255 }
2256
2257 RTLIL::Cell* RTLIL::Module::addAdff(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
2258                 RTLIL::Const arst_value, bool clk_polarity, bool arst_polarity, const std::string &src)
2259 {
2260         RTLIL::Cell *cell = addCell(name, ID($adff));
2261         cell->parameters[ID::CLK_POLARITY] = clk_polarity;
2262         cell->parameters[ID::ARST_POLARITY] = arst_polarity;
2263         cell->parameters[ID::ARST_VALUE] = arst_value;
2264         cell->parameters[ID::WIDTH] = sig_q.size();
2265         cell->setPort(ID::CLK, sig_clk);
2266         cell->setPort(ID::ARST, sig_arst);
2267         cell->setPort(ID::D, sig_d);
2268         cell->setPort(ID::Q, sig_q);
2269         cell->set_src_attribute(src);
2270         return cell;
2271 }
2272
2273 RTLIL::Cell* RTLIL::Module::addDlatch(RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity, const std::string &src)
2274 {
2275         RTLIL::Cell *cell = addCell(name, ID($dlatch));
2276         cell->parameters[ID::EN_POLARITY] = en_polarity;
2277         cell->parameters[ID::WIDTH] = sig_q.size();
2278         cell->setPort(ID::EN, sig_en);
2279         cell->setPort(ID::D, sig_d);
2280         cell->setPort(ID::Q, sig_q);
2281         cell->set_src_attribute(src);
2282         return cell;
2283 }
2284
2285 RTLIL::Cell* RTLIL::Module::addDlatchsr(RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,
2286                 RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
2287 {
2288         RTLIL::Cell *cell = addCell(name, ID($dlatchsr));
2289         cell->parameters[ID::EN_POLARITY] = en_polarity;
2290         cell->parameters[ID::SET_POLARITY] = set_polarity;
2291         cell->parameters[ID::CLR_POLARITY] = clr_polarity;
2292         cell->parameters[ID::WIDTH] = sig_q.size();
2293         cell->setPort(ID::EN, sig_en);
2294         cell->setPort(ID::SET, sig_set);
2295         cell->setPort(ID::CLR, sig_clr);
2296         cell->setPort(ID::D, sig_d);
2297         cell->setPort(ID::Q, sig_q);
2298         cell->set_src_attribute(src);
2299         return cell;
2300 }
2301
2302 RTLIL::Cell* RTLIL::Module::addFfGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const std::string &src)
2303 {
2304         RTLIL::Cell *cell = addCell(name, ID($_FF_));
2305         cell->setPort(ID::D, sig_d);
2306         cell->setPort(ID::Q, sig_q);
2307         cell->set_src_attribute(src);
2308         return cell;
2309 }
2310
2311 RTLIL::Cell* RTLIL::Module::addDffGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, const std::string &src)
2312 {
2313         RTLIL::Cell *cell = addCell(name, stringf("$_DFF_%c_", clk_polarity ? 'P' : 'N'));
2314         cell->setPort(ID::C, sig_clk);
2315         cell->setPort(ID::D, sig_d);
2316         cell->setPort(ID::Q, sig_q);
2317         cell->set_src_attribute(src);
2318         return cell;
2319 }
2320
2321 RTLIL::Cell* RTLIL::Module::addDffeGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, bool en_polarity, const std::string &src)
2322 {
2323         RTLIL::Cell *cell = addCell(name, stringf("$_DFFE_%c%c_", clk_polarity ? 'P' : 'N', en_polarity ? 'P' : 'N'));
2324         cell->setPort(ID::C, sig_clk);
2325         cell->setPort(ID::E, sig_en);
2326         cell->setPort(ID::D, sig_d);
2327         cell->setPort(ID::Q, sig_q);
2328         cell->set_src_attribute(src);
2329         return cell;
2330 }
2331
2332 RTLIL::Cell* RTLIL::Module::addDffsrGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,
2333                 RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
2334 {
2335         RTLIL::Cell *cell = addCell(name, stringf("$_DFFSR_%c%c%c_", clk_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N'));
2336         cell->setPort(ID::C, sig_clk);
2337         cell->setPort(ID::S, sig_set);
2338         cell->setPort(ID::R, sig_clr);
2339         cell->setPort(ID::D, sig_d);
2340         cell->setPort(ID::Q, sig_q);
2341         cell->set_src_attribute(src);
2342         return cell;
2343 }
2344
2345 RTLIL::Cell* RTLIL::Module::addAdffGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
2346                 bool arst_value, bool clk_polarity, bool arst_polarity, const std::string &src)
2347 {
2348         RTLIL::Cell *cell = addCell(name, stringf("$_DFF_%c%c%c_", clk_polarity ? 'P' : 'N', arst_polarity ? 'P' : 'N', arst_value ? '1' : '0'));
2349         cell->setPort(ID::C, sig_clk);
2350         cell->setPort(ID::R, sig_arst);
2351         cell->setPort(ID::D, sig_d);
2352         cell->setPort(ID::Q, sig_q);
2353         cell->set_src_attribute(src);
2354         return cell;
2355 }
2356
2357 RTLIL::Cell* RTLIL::Module::addDlatchGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity, const std::string &src)
2358 {
2359         RTLIL::Cell *cell = addCell(name, stringf("$_DLATCH_%c_", en_polarity ? 'P' : 'N'));
2360         cell->setPort(ID::E, sig_en);
2361         cell->setPort(ID::D, sig_d);
2362         cell->setPort(ID::Q, sig_q);
2363         cell->set_src_attribute(src);
2364         return cell;
2365 }
2366
2367 RTLIL::Cell* RTLIL::Module::addDlatchsrGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,
2368                 RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
2369 {
2370         RTLIL::Cell *cell = addCell(name, stringf("$_DLATCHSR_%c%c%c_", en_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N'));
2371         cell->setPort(ID::E, sig_en);
2372         cell->setPort(ID::S, sig_set);
2373         cell->setPort(ID::R, sig_clr);
2374         cell->setPort(ID::D, sig_d);
2375         cell->setPort(ID::Q, sig_q);
2376         cell->set_src_attribute(src);
2377         return cell;
2378 }
2379
2380 RTLIL::SigSpec RTLIL::Module::Anyconst(RTLIL::IdString name, int width, const std::string &src)
2381 {
2382         RTLIL::SigSpec sig = addWire(NEW_ID, width);
2383         Cell *cell = addCell(name, ID($anyconst));
2384         cell->setParam(ID::WIDTH, width);
2385         cell->setPort(ID::Y, sig);
2386         cell->set_src_attribute(src);
2387         return sig;
2388 }
2389
2390 RTLIL::SigSpec RTLIL::Module::Anyseq(RTLIL::IdString name, int width, const std::string &src)
2391 {
2392         RTLIL::SigSpec sig = addWire(NEW_ID, width);
2393         Cell *cell = addCell(name, ID($anyseq));
2394         cell->setParam(ID::WIDTH, width);
2395         cell->setPort(ID::Y, sig);
2396         cell->set_src_attribute(src);
2397         return sig;
2398 }
2399
2400 RTLIL::SigSpec RTLIL::Module::Allconst(RTLIL::IdString name, int width, const std::string &src)
2401 {
2402         RTLIL::SigSpec sig = addWire(NEW_ID, width);
2403         Cell *cell = addCell(name, ID($allconst));
2404         cell->setParam(ID::WIDTH, width);
2405         cell->setPort(ID::Y, sig);
2406         cell->set_src_attribute(src);
2407         return sig;
2408 }
2409
2410 RTLIL::SigSpec RTLIL::Module::Allseq(RTLIL::IdString name, int width, const std::string &src)
2411 {
2412         RTLIL::SigSpec sig = addWire(NEW_ID, width);
2413         Cell *cell = addCell(name, ID($allseq));
2414         cell->setParam(ID::WIDTH, width);
2415         cell->setPort(ID::Y, sig);
2416         cell->set_src_attribute(src);
2417         return sig;
2418 }
2419
2420 RTLIL::SigSpec RTLIL::Module::Initstate(RTLIL::IdString name, const std::string &src)
2421 {
2422         RTLIL::SigSpec sig = addWire(NEW_ID);
2423         Cell *cell = addCell(name, ID($initstate));
2424         cell->setPort(ID::Y, sig);
2425         cell->set_src_attribute(src);
2426         return sig;
2427 }
2428
2429 RTLIL::Wire::Wire()
2430 {
2431         static unsigned int hashidx_count = 123456789;
2432         hashidx_count = mkhash_xorshift(hashidx_count);
2433         hashidx_ = hashidx_count;
2434
2435         module = nullptr;
2436         width = 1;
2437         start_offset = 0;
2438         port_id = 0;
2439         port_input = false;
2440         port_output = false;
2441         upto = false;
2442
2443 #ifdef WITH_PYTHON
2444         RTLIL::Wire::get_all_wires()->insert(std::pair<unsigned int, RTLIL::Wire*>(hashidx_, this));
2445 #endif
2446 }
2447
2448 RTLIL::Wire::~Wire()
2449 {
2450 #ifdef WITH_PYTHON
2451         RTLIL::Wire::get_all_wires()->erase(hashidx_);
2452 #endif
2453 }
2454
2455 #ifdef WITH_PYTHON
2456 static std::map<unsigned int, RTLIL::Wire*> all_wires;
2457 std::map<unsigned int, RTLIL::Wire*> *RTLIL::Wire::get_all_wires(void)
2458 {
2459         return &all_wires;
2460 }
2461 #endif
2462
2463 RTLIL::Memory::Memory()
2464 {
2465         static unsigned int hashidx_count = 123456789;
2466         hashidx_count = mkhash_xorshift(hashidx_count);
2467         hashidx_ = hashidx_count;
2468
2469         width = 1;
2470         start_offset = 0;
2471         size = 0;
2472 #ifdef WITH_PYTHON
2473         RTLIL::Memory::get_all_memorys()->insert(std::pair<unsigned int, RTLIL::Memory*>(hashidx_, this));
2474 #endif
2475 }
2476
2477 RTLIL::Cell::Cell() : module(nullptr)
2478 {
2479         static unsigned int hashidx_count = 123456789;
2480         hashidx_count = mkhash_xorshift(hashidx_count);
2481         hashidx_ = hashidx_count;
2482
2483         // log("#memtrace# %p\n", this);
2484         memhasher();
2485
2486 #ifdef WITH_PYTHON
2487         RTLIL::Cell::get_all_cells()->insert(std::pair<unsigned int, RTLIL::Cell*>(hashidx_, this));
2488 #endif
2489 }
2490
2491 RTLIL::Cell::~Cell()
2492 {
2493 #ifdef WITH_PYTHON
2494         RTLIL::Cell::get_all_cells()->erase(hashidx_);
2495 #endif
2496 }
2497
2498 #ifdef WITH_PYTHON
2499 static std::map<unsigned int, RTLIL::Cell*> all_cells;
2500 std::map<unsigned int, RTLIL::Cell*> *RTLIL::Cell::get_all_cells(void)
2501 {
2502         return &all_cells;
2503 }
2504 #endif
2505
2506 bool RTLIL::Cell::hasPort(RTLIL::IdString portname) const
2507 {
2508         return connections_.count(portname) != 0;
2509 }
2510
2511 void RTLIL::Cell::unsetPort(RTLIL::IdString portname)
2512 {
2513         RTLIL::SigSpec signal;
2514         auto conn_it = connections_.find(portname);
2515
2516         if (conn_it != connections_.end())
2517         {
2518                 for (auto mon : module->monitors)
2519                         mon->notify_connect(this, conn_it->first, conn_it->second, signal);
2520
2521                 if (module->design)
2522                         for (auto mon : module->design->monitors)
2523                                 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
2524
2525                 if (yosys_xtrace) {
2526                         log("#X# Unconnect %s.%s.%s\n", log_id(this->module), log_id(this), log_id(portname));
2527                         log_backtrace("-X- ", yosys_xtrace-1);
2528                 }
2529
2530                 connections_.erase(conn_it);
2531         }
2532 }
2533
2534 void RTLIL::Cell::setPort(RTLIL::IdString portname, RTLIL::SigSpec signal)
2535 {
2536         auto r = connections_.insert(portname);
2537         auto conn_it = r.first;
2538         if (!r.second && conn_it->second == signal)
2539                 return;
2540
2541         for (auto mon : module->monitors)
2542                 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
2543
2544         if (module->design)
2545                 for (auto mon : module->design->monitors)
2546                         mon->notify_connect(this, conn_it->first, conn_it->second, signal);
2547
2548         if (yosys_xtrace) {
2549                 log("#X# Connect %s.%s.%s = %s (%d)\n", log_id(this->module), log_id(this), log_id(portname), log_signal(signal), GetSize(signal));
2550                 log_backtrace("-X- ", yosys_xtrace-1);
2551         }
2552
2553         conn_it->second = std::move(signal);
2554 }
2555
2556 const RTLIL::SigSpec &RTLIL::Cell::getPort(RTLIL::IdString portname) const
2557 {
2558         return connections_.at(portname);
2559 }
2560
2561 const dict<RTLIL::IdString, RTLIL::SigSpec> &RTLIL::Cell::connections() const
2562 {
2563         return connections_;
2564 }
2565
2566 bool RTLIL::Cell::known() const
2567 {
2568         if (yosys_celltypes.cell_known(type))
2569                 return true;
2570         if (module && module->design && module->design->module(type))
2571                 return true;
2572         return false;
2573 }
2574
2575 bool RTLIL::Cell::input(RTLIL::IdString portname) const
2576 {
2577         if (yosys_celltypes.cell_known(type))
2578                 return yosys_celltypes.cell_input(type, portname);
2579         if (module && module->design) {
2580                 RTLIL::Module *m = module->design->module(type);
2581                 RTLIL::Wire *w = m ? m->wire(portname) : nullptr;
2582                 return w && w->port_input;
2583         }
2584         return false;
2585 }
2586
2587 bool RTLIL::Cell::output(RTLIL::IdString portname) const
2588 {
2589         if (yosys_celltypes.cell_known(type))
2590                 return yosys_celltypes.cell_output(type, portname);
2591         if (module && module->design) {
2592                 RTLIL::Module *m = module->design->module(type);
2593                 RTLIL::Wire *w = m ? m->wire(portname) : nullptr;
2594                 return w && w->port_output;
2595         }
2596         return false;
2597 }
2598
2599 bool RTLIL::Cell::hasParam(RTLIL::IdString paramname) const
2600 {
2601         return parameters.count(paramname) != 0;
2602 }
2603
2604 void RTLIL::Cell::unsetParam(RTLIL::IdString paramname)
2605 {
2606         parameters.erase(paramname);
2607 }
2608
2609 void RTLIL::Cell::setParam(RTLIL::IdString paramname, RTLIL::Const value)
2610 {
2611         parameters[paramname] = std::move(value);
2612 }
2613
2614 const RTLIL::Const &RTLIL::Cell::getParam(RTLIL::IdString paramname) const
2615 {
2616         return parameters.at(paramname);
2617 }
2618
2619 void RTLIL::Cell::sort()
2620 {
2621         connections_.sort(sort_by_id_str());
2622         parameters.sort(sort_by_id_str());
2623         attributes.sort(sort_by_id_str());
2624 }
2625
2626 void RTLIL::Cell::check()
2627 {
2628 #ifndef NDEBUG
2629         InternalCellChecker checker(NULL, this);
2630         checker.check();
2631 #endif
2632 }
2633
2634 void RTLIL::Cell::fixup_parameters(bool set_a_signed, bool set_b_signed)
2635 {
2636         if (!type.begins_with("$") || type.begins_with("$_") || type.begins_with("$paramod") || type.begins_with("$fmcombine") ||
2637                         type.begins_with("$verific$") || type.begins_with("$array:") || type.begins_with("$extern:"))
2638                 return;
2639
2640         if (type == ID($mux) || type == ID($pmux)) {
2641                 parameters[ID::WIDTH] = GetSize(connections_[ID::Y]);
2642                 if (type == ID($pmux))
2643                         parameters[ID::S_WIDTH] = GetSize(connections_[ID::S]);
2644                 check();
2645                 return;
2646         }
2647
2648         if (type == ID($lut) || type == ID($sop)) {
2649                 parameters[ID::WIDTH] = GetSize(connections_[ID::A]);
2650                 return;
2651         }
2652
2653         if (type == ID($fa)) {
2654                 parameters[ID::WIDTH] = GetSize(connections_[ID::Y]);
2655                 return;
2656         }
2657
2658         if (type == ID($lcu)) {
2659                 parameters[ID::WIDTH] = GetSize(connections_[ID::CO]);
2660                 return;
2661         }
2662
2663         bool signedness_ab = !type.in(ID($slice), ID($concat), ID($macc));
2664
2665         if (connections_.count(ID::A)) {
2666                 if (signedness_ab) {
2667                         if (set_a_signed)
2668                                 parameters[ID::A_SIGNED] = true;
2669                         else if (parameters.count(ID::A_SIGNED) == 0)
2670                                 parameters[ID::A_SIGNED] = false;
2671                 }
2672                 parameters[ID::A_WIDTH] = GetSize(connections_[ID::A]);
2673         }
2674
2675         if (connections_.count(ID::B)) {
2676                 if (signedness_ab) {
2677                         if (set_b_signed)
2678                                 parameters[ID::B_SIGNED] = true;
2679                         else if (parameters.count(ID::B_SIGNED) == 0)
2680                                 parameters[ID::B_SIGNED] = false;
2681                 }
2682                 parameters[ID::B_WIDTH] = GetSize(connections_[ID::B]);
2683         }
2684
2685         if (connections_.count(ID::Y))
2686                 parameters[ID::Y_WIDTH] = GetSize(connections_[ID::Y]);
2687
2688         if (connections_.count(ID::Q))
2689                 parameters[ID::WIDTH] = GetSize(connections_[ID::Q]);
2690
2691         check();
2692 }
2693
2694 RTLIL::SigChunk::SigChunk()
2695 {
2696         wire = NULL;
2697         width = 0;
2698         offset = 0;
2699 }
2700
2701 RTLIL::SigChunk::SigChunk(const RTLIL::Const &value)
2702 {
2703         wire = NULL;
2704         data = value.bits;
2705         width = GetSize(data);
2706         offset = 0;
2707 }
2708
2709 RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire)
2710 {
2711         log_assert(wire != nullptr);
2712         this->wire = wire;
2713         this->width = wire->width;
2714         this->offset = 0;
2715 }
2716
2717 RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire, int offset, int width)
2718 {
2719         log_assert(wire != nullptr);
2720         this->wire = wire;
2721         this->width = width;
2722         this->offset = offset;
2723 }
2724
2725 RTLIL::SigChunk::SigChunk(const std::string &str)
2726 {
2727         wire = NULL;
2728         data = RTLIL::Const(str).bits;
2729         width = GetSize(data);
2730         offset = 0;
2731 }
2732
2733 RTLIL::SigChunk::SigChunk(int val, int width)
2734 {
2735         wire = NULL;
2736         data = RTLIL::Const(val, width).bits;
2737         this->width = GetSize(data);
2738         offset = 0;
2739 }
2740
2741 RTLIL::SigChunk::SigChunk(RTLIL::State bit, int width)
2742 {
2743         wire = NULL;
2744         data = RTLIL::Const(bit, width).bits;
2745         this->width = GetSize(data);
2746         offset = 0;
2747 }
2748
2749 RTLIL::SigChunk::SigChunk(const RTLIL::SigBit &bit)
2750 {
2751         wire = bit.wire;
2752         offset = 0;
2753         if (wire == NULL)
2754                 data = RTLIL::Const(bit.data).bits;
2755         else
2756                 offset = bit.offset;
2757         width = 1;
2758 }
2759
2760 RTLIL::SigChunk::SigChunk(const RTLIL::SigChunk &sigchunk)
2761 {
2762         *this = sigchunk;
2763 }
2764
2765 RTLIL::SigChunk RTLIL::SigChunk::extract(int offset, int length) const
2766 {
2767         RTLIL::SigChunk ret;
2768         if (wire) {
2769                 ret.wire = wire;
2770                 ret.offset = this->offset + offset;
2771                 ret.width = length;
2772         } else {
2773                 for (int i = 0; i < length; i++)
2774                         ret.data.push_back(data[offset+i]);
2775                 ret.width = length;
2776         }
2777         return ret;
2778 }
2779
2780 bool RTLIL::SigChunk::operator <(const RTLIL::SigChunk &other) const
2781 {
2782         if (wire && other.wire)
2783                 if (wire->name != other.wire->name)
2784                         return wire->name < other.wire->name;
2785
2786         if (wire != other.wire)
2787                 return wire < other.wire;
2788
2789         if (offset != other.offset)
2790                 return offset < other.offset;
2791
2792         if (width != other.width)
2793                 return width < other.width;
2794
2795         return data < other.data;
2796 }
2797
2798 bool RTLIL::SigChunk::operator ==(const RTLIL::SigChunk &other) const
2799 {
2800         return wire == other.wire && width == other.width && offset == other.offset && data == other.data;
2801 }
2802
2803 bool RTLIL::SigChunk::operator !=(const RTLIL::SigChunk &other) const
2804 {
2805         if (*this == other)
2806                 return false;
2807         return true;
2808 }
2809
2810 RTLIL::SigSpec::SigSpec()
2811 {
2812         width_ = 0;
2813         hash_ = 0;
2814 }
2815
2816 RTLIL::SigSpec::SigSpec(const RTLIL::SigSpec &other)
2817 {
2818         *this = other;
2819 }
2820
2821 RTLIL::SigSpec::SigSpec(std::initializer_list<RTLIL::SigSpec> parts)
2822 {
2823         cover("kernel.rtlil.sigspec.init.list");
2824
2825         width_ = 0;
2826         hash_ = 0;
2827
2828         log_assert(parts.size() > 0);
2829         auto ie = parts.begin();
2830         auto it = ie + parts.size() - 1;
2831         while (it >= ie)
2832                 append(*it--);
2833 }
2834
2835 RTLIL::SigSpec &RTLIL::SigSpec::operator=(const RTLIL::SigSpec &other)
2836 {
2837         cover("kernel.rtlil.sigspec.assign");
2838
2839         width_ = other.width_;
2840         hash_ = other.hash_;
2841         chunks_ = other.chunks_;
2842         bits_ = other.bits_;
2843         return *this;
2844 }
2845
2846 RTLIL::SigSpec::SigSpec(const RTLIL::Const &value)
2847 {
2848         cover("kernel.rtlil.sigspec.init.const");
2849
2850         chunks_.emplace_back(value);
2851         width_ = chunks_.back().width;
2852         hash_ = 0;
2853         check();
2854 }
2855
2856 RTLIL::SigSpec::SigSpec(const RTLIL::SigChunk &chunk)
2857 {
2858         cover("kernel.rtlil.sigspec.init.chunk");
2859
2860         chunks_.emplace_back(chunk);
2861         width_ = chunks_.back().width;
2862         hash_ = 0;
2863         check();
2864 }
2865
2866 RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire)
2867 {
2868         cover("kernel.rtlil.sigspec.init.wire");
2869
2870         chunks_.emplace_back(wire);
2871         width_ = chunks_.back().width;
2872         hash_ = 0;
2873         check();
2874 }
2875
2876 RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire, int offset, int width)
2877 {
2878         cover("kernel.rtlil.sigspec.init.wire_part");
2879
2880         chunks_.emplace_back(wire, offset, width);
2881         width_ = chunks_.back().width;
2882         hash_ = 0;
2883         check();
2884 }
2885
2886 RTLIL::SigSpec::SigSpec(const std::string &str)
2887 {
2888         cover("kernel.rtlil.sigspec.init.str");
2889
2890         chunks_.emplace_back(str);
2891         width_ = chunks_.back().width;
2892         hash_ = 0;
2893         check();
2894 }
2895
2896 RTLIL::SigSpec::SigSpec(int val, int width)
2897 {
2898         cover("kernel.rtlil.sigspec.init.int");
2899
2900         chunks_.emplace_back(val, width);
2901         width_ = width;
2902         hash_ = 0;
2903         check();
2904 }
2905
2906 RTLIL::SigSpec::SigSpec(RTLIL::State bit, int width)
2907 {
2908         cover("kernel.rtlil.sigspec.init.state");
2909
2910         chunks_.emplace_back(bit, width);
2911         width_ = width;
2912         hash_ = 0;
2913         check();
2914 }
2915
2916 RTLIL::SigSpec::SigSpec(const RTLIL::SigBit &bit, int width)
2917 {
2918         cover("kernel.rtlil.sigspec.init.bit");
2919
2920         if (bit.wire == NULL)
2921                 chunks_.emplace_back(bit.data, width);
2922         else
2923                 for (int i = 0; i < width; i++)
2924                         chunks_.push_back(bit);
2925         width_ = width;
2926         hash_ = 0;
2927         check();
2928 }
2929
2930 RTLIL::SigSpec::SigSpec(const std::vector<RTLIL::SigChunk> &chunks)
2931 {
2932         cover("kernel.rtlil.sigspec.init.stdvec_chunks");
2933
2934         width_ = 0;
2935         hash_ = 0;
2936         for (const auto &c : chunks)
2937                 append(c);
2938         check();
2939 }
2940
2941 RTLIL::SigSpec::SigSpec(const std::vector<RTLIL::SigBit> &bits)
2942 {
2943         cover("kernel.rtlil.sigspec.init.stdvec_bits");
2944
2945         width_ = 0;
2946         hash_ = 0;
2947         for (const auto &bit : bits)
2948                 append(bit);
2949         check();
2950 }
2951
2952 RTLIL::SigSpec::SigSpec(const pool<RTLIL::SigBit> &bits)
2953 {
2954         cover("kernel.rtlil.sigspec.init.pool_bits");
2955
2956         width_ = 0;
2957         hash_ = 0;
2958         for (const auto &bit : bits)
2959                 append(bit);
2960         check();
2961 }
2962
2963 RTLIL::SigSpec::SigSpec(const std::set<RTLIL::SigBit> &bits)
2964 {
2965         cover("kernel.rtlil.sigspec.init.stdset_bits");
2966
2967         width_ = 0;
2968         hash_ = 0;
2969         for (const auto &bit : bits)
2970                 append(bit);
2971         check();
2972 }
2973
2974 RTLIL::SigSpec::SigSpec(bool bit)
2975 {
2976         cover("kernel.rtlil.sigspec.init.bool");
2977
2978         width_ = 0;
2979         hash_ = 0;
2980         append(SigBit(bit));
2981         check();
2982 }
2983
2984 void RTLIL::SigSpec::pack() const
2985 {
2986         RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
2987
2988         if (that->bits_.empty())
2989                 return;
2990
2991         cover("kernel.rtlil.sigspec.convert.pack");
2992         log_assert(that->chunks_.empty());
2993
2994         std::vector<RTLIL::SigBit> old_bits;
2995         old_bits.swap(that->bits_);
2996
2997         RTLIL::SigChunk *last = NULL;
2998         int last_end_offset = 0;
2999
3000         for (auto &bit : old_bits) {
3001                 if (last && bit.wire == last->wire) {
3002                         if (bit.wire == NULL) {
3003                                 last->data.push_back(bit.data);
3004                                 last->width++;
3005                                 continue;
3006                         } else if (last_end_offset == bit.offset) {
3007                                 last_end_offset++;
3008                                 last->width++;
3009                                 continue;
3010                         }
3011                 }
3012                 that->chunks_.push_back(bit);
3013                 last = &that->chunks_.back();
3014                 last_end_offset = bit.offset + 1;
3015         }
3016
3017         check();
3018 }
3019
3020 void RTLIL::SigSpec::unpack() const
3021 {
3022         RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
3023
3024         if (that->chunks_.empty())
3025                 return;
3026
3027         cover("kernel.rtlil.sigspec.convert.unpack");
3028         log_assert(that->bits_.empty());
3029
3030         that->bits_.reserve(that->width_);
3031         for (auto &c : that->chunks_)
3032                 for (int i = 0; i < c.width; i++)
3033                         that->bits_.emplace_back(c, i);
3034
3035         that->chunks_.clear();
3036         that->hash_ = 0;
3037 }
3038
3039 void RTLIL::SigSpec::updhash() const
3040 {
3041         RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
3042
3043         if (that->hash_ != 0)
3044                 return;
3045
3046         cover("kernel.rtlil.sigspec.hash");
3047         that->pack();
3048
3049         that->hash_ = mkhash_init;
3050         for (auto &c : that->chunks_)
3051                 if (c.wire == NULL) {
3052                         for (auto &v : c.data)
3053                                 that->hash_ = mkhash(that->hash_, v);
3054                 } else {
3055                         that->hash_ = mkhash(that->hash_, c.wire->name.index_);
3056                         that->hash_ = mkhash(that->hash_, c.offset);
3057                         that->hash_ = mkhash(that->hash_, c.width);
3058                 }
3059
3060         if (that->hash_ == 0)
3061                 that->hash_ = 1;
3062 }
3063
3064 void RTLIL::SigSpec::sort()
3065 {
3066         unpack();
3067         cover("kernel.rtlil.sigspec.sort");
3068         std::sort(bits_.begin(), bits_.end());
3069 }
3070
3071 void RTLIL::SigSpec::sort_and_unify()
3072 {
3073         unpack();
3074         cover("kernel.rtlil.sigspec.sort_and_unify");
3075
3076         // A copy of the bits vector is used to prevent duplicating the logic from
3077         // SigSpec::SigSpec(std::vector<SigBit>).  This incurrs an extra copy but
3078         // that isn't showing up as significant in profiles.
3079         std::vector<SigBit> unique_bits = bits_;
3080         std::sort(unique_bits.begin(), unique_bits.end());
3081         auto last = std::unique(unique_bits.begin(), unique_bits.end());
3082         unique_bits.erase(last, unique_bits.end());
3083
3084         *this = unique_bits;
3085 }
3086
3087 void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with)
3088 {
3089         replace(pattern, with, this);
3090 }
3091
3092 void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with, RTLIL::SigSpec *other) const
3093 {
3094         log_assert(other != NULL);
3095         log_assert(width_ == other->width_);
3096         log_assert(pattern.width_ == with.width_);
3097
3098         pattern.unpack();
3099         with.unpack();
3100         unpack();
3101         other->unpack();
3102
3103         for (int i = 0; i < GetSize(pattern.bits_); i++) {
3104                 if (pattern.bits_[i].wire != NULL) {
3105                         for (int j = 0; j < GetSize(bits_); j++) {
3106                                 if (bits_[j] == pattern.bits_[i]) {
3107                                         other->bits_[j] = with.bits_[i];
3108                                 }
3109                         }
3110                 }
3111         }
3112
3113         other->check();
3114 }
3115
3116 void RTLIL::SigSpec::replace(const dict<RTLIL::SigBit, RTLIL::SigBit> &rules)
3117 {
3118         replace(rules, this);
3119 }
3120
3121 void RTLIL::SigSpec::replace(const dict<RTLIL::SigBit, RTLIL::SigBit> &rules, RTLIL::SigSpec *other) const
3122 {
3123         cover("kernel.rtlil.sigspec.replace_dict");
3124
3125         log_assert(other != NULL);
3126         log_assert(width_ == other->width_);
3127
3128         if (rules.empty()) return;
3129         unpack();
3130         other->unpack();
3131
3132         for (int i = 0; i < GetSize(bits_); i++) {
3133                 auto it = rules.find(bits_[i]);
3134                 if (it != rules.end())
3135                         other->bits_[i] = it->second;
3136         }
3137
3138         other->check();
3139 }
3140
3141 void RTLIL::SigSpec::replace(const std::map<RTLIL::SigBit, RTLIL::SigBit> &rules)
3142 {
3143         replace(rules, this);
3144 }
3145
3146 void RTLIL::SigSpec::replace(const std::map<RTLIL::SigBit, RTLIL::SigBit> &rules, RTLIL::SigSpec *other) const
3147 {
3148         cover("kernel.rtlil.sigspec.replace_map");
3149
3150         log_assert(other != NULL);
3151         log_assert(width_ == other->width_);
3152
3153         if (rules.empty()) return;
3154         unpack();
3155         other->unpack();
3156
3157         for (int i = 0; i < GetSize(bits_); i++) {
3158                 auto it = rules.find(bits_[i]);
3159                 if (it != rules.end())
3160                         other->bits_[i] = it->second;
3161         }
3162
3163         other->check();
3164 }
3165
3166 void RTLIL::SigSpec::remove(const RTLIL::SigSpec &pattern)
3167 {
3168         remove2(pattern, NULL);
3169 }
3170
3171 void RTLIL::SigSpec::remove(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other) const
3172 {
3173         RTLIL::SigSpec tmp = *this;
3174         tmp.remove2(pattern, other);
3175 }
3176
3177 void RTLIL::SigSpec::remove2(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other)
3178 {
3179         if (other)
3180                 cover("kernel.rtlil.sigspec.remove_other");
3181         else
3182                 cover("kernel.rtlil.sigspec.remove");
3183
3184         unpack();
3185         if (other != NULL) {
3186                 log_assert(width_ == other->width_);
3187                 other->unpack();
3188         }
3189
3190         for (int i = GetSize(bits_) - 1; i >= 0; i--)
3191         {
3192                 if (bits_[i].wire == NULL) continue;
3193
3194                 for (auto &pattern_chunk : pattern.chunks())
3195                         if (bits_[i].wire == pattern_chunk.wire &&
3196                                 bits_[i].offset >= pattern_chunk.offset &&
3197                                 bits_[i].offset < pattern_chunk.offset + pattern_chunk.width) {
3198                                 bits_.erase(bits_.begin() + i);
3199                                 width_--;
3200                                 if (other != NULL) {
3201                                         other->bits_.erase(other->bits_.begin() + i);
3202                                         other->width_--;
3203                                 }
3204                                 break;
3205                         }
3206         }
3207
3208         check();
3209 }
3210
3211 void RTLIL::SigSpec::remove(const pool<RTLIL::SigBit> &pattern)
3212 {
3213         remove2(pattern, NULL);
3214 }
3215
3216 void RTLIL::SigSpec::remove(const pool<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other) const
3217 {
3218         RTLIL::SigSpec tmp = *this;
3219         tmp.remove2(pattern, other);
3220 }
3221
3222 void RTLIL::SigSpec::remove2(const pool<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other)
3223 {
3224         if (other)
3225                 cover("kernel.rtlil.sigspec.remove_other");
3226         else
3227                 cover("kernel.rtlil.sigspec.remove");
3228
3229         unpack();
3230
3231         if (other != NULL) {
3232                 log_assert(width_ == other->width_);
3233                 other->unpack();
3234         }
3235
3236         for (int i = GetSize(bits_) - 1; i >= 0; i--) {
3237                 if (bits_[i].wire != NULL && pattern.count(bits_[i])) {
3238                         bits_.erase(bits_.begin() + i);
3239                         width_--;
3240                         if (other != NULL) {
3241                                 other->bits_.erase(other->bits_.begin() + i);
3242                                 other->width_--;
3243                         }
3244                 }
3245         }
3246
3247         check();
3248 }
3249
3250 void RTLIL::SigSpec::remove2(const std::set<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other)
3251 {
3252         if (other)
3253                 cover("kernel.rtlil.sigspec.remove_other");
3254         else
3255                 cover("kernel.rtlil.sigspec.remove");
3256
3257         unpack();
3258
3259         if (other != NULL) {
3260                 log_assert(width_ == other->width_);
3261                 other->unpack();
3262         }
3263
3264         for (int i = GetSize(bits_) - 1; i >= 0; i--) {
3265                 if (bits_[i].wire != NULL && pattern.count(bits_[i])) {
3266                         bits_.erase(bits_.begin() + i);
3267                         width_--;
3268                         if (other != NULL) {
3269                                 other->bits_.erase(other->bits_.begin() + i);
3270                                 other->width_--;
3271                         }
3272                 }
3273         }
3274
3275         check();
3276 }
3277
3278 RTLIL::SigSpec RTLIL::SigSpec::extract(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec *other) const
3279 {
3280         if (other)
3281                 cover("kernel.rtlil.sigspec.extract_other");
3282         else
3283                 cover("kernel.rtlil.sigspec.extract");
3284
3285         log_assert(other == NULL || width_ == other->width_);
3286
3287         RTLIL::SigSpec ret;
3288         std::vector<RTLIL::SigBit> bits_match = to_sigbit_vector();
3289
3290         for (auto& pattern_chunk : pattern.chunks()) {
3291                 if (other) {
3292                         std::vector<RTLIL::SigBit> bits_other = other->to_sigbit_vector();
3293                         for (int i = 0; i < width_; i++)
3294                                 if (bits_match[i].wire &&
3295                                         bits_match[i].wire == pattern_chunk.wire &&
3296                                         bits_match[i].offset >= pattern_chunk.offset &&
3297                                         bits_match[i].offset < pattern_chunk.offset + pattern_chunk.width)
3298                                         ret.append(bits_other[i]);
3299                 } else {
3300                         for (int i = 0; i < width_; i++)
3301                                 if (bits_match[i].wire &&
3302                                         bits_match[i].wire == pattern_chunk.wire &&
3303                                         bits_match[i].offset >= pattern_chunk.offset &&
3304                                         bits_match[i].offset < pattern_chunk.offset + pattern_chunk.width)
3305                                         ret.append(bits_match[i]);
3306                 }
3307         }
3308
3309         ret.check();
3310         return ret;
3311 }
3312
3313 RTLIL::SigSpec RTLIL::SigSpec::extract(const pool<RTLIL::SigBit> &pattern, const RTLIL::SigSpec *other) const
3314 {
3315         if (other)
3316                 cover("kernel.rtlil.sigspec.extract_other");
3317         else
3318                 cover("kernel.rtlil.sigspec.extract");
3319
3320         log_assert(other == NULL || width_ == other->width_);
3321
3322         std::vector<RTLIL::SigBit> bits_match = to_sigbit_vector();
3323         RTLIL::SigSpec ret;
3324
3325         if (other) {
3326                 std::vector<RTLIL::SigBit> bits_other = other->to_sigbit_vector();
3327                 for (int i = 0; i < width_; i++)
3328                         if (bits_match[i].wire && pattern.count(bits_match[i]))
3329                                 ret.append(bits_other[i]);
3330         } else {
3331                 for (int i = 0; i < width_; i++)
3332                         if (bits_match[i].wire && pattern.count(bits_match[i]))
3333                                 ret.append(bits_match[i]);
3334         }
3335
3336         ret.check();
3337         return ret;
3338 }
3339
3340 void RTLIL::SigSpec::replace(int offset, const RTLIL::SigSpec &with)
3341 {
3342         cover("kernel.rtlil.sigspec.replace_pos");
3343
3344         unpack();
3345         with.unpack();
3346
3347         log_assert(offset >= 0);
3348         log_assert(with.width_ >= 0);
3349         log_assert(offset+with.width_ <= width_);
3350
3351         for (int i = 0; i < with.width_; i++)
3352                 bits_.at(offset + i) = with.bits_.at(i);
3353
3354         check();
3355 }
3356
3357 void RTLIL::SigSpec::remove_const()
3358 {
3359         if (packed())
3360         {
3361                 cover("kernel.rtlil.sigspec.remove_const.packed");
3362
3363                 std::vector<RTLIL::SigChunk> new_chunks;
3364                 new_chunks.reserve(GetSize(chunks_));
3365
3366                 width_ = 0;
3367                 for (auto &chunk : chunks_)
3368                         if (chunk.wire != NULL) {
3369                                 new_chunks.push_back(chunk);
3370                                 width_ += chunk.width;
3371                         }
3372
3373                 chunks_.swap(new_chunks);
3374         }
3375         else
3376         {
3377                 cover("kernel.rtlil.sigspec.remove_const.unpacked");
3378
3379                 std::vector<RTLIL::SigBit> new_bits;
3380                 new_bits.reserve(width_);
3381
3382                 for (auto &bit : bits_)
3383                         if (bit.wire != NULL)
3384                                 new_bits.push_back(bit);
3385
3386                 bits_.swap(new_bits);
3387                 width_ = bits_.size();
3388         }
3389
3390         check();
3391 }
3392
3393 void RTLIL::SigSpec::remove(int offset, int length)
3394 {
3395         cover("kernel.rtlil.sigspec.remove_pos");
3396
3397         unpack();
3398
3399         log_assert(offset >= 0);
3400         log_assert(length >= 0);
3401         log_assert(offset + length <= width_);
3402
3403         bits_.erase(bits_.begin() + offset, bits_.begin() + offset + length);
3404         width_ = bits_.size();
3405
3406         check();
3407 }
3408
3409 RTLIL::SigSpec RTLIL::SigSpec::extract(int offset, int length) const
3410 {
3411         unpack();
3412         cover("kernel.rtlil.sigspec.extract_pos");
3413         return std::vector<RTLIL::SigBit>(bits_.begin() + offset, bits_.begin() + offset + length);
3414 }
3415
3416 void RTLIL::SigSpec::append(const RTLIL::SigSpec &signal)
3417 {
3418         if (signal.width_ == 0)
3419                 return;
3420
3421         if (width_ == 0) {
3422                 *this = signal;
3423                 return;
3424         }
3425
3426         cover("kernel.rtlil.sigspec.append");
3427
3428         if (packed() != signal.packed()) {
3429                 pack();
3430                 signal.pack();
3431         }
3432
3433         if (packed())
3434                 for (auto &other_c : signal.chunks_)
3435                 {
3436                         auto &my_last_c = chunks_.back();
3437                         if (my_last_c.wire == NULL && other_c.wire == NULL) {
3438                                 auto &this_data = my_last_c.data;
3439                                 auto &other_data = other_c.data;
3440                                 this_data.insert(this_data.end(), other_data.begin(), other_data.end());
3441                                 my_last_c.width += other_c.width;
3442                         } else
3443                         if (my_last_c.wire == other_c.wire && my_last_c.offset + my_last_c.width == other_c.offset) {
3444                                 my_last_c.width += other_c.width;
3445                         } else
3446                                 chunks_.push_back(other_c);
3447                 }
3448         else
3449                 bits_.insert(bits_.end(), signal.bits_.begin(), signal.bits_.end());
3450
3451         width_ += signal.width_;
3452         check();
3453 }
3454
3455 void RTLIL::SigSpec::append(const RTLIL::SigBit &bit)
3456 {
3457         if (packed())
3458         {
3459                 cover("kernel.rtlil.sigspec.append_bit.packed");
3460
3461                 if (chunks_.size() == 0)
3462                         chunks_.push_back(bit);
3463                 else
3464                         if (bit.wire == NULL)
3465                                 if (chunks_.back().wire == NULL) {
3466                                         chunks_.back().data.push_back(bit.data);
3467                                         chunks_.back().width++;
3468                                 } else
3469                                         chunks_.push_back(bit);
3470                         else
3471                                 if (chunks_.back().wire == bit.wire && chunks_.back().offset + chunks_.back().width == bit.offset)
3472                                         chunks_.back().width++;
3473                                 else
3474                                         chunks_.push_back(bit);
3475         }
3476         else
3477         {
3478                 cover("kernel.rtlil.sigspec.append_bit.unpacked");
3479                 bits_.push_back(bit);
3480         }
3481
3482         width_++;
3483         check();
3484 }
3485
3486 void RTLIL::SigSpec::extend_u0(int width, bool is_signed)
3487 {
3488         cover("kernel.rtlil.sigspec.extend_u0");
3489
3490         pack();
3491
3492         if (width_ > width)
3493                 remove(width, width_ - width);
3494
3495         if (width_ < width) {
3496                 RTLIL::SigBit padding = width_ > 0 ? (*this)[width_ - 1] : RTLIL::State::Sx;
3497                 if (!is_signed)
3498                         padding = RTLIL::State::S0;
3499                 while (width_ < width)
3500                         append(padding);
3501         }
3502
3503 }
3504
3505 RTLIL::SigSpec RTLIL::SigSpec::repeat(int num) const
3506 {
3507         cover("kernel.rtlil.sigspec.repeat");
3508
3509         RTLIL::SigSpec sig;
3510         for (int i = 0; i < num; i++)
3511                 sig.append(*this);
3512         return sig;
3513 }
3514
3515 #ifndef NDEBUG
3516 void RTLIL::SigSpec::check() const
3517 {
3518         if (width_ > 64)
3519         {
3520                 cover("kernel.rtlil.sigspec.check.skip");
3521         }
3522         else if (packed())
3523         {
3524                 cover("kernel.rtlil.sigspec.check.packed");
3525
3526                 int w = 0;
3527                 for (size_t i = 0; i < chunks_.size(); i++) {
3528                         const RTLIL::SigChunk &chunk = chunks_[i];
3529                         if (chunk.wire == NULL) {
3530                                 if (i > 0)
3531                                         log_assert(chunks_[i-1].wire != NULL);
3532                                 log_assert(chunk.offset == 0);
3533                                 log_assert(chunk.data.size() == (size_t)chunk.width);
3534                         } else {
3535                                 if (i > 0 && chunks_[i-1].wire == chunk.wire)
3536                                         log_assert(chunk.offset != chunks_[i-1].offset + chunks_[i-1].width);
3537                                 log_assert(chunk.offset >= 0);
3538                                 log_assert(chunk.width >= 0);
3539                                 log_assert(chunk.offset + chunk.width <= chunk.wire->width);
3540                                 log_assert(chunk.data.size() == 0);
3541                         }
3542                         w += chunk.width;
3543                 }
3544                 log_assert(w == width_);
3545                 log_assert(bits_.empty());
3546         }
3547         else
3548         {
3549                 cover("kernel.rtlil.sigspec.check.unpacked");
3550
3551                 log_assert(width_ == GetSize(bits_));
3552                 log_assert(chunks_.empty());
3553         }
3554 }
3555 #endif
3556
3557 bool RTLIL::SigSpec::operator <(const RTLIL::SigSpec &other) const
3558 {
3559         cover("kernel.rtlil.sigspec.comp_lt");
3560
3561         if (this == &other)
3562                 return false;
3563
3564         if (width_ != other.width_)
3565                 return width_ < other.width_;
3566
3567         pack();
3568         other.pack();
3569
3570         if (chunks_.size() != other.chunks_.size())
3571                 return chunks_.size() < other.chunks_.size();
3572
3573         updhash();
3574         other.updhash();
3575
3576         if (hash_ != other.hash_)
3577                 return hash_ < other.hash_;
3578
3579         for (size_t i = 0; i < chunks_.size(); i++)
3580                 if (chunks_[i] != other.chunks_[i]) {
3581                         cover("kernel.rtlil.sigspec.comp_lt.hash_collision");
3582                         return chunks_[i] < other.chunks_[i];
3583                 }
3584
3585         cover("kernel.rtlil.sigspec.comp_lt.equal");
3586         return false;
3587 }
3588
3589 bool RTLIL::SigSpec::operator ==(const RTLIL::SigSpec &other) const
3590 {
3591         cover("kernel.rtlil.sigspec.comp_eq");
3592
3593         if (this == &other)
3594                 return true;
3595
3596         if (width_ != other.width_)
3597                 return false;
3598
3599         // Without this, SigSpec() == SigSpec(State::S0, 0) will fail
3600         //   since the RHS will contain one SigChunk of width 0 causing
3601         //   the size check below to fail
3602         if (width_ == 0)
3603                 return true;
3604
3605         pack();
3606         other.pack();
3607
3608         if (chunks_.size() != other.chunks_.size())
3609                 return false;
3610
3611         updhash();
3612         other.updhash();
3613
3614         if (hash_ != other.hash_)
3615                 return false;
3616
3617         for (size_t i = 0; i < chunks_.size(); i++)
3618                 if (chunks_[i] != other.chunks_[i]) {
3619                         cover("kernel.rtlil.sigspec.comp_eq.hash_collision");
3620                         return false;
3621                 }
3622
3623         cover("kernel.rtlil.sigspec.comp_eq.equal");
3624         return true;
3625 }
3626
3627 bool RTLIL::SigSpec::is_wire() const
3628 {
3629         cover("kernel.rtlil.sigspec.is_wire");
3630
3631         pack();
3632         return GetSize(chunks_) == 1 && chunks_[0].wire && chunks_[0].wire->width == width_;
3633 }
3634
3635 bool RTLIL::SigSpec::is_chunk() const
3636 {
3637         cover("kernel.rtlil.sigspec.is_chunk");
3638
3639         pack();
3640         return GetSize(chunks_) == 1;
3641 }
3642
3643 bool RTLIL::SigSpec::is_fully_const() const
3644 {
3645         cover("kernel.rtlil.sigspec.is_fully_const");
3646
3647         pack();
3648         for (auto it = chunks_.begin(); it != chunks_.end(); it++)
3649                 if (it->width > 0 && it->wire != NULL)
3650                         return false;
3651         return true;
3652 }
3653
3654 bool RTLIL::SigSpec::is_fully_zero() const
3655 {
3656         cover("kernel.rtlil.sigspec.is_fully_zero");
3657
3658         pack();
3659         for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
3660                 if (it->width > 0 && it->wire != NULL)
3661                         return false;
3662                 for (size_t i = 0; i < it->data.size(); i++)
3663                         if (it->data[i] != RTLIL::State::S0)
3664                                 return false;
3665         }
3666         return true;
3667 }
3668
3669 bool RTLIL::SigSpec::is_fully_ones() const
3670 {
3671         cover("kernel.rtlil.sigspec.is_fully_ones");
3672
3673         pack();
3674         for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
3675                 if (it->width > 0 && it->wire != NULL)
3676                         return false;
3677                 for (size_t i = 0; i < it->data.size(); i++)
3678                         if (it->data[i] != RTLIL::State::S1)
3679                                 return false;
3680         }
3681         return true;
3682 }
3683
3684 bool RTLIL::SigSpec::is_fully_def() const
3685 {
3686         cover("kernel.rtlil.sigspec.is_fully_def");
3687
3688         pack();
3689         for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
3690                 if (it->width > 0 && it->wire != NULL)
3691                         return false;
3692                 for (size_t i = 0; i < it->data.size(); i++)
3693                         if (it->data[i] != RTLIL::State::S0 && it->data[i] != RTLIL::State::S1)
3694                                 return false;
3695         }
3696         return true;
3697 }
3698
3699 bool RTLIL::SigSpec::is_fully_undef() const
3700 {
3701         cover("kernel.rtlil.sigspec.is_fully_undef");
3702
3703         pack();
3704         for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
3705                 if (it->width > 0 && it->wire != NULL)
3706                         return false;
3707                 for (size_t i = 0; i < it->data.size(); i++)
3708                         if (it->data[i] != RTLIL::State::Sx && it->data[i] != RTLIL::State::Sz)
3709                                 return false;
3710         }
3711         return true;
3712 }
3713
3714 bool RTLIL::SigSpec::has_const() const
3715 {
3716         cover("kernel.rtlil.sigspec.has_const");
3717
3718         pack();
3719         for (auto it = chunks_.begin(); it != chunks_.end(); it++)
3720                 if (it->width > 0 && it->wire == NULL)
3721                         return true;
3722         return false;
3723 }
3724
3725 bool RTLIL::SigSpec::has_marked_bits() const
3726 {
3727         cover("kernel.rtlil.sigspec.has_marked_bits");
3728
3729         pack();
3730         for (auto it = chunks_.begin(); it != chunks_.end(); it++)
3731                 if (it->width > 0 && it->wire == NULL) {
3732                         for (size_t i = 0; i < it->data.size(); i++)
3733                                 if (it->data[i] == RTLIL::State::Sm)
3734                                         return true;
3735                 }
3736         return false;
3737 }
3738
3739 bool RTLIL::SigSpec::as_bool() const
3740 {
3741         cover("kernel.rtlil.sigspec.as_bool");
3742
3743         pack();
3744         log_assert(is_fully_const() && GetSize(chunks_) <= 1);
3745         if (width_)
3746                 return RTLIL::Const(chunks_[0].data).as_bool();
3747         return false;
3748 }
3749
3750 int RTLIL::SigSpec::as_int(bool is_signed) const
3751 {
3752         cover("kernel.rtlil.sigspec.as_int");
3753
3754         pack();
3755         log_assert(is_fully_const() && GetSize(chunks_) <= 1);
3756         if (width_)
3757                 return RTLIL::Const(chunks_[0].data).as_int(is_signed);
3758         return 0;
3759 }
3760
3761 std::string RTLIL::SigSpec::as_string() const
3762 {
3763         cover("kernel.rtlil.sigspec.as_string");
3764
3765         pack();
3766         std::string str;
3767         str.reserve(size());
3768         for (size_t i = chunks_.size(); i > 0; i--) {
3769                 const RTLIL::SigChunk &chunk = chunks_[i-1];
3770                 if (chunk.wire != NULL)
3771                         str.append(chunk.width, '?');
3772                 else
3773                         str += RTLIL::Const(chunk.data).as_string();
3774         }
3775         return str;
3776 }
3777
3778 RTLIL::Const RTLIL::SigSpec::as_const() const
3779 {
3780         cover("kernel.rtlil.sigspec.as_const");
3781
3782         pack();
3783         log_assert(is_fully_const() && GetSize(chunks_) <= 1);
3784         if (width_)
3785                 return chunks_[0].data;
3786         return RTLIL::Const();
3787 }
3788
3789 RTLIL::Wire *RTLIL::SigSpec::as_wire() const
3790 {
3791         cover("kernel.rtlil.sigspec.as_wire");
3792
3793         pack();
3794         log_assert(is_wire());
3795         return chunks_[0].wire;
3796 }
3797
3798 RTLIL::SigChunk RTLIL::SigSpec::as_chunk() const
3799 {
3800         cover("kernel.rtlil.sigspec.as_chunk");
3801
3802         pack();
3803         log_assert(is_chunk());
3804         return chunks_[0];
3805 }
3806
3807 RTLIL::SigBit RTLIL::SigSpec::as_bit() const
3808 {
3809         cover("kernel.rtlil.sigspec.as_bit");
3810
3811         log_assert(width_ == 1);
3812         if (packed())
3813                 return RTLIL::SigBit(*chunks_.begin());
3814         else
3815                 return bits_[0];
3816 }
3817
3818 bool RTLIL::SigSpec::match(const char* pattern) const
3819 {
3820         cover("kernel.rtlil.sigspec.match");
3821
3822         unpack();
3823         log_assert(int(strlen(pattern)) == GetSize(bits_));
3824
3825         for (auto it = bits_.rbegin(); it != bits_.rend(); it++, pattern++) {
3826                 if (*pattern == ' ')
3827                         continue;
3828                 if (*pattern == '*') {
3829                         if (*it != State::Sz && *it != State::Sx)
3830                                 return false;
3831                         continue;
3832                 }
3833                 if (*pattern == '0') {
3834                         if (*it != State::S0)
3835                                 return false;
3836                 } else
3837                 if (*pattern == '1') {
3838                         if (*it != State::S1)
3839                                 return false;
3840                 } else
3841                         log_abort();
3842         }
3843
3844         return true;
3845 }
3846
3847 std::set<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_set() const
3848 {
3849         cover("kernel.rtlil.sigspec.to_sigbit_set");
3850
3851         pack();
3852         std::set<RTLIL::SigBit> sigbits;
3853         for (auto &c : chunks_)
3854                 for (int i = 0; i < c.width; i++)
3855                         sigbits.insert(RTLIL::SigBit(c, i));
3856         return sigbits;
3857 }
3858
3859 pool<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_pool() const
3860 {
3861         cover("kernel.rtlil.sigspec.to_sigbit_pool");
3862
3863         pack();
3864         pool<RTLIL::SigBit> sigbits;
3865         sigbits.reserve(size());
3866         for (auto &c : chunks_)
3867                 for (int i = 0; i < c.width; i++)
3868                         sigbits.insert(RTLIL::SigBit(c, i));
3869         return sigbits;
3870 }
3871
3872 std::vector<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_vector() const
3873 {
3874         cover("kernel.rtlil.sigspec.to_sigbit_vector");
3875
3876         unpack();
3877         return bits_;
3878 }
3879
3880 std::map<RTLIL::SigBit, RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_map(const RTLIL::SigSpec &other) const
3881 {
3882         cover("kernel.rtlil.sigspec.to_sigbit_map");
3883
3884         unpack();
3885         other.unpack();
3886
3887         log_assert(width_ == other.width_);
3888
3889         std::map<RTLIL::SigBit, RTLIL::SigBit> new_map;
3890         for (int i = 0; i < width_; i++)
3891                 new_map[bits_[i]] = other.bits_[i];
3892
3893         return new_map;
3894 }
3895
3896 dict<RTLIL::SigBit, RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_dict(const RTLIL::SigSpec &other) const
3897 {
3898         cover("kernel.rtlil.sigspec.to_sigbit_dict");
3899
3900         unpack();
3901         other.unpack();
3902
3903         log_assert(width_ == other.width_);
3904
3905         dict<RTLIL::SigBit, RTLIL::SigBit> new_map;
3906         new_map.reserve(size());
3907         for (int i = 0; i < width_; i++)
3908                 new_map[bits_[i]] = other.bits_[i];
3909
3910         return new_map;
3911 }
3912
3913 static void sigspec_parse_split(std::vector<std::string> &tokens, const std::string &text, char sep)
3914 {
3915         size_t start = 0, end = 0;
3916         while ((end = text.find(sep, start)) != std::string::npos) {
3917                 tokens.push_back(text.substr(start, end - start));
3918                 start = end + 1;
3919         }
3920         tokens.push_back(text.substr(start));
3921 }
3922
3923 static int sigspec_parse_get_dummy_line_num()
3924 {
3925         return 0;
3926 }
3927
3928 bool RTLIL::SigSpec::parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str)
3929 {
3930         cover("kernel.rtlil.sigspec.parse");
3931
3932         AST::current_filename = "input";
3933
3934         std::vector<std::string> tokens;
3935         sigspec_parse_split(tokens, str, ',');
3936
3937         sig = RTLIL::SigSpec();
3938         for (int tokidx = int(tokens.size())-1; tokidx >= 0; tokidx--)
3939         {
3940                 std::string netname = tokens[tokidx];
3941                 std::string indices;
3942
3943                 if (netname.size() == 0)
3944                         continue;
3945
3946                 if (('0' <= netname[0] && netname[0] <= '9') || netname[0] == '\'') {
3947                         cover("kernel.rtlil.sigspec.parse.const");
3948                         AST::get_line_num = sigspec_parse_get_dummy_line_num;
3949                         AST::AstNode *ast = VERILOG_FRONTEND::const2ast(netname);
3950                         if (ast == NULL)
3951                                 return false;
3952                         sig.append(RTLIL::Const(ast->bits));
3953                         delete ast;
3954                         continue;
3955                 }
3956
3957                 if (module == NULL)
3958                         return false;
3959
3960                 cover("kernel.rtlil.sigspec.parse.net");
3961
3962                 if (netname[0] != '$' && netname[0] != '\\')
3963                         netname = "\\" + netname;
3964
3965                 if (module->wires_.count(netname) == 0) {
3966                         size_t indices_pos = netname.size()-1;
3967                         if (indices_pos > 2 && netname[indices_pos] == ']')
3968                         {
3969                                 indices_pos--;
3970                                 while (indices_pos > 0 && ('0' <= netname[indices_pos] && netname[indices_pos] <= '9')) indices_pos--;
3971                                 if (indices_pos > 0 && netname[indices_pos] == ':') {
3972                                         indices_pos--;
3973                                         while (indices_pos > 0 && ('0' <= netname[indices_pos] && netname[indices_pos] <= '9')) indices_pos--;
3974                                 }
3975                                 if (indices_pos > 0 && netname[indices_pos] == '[') {
3976                                         indices = netname.substr(indices_pos);
3977                                         netname = netname.substr(0, indices_pos);
3978                                 }
3979                         }
3980                 }
3981
3982                 if (module->wires_.count(netname) == 0)
3983                         return false;
3984
3985                 RTLIL::Wire *wire = module->wires_.at(netname);
3986                 if (!indices.empty()) {
3987                         std::vector<std::string> index_tokens;
3988                         sigspec_parse_split(index_tokens, indices.substr(1, indices.size()-2), ':');
3989                         if (index_tokens.size() == 1) {
3990                                 cover("kernel.rtlil.sigspec.parse.bit_sel");
3991                                 int a = atoi(index_tokens.at(0).c_str());
3992                                 if (a < 0 || a >= wire->width)
3993                                         return false;
3994                                 sig.append(RTLIL::SigSpec(wire, a));
3995                         } else {
3996                                 cover("kernel.rtlil.sigspec.parse.part_sel");
3997                                 int a = atoi(index_tokens.at(0).c_str());
3998                                 int b = atoi(index_tokens.at(1).c_str());
3999                                 if (a > b) {
4000                                         int tmp = a;
4001                                         a = b, b = tmp;
4002                                 }
4003                                 if (a < 0 || a >= wire->width)
4004                                         return false;
4005                                 if (b < 0 || b >= wire->width)
4006                                         return false;
4007                                 sig.append(RTLIL::SigSpec(wire, a, b-a+1));
4008                         }
4009                 } else
4010                         sig.append(wire);
4011         }
4012
4013         return true;
4014 }
4015
4016 bool RTLIL::SigSpec::parse_sel(RTLIL::SigSpec &sig, RTLIL::Design *design, RTLIL::Module *module, std::string str)
4017 {
4018         if (str.empty() || str[0] != '@')
4019                 return parse(sig, module, str);
4020
4021         cover("kernel.rtlil.sigspec.parse.sel");
4022
4023         str = RTLIL::escape_id(str.substr(1));
4024         if (design->selection_vars.count(str) == 0)
4025                 return false;
4026
4027         sig = RTLIL::SigSpec();
4028         RTLIL::Selection &sel = design->selection_vars.at(str);
4029         for (auto &it : module->wires_)
4030                 if (sel.selected_member(module->name, it.first))
4031                         sig.append(it.second);
4032
4033         return true;
4034 }
4035
4036 bool RTLIL::SigSpec::parse_rhs(const RTLIL::SigSpec &lhs, RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str)
4037 {
4038         if (str == "0") {
4039                 cover("kernel.rtlil.sigspec.parse.rhs_zeros");
4040                 sig = RTLIL::SigSpec(RTLIL::State::S0, lhs.width_);
4041                 return true;
4042         }
4043
4044         if (str == "~0") {
4045                 cover("kernel.rtlil.sigspec.parse.rhs_ones");
4046                 sig = RTLIL::SigSpec(RTLIL::State::S1, lhs.width_);
4047                 return true;
4048         }
4049
4050         if (lhs.chunks_.size() == 1) {
4051                 char *p = (char*)str.c_str(), *endptr;
4052                 long int val = strtol(p, &endptr, 10);
4053                 if (endptr && endptr != p && *endptr == 0) {
4054                         sig = RTLIL::SigSpec(val, lhs.width_);
4055                         cover("kernel.rtlil.sigspec.parse.rhs_dec");
4056                         return true;
4057                 }
4058         }
4059
4060         return parse(sig, module, str);
4061 }
4062
4063 RTLIL::CaseRule::~CaseRule()
4064 {
4065         for (auto it = switches.begin(); it != switches.end(); it++)
4066                 delete *it;
4067 }
4068
4069 bool RTLIL::CaseRule::empty() const
4070 {
4071         return actions.empty() && switches.empty();
4072 }
4073
4074 RTLIL::CaseRule *RTLIL::CaseRule::clone() const
4075 {
4076         RTLIL::CaseRule *new_caserule = new RTLIL::CaseRule;
4077         new_caserule->compare = compare;
4078         new_caserule->actions = actions;
4079         for (auto &it : switches)
4080                 new_caserule->switches.push_back(it->clone());
4081         return new_caserule;
4082 }
4083
4084 RTLIL::SwitchRule::~SwitchRule()
4085 {
4086         for (auto it = cases.begin(); it != cases.end(); it++)
4087                 delete *it;
4088 }
4089
4090 bool RTLIL::SwitchRule::empty() const
4091 {
4092         return cases.empty();
4093 }
4094
4095 RTLIL::SwitchRule *RTLIL::SwitchRule::clone() const
4096 {
4097         RTLIL::SwitchRule *new_switchrule = new RTLIL::SwitchRule;
4098         new_switchrule->signal = signal;
4099         new_switchrule->attributes = attributes;
4100         for (auto &it : cases)
4101                 new_switchrule->cases.push_back(it->clone());
4102         return new_switchrule;
4103
4104 }
4105
4106 RTLIL::SyncRule *RTLIL::SyncRule::clone() const
4107 {
4108         RTLIL::SyncRule *new_syncrule = new RTLIL::SyncRule;
4109         new_syncrule->type = type;
4110         new_syncrule->signal = signal;
4111         new_syncrule->actions = actions;
4112         return new_syncrule;
4113 }
4114
4115 RTLIL::Process::~Process()
4116 {
4117         for (auto it = syncs.begin(); it != syncs.end(); it++)
4118                 delete *it;
4119 }
4120
4121 RTLIL::Process *RTLIL::Process::clone() const
4122 {
4123         RTLIL::Process *new_proc = new RTLIL::Process;
4124
4125         new_proc->name = name;
4126         new_proc->attributes = attributes;
4127
4128         RTLIL::CaseRule *rc_ptr = root_case.clone();
4129         new_proc->root_case = *rc_ptr;
4130         rc_ptr->switches.clear();
4131         delete rc_ptr;
4132
4133         for (auto &it : syncs)
4134                 new_proc->syncs.push_back(it->clone());
4135
4136         return new_proc;
4137 }
4138
4139 #ifdef WITH_PYTHON
4140 RTLIL::Memory::~Memory()
4141 {
4142         RTLIL::Memory::get_all_memorys()->erase(hashidx_);
4143 }
4144 static std::map<unsigned int, RTLIL::Memory*> all_memorys;
4145 std::map<unsigned int, RTLIL::Memory*> *RTLIL::Memory::get_all_memorys(void)
4146 {
4147         return &all_memorys;
4148 }
4149 #endif
4150 YOSYS_NAMESPACE_END