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Merge pull request #1603 from whitequark/ice40-ram_style
[yosys.git] / kernel / rtlil.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 #include "kernel/yosys.h"
21 #include "kernel/macc.h"
22 #include "kernel/celltypes.h"
23 #include "frontends/verilog/verilog_frontend.h"
24 #include "frontends/verilog/preproc.h"
25 #include "backends/ilang/ilang_backend.h"
26
27 #include <string.h>
28 #include <algorithm>
29
30 YOSYS_NAMESPACE_BEGIN
31
32 RTLIL::IdString::destruct_guard_t RTLIL::IdString::destruct_guard;
33 std::vector<char*> RTLIL::IdString::global_id_storage_;
34 dict<char*, int, hash_cstr_ops> RTLIL::IdString::global_id_index_;
35 #ifndef YOSYS_NO_IDS_REFCNT
36 std::vector<int> RTLIL::IdString::global_refcount_storage_;
37 std::vector<int> RTLIL::IdString::global_free_idx_list_;
38 #endif
39 #ifdef YOSYS_USE_STICKY_IDS
40 int RTLIL::IdString::last_created_idx_[8];
41 int RTLIL::IdString::last_created_idx_ptr_;
42 #endif
43
44 #define X(_id) IdString RTLIL::ID::_id;
45 #include "kernel/constids.inc"
46 #undef X
47
48 dict<std::string, std::string> RTLIL::constpad;
49
50 const pool<IdString> &RTLIL::builtin_ff_cell_types() {
51 static const pool<IdString> res = {
52 ID($sr),
53 ID($ff),
54 ID($dff),
55 ID($dffe),
56 ID($dffsr),
57 ID($adff),
58 ID($dlatch),
59 ID($dlatchsr),
60 ID($_DFFE_NN_),
61 ID($_DFFE_NP_),
62 ID($_DFFE_PN_),
63 ID($_DFFE_PP_),
64 ID($_DFFSR_NNN_),
65 ID($_DFFSR_NNP_),
66 ID($_DFFSR_NPN_),
67 ID($_DFFSR_NPP_),
68 ID($_DFFSR_PNN_),
69 ID($_DFFSR_PNP_),
70 ID($_DFFSR_PPN_),
71 ID($_DFFSR_PPP_),
72 ID($_DFF_NN0_),
73 ID($_DFF_NN1_),
74 ID($_DFF_NP0_),
75 ID($_DFF_NP1_),
76 ID($_DFF_N_),
77 ID($_DFF_PN0_),
78 ID($_DFF_PN1_),
79 ID($_DFF_PP0_),
80 ID($_DFF_PP1_),
81 ID($_DFF_P_),
82 ID($_DLATCHSR_NNN_),
83 ID($_DLATCHSR_NNP_),
84 ID($_DLATCHSR_NPN_),
85 ID($_DLATCHSR_NPP_),
86 ID($_DLATCHSR_PNN_),
87 ID($_DLATCHSR_PNP_),
88 ID($_DLATCHSR_PPN_),
89 ID($_DLATCHSR_PPP_),
90 ID($_DLATCH_N_),
91 ID($_DLATCH_P_),
92 ID($_FF_),
93 };
94 return res;
95 }
96
97 RTLIL::Const::Const()
98 {
99 flags = RTLIL::CONST_FLAG_NONE;
100 }
101
102 RTLIL::Const::Const(std::string str)
103 {
104 flags = RTLIL::CONST_FLAG_STRING;
105 for (int i = str.size()-1; i >= 0; i--) {
106 unsigned char ch = str[i];
107 for (int j = 0; j < 8; j++) {
108 bits.push_back((ch & 1) != 0 ? State::S1 : State::S0);
109 ch = ch >> 1;
110 }
111 }
112 }
113
114 RTLIL::Const::Const(int val, int width)
115 {
116 flags = RTLIL::CONST_FLAG_NONE;
117 for (int i = 0; i < width; i++) {
118 bits.push_back((val & 1) != 0 ? State::S1 : State::S0);
119 val = val >> 1;
120 }
121 }
122
123 RTLIL::Const::Const(RTLIL::State bit, int width)
124 {
125 flags = RTLIL::CONST_FLAG_NONE;
126 for (int i = 0; i < width; i++)
127 bits.push_back(bit);
128 }
129
130 RTLIL::Const::Const(const std::vector<bool> &bits)
131 {
132 flags = RTLIL::CONST_FLAG_NONE;
133 for (const auto &b : bits)
134 this->bits.emplace_back(b ? State::S1 : State::S0);
135 }
136
137 RTLIL::Const::Const(const RTLIL::Const &c)
138 {
139 flags = c.flags;
140 for (const auto &b : c.bits)
141 this->bits.push_back(b);
142 }
143
144 bool RTLIL::Const::operator <(const RTLIL::Const &other) const
145 {
146 if (bits.size() != other.bits.size())
147 return bits.size() < other.bits.size();
148 for (size_t i = 0; i < bits.size(); i++)
149 if (bits[i] != other.bits[i])
150 return bits[i] < other.bits[i];
151 return false;
152 }
153
154 bool RTLIL::Const::operator ==(const RTLIL::Const &other) const
155 {
156 return bits == other.bits;
157 }
158
159 bool RTLIL::Const::operator !=(const RTLIL::Const &other) const
160 {
161 return bits != other.bits;
162 }
163
164 bool RTLIL::Const::as_bool() const
165 {
166 for (size_t i = 0; i < bits.size(); i++)
167 if (bits[i] == State::S1)
168 return true;
169 return false;
170 }
171
172 int RTLIL::Const::as_int(bool is_signed) const
173 {
174 int32_t ret = 0;
175 for (size_t i = 0; i < bits.size() && i < 32; i++)
176 if (bits[i] == State::S1)
177 ret |= 1 << i;
178 if (is_signed && bits.back() == State::S1)
179 for (size_t i = bits.size(); i < 32; i++)
180 ret |= 1 << i;
181 return ret;
182 }
183
184 std::string RTLIL::Const::as_string() const
185 {
186 std::string ret;
187 ret.reserve(bits.size());
188 for (size_t i = bits.size(); i > 0; i--)
189 switch (bits[i-1]) {
190 case S0: ret += "0"; break;
191 case S1: ret += "1"; break;
192 case Sx: ret += "x"; break;
193 case Sz: ret += "z"; break;
194 case Sa: ret += "-"; break;
195 case Sm: ret += "m"; break;
196 }
197 return ret;
198 }
199
200 RTLIL::Const RTLIL::Const::from_string(const std::string &str)
201 {
202 Const c;
203 c.bits.reserve(str.size());
204 for (auto it = str.rbegin(); it != str.rend(); it++)
205 switch (*it) {
206 case '0': c.bits.push_back(State::S0); break;
207 case '1': c.bits.push_back(State::S1); break;
208 case 'x': c.bits.push_back(State::Sx); break;
209 case 'z': c.bits.push_back(State::Sz); break;
210 case 'm': c.bits.push_back(State::Sm); break;
211 default: c.bits.push_back(State::Sa);
212 }
213 return c;
214 }
215
216 std::string RTLIL::Const::decode_string() const
217 {
218 std::string string;
219 string.reserve(GetSize(bits)/8);
220 for (int i = 0; i < GetSize(bits); i += 8) {
221 char ch = 0;
222 for (int j = 0; j < 8 && i + j < int (bits.size()); j++)
223 if (bits[i + j] == RTLIL::State::S1)
224 ch |= 1 << j;
225 if (ch != 0)
226 string.append({ch});
227 }
228 std::reverse(string.begin(), string.end());
229 return string;
230 }
231
232 bool RTLIL::Const::is_fully_zero() const
233 {
234 cover("kernel.rtlil.const.is_fully_zero");
235
236 for (const auto &bit : bits)
237 if (bit != RTLIL::State::S0)
238 return false;
239
240 return true;
241 }
242
243 bool RTLIL::Const::is_fully_ones() const
244 {
245 cover("kernel.rtlil.const.is_fully_ones");
246
247 for (const auto &bit : bits)
248 if (bit != RTLIL::State::S1)
249 return false;
250
251 return true;
252 }
253
254 bool RTLIL::Const::is_fully_def() const
255 {
256 cover("kernel.rtlil.const.is_fully_def");
257
258 for (const auto &bit : bits)
259 if (bit != RTLIL::State::S0 && bit != RTLIL::State::S1)
260 return false;
261
262 return true;
263 }
264
265 bool RTLIL::Const::is_fully_undef() const
266 {
267 cover("kernel.rtlil.const.is_fully_undef");
268
269 for (const auto &bit : bits)
270 if (bit != RTLIL::State::Sx && bit != RTLIL::State::Sz)
271 return false;
272
273 return true;
274 }
275
276 void RTLIL::AttrObject::set_bool_attribute(RTLIL::IdString id, bool value)
277 {
278 if (value)
279 attributes[id] = RTLIL::Const(1);
280 else
281 attributes.erase(id);
282 }
283
284 bool RTLIL::AttrObject::get_bool_attribute(RTLIL::IdString id) const
285 {
286 const auto it = attributes.find(id);
287 if (it == attributes.end())
288 return false;
289 return it->second.as_bool();
290 }
291
292 void RTLIL::AttrObject::set_strpool_attribute(RTLIL::IdString id, const pool<string> &data)
293 {
294 string attrval;
295 for (const auto &s : data) {
296 if (!attrval.empty())
297 attrval += "|";
298 attrval += s;
299 }
300 attributes[id] = RTLIL::Const(attrval);
301 }
302
303 void RTLIL::AttrObject::add_strpool_attribute(RTLIL::IdString id, const pool<string> &data)
304 {
305 pool<string> union_data = get_strpool_attribute(id);
306 union_data.insert(data.begin(), data.end());
307 if (!union_data.empty())
308 set_strpool_attribute(id, union_data);
309 }
310
311 pool<string> RTLIL::AttrObject::get_strpool_attribute(RTLIL::IdString id) const
312 {
313 pool<string> data;
314 if (attributes.count(id) != 0)
315 for (auto s : split_tokens(attributes.at(id).decode_string(), "|"))
316 data.insert(s);
317 return data;
318 }
319
320 void RTLIL::AttrObject::set_src_attribute(const std::string &src)
321 {
322 if (src.empty())
323 attributes.erase(ID::src);
324 else
325 attributes[ID::src] = src;
326 }
327
328 std::string RTLIL::AttrObject::get_src_attribute() const
329 {
330 std::string src;
331 const auto it = attributes.find(ID::src);
332 if (it != attributes.end())
333 src = it->second.decode_string();
334 return src;
335 }
336
337 bool RTLIL::Selection::selected_module(RTLIL::IdString mod_name) const
338 {
339 if (full_selection)
340 return true;
341 if (selected_modules.count(mod_name) > 0)
342 return true;
343 if (selected_members.count(mod_name) > 0)
344 return true;
345 return false;
346 }
347
348 bool RTLIL::Selection::selected_whole_module(RTLIL::IdString mod_name) const
349 {
350 if (full_selection)
351 return true;
352 if (selected_modules.count(mod_name) > 0)
353 return true;
354 return false;
355 }
356
357 bool RTLIL::Selection::selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const
358 {
359 if (full_selection)
360 return true;
361 if (selected_modules.count(mod_name) > 0)
362 return true;
363 if (selected_members.count(mod_name) > 0)
364 if (selected_members.at(mod_name).count(memb_name) > 0)
365 return true;
366 return false;
367 }
368
369 void RTLIL::Selection::optimize(RTLIL::Design *design)
370 {
371 if (full_selection) {
372 selected_modules.clear();
373 selected_members.clear();
374 return;
375 }
376
377 std::vector<RTLIL::IdString> del_list, add_list;
378
379 del_list.clear();
380 for (auto mod_name : selected_modules) {
381 if (design->modules_.count(mod_name) == 0)
382 del_list.push_back(mod_name);
383 selected_members.erase(mod_name);
384 }
385 for (auto mod_name : del_list)
386 selected_modules.erase(mod_name);
387
388 del_list.clear();
389 for (auto &it : selected_members)
390 if (design->modules_.count(it.first) == 0)
391 del_list.push_back(it.first);
392 for (auto mod_name : del_list)
393 selected_members.erase(mod_name);
394
395 for (auto &it : selected_members) {
396 del_list.clear();
397 for (auto memb_name : it.second)
398 if (design->modules_[it.first]->count_id(memb_name) == 0)
399 del_list.push_back(memb_name);
400 for (auto memb_name : del_list)
401 it.second.erase(memb_name);
402 }
403
404 del_list.clear();
405 add_list.clear();
406 for (auto &it : selected_members)
407 if (it.second.size() == 0)
408 del_list.push_back(it.first);
409 else if (it.second.size() == design->modules_[it.first]->wires_.size() + design->modules_[it.first]->memories.size() +
410 design->modules_[it.first]->cells_.size() + design->modules_[it.first]->processes.size())
411 add_list.push_back(it.first);
412 for (auto mod_name : del_list)
413 selected_members.erase(mod_name);
414 for (auto mod_name : add_list) {
415 selected_members.erase(mod_name);
416 selected_modules.insert(mod_name);
417 }
418
419 if (selected_modules.size() == design->modules_.size()) {
420 full_selection = true;
421 selected_modules.clear();
422 selected_members.clear();
423 }
424 }
425
426 RTLIL::Design::Design()
427 : verilog_defines (new define_map_t)
428 {
429 static unsigned int hashidx_count = 123456789;
430 hashidx_count = mkhash_xorshift(hashidx_count);
431 hashidx_ = hashidx_count;
432
433 refcount_modules_ = 0;
434 selection_stack.push_back(RTLIL::Selection());
435
436 #ifdef WITH_PYTHON
437 RTLIL::Design::get_all_designs()->insert(std::pair<unsigned int, RTLIL::Design*>(hashidx_, this));
438 #endif
439 }
440
441 RTLIL::Design::~Design()
442 {
443 for (auto it = modules_.begin(); it != modules_.end(); ++it)
444 delete it->second;
445 for (auto n : verilog_packages)
446 delete n;
447 for (auto n : verilog_globals)
448 delete n;
449 #ifdef WITH_PYTHON
450 RTLIL::Design::get_all_designs()->erase(hashidx_);
451 #endif
452 }
453
454 #ifdef WITH_PYTHON
455 static std::map<unsigned int, RTLIL::Design*> all_designs;
456 std::map<unsigned int, RTLIL::Design*> *RTLIL::Design::get_all_designs(void)
457 {
458 return &all_designs;
459 }
460 #endif
461
462 RTLIL::ObjRange<RTLIL::Module*> RTLIL::Design::modules()
463 {
464 return RTLIL::ObjRange<RTLIL::Module*>(&modules_, &refcount_modules_);
465 }
466
467 RTLIL::Module *RTLIL::Design::module(RTLIL::IdString name)
468 {
469 return modules_.count(name) ? modules_.at(name) : NULL;
470 }
471
472 RTLIL::Module *RTLIL::Design::top_module()
473 {
474 RTLIL::Module *module = nullptr;
475 int module_count = 0;
476
477 for (auto mod : selected_modules()) {
478 if (mod->get_bool_attribute(ID::top))
479 return mod;
480 module_count++;
481 module = mod;
482 }
483
484 return module_count == 1 ? module : nullptr;
485 }
486
487 void RTLIL::Design::add(RTLIL::Module *module)
488 {
489 log_assert(modules_.count(module->name) == 0);
490 log_assert(refcount_modules_ == 0);
491 modules_[module->name] = module;
492 module->design = this;
493
494 for (auto mon : monitors)
495 mon->notify_module_add(module);
496
497 if (yosys_xtrace) {
498 log("#X# New Module: %s\n", log_id(module));
499 log_backtrace("-X- ", yosys_xtrace-1);
500 }
501 }
502
503 RTLIL::Module *RTLIL::Design::addModule(RTLIL::IdString name)
504 {
505 log_assert(modules_.count(name) == 0);
506 log_assert(refcount_modules_ == 0);
507
508 RTLIL::Module *module = new RTLIL::Module;
509 modules_[name] = module;
510 module->design = this;
511 module->name = name;
512
513 for (auto mon : monitors)
514 mon->notify_module_add(module);
515
516 if (yosys_xtrace) {
517 log("#X# New Module: %s\n", log_id(module));
518 log_backtrace("-X- ", yosys_xtrace-1);
519 }
520
521 return module;
522 }
523
524 void RTLIL::Design::scratchpad_unset(const std::string &varname)
525 {
526 scratchpad.erase(varname);
527 }
528
529 void RTLIL::Design::scratchpad_set_int(const std::string &varname, int value)
530 {
531 scratchpad[varname] = stringf("%d", value);
532 }
533
534 void RTLIL::Design::scratchpad_set_bool(const std::string &varname, bool value)
535 {
536 scratchpad[varname] = value ? "true" : "false";
537 }
538
539 void RTLIL::Design::scratchpad_set_string(const std::string &varname, std::string value)
540 {
541 scratchpad[varname] = std::move(value);
542 }
543
544 int RTLIL::Design::scratchpad_get_int(const std::string &varname, int default_value) const
545 {
546 auto it = scratchpad.find(varname);
547 if (it == scratchpad.end())
548 return default_value;
549
550 const std::string &str = it->second;
551
552 if (str == "0" || str == "false")
553 return 0;
554
555 if (str == "1" || str == "true")
556 return 1;
557
558 char *endptr = nullptr;
559 long int parsed_value = strtol(str.c_str(), &endptr, 10);
560 return *endptr ? default_value : parsed_value;
561 }
562
563 bool RTLIL::Design::scratchpad_get_bool(const std::string &varname, bool default_value) const
564 {
565 auto it = scratchpad.find(varname);
566 if (it == scratchpad.end())
567 return default_value;
568
569 const std::string &str = it->second;
570
571 if (str == "0" || str == "false")
572 return false;
573
574 if (str == "1" || str == "true")
575 return true;
576
577 return default_value;
578 }
579
580 std::string RTLIL::Design::scratchpad_get_string(const std::string &varname, const std::string &default_value) const
581 {
582 auto it = scratchpad.find(varname);
583 if (it == scratchpad.end())
584 return default_value;
585
586 return it->second;
587 }
588
589 void RTLIL::Design::remove(RTLIL::Module *module)
590 {
591 for (auto mon : monitors)
592 mon->notify_module_del(module);
593
594 if (yosys_xtrace) {
595 log("#X# Remove Module: %s\n", log_id(module));
596 log_backtrace("-X- ", yosys_xtrace-1);
597 }
598
599 log_assert(modules_.at(module->name) == module);
600 modules_.erase(module->name);
601 delete module;
602 }
603
604 void RTLIL::Design::rename(RTLIL::Module *module, RTLIL::IdString new_name)
605 {
606 modules_.erase(module->name);
607 module->name = new_name;
608 add(module);
609 }
610
611 void RTLIL::Design::sort()
612 {
613 scratchpad.sort();
614 modules_.sort(sort_by_id_str());
615 for (auto &it : modules_)
616 it.second->sort();
617 }
618
619 void RTLIL::Design::check()
620 {
621 #ifndef NDEBUG
622 for (auto &it : modules_) {
623 log_assert(this == it.second->design);
624 log_assert(it.first == it.second->name);
625 log_assert(!it.first.empty());
626 it.second->check();
627 }
628 #endif
629 }
630
631 void RTLIL::Design::optimize()
632 {
633 for (auto &it : modules_)
634 it.second->optimize();
635 for (auto &it : selection_stack)
636 it.optimize(this);
637 for (auto &it : selection_vars)
638 it.second.optimize(this);
639 }
640
641 bool RTLIL::Design::selected_module(RTLIL::IdString mod_name) const
642 {
643 if (!selected_active_module.empty() && mod_name != selected_active_module)
644 return false;
645 if (selection_stack.size() == 0)
646 return true;
647 return selection_stack.back().selected_module(mod_name);
648 }
649
650 bool RTLIL::Design::selected_whole_module(RTLIL::IdString mod_name) const
651 {
652 if (!selected_active_module.empty() && mod_name != selected_active_module)
653 return false;
654 if (selection_stack.size() == 0)
655 return true;
656 return selection_stack.back().selected_whole_module(mod_name);
657 }
658
659 bool RTLIL::Design::selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const
660 {
661 if (!selected_active_module.empty() && mod_name != selected_active_module)
662 return false;
663 if (selection_stack.size() == 0)
664 return true;
665 return selection_stack.back().selected_member(mod_name, memb_name);
666 }
667
668 bool RTLIL::Design::selected_module(RTLIL::Module *mod) const
669 {
670 return selected_module(mod->name);
671 }
672
673 bool RTLIL::Design::selected_whole_module(RTLIL::Module *mod) const
674 {
675 return selected_whole_module(mod->name);
676 }
677
678 std::vector<RTLIL::Module*> RTLIL::Design::selected_modules() const
679 {
680 std::vector<RTLIL::Module*> result;
681 result.reserve(modules_.size());
682 for (auto &it : modules_)
683 if (selected_module(it.first) && !it.second->get_blackbox_attribute())
684 result.push_back(it.second);
685 return result;
686 }
687
688 std::vector<RTLIL::Module*> RTLIL::Design::selected_whole_modules() const
689 {
690 std::vector<RTLIL::Module*> result;
691 result.reserve(modules_.size());
692 for (auto &it : modules_)
693 if (selected_whole_module(it.first) && !it.second->get_blackbox_attribute())
694 result.push_back(it.second);
695 return result;
696 }
697
698 std::vector<RTLIL::Module*> RTLIL::Design::selected_whole_modules_warn() const
699 {
700 std::vector<RTLIL::Module*> result;
701 result.reserve(modules_.size());
702 for (auto &it : modules_)
703 if (it.second->get_blackbox_attribute())
704 continue;
705 else if (selected_whole_module(it.first))
706 result.push_back(it.second);
707 else if (selected_module(it.first))
708 log_warning("Ignoring partially selected module %s.\n", log_id(it.first));
709 return result;
710 }
711
712 RTLIL::Module::Module()
713 {
714 static unsigned int hashidx_count = 123456789;
715 hashidx_count = mkhash_xorshift(hashidx_count);
716 hashidx_ = hashidx_count;
717
718 design = nullptr;
719 refcount_wires_ = 0;
720 refcount_cells_ = 0;
721
722 #ifdef WITH_PYTHON
723 RTLIL::Module::get_all_modules()->insert(std::pair<unsigned int, RTLIL::Module*>(hashidx_, this));
724 #endif
725 }
726
727 RTLIL::Module::~Module()
728 {
729 for (auto it = wires_.begin(); it != wires_.end(); ++it)
730 delete it->second;
731 for (auto it = memories.begin(); it != memories.end(); ++it)
732 delete it->second;
733 for (auto it = cells_.begin(); it != cells_.end(); ++it)
734 delete it->second;
735 for (auto it = processes.begin(); it != processes.end(); ++it)
736 delete it->second;
737 #ifdef WITH_PYTHON
738 RTLIL::Module::get_all_modules()->erase(hashidx_);
739 #endif
740 }
741
742 #ifdef WITH_PYTHON
743 static std::map<unsigned int, RTLIL::Module*> all_modules;
744 std::map<unsigned int, RTLIL::Module*> *RTLIL::Module::get_all_modules(void)
745 {
746 return &all_modules;
747 }
748 #endif
749
750 void RTLIL::Module::makeblackbox()
751 {
752 pool<RTLIL::Wire*> delwires;
753
754 for (auto it = wires_.begin(); it != wires_.end(); ++it)
755 if (!it->second->port_input && !it->second->port_output)
756 delwires.insert(it->second);
757
758 for (auto it = memories.begin(); it != memories.end(); ++it)
759 delete it->second;
760 memories.clear();
761
762 for (auto it = cells_.begin(); it != cells_.end(); ++it)
763 delete it->second;
764 cells_.clear();
765
766 for (auto it = processes.begin(); it != processes.end(); ++it)
767 delete it->second;
768 processes.clear();
769
770 remove(delwires);
771 set_bool_attribute(ID::blackbox);
772 }
773
774 void RTLIL::Module::reprocess_module(RTLIL::Design *, const dict<RTLIL::IdString, RTLIL::Module *> &)
775 {
776 log_error("Cannot reprocess_module module `%s' !\n", id2cstr(name));
777 }
778
779 RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, const dict<RTLIL::IdString, RTLIL::Const> &, bool mayfail)
780 {
781 if (mayfail)
782 return RTLIL::IdString();
783 log_error("Module `%s' is used with parameters but is not parametric!\n", id2cstr(name));
784 }
785
786
787 RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, const dict<RTLIL::IdString, RTLIL::Const> &, const dict<RTLIL::IdString, RTLIL::Module*> &, const dict<RTLIL::IdString, RTLIL::IdString> &, bool mayfail)
788 {
789 if (mayfail)
790 return RTLIL::IdString();
791 log_error("Module `%s' is used with parameters but is not parametric!\n", id2cstr(name));
792 }
793
794 size_t RTLIL::Module::count_id(RTLIL::IdString id)
795 {
796 return wires_.count(id) + memories.count(id) + cells_.count(id) + processes.count(id);
797 }
798
799 #ifndef NDEBUG
800 namespace {
801 struct InternalCellChecker
802 {
803 RTLIL::Module *module;
804 RTLIL::Cell *cell;
805 pool<RTLIL::IdString> expected_params, expected_ports;
806
807 InternalCellChecker(RTLIL::Module *module, RTLIL::Cell *cell) : module(module), cell(cell) { }
808
809 void error(int linenr)
810 {
811 std::stringstream buf;
812 ILANG_BACKEND::dump_cell(buf, " ", cell);
813
814 log_error("Found error in internal cell %s%s%s (%s) at %s:%d:\n%s",
815 module ? module->name.c_str() : "", module ? "." : "",
816 cell->name.c_str(), cell->type.c_str(), __FILE__, linenr, buf.str().c_str());
817 }
818
819 int param(RTLIL::IdString name)
820 {
821 auto it = cell->parameters.find(name);
822 if (it == cell->parameters.end())
823 error(__LINE__);
824 expected_params.insert(name);
825 return it->second.as_int();
826 }
827
828 int param_bool(RTLIL::IdString name)
829 {
830 int v = param(name);
831 if (GetSize(cell->parameters.at(name)) > 32)
832 error(__LINE__);
833 if (v != 0 && v != 1)
834 error(__LINE__);
835 return v;
836 }
837
838 int param_bool(RTLIL::IdString name, bool expected)
839 {
840 int v = param_bool(name);
841 if (v != expected)
842 error(__LINE__);
843 return v;
844 }
845
846 void param_bits(RTLIL::IdString name, int width)
847 {
848 param(name);
849 if (GetSize(cell->parameters.at(name).bits) != width)
850 error(__LINE__);
851 }
852
853 void port(RTLIL::IdString name, int width)
854 {
855 auto it = cell->connections_.find(name);
856 if (it == cell->connections_.end())
857 error(__LINE__);
858 if (GetSize(it->second) != width)
859 error(__LINE__);
860 expected_ports.insert(name);
861 }
862
863 void check_expected(bool check_matched_sign = false)
864 {
865 for (auto &para : cell->parameters)
866 if (expected_params.count(para.first) == 0)
867 error(__LINE__);
868 for (auto &conn : cell->connections())
869 if (expected_ports.count(conn.first) == 0)
870 error(__LINE__);
871
872 if (check_matched_sign) {
873 log_assert(expected_params.count(ID::A_SIGNED) != 0 && expected_params.count(ID::B_SIGNED) != 0);
874 bool a_is_signed = cell->parameters.at(ID::A_SIGNED).as_bool();
875 bool b_is_signed = cell->parameters.at(ID::B_SIGNED).as_bool();
876 if (a_is_signed != b_is_signed)
877 error(__LINE__);
878 }
879 }
880
881 void check()
882 {
883 if (!cell->type.begins_with("$") || cell->type.begins_with("$__") || cell->type.begins_with("$paramod") || cell->type.begins_with("$fmcombine") ||
884 cell->type.begins_with("$verific$") || cell->type.begins_with("$array:") || cell->type.begins_with("$extern:"))
885 return;
886
887 if (cell->type.in(ID($not), ID($pos), ID($neg))) {
888 param_bool(ID::A_SIGNED);
889 port(ID::A, param(ID::A_WIDTH));
890 port(ID::Y, param(ID::Y_WIDTH));
891 check_expected();
892 return;
893 }
894
895 if (cell->type.in(ID($and), ID($or), ID($xor), ID($xnor))) {
896 param_bool(ID::A_SIGNED);
897 param_bool(ID::B_SIGNED);
898 port(ID::A, param(ID::A_WIDTH));
899 port(ID::B, param(ID::B_WIDTH));
900 port(ID::Y, param(ID::Y_WIDTH));
901 check_expected(true);
902 return;
903 }
904
905 if (cell->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor), ID($reduce_bool))) {
906 param_bool(ID::A_SIGNED);
907 port(ID::A, param(ID::A_WIDTH));
908 port(ID::Y, param(ID::Y_WIDTH));
909 check_expected();
910 return;
911 }
912
913 if (cell->type.in(ID($shl), ID($shr), ID($sshl), ID($sshr))) {
914 param_bool(ID::A_SIGNED);
915 param_bool(ID::B_SIGNED, /*expected=*/false);
916 port(ID::A, param(ID::A_WIDTH));
917 port(ID::B, param(ID::B_WIDTH));
918 port(ID::Y, param(ID::Y_WIDTH));
919 check_expected(/*check_matched_sign=*/false);
920 return;
921 }
922
923 if (cell->type.in(ID($shift), ID($shiftx))) {
924 param_bool(ID::A_SIGNED);
925 param_bool(ID::B_SIGNED);
926 port(ID::A, param(ID::A_WIDTH));
927 port(ID::B, param(ID::B_WIDTH));
928 port(ID::Y, param(ID::Y_WIDTH));
929 check_expected(/*check_matched_sign=*/false);
930 return;
931 }
932
933 if (cell->type.in(ID($lt), ID($le), ID($eq), ID($ne), ID($eqx), ID($nex), ID($ge), ID($gt))) {
934 param_bool(ID::A_SIGNED);
935 param_bool(ID::B_SIGNED);
936 port(ID::A, param(ID::A_WIDTH));
937 port(ID::B, param(ID::B_WIDTH));
938 port(ID::Y, param(ID::Y_WIDTH));
939 check_expected(true);
940 return;
941 }
942
943 if (cell->type.in(ID($add), ID($sub), ID($mul), ID($div), ID($mod), ID($pow))) {
944 param_bool(ID::A_SIGNED);
945 param_bool(ID::B_SIGNED);
946 port(ID::A, param(ID::A_WIDTH));
947 port(ID::B, param(ID::B_WIDTH));
948 port(ID::Y, param(ID::Y_WIDTH));
949 check_expected(cell->type != ID($pow));
950 return;
951 }
952
953 if (cell->type == ID($fa)) {
954 port(ID::A, param(ID::WIDTH));
955 port(ID::B, param(ID::WIDTH));
956 port(ID::C, param(ID::WIDTH));
957 port(ID::X, param(ID::WIDTH));
958 port(ID::Y, param(ID::WIDTH));
959 check_expected();
960 return;
961 }
962
963 if (cell->type == ID($lcu)) {
964 port(ID::P, param(ID::WIDTH));
965 port(ID::G, param(ID::WIDTH));
966 port(ID::CI, 1);
967 port(ID::CO, param(ID::WIDTH));
968 check_expected();
969 return;
970 }
971
972 if (cell->type == ID($alu)) {
973 param_bool(ID::A_SIGNED);
974 param_bool(ID::B_SIGNED);
975 port(ID::A, param(ID::A_WIDTH));
976 port(ID::B, param(ID::B_WIDTH));
977 port(ID::CI, 1);
978 port(ID::BI, 1);
979 port(ID::X, param(ID::Y_WIDTH));
980 port(ID::Y, param(ID::Y_WIDTH));
981 port(ID::CO, param(ID::Y_WIDTH));
982 check_expected(true);
983 return;
984 }
985
986 if (cell->type == ID($macc)) {
987 param(ID::CONFIG);
988 param(ID::CONFIG_WIDTH);
989 port(ID::A, param(ID::A_WIDTH));
990 port(ID::B, param(ID::B_WIDTH));
991 port(ID::Y, param(ID::Y_WIDTH));
992 check_expected();
993 Macc().from_cell(cell);
994 return;
995 }
996
997 if (cell->type == ID($logic_not)) {
998 param_bool(ID::A_SIGNED);
999 port(ID::A, param(ID::A_WIDTH));
1000 port(ID::Y, param(ID::Y_WIDTH));
1001 check_expected();
1002 return;
1003 }
1004
1005 if (cell->type.in(ID($logic_and), ID($logic_or))) {
1006 param_bool(ID::A_SIGNED);
1007 param_bool(ID::B_SIGNED);
1008 port(ID::A, param(ID::A_WIDTH));
1009 port(ID::B, param(ID::B_WIDTH));
1010 port(ID::Y, param(ID::Y_WIDTH));
1011 check_expected(/*check_matched_sign=*/false);
1012 return;
1013 }
1014
1015 if (cell->type == ID($slice)) {
1016 param(ID::OFFSET);
1017 port(ID::A, param(ID::A_WIDTH));
1018 port(ID::Y, param(ID::Y_WIDTH));
1019 if (param(ID::OFFSET) + param(ID::Y_WIDTH) > param(ID::A_WIDTH))
1020 error(__LINE__);
1021 check_expected();
1022 return;
1023 }
1024
1025 if (cell->type == ID($concat)) {
1026 port(ID::A, param(ID::A_WIDTH));
1027 port(ID::B, param(ID::B_WIDTH));
1028 port(ID::Y, param(ID::A_WIDTH) + param(ID::B_WIDTH));
1029 check_expected();
1030 return;
1031 }
1032
1033 if (cell->type == ID($mux)) {
1034 port(ID::A, param(ID::WIDTH));
1035 port(ID::B, param(ID::WIDTH));
1036 port(ID::S, 1);
1037 port(ID::Y, param(ID::WIDTH));
1038 check_expected();
1039 return;
1040 }
1041
1042 if (cell->type == ID($pmux)) {
1043 port(ID::A, param(ID::WIDTH));
1044 port(ID::B, param(ID::WIDTH) * param(ID::S_WIDTH));
1045 port(ID::S, param(ID::S_WIDTH));
1046 port(ID::Y, param(ID::WIDTH));
1047 check_expected();
1048 return;
1049 }
1050
1051 if (cell->type == ID($lut)) {
1052 param(ID::LUT);
1053 port(ID::A, param(ID::WIDTH));
1054 port(ID::Y, 1);
1055 check_expected();
1056 return;
1057 }
1058
1059 if (cell->type == ID($sop)) {
1060 param(ID::DEPTH);
1061 param(ID::TABLE);
1062 port(ID::A, param(ID::WIDTH));
1063 port(ID::Y, 1);
1064 check_expected();
1065 return;
1066 }
1067
1068 if (cell->type == ID($sr)) {
1069 param_bool(ID::SET_POLARITY);
1070 param_bool(ID::CLR_POLARITY);
1071 port(ID::SET, param(ID::WIDTH));
1072 port(ID::CLR, param(ID::WIDTH));
1073 port(ID::Q, param(ID::WIDTH));
1074 check_expected();
1075 return;
1076 }
1077
1078 if (cell->type == ID($ff)) {
1079 port(ID::D, param(ID::WIDTH));
1080 port(ID::Q, param(ID::WIDTH));
1081 check_expected();
1082 return;
1083 }
1084
1085 if (cell->type == ID($dff)) {
1086 param_bool(ID::CLK_POLARITY);
1087 port(ID::CLK, 1);
1088 port(ID::D, param(ID::WIDTH));
1089 port(ID::Q, param(ID::WIDTH));
1090 check_expected();
1091 return;
1092 }
1093
1094 if (cell->type == ID($dffe)) {
1095 param_bool(ID::CLK_POLARITY);
1096 param_bool(ID::EN_POLARITY);
1097 port(ID::CLK, 1);
1098 port(ID::EN, 1);
1099 port(ID::D, param(ID::WIDTH));
1100 port(ID::Q, param(ID::WIDTH));
1101 check_expected();
1102 return;
1103 }
1104
1105 if (cell->type == ID($dffsr)) {
1106 param_bool(ID::CLK_POLARITY);
1107 param_bool(ID::SET_POLARITY);
1108 param_bool(ID::CLR_POLARITY);
1109 port(ID::CLK, 1);
1110 port(ID::SET, param(ID::WIDTH));
1111 port(ID::CLR, param(ID::WIDTH));
1112 port(ID::D, param(ID::WIDTH));
1113 port(ID::Q, param(ID::WIDTH));
1114 check_expected();
1115 return;
1116 }
1117
1118 if (cell->type == ID($adff)) {
1119 param_bool(ID::CLK_POLARITY);
1120 param_bool(ID::ARST_POLARITY);
1121 param_bits(ID::ARST_VALUE, param(ID::WIDTH));
1122 port(ID::CLK, 1);
1123 port(ID::ARST, 1);
1124 port(ID::D, param(ID::WIDTH));
1125 port(ID::Q, param(ID::WIDTH));
1126 check_expected();
1127 return;
1128 }
1129
1130 if (cell->type == ID($dlatch)) {
1131 param_bool(ID::EN_POLARITY);
1132 port(ID::EN, 1);
1133 port(ID::D, param(ID::WIDTH));
1134 port(ID::Q, param(ID::WIDTH));
1135 check_expected();
1136 return;
1137 }
1138
1139 if (cell->type == ID($dlatchsr)) {
1140 param_bool(ID::EN_POLARITY);
1141 param_bool(ID::SET_POLARITY);
1142 param_bool(ID::CLR_POLARITY);
1143 port(ID::EN, 1);
1144 port(ID::SET, param(ID::WIDTH));
1145 port(ID::CLR, param(ID::WIDTH));
1146 port(ID::D, param(ID::WIDTH));
1147 port(ID::Q, param(ID::WIDTH));
1148 check_expected();
1149 return;
1150 }
1151
1152 if (cell->type == ID($fsm)) {
1153 param(ID::NAME);
1154 param_bool(ID::CLK_POLARITY);
1155 param_bool(ID::ARST_POLARITY);
1156 param(ID::STATE_BITS);
1157 param(ID::STATE_NUM);
1158 param(ID::STATE_NUM_LOG2);
1159 param(ID::STATE_RST);
1160 param_bits(ID::STATE_TABLE, param(ID::STATE_BITS) * param(ID::STATE_NUM));
1161 param(ID::TRANS_NUM);
1162 param_bits(ID::TRANS_TABLE, param(ID::TRANS_NUM) * (2*param(ID::STATE_NUM_LOG2) + param(ID::CTRL_IN_WIDTH) + param(ID::CTRL_OUT_WIDTH)));
1163 port(ID::CLK, 1);
1164 port(ID::ARST, 1);
1165 port(ID::CTRL_IN, param(ID::CTRL_IN_WIDTH));
1166 port(ID::CTRL_OUT, param(ID::CTRL_OUT_WIDTH));
1167 check_expected();
1168 return;
1169 }
1170
1171 if (cell->type == ID($memrd)) {
1172 param(ID::MEMID);
1173 param_bool(ID::CLK_ENABLE);
1174 param_bool(ID::CLK_POLARITY);
1175 param_bool(ID::TRANSPARENT);
1176 port(ID::CLK, 1);
1177 port(ID::EN, 1);
1178 port(ID::ADDR, param(ID::ABITS));
1179 port(ID::DATA, param(ID::WIDTH));
1180 check_expected();
1181 return;
1182 }
1183
1184 if (cell->type == ID($memwr)) {
1185 param(ID::MEMID);
1186 param_bool(ID::CLK_ENABLE);
1187 param_bool(ID::CLK_POLARITY);
1188 param(ID::PRIORITY);
1189 port(ID::CLK, 1);
1190 port(ID::EN, param(ID::WIDTH));
1191 port(ID::ADDR, param(ID::ABITS));
1192 port(ID::DATA, param(ID::WIDTH));
1193 check_expected();
1194 return;
1195 }
1196
1197 if (cell->type == ID($meminit)) {
1198 param(ID::MEMID);
1199 param(ID::PRIORITY);
1200 port(ID::ADDR, param(ID::ABITS));
1201 port(ID::DATA, param(ID::WIDTH) * param(ID::WORDS));
1202 check_expected();
1203 return;
1204 }
1205
1206 if (cell->type == ID($mem)) {
1207 param(ID::MEMID);
1208 param(ID::SIZE);
1209 param(ID::OFFSET);
1210 param(ID::INIT);
1211 param_bits(ID::RD_CLK_ENABLE, max(1, param(ID::RD_PORTS)));
1212 param_bits(ID::RD_CLK_POLARITY, max(1, param(ID::RD_PORTS)));
1213 param_bits(ID::RD_TRANSPARENT, max(1, param(ID::RD_PORTS)));
1214 param_bits(ID::WR_CLK_ENABLE, max(1, param(ID::WR_PORTS)));
1215 param_bits(ID::WR_CLK_POLARITY, max(1, param(ID::WR_PORTS)));
1216 port(ID::RD_CLK, param(ID::RD_PORTS));
1217 port(ID::RD_EN, param(ID::RD_PORTS));
1218 port(ID::RD_ADDR, param(ID::RD_PORTS) * param(ID::ABITS));
1219 port(ID::RD_DATA, param(ID::RD_PORTS) * param(ID::WIDTH));
1220 port(ID::WR_CLK, param(ID::WR_PORTS));
1221 port(ID::WR_EN, param(ID::WR_PORTS) * param(ID::WIDTH));
1222 port(ID::WR_ADDR, param(ID::WR_PORTS) * param(ID::ABITS));
1223 port(ID::WR_DATA, param(ID::WR_PORTS) * param(ID::WIDTH));
1224 check_expected();
1225 return;
1226 }
1227
1228 if (cell->type == ID($tribuf)) {
1229 port(ID::A, param(ID::WIDTH));
1230 port(ID::Y, param(ID::WIDTH));
1231 port(ID::EN, 1);
1232 check_expected();
1233 return;
1234 }
1235
1236 if (cell->type.in(ID($assert), ID($assume), ID($live), ID($fair), ID($cover))) {
1237 port(ID::A, 1);
1238 port(ID::EN, 1);
1239 check_expected();
1240 return;
1241 }
1242
1243 if (cell->type == ID($initstate)) {
1244 port(ID::Y, 1);
1245 check_expected();
1246 return;
1247 }
1248
1249 if (cell->type.in(ID($anyconst), ID($anyseq), ID($allconst), ID($allseq))) {
1250 port(ID::Y, param(ID::WIDTH));
1251 check_expected();
1252 return;
1253 }
1254
1255 if (cell->type == ID($equiv)) {
1256 port(ID::A, 1);
1257 port(ID::B, 1);
1258 port(ID::Y, 1);
1259 check_expected();
1260 return;
1261 }
1262
1263 if (cell->type.in(ID($specify2), ID($specify3))) {
1264 param_bool(ID::FULL);
1265 param_bool(ID::SRC_DST_PEN);
1266 param_bool(ID::SRC_DST_POL);
1267 param(ID::T_RISE_MIN);
1268 param(ID::T_RISE_TYP);
1269 param(ID::T_RISE_MAX);
1270 param(ID::T_FALL_MIN);
1271 param(ID::T_FALL_TYP);
1272 param(ID::T_FALL_MAX);
1273 port(ID::EN, 1);
1274 port(ID::SRC, param(ID::SRC_WIDTH));
1275 port(ID::DST, param(ID::DST_WIDTH));
1276 if (cell->type == ID($specify3)) {
1277 param_bool(ID::EDGE_EN);
1278 param_bool(ID::EDGE_POL);
1279 param_bool(ID::DAT_DST_PEN);
1280 param_bool(ID::DAT_DST_POL);
1281 port(ID::DAT, param(ID::DST_WIDTH));
1282 }
1283 check_expected();
1284 return;
1285 }
1286
1287 if (cell->type == ID($specrule)) {
1288 param(ID::TYPE);
1289 param_bool(ID::SRC_PEN);
1290 param_bool(ID::SRC_POL);
1291 param_bool(ID::DST_PEN);
1292 param_bool(ID::DST_POL);
1293 param(ID::T_LIMIT_MIN);
1294 param(ID::T_LIMIT_TYP);
1295 param(ID::T_LIMIT_MAX);
1296 param(ID::T_LIMIT2_MIN);
1297 param(ID::T_LIMIT2_TYP);
1298 param(ID::T_LIMIT2_MAX);
1299 port(ID::SRC_EN, 1);
1300 port(ID::DST_EN, 1);
1301 port(ID::SRC, param(ID::SRC_WIDTH));
1302 port(ID::DST, param(ID::DST_WIDTH));
1303 check_expected();
1304 return;
1305 }
1306
1307 if (cell->type == ID($_BUF_)) { port(ID::A,1); port(ID::Y,1); check_expected(); return; }
1308 if (cell->type == ID($_NOT_)) { port(ID::A,1); port(ID::Y,1); check_expected(); return; }
1309 if (cell->type == ID($_AND_)) { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; }
1310 if (cell->type == ID($_NAND_)) { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; }
1311 if (cell->type == ID($_OR_)) { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; }
1312 if (cell->type == ID($_NOR_)) { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; }
1313 if (cell->type == ID($_XOR_)) { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; }
1314 if (cell->type == ID($_XNOR_)) { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; }
1315 if (cell->type == ID($_ANDNOT_)) { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; }
1316 if (cell->type == ID($_ORNOT_)) { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; }
1317 if (cell->type == ID($_MUX_)) { port(ID::A,1); port(ID::B,1); port(ID::S,1); port(ID::Y,1); check_expected(); return; }
1318 if (cell->type == ID($_NMUX_)) { port(ID::A,1); port(ID::B,1); port(ID::S,1); port(ID::Y,1); check_expected(); return; }
1319 if (cell->type == ID($_AOI3_)) { port(ID::A,1); port(ID::B,1); port(ID::C,1); port(ID::Y,1); check_expected(); return; }
1320 if (cell->type == ID($_OAI3_)) { port(ID::A,1); port(ID::B,1); port(ID::C,1); port(ID::Y,1); check_expected(); return; }
1321 if (cell->type == ID($_AOI4_)) { port(ID::A,1); port(ID::B,1); port(ID::C,1); port(ID::D,1); port(ID::Y,1); check_expected(); return; }
1322 if (cell->type == ID($_OAI4_)) { port(ID::A,1); port(ID::B,1); port(ID::C,1); port(ID::D,1); port(ID::Y,1); check_expected(); return; }
1323
1324 if (cell->type == ID($_TBUF_)) { port(ID::A,1); port(ID::Y,1); port(ID::E,1); check_expected(); return; }
1325
1326 if (cell->type == ID($_MUX4_)) { port(ID::A,1); port(ID::B,1); port(ID::C,1); port(ID::D,1); port(ID::S,1); port(ID::T,1); port(ID::Y,1); check_expected(); return; }
1327 if (cell->type == ID($_MUX8_)) { port(ID::A,1); port(ID::B,1); port(ID::C,1); port(ID::D,1); port(ID::E,1); port(ID::F,1); port(ID::G,1); port(ID::H,1); port(ID::S,1); port(ID::T,1); port(ID::U,1); port(ID::Y,1); check_expected(); return; }
1328 if (cell->type == ID($_MUX16_)) { port(ID::A,1); port(ID::B,1); port(ID::C,1); port(ID::D,1); port(ID::E,1); port(ID::F,1); port(ID::G,1); port(ID::H,1); port(ID::I,1); port(ID::J,1); port(ID::K,1); port(ID::L,1); port(ID::M,1); port(ID::N,1); port(ID::O,1); port(ID::P,1); port(ID::S,1); port(ID::T,1); port(ID::U,1); port(ID::V,1); port(ID::Y,1); check_expected(); return; }
1329
1330 if (cell->type == ID($_SR_NN_)) { port(ID::S,1); port(ID::R,1); port(ID::Q,1); check_expected(); return; }
1331 if (cell->type == ID($_SR_NP_)) { port(ID::S,1); port(ID::R,1); port(ID::Q,1); check_expected(); return; }
1332 if (cell->type == ID($_SR_PN_)) { port(ID::S,1); port(ID::R,1); port(ID::Q,1); check_expected(); return; }
1333 if (cell->type == ID($_SR_PP_)) { port(ID::S,1); port(ID::R,1); port(ID::Q,1); check_expected(); return; }
1334
1335 if (cell->type == ID($_FF_)) { port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1336 if (cell->type == ID($_DFF_N_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); check_expected(); return; }
1337 if (cell->type == ID($_DFF_P_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); check_expected(); return; }
1338
1339 if (cell->type == ID($_DFFE_NN_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::E,1); check_expected(); return; }
1340 if (cell->type == ID($_DFFE_NP_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::E,1); check_expected(); return; }
1341 if (cell->type == ID($_DFFE_PN_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::E,1); check_expected(); return; }
1342 if (cell->type == ID($_DFFE_PP_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::E,1); check_expected(); return; }
1343
1344 if (cell->type == ID($_DFF_NN0_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::R,1); check_expected(); return; }
1345 if (cell->type == ID($_DFF_NN1_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::R,1); check_expected(); return; }
1346 if (cell->type == ID($_DFF_NP0_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::R,1); check_expected(); return; }
1347 if (cell->type == ID($_DFF_NP1_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::R,1); check_expected(); return; }
1348 if (cell->type == ID($_DFF_PN0_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::R,1); check_expected(); return; }
1349 if (cell->type == ID($_DFF_PN1_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::R,1); check_expected(); return; }
1350 if (cell->type == ID($_DFF_PP0_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::R,1); check_expected(); return; }
1351 if (cell->type == ID($_DFF_PP1_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::R,1); check_expected(); return; }
1352
1353 if (cell->type == ID($_DFFSR_NNN_)) { port(ID::C,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1354 if (cell->type == ID($_DFFSR_NNP_)) { port(ID::C,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1355 if (cell->type == ID($_DFFSR_NPN_)) { port(ID::C,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1356 if (cell->type == ID($_DFFSR_NPP_)) { port(ID::C,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1357 if (cell->type == ID($_DFFSR_PNN_)) { port(ID::C,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1358 if (cell->type == ID($_DFFSR_PNP_)) { port(ID::C,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1359 if (cell->type == ID($_DFFSR_PPN_)) { port(ID::C,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1360 if (cell->type == ID($_DFFSR_PPP_)) { port(ID::C,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1361
1362 if (cell->type == ID($_DLATCH_N_)) { port(ID::E,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1363 if (cell->type == ID($_DLATCH_P_)) { port(ID::E,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1364
1365 if (cell->type == ID($_DLATCHSR_NNN_)) { port(ID::E,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1366 if (cell->type == ID($_DLATCHSR_NNP_)) { port(ID::E,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1367 if (cell->type == ID($_DLATCHSR_NPN_)) { port(ID::E,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1368 if (cell->type == ID($_DLATCHSR_NPP_)) { port(ID::E,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1369 if (cell->type == ID($_DLATCHSR_PNN_)) { port(ID::E,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1370 if (cell->type == ID($_DLATCHSR_PNP_)) { port(ID::E,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1371 if (cell->type == ID($_DLATCHSR_PPN_)) { port(ID::E,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1372 if (cell->type == ID($_DLATCHSR_PPP_)) { port(ID::E,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
1373
1374 error(__LINE__);
1375 }
1376 };
1377 }
1378 #endif
1379
1380 void RTLIL::Module::sort()
1381 {
1382 wires_.sort(sort_by_id_str());
1383 cells_.sort(sort_by_id_str());
1384 avail_parameters.sort(sort_by_id_str());
1385 memories.sort(sort_by_id_str());
1386 processes.sort(sort_by_id_str());
1387 for (auto &it : cells_)
1388 it.second->sort();
1389 for (auto &it : wires_)
1390 it.second->attributes.sort(sort_by_id_str());
1391 for (auto &it : memories)
1392 it.second->attributes.sort(sort_by_id_str());
1393 }
1394
1395 void RTLIL::Module::check()
1396 {
1397 #ifndef NDEBUG
1398 std::vector<bool> ports_declared;
1399 for (auto &it : wires_) {
1400 log_assert(this == it.second->module);
1401 log_assert(it.first == it.second->name);
1402 log_assert(!it.first.empty());
1403 log_assert(it.second->width >= 0);
1404 log_assert(it.second->port_id >= 0);
1405 for (auto &it2 : it.second->attributes)
1406 log_assert(!it2.first.empty());
1407 if (it.second->port_id) {
1408 log_assert(GetSize(ports) >= it.second->port_id);
1409 log_assert(ports.at(it.second->port_id-1) == it.first);
1410 log_assert(it.second->port_input || it.second->port_output);
1411 if (GetSize(ports_declared) < it.second->port_id)
1412 ports_declared.resize(it.second->port_id);
1413 log_assert(ports_declared[it.second->port_id-1] == false);
1414 ports_declared[it.second->port_id-1] = true;
1415 } else
1416 log_assert(!it.second->port_input && !it.second->port_output);
1417 }
1418 for (auto port_declared : ports_declared)
1419 log_assert(port_declared == true);
1420 log_assert(GetSize(ports) == GetSize(ports_declared));
1421
1422 for (auto &it : memories) {
1423 log_assert(it.first == it.second->name);
1424 log_assert(!it.first.empty());
1425 log_assert(it.second->width >= 0);
1426 log_assert(it.second->size >= 0);
1427 for (auto &it2 : it.second->attributes)
1428 log_assert(!it2.first.empty());
1429 }
1430
1431 for (auto &it : cells_) {
1432 log_assert(this == it.second->module);
1433 log_assert(it.first == it.second->name);
1434 log_assert(!it.first.empty());
1435 log_assert(!it.second->type.empty());
1436 for (auto &it2 : it.second->connections()) {
1437 log_assert(!it2.first.empty());
1438 it2.second.check();
1439 }
1440 for (auto &it2 : it.second->attributes)
1441 log_assert(!it2.first.empty());
1442 for (auto &it2 : it.second->parameters)
1443 log_assert(!it2.first.empty());
1444 InternalCellChecker checker(this, it.second);
1445 checker.check();
1446 }
1447
1448 for (auto &it : processes) {
1449 log_assert(it.first == it.second->name);
1450 log_assert(!it.first.empty());
1451 log_assert(it.second->root_case.compare.empty());
1452 std::vector<CaseRule*> all_cases = {&it.second->root_case};
1453 for (size_t i = 0; i < all_cases.size(); i++) {
1454 for (auto &switch_it : all_cases[i]->switches) {
1455 for (auto &case_it : switch_it->cases) {
1456 for (auto &compare_it : case_it->compare) {
1457 log_assert(switch_it->signal.size() == compare_it.size());
1458 }
1459 all_cases.push_back(case_it);
1460 }
1461 }
1462 }
1463 for (auto &sync_it : it.second->syncs) {
1464 switch (sync_it->type) {
1465 case SyncType::ST0:
1466 case SyncType::ST1:
1467 case SyncType::STp:
1468 case SyncType::STn:
1469 case SyncType::STe:
1470 log_assert(!sync_it->signal.empty());
1471 break;
1472 case SyncType::STa:
1473 case SyncType::STg:
1474 case SyncType::STi:
1475 log_assert(sync_it->signal.empty());
1476 break;
1477 }
1478 }
1479 }
1480
1481 for (auto &it : connections_) {
1482 log_assert(it.first.size() == it.second.size());
1483 log_assert(!it.first.has_const());
1484 it.first.check();
1485 it.second.check();
1486 }
1487
1488 for (auto &it : attributes)
1489 log_assert(!it.first.empty());
1490 #endif
1491 }
1492
1493 void RTLIL::Module::optimize()
1494 {
1495 }
1496
1497 void RTLIL::Module::cloneInto(RTLIL::Module *new_mod) const
1498 {
1499 log_assert(new_mod->refcount_wires_ == 0);
1500 log_assert(new_mod->refcount_cells_ == 0);
1501
1502 new_mod->avail_parameters = avail_parameters;
1503
1504 for (auto &conn : connections_)
1505 new_mod->connect(conn);
1506
1507 for (auto &attr : attributes)
1508 new_mod->attributes[attr.first] = attr.second;
1509
1510 for (auto &it : wires_)
1511 new_mod->addWire(it.first, it.second);
1512
1513 for (auto &it : memories)
1514 new_mod->memories[it.first] = new RTLIL::Memory(*it.second);
1515
1516 for (auto &it : cells_)
1517 new_mod->addCell(it.first, it.second);
1518
1519 for (auto &it : processes)
1520 new_mod->processes[it.first] = it.second->clone();
1521
1522 struct RewriteSigSpecWorker
1523 {
1524 RTLIL::Module *mod;
1525 void operator()(RTLIL::SigSpec &sig)
1526 {
1527 sig.pack();
1528 for (auto &c : sig.chunks_)
1529 if (c.wire != NULL)
1530 c.wire = mod->wires_.at(c.wire->name);
1531 }
1532 };
1533
1534 RewriteSigSpecWorker rewriteSigSpecWorker;
1535 rewriteSigSpecWorker.mod = new_mod;
1536 new_mod->rewrite_sigspecs(rewriteSigSpecWorker);
1537 new_mod->fixup_ports();
1538 }
1539
1540 RTLIL::Module *RTLIL::Module::clone() const
1541 {
1542 RTLIL::Module *new_mod = new RTLIL::Module;
1543 new_mod->name = name;
1544 cloneInto(new_mod);
1545 return new_mod;
1546 }
1547
1548 bool RTLIL::Module::has_memories() const
1549 {
1550 return !memories.empty();
1551 }
1552
1553 bool RTLIL::Module::has_processes() const
1554 {
1555 return !processes.empty();
1556 }
1557
1558 bool RTLIL::Module::has_memories_warn() const
1559 {
1560 if (!memories.empty())
1561 log_warning("Ignoring module %s because it contains memories (run 'memory' command first).\n", log_id(this));
1562 return !memories.empty();
1563 }
1564
1565 bool RTLIL::Module::has_processes_warn() const
1566 {
1567 if (!processes.empty())
1568 log_warning("Ignoring module %s because it contains processes (run 'proc' command first).\n", log_id(this));
1569 return !processes.empty();
1570 }
1571
1572 std::vector<RTLIL::Wire*> RTLIL::Module::selected_wires() const
1573 {
1574 std::vector<RTLIL::Wire*> result;
1575 result.reserve(wires_.size());
1576 for (auto &it : wires_)
1577 if (design->selected(this, it.second))
1578 result.push_back(it.second);
1579 return result;
1580 }
1581
1582 std::vector<RTLIL::Cell*> RTLIL::Module::selected_cells() const
1583 {
1584 std::vector<RTLIL::Cell*> result;
1585 result.reserve(cells_.size());
1586 for (auto &it : cells_)
1587 if (design->selected(this, it.second))
1588 result.push_back(it.second);
1589 return result;
1590 }
1591
1592 void RTLIL::Module::add(RTLIL::Wire *wire)
1593 {
1594 log_assert(!wire->name.empty());
1595 log_assert(count_id(wire->name) == 0);
1596 log_assert(refcount_wires_ == 0);
1597 wires_[wire->name] = wire;
1598 wire->module = this;
1599 }
1600
1601 void RTLIL::Module::add(RTLIL::Cell *cell)
1602 {
1603 log_assert(!cell->name.empty());
1604 log_assert(count_id(cell->name) == 0);
1605 log_assert(refcount_cells_ == 0);
1606 cells_[cell->name] = cell;
1607 cell->module = this;
1608 }
1609
1610 void RTLIL::Module::remove(const pool<RTLIL::Wire*> &wires)
1611 {
1612 log_assert(refcount_wires_ == 0);
1613
1614 struct DeleteWireWorker
1615 {
1616 RTLIL::Module *module;
1617 const pool<RTLIL::Wire*> *wires_p;
1618
1619 void operator()(RTLIL::SigSpec &sig) {
1620 sig.pack();
1621 for (auto &c : sig.chunks_)
1622 if (c.wire != NULL && wires_p->count(c.wire)) {
1623 c.wire = module->addWire(NEW_ID, c.width);
1624 c.offset = 0;
1625 }
1626 }
1627
1628 void operator()(RTLIL::SigSpec &lhs, RTLIL::SigSpec &rhs) {
1629 log_assert(GetSize(lhs) == GetSize(rhs));
1630 lhs.unpack();
1631 rhs.unpack();
1632 for (int i = 0; i < GetSize(lhs); i++) {
1633 RTLIL::SigBit &lhs_bit = lhs.bits_[i];
1634 RTLIL::SigBit &rhs_bit = rhs.bits_[i];
1635 if ((lhs_bit.wire != nullptr && wires_p->count(lhs_bit.wire)) || (rhs_bit.wire != nullptr && wires_p->count(rhs_bit.wire))) {
1636 lhs_bit = State::Sx;
1637 rhs_bit = State::Sx;
1638 }
1639 }
1640 }
1641 };
1642
1643 DeleteWireWorker delete_wire_worker;
1644 delete_wire_worker.module = this;
1645 delete_wire_worker.wires_p = &wires;
1646 rewrite_sigspecs2(delete_wire_worker);
1647
1648 for (auto &it : wires) {
1649 log_assert(wires_.count(it->name) != 0);
1650 wires_.erase(it->name);
1651 delete it;
1652 }
1653 }
1654
1655 void RTLIL::Module::remove(RTLIL::Cell *cell)
1656 {
1657 while (!cell->connections_.empty())
1658 cell->unsetPort(cell->connections_.begin()->first);
1659
1660 log_assert(cells_.count(cell->name) != 0);
1661 log_assert(refcount_cells_ == 0);
1662 cells_.erase(cell->name);
1663 delete cell;
1664 }
1665
1666 void RTLIL::Module::rename(RTLIL::Wire *wire, RTLIL::IdString new_name)
1667 {
1668 log_assert(wires_[wire->name] == wire);
1669 log_assert(refcount_wires_ == 0);
1670 wires_.erase(wire->name);
1671 wire->name = new_name;
1672 add(wire);
1673 }
1674
1675 void RTLIL::Module::rename(RTLIL::Cell *cell, RTLIL::IdString new_name)
1676 {
1677 log_assert(cells_[cell->name] == cell);
1678 log_assert(refcount_wires_ == 0);
1679 cells_.erase(cell->name);
1680 cell->name = new_name;
1681 add(cell);
1682 }
1683
1684 void RTLIL::Module::rename(RTLIL::IdString old_name, RTLIL::IdString new_name)
1685 {
1686 log_assert(count_id(old_name) != 0);
1687 if (wires_.count(old_name))
1688 rename(wires_.at(old_name), new_name);
1689 else if (cells_.count(old_name))
1690 rename(cells_.at(old_name), new_name);
1691 else
1692 log_abort();
1693 }
1694
1695 void RTLIL::Module::swap_names(RTLIL::Wire *w1, RTLIL::Wire *w2)
1696 {
1697 log_assert(wires_[w1->name] == w1);
1698 log_assert(wires_[w2->name] == w2);
1699 log_assert(refcount_wires_ == 0);
1700
1701 wires_.erase(w1->name);
1702 wires_.erase(w2->name);
1703
1704 std::swap(w1->name, w2->name);
1705
1706 wires_[w1->name] = w1;
1707 wires_[w2->name] = w2;
1708 }
1709
1710 void RTLIL::Module::swap_names(RTLIL::Cell *c1, RTLIL::Cell *c2)
1711 {
1712 log_assert(cells_[c1->name] == c1);
1713 log_assert(cells_[c2->name] == c2);
1714 log_assert(refcount_cells_ == 0);
1715
1716 cells_.erase(c1->name);
1717 cells_.erase(c2->name);
1718
1719 std::swap(c1->name, c2->name);
1720
1721 cells_[c1->name] = c1;
1722 cells_[c2->name] = c2;
1723 }
1724
1725 RTLIL::IdString RTLIL::Module::uniquify(RTLIL::IdString name)
1726 {
1727 int index = 0;
1728 return uniquify(name, index);
1729 }
1730
1731 RTLIL::IdString RTLIL::Module::uniquify(RTLIL::IdString name, int &index)
1732 {
1733 if (index == 0) {
1734 if (count_id(name) == 0)
1735 return name;
1736 index++;
1737 }
1738
1739 while (1) {
1740 RTLIL::IdString new_name = stringf("%s_%d", name.c_str(), index);
1741 if (count_id(new_name) == 0)
1742 return new_name;
1743 index++;
1744 }
1745 }
1746
1747 static bool fixup_ports_compare(const RTLIL::Wire *a, const RTLIL::Wire *b)
1748 {
1749 if (a->port_id && !b->port_id)
1750 return true;
1751 if (!a->port_id && b->port_id)
1752 return false;
1753
1754 if (a->port_id == b->port_id)
1755 return a->name < b->name;
1756 return a->port_id < b->port_id;
1757 }
1758
1759 void RTLIL::Module::connect(const RTLIL::SigSig &conn)
1760 {
1761 for (auto mon : monitors)
1762 mon->notify_connect(this, conn);
1763
1764 if (design)
1765 for (auto mon : design->monitors)
1766 mon->notify_connect(this, conn);
1767
1768 // ignore all attempts to assign constants to other constants
1769 if (conn.first.has_const()) {
1770 RTLIL::SigSig new_conn;
1771 for (int i = 0; i < GetSize(conn.first); i++)
1772 if (conn.first[i].wire) {
1773 new_conn.first.append(conn.first[i]);
1774 new_conn.second.append(conn.second[i]);
1775 }
1776 if (GetSize(new_conn.first))
1777 connect(new_conn);
1778 return;
1779 }
1780
1781 if (yosys_xtrace) {
1782 log("#X# Connect (SigSig) in %s: %s = %s (%d bits)\n", log_id(this), log_signal(conn.first), log_signal(conn.second), GetSize(conn.first));
1783 log_backtrace("-X- ", yosys_xtrace-1);
1784 }
1785
1786 log_assert(GetSize(conn.first) == GetSize(conn.second));
1787 connections_.push_back(conn);
1788 }
1789
1790 void RTLIL::Module::connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs)
1791 {
1792 connect(RTLIL::SigSig(lhs, rhs));
1793 }
1794
1795 void RTLIL::Module::new_connections(const std::vector<RTLIL::SigSig> &new_conn)
1796 {
1797 for (auto mon : monitors)
1798 mon->notify_connect(this, new_conn);
1799
1800 if (design)
1801 for (auto mon : design->monitors)
1802 mon->notify_connect(this, new_conn);
1803
1804 if (yosys_xtrace) {
1805 log("#X# New connections vector in %s:\n", log_id(this));
1806 for (auto &conn: new_conn)
1807 log("#X# %s = %s (%d bits)\n", log_signal(conn.first), log_signal(conn.second), GetSize(conn.first));
1808 log_backtrace("-X- ", yosys_xtrace-1);
1809 }
1810
1811 connections_ = new_conn;
1812 }
1813
1814 const std::vector<RTLIL::SigSig> &RTLIL::Module::connections() const
1815 {
1816 return connections_;
1817 }
1818
1819 void RTLIL::Module::fixup_ports()
1820 {
1821 std::vector<RTLIL::Wire*> all_ports;
1822
1823 for (auto &w : wires_)
1824 if (w.second->port_input || w.second->port_output)
1825 all_ports.push_back(w.second);
1826 else
1827 w.second->port_id = 0;
1828
1829 std::sort(all_ports.begin(), all_ports.end(), fixup_ports_compare);
1830
1831 ports.clear();
1832 for (size_t i = 0; i < all_ports.size(); i++) {
1833 ports.push_back(all_ports[i]->name);
1834 all_ports[i]->port_id = i+1;
1835 }
1836 }
1837
1838 RTLIL::Wire *RTLIL::Module::addWire(RTLIL::IdString name, int width)
1839 {
1840 RTLIL::Wire *wire = new RTLIL::Wire;
1841 wire->name = name;
1842 wire->width = width;
1843 add(wire);
1844 return wire;
1845 }
1846
1847 RTLIL::Wire *RTLIL::Module::addWire(RTLIL::IdString name, const RTLIL::Wire *other)
1848 {
1849 RTLIL::Wire *wire = addWire(name);
1850 wire->width = other->width;
1851 wire->start_offset = other->start_offset;
1852 wire->port_id = other->port_id;
1853 wire->port_input = other->port_input;
1854 wire->port_output = other->port_output;
1855 wire->upto = other->upto;
1856 wire->attributes = other->attributes;
1857 return wire;
1858 }
1859
1860 RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, RTLIL::IdString type)
1861 {
1862 RTLIL::Cell *cell = new RTLIL::Cell;
1863 cell->name = name;
1864 cell->type = type;
1865 add(cell);
1866 return cell;
1867 }
1868
1869 RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, const RTLIL::Cell *other)
1870 {
1871 RTLIL::Cell *cell = addCell(name, other->type);
1872 cell->connections_ = other->connections_;
1873 cell->parameters = other->parameters;
1874 cell->attributes = other->attributes;
1875 return cell;
1876 }
1877
1878 #define DEF_METHOD(_func, _y_size, _type) \
1879 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed, const std::string &src) { \
1880 RTLIL::Cell *cell = addCell(name, _type); \
1881 cell->parameters[ID::A_SIGNED] = is_signed; \
1882 cell->parameters[ID::A_WIDTH] = sig_a.size(); \
1883 cell->parameters[ID::Y_WIDTH] = sig_y.size(); \
1884 cell->setPort(ID::A, sig_a); \
1885 cell->setPort(ID::Y, sig_y); \
1886 cell->set_src_attribute(src); \
1887 return cell; \
1888 } \
1889 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed, const std::string &src) { \
1890 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
1891 add ## _func(name, sig_a, sig_y, is_signed, src); \
1892 return sig_y; \
1893 }
1894 DEF_METHOD(Not, sig_a.size(), ID($not))
1895 DEF_METHOD(Pos, sig_a.size(), ID($pos))
1896 DEF_METHOD(Neg, sig_a.size(), ID($neg))
1897 DEF_METHOD(ReduceAnd, 1, ID($reduce_and))
1898 DEF_METHOD(ReduceOr, 1, ID($reduce_or))
1899 DEF_METHOD(ReduceXor, 1, ID($reduce_xor))
1900 DEF_METHOD(ReduceXnor, 1, ID($reduce_xnor))
1901 DEF_METHOD(ReduceBool, 1, ID($reduce_bool))
1902 DEF_METHOD(LogicNot, 1, ID($logic_not))
1903 #undef DEF_METHOD
1904
1905 #define DEF_METHOD(_func, _y_size, _type) \
1906 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed, const std::string &src) { \
1907 RTLIL::Cell *cell = addCell(name, _type); \
1908 cell->parameters[ID::A_SIGNED] = is_signed; \
1909 cell->parameters[ID::B_SIGNED] = is_signed; \
1910 cell->parameters[ID::A_WIDTH] = sig_a.size(); \
1911 cell->parameters[ID::B_WIDTH] = sig_b.size(); \
1912 cell->parameters[ID::Y_WIDTH] = sig_y.size(); \
1913 cell->setPort(ID::A, sig_a); \
1914 cell->setPort(ID::B, sig_b); \
1915 cell->setPort(ID::Y, sig_y); \
1916 cell->set_src_attribute(src); \
1917 return cell; \
1918 } \
1919 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed, const std::string &src) { \
1920 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
1921 add ## _func(name, sig_a, sig_b, sig_y, is_signed, src); \
1922 return sig_y; \
1923 }
1924 DEF_METHOD(And, max(sig_a.size(), sig_b.size()), ID($and))
1925 DEF_METHOD(Or, max(sig_a.size(), sig_b.size()), ID($or))
1926 DEF_METHOD(Xor, max(sig_a.size(), sig_b.size()), ID($xor))
1927 DEF_METHOD(Xnor, max(sig_a.size(), sig_b.size()), ID($xnor))
1928 DEF_METHOD(Shift, sig_a.size(), ID($shift))
1929 DEF_METHOD(Shiftx, sig_a.size(), ID($shiftx))
1930 DEF_METHOD(Lt, 1, ID($lt))
1931 DEF_METHOD(Le, 1, ID($le))
1932 DEF_METHOD(Eq, 1, ID($eq))
1933 DEF_METHOD(Ne, 1, ID($ne))
1934 DEF_METHOD(Eqx, 1, ID($eqx))
1935 DEF_METHOD(Nex, 1, ID($nex))
1936 DEF_METHOD(Ge, 1, ID($ge))
1937 DEF_METHOD(Gt, 1, ID($gt))
1938 DEF_METHOD(Add, max(sig_a.size(), sig_b.size()), ID($add))
1939 DEF_METHOD(Sub, max(sig_a.size(), sig_b.size()), ID($sub))
1940 DEF_METHOD(Mul, max(sig_a.size(), sig_b.size()), ID($mul))
1941 DEF_METHOD(Div, max(sig_a.size(), sig_b.size()), ID($div))
1942 DEF_METHOD(Mod, max(sig_a.size(), sig_b.size()), ID($mod))
1943 DEF_METHOD(LogicAnd, 1, ID($logic_and))
1944 DEF_METHOD(LogicOr, 1, ID($logic_or))
1945 #undef DEF_METHOD
1946
1947 #define DEF_METHOD(_func, _y_size, _type) \
1948 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed, const std::string &src) { \
1949 RTLIL::Cell *cell = addCell(name, _type); \
1950 cell->parameters[ID::A_SIGNED] = is_signed; \
1951 cell->parameters[ID::B_SIGNED] = false; \
1952 cell->parameters[ID::A_WIDTH] = sig_a.size(); \
1953 cell->parameters[ID::B_WIDTH] = sig_b.size(); \
1954 cell->parameters[ID::Y_WIDTH] = sig_y.size(); \
1955 cell->setPort(ID::A, sig_a); \
1956 cell->setPort(ID::B, sig_b); \
1957 cell->setPort(ID::Y, sig_y); \
1958 cell->set_src_attribute(src); \
1959 return cell; \
1960 } \
1961 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed, const std::string &src) { \
1962 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
1963 add ## _func(name, sig_a, sig_b, sig_y, is_signed, src); \
1964 return sig_y; \
1965 }
1966 DEF_METHOD(Shl, sig_a.size(), ID($shl))
1967 DEF_METHOD(Shr, sig_a.size(), ID($shr))
1968 DEF_METHOD(Sshl, sig_a.size(), ID($sshl))
1969 DEF_METHOD(Sshr, sig_a.size(), ID($sshr))
1970 #undef DEF_METHOD
1971
1972 #define DEF_METHOD(_func, _type, _pmux) \
1973 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, const std::string &src) { \
1974 RTLIL::Cell *cell = addCell(name, _type); \
1975 cell->parameters[ID::WIDTH] = sig_a.size(); \
1976 if (_pmux) cell->parameters[ID::S_WIDTH] = sig_s.size(); \
1977 cell->setPort(ID::A, sig_a); \
1978 cell->setPort(ID::B, sig_b); \
1979 cell->setPort(ID::S, sig_s); \
1980 cell->setPort(ID::Y, sig_y); \
1981 cell->set_src_attribute(src); \
1982 return cell; \
1983 } \
1984 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const std::string &src) { \
1985 RTLIL::SigSpec sig_y = addWire(NEW_ID, sig_a.size()); \
1986 add ## _func(name, sig_a, sig_b, sig_s, sig_y, src); \
1987 return sig_y; \
1988 }
1989 DEF_METHOD(Mux, ID($mux), 0)
1990 DEF_METHOD(Pmux, ID($pmux), 1)
1991 #undef DEF_METHOD
1992
1993 #define DEF_METHOD_2(_func, _type, _P1, _P2) \
1994 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const std::string &src) { \
1995 RTLIL::Cell *cell = addCell(name, _type); \
1996 cell->setPort("\\" #_P1, sig1); \
1997 cell->setPort("\\" #_P2, sig2); \
1998 cell->set_src_attribute(src); \
1999 return cell; \
2000 } \
2001 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const std::string &src) { \
2002 RTLIL::SigBit sig2 = addWire(NEW_ID); \
2003 add ## _func(name, sig1, sig2, src); \
2004 return sig2; \
2005 }
2006 #define DEF_METHOD_3(_func, _type, _P1, _P2, _P3) \
2007 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const RTLIL::SigBit &sig3, const std::string &src) { \
2008 RTLIL::Cell *cell = addCell(name, _type); \
2009 cell->setPort("\\" #_P1, sig1); \
2010 cell->setPort("\\" #_P2, sig2); \
2011 cell->setPort("\\" #_P3, sig3); \
2012 cell->set_src_attribute(src); \
2013 return cell; \
2014 } \
2015 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const std::string &src) { \
2016 RTLIL::SigBit sig3 = addWire(NEW_ID); \
2017 add ## _func(name, sig1, sig2, sig3, src); \
2018 return sig3; \
2019 }
2020 #define DEF_METHOD_4(_func, _type, _P1, _P2, _P3, _P4) \
2021 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const RTLIL::SigBit &sig3, const RTLIL::SigBit &sig4, const std::string &src) { \
2022 RTLIL::Cell *cell = addCell(name, _type); \
2023 cell->setPort("\\" #_P1, sig1); \
2024 cell->setPort("\\" #_P2, sig2); \
2025 cell->setPort("\\" #_P3, sig3); \
2026 cell->setPort("\\" #_P4, sig4); \
2027 cell->set_src_attribute(src); \
2028 return cell; \
2029 } \
2030 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const RTLIL::SigBit &sig3, const std::string &src) { \
2031 RTLIL::SigBit sig4 = addWire(NEW_ID); \
2032 add ## _func(name, sig1, sig2, sig3, sig4, src); \
2033 return sig4; \
2034 }
2035 #define DEF_METHOD_5(_func, _type, _P1, _P2, _P3, _P4, _P5) \
2036 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const RTLIL::SigBit &sig3, const RTLIL::SigBit &sig4, const RTLIL::SigBit &sig5, const std::string &src) { \
2037 RTLIL::Cell *cell = addCell(name, _type); \
2038 cell->setPort("\\" #_P1, sig1); \
2039 cell->setPort("\\" #_P2, sig2); \
2040 cell->setPort("\\" #_P3, sig3); \
2041 cell->setPort("\\" #_P4, sig4); \
2042 cell->setPort("\\" #_P5, sig5); \
2043 cell->set_src_attribute(src); \
2044 return cell; \
2045 } \
2046 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const RTLIL::SigBit &sig3, const RTLIL::SigBit &sig4, const std::string &src) { \
2047 RTLIL::SigBit sig5 = addWire(NEW_ID); \
2048 add ## _func(name, sig1, sig2, sig3, sig4, sig5, src); \
2049 return sig5; \
2050 }
2051 DEF_METHOD_2(BufGate, ID($_BUF_), A, Y)
2052 DEF_METHOD_2(NotGate, ID($_NOT_), A, Y)
2053 DEF_METHOD_3(AndGate, ID($_AND_), A, B, Y)
2054 DEF_METHOD_3(NandGate, ID($_NAND_), A, B, Y)
2055 DEF_METHOD_3(OrGate, ID($_OR_), A, B, Y)
2056 DEF_METHOD_3(NorGate, ID($_NOR_), A, B, Y)
2057 DEF_METHOD_3(XorGate, ID($_XOR_), A, B, Y)
2058 DEF_METHOD_3(XnorGate, ID($_XNOR_), A, B, Y)
2059 DEF_METHOD_3(AndnotGate, ID($_ANDNOT_), A, B, Y)
2060 DEF_METHOD_3(OrnotGate, ID($_ORNOT_), A, B, Y)
2061 DEF_METHOD_4(MuxGate, ID($_MUX_), A, B, S, Y)
2062 DEF_METHOD_4(NmuxGate, ID($_NMUX_), A, B, S, Y)
2063 DEF_METHOD_4(Aoi3Gate, ID($_AOI3_), A, B, C, Y)
2064 DEF_METHOD_4(Oai3Gate, ID($_OAI3_), A, B, C, Y)
2065 DEF_METHOD_5(Aoi4Gate, ID($_AOI4_), A, B, C, D, Y)
2066 DEF_METHOD_5(Oai4Gate, ID($_OAI4_), A, B, C, D, Y)
2067 #undef DEF_METHOD_2
2068 #undef DEF_METHOD_3
2069 #undef DEF_METHOD_4
2070 #undef DEF_METHOD_5
2071
2072 RTLIL::Cell* RTLIL::Module::addPow(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool a_signed, bool b_signed, const std::string &src)
2073 {
2074 RTLIL::Cell *cell = addCell(name, ID($pow));
2075 cell->parameters[ID::A_SIGNED] = a_signed;
2076 cell->parameters[ID::B_SIGNED] = b_signed;
2077 cell->parameters[ID::A_WIDTH] = sig_a.size();
2078 cell->parameters[ID::B_WIDTH] = sig_b.size();
2079 cell->parameters[ID::Y_WIDTH] = sig_y.size();
2080 cell->setPort(ID::A, sig_a);
2081 cell->setPort(ID::B, sig_b);
2082 cell->setPort(ID::Y, sig_y);
2083 cell->set_src_attribute(src);
2084 return cell;
2085 }
2086
2087 RTLIL::Cell* RTLIL::Module::addSlice(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, RTLIL::Const offset, const std::string &src)
2088 {
2089 RTLIL::Cell *cell = addCell(name, ID($slice));
2090 cell->parameters[ID::A_WIDTH] = sig_a.size();
2091 cell->parameters[ID::Y_WIDTH] = sig_y.size();
2092 cell->parameters[ID::OFFSET] = offset;
2093 cell->setPort(ID::A, sig_a);
2094 cell->setPort(ID::Y, sig_y);
2095 cell->set_src_attribute(src);
2096 return cell;
2097 }
2098
2099 RTLIL::Cell* RTLIL::Module::addConcat(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, const std::string &src)
2100 {
2101 RTLIL::Cell *cell = addCell(name, ID($concat));
2102 cell->parameters[ID::A_WIDTH] = sig_a.size();
2103 cell->parameters[ID::B_WIDTH] = sig_b.size();
2104 cell->setPort(ID::A, sig_a);
2105 cell->setPort(ID::B, sig_b);
2106 cell->setPort(ID::Y, sig_y);
2107 cell->set_src_attribute(src);
2108 return cell;
2109 }
2110
2111 RTLIL::Cell* RTLIL::Module::addLut(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, RTLIL::Const lut, const std::string &src)
2112 {
2113 RTLIL::Cell *cell = addCell(name, ID($lut));
2114 cell->parameters[ID::LUT] = lut;
2115 cell->parameters[ID::WIDTH] = sig_a.size();
2116 cell->setPort(ID::A, sig_a);
2117 cell->setPort(ID::Y, sig_y);
2118 cell->set_src_attribute(src);
2119 return cell;
2120 }
2121
2122 RTLIL::Cell* RTLIL::Module::addTribuf(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_y, const std::string &src)
2123 {
2124 RTLIL::Cell *cell = addCell(name, ID($tribuf));
2125 cell->parameters[ID::WIDTH] = sig_a.size();
2126 cell->setPort(ID::A, sig_a);
2127 cell->setPort(ID::EN, sig_en);
2128 cell->setPort(ID::Y, sig_y);
2129 cell->set_src_attribute(src);
2130 return cell;
2131 }
2132
2133 RTLIL::Cell* RTLIL::Module::addAssert(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src)
2134 {
2135 RTLIL::Cell *cell = addCell(name, ID($assert));
2136 cell->setPort(ID::A, sig_a);
2137 cell->setPort(ID::EN, sig_en);
2138 cell->set_src_attribute(src);
2139 return cell;
2140 }
2141
2142 RTLIL::Cell* RTLIL::Module::addAssume(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src)
2143 {
2144 RTLIL::Cell *cell = addCell(name, ID($assume));
2145 cell->setPort(ID::A, sig_a);
2146 cell->setPort(ID::EN, sig_en);
2147 cell->set_src_attribute(src);
2148 return cell;
2149 }
2150
2151 RTLIL::Cell* RTLIL::Module::addLive(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src)
2152 {
2153 RTLIL::Cell *cell = addCell(name, ID($live));
2154 cell->setPort(ID::A, sig_a);
2155 cell->setPort(ID::EN, sig_en);
2156 cell->set_src_attribute(src);
2157 return cell;
2158 }
2159
2160 RTLIL::Cell* RTLIL::Module::addFair(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src)
2161 {
2162 RTLIL::Cell *cell = addCell(name, ID($fair));
2163 cell->setPort(ID::A, sig_a);
2164 cell->setPort(ID::EN, sig_en);
2165 cell->set_src_attribute(src);
2166 return cell;
2167 }
2168
2169 RTLIL::Cell* RTLIL::Module::addCover(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const std::string &src)
2170 {
2171 RTLIL::Cell *cell = addCell(name, ID($cover));
2172 cell->setPort(ID::A, sig_a);
2173 cell->setPort(ID::EN, sig_en);
2174 cell->set_src_attribute(src);
2175 return cell;
2176 }
2177
2178 RTLIL::Cell* RTLIL::Module::addEquiv(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, const std::string &src)
2179 {
2180 RTLIL::Cell *cell = addCell(name, ID($equiv));
2181 cell->setPort(ID::A, sig_a);
2182 cell->setPort(ID::B, sig_b);
2183 cell->setPort(ID::Y, sig_y);
2184 cell->set_src_attribute(src);
2185 return cell;
2186 }
2187
2188 RTLIL::Cell* RTLIL::Module::addSr(RTLIL::IdString name, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, const RTLIL::SigSpec &sig_q, bool set_polarity, bool clr_polarity, const std::string &src)
2189 {
2190 RTLIL::Cell *cell = addCell(name, ID($sr));
2191 cell->parameters[ID::SET_POLARITY] = set_polarity;
2192 cell->parameters[ID::CLR_POLARITY] = clr_polarity;
2193 cell->parameters[ID::WIDTH] = sig_q.size();
2194 cell->setPort(ID::SET, sig_set);
2195 cell->setPort(ID::CLR, sig_clr);
2196 cell->setPort(ID::Q, sig_q);
2197 cell->set_src_attribute(src);
2198 return cell;
2199 }
2200
2201 RTLIL::Cell* RTLIL::Module::addFf(RTLIL::IdString name, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const std::string &src)
2202 {
2203 RTLIL::Cell *cell = addCell(name, ID($ff));
2204 cell->parameters[ID::WIDTH] = sig_q.size();
2205 cell->setPort(ID::D, sig_d);
2206 cell->setPort(ID::Q, sig_q);
2207 cell->set_src_attribute(src);
2208 return cell;
2209 }
2210
2211 RTLIL::Cell* RTLIL::Module::addDff(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, const std::string &src)
2212 {
2213 RTLIL::Cell *cell = addCell(name, ID($dff));
2214 cell->parameters[ID::CLK_POLARITY] = clk_polarity;
2215 cell->parameters[ID::WIDTH] = sig_q.size();
2216 cell->setPort(ID::CLK, sig_clk);
2217 cell->setPort(ID::D, sig_d);
2218 cell->setPort(ID::Q, sig_q);
2219 cell->set_src_attribute(src);
2220 return cell;
2221 }
2222
2223 RTLIL::Cell* RTLIL::Module::addDffe(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, bool en_polarity, const std::string &src)
2224 {
2225 RTLIL::Cell *cell = addCell(name, ID($dffe));
2226 cell->parameters[ID::CLK_POLARITY] = clk_polarity;
2227 cell->parameters[ID::EN_POLARITY] = en_polarity;
2228 cell->parameters[ID::WIDTH] = sig_q.size();
2229 cell->setPort(ID::CLK, sig_clk);
2230 cell->setPort(ID::EN, sig_en);
2231 cell->setPort(ID::D, sig_d);
2232 cell->setPort(ID::Q, sig_q);
2233 cell->set_src_attribute(src);
2234 return cell;
2235 }
2236
2237 RTLIL::Cell* RTLIL::Module::addDffsr(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,
2238 RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
2239 {
2240 RTLIL::Cell *cell = addCell(name, ID($dffsr));
2241 cell->parameters[ID::CLK_POLARITY] = clk_polarity;
2242 cell->parameters[ID::SET_POLARITY] = set_polarity;
2243 cell->parameters[ID::CLR_POLARITY] = clr_polarity;
2244 cell->parameters[ID::WIDTH] = sig_q.size();
2245 cell->setPort(ID::CLK, sig_clk);
2246 cell->setPort(ID::SET, sig_set);
2247 cell->setPort(ID::CLR, sig_clr);
2248 cell->setPort(ID::D, sig_d);
2249 cell->setPort(ID::Q, sig_q);
2250 cell->set_src_attribute(src);
2251 return cell;
2252 }
2253
2254 RTLIL::Cell* RTLIL::Module::addAdff(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
2255 RTLIL::Const arst_value, bool clk_polarity, bool arst_polarity, const std::string &src)
2256 {
2257 RTLIL::Cell *cell = addCell(name, ID($adff));
2258 cell->parameters[ID::CLK_POLARITY] = clk_polarity;
2259 cell->parameters[ID::ARST_POLARITY] = arst_polarity;
2260 cell->parameters[ID::ARST_VALUE] = arst_value;
2261 cell->parameters[ID::WIDTH] = sig_q.size();
2262 cell->setPort(ID::CLK, sig_clk);
2263 cell->setPort(ID::ARST, sig_arst);
2264 cell->setPort(ID::D, sig_d);
2265 cell->setPort(ID::Q, sig_q);
2266 cell->set_src_attribute(src);
2267 return cell;
2268 }
2269
2270 RTLIL::Cell* RTLIL::Module::addDlatch(RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity, const std::string &src)
2271 {
2272 RTLIL::Cell *cell = addCell(name, ID($dlatch));
2273 cell->parameters[ID::EN_POLARITY] = en_polarity;
2274 cell->parameters[ID::WIDTH] = sig_q.size();
2275 cell->setPort(ID::EN, sig_en);
2276 cell->setPort(ID::D, sig_d);
2277 cell->setPort(ID::Q, sig_q);
2278 cell->set_src_attribute(src);
2279 return cell;
2280 }
2281
2282 RTLIL::Cell* RTLIL::Module::addDlatchsr(RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,
2283 RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
2284 {
2285 RTLIL::Cell *cell = addCell(name, ID($dlatchsr));
2286 cell->parameters[ID::EN_POLARITY] = en_polarity;
2287 cell->parameters[ID::SET_POLARITY] = set_polarity;
2288 cell->parameters[ID::CLR_POLARITY] = clr_polarity;
2289 cell->parameters[ID::WIDTH] = sig_q.size();
2290 cell->setPort(ID::EN, sig_en);
2291 cell->setPort(ID::SET, sig_set);
2292 cell->setPort(ID::CLR, sig_clr);
2293 cell->setPort(ID::D, sig_d);
2294 cell->setPort(ID::Q, sig_q);
2295 cell->set_src_attribute(src);
2296 return cell;
2297 }
2298
2299 RTLIL::Cell* RTLIL::Module::addFfGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const std::string &src)
2300 {
2301 RTLIL::Cell *cell = addCell(name, ID($_FF_));
2302 cell->setPort(ID::D, sig_d);
2303 cell->setPort(ID::Q, sig_q);
2304 cell->set_src_attribute(src);
2305 return cell;
2306 }
2307
2308 RTLIL::Cell* RTLIL::Module::addDffGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, const std::string &src)
2309 {
2310 RTLIL::Cell *cell = addCell(name, stringf("$_DFF_%c_", clk_polarity ? 'P' : 'N'));
2311 cell->setPort(ID::C, sig_clk);
2312 cell->setPort(ID::D, sig_d);
2313 cell->setPort(ID::Q, sig_q);
2314 cell->set_src_attribute(src);
2315 return cell;
2316 }
2317
2318 RTLIL::Cell* RTLIL::Module::addDffeGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, bool en_polarity, const std::string &src)
2319 {
2320 RTLIL::Cell *cell = addCell(name, stringf("$_DFFE_%c%c_", clk_polarity ? 'P' : 'N', en_polarity ? 'P' : 'N'));
2321 cell->setPort(ID::C, sig_clk);
2322 cell->setPort(ID::E, sig_en);
2323 cell->setPort(ID::D, sig_d);
2324 cell->setPort(ID::Q, sig_q);
2325 cell->set_src_attribute(src);
2326 return cell;
2327 }
2328
2329 RTLIL::Cell* RTLIL::Module::addDffsrGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,
2330 RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
2331 {
2332 RTLIL::Cell *cell = addCell(name, stringf("$_DFFSR_%c%c%c_", clk_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N'));
2333 cell->setPort(ID::C, sig_clk);
2334 cell->setPort(ID::S, sig_set);
2335 cell->setPort(ID::R, sig_clr);
2336 cell->setPort(ID::D, sig_d);
2337 cell->setPort(ID::Q, sig_q);
2338 cell->set_src_attribute(src);
2339 return cell;
2340 }
2341
2342 RTLIL::Cell* RTLIL::Module::addAdffGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
2343 bool arst_value, bool clk_polarity, bool arst_polarity, const std::string &src)
2344 {
2345 RTLIL::Cell *cell = addCell(name, stringf("$_DFF_%c%c%c_", clk_polarity ? 'P' : 'N', arst_polarity ? 'P' : 'N', arst_value ? '1' : '0'));
2346 cell->setPort(ID::C, sig_clk);
2347 cell->setPort(ID::R, sig_arst);
2348 cell->setPort(ID::D, sig_d);
2349 cell->setPort(ID::Q, sig_q);
2350 cell->set_src_attribute(src);
2351 return cell;
2352 }
2353
2354 RTLIL::Cell* RTLIL::Module::addDlatchGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity, const std::string &src)
2355 {
2356 RTLIL::Cell *cell = addCell(name, stringf("$_DLATCH_%c_", en_polarity ? 'P' : 'N'));
2357 cell->setPort(ID::E, sig_en);
2358 cell->setPort(ID::D, sig_d);
2359 cell->setPort(ID::Q, sig_q);
2360 cell->set_src_attribute(src);
2361 return cell;
2362 }
2363
2364 RTLIL::Cell* RTLIL::Module::addDlatchsrGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,
2365 RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
2366 {
2367 RTLIL::Cell *cell = addCell(name, stringf("$_DLATCHSR_%c%c%c_", en_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N'));
2368 cell->setPort(ID::E, sig_en);
2369 cell->setPort(ID::S, sig_set);
2370 cell->setPort(ID::R, sig_clr);
2371 cell->setPort(ID::D, sig_d);
2372 cell->setPort(ID::Q, sig_q);
2373 cell->set_src_attribute(src);
2374 return cell;
2375 }
2376
2377 RTLIL::SigSpec RTLIL::Module::Anyconst(RTLIL::IdString name, int width, const std::string &src)
2378 {
2379 RTLIL::SigSpec sig = addWire(NEW_ID, width);
2380 Cell *cell = addCell(name, ID($anyconst));
2381 cell->setParam(ID::WIDTH, width);
2382 cell->setPort(ID::Y, sig);
2383 cell->set_src_attribute(src);
2384 return sig;
2385 }
2386
2387 RTLIL::SigSpec RTLIL::Module::Anyseq(RTLIL::IdString name, int width, const std::string &src)
2388 {
2389 RTLIL::SigSpec sig = addWire(NEW_ID, width);
2390 Cell *cell = addCell(name, ID($anyseq));
2391 cell->setParam(ID::WIDTH, width);
2392 cell->setPort(ID::Y, sig);
2393 cell->set_src_attribute(src);
2394 return sig;
2395 }
2396
2397 RTLIL::SigSpec RTLIL::Module::Allconst(RTLIL::IdString name, int width, const std::string &src)
2398 {
2399 RTLIL::SigSpec sig = addWire(NEW_ID, width);
2400 Cell *cell = addCell(name, ID($allconst));
2401 cell->setParam(ID::WIDTH, width);
2402 cell->setPort(ID::Y, sig);
2403 cell->set_src_attribute(src);
2404 return sig;
2405 }
2406
2407 RTLIL::SigSpec RTLIL::Module::Allseq(RTLIL::IdString name, int width, const std::string &src)
2408 {
2409 RTLIL::SigSpec sig = addWire(NEW_ID, width);
2410 Cell *cell = addCell(name, ID($allseq));
2411 cell->setParam(ID::WIDTH, width);
2412 cell->setPort(ID::Y, sig);
2413 cell->set_src_attribute(src);
2414 return sig;
2415 }
2416
2417 RTLIL::SigSpec RTLIL::Module::Initstate(RTLIL::IdString name, const std::string &src)
2418 {
2419 RTLIL::SigSpec sig = addWire(NEW_ID);
2420 Cell *cell = addCell(name, ID($initstate));
2421 cell->setPort(ID::Y, sig);
2422 cell->set_src_attribute(src);
2423 return sig;
2424 }
2425
2426 RTLIL::Wire::Wire()
2427 {
2428 static unsigned int hashidx_count = 123456789;
2429 hashidx_count = mkhash_xorshift(hashidx_count);
2430 hashidx_ = hashidx_count;
2431
2432 module = nullptr;
2433 width = 1;
2434 start_offset = 0;
2435 port_id = 0;
2436 port_input = false;
2437 port_output = false;
2438 upto = false;
2439
2440 #ifdef WITH_PYTHON
2441 RTLIL::Wire::get_all_wires()->insert(std::pair<unsigned int, RTLIL::Wire*>(hashidx_, this));
2442 #endif
2443 }
2444
2445 RTLIL::Wire::~Wire()
2446 {
2447 #ifdef WITH_PYTHON
2448 RTLIL::Wire::get_all_wires()->erase(hashidx_);
2449 #endif
2450 }
2451
2452 #ifdef WITH_PYTHON
2453 static std::map<unsigned int, RTLIL::Wire*> all_wires;
2454 std::map<unsigned int, RTLIL::Wire*> *RTLIL::Wire::get_all_wires(void)
2455 {
2456 return &all_wires;
2457 }
2458 #endif
2459
2460 RTLIL::Memory::Memory()
2461 {
2462 static unsigned int hashidx_count = 123456789;
2463 hashidx_count = mkhash_xorshift(hashidx_count);
2464 hashidx_ = hashidx_count;
2465
2466 width = 1;
2467 start_offset = 0;
2468 size = 0;
2469 #ifdef WITH_PYTHON
2470 RTLIL::Memory::get_all_memorys()->insert(std::pair<unsigned int, RTLIL::Memory*>(hashidx_, this));
2471 #endif
2472 }
2473
2474 RTLIL::Cell::Cell() : module(nullptr)
2475 {
2476 static unsigned int hashidx_count = 123456789;
2477 hashidx_count = mkhash_xorshift(hashidx_count);
2478 hashidx_ = hashidx_count;
2479
2480 // log("#memtrace# %p\n", this);
2481 memhasher();
2482
2483 #ifdef WITH_PYTHON
2484 RTLIL::Cell::get_all_cells()->insert(std::pair<unsigned int, RTLIL::Cell*>(hashidx_, this));
2485 #endif
2486 }
2487
2488 RTLIL::Cell::~Cell()
2489 {
2490 #ifdef WITH_PYTHON
2491 RTLIL::Cell::get_all_cells()->erase(hashidx_);
2492 #endif
2493 }
2494
2495 #ifdef WITH_PYTHON
2496 static std::map<unsigned int, RTLIL::Cell*> all_cells;
2497 std::map<unsigned int, RTLIL::Cell*> *RTLIL::Cell::get_all_cells(void)
2498 {
2499 return &all_cells;
2500 }
2501 #endif
2502
2503 bool RTLIL::Cell::hasPort(RTLIL::IdString portname) const
2504 {
2505 return connections_.count(portname) != 0;
2506 }
2507
2508 void RTLIL::Cell::unsetPort(RTLIL::IdString portname)
2509 {
2510 RTLIL::SigSpec signal;
2511 auto conn_it = connections_.find(portname);
2512
2513 if (conn_it != connections_.end())
2514 {
2515 for (auto mon : module->monitors)
2516 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
2517
2518 if (module->design)
2519 for (auto mon : module->design->monitors)
2520 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
2521
2522 if (yosys_xtrace) {
2523 log("#X# Unconnect %s.%s.%s\n", log_id(this->module), log_id(this), log_id(portname));
2524 log_backtrace("-X- ", yosys_xtrace-1);
2525 }
2526
2527 connections_.erase(conn_it);
2528 }
2529 }
2530
2531 void RTLIL::Cell::setPort(RTLIL::IdString portname, RTLIL::SigSpec signal)
2532 {
2533 auto r = connections_.insert(portname);
2534 auto conn_it = r.first;
2535 if (!r.second && conn_it->second == signal)
2536 return;
2537
2538 for (auto mon : module->monitors)
2539 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
2540
2541 if (module->design)
2542 for (auto mon : module->design->monitors)
2543 mon->notify_connect(this, conn_it->first, conn_it->second, signal);
2544
2545 if (yosys_xtrace) {
2546 log("#X# Connect %s.%s.%s = %s (%d)\n", log_id(this->module), log_id(this), log_id(portname), log_signal(signal), GetSize(signal));
2547 log_backtrace("-X- ", yosys_xtrace-1);
2548 }
2549
2550 conn_it->second = std::move(signal);
2551 }
2552
2553 const RTLIL::SigSpec &RTLIL::Cell::getPort(RTLIL::IdString portname) const
2554 {
2555 return connections_.at(portname);
2556 }
2557
2558 const dict<RTLIL::IdString, RTLIL::SigSpec> &RTLIL::Cell::connections() const
2559 {
2560 return connections_;
2561 }
2562
2563 bool RTLIL::Cell::known() const
2564 {
2565 if (yosys_celltypes.cell_known(type))
2566 return true;
2567 if (module && module->design && module->design->module(type))
2568 return true;
2569 return false;
2570 }
2571
2572 bool RTLIL::Cell::input(RTLIL::IdString portname) const
2573 {
2574 if (yosys_celltypes.cell_known(type))
2575 return yosys_celltypes.cell_input(type, portname);
2576 if (module && module->design) {
2577 RTLIL::Module *m = module->design->module(type);
2578 RTLIL::Wire *w = m ? m->wire(portname) : nullptr;
2579 return w && w->port_input;
2580 }
2581 return false;
2582 }
2583
2584 bool RTLIL::Cell::output(RTLIL::IdString portname) const
2585 {
2586 if (yosys_celltypes.cell_known(type))
2587 return yosys_celltypes.cell_output(type, portname);
2588 if (module && module->design) {
2589 RTLIL::Module *m = module->design->module(type);
2590 RTLIL::Wire *w = m ? m->wire(portname) : nullptr;
2591 return w && w->port_output;
2592 }
2593 return false;
2594 }
2595
2596 bool RTLIL::Cell::hasParam(RTLIL::IdString paramname) const
2597 {
2598 return parameters.count(paramname) != 0;
2599 }
2600
2601 void RTLIL::Cell::unsetParam(RTLIL::IdString paramname)
2602 {
2603 parameters.erase(paramname);
2604 }
2605
2606 void RTLIL::Cell::setParam(RTLIL::IdString paramname, RTLIL::Const value)
2607 {
2608 parameters[paramname] = std::move(value);
2609 }
2610
2611 const RTLIL::Const &RTLIL::Cell::getParam(RTLIL::IdString paramname) const
2612 {
2613 return parameters.at(paramname);
2614 }
2615
2616 void RTLIL::Cell::sort()
2617 {
2618 connections_.sort(sort_by_id_str());
2619 parameters.sort(sort_by_id_str());
2620 attributes.sort(sort_by_id_str());
2621 }
2622
2623 void RTLIL::Cell::check()
2624 {
2625 #ifndef NDEBUG
2626 InternalCellChecker checker(NULL, this);
2627 checker.check();
2628 #endif
2629 }
2630
2631 void RTLIL::Cell::fixup_parameters(bool set_a_signed, bool set_b_signed)
2632 {
2633 if (!type.begins_with("$") || type.begins_with("$_") || type.begins_with("$paramod") || type.begins_with("$fmcombine") ||
2634 type.begins_with("$verific$") || type.begins_with("$array:") || type.begins_with("$extern:"))
2635 return;
2636
2637 if (type == ID($mux) || type == ID($pmux)) {
2638 parameters[ID::WIDTH] = GetSize(connections_[ID::Y]);
2639 if (type == ID($pmux))
2640 parameters[ID::S_WIDTH] = GetSize(connections_[ID::S]);
2641 check();
2642 return;
2643 }
2644
2645 if (type == ID($lut) || type == ID($sop)) {
2646 parameters[ID::WIDTH] = GetSize(connections_[ID::A]);
2647 return;
2648 }
2649
2650 if (type == ID($fa)) {
2651 parameters[ID::WIDTH] = GetSize(connections_[ID::Y]);
2652 return;
2653 }
2654
2655 if (type == ID($lcu)) {
2656 parameters[ID::WIDTH] = GetSize(connections_[ID::CO]);
2657 return;
2658 }
2659
2660 bool signedness_ab = !type.in(ID($slice), ID($concat), ID($macc));
2661
2662 if (connections_.count(ID::A)) {
2663 if (signedness_ab) {
2664 if (set_a_signed)
2665 parameters[ID::A_SIGNED] = true;
2666 else if (parameters.count(ID::A_SIGNED) == 0)
2667 parameters[ID::A_SIGNED] = false;
2668 }
2669 parameters[ID::A_WIDTH] = GetSize(connections_[ID::A]);
2670 }
2671
2672 if (connections_.count(ID::B)) {
2673 if (signedness_ab) {
2674 if (set_b_signed)
2675 parameters[ID::B_SIGNED] = true;
2676 else if (parameters.count(ID::B_SIGNED) == 0)
2677 parameters[ID::B_SIGNED] = false;
2678 }
2679 parameters[ID::B_WIDTH] = GetSize(connections_[ID::B]);
2680 }
2681
2682 if (connections_.count(ID::Y))
2683 parameters[ID::Y_WIDTH] = GetSize(connections_[ID::Y]);
2684
2685 if (connections_.count(ID::Q))
2686 parameters[ID::WIDTH] = GetSize(connections_[ID::Q]);
2687
2688 check();
2689 }
2690
2691 RTLIL::SigChunk::SigChunk()
2692 {
2693 wire = NULL;
2694 width = 0;
2695 offset = 0;
2696 }
2697
2698 RTLIL::SigChunk::SigChunk(const RTLIL::Const &value)
2699 {
2700 wire = NULL;
2701 data = value.bits;
2702 width = GetSize(data);
2703 offset = 0;
2704 }
2705
2706 RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire)
2707 {
2708 log_assert(wire != nullptr);
2709 this->wire = wire;
2710 this->width = wire->width;
2711 this->offset = 0;
2712 }
2713
2714 RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire, int offset, int width)
2715 {
2716 log_assert(wire != nullptr);
2717 this->wire = wire;
2718 this->width = width;
2719 this->offset = offset;
2720 }
2721
2722 RTLIL::SigChunk::SigChunk(const std::string &str)
2723 {
2724 wire = NULL;
2725 data = RTLIL::Const(str).bits;
2726 width = GetSize(data);
2727 offset = 0;
2728 }
2729
2730 RTLIL::SigChunk::SigChunk(int val, int width)
2731 {
2732 wire = NULL;
2733 data = RTLIL::Const(val, width).bits;
2734 this->width = GetSize(data);
2735 offset = 0;
2736 }
2737
2738 RTLIL::SigChunk::SigChunk(RTLIL::State bit, int width)
2739 {
2740 wire = NULL;
2741 data = RTLIL::Const(bit, width).bits;
2742 this->width = GetSize(data);
2743 offset = 0;
2744 }
2745
2746 RTLIL::SigChunk::SigChunk(const RTLIL::SigBit &bit)
2747 {
2748 wire = bit.wire;
2749 offset = 0;
2750 if (wire == NULL)
2751 data = RTLIL::Const(bit.data).bits;
2752 else
2753 offset = bit.offset;
2754 width = 1;
2755 }
2756
2757 RTLIL::SigChunk::SigChunk(const RTLIL::SigChunk &sigchunk)
2758 {
2759 *this = sigchunk;
2760 }
2761
2762 RTLIL::SigChunk RTLIL::SigChunk::extract(int offset, int length) const
2763 {
2764 RTLIL::SigChunk ret;
2765 if (wire) {
2766 ret.wire = wire;
2767 ret.offset = this->offset + offset;
2768 ret.width = length;
2769 } else {
2770 for (int i = 0; i < length; i++)
2771 ret.data.push_back(data[offset+i]);
2772 ret.width = length;
2773 }
2774 return ret;
2775 }
2776
2777 bool RTLIL::SigChunk::operator <(const RTLIL::SigChunk &other) const
2778 {
2779 if (wire && other.wire)
2780 if (wire->name != other.wire->name)
2781 return wire->name < other.wire->name;
2782
2783 if (wire != other.wire)
2784 return wire < other.wire;
2785
2786 if (offset != other.offset)
2787 return offset < other.offset;
2788
2789 if (width != other.width)
2790 return width < other.width;
2791
2792 return data < other.data;
2793 }
2794
2795 bool RTLIL::SigChunk::operator ==(const RTLIL::SigChunk &other) const
2796 {
2797 return wire == other.wire && width == other.width && offset == other.offset && data == other.data;
2798 }
2799
2800 bool RTLIL::SigChunk::operator !=(const RTLIL::SigChunk &other) const
2801 {
2802 if (*this == other)
2803 return false;
2804 return true;
2805 }
2806
2807 RTLIL::SigSpec::SigSpec()
2808 {
2809 width_ = 0;
2810 hash_ = 0;
2811 }
2812
2813 RTLIL::SigSpec::SigSpec(const RTLIL::SigSpec &other)
2814 {
2815 *this = other;
2816 }
2817
2818 RTLIL::SigSpec::SigSpec(std::initializer_list<RTLIL::SigSpec> parts)
2819 {
2820 cover("kernel.rtlil.sigspec.init.list");
2821
2822 width_ = 0;
2823 hash_ = 0;
2824
2825 log_assert(parts.size() > 0);
2826 auto ie = parts.begin();
2827 auto it = ie + parts.size() - 1;
2828 while (it >= ie)
2829 append(*it--);
2830 }
2831
2832 RTLIL::SigSpec &RTLIL::SigSpec::operator=(const RTLIL::SigSpec &other)
2833 {
2834 cover("kernel.rtlil.sigspec.assign");
2835
2836 width_ = other.width_;
2837 hash_ = other.hash_;
2838 chunks_ = other.chunks_;
2839 bits_ = other.bits_;
2840 return *this;
2841 }
2842
2843 RTLIL::SigSpec::SigSpec(const RTLIL::Const &value)
2844 {
2845 cover("kernel.rtlil.sigspec.init.const");
2846
2847 chunks_.emplace_back(value);
2848 width_ = chunks_.back().width;
2849 hash_ = 0;
2850 check();
2851 }
2852
2853 RTLIL::SigSpec::SigSpec(const RTLIL::SigChunk &chunk)
2854 {
2855 cover("kernel.rtlil.sigspec.init.chunk");
2856
2857 chunks_.emplace_back(chunk);
2858 width_ = chunks_.back().width;
2859 hash_ = 0;
2860 check();
2861 }
2862
2863 RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire)
2864 {
2865 cover("kernel.rtlil.sigspec.init.wire");
2866
2867 chunks_.emplace_back(wire);
2868 width_ = chunks_.back().width;
2869 hash_ = 0;
2870 check();
2871 }
2872
2873 RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire, int offset, int width)
2874 {
2875 cover("kernel.rtlil.sigspec.init.wire_part");
2876
2877 chunks_.emplace_back(wire, offset, width);
2878 width_ = chunks_.back().width;
2879 hash_ = 0;
2880 check();
2881 }
2882
2883 RTLIL::SigSpec::SigSpec(const std::string &str)
2884 {
2885 cover("kernel.rtlil.sigspec.init.str");
2886
2887 chunks_.emplace_back(str);
2888 width_ = chunks_.back().width;
2889 hash_ = 0;
2890 check();
2891 }
2892
2893 RTLIL::SigSpec::SigSpec(int val, int width)
2894 {
2895 cover("kernel.rtlil.sigspec.init.int");
2896
2897 chunks_.emplace_back(val, width);
2898 width_ = width;
2899 hash_ = 0;
2900 check();
2901 }
2902
2903 RTLIL::SigSpec::SigSpec(RTLIL::State bit, int width)
2904 {
2905 cover("kernel.rtlil.sigspec.init.state");
2906
2907 chunks_.emplace_back(bit, width);
2908 width_ = width;
2909 hash_ = 0;
2910 check();
2911 }
2912
2913 RTLIL::SigSpec::SigSpec(const RTLIL::SigBit &bit, int width)
2914 {
2915 cover("kernel.rtlil.sigspec.init.bit");
2916
2917 if (bit.wire == NULL)
2918 chunks_.emplace_back(bit.data, width);
2919 else
2920 for (int i = 0; i < width; i++)
2921 chunks_.push_back(bit);
2922 width_ = width;
2923 hash_ = 0;
2924 check();
2925 }
2926
2927 RTLIL::SigSpec::SigSpec(const std::vector<RTLIL::SigChunk> &chunks)
2928 {
2929 cover("kernel.rtlil.sigspec.init.stdvec_chunks");
2930
2931 width_ = 0;
2932 hash_ = 0;
2933 for (const auto &c : chunks)
2934 append(c);
2935 check();
2936 }
2937
2938 RTLIL::SigSpec::SigSpec(const std::vector<RTLIL::SigBit> &bits)
2939 {
2940 cover("kernel.rtlil.sigspec.init.stdvec_bits");
2941
2942 width_ = 0;
2943 hash_ = 0;
2944 for (const auto &bit : bits)
2945 append(bit);
2946 check();
2947 }
2948
2949 RTLIL::SigSpec::SigSpec(const pool<RTLIL::SigBit> &bits)
2950 {
2951 cover("kernel.rtlil.sigspec.init.pool_bits");
2952
2953 width_ = 0;
2954 hash_ = 0;
2955 for (const auto &bit : bits)
2956 append(bit);
2957 check();
2958 }
2959
2960 RTLIL::SigSpec::SigSpec(const std::set<RTLIL::SigBit> &bits)
2961 {
2962 cover("kernel.rtlil.sigspec.init.stdset_bits");
2963
2964 width_ = 0;
2965 hash_ = 0;
2966 for (const auto &bit : bits)
2967 append(bit);
2968 check();
2969 }
2970
2971 RTLIL::SigSpec::SigSpec(bool bit)
2972 {
2973 cover("kernel.rtlil.sigspec.init.bool");
2974
2975 width_ = 0;
2976 hash_ = 0;
2977 append(SigBit(bit));
2978 check();
2979 }
2980
2981 void RTLIL::SigSpec::pack() const
2982 {
2983 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
2984
2985 if (that->bits_.empty())
2986 return;
2987
2988 cover("kernel.rtlil.sigspec.convert.pack");
2989 log_assert(that->chunks_.empty());
2990
2991 std::vector<RTLIL::SigBit> old_bits;
2992 old_bits.swap(that->bits_);
2993
2994 RTLIL::SigChunk *last = NULL;
2995 int last_end_offset = 0;
2996
2997 for (auto &bit : old_bits) {
2998 if (last && bit.wire == last->wire) {
2999 if (bit.wire == NULL) {
3000 last->data.push_back(bit.data);
3001 last->width++;
3002 continue;
3003 } else if (last_end_offset == bit.offset) {
3004 last_end_offset++;
3005 last->width++;
3006 continue;
3007 }
3008 }
3009 that->chunks_.push_back(bit);
3010 last = &that->chunks_.back();
3011 last_end_offset = bit.offset + 1;
3012 }
3013
3014 check();
3015 }
3016
3017 void RTLIL::SigSpec::unpack() const
3018 {
3019 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
3020
3021 if (that->chunks_.empty())
3022 return;
3023
3024 cover("kernel.rtlil.sigspec.convert.unpack");
3025 log_assert(that->bits_.empty());
3026
3027 that->bits_.reserve(that->width_);
3028 for (auto &c : that->chunks_)
3029 for (int i = 0; i < c.width; i++)
3030 that->bits_.emplace_back(c, i);
3031
3032 that->chunks_.clear();
3033 that->hash_ = 0;
3034 }
3035
3036 void RTLIL::SigSpec::updhash() const
3037 {
3038 RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
3039
3040 if (that->hash_ != 0)
3041 return;
3042
3043 cover("kernel.rtlil.sigspec.hash");
3044 that->pack();
3045
3046 that->hash_ = mkhash_init;
3047 for (auto &c : that->chunks_)
3048 if (c.wire == NULL) {
3049 for (auto &v : c.data)
3050 that->hash_ = mkhash(that->hash_, v);
3051 } else {
3052 that->hash_ = mkhash(that->hash_, c.wire->name.index_);
3053 that->hash_ = mkhash(that->hash_, c.offset);
3054 that->hash_ = mkhash(that->hash_, c.width);
3055 }
3056
3057 if (that->hash_ == 0)
3058 that->hash_ = 1;
3059 }
3060
3061 void RTLIL::SigSpec::sort()
3062 {
3063 unpack();
3064 cover("kernel.rtlil.sigspec.sort");
3065 std::sort(bits_.begin(), bits_.end());
3066 }
3067
3068 void RTLIL::SigSpec::sort_and_unify()
3069 {
3070 unpack();
3071 cover("kernel.rtlil.sigspec.sort_and_unify");
3072
3073 // A copy of the bits vector is used to prevent duplicating the logic from
3074 // SigSpec::SigSpec(std::vector<SigBit>). This incurrs an extra copy but
3075 // that isn't showing up as significant in profiles.
3076 std::vector<SigBit> unique_bits = bits_;
3077 std::sort(unique_bits.begin(), unique_bits.end());
3078 auto last = std::unique(unique_bits.begin(), unique_bits.end());
3079 unique_bits.erase(last, unique_bits.end());
3080
3081 *this = unique_bits;
3082 }
3083
3084 void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with)
3085 {
3086 replace(pattern, with, this);
3087 }
3088
3089 void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with, RTLIL::SigSpec *other) const
3090 {
3091 log_assert(other != NULL);
3092 log_assert(width_ == other->width_);
3093 log_assert(pattern.width_ == with.width_);
3094
3095 pattern.unpack();
3096 with.unpack();
3097 unpack();
3098 other->unpack();
3099
3100 for (int i = 0; i < GetSize(pattern.bits_); i++) {
3101 if (pattern.bits_[i].wire != NULL) {
3102 for (int j = 0; j < GetSize(bits_); j++) {
3103 if (bits_[j] == pattern.bits_[i]) {
3104 other->bits_[j] = with.bits_[i];
3105 }
3106 }
3107 }
3108 }
3109
3110 other->check();
3111 }
3112
3113 void RTLIL::SigSpec::replace(const dict<RTLIL::SigBit, RTLIL::SigBit> &rules)
3114 {
3115 replace(rules, this);
3116 }
3117
3118 void RTLIL::SigSpec::replace(const dict<RTLIL::SigBit, RTLIL::SigBit> &rules, RTLIL::SigSpec *other) const
3119 {
3120 cover("kernel.rtlil.sigspec.replace_dict");
3121
3122 log_assert(other != NULL);
3123 log_assert(width_ == other->width_);
3124
3125 if (rules.empty()) return;
3126 unpack();
3127 other->unpack();
3128
3129 for (int i = 0; i < GetSize(bits_); i++) {
3130 auto it = rules.find(bits_[i]);
3131 if (it != rules.end())
3132 other->bits_[i] = it->second;
3133 }
3134
3135 other->check();
3136 }
3137
3138 void RTLIL::SigSpec::replace(const std::map<RTLIL::SigBit, RTLIL::SigBit> &rules)
3139 {
3140 replace(rules, this);
3141 }
3142
3143 void RTLIL::SigSpec::replace(const std::map<RTLIL::SigBit, RTLIL::SigBit> &rules, RTLIL::SigSpec *other) const
3144 {
3145 cover("kernel.rtlil.sigspec.replace_map");
3146
3147 log_assert(other != NULL);
3148 log_assert(width_ == other->width_);
3149
3150 if (rules.empty()) return;
3151 unpack();
3152 other->unpack();
3153
3154 for (int i = 0; i < GetSize(bits_); i++) {
3155 auto it = rules.find(bits_[i]);
3156 if (it != rules.end())
3157 other->bits_[i] = it->second;
3158 }
3159
3160 other->check();
3161 }
3162
3163 void RTLIL::SigSpec::remove(const RTLIL::SigSpec &pattern)
3164 {
3165 remove2(pattern, NULL);
3166 }
3167
3168 void RTLIL::SigSpec::remove(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other) const
3169 {
3170 RTLIL::SigSpec tmp = *this;
3171 tmp.remove2(pattern, other);
3172 }
3173
3174 void RTLIL::SigSpec::remove2(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other)
3175 {
3176 if (other)
3177 cover("kernel.rtlil.sigspec.remove_other");
3178 else
3179 cover("kernel.rtlil.sigspec.remove");
3180
3181 unpack();
3182 if (other != NULL) {
3183 log_assert(width_ == other->width_);
3184 other->unpack();
3185 }
3186
3187 for (int i = GetSize(bits_) - 1; i >= 0; i--)
3188 {
3189 if (bits_[i].wire == NULL) continue;
3190
3191 for (auto &pattern_chunk : pattern.chunks())
3192 if (bits_[i].wire == pattern_chunk.wire &&
3193 bits_[i].offset >= pattern_chunk.offset &&
3194 bits_[i].offset < pattern_chunk.offset + pattern_chunk.width) {
3195 bits_.erase(bits_.begin() + i);
3196 width_--;
3197 if (other != NULL) {
3198 other->bits_.erase(other->bits_.begin() + i);
3199 other->width_--;
3200 }
3201 break;
3202 }
3203 }
3204
3205 check();
3206 }
3207
3208 void RTLIL::SigSpec::remove(const pool<RTLIL::SigBit> &pattern)
3209 {
3210 remove2(pattern, NULL);
3211 }
3212
3213 void RTLIL::SigSpec::remove(const pool<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other) const
3214 {
3215 RTLIL::SigSpec tmp = *this;
3216 tmp.remove2(pattern, other);
3217 }
3218
3219 void RTLIL::SigSpec::remove2(const pool<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other)
3220 {
3221 if (other)
3222 cover("kernel.rtlil.sigspec.remove_other");
3223 else
3224 cover("kernel.rtlil.sigspec.remove");
3225
3226 unpack();
3227
3228 if (other != NULL) {
3229 log_assert(width_ == other->width_);
3230 other->unpack();
3231 }
3232
3233 for (int i = GetSize(bits_) - 1; i >= 0; i--) {
3234 if (bits_[i].wire != NULL && pattern.count(bits_[i])) {
3235 bits_.erase(bits_.begin() + i);
3236 width_--;
3237 if (other != NULL) {
3238 other->bits_.erase(other->bits_.begin() + i);
3239 other->width_--;
3240 }
3241 }
3242 }
3243
3244 check();
3245 }
3246
3247 void RTLIL::SigSpec::remove2(const std::set<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other)
3248 {
3249 if (other)
3250 cover("kernel.rtlil.sigspec.remove_other");
3251 else
3252 cover("kernel.rtlil.sigspec.remove");
3253
3254 unpack();
3255
3256 if (other != NULL) {
3257 log_assert(width_ == other->width_);
3258 other->unpack();
3259 }
3260
3261 for (int i = GetSize(bits_) - 1; i >= 0; i--) {
3262 if (bits_[i].wire != NULL && pattern.count(bits_[i])) {
3263 bits_.erase(bits_.begin() + i);
3264 width_--;
3265 if (other != NULL) {
3266 other->bits_.erase(other->bits_.begin() + i);
3267 other->width_--;
3268 }
3269 }
3270 }
3271
3272 check();
3273 }
3274
3275 RTLIL::SigSpec RTLIL::SigSpec::extract(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec *other) const
3276 {
3277 if (other)
3278 cover("kernel.rtlil.sigspec.extract_other");
3279 else
3280 cover("kernel.rtlil.sigspec.extract");
3281
3282 log_assert(other == NULL || width_ == other->width_);
3283
3284 RTLIL::SigSpec ret;
3285 std::vector<RTLIL::SigBit> bits_match = to_sigbit_vector();
3286
3287 for (auto& pattern_chunk : pattern.chunks()) {
3288 if (other) {
3289 std::vector<RTLIL::SigBit> bits_other = other->to_sigbit_vector();
3290 for (int i = 0; i < width_; i++)
3291 if (bits_match[i].wire &&
3292 bits_match[i].wire == pattern_chunk.wire &&
3293 bits_match[i].offset >= pattern_chunk.offset &&
3294 bits_match[i].offset < pattern_chunk.offset + pattern_chunk.width)
3295 ret.append(bits_other[i]);
3296 } else {
3297 for (int i = 0; i < width_; i++)
3298 if (bits_match[i].wire &&
3299 bits_match[i].wire == pattern_chunk.wire &&
3300 bits_match[i].offset >= pattern_chunk.offset &&
3301 bits_match[i].offset < pattern_chunk.offset + pattern_chunk.width)
3302 ret.append(bits_match[i]);
3303 }
3304 }
3305
3306 ret.check();
3307 return ret;
3308 }
3309
3310 RTLIL::SigSpec RTLIL::SigSpec::extract(const pool<RTLIL::SigBit> &pattern, const RTLIL::SigSpec *other) const
3311 {
3312 if (other)
3313 cover("kernel.rtlil.sigspec.extract_other");
3314 else
3315 cover("kernel.rtlil.sigspec.extract");
3316
3317 log_assert(other == NULL || width_ == other->width_);
3318
3319 std::vector<RTLIL::SigBit> bits_match = to_sigbit_vector();
3320 RTLIL::SigSpec ret;
3321
3322 if (other) {
3323 std::vector<RTLIL::SigBit> bits_other = other->to_sigbit_vector();
3324 for (int i = 0; i < width_; i++)
3325 if (bits_match[i].wire && pattern.count(bits_match[i]))
3326 ret.append(bits_other[i]);
3327 } else {
3328 for (int i = 0; i < width_; i++)
3329 if (bits_match[i].wire && pattern.count(bits_match[i]))
3330 ret.append(bits_match[i]);
3331 }
3332
3333 ret.check();
3334 return ret;
3335 }
3336
3337 void RTLIL::SigSpec::replace(int offset, const RTLIL::SigSpec &with)
3338 {
3339 cover("kernel.rtlil.sigspec.replace_pos");
3340
3341 unpack();
3342 with.unpack();
3343
3344 log_assert(offset >= 0);
3345 log_assert(with.width_ >= 0);
3346 log_assert(offset+with.width_ <= width_);
3347
3348 for (int i = 0; i < with.width_; i++)
3349 bits_.at(offset + i) = with.bits_.at(i);
3350
3351 check();
3352 }
3353
3354 void RTLIL::SigSpec::remove_const()
3355 {
3356 if (packed())
3357 {
3358 cover("kernel.rtlil.sigspec.remove_const.packed");
3359
3360 std::vector<RTLIL::SigChunk> new_chunks;
3361 new_chunks.reserve(GetSize(chunks_));
3362
3363 width_ = 0;
3364 for (auto &chunk : chunks_)
3365 if (chunk.wire != NULL) {
3366 new_chunks.push_back(chunk);
3367 width_ += chunk.width;
3368 }
3369
3370 chunks_.swap(new_chunks);
3371 }
3372 else
3373 {
3374 cover("kernel.rtlil.sigspec.remove_const.unpacked");
3375
3376 std::vector<RTLIL::SigBit> new_bits;
3377 new_bits.reserve(width_);
3378
3379 for (auto &bit : bits_)
3380 if (bit.wire != NULL)
3381 new_bits.push_back(bit);
3382
3383 bits_.swap(new_bits);
3384 width_ = bits_.size();
3385 }
3386
3387 check();
3388 }
3389
3390 void RTLIL::SigSpec::remove(int offset, int length)
3391 {
3392 cover("kernel.rtlil.sigspec.remove_pos");
3393
3394 unpack();
3395
3396 log_assert(offset >= 0);
3397 log_assert(length >= 0);
3398 log_assert(offset + length <= width_);
3399
3400 bits_.erase(bits_.begin() + offset, bits_.begin() + offset + length);
3401 width_ = bits_.size();
3402
3403 check();
3404 }
3405
3406 RTLIL::SigSpec RTLIL::SigSpec::extract(int offset, int length) const
3407 {
3408 unpack();
3409 cover("kernel.rtlil.sigspec.extract_pos");
3410 return std::vector<RTLIL::SigBit>(bits_.begin() + offset, bits_.begin() + offset + length);
3411 }
3412
3413 void RTLIL::SigSpec::append(const RTLIL::SigSpec &signal)
3414 {
3415 if (signal.width_ == 0)
3416 return;
3417
3418 if (width_ == 0) {
3419 *this = signal;
3420 return;
3421 }
3422
3423 cover("kernel.rtlil.sigspec.append");
3424
3425 if (packed() != signal.packed()) {
3426 pack();
3427 signal.pack();
3428 }
3429
3430 if (packed())
3431 for (auto &other_c : signal.chunks_)
3432 {
3433 auto &my_last_c = chunks_.back();
3434 if (my_last_c.wire == NULL && other_c.wire == NULL) {
3435 auto &this_data = my_last_c.data;
3436 auto &other_data = other_c.data;
3437 this_data.insert(this_data.end(), other_data.begin(), other_data.end());
3438 my_last_c.width += other_c.width;
3439 } else
3440 if (my_last_c.wire == other_c.wire && my_last_c.offset + my_last_c.width == other_c.offset) {
3441 my_last_c.width += other_c.width;
3442 } else
3443 chunks_.push_back(other_c);
3444 }
3445 else
3446 bits_.insert(bits_.end(), signal.bits_.begin(), signal.bits_.end());
3447
3448 width_ += signal.width_;
3449 check();
3450 }
3451
3452 void RTLIL::SigSpec::append(const RTLIL::SigBit &bit)
3453 {
3454 if (packed())
3455 {
3456 cover("kernel.rtlil.sigspec.append_bit.packed");
3457
3458 if (chunks_.size() == 0)
3459 chunks_.push_back(bit);
3460 else
3461 if (bit.wire == NULL)
3462 if (chunks_.back().wire == NULL) {
3463 chunks_.back().data.push_back(bit.data);
3464 chunks_.back().width++;
3465 } else
3466 chunks_.push_back(bit);
3467 else
3468 if (chunks_.back().wire == bit.wire && chunks_.back().offset + chunks_.back().width == bit.offset)
3469 chunks_.back().width++;
3470 else
3471 chunks_.push_back(bit);
3472 }
3473 else
3474 {
3475 cover("kernel.rtlil.sigspec.append_bit.unpacked");
3476 bits_.push_back(bit);
3477 }
3478
3479 width_++;
3480 check();
3481 }
3482
3483 void RTLIL::SigSpec::extend_u0(int width, bool is_signed)
3484 {
3485 cover("kernel.rtlil.sigspec.extend_u0");
3486
3487 pack();
3488
3489 if (width_ > width)
3490 remove(width, width_ - width);
3491
3492 if (width_ < width) {
3493 RTLIL::SigBit padding = width_ > 0 ? (*this)[width_ - 1] : RTLIL::State::Sx;
3494 if (!is_signed)
3495 padding = RTLIL::State::S0;
3496 while (width_ < width)
3497 append(padding);
3498 }
3499
3500 }
3501
3502 RTLIL::SigSpec RTLIL::SigSpec::repeat(int num) const
3503 {
3504 cover("kernel.rtlil.sigspec.repeat");
3505
3506 RTLIL::SigSpec sig;
3507 for (int i = 0; i < num; i++)
3508 sig.append(*this);
3509 return sig;
3510 }
3511
3512 #ifndef NDEBUG
3513 void RTLIL::SigSpec::check() const
3514 {
3515 if (width_ > 64)
3516 {
3517 cover("kernel.rtlil.sigspec.check.skip");
3518 }
3519 else if (packed())
3520 {
3521 cover("kernel.rtlil.sigspec.check.packed");
3522
3523 int w = 0;
3524 for (size_t i = 0; i < chunks_.size(); i++) {
3525 const RTLIL::SigChunk &chunk = chunks_[i];
3526 if (chunk.wire == NULL) {
3527 if (i > 0)
3528 log_assert(chunks_[i-1].wire != NULL);
3529 log_assert(chunk.offset == 0);
3530 log_assert(chunk.data.size() == (size_t)chunk.width);
3531 } else {
3532 if (i > 0 && chunks_[i-1].wire == chunk.wire)
3533 log_assert(chunk.offset != chunks_[i-1].offset + chunks_[i-1].width);
3534 log_assert(chunk.offset >= 0);
3535 log_assert(chunk.width >= 0);
3536 log_assert(chunk.offset + chunk.width <= chunk.wire->width);
3537 log_assert(chunk.data.size() == 0);
3538 }
3539 w += chunk.width;
3540 }
3541 log_assert(w == width_);
3542 log_assert(bits_.empty());
3543 }
3544 else
3545 {
3546 cover("kernel.rtlil.sigspec.check.unpacked");
3547
3548 log_assert(width_ == GetSize(bits_));
3549 log_assert(chunks_.empty());
3550 }
3551 }
3552 #endif
3553
3554 bool RTLIL::SigSpec::operator <(const RTLIL::SigSpec &other) const
3555 {
3556 cover("kernel.rtlil.sigspec.comp_lt");
3557
3558 if (this == &other)
3559 return false;
3560
3561 if (width_ != other.width_)
3562 return width_ < other.width_;
3563
3564 pack();
3565 other.pack();
3566
3567 if (chunks_.size() != other.chunks_.size())
3568 return chunks_.size() < other.chunks_.size();
3569
3570 updhash();
3571 other.updhash();
3572
3573 if (hash_ != other.hash_)
3574 return hash_ < other.hash_;
3575
3576 for (size_t i = 0; i < chunks_.size(); i++)
3577 if (chunks_[i] != other.chunks_[i]) {
3578 cover("kernel.rtlil.sigspec.comp_lt.hash_collision");
3579 return chunks_[i] < other.chunks_[i];
3580 }
3581
3582 cover("kernel.rtlil.sigspec.comp_lt.equal");
3583 return false;
3584 }
3585
3586 bool RTLIL::SigSpec::operator ==(const RTLIL::SigSpec &other) const
3587 {
3588 cover("kernel.rtlil.sigspec.comp_eq");
3589
3590 if (this == &other)
3591 return true;
3592
3593 if (width_ != other.width_)
3594 return false;
3595
3596 // Without this, SigSpec() == SigSpec(State::S0, 0) will fail
3597 // since the RHS will contain one SigChunk of width 0 causing
3598 // the size check below to fail
3599 if (width_ == 0)
3600 return true;
3601
3602 pack();
3603 other.pack();
3604
3605 if (chunks_.size() != other.chunks_.size())
3606 return false;
3607
3608 updhash();
3609 other.updhash();
3610
3611 if (hash_ != other.hash_)
3612 return false;
3613
3614 for (size_t i = 0; i < chunks_.size(); i++)
3615 if (chunks_[i] != other.chunks_[i]) {
3616 cover("kernel.rtlil.sigspec.comp_eq.hash_collision");
3617 return false;
3618 }
3619
3620 cover("kernel.rtlil.sigspec.comp_eq.equal");
3621 return true;
3622 }
3623
3624 bool RTLIL::SigSpec::is_wire() const
3625 {
3626 cover("kernel.rtlil.sigspec.is_wire");
3627
3628 pack();
3629 return GetSize(chunks_) == 1 && chunks_[0].wire && chunks_[0].wire->width == width_;
3630 }
3631
3632 bool RTLIL::SigSpec::is_chunk() const
3633 {
3634 cover("kernel.rtlil.sigspec.is_chunk");
3635
3636 pack();
3637 return GetSize(chunks_) == 1;
3638 }
3639
3640 bool RTLIL::SigSpec::is_fully_const() const
3641 {
3642 cover("kernel.rtlil.sigspec.is_fully_const");
3643
3644 pack();
3645 for (auto it = chunks_.begin(); it != chunks_.end(); it++)
3646 if (it->width > 0 && it->wire != NULL)
3647 return false;
3648 return true;
3649 }
3650
3651 bool RTLIL::SigSpec::is_fully_zero() const
3652 {
3653 cover("kernel.rtlil.sigspec.is_fully_zero");
3654
3655 pack();
3656 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
3657 if (it->width > 0 && it->wire != NULL)
3658 return false;
3659 for (size_t i = 0; i < it->data.size(); i++)
3660 if (it->data[i] != RTLIL::State::S0)
3661 return false;
3662 }
3663 return true;
3664 }
3665
3666 bool RTLIL::SigSpec::is_fully_ones() const
3667 {
3668 cover("kernel.rtlil.sigspec.is_fully_ones");
3669
3670 pack();
3671 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
3672 if (it->width > 0 && it->wire != NULL)
3673 return false;
3674 for (size_t i = 0; i < it->data.size(); i++)
3675 if (it->data[i] != RTLIL::State::S1)
3676 return false;
3677 }
3678 return true;
3679 }
3680
3681 bool RTLIL::SigSpec::is_fully_def() const
3682 {
3683 cover("kernel.rtlil.sigspec.is_fully_def");
3684
3685 pack();
3686 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
3687 if (it->width > 0 && it->wire != NULL)
3688 return false;
3689 for (size_t i = 0; i < it->data.size(); i++)
3690 if (it->data[i] != RTLIL::State::S0 && it->data[i] != RTLIL::State::S1)
3691 return false;
3692 }
3693 return true;
3694 }
3695
3696 bool RTLIL::SigSpec::is_fully_undef() const
3697 {
3698 cover("kernel.rtlil.sigspec.is_fully_undef");
3699
3700 pack();
3701 for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
3702 if (it->width > 0 && it->wire != NULL)
3703 return false;
3704 for (size_t i = 0; i < it->data.size(); i++)
3705 if (it->data[i] != RTLIL::State::Sx && it->data[i] != RTLIL::State::Sz)
3706 return false;
3707 }
3708 return true;
3709 }
3710
3711 bool RTLIL::SigSpec::has_const() const
3712 {
3713 cover("kernel.rtlil.sigspec.has_const");
3714
3715 pack();
3716 for (auto it = chunks_.begin(); it != chunks_.end(); it++)
3717 if (it->width > 0 && it->wire == NULL)
3718 return true;
3719 return false;
3720 }
3721
3722 bool RTLIL::SigSpec::has_marked_bits() const
3723 {
3724 cover("kernel.rtlil.sigspec.has_marked_bits");
3725
3726 pack();
3727 for (auto it = chunks_.begin(); it != chunks_.end(); it++)
3728 if (it->width > 0 && it->wire == NULL) {
3729 for (size_t i = 0; i < it->data.size(); i++)
3730 if (it->data[i] == RTLIL::State::Sm)
3731 return true;
3732 }
3733 return false;
3734 }
3735
3736 bool RTLIL::SigSpec::as_bool() const
3737 {
3738 cover("kernel.rtlil.sigspec.as_bool");
3739
3740 pack();
3741 log_assert(is_fully_const() && GetSize(chunks_) <= 1);
3742 if (width_)
3743 return RTLIL::Const(chunks_[0].data).as_bool();
3744 return false;
3745 }
3746
3747 int RTLIL::SigSpec::as_int(bool is_signed) const
3748 {
3749 cover("kernel.rtlil.sigspec.as_int");
3750
3751 pack();
3752 log_assert(is_fully_const() && GetSize(chunks_) <= 1);
3753 if (width_)
3754 return RTLIL::Const(chunks_[0].data).as_int(is_signed);
3755 return 0;
3756 }
3757
3758 std::string RTLIL::SigSpec::as_string() const
3759 {
3760 cover("kernel.rtlil.sigspec.as_string");
3761
3762 pack();
3763 std::string str;
3764 str.reserve(size());
3765 for (size_t i = chunks_.size(); i > 0; i--) {
3766 const RTLIL::SigChunk &chunk = chunks_[i-1];
3767 if (chunk.wire != NULL)
3768 str.append(chunk.width, '?');
3769 else
3770 str += RTLIL::Const(chunk.data).as_string();
3771 }
3772 return str;
3773 }
3774
3775 RTLIL::Const RTLIL::SigSpec::as_const() const
3776 {
3777 cover("kernel.rtlil.sigspec.as_const");
3778
3779 pack();
3780 log_assert(is_fully_const() && GetSize(chunks_) <= 1);
3781 if (width_)
3782 return chunks_[0].data;
3783 return RTLIL::Const();
3784 }
3785
3786 RTLIL::Wire *RTLIL::SigSpec::as_wire() const
3787 {
3788 cover("kernel.rtlil.sigspec.as_wire");
3789
3790 pack();
3791 log_assert(is_wire());
3792 return chunks_[0].wire;
3793 }
3794
3795 RTLIL::SigChunk RTLIL::SigSpec::as_chunk() const
3796 {
3797 cover("kernel.rtlil.sigspec.as_chunk");
3798
3799 pack();
3800 log_assert(is_chunk());
3801 return chunks_[0];
3802 }
3803
3804 RTLIL::SigBit RTLIL::SigSpec::as_bit() const
3805 {
3806 cover("kernel.rtlil.sigspec.as_bit");
3807
3808 log_assert(width_ == 1);
3809 if (packed())
3810 return RTLIL::SigBit(*chunks_.begin());
3811 else
3812 return bits_[0];
3813 }
3814
3815 bool RTLIL::SigSpec::match(const char* pattern) const
3816 {
3817 cover("kernel.rtlil.sigspec.match");
3818
3819 unpack();
3820 log_assert(int(strlen(pattern)) == GetSize(bits_));
3821
3822 for (auto it = bits_.rbegin(); it != bits_.rend(); it++, pattern++) {
3823 if (*pattern == ' ')
3824 continue;
3825 if (*pattern == '*') {
3826 if (*it != State::Sz && *it != State::Sx)
3827 return false;
3828 continue;
3829 }
3830 if (*pattern == '0') {
3831 if (*it != State::S0)
3832 return false;
3833 } else
3834 if (*pattern == '1') {
3835 if (*it != State::S1)
3836 return false;
3837 } else
3838 log_abort();
3839 }
3840
3841 return true;
3842 }
3843
3844 std::set<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_set() const
3845 {
3846 cover("kernel.rtlil.sigspec.to_sigbit_set");
3847
3848 pack();
3849 std::set<RTLIL::SigBit> sigbits;
3850 for (auto &c : chunks_)
3851 for (int i = 0; i < c.width; i++)
3852 sigbits.insert(RTLIL::SigBit(c, i));
3853 return sigbits;
3854 }
3855
3856 pool<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_pool() const
3857 {
3858 cover("kernel.rtlil.sigspec.to_sigbit_pool");
3859
3860 pack();
3861 pool<RTLIL::SigBit> sigbits;
3862 sigbits.reserve(size());
3863 for (auto &c : chunks_)
3864 for (int i = 0; i < c.width; i++)
3865 sigbits.insert(RTLIL::SigBit(c, i));
3866 return sigbits;
3867 }
3868
3869 std::vector<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_vector() const
3870 {
3871 cover("kernel.rtlil.sigspec.to_sigbit_vector");
3872
3873 unpack();
3874 return bits_;
3875 }
3876
3877 std::map<RTLIL::SigBit, RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_map(const RTLIL::SigSpec &other) const
3878 {
3879 cover("kernel.rtlil.sigspec.to_sigbit_map");
3880
3881 unpack();
3882 other.unpack();
3883
3884 log_assert(width_ == other.width_);
3885
3886 std::map<RTLIL::SigBit, RTLIL::SigBit> new_map;
3887 for (int i = 0; i < width_; i++)
3888 new_map[bits_[i]] = other.bits_[i];
3889
3890 return new_map;
3891 }
3892
3893 dict<RTLIL::SigBit, RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_dict(const RTLIL::SigSpec &other) const
3894 {
3895 cover("kernel.rtlil.sigspec.to_sigbit_dict");
3896
3897 unpack();
3898 other.unpack();
3899
3900 log_assert(width_ == other.width_);
3901
3902 dict<RTLIL::SigBit, RTLIL::SigBit> new_map;
3903 new_map.reserve(size());
3904 for (int i = 0; i < width_; i++)
3905 new_map[bits_[i]] = other.bits_[i];
3906
3907 return new_map;
3908 }
3909
3910 static void sigspec_parse_split(std::vector<std::string> &tokens, const std::string &text, char sep)
3911 {
3912 size_t start = 0, end = 0;
3913 while ((end = text.find(sep, start)) != std::string::npos) {
3914 tokens.push_back(text.substr(start, end - start));
3915 start = end + 1;
3916 }
3917 tokens.push_back(text.substr(start));
3918 }
3919
3920 static int sigspec_parse_get_dummy_line_num()
3921 {
3922 return 0;
3923 }
3924
3925 bool RTLIL::SigSpec::parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str)
3926 {
3927 cover("kernel.rtlil.sigspec.parse");
3928
3929 AST::current_filename = "input";
3930
3931 std::vector<std::string> tokens;
3932 sigspec_parse_split(tokens, str, ',');
3933
3934 sig = RTLIL::SigSpec();
3935 for (int tokidx = int(tokens.size())-1; tokidx >= 0; tokidx--)
3936 {
3937 std::string netname = tokens[tokidx];
3938 std::string indices;
3939
3940 if (netname.size() == 0)
3941 continue;
3942
3943 if (('0' <= netname[0] && netname[0] <= '9') || netname[0] == '\'') {
3944 cover("kernel.rtlil.sigspec.parse.const");
3945 AST::get_line_num = sigspec_parse_get_dummy_line_num;
3946 AST::AstNode *ast = VERILOG_FRONTEND::const2ast(netname);
3947 if (ast == NULL)
3948 return false;
3949 sig.append(RTLIL::Const(ast->bits));
3950 delete ast;
3951 continue;
3952 }
3953
3954 if (module == NULL)
3955 return false;
3956
3957 cover("kernel.rtlil.sigspec.parse.net");
3958
3959 if (netname[0] != '$' && netname[0] != '\\')
3960 netname = "\\" + netname;
3961
3962 if (module->wires_.count(netname) == 0) {
3963 size_t indices_pos = netname.size()-1;
3964 if (indices_pos > 2 && netname[indices_pos] == ']')
3965 {
3966 indices_pos--;
3967 while (indices_pos > 0 && ('0' <= netname[indices_pos] && netname[indices_pos] <= '9')) indices_pos--;
3968 if (indices_pos > 0 && netname[indices_pos] == ':') {
3969 indices_pos--;
3970 while (indices_pos > 0 && ('0' <= netname[indices_pos] && netname[indices_pos] <= '9')) indices_pos--;
3971 }
3972 if (indices_pos > 0 && netname[indices_pos] == '[') {
3973 indices = netname.substr(indices_pos);
3974 netname = netname.substr(0, indices_pos);
3975 }
3976 }
3977 }
3978
3979 if (module->wires_.count(netname) == 0)
3980 return false;
3981
3982 RTLIL::Wire *wire = module->wires_.at(netname);
3983 if (!indices.empty()) {
3984 std::vector<std::string> index_tokens;
3985 sigspec_parse_split(index_tokens, indices.substr(1, indices.size()-2), ':');
3986 if (index_tokens.size() == 1) {
3987 cover("kernel.rtlil.sigspec.parse.bit_sel");
3988 int a = atoi(index_tokens.at(0).c_str());
3989 if (a < 0 || a >= wire->width)
3990 return false;
3991 sig.append(RTLIL::SigSpec(wire, a));
3992 } else {
3993 cover("kernel.rtlil.sigspec.parse.part_sel");
3994 int a = atoi(index_tokens.at(0).c_str());
3995 int b = atoi(index_tokens.at(1).c_str());
3996 if (a > b) {
3997 int tmp = a;
3998 a = b, b = tmp;
3999 }
4000 if (a < 0 || a >= wire->width)
4001 return false;
4002 if (b < 0 || b >= wire->width)
4003 return false;
4004 sig.append(RTLIL::SigSpec(wire, a, b-a+1));
4005 }
4006 } else
4007 sig.append(wire);
4008 }
4009
4010 return true;
4011 }
4012
4013 bool RTLIL::SigSpec::parse_sel(RTLIL::SigSpec &sig, RTLIL::Design *design, RTLIL::Module *module, std::string str)
4014 {
4015 if (str.empty() || str[0] != '@')
4016 return parse(sig, module, str);
4017
4018 cover("kernel.rtlil.sigspec.parse.sel");
4019
4020 str = RTLIL::escape_id(str.substr(1));
4021 if (design->selection_vars.count(str) == 0)
4022 return false;
4023
4024 sig = RTLIL::SigSpec();
4025 RTLIL::Selection &sel = design->selection_vars.at(str);
4026 for (auto &it : module->wires_)
4027 if (sel.selected_member(module->name, it.first))
4028 sig.append(it.second);
4029
4030 return true;
4031 }
4032
4033 bool RTLIL::SigSpec::parse_rhs(const RTLIL::SigSpec &lhs, RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str)
4034 {
4035 if (str == "0") {
4036 cover("kernel.rtlil.sigspec.parse.rhs_zeros");
4037 sig = RTLIL::SigSpec(RTLIL::State::S0, lhs.width_);
4038 return true;
4039 }
4040
4041 if (str == "~0") {
4042 cover("kernel.rtlil.sigspec.parse.rhs_ones");
4043 sig = RTLIL::SigSpec(RTLIL::State::S1, lhs.width_);
4044 return true;
4045 }
4046
4047 if (lhs.chunks_.size() == 1) {
4048 char *p = (char*)str.c_str(), *endptr;
4049 long int val = strtol(p, &endptr, 10);
4050 if (endptr && endptr != p && *endptr == 0) {
4051 sig = RTLIL::SigSpec(val, lhs.width_);
4052 cover("kernel.rtlil.sigspec.parse.rhs_dec");
4053 return true;
4054 }
4055 }
4056
4057 return parse(sig, module, str);
4058 }
4059
4060 RTLIL::CaseRule::~CaseRule()
4061 {
4062 for (auto it = switches.begin(); it != switches.end(); it++)
4063 delete *it;
4064 }
4065
4066 bool RTLIL::CaseRule::empty() const
4067 {
4068 return actions.empty() && switches.empty();
4069 }
4070
4071 RTLIL::CaseRule *RTLIL::CaseRule::clone() const
4072 {
4073 RTLIL::CaseRule *new_caserule = new RTLIL::CaseRule;
4074 new_caserule->compare = compare;
4075 new_caserule->actions = actions;
4076 for (auto &it : switches)
4077 new_caserule->switches.push_back(it->clone());
4078 return new_caserule;
4079 }
4080
4081 RTLIL::SwitchRule::~SwitchRule()
4082 {
4083 for (auto it = cases.begin(); it != cases.end(); it++)
4084 delete *it;
4085 }
4086
4087 bool RTLIL::SwitchRule::empty() const
4088 {
4089 return cases.empty();
4090 }
4091
4092 RTLIL::SwitchRule *RTLIL::SwitchRule::clone() const
4093 {
4094 RTLIL::SwitchRule *new_switchrule = new RTLIL::SwitchRule;
4095 new_switchrule->signal = signal;
4096 new_switchrule->attributes = attributes;
4097 for (auto &it : cases)
4098 new_switchrule->cases.push_back(it->clone());
4099 return new_switchrule;
4100
4101 }
4102
4103 RTLIL::SyncRule *RTLIL::SyncRule::clone() const
4104 {
4105 RTLIL::SyncRule *new_syncrule = new RTLIL::SyncRule;
4106 new_syncrule->type = type;
4107 new_syncrule->signal = signal;
4108 new_syncrule->actions = actions;
4109 return new_syncrule;
4110 }
4111
4112 RTLIL::Process::~Process()
4113 {
4114 for (auto it = syncs.begin(); it != syncs.end(); it++)
4115 delete *it;
4116 }
4117
4118 RTLIL::Process *RTLIL::Process::clone() const
4119 {
4120 RTLIL::Process *new_proc = new RTLIL::Process;
4121
4122 new_proc->name = name;
4123 new_proc->attributes = attributes;
4124
4125 RTLIL::CaseRule *rc_ptr = root_case.clone();
4126 new_proc->root_case = *rc_ptr;
4127 rc_ptr->switches.clear();
4128 delete rc_ptr;
4129
4130 for (auto &it : syncs)
4131 new_proc->syncs.push_back(it->clone());
4132
4133 return new_proc;
4134 }
4135
4136 #ifdef WITH_PYTHON
4137 RTLIL::Memory::~Memory()
4138 {
4139 RTLIL::Memory::get_all_memorys()->erase(hashidx_);
4140 }
4141 static std::map<unsigned int, RTLIL::Memory*> all_memorys;
4142 std::map<unsigned int, RTLIL::Memory*> *RTLIL::Memory::get_all_memorys(void)
4143 {
4144 return &all_memorys;
4145 }
4146 #endif
4147 YOSYS_NAMESPACE_END