2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include "kernel/yosys.h"
21 #include "kernel/macc.h"
22 #include "kernel/celltypes.h"
23 #include "frontends/verilog/verilog_frontend.h"
24 #include "frontends/verilog/preproc.h"
25 #include "backends/ilang/ilang_backend.h"
32 RTLIL::IdString::destruct_guard_t
RTLIL::IdString::destruct_guard
;
33 std::vector
<char*> RTLIL::IdString::global_id_storage_
;
34 dict
<char*, int, hash_cstr_ops
> RTLIL::IdString::global_id_index_
;
35 #ifndef YOSYS_NO_IDS_REFCNT
36 std::vector
<int> RTLIL::IdString::global_refcount_storage_
;
37 std::vector
<int> RTLIL::IdString::global_free_idx_list_
;
39 #ifdef YOSYS_USE_STICKY_IDS
40 int RTLIL::IdString::last_created_idx_
[8];
41 int RTLIL::IdString::last_created_idx_ptr_
;
44 #define X(_id) IdString RTLIL::ID::_id;
45 #include "kernel/constids.inc"
48 dict
<std::string
, std::string
> RTLIL::constpad
;
50 const pool
<IdString
> &RTLIL::builtin_ff_cell_types() {
51 static const pool
<IdString
> res
= {
99 flags
= RTLIL::CONST_FLAG_NONE
;
102 RTLIL::Const::Const(std::string str
)
104 flags
= RTLIL::CONST_FLAG_STRING
;
105 for (int i
= str
.size()-1; i
>= 0; i
--) {
106 unsigned char ch
= str
[i
];
107 for (int j
= 0; j
< 8; j
++) {
108 bits
.push_back((ch
& 1) != 0 ? State::S1
: State::S0
);
114 RTLIL::Const::Const(int val
, int width
)
116 flags
= RTLIL::CONST_FLAG_NONE
;
117 for (int i
= 0; i
< width
; i
++) {
118 bits
.push_back((val
& 1) != 0 ? State::S1
: State::S0
);
123 RTLIL::Const::Const(RTLIL::State bit
, int width
)
125 flags
= RTLIL::CONST_FLAG_NONE
;
126 for (int i
= 0; i
< width
; i
++)
130 RTLIL::Const::Const(const std::vector
<bool> &bits
)
132 flags
= RTLIL::CONST_FLAG_NONE
;
133 for (const auto &b
: bits
)
134 this->bits
.emplace_back(b
? State::S1
: State::S0
);
137 RTLIL::Const::Const(const RTLIL::Const
&c
)
140 for (const auto &b
: c
.bits
)
141 this->bits
.push_back(b
);
144 bool RTLIL::Const::operator <(const RTLIL::Const
&other
) const
146 if (bits
.size() != other
.bits
.size())
147 return bits
.size() < other
.bits
.size();
148 for (size_t i
= 0; i
< bits
.size(); i
++)
149 if (bits
[i
] != other
.bits
[i
])
150 return bits
[i
] < other
.bits
[i
];
154 bool RTLIL::Const::operator ==(const RTLIL::Const
&other
) const
156 return bits
== other
.bits
;
159 bool RTLIL::Const::operator !=(const RTLIL::Const
&other
) const
161 return bits
!= other
.bits
;
164 bool RTLIL::Const::as_bool() const
166 for (size_t i
= 0; i
< bits
.size(); i
++)
167 if (bits
[i
] == State::S1
)
172 int RTLIL::Const::as_int(bool is_signed
) const
175 for (size_t i
= 0; i
< bits
.size() && i
< 32; i
++)
176 if (bits
[i
] == State::S1
)
178 if (is_signed
&& bits
.back() == State::S1
)
179 for (size_t i
= bits
.size(); i
< 32; i
++)
184 std::string
RTLIL::Const::as_string() const
187 ret
.reserve(bits
.size());
188 for (size_t i
= bits
.size(); i
> 0; i
--)
190 case S0
: ret
+= "0"; break;
191 case S1
: ret
+= "1"; break;
192 case Sx
: ret
+= "x"; break;
193 case Sz
: ret
+= "z"; break;
194 case Sa
: ret
+= "-"; break;
195 case Sm
: ret
+= "m"; break;
200 RTLIL::Const
RTLIL::Const::from_string(const std::string
&str
)
203 c
.bits
.reserve(str
.size());
204 for (auto it
= str
.rbegin(); it
!= str
.rend(); it
++)
206 case '0': c
.bits
.push_back(State::S0
); break;
207 case '1': c
.bits
.push_back(State::S1
); break;
208 case 'x': c
.bits
.push_back(State::Sx
); break;
209 case 'z': c
.bits
.push_back(State::Sz
); break;
210 case 'm': c
.bits
.push_back(State::Sm
); break;
211 default: c
.bits
.push_back(State::Sa
);
216 std::string
RTLIL::Const::decode_string() const
219 string
.reserve(GetSize(bits
)/8);
220 for (int i
= 0; i
< GetSize(bits
); i
+= 8) {
222 for (int j
= 0; j
< 8 && i
+ j
< int (bits
.size()); j
++)
223 if (bits
[i
+ j
] == RTLIL::State::S1
)
228 std::reverse(string
.begin(), string
.end());
232 bool RTLIL::Const::is_fully_zero() const
234 cover("kernel.rtlil.const.is_fully_zero");
236 for (const auto &bit
: bits
)
237 if (bit
!= RTLIL::State::S0
)
243 bool RTLIL::Const::is_fully_ones() const
245 cover("kernel.rtlil.const.is_fully_ones");
247 for (const auto &bit
: bits
)
248 if (bit
!= RTLIL::State::S1
)
254 bool RTLIL::Const::is_fully_def() const
256 cover("kernel.rtlil.const.is_fully_def");
258 for (const auto &bit
: bits
)
259 if (bit
!= RTLIL::State::S0
&& bit
!= RTLIL::State::S1
)
265 bool RTLIL::Const::is_fully_undef() const
267 cover("kernel.rtlil.const.is_fully_undef");
269 for (const auto &bit
: bits
)
270 if (bit
!= RTLIL::State::Sx
&& bit
!= RTLIL::State::Sz
)
276 void RTLIL::AttrObject::set_bool_attribute(RTLIL::IdString id
, bool value
)
279 attributes
[id
] = RTLIL::Const(1);
281 attributes
.erase(id
);
284 bool RTLIL::AttrObject::get_bool_attribute(RTLIL::IdString id
) const
286 const auto it
= attributes
.find(id
);
287 if (it
== attributes
.end())
289 return it
->second
.as_bool();
292 void RTLIL::AttrObject::set_strpool_attribute(RTLIL::IdString id
, const pool
<string
> &data
)
295 for (const auto &s
: data
) {
296 if (!attrval
.empty())
300 attributes
[id
] = RTLIL::Const(attrval
);
303 void RTLIL::AttrObject::add_strpool_attribute(RTLIL::IdString id
, const pool
<string
> &data
)
305 pool
<string
> union_data
= get_strpool_attribute(id
);
306 union_data
.insert(data
.begin(), data
.end());
307 if (!union_data
.empty())
308 set_strpool_attribute(id
, union_data
);
311 pool
<string
> RTLIL::AttrObject::get_strpool_attribute(RTLIL::IdString id
) const
314 if (attributes
.count(id
) != 0)
315 for (auto s
: split_tokens(attributes
.at(id
).decode_string(), "|"))
320 void RTLIL::AttrObject::set_src_attribute(const std::string
&src
)
323 attributes
.erase(ID::src
);
325 attributes
[ID::src
] = src
;
328 std::string
RTLIL::AttrObject::get_src_attribute() const
331 const auto it
= attributes
.find(ID::src
);
332 if (it
!= attributes
.end())
333 src
= it
->second
.decode_string();
337 bool RTLIL::Selection::selected_module(RTLIL::IdString mod_name
) const
341 if (selected_modules
.count(mod_name
) > 0)
343 if (selected_members
.count(mod_name
) > 0)
348 bool RTLIL::Selection::selected_whole_module(RTLIL::IdString mod_name
) const
352 if (selected_modules
.count(mod_name
) > 0)
357 bool RTLIL::Selection::selected_member(RTLIL::IdString mod_name
, RTLIL::IdString memb_name
) const
361 if (selected_modules
.count(mod_name
) > 0)
363 if (selected_members
.count(mod_name
) > 0)
364 if (selected_members
.at(mod_name
).count(memb_name
) > 0)
369 void RTLIL::Selection::optimize(RTLIL::Design
*design
)
371 if (full_selection
) {
372 selected_modules
.clear();
373 selected_members
.clear();
377 std::vector
<RTLIL::IdString
> del_list
, add_list
;
380 for (auto mod_name
: selected_modules
) {
381 if (design
->modules_
.count(mod_name
) == 0)
382 del_list
.push_back(mod_name
);
383 selected_members
.erase(mod_name
);
385 for (auto mod_name
: del_list
)
386 selected_modules
.erase(mod_name
);
389 for (auto &it
: selected_members
)
390 if (design
->modules_
.count(it
.first
) == 0)
391 del_list
.push_back(it
.first
);
392 for (auto mod_name
: del_list
)
393 selected_members
.erase(mod_name
);
395 for (auto &it
: selected_members
) {
397 for (auto memb_name
: it
.second
)
398 if (design
->modules_
[it
.first
]->count_id(memb_name
) == 0)
399 del_list
.push_back(memb_name
);
400 for (auto memb_name
: del_list
)
401 it
.second
.erase(memb_name
);
406 for (auto &it
: selected_members
)
407 if (it
.second
.size() == 0)
408 del_list
.push_back(it
.first
);
409 else if (it
.second
.size() == design
->modules_
[it
.first
]->wires_
.size() + design
->modules_
[it
.first
]->memories
.size() +
410 design
->modules_
[it
.first
]->cells_
.size() + design
->modules_
[it
.first
]->processes
.size())
411 add_list
.push_back(it
.first
);
412 for (auto mod_name
: del_list
)
413 selected_members
.erase(mod_name
);
414 for (auto mod_name
: add_list
) {
415 selected_members
.erase(mod_name
);
416 selected_modules
.insert(mod_name
);
419 if (selected_modules
.size() == design
->modules_
.size()) {
420 full_selection
= true;
421 selected_modules
.clear();
422 selected_members
.clear();
426 RTLIL::Design::Design()
427 : verilog_defines (new define_map_t
)
429 static unsigned int hashidx_count
= 123456789;
430 hashidx_count
= mkhash_xorshift(hashidx_count
);
431 hashidx_
= hashidx_count
;
433 refcount_modules_
= 0;
434 selection_stack
.push_back(RTLIL::Selection());
437 RTLIL::Design::get_all_designs()->insert(std::pair
<unsigned int, RTLIL::Design
*>(hashidx_
, this));
441 RTLIL::Design::~Design()
443 for (auto it
= modules_
.begin(); it
!= modules_
.end(); ++it
)
445 for (auto n
: verilog_packages
)
447 for (auto n
: verilog_globals
)
450 RTLIL::Design::get_all_designs()->erase(hashidx_
);
455 static std::map
<unsigned int, RTLIL::Design
*> all_designs
;
456 std::map
<unsigned int, RTLIL::Design
*> *RTLIL::Design::get_all_designs(void)
462 RTLIL::ObjRange
<RTLIL::Module
*> RTLIL::Design::modules()
464 return RTLIL::ObjRange
<RTLIL::Module
*>(&modules_
, &refcount_modules_
);
467 RTLIL::Module
*RTLIL::Design::module(RTLIL::IdString name
)
469 return modules_
.count(name
) ? modules_
.at(name
) : NULL
;
472 RTLIL::Module
*RTLIL::Design::top_module()
474 RTLIL::Module
*module
= nullptr;
475 int module_count
= 0;
477 for (auto mod
: selected_modules()) {
478 if (mod
->get_bool_attribute(ID::top
))
484 return module_count
== 1 ? module
: nullptr;
487 void RTLIL::Design::add(RTLIL::Module
*module
)
489 log_assert(modules_
.count(module
->name
) == 0);
490 log_assert(refcount_modules_
== 0);
491 modules_
[module
->name
] = module
;
492 module
->design
= this;
494 for (auto mon
: monitors
)
495 mon
->notify_module_add(module
);
498 log("#X# New Module: %s\n", log_id(module
));
499 log_backtrace("-X- ", yosys_xtrace
-1);
503 RTLIL::Module
*RTLIL::Design::addModule(RTLIL::IdString name
)
505 log_assert(modules_
.count(name
) == 0);
506 log_assert(refcount_modules_
== 0);
508 RTLIL::Module
*module
= new RTLIL::Module
;
509 modules_
[name
] = module
;
510 module
->design
= this;
513 for (auto mon
: monitors
)
514 mon
->notify_module_add(module
);
517 log("#X# New Module: %s\n", log_id(module
));
518 log_backtrace("-X- ", yosys_xtrace
-1);
524 void RTLIL::Design::scratchpad_unset(const std::string
&varname
)
526 scratchpad
.erase(varname
);
529 void RTLIL::Design::scratchpad_set_int(const std::string
&varname
, int value
)
531 scratchpad
[varname
] = stringf("%d", value
);
534 void RTLIL::Design::scratchpad_set_bool(const std::string
&varname
, bool value
)
536 scratchpad
[varname
] = value
? "true" : "false";
539 void RTLIL::Design::scratchpad_set_string(const std::string
&varname
, std::string value
)
541 scratchpad
[varname
] = std::move(value
);
544 int RTLIL::Design::scratchpad_get_int(const std::string
&varname
, int default_value
) const
546 auto it
= scratchpad
.find(varname
);
547 if (it
== scratchpad
.end())
548 return default_value
;
550 const std::string
&str
= it
->second
;
552 if (str
== "0" || str
== "false")
555 if (str
== "1" || str
== "true")
558 char *endptr
= nullptr;
559 long int parsed_value
= strtol(str
.c_str(), &endptr
, 10);
560 return *endptr
? default_value
: parsed_value
;
563 bool RTLIL::Design::scratchpad_get_bool(const std::string
&varname
, bool default_value
) const
565 auto it
= scratchpad
.find(varname
);
566 if (it
== scratchpad
.end())
567 return default_value
;
569 const std::string
&str
= it
->second
;
571 if (str
== "0" || str
== "false")
574 if (str
== "1" || str
== "true")
577 return default_value
;
580 std::string
RTLIL::Design::scratchpad_get_string(const std::string
&varname
, const std::string
&default_value
) const
582 auto it
= scratchpad
.find(varname
);
583 if (it
== scratchpad
.end())
584 return default_value
;
589 void RTLIL::Design::remove(RTLIL::Module
*module
)
591 for (auto mon
: monitors
)
592 mon
->notify_module_del(module
);
595 log("#X# Remove Module: %s\n", log_id(module
));
596 log_backtrace("-X- ", yosys_xtrace
-1);
599 log_assert(modules_
.at(module
->name
) == module
);
600 modules_
.erase(module
->name
);
604 void RTLIL::Design::rename(RTLIL::Module
*module
, RTLIL::IdString new_name
)
606 modules_
.erase(module
->name
);
607 module
->name
= new_name
;
611 void RTLIL::Design::sort()
614 modules_
.sort(sort_by_id_str());
615 for (auto &it
: modules_
)
619 void RTLIL::Design::check()
622 for (auto &it
: modules_
) {
623 log_assert(this == it
.second
->design
);
624 log_assert(it
.first
== it
.second
->name
);
625 log_assert(!it
.first
.empty());
631 void RTLIL::Design::optimize()
633 for (auto &it
: modules_
)
634 it
.second
->optimize();
635 for (auto &it
: selection_stack
)
637 for (auto &it
: selection_vars
)
638 it
.second
.optimize(this);
641 bool RTLIL::Design::selected_module(RTLIL::IdString mod_name
) const
643 if (!selected_active_module
.empty() && mod_name
!= selected_active_module
)
645 if (selection_stack
.size() == 0)
647 return selection_stack
.back().selected_module(mod_name
);
650 bool RTLIL::Design::selected_whole_module(RTLIL::IdString mod_name
) const
652 if (!selected_active_module
.empty() && mod_name
!= selected_active_module
)
654 if (selection_stack
.size() == 0)
656 return selection_stack
.back().selected_whole_module(mod_name
);
659 bool RTLIL::Design::selected_member(RTLIL::IdString mod_name
, RTLIL::IdString memb_name
) const
661 if (!selected_active_module
.empty() && mod_name
!= selected_active_module
)
663 if (selection_stack
.size() == 0)
665 return selection_stack
.back().selected_member(mod_name
, memb_name
);
668 bool RTLIL::Design::selected_module(RTLIL::Module
*mod
) const
670 return selected_module(mod
->name
);
673 bool RTLIL::Design::selected_whole_module(RTLIL::Module
*mod
) const
675 return selected_whole_module(mod
->name
);
678 std::vector
<RTLIL::Module
*> RTLIL::Design::selected_modules() const
680 std::vector
<RTLIL::Module
*> result
;
681 result
.reserve(modules_
.size());
682 for (auto &it
: modules_
)
683 if (selected_module(it
.first
) && !it
.second
->get_blackbox_attribute())
684 result
.push_back(it
.second
);
688 std::vector
<RTLIL::Module
*> RTLIL::Design::selected_whole_modules() const
690 std::vector
<RTLIL::Module
*> result
;
691 result
.reserve(modules_
.size());
692 for (auto &it
: modules_
)
693 if (selected_whole_module(it
.first
) && !it
.second
->get_blackbox_attribute())
694 result
.push_back(it
.second
);
698 std::vector
<RTLIL::Module
*> RTLIL::Design::selected_whole_modules_warn() const
700 std::vector
<RTLIL::Module
*> result
;
701 result
.reserve(modules_
.size());
702 for (auto &it
: modules_
)
703 if (it
.second
->get_blackbox_attribute())
705 else if (selected_whole_module(it
.first
))
706 result
.push_back(it
.second
);
707 else if (selected_module(it
.first
))
708 log_warning("Ignoring partially selected module %s.\n", log_id(it
.first
));
712 RTLIL::Module::Module()
714 static unsigned int hashidx_count
= 123456789;
715 hashidx_count
= mkhash_xorshift(hashidx_count
);
716 hashidx_
= hashidx_count
;
723 RTLIL::Module::get_all_modules()->insert(std::pair
<unsigned int, RTLIL::Module
*>(hashidx_
, this));
727 RTLIL::Module::~Module()
729 for (auto it
= wires_
.begin(); it
!= wires_
.end(); ++it
)
731 for (auto it
= memories
.begin(); it
!= memories
.end(); ++it
)
733 for (auto it
= cells_
.begin(); it
!= cells_
.end(); ++it
)
735 for (auto it
= processes
.begin(); it
!= processes
.end(); ++it
)
738 RTLIL::Module::get_all_modules()->erase(hashidx_
);
743 static std::map
<unsigned int, RTLIL::Module
*> all_modules
;
744 std::map
<unsigned int, RTLIL::Module
*> *RTLIL::Module::get_all_modules(void)
750 void RTLIL::Module::makeblackbox()
752 pool
<RTLIL::Wire
*> delwires
;
754 for (auto it
= wires_
.begin(); it
!= wires_
.end(); ++it
)
755 if (!it
->second
->port_input
&& !it
->second
->port_output
)
756 delwires
.insert(it
->second
);
758 for (auto it
= memories
.begin(); it
!= memories
.end(); ++it
)
762 for (auto it
= cells_
.begin(); it
!= cells_
.end(); ++it
)
766 for (auto it
= processes
.begin(); it
!= processes
.end(); ++it
)
770 connections_
.clear();
773 set_bool_attribute(ID::blackbox
);
776 void RTLIL::Module::reprocess_module(RTLIL::Design
*, const dict
<RTLIL::IdString
, RTLIL::Module
*> &)
778 log_error("Cannot reprocess_module module `%s' !\n", id2cstr(name
));
781 RTLIL::IdString
RTLIL::Module::derive(RTLIL::Design
*, const dict
<RTLIL::IdString
, RTLIL::Const
> &, bool mayfail
)
784 return RTLIL::IdString();
785 log_error("Module `%s' is used with parameters but is not parametric!\n", id2cstr(name
));
789 RTLIL::IdString
RTLIL::Module::derive(RTLIL::Design
*, const dict
<RTLIL::IdString
, RTLIL::Const
> &, const dict
<RTLIL::IdString
, RTLIL::Module
*> &, const dict
<RTLIL::IdString
, RTLIL::IdString
> &, bool mayfail
)
792 return RTLIL::IdString();
793 log_error("Module `%s' is used with parameters but is not parametric!\n", id2cstr(name
));
796 size_t RTLIL::Module::count_id(RTLIL::IdString id
)
798 return wires_
.count(id
) + memories
.count(id
) + cells_
.count(id
) + processes
.count(id
);
803 struct InternalCellChecker
805 RTLIL::Module
*module
;
807 pool
<RTLIL::IdString
> expected_params
, expected_ports
;
809 InternalCellChecker(RTLIL::Module
*module
, RTLIL::Cell
*cell
) : module(module
), cell(cell
) { }
811 void error(int linenr
)
813 std::stringstream buf
;
814 ILANG_BACKEND::dump_cell(buf
, " ", cell
);
816 log_error("Found error in internal cell %s%s%s (%s) at %s:%d:\n%s",
817 module
? module
->name
.c_str() : "", module
? "." : "",
818 cell
->name
.c_str(), cell
->type
.c_str(), __FILE__
, linenr
, buf
.str().c_str());
821 int param(RTLIL::IdString name
)
823 auto it
= cell
->parameters
.find(name
);
824 if (it
== cell
->parameters
.end())
826 expected_params
.insert(name
);
827 return it
->second
.as_int();
830 int param_bool(RTLIL::IdString name
)
833 if (GetSize(cell
->parameters
.at(name
)) > 32)
835 if (v
!= 0 && v
!= 1)
840 int param_bool(RTLIL::IdString name
, bool expected
)
842 int v
= param_bool(name
);
848 void param_bits(RTLIL::IdString name
, int width
)
851 if (GetSize(cell
->parameters
.at(name
).bits
) != width
)
855 void port(RTLIL::IdString name
, int width
)
857 auto it
= cell
->connections_
.find(name
);
858 if (it
== cell
->connections_
.end())
860 if (GetSize(it
->second
) != width
)
862 expected_ports
.insert(name
);
865 void check_expected(bool check_matched_sign
= false)
867 for (auto ¶
: cell
->parameters
)
868 if (expected_params
.count(para
.first
) == 0)
870 for (auto &conn
: cell
->connections())
871 if (expected_ports
.count(conn
.first
) == 0)
874 if (check_matched_sign
) {
875 log_assert(expected_params
.count(ID::A_SIGNED
) != 0 && expected_params
.count(ID::B_SIGNED
) != 0);
876 bool a_is_signed
= cell
->parameters
.at(ID::A_SIGNED
).as_bool();
877 bool b_is_signed
= cell
->parameters
.at(ID::B_SIGNED
).as_bool();
878 if (a_is_signed
!= b_is_signed
)
885 if (!cell
->type
.begins_with("$") || cell
->type
.begins_with("$__") || cell
->type
.begins_with("$paramod") || cell
->type
.begins_with("$fmcombine") ||
886 cell
->type
.begins_with("$verific$") || cell
->type
.begins_with("$array:") || cell
->type
.begins_with("$extern:"))
889 if (cell
->type
.in(ID($
not), ID($pos
), ID($neg
))) {
890 param_bool(ID::A_SIGNED
);
891 port(ID::A
, param(ID::A_WIDTH
));
892 port(ID::Y
, param(ID::Y_WIDTH
));
897 if (cell
->type
.in(ID($
and), ID($
or), ID($
xor), ID($xnor
))) {
898 param_bool(ID::A_SIGNED
);
899 param_bool(ID::B_SIGNED
);
900 port(ID::A
, param(ID::A_WIDTH
));
901 port(ID::B
, param(ID::B_WIDTH
));
902 port(ID::Y
, param(ID::Y_WIDTH
));
903 check_expected(true);
907 if (cell
->type
.in(ID($reduce_and
), ID($reduce_or
), ID($reduce_xor
), ID($reduce_xnor
), ID($reduce_bool
))) {
908 param_bool(ID::A_SIGNED
);
909 port(ID::A
, param(ID::A_WIDTH
));
910 port(ID::Y
, param(ID::Y_WIDTH
));
915 if (cell
->type
.in(ID($shl
), ID($shr
), ID($sshl
), ID($sshr
))) {
916 param_bool(ID::A_SIGNED
);
917 param_bool(ID::B_SIGNED
, /*expected=*/false);
918 port(ID::A
, param(ID::A_WIDTH
));
919 port(ID::B
, param(ID::B_WIDTH
));
920 port(ID::Y
, param(ID::Y_WIDTH
));
921 check_expected(/*check_matched_sign=*/false);
925 if (cell
->type
.in(ID($shift
), ID($shiftx
))) {
926 param_bool(ID::A_SIGNED
);
927 param_bool(ID::B_SIGNED
);
928 port(ID::A
, param(ID::A_WIDTH
));
929 port(ID::B
, param(ID::B_WIDTH
));
930 port(ID::Y
, param(ID::Y_WIDTH
));
931 check_expected(/*check_matched_sign=*/false);
935 if (cell
->type
.in(ID($lt
), ID($le
), ID($eq
), ID($ne
), ID($eqx
), ID($nex
), ID($ge
), ID($gt
))) {
936 param_bool(ID::A_SIGNED
);
937 param_bool(ID::B_SIGNED
);
938 port(ID::A
, param(ID::A_WIDTH
));
939 port(ID::B
, param(ID::B_WIDTH
));
940 port(ID::Y
, param(ID::Y_WIDTH
));
941 check_expected(true);
945 if (cell
->type
.in(ID($add
), ID($sub
), ID($mul
), ID($div
), ID($mod
), ID($pow
))) {
946 param_bool(ID::A_SIGNED
);
947 param_bool(ID::B_SIGNED
);
948 port(ID::A
, param(ID::A_WIDTH
));
949 port(ID::B
, param(ID::B_WIDTH
));
950 port(ID::Y
, param(ID::Y_WIDTH
));
951 check_expected(cell
->type
!= ID($pow
));
955 if (cell
->type
== ID($fa
)) {
956 port(ID::A
, param(ID::WIDTH
));
957 port(ID::B
, param(ID::WIDTH
));
958 port(ID::C
, param(ID::WIDTH
));
959 port(ID::X
, param(ID::WIDTH
));
960 port(ID::Y
, param(ID::WIDTH
));
965 if (cell
->type
== ID($lcu
)) {
966 port(ID::P
, param(ID::WIDTH
));
967 port(ID::G
, param(ID::WIDTH
));
969 port(ID::CO
, param(ID::WIDTH
));
974 if (cell
->type
== ID($alu
)) {
975 param_bool(ID::A_SIGNED
);
976 param_bool(ID::B_SIGNED
);
977 port(ID::A
, param(ID::A_WIDTH
));
978 port(ID::B
, param(ID::B_WIDTH
));
981 port(ID::X
, param(ID::Y_WIDTH
));
982 port(ID::Y
, param(ID::Y_WIDTH
));
983 port(ID::CO
, param(ID::Y_WIDTH
));
984 check_expected(true);
988 if (cell
->type
== ID($macc
)) {
990 param(ID::CONFIG_WIDTH
);
991 port(ID::A
, param(ID::A_WIDTH
));
992 port(ID::B
, param(ID::B_WIDTH
));
993 port(ID::Y
, param(ID::Y_WIDTH
));
995 Macc().from_cell(cell
);
999 if (cell
->type
== ID($logic_not
)) {
1000 param_bool(ID::A_SIGNED
);
1001 port(ID::A
, param(ID::A_WIDTH
));
1002 port(ID::Y
, param(ID::Y_WIDTH
));
1007 if (cell
->type
.in(ID($logic_and
), ID($logic_or
))) {
1008 param_bool(ID::A_SIGNED
);
1009 param_bool(ID::B_SIGNED
);
1010 port(ID::A
, param(ID::A_WIDTH
));
1011 port(ID::B
, param(ID::B_WIDTH
));
1012 port(ID::Y
, param(ID::Y_WIDTH
));
1013 check_expected(/*check_matched_sign=*/false);
1017 if (cell
->type
== ID($slice
)) {
1019 port(ID::A
, param(ID::A_WIDTH
));
1020 port(ID::Y
, param(ID::Y_WIDTH
));
1021 if (param(ID::OFFSET
) + param(ID::Y_WIDTH
) > param(ID::A_WIDTH
))
1027 if (cell
->type
== ID($concat
)) {
1028 port(ID::A
, param(ID::A_WIDTH
));
1029 port(ID::B
, param(ID::B_WIDTH
));
1030 port(ID::Y
, param(ID::A_WIDTH
) + param(ID::B_WIDTH
));
1035 if (cell
->type
== ID($mux
)) {
1036 port(ID::A
, param(ID::WIDTH
));
1037 port(ID::B
, param(ID::WIDTH
));
1039 port(ID::Y
, param(ID::WIDTH
));
1044 if (cell
->type
== ID($pmux
)) {
1045 port(ID::A
, param(ID::WIDTH
));
1046 port(ID::B
, param(ID::WIDTH
) * param(ID::S_WIDTH
));
1047 port(ID::S
, param(ID::S_WIDTH
));
1048 port(ID::Y
, param(ID::WIDTH
));
1053 if (cell
->type
== ID($lut
)) {
1055 port(ID::A
, param(ID::WIDTH
));
1061 if (cell
->type
== ID($sop
)) {
1064 port(ID::A
, param(ID::WIDTH
));
1070 if (cell
->type
== ID($sr
)) {
1071 param_bool(ID::SET_POLARITY
);
1072 param_bool(ID::CLR_POLARITY
);
1073 port(ID::SET
, param(ID::WIDTH
));
1074 port(ID::CLR
, param(ID::WIDTH
));
1075 port(ID::Q
, param(ID::WIDTH
));
1080 if (cell
->type
== ID($ff
)) {
1081 port(ID::D
, param(ID::WIDTH
));
1082 port(ID::Q
, param(ID::WIDTH
));
1087 if (cell
->type
== ID($dff
)) {
1088 param_bool(ID::CLK_POLARITY
);
1090 port(ID::D
, param(ID::WIDTH
));
1091 port(ID::Q
, param(ID::WIDTH
));
1096 if (cell
->type
== ID($dffe
)) {
1097 param_bool(ID::CLK_POLARITY
);
1098 param_bool(ID::EN_POLARITY
);
1101 port(ID::D
, param(ID::WIDTH
));
1102 port(ID::Q
, param(ID::WIDTH
));
1107 if (cell
->type
== ID($dffsr
)) {
1108 param_bool(ID::CLK_POLARITY
);
1109 param_bool(ID::SET_POLARITY
);
1110 param_bool(ID::CLR_POLARITY
);
1112 port(ID::SET
, param(ID::WIDTH
));
1113 port(ID::CLR
, param(ID::WIDTH
));
1114 port(ID::D
, param(ID::WIDTH
));
1115 port(ID::Q
, param(ID::WIDTH
));
1120 if (cell
->type
== ID($adff
)) {
1121 param_bool(ID::CLK_POLARITY
);
1122 param_bool(ID::ARST_POLARITY
);
1123 param_bits(ID::ARST_VALUE
, param(ID::WIDTH
));
1126 port(ID::D
, param(ID::WIDTH
));
1127 port(ID::Q
, param(ID::WIDTH
));
1132 if (cell
->type
== ID($dlatch
)) {
1133 param_bool(ID::EN_POLARITY
);
1135 port(ID::D
, param(ID::WIDTH
));
1136 port(ID::Q
, param(ID::WIDTH
));
1141 if (cell
->type
== ID($dlatchsr
)) {
1142 param_bool(ID::EN_POLARITY
);
1143 param_bool(ID::SET_POLARITY
);
1144 param_bool(ID::CLR_POLARITY
);
1146 port(ID::SET
, param(ID::WIDTH
));
1147 port(ID::CLR
, param(ID::WIDTH
));
1148 port(ID::D
, param(ID::WIDTH
));
1149 port(ID::Q
, param(ID::WIDTH
));
1154 if (cell
->type
== ID($fsm
)) {
1156 param_bool(ID::CLK_POLARITY
);
1157 param_bool(ID::ARST_POLARITY
);
1158 param(ID::STATE_BITS
);
1159 param(ID::STATE_NUM
);
1160 param(ID::STATE_NUM_LOG2
);
1161 param(ID::STATE_RST
);
1162 param_bits(ID::STATE_TABLE
, param(ID::STATE_BITS
) * param(ID::STATE_NUM
));
1163 param(ID::TRANS_NUM
);
1164 param_bits(ID::TRANS_TABLE
, param(ID::TRANS_NUM
) * (2*param(ID::STATE_NUM_LOG2
) + param(ID::CTRL_IN_WIDTH
) + param(ID::CTRL_OUT_WIDTH
)));
1167 port(ID::CTRL_IN
, param(ID::CTRL_IN_WIDTH
));
1168 port(ID::CTRL_OUT
, param(ID::CTRL_OUT_WIDTH
));
1173 if (cell
->type
== ID($memrd
)) {
1175 param_bool(ID::CLK_ENABLE
);
1176 param_bool(ID::CLK_POLARITY
);
1177 param_bool(ID::TRANSPARENT
);
1180 port(ID::ADDR
, param(ID::ABITS
));
1181 port(ID::DATA
, param(ID::WIDTH
));
1186 if (cell
->type
== ID($memwr
)) {
1188 param_bool(ID::CLK_ENABLE
);
1189 param_bool(ID::CLK_POLARITY
);
1190 param(ID::PRIORITY
);
1192 port(ID::EN
, param(ID::WIDTH
));
1193 port(ID::ADDR
, param(ID::ABITS
));
1194 port(ID::DATA
, param(ID::WIDTH
));
1199 if (cell
->type
== ID($meminit
)) {
1201 param(ID::PRIORITY
);
1202 port(ID::ADDR
, param(ID::ABITS
));
1203 port(ID::DATA
, param(ID::WIDTH
) * param(ID::WORDS
));
1208 if (cell
->type
== ID($mem
)) {
1213 param_bits(ID::RD_CLK_ENABLE
, max(1, param(ID::RD_PORTS
)));
1214 param_bits(ID::RD_CLK_POLARITY
, max(1, param(ID::RD_PORTS
)));
1215 param_bits(ID::RD_TRANSPARENT
, max(1, param(ID::RD_PORTS
)));
1216 param_bits(ID::WR_CLK_ENABLE
, max(1, param(ID::WR_PORTS
)));
1217 param_bits(ID::WR_CLK_POLARITY
, max(1, param(ID::WR_PORTS
)));
1218 port(ID::RD_CLK
, param(ID::RD_PORTS
));
1219 port(ID::RD_EN
, param(ID::RD_PORTS
));
1220 port(ID::RD_ADDR
, param(ID::RD_PORTS
) * param(ID::ABITS
));
1221 port(ID::RD_DATA
, param(ID::RD_PORTS
) * param(ID::WIDTH
));
1222 port(ID::WR_CLK
, param(ID::WR_PORTS
));
1223 port(ID::WR_EN
, param(ID::WR_PORTS
) * param(ID::WIDTH
));
1224 port(ID::WR_ADDR
, param(ID::WR_PORTS
) * param(ID::ABITS
));
1225 port(ID::WR_DATA
, param(ID::WR_PORTS
) * param(ID::WIDTH
));
1230 if (cell
->type
== ID($tribuf
)) {
1231 port(ID::A
, param(ID::WIDTH
));
1232 port(ID::Y
, param(ID::WIDTH
));
1238 if (cell
->type
.in(ID($
assert), ID($assume
), ID($live
), ID($fair
), ID($cover
))) {
1245 if (cell
->type
== ID($initstate
)) {
1251 if (cell
->type
.in(ID($anyconst
), ID($anyseq
), ID($allconst
), ID($allseq
))) {
1252 port(ID::Y
, param(ID::WIDTH
));
1257 if (cell
->type
== ID($equiv
)) {
1265 if (cell
->type
.in(ID($specify2
), ID($specify3
))) {
1266 param_bool(ID::FULL
);
1267 param_bool(ID::SRC_DST_PEN
);
1268 param_bool(ID::SRC_DST_POL
);
1269 param(ID::T_RISE_MIN
);
1270 param(ID::T_RISE_TYP
);
1271 param(ID::T_RISE_MAX
);
1272 param(ID::T_FALL_MIN
);
1273 param(ID::T_FALL_TYP
);
1274 param(ID::T_FALL_MAX
);
1276 port(ID::SRC
, param(ID::SRC_WIDTH
));
1277 port(ID::DST
, param(ID::DST_WIDTH
));
1278 if (cell
->type
== ID($specify3
)) {
1279 param_bool(ID::EDGE_EN
);
1280 param_bool(ID::EDGE_POL
);
1281 param_bool(ID::DAT_DST_PEN
);
1282 param_bool(ID::DAT_DST_POL
);
1283 port(ID::DAT
, param(ID::DST_WIDTH
));
1289 if (cell
->type
== ID($specrule
)) {
1291 param_bool(ID::SRC_PEN
);
1292 param_bool(ID::SRC_POL
);
1293 param_bool(ID::DST_PEN
);
1294 param_bool(ID::DST_POL
);
1295 param(ID::T_LIMIT_MIN
);
1296 param(ID::T_LIMIT_TYP
);
1297 param(ID::T_LIMIT_MAX
);
1298 param(ID::T_LIMIT2_MIN
);
1299 param(ID::T_LIMIT2_TYP
);
1300 param(ID::T_LIMIT2_MAX
);
1301 port(ID::SRC_EN
, 1);
1302 port(ID::DST_EN
, 1);
1303 port(ID::SRC
, param(ID::SRC_WIDTH
));
1304 port(ID::DST
, param(ID::DST_WIDTH
));
1309 if (cell
->type
== ID($_BUF_
)) { port(ID::A
,1); port(ID::Y
,1); check_expected(); return; }
1310 if (cell
->type
== ID($_NOT_
)) { port(ID::A
,1); port(ID::Y
,1); check_expected(); return; }
1311 if (cell
->type
== ID($_AND_
)) { port(ID::A
,1); port(ID::B
,1); port(ID::Y
,1); check_expected(); return; }
1312 if (cell
->type
== ID($_NAND_
)) { port(ID::A
,1); port(ID::B
,1); port(ID::Y
,1); check_expected(); return; }
1313 if (cell
->type
== ID($_OR_
)) { port(ID::A
,1); port(ID::B
,1); port(ID::Y
,1); check_expected(); return; }
1314 if (cell
->type
== ID($_NOR_
)) { port(ID::A
,1); port(ID::B
,1); port(ID::Y
,1); check_expected(); return; }
1315 if (cell
->type
== ID($_XOR_
)) { port(ID::A
,1); port(ID::B
,1); port(ID::Y
,1); check_expected(); return; }
1316 if (cell
->type
== ID($_XNOR_
)) { port(ID::A
,1); port(ID::B
,1); port(ID::Y
,1); check_expected(); return; }
1317 if (cell
->type
== ID($_ANDNOT_
)) { port(ID::A
,1); port(ID::B
,1); port(ID::Y
,1); check_expected(); return; }
1318 if (cell
->type
== ID($_ORNOT_
)) { port(ID::A
,1); port(ID::B
,1); port(ID::Y
,1); check_expected(); return; }
1319 if (cell
->type
== ID($_MUX_
)) { port(ID::A
,1); port(ID::B
,1); port(ID::S
,1); port(ID::Y
,1); check_expected(); return; }
1320 if (cell
->type
== ID($_NMUX_
)) { port(ID::A
,1); port(ID::B
,1); port(ID::S
,1); port(ID::Y
,1); check_expected(); return; }
1321 if (cell
->type
== ID($_AOI3_
)) { port(ID::A
,1); port(ID::B
,1); port(ID::C
,1); port(ID::Y
,1); check_expected(); return; }
1322 if (cell
->type
== ID($_OAI3_
)) { port(ID::A
,1); port(ID::B
,1); port(ID::C
,1); port(ID::Y
,1); check_expected(); return; }
1323 if (cell
->type
== ID($_AOI4_
)) { port(ID::A
,1); port(ID::B
,1); port(ID::C
,1); port(ID::D
,1); port(ID::Y
,1); check_expected(); return; }
1324 if (cell
->type
== ID($_OAI4_
)) { port(ID::A
,1); port(ID::B
,1); port(ID::C
,1); port(ID::D
,1); port(ID::Y
,1); check_expected(); return; }
1326 if (cell
->type
== ID($_TBUF_
)) { port(ID::A
,1); port(ID::Y
,1); port(ID::E
,1); check_expected(); return; }
1328 if (cell
->type
== ID($_MUX4_
)) { port(ID::A
,1); port(ID::B
,1); port(ID::C
,1); port(ID::D
,1); port(ID::S
,1); port(ID::T
,1); port(ID::Y
,1); check_expected(); return; }
1329 if (cell
->type
== ID($_MUX8_
)) { port(ID::A
,1); port(ID::B
,1); port(ID::C
,1); port(ID::D
,1); port(ID::E
,1); port(ID::F
,1); port(ID::G
,1); port(ID::H
,1); port(ID::S
,1); port(ID::T
,1); port(ID::U
,1); port(ID::Y
,1); check_expected(); return; }
1330 if (cell
->type
== ID($_MUX16_
)) { port(ID::A
,1); port(ID::B
,1); port(ID::C
,1); port(ID::D
,1); port(ID::E
,1); port(ID::F
,1); port(ID::G
,1); port(ID::H
,1); port(ID::I
,1); port(ID::J
,1); port(ID::K
,1); port(ID::L
,1); port(ID::M
,1); port(ID::N
,1); port(ID::O
,1); port(ID::P
,1); port(ID::S
,1); port(ID::T
,1); port(ID::U
,1); port(ID::V
,1); port(ID::Y
,1); check_expected(); return; }
1332 if (cell
->type
== ID($_SR_NN_
)) { port(ID::S
,1); port(ID::R
,1); port(ID::Q
,1); check_expected(); return; }
1333 if (cell
->type
== ID($_SR_NP_
)) { port(ID::S
,1); port(ID::R
,1); port(ID::Q
,1); check_expected(); return; }
1334 if (cell
->type
== ID($_SR_PN_
)) { port(ID::S
,1); port(ID::R
,1); port(ID::Q
,1); check_expected(); return; }
1335 if (cell
->type
== ID($_SR_PP_
)) { port(ID::S
,1); port(ID::R
,1); port(ID::Q
,1); check_expected(); return; }
1337 if (cell
->type
== ID($_FF_
)) { port(ID::D
,1); port(ID::Q
,1); check_expected(); return; }
1338 if (cell
->type
== ID($_DFF_N_
)) { port(ID::D
,1); port(ID::Q
,1); port(ID::C
,1); check_expected(); return; }
1339 if (cell
->type
== ID($_DFF_P_
)) { port(ID::D
,1); port(ID::Q
,1); port(ID::C
,1); check_expected(); return; }
1341 if (cell
->type
== ID($_DFFE_NN_
)) { port(ID::D
,1); port(ID::Q
,1); port(ID::C
,1); port(ID::E
,1); check_expected(); return; }
1342 if (cell
->type
== ID($_DFFE_NP_
)) { port(ID::D
,1); port(ID::Q
,1); port(ID::C
,1); port(ID::E
,1); check_expected(); return; }
1343 if (cell
->type
== ID($_DFFE_PN_
)) { port(ID::D
,1); port(ID::Q
,1); port(ID::C
,1); port(ID::E
,1); check_expected(); return; }
1344 if (cell
->type
== ID($_DFFE_PP_
)) { port(ID::D
,1); port(ID::Q
,1); port(ID::C
,1); port(ID::E
,1); check_expected(); return; }
1346 if (cell
->type
== ID($_DFF_NN0_
)) { port(ID::D
,1); port(ID::Q
,1); port(ID::C
,1); port(ID::R
,1); check_expected(); return; }
1347 if (cell
->type
== ID($_DFF_NN1_
)) { port(ID::D
,1); port(ID::Q
,1); port(ID::C
,1); port(ID::R
,1); check_expected(); return; }
1348 if (cell
->type
== ID($_DFF_NP0_
)) { port(ID::D
,1); port(ID::Q
,1); port(ID::C
,1); port(ID::R
,1); check_expected(); return; }
1349 if (cell
->type
== ID($_DFF_NP1_
)) { port(ID::D
,1); port(ID::Q
,1); port(ID::C
,1); port(ID::R
,1); check_expected(); return; }
1350 if (cell
->type
== ID($_DFF_PN0_
)) { port(ID::D
,1); port(ID::Q
,1); port(ID::C
,1); port(ID::R
,1); check_expected(); return; }
1351 if (cell
->type
== ID($_DFF_PN1_
)) { port(ID::D
,1); port(ID::Q
,1); port(ID::C
,1); port(ID::R
,1); check_expected(); return; }
1352 if (cell
->type
== ID($_DFF_PP0_
)) { port(ID::D
,1); port(ID::Q
,1); port(ID::C
,1); port(ID::R
,1); check_expected(); return; }
1353 if (cell
->type
== ID($_DFF_PP1_
)) { port(ID::D
,1); port(ID::Q
,1); port(ID::C
,1); port(ID::R
,1); check_expected(); return; }
1355 if (cell
->type
== ID($_DFFSR_NNN_
)) { port(ID::C
,1); port(ID::S
,1); port(ID::R
,1); port(ID::D
,1); port(ID::Q
,1); check_expected(); return; }
1356 if (cell
->type
== ID($_DFFSR_NNP_
)) { port(ID::C
,1); port(ID::S
,1); port(ID::R
,1); port(ID::D
,1); port(ID::Q
,1); check_expected(); return; }
1357 if (cell
->type
== ID($_DFFSR_NPN_
)) { port(ID::C
,1); port(ID::S
,1); port(ID::R
,1); port(ID::D
,1); port(ID::Q
,1); check_expected(); return; }
1358 if (cell
->type
== ID($_DFFSR_NPP_
)) { port(ID::C
,1); port(ID::S
,1); port(ID::R
,1); port(ID::D
,1); port(ID::Q
,1); check_expected(); return; }
1359 if (cell
->type
== ID($_DFFSR_PNN_
)) { port(ID::C
,1); port(ID::S
,1); port(ID::R
,1); port(ID::D
,1); port(ID::Q
,1); check_expected(); return; }
1360 if (cell
->type
== ID($_DFFSR_PNP_
)) { port(ID::C
,1); port(ID::S
,1); port(ID::R
,1); port(ID::D
,1); port(ID::Q
,1); check_expected(); return; }
1361 if (cell
->type
== ID($_DFFSR_PPN_
)) { port(ID::C
,1); port(ID::S
,1); port(ID::R
,1); port(ID::D
,1); port(ID::Q
,1); check_expected(); return; }
1362 if (cell
->type
== ID($_DFFSR_PPP_
)) { port(ID::C
,1); port(ID::S
,1); port(ID::R
,1); port(ID::D
,1); port(ID::Q
,1); check_expected(); return; }
1364 if (cell
->type
== ID($_DLATCH_N_
)) { port(ID::E
,1); port(ID::D
,1); port(ID::Q
,1); check_expected(); return; }
1365 if (cell
->type
== ID($_DLATCH_P_
)) { port(ID::E
,1); port(ID::D
,1); port(ID::Q
,1); check_expected(); return; }
1367 if (cell
->type
== ID($_DLATCHSR_NNN_
)) { port(ID::E
,1); port(ID::S
,1); port(ID::R
,1); port(ID::D
,1); port(ID::Q
,1); check_expected(); return; }
1368 if (cell
->type
== ID($_DLATCHSR_NNP_
)) { port(ID::E
,1); port(ID::S
,1); port(ID::R
,1); port(ID::D
,1); port(ID::Q
,1); check_expected(); return; }
1369 if (cell
->type
== ID($_DLATCHSR_NPN_
)) { port(ID::E
,1); port(ID::S
,1); port(ID::R
,1); port(ID::D
,1); port(ID::Q
,1); check_expected(); return; }
1370 if (cell
->type
== ID($_DLATCHSR_NPP_
)) { port(ID::E
,1); port(ID::S
,1); port(ID::R
,1); port(ID::D
,1); port(ID::Q
,1); check_expected(); return; }
1371 if (cell
->type
== ID($_DLATCHSR_PNN_
)) { port(ID::E
,1); port(ID::S
,1); port(ID::R
,1); port(ID::D
,1); port(ID::Q
,1); check_expected(); return; }
1372 if (cell
->type
== ID($_DLATCHSR_PNP_
)) { port(ID::E
,1); port(ID::S
,1); port(ID::R
,1); port(ID::D
,1); port(ID::Q
,1); check_expected(); return; }
1373 if (cell
->type
== ID($_DLATCHSR_PPN_
)) { port(ID::E
,1); port(ID::S
,1); port(ID::R
,1); port(ID::D
,1); port(ID::Q
,1); check_expected(); return; }
1374 if (cell
->type
== ID($_DLATCHSR_PPP_
)) { port(ID::E
,1); port(ID::S
,1); port(ID::R
,1); port(ID::D
,1); port(ID::Q
,1); check_expected(); return; }
1382 void RTLIL::Module::sort()
1384 wires_
.sort(sort_by_id_str());
1385 cells_
.sort(sort_by_id_str());
1386 avail_parameters
.sort(sort_by_id_str());
1387 memories
.sort(sort_by_id_str());
1388 processes
.sort(sort_by_id_str());
1389 for (auto &it
: cells_
)
1391 for (auto &it
: wires_
)
1392 it
.second
->attributes
.sort(sort_by_id_str());
1393 for (auto &it
: memories
)
1394 it
.second
->attributes
.sort(sort_by_id_str());
1397 void RTLIL::Module::check()
1400 std::vector
<bool> ports_declared
;
1401 for (auto &it
: wires_
) {
1402 log_assert(this == it
.second
->module
);
1403 log_assert(it
.first
== it
.second
->name
);
1404 log_assert(!it
.first
.empty());
1405 log_assert(it
.second
->width
>= 0);
1406 log_assert(it
.second
->port_id
>= 0);
1407 for (auto &it2
: it
.second
->attributes
)
1408 log_assert(!it2
.first
.empty());
1409 if (it
.second
->port_id
) {
1410 log_assert(GetSize(ports
) >= it
.second
->port_id
);
1411 log_assert(ports
.at(it
.second
->port_id
-1) == it
.first
);
1412 log_assert(it
.second
->port_input
|| it
.second
->port_output
);
1413 if (GetSize(ports_declared
) < it
.second
->port_id
)
1414 ports_declared
.resize(it
.second
->port_id
);
1415 log_assert(ports_declared
[it
.second
->port_id
-1] == false);
1416 ports_declared
[it
.second
->port_id
-1] = true;
1418 log_assert(!it
.second
->port_input
&& !it
.second
->port_output
);
1420 for (auto port_declared
: ports_declared
)
1421 log_assert(port_declared
== true);
1422 log_assert(GetSize(ports
) == GetSize(ports_declared
));
1424 for (auto &it
: memories
) {
1425 log_assert(it
.first
== it
.second
->name
);
1426 log_assert(!it
.first
.empty());
1427 log_assert(it
.second
->width
>= 0);
1428 log_assert(it
.second
->size
>= 0);
1429 for (auto &it2
: it
.second
->attributes
)
1430 log_assert(!it2
.first
.empty());
1433 for (auto &it
: cells_
) {
1434 log_assert(this == it
.second
->module
);
1435 log_assert(it
.first
== it
.second
->name
);
1436 log_assert(!it
.first
.empty());
1437 log_assert(!it
.second
->type
.empty());
1438 for (auto &it2
: it
.second
->connections()) {
1439 log_assert(!it2
.first
.empty());
1442 for (auto &it2
: it
.second
->attributes
)
1443 log_assert(!it2
.first
.empty());
1444 for (auto &it2
: it
.second
->parameters
)
1445 log_assert(!it2
.first
.empty());
1446 InternalCellChecker
checker(this, it
.second
);
1450 for (auto &it
: processes
) {
1451 log_assert(it
.first
== it
.second
->name
);
1452 log_assert(!it
.first
.empty());
1453 log_assert(it
.second
->root_case
.compare
.empty());
1454 std::vector
<CaseRule
*> all_cases
= {&it
.second
->root_case
};
1455 for (size_t i
= 0; i
< all_cases
.size(); i
++) {
1456 for (auto &switch_it
: all_cases
[i
]->switches
) {
1457 for (auto &case_it
: switch_it
->cases
) {
1458 for (auto &compare_it
: case_it
->compare
) {
1459 log_assert(switch_it
->signal
.size() == compare_it
.size());
1461 all_cases
.push_back(case_it
);
1465 for (auto &sync_it
: it
.second
->syncs
) {
1466 switch (sync_it
->type
) {
1472 log_assert(!sync_it
->signal
.empty());
1477 log_assert(sync_it
->signal
.empty());
1483 for (auto &it
: connections_
) {
1484 log_assert(it
.first
.size() == it
.second
.size());
1485 log_assert(!it
.first
.has_const());
1490 for (auto &it
: attributes
)
1491 log_assert(!it
.first
.empty());
1495 void RTLIL::Module::optimize()
1499 void RTLIL::Module::cloneInto(RTLIL::Module
*new_mod
) const
1501 log_assert(new_mod
->refcount_wires_
== 0);
1502 log_assert(new_mod
->refcount_cells_
== 0);
1504 new_mod
->avail_parameters
= avail_parameters
;
1506 for (auto &conn
: connections_
)
1507 new_mod
->connect(conn
);
1509 for (auto &attr
: attributes
)
1510 new_mod
->attributes
[attr
.first
] = attr
.second
;
1512 for (auto &it
: wires_
)
1513 new_mod
->addWire(it
.first
, it
.second
);
1515 for (auto &it
: memories
)
1516 new_mod
->memories
[it
.first
] = new RTLIL::Memory(*it
.second
);
1518 for (auto &it
: cells_
)
1519 new_mod
->addCell(it
.first
, it
.second
);
1521 for (auto &it
: processes
)
1522 new_mod
->processes
[it
.first
] = it
.second
->clone();
1524 struct RewriteSigSpecWorker
1527 void operator()(RTLIL::SigSpec
&sig
)
1530 for (auto &c
: sig
.chunks_
)
1532 c
.wire
= mod
->wires_
.at(c
.wire
->name
);
1536 RewriteSigSpecWorker rewriteSigSpecWorker
;
1537 rewriteSigSpecWorker
.mod
= new_mod
;
1538 new_mod
->rewrite_sigspecs(rewriteSigSpecWorker
);
1539 new_mod
->fixup_ports();
1542 RTLIL::Module
*RTLIL::Module::clone() const
1544 RTLIL::Module
*new_mod
= new RTLIL::Module
;
1545 new_mod
->name
= name
;
1550 bool RTLIL::Module::has_memories() const
1552 return !memories
.empty();
1555 bool RTLIL::Module::has_processes() const
1557 return !processes
.empty();
1560 bool RTLIL::Module::has_memories_warn() const
1562 if (!memories
.empty())
1563 log_warning("Ignoring module %s because it contains memories (run 'memory' command first).\n", log_id(this));
1564 return !memories
.empty();
1567 bool RTLIL::Module::has_processes_warn() const
1569 if (!processes
.empty())
1570 log_warning("Ignoring module %s because it contains processes (run 'proc' command first).\n", log_id(this));
1571 return !processes
.empty();
1574 std::vector
<RTLIL::Wire
*> RTLIL::Module::selected_wires() const
1576 std::vector
<RTLIL::Wire
*> result
;
1577 result
.reserve(wires_
.size());
1578 for (auto &it
: wires_
)
1579 if (design
->selected(this, it
.second
))
1580 result
.push_back(it
.second
);
1584 std::vector
<RTLIL::Cell
*> RTLIL::Module::selected_cells() const
1586 std::vector
<RTLIL::Cell
*> result
;
1587 result
.reserve(cells_
.size());
1588 for (auto &it
: cells_
)
1589 if (design
->selected(this, it
.second
))
1590 result
.push_back(it
.second
);
1594 void RTLIL::Module::add(RTLIL::Wire
*wire
)
1596 log_assert(!wire
->name
.empty());
1597 log_assert(count_id(wire
->name
) == 0);
1598 log_assert(refcount_wires_
== 0);
1599 wires_
[wire
->name
] = wire
;
1600 wire
->module
= this;
1603 void RTLIL::Module::add(RTLIL::Cell
*cell
)
1605 log_assert(!cell
->name
.empty());
1606 log_assert(count_id(cell
->name
) == 0);
1607 log_assert(refcount_cells_
== 0);
1608 cells_
[cell
->name
] = cell
;
1609 cell
->module
= this;
1612 void RTLIL::Module::remove(const pool
<RTLIL::Wire
*> &wires
)
1614 log_assert(refcount_wires_
== 0);
1616 struct DeleteWireWorker
1618 RTLIL::Module
*module
;
1619 const pool
<RTLIL::Wire
*> *wires_p
;
1621 void operator()(RTLIL::SigSpec
&sig
) {
1623 for (auto &c
: sig
.chunks_
)
1624 if (c
.wire
!= NULL
&& wires_p
->count(c
.wire
)) {
1625 c
.wire
= module
->addWire(NEW_ID
, c
.width
);
1630 void operator()(RTLIL::SigSpec
&lhs
, RTLIL::SigSpec
&rhs
) {
1631 log_assert(GetSize(lhs
) == GetSize(rhs
));
1634 for (int i
= 0; i
< GetSize(lhs
); i
++) {
1635 RTLIL::SigBit
&lhs_bit
= lhs
.bits_
[i
];
1636 RTLIL::SigBit
&rhs_bit
= rhs
.bits_
[i
];
1637 if ((lhs_bit
.wire
!= nullptr && wires_p
->count(lhs_bit
.wire
)) || (rhs_bit
.wire
!= nullptr && wires_p
->count(rhs_bit
.wire
))) {
1638 lhs_bit
= State::Sx
;
1639 rhs_bit
= State::Sx
;
1645 DeleteWireWorker delete_wire_worker
;
1646 delete_wire_worker
.module
= this;
1647 delete_wire_worker
.wires_p
= &wires
;
1648 rewrite_sigspecs2(delete_wire_worker
);
1650 for (auto &it
: wires
) {
1651 log_assert(wires_
.count(it
->name
) != 0);
1652 wires_
.erase(it
->name
);
1657 void RTLIL::Module::remove(RTLIL::Cell
*cell
)
1659 while (!cell
->connections_
.empty())
1660 cell
->unsetPort(cell
->connections_
.begin()->first
);
1662 log_assert(cells_
.count(cell
->name
) != 0);
1663 log_assert(refcount_cells_
== 0);
1664 cells_
.erase(cell
->name
);
1668 void RTLIL::Module::rename(RTLIL::Wire
*wire
, RTLIL::IdString new_name
)
1670 log_assert(wires_
[wire
->name
] == wire
);
1671 log_assert(refcount_wires_
== 0);
1672 wires_
.erase(wire
->name
);
1673 wire
->name
= new_name
;
1677 void RTLIL::Module::rename(RTLIL::Cell
*cell
, RTLIL::IdString new_name
)
1679 log_assert(cells_
[cell
->name
] == cell
);
1680 log_assert(refcount_wires_
== 0);
1681 cells_
.erase(cell
->name
);
1682 cell
->name
= new_name
;
1686 void RTLIL::Module::rename(RTLIL::IdString old_name
, RTLIL::IdString new_name
)
1688 log_assert(count_id(old_name
) != 0);
1689 if (wires_
.count(old_name
))
1690 rename(wires_
.at(old_name
), new_name
);
1691 else if (cells_
.count(old_name
))
1692 rename(cells_
.at(old_name
), new_name
);
1697 void RTLIL::Module::swap_names(RTLIL::Wire
*w1
, RTLIL::Wire
*w2
)
1699 log_assert(wires_
[w1
->name
] == w1
);
1700 log_assert(wires_
[w2
->name
] == w2
);
1701 log_assert(refcount_wires_
== 0);
1703 wires_
.erase(w1
->name
);
1704 wires_
.erase(w2
->name
);
1706 std::swap(w1
->name
, w2
->name
);
1708 wires_
[w1
->name
] = w1
;
1709 wires_
[w2
->name
] = w2
;
1712 void RTLIL::Module::swap_names(RTLIL::Cell
*c1
, RTLIL::Cell
*c2
)
1714 log_assert(cells_
[c1
->name
] == c1
);
1715 log_assert(cells_
[c2
->name
] == c2
);
1716 log_assert(refcount_cells_
== 0);
1718 cells_
.erase(c1
->name
);
1719 cells_
.erase(c2
->name
);
1721 std::swap(c1
->name
, c2
->name
);
1723 cells_
[c1
->name
] = c1
;
1724 cells_
[c2
->name
] = c2
;
1727 RTLIL::IdString
RTLIL::Module::uniquify(RTLIL::IdString name
)
1730 return uniquify(name
, index
);
1733 RTLIL::IdString
RTLIL::Module::uniquify(RTLIL::IdString name
, int &index
)
1736 if (count_id(name
) == 0)
1742 RTLIL::IdString new_name
= stringf("%s_%d", name
.c_str(), index
);
1743 if (count_id(new_name
) == 0)
1749 static bool fixup_ports_compare(const RTLIL::Wire
*a
, const RTLIL::Wire
*b
)
1751 if (a
->port_id
&& !b
->port_id
)
1753 if (!a
->port_id
&& b
->port_id
)
1756 if (a
->port_id
== b
->port_id
)
1757 return a
->name
< b
->name
;
1758 return a
->port_id
< b
->port_id
;
1761 void RTLIL::Module::connect(const RTLIL::SigSig
&conn
)
1763 for (auto mon
: monitors
)
1764 mon
->notify_connect(this, conn
);
1767 for (auto mon
: design
->monitors
)
1768 mon
->notify_connect(this, conn
);
1770 // ignore all attempts to assign constants to other constants
1771 if (conn
.first
.has_const()) {
1772 RTLIL::SigSig new_conn
;
1773 for (int i
= 0; i
< GetSize(conn
.first
); i
++)
1774 if (conn
.first
[i
].wire
) {
1775 new_conn
.first
.append(conn
.first
[i
]);
1776 new_conn
.second
.append(conn
.second
[i
]);
1778 if (GetSize(new_conn
.first
))
1784 log("#X# Connect (SigSig) in %s: %s = %s (%d bits)\n", log_id(this), log_signal(conn
.first
), log_signal(conn
.second
), GetSize(conn
.first
));
1785 log_backtrace("-X- ", yosys_xtrace
-1);
1788 log_assert(GetSize(conn
.first
) == GetSize(conn
.second
));
1789 connections_
.push_back(conn
);
1792 void RTLIL::Module::connect(const RTLIL::SigSpec
&lhs
, const RTLIL::SigSpec
&rhs
)
1794 connect(RTLIL::SigSig(lhs
, rhs
));
1797 void RTLIL::Module::new_connections(const std::vector
<RTLIL::SigSig
> &new_conn
)
1799 for (auto mon
: monitors
)
1800 mon
->notify_connect(this, new_conn
);
1803 for (auto mon
: design
->monitors
)
1804 mon
->notify_connect(this, new_conn
);
1807 log("#X# New connections vector in %s:\n", log_id(this));
1808 for (auto &conn
: new_conn
)
1809 log("#X# %s = %s (%d bits)\n", log_signal(conn
.first
), log_signal(conn
.second
), GetSize(conn
.first
));
1810 log_backtrace("-X- ", yosys_xtrace
-1);
1813 connections_
= new_conn
;
1816 const std::vector
<RTLIL::SigSig
> &RTLIL::Module::connections() const
1818 return connections_
;
1821 void RTLIL::Module::fixup_ports()
1823 std::vector
<RTLIL::Wire
*> all_ports
;
1825 for (auto &w
: wires_
)
1826 if (w
.second
->port_input
|| w
.second
->port_output
)
1827 all_ports
.push_back(w
.second
);
1829 w
.second
->port_id
= 0;
1831 std::sort(all_ports
.begin(), all_ports
.end(), fixup_ports_compare
);
1834 for (size_t i
= 0; i
< all_ports
.size(); i
++) {
1835 ports
.push_back(all_ports
[i
]->name
);
1836 all_ports
[i
]->port_id
= i
+1;
1840 RTLIL::Wire
*RTLIL::Module::addWire(RTLIL::IdString name
, int width
)
1842 RTLIL::Wire
*wire
= new RTLIL::Wire
;
1844 wire
->width
= width
;
1849 RTLIL::Wire
*RTLIL::Module::addWire(RTLIL::IdString name
, const RTLIL::Wire
*other
)
1851 RTLIL::Wire
*wire
= addWire(name
);
1852 wire
->width
= other
->width
;
1853 wire
->start_offset
= other
->start_offset
;
1854 wire
->port_id
= other
->port_id
;
1855 wire
->port_input
= other
->port_input
;
1856 wire
->port_output
= other
->port_output
;
1857 wire
->upto
= other
->upto
;
1858 wire
->attributes
= other
->attributes
;
1862 RTLIL::Cell
*RTLIL::Module::addCell(RTLIL::IdString name
, RTLIL::IdString type
)
1864 RTLIL::Cell
*cell
= new RTLIL::Cell
;
1871 RTLIL::Cell
*RTLIL::Module::addCell(RTLIL::IdString name
, const RTLIL::Cell
*other
)
1873 RTLIL::Cell
*cell
= addCell(name
, other
->type
);
1874 cell
->connections_
= other
->connections_
;
1875 cell
->parameters
= other
->parameters
;
1876 cell
->attributes
= other
->attributes
;
1880 #define DEF_METHOD(_func, _y_size, _type) \
1881 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed, const std::string &src) { \
1882 RTLIL::Cell *cell = addCell(name, _type); \
1883 cell->parameters[ID::A_SIGNED] = is_signed; \
1884 cell->parameters[ID::A_WIDTH] = sig_a.size(); \
1885 cell->parameters[ID::Y_WIDTH] = sig_y.size(); \
1886 cell->setPort(ID::A, sig_a); \
1887 cell->setPort(ID::Y, sig_y); \
1888 cell->set_src_attribute(src); \
1891 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed, const std::string &src) { \
1892 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
1893 add ## _func(name, sig_a, sig_y, is_signed, src); \
1896 DEF_METHOD(Not
, sig_a
.size(), ID($
not))
1897 DEF_METHOD(Pos
, sig_a
.size(), ID($pos
))
1898 DEF_METHOD(Neg
, sig_a
.size(), ID($neg
))
1899 DEF_METHOD(ReduceAnd
, 1, ID($reduce_and
))
1900 DEF_METHOD(ReduceOr
, 1, ID($reduce_or
))
1901 DEF_METHOD(ReduceXor
, 1, ID($reduce_xor
))
1902 DEF_METHOD(ReduceXnor
, 1, ID($reduce_xnor
))
1903 DEF_METHOD(ReduceBool
, 1, ID($reduce_bool
))
1904 DEF_METHOD(LogicNot
, 1, ID($logic_not
))
1907 #define DEF_METHOD(_func, _y_size, _type) \
1908 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed, const std::string &src) { \
1909 RTLIL::Cell *cell = addCell(name, _type); \
1910 cell->parameters[ID::A_SIGNED] = is_signed; \
1911 cell->parameters[ID::B_SIGNED] = is_signed; \
1912 cell->parameters[ID::A_WIDTH] = sig_a.size(); \
1913 cell->parameters[ID::B_WIDTH] = sig_b.size(); \
1914 cell->parameters[ID::Y_WIDTH] = sig_y.size(); \
1915 cell->setPort(ID::A, sig_a); \
1916 cell->setPort(ID::B, sig_b); \
1917 cell->setPort(ID::Y, sig_y); \
1918 cell->set_src_attribute(src); \
1921 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed, const std::string &src) { \
1922 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
1923 add ## _func(name, sig_a, sig_b, sig_y, is_signed, src); \
1926 DEF_METHOD(And
, max(sig_a
.size(), sig_b
.size()), ID($
and))
1927 DEF_METHOD(Or
, max(sig_a
.size(), sig_b
.size()), ID($
or))
1928 DEF_METHOD(Xor
, max(sig_a
.size(), sig_b
.size()), ID($
xor))
1929 DEF_METHOD(Xnor
, max(sig_a
.size(), sig_b
.size()), ID($xnor
))
1930 DEF_METHOD(Shift
, sig_a
.size(), ID($shift
))
1931 DEF_METHOD(Shiftx
, sig_a
.size(), ID($shiftx
))
1932 DEF_METHOD(Lt
, 1, ID($lt
))
1933 DEF_METHOD(Le
, 1, ID($le
))
1934 DEF_METHOD(Eq
, 1, ID($eq
))
1935 DEF_METHOD(Ne
, 1, ID($ne
))
1936 DEF_METHOD(Eqx
, 1, ID($eqx
))
1937 DEF_METHOD(Nex
, 1, ID($nex
))
1938 DEF_METHOD(Ge
, 1, ID($ge
))
1939 DEF_METHOD(Gt
, 1, ID($gt
))
1940 DEF_METHOD(Add
, max(sig_a
.size(), sig_b
.size()), ID($add
))
1941 DEF_METHOD(Sub
, max(sig_a
.size(), sig_b
.size()), ID($sub
))
1942 DEF_METHOD(Mul
, max(sig_a
.size(), sig_b
.size()), ID($mul
))
1943 DEF_METHOD(Div
, max(sig_a
.size(), sig_b
.size()), ID($div
))
1944 DEF_METHOD(Mod
, max(sig_a
.size(), sig_b
.size()), ID($mod
))
1945 DEF_METHOD(LogicAnd
, 1, ID($logic_and
))
1946 DEF_METHOD(LogicOr
, 1, ID($logic_or
))
1949 #define DEF_METHOD(_func, _y_size, _type) \
1950 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed, const std::string &src) { \
1951 RTLIL::Cell *cell = addCell(name, _type); \
1952 cell->parameters[ID::A_SIGNED] = is_signed; \
1953 cell->parameters[ID::B_SIGNED] = false; \
1954 cell->parameters[ID::A_WIDTH] = sig_a.size(); \
1955 cell->parameters[ID::B_WIDTH] = sig_b.size(); \
1956 cell->parameters[ID::Y_WIDTH] = sig_y.size(); \
1957 cell->setPort(ID::A, sig_a); \
1958 cell->setPort(ID::B, sig_b); \
1959 cell->setPort(ID::Y, sig_y); \
1960 cell->set_src_attribute(src); \
1963 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed, const std::string &src) { \
1964 RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
1965 add ## _func(name, sig_a, sig_b, sig_y, is_signed, src); \
1968 DEF_METHOD(Shl
, sig_a
.size(), ID($shl
))
1969 DEF_METHOD(Shr
, sig_a
.size(), ID($shr
))
1970 DEF_METHOD(Sshl
, sig_a
.size(), ID($sshl
))
1971 DEF_METHOD(Sshr
, sig_a
.size(), ID($sshr
))
1974 #define DEF_METHOD(_func, _type, _pmux) \
1975 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, const std::string &src) { \
1976 RTLIL::Cell *cell = addCell(name, _type); \
1977 cell->parameters[ID::WIDTH] = sig_a.size(); \
1978 if (_pmux) cell->parameters[ID::S_WIDTH] = sig_s.size(); \
1979 cell->setPort(ID::A, sig_a); \
1980 cell->setPort(ID::B, sig_b); \
1981 cell->setPort(ID::S, sig_s); \
1982 cell->setPort(ID::Y, sig_y); \
1983 cell->set_src_attribute(src); \
1986 RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const std::string &src) { \
1987 RTLIL::SigSpec sig_y = addWire(NEW_ID, sig_a.size()); \
1988 add ## _func(name, sig_a, sig_b, sig_s, sig_y, src); \
1991 DEF_METHOD(Mux
, ID($mux
), 0)
1992 DEF_METHOD(Pmux
, ID($pmux
), 1)
1995 #define DEF_METHOD_2(_func, _type, _P1, _P2) \
1996 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const std::string &src) { \
1997 RTLIL::Cell *cell = addCell(name, _type); \
1998 cell->setPort("\\" #_P1, sig1); \
1999 cell->setPort("\\" #_P2, sig2); \
2000 cell->set_src_attribute(src); \
2003 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const std::string &src) { \
2004 RTLIL::SigBit sig2 = addWire(NEW_ID); \
2005 add ## _func(name, sig1, sig2, src); \
2008 #define DEF_METHOD_3(_func, _type, _P1, _P2, _P3) \
2009 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const RTLIL::SigBit &sig3, const std::string &src) { \
2010 RTLIL::Cell *cell = addCell(name, _type); \
2011 cell->setPort("\\" #_P1, sig1); \
2012 cell->setPort("\\" #_P2, sig2); \
2013 cell->setPort("\\" #_P3, sig3); \
2014 cell->set_src_attribute(src); \
2017 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const std::string &src) { \
2018 RTLIL::SigBit sig3 = addWire(NEW_ID); \
2019 add ## _func(name, sig1, sig2, sig3, src); \
2022 #define DEF_METHOD_4(_func, _type, _P1, _P2, _P3, _P4) \
2023 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const RTLIL::SigBit &sig3, const RTLIL::SigBit &sig4, const std::string &src) { \
2024 RTLIL::Cell *cell = addCell(name, _type); \
2025 cell->setPort("\\" #_P1, sig1); \
2026 cell->setPort("\\" #_P2, sig2); \
2027 cell->setPort("\\" #_P3, sig3); \
2028 cell->setPort("\\" #_P4, sig4); \
2029 cell->set_src_attribute(src); \
2032 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const RTLIL::SigBit &sig3, const std::string &src) { \
2033 RTLIL::SigBit sig4 = addWire(NEW_ID); \
2034 add ## _func(name, sig1, sig2, sig3, sig4, src); \
2037 #define DEF_METHOD_5(_func, _type, _P1, _P2, _P3, _P4, _P5) \
2038 RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const RTLIL::SigBit &sig3, const RTLIL::SigBit &sig4, const RTLIL::SigBit &sig5, const std::string &src) { \
2039 RTLIL::Cell *cell = addCell(name, _type); \
2040 cell->setPort("\\" #_P1, sig1); \
2041 cell->setPort("\\" #_P2, sig2); \
2042 cell->setPort("\\" #_P3, sig3); \
2043 cell->setPort("\\" #_P4, sig4); \
2044 cell->setPort("\\" #_P5, sig5); \
2045 cell->set_src_attribute(src); \
2048 RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const RTLIL::SigBit &sig3, const RTLIL::SigBit &sig4, const std::string &src) { \
2049 RTLIL::SigBit sig5 = addWire(NEW_ID); \
2050 add ## _func(name, sig1, sig2, sig3, sig4, sig5, src); \
2053 DEF_METHOD_2(BufGate
, ID($_BUF_
), A
, Y
)
2054 DEF_METHOD_2(NotGate
, ID($_NOT_
), A
, Y
)
2055 DEF_METHOD_3(AndGate
, ID($_AND_
), A
, B
, Y
)
2056 DEF_METHOD_3(NandGate
, ID($_NAND_
), A
, B
, Y
)
2057 DEF_METHOD_3(OrGate
, ID($_OR_
), A
, B
, Y
)
2058 DEF_METHOD_3(NorGate
, ID($_NOR_
), A
, B
, Y
)
2059 DEF_METHOD_3(XorGate
, ID($_XOR_
), A
, B
, Y
)
2060 DEF_METHOD_3(XnorGate
, ID($_XNOR_
), A
, B
, Y
)
2061 DEF_METHOD_3(AndnotGate
, ID($_ANDNOT_
), A
, B
, Y
)
2062 DEF_METHOD_3(OrnotGate
, ID($_ORNOT_
), A
, B
, Y
)
2063 DEF_METHOD_4(MuxGate
, ID($_MUX_
), A
, B
, S
, Y
)
2064 DEF_METHOD_4(NmuxGate
, ID($_NMUX_
), A
, B
, S
, Y
)
2065 DEF_METHOD_4(Aoi3Gate
, ID($_AOI3_
), A
, B
, C
, Y
)
2066 DEF_METHOD_4(Oai3Gate
, ID($_OAI3_
), A
, B
, C
, Y
)
2067 DEF_METHOD_5(Aoi4Gate
, ID($_AOI4_
), A
, B
, C
, D
, Y
)
2068 DEF_METHOD_5(Oai4Gate
, ID($_OAI4_
), A
, B
, C
, D
, Y
)
2074 RTLIL::Cell
* RTLIL::Module::addPow(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_a
, const RTLIL::SigSpec
&sig_b
, const RTLIL::SigSpec
&sig_y
, bool a_signed
, bool b_signed
, const std::string
&src
)
2076 RTLIL::Cell
*cell
= addCell(name
, ID($pow
));
2077 cell
->parameters
[ID::A_SIGNED
] = a_signed
;
2078 cell
->parameters
[ID::B_SIGNED
] = b_signed
;
2079 cell
->parameters
[ID::A_WIDTH
] = sig_a
.size();
2080 cell
->parameters
[ID::B_WIDTH
] = sig_b
.size();
2081 cell
->parameters
[ID::Y_WIDTH
] = sig_y
.size();
2082 cell
->setPort(ID::A
, sig_a
);
2083 cell
->setPort(ID::B
, sig_b
);
2084 cell
->setPort(ID::Y
, sig_y
);
2085 cell
->set_src_attribute(src
);
2089 RTLIL::Cell
* RTLIL::Module::addSlice(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_a
, const RTLIL::SigSpec
&sig_y
, RTLIL::Const offset
, const std::string
&src
)
2091 RTLIL::Cell
*cell
= addCell(name
, ID($slice
));
2092 cell
->parameters
[ID::A_WIDTH
] = sig_a
.size();
2093 cell
->parameters
[ID::Y_WIDTH
] = sig_y
.size();
2094 cell
->parameters
[ID::OFFSET
] = offset
;
2095 cell
->setPort(ID::A
, sig_a
);
2096 cell
->setPort(ID::Y
, sig_y
);
2097 cell
->set_src_attribute(src
);
2101 RTLIL::Cell
* RTLIL::Module::addConcat(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_a
, const RTLIL::SigSpec
&sig_b
, const RTLIL::SigSpec
&sig_y
, const std::string
&src
)
2103 RTLIL::Cell
*cell
= addCell(name
, ID($concat
));
2104 cell
->parameters
[ID::A_WIDTH
] = sig_a
.size();
2105 cell
->parameters
[ID::B_WIDTH
] = sig_b
.size();
2106 cell
->setPort(ID::A
, sig_a
);
2107 cell
->setPort(ID::B
, sig_b
);
2108 cell
->setPort(ID::Y
, sig_y
);
2109 cell
->set_src_attribute(src
);
2113 RTLIL::Cell
* RTLIL::Module::addLut(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_a
, const RTLIL::SigSpec
&sig_y
, RTLIL::Const lut
, const std::string
&src
)
2115 RTLIL::Cell
*cell
= addCell(name
, ID($lut
));
2116 cell
->parameters
[ID::LUT
] = lut
;
2117 cell
->parameters
[ID::WIDTH
] = sig_a
.size();
2118 cell
->setPort(ID::A
, sig_a
);
2119 cell
->setPort(ID::Y
, sig_y
);
2120 cell
->set_src_attribute(src
);
2124 RTLIL::Cell
* RTLIL::Module::addTribuf(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_a
, const RTLIL::SigSpec
&sig_en
, const RTLIL::SigSpec
&sig_y
, const std::string
&src
)
2126 RTLIL::Cell
*cell
= addCell(name
, ID($tribuf
));
2127 cell
->parameters
[ID::WIDTH
] = sig_a
.size();
2128 cell
->setPort(ID::A
, sig_a
);
2129 cell
->setPort(ID::EN
, sig_en
);
2130 cell
->setPort(ID::Y
, sig_y
);
2131 cell
->set_src_attribute(src
);
2135 RTLIL::Cell
* RTLIL::Module::addAssert(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_a
, const RTLIL::SigSpec
&sig_en
, const std::string
&src
)
2137 RTLIL::Cell
*cell
= addCell(name
, ID($
assert));
2138 cell
->setPort(ID::A
, sig_a
);
2139 cell
->setPort(ID::EN
, sig_en
);
2140 cell
->set_src_attribute(src
);
2144 RTLIL::Cell
* RTLIL::Module::addAssume(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_a
, const RTLIL::SigSpec
&sig_en
, const std::string
&src
)
2146 RTLIL::Cell
*cell
= addCell(name
, ID($assume
));
2147 cell
->setPort(ID::A
, sig_a
);
2148 cell
->setPort(ID::EN
, sig_en
);
2149 cell
->set_src_attribute(src
);
2153 RTLIL::Cell
* RTLIL::Module::addLive(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_a
, const RTLIL::SigSpec
&sig_en
, const std::string
&src
)
2155 RTLIL::Cell
*cell
= addCell(name
, ID($live
));
2156 cell
->setPort(ID::A
, sig_a
);
2157 cell
->setPort(ID::EN
, sig_en
);
2158 cell
->set_src_attribute(src
);
2162 RTLIL::Cell
* RTLIL::Module::addFair(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_a
, const RTLIL::SigSpec
&sig_en
, const std::string
&src
)
2164 RTLIL::Cell
*cell
= addCell(name
, ID($fair
));
2165 cell
->setPort(ID::A
, sig_a
);
2166 cell
->setPort(ID::EN
, sig_en
);
2167 cell
->set_src_attribute(src
);
2171 RTLIL::Cell
* RTLIL::Module::addCover(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_a
, const RTLIL::SigSpec
&sig_en
, const std::string
&src
)
2173 RTLIL::Cell
*cell
= addCell(name
, ID($cover
));
2174 cell
->setPort(ID::A
, sig_a
);
2175 cell
->setPort(ID::EN
, sig_en
);
2176 cell
->set_src_attribute(src
);
2180 RTLIL::Cell
* RTLIL::Module::addEquiv(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_a
, const RTLIL::SigSpec
&sig_b
, const RTLIL::SigSpec
&sig_y
, const std::string
&src
)
2182 RTLIL::Cell
*cell
= addCell(name
, ID($equiv
));
2183 cell
->setPort(ID::A
, sig_a
);
2184 cell
->setPort(ID::B
, sig_b
);
2185 cell
->setPort(ID::Y
, sig_y
);
2186 cell
->set_src_attribute(src
);
2190 RTLIL::Cell
* RTLIL::Module::addSr(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_set
, const RTLIL::SigSpec
&sig_clr
, const RTLIL::SigSpec
&sig_q
, bool set_polarity
, bool clr_polarity
, const std::string
&src
)
2192 RTLIL::Cell
*cell
= addCell(name
, ID($sr
));
2193 cell
->parameters
[ID::SET_POLARITY
] = set_polarity
;
2194 cell
->parameters
[ID::CLR_POLARITY
] = clr_polarity
;
2195 cell
->parameters
[ID::WIDTH
] = sig_q
.size();
2196 cell
->setPort(ID::SET
, sig_set
);
2197 cell
->setPort(ID::CLR
, sig_clr
);
2198 cell
->setPort(ID::Q
, sig_q
);
2199 cell
->set_src_attribute(src
);
2203 RTLIL::Cell
* RTLIL::Module::addFf(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_d
, const RTLIL::SigSpec
&sig_q
, const std::string
&src
)
2205 RTLIL::Cell
*cell
= addCell(name
, ID($ff
));
2206 cell
->parameters
[ID::WIDTH
] = sig_q
.size();
2207 cell
->setPort(ID::D
, sig_d
);
2208 cell
->setPort(ID::Q
, sig_q
);
2209 cell
->set_src_attribute(src
);
2213 RTLIL::Cell
* RTLIL::Module::addDff(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_clk
, const RTLIL::SigSpec
&sig_d
, const RTLIL::SigSpec
&sig_q
, bool clk_polarity
, const std::string
&src
)
2215 RTLIL::Cell
*cell
= addCell(name
, ID($dff
));
2216 cell
->parameters
[ID::CLK_POLARITY
] = clk_polarity
;
2217 cell
->parameters
[ID::WIDTH
] = sig_q
.size();
2218 cell
->setPort(ID::CLK
, sig_clk
);
2219 cell
->setPort(ID::D
, sig_d
);
2220 cell
->setPort(ID::Q
, sig_q
);
2221 cell
->set_src_attribute(src
);
2225 RTLIL::Cell
* RTLIL::Module::addDffe(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_clk
, const RTLIL::SigSpec
&sig_en
, const RTLIL::SigSpec
&sig_d
, const RTLIL::SigSpec
&sig_q
, bool clk_polarity
, bool en_polarity
, const std::string
&src
)
2227 RTLIL::Cell
*cell
= addCell(name
, ID($dffe
));
2228 cell
->parameters
[ID::CLK_POLARITY
] = clk_polarity
;
2229 cell
->parameters
[ID::EN_POLARITY
] = en_polarity
;
2230 cell
->parameters
[ID::WIDTH
] = sig_q
.size();
2231 cell
->setPort(ID::CLK
, sig_clk
);
2232 cell
->setPort(ID::EN
, sig_en
);
2233 cell
->setPort(ID::D
, sig_d
);
2234 cell
->setPort(ID::Q
, sig_q
);
2235 cell
->set_src_attribute(src
);
2239 RTLIL::Cell
* RTLIL::Module::addDffsr(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_clk
, const RTLIL::SigSpec
&sig_set
, const RTLIL::SigSpec
&sig_clr
,
2240 RTLIL::SigSpec sig_d
, const RTLIL::SigSpec
&sig_q
, bool clk_polarity
, bool set_polarity
, bool clr_polarity
, const std::string
&src
)
2242 RTLIL::Cell
*cell
= addCell(name
, ID($dffsr
));
2243 cell
->parameters
[ID::CLK_POLARITY
] = clk_polarity
;
2244 cell
->parameters
[ID::SET_POLARITY
] = set_polarity
;
2245 cell
->parameters
[ID::CLR_POLARITY
] = clr_polarity
;
2246 cell
->parameters
[ID::WIDTH
] = sig_q
.size();
2247 cell
->setPort(ID::CLK
, sig_clk
);
2248 cell
->setPort(ID::SET
, sig_set
);
2249 cell
->setPort(ID::CLR
, sig_clr
);
2250 cell
->setPort(ID::D
, sig_d
);
2251 cell
->setPort(ID::Q
, sig_q
);
2252 cell
->set_src_attribute(src
);
2256 RTLIL::Cell
* RTLIL::Module::addAdff(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_clk
, const RTLIL::SigSpec
&sig_arst
, const RTLIL::SigSpec
&sig_d
, const RTLIL::SigSpec
&sig_q
,
2257 RTLIL::Const arst_value
, bool clk_polarity
, bool arst_polarity
, const std::string
&src
)
2259 RTLIL::Cell
*cell
= addCell(name
, ID($adff
));
2260 cell
->parameters
[ID::CLK_POLARITY
] = clk_polarity
;
2261 cell
->parameters
[ID::ARST_POLARITY
] = arst_polarity
;
2262 cell
->parameters
[ID::ARST_VALUE
] = arst_value
;
2263 cell
->parameters
[ID::WIDTH
] = sig_q
.size();
2264 cell
->setPort(ID::CLK
, sig_clk
);
2265 cell
->setPort(ID::ARST
, sig_arst
);
2266 cell
->setPort(ID::D
, sig_d
);
2267 cell
->setPort(ID::Q
, sig_q
);
2268 cell
->set_src_attribute(src
);
2272 RTLIL::Cell
* RTLIL::Module::addDlatch(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_en
, const RTLIL::SigSpec
&sig_d
, const RTLIL::SigSpec
&sig_q
, bool en_polarity
, const std::string
&src
)
2274 RTLIL::Cell
*cell
= addCell(name
, ID($dlatch
));
2275 cell
->parameters
[ID::EN_POLARITY
] = en_polarity
;
2276 cell
->parameters
[ID::WIDTH
] = sig_q
.size();
2277 cell
->setPort(ID::EN
, sig_en
);
2278 cell
->setPort(ID::D
, sig_d
);
2279 cell
->setPort(ID::Q
, sig_q
);
2280 cell
->set_src_attribute(src
);
2284 RTLIL::Cell
* RTLIL::Module::addDlatchsr(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_en
, const RTLIL::SigSpec
&sig_set
, const RTLIL::SigSpec
&sig_clr
,
2285 RTLIL::SigSpec sig_d
, const RTLIL::SigSpec
&sig_q
, bool en_polarity
, bool set_polarity
, bool clr_polarity
, const std::string
&src
)
2287 RTLIL::Cell
*cell
= addCell(name
, ID($dlatchsr
));
2288 cell
->parameters
[ID::EN_POLARITY
] = en_polarity
;
2289 cell
->parameters
[ID::SET_POLARITY
] = set_polarity
;
2290 cell
->parameters
[ID::CLR_POLARITY
] = clr_polarity
;
2291 cell
->parameters
[ID::WIDTH
] = sig_q
.size();
2292 cell
->setPort(ID::EN
, sig_en
);
2293 cell
->setPort(ID::SET
, sig_set
);
2294 cell
->setPort(ID::CLR
, sig_clr
);
2295 cell
->setPort(ID::D
, sig_d
);
2296 cell
->setPort(ID::Q
, sig_q
);
2297 cell
->set_src_attribute(src
);
2301 RTLIL::Cell
* RTLIL::Module::addFfGate(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_d
, const RTLIL::SigSpec
&sig_q
, const std::string
&src
)
2303 RTLIL::Cell
*cell
= addCell(name
, ID($_FF_
));
2304 cell
->setPort(ID::D
, sig_d
);
2305 cell
->setPort(ID::Q
, sig_q
);
2306 cell
->set_src_attribute(src
);
2310 RTLIL::Cell
* RTLIL::Module::addDffGate(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_clk
, const RTLIL::SigSpec
&sig_d
, const RTLIL::SigSpec
&sig_q
, bool clk_polarity
, const std::string
&src
)
2312 RTLIL::Cell
*cell
= addCell(name
, stringf("$_DFF_%c_", clk_polarity
? 'P' : 'N'));
2313 cell
->setPort(ID::C
, sig_clk
);
2314 cell
->setPort(ID::D
, sig_d
);
2315 cell
->setPort(ID::Q
, sig_q
);
2316 cell
->set_src_attribute(src
);
2320 RTLIL::Cell
* RTLIL::Module::addDffeGate(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_clk
, const RTLIL::SigSpec
&sig_en
, const RTLIL::SigSpec
&sig_d
, const RTLIL::SigSpec
&sig_q
, bool clk_polarity
, bool en_polarity
, const std::string
&src
)
2322 RTLIL::Cell
*cell
= addCell(name
, stringf("$_DFFE_%c%c_", clk_polarity
? 'P' : 'N', en_polarity
? 'P' : 'N'));
2323 cell
->setPort(ID::C
, sig_clk
);
2324 cell
->setPort(ID::E
, sig_en
);
2325 cell
->setPort(ID::D
, sig_d
);
2326 cell
->setPort(ID::Q
, sig_q
);
2327 cell
->set_src_attribute(src
);
2331 RTLIL::Cell
* RTLIL::Module::addDffsrGate(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_clk
, const RTLIL::SigSpec
&sig_set
, const RTLIL::SigSpec
&sig_clr
,
2332 RTLIL::SigSpec sig_d
, const RTLIL::SigSpec
&sig_q
, bool clk_polarity
, bool set_polarity
, bool clr_polarity
, const std::string
&src
)
2334 RTLIL::Cell
*cell
= addCell(name
, stringf("$_DFFSR_%c%c%c_", clk_polarity
? 'P' : 'N', set_polarity
? 'P' : 'N', clr_polarity
? 'P' : 'N'));
2335 cell
->setPort(ID::C
, sig_clk
);
2336 cell
->setPort(ID::S
, sig_set
);
2337 cell
->setPort(ID::R
, sig_clr
);
2338 cell
->setPort(ID::D
, sig_d
);
2339 cell
->setPort(ID::Q
, sig_q
);
2340 cell
->set_src_attribute(src
);
2344 RTLIL::Cell
* RTLIL::Module::addAdffGate(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_clk
, const RTLIL::SigSpec
&sig_arst
, const RTLIL::SigSpec
&sig_d
, const RTLIL::SigSpec
&sig_q
,
2345 bool arst_value
, bool clk_polarity
, bool arst_polarity
, const std::string
&src
)
2347 RTLIL::Cell
*cell
= addCell(name
, stringf("$_DFF_%c%c%c_", clk_polarity
? 'P' : 'N', arst_polarity
? 'P' : 'N', arst_value
? '1' : '0'));
2348 cell
->setPort(ID::C
, sig_clk
);
2349 cell
->setPort(ID::R
, sig_arst
);
2350 cell
->setPort(ID::D
, sig_d
);
2351 cell
->setPort(ID::Q
, sig_q
);
2352 cell
->set_src_attribute(src
);
2356 RTLIL::Cell
* RTLIL::Module::addDlatchGate(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_en
, const RTLIL::SigSpec
&sig_d
, const RTLIL::SigSpec
&sig_q
, bool en_polarity
, const std::string
&src
)
2358 RTLIL::Cell
*cell
= addCell(name
, stringf("$_DLATCH_%c_", en_polarity
? 'P' : 'N'));
2359 cell
->setPort(ID::E
, sig_en
);
2360 cell
->setPort(ID::D
, sig_d
);
2361 cell
->setPort(ID::Q
, sig_q
);
2362 cell
->set_src_attribute(src
);
2366 RTLIL::Cell
* RTLIL::Module::addDlatchsrGate(RTLIL::IdString name
, const RTLIL::SigSpec
&sig_en
, const RTLIL::SigSpec
&sig_set
, const RTLIL::SigSpec
&sig_clr
,
2367 RTLIL::SigSpec sig_d
, const RTLIL::SigSpec
&sig_q
, bool en_polarity
, bool set_polarity
, bool clr_polarity
, const std::string
&src
)
2369 RTLIL::Cell
*cell
= addCell(name
, stringf("$_DLATCHSR_%c%c%c_", en_polarity
? 'P' : 'N', set_polarity
? 'P' : 'N', clr_polarity
? 'P' : 'N'));
2370 cell
->setPort(ID::E
, sig_en
);
2371 cell
->setPort(ID::S
, sig_set
);
2372 cell
->setPort(ID::R
, sig_clr
);
2373 cell
->setPort(ID::D
, sig_d
);
2374 cell
->setPort(ID::Q
, sig_q
);
2375 cell
->set_src_attribute(src
);
2379 RTLIL::SigSpec
RTLIL::Module::Anyconst(RTLIL::IdString name
, int width
, const std::string
&src
)
2381 RTLIL::SigSpec sig
= addWire(NEW_ID
, width
);
2382 Cell
*cell
= addCell(name
, ID($anyconst
));
2383 cell
->setParam(ID::WIDTH
, width
);
2384 cell
->setPort(ID::Y
, sig
);
2385 cell
->set_src_attribute(src
);
2389 RTLIL::SigSpec
RTLIL::Module::Anyseq(RTLIL::IdString name
, int width
, const std::string
&src
)
2391 RTLIL::SigSpec sig
= addWire(NEW_ID
, width
);
2392 Cell
*cell
= addCell(name
, ID($anyseq
));
2393 cell
->setParam(ID::WIDTH
, width
);
2394 cell
->setPort(ID::Y
, sig
);
2395 cell
->set_src_attribute(src
);
2399 RTLIL::SigSpec
RTLIL::Module::Allconst(RTLIL::IdString name
, int width
, const std::string
&src
)
2401 RTLIL::SigSpec sig
= addWire(NEW_ID
, width
);
2402 Cell
*cell
= addCell(name
, ID($allconst
));
2403 cell
->setParam(ID::WIDTH
, width
);
2404 cell
->setPort(ID::Y
, sig
);
2405 cell
->set_src_attribute(src
);
2409 RTLIL::SigSpec
RTLIL::Module::Allseq(RTLIL::IdString name
, int width
, const std::string
&src
)
2411 RTLIL::SigSpec sig
= addWire(NEW_ID
, width
);
2412 Cell
*cell
= addCell(name
, ID($allseq
));
2413 cell
->setParam(ID::WIDTH
, width
);
2414 cell
->setPort(ID::Y
, sig
);
2415 cell
->set_src_attribute(src
);
2419 RTLIL::SigSpec
RTLIL::Module::Initstate(RTLIL::IdString name
, const std::string
&src
)
2421 RTLIL::SigSpec sig
= addWire(NEW_ID
);
2422 Cell
*cell
= addCell(name
, ID($initstate
));
2423 cell
->setPort(ID::Y
, sig
);
2424 cell
->set_src_attribute(src
);
2430 static unsigned int hashidx_count
= 123456789;
2431 hashidx_count
= mkhash_xorshift(hashidx_count
);
2432 hashidx_
= hashidx_count
;
2439 port_output
= false;
2443 RTLIL::Wire::get_all_wires()->insert(std::pair
<unsigned int, RTLIL::Wire
*>(hashidx_
, this));
2447 RTLIL::Wire::~Wire()
2450 RTLIL::Wire::get_all_wires()->erase(hashidx_
);
2455 static std::map
<unsigned int, RTLIL::Wire
*> all_wires
;
2456 std::map
<unsigned int, RTLIL::Wire
*> *RTLIL::Wire::get_all_wires(void)
2462 RTLIL::Memory::Memory()
2464 static unsigned int hashidx_count
= 123456789;
2465 hashidx_count
= mkhash_xorshift(hashidx_count
);
2466 hashidx_
= hashidx_count
;
2472 RTLIL::Memory::get_all_memorys()->insert(std::pair
<unsigned int, RTLIL::Memory
*>(hashidx_
, this));
2476 RTLIL::Cell::Cell() : module(nullptr)
2478 static unsigned int hashidx_count
= 123456789;
2479 hashidx_count
= mkhash_xorshift(hashidx_count
);
2480 hashidx_
= hashidx_count
;
2482 // log("#memtrace# %p\n", this);
2486 RTLIL::Cell::get_all_cells()->insert(std::pair
<unsigned int, RTLIL::Cell
*>(hashidx_
, this));
2490 RTLIL::Cell::~Cell()
2493 RTLIL::Cell::get_all_cells()->erase(hashidx_
);
2498 static std::map
<unsigned int, RTLIL::Cell
*> all_cells
;
2499 std::map
<unsigned int, RTLIL::Cell
*> *RTLIL::Cell::get_all_cells(void)
2505 bool RTLIL::Cell::hasPort(RTLIL::IdString portname
) const
2507 return connections_
.count(portname
) != 0;
2510 void RTLIL::Cell::unsetPort(RTLIL::IdString portname
)
2512 RTLIL::SigSpec signal
;
2513 auto conn_it
= connections_
.find(portname
);
2515 if (conn_it
!= connections_
.end())
2517 for (auto mon
: module
->monitors
)
2518 mon
->notify_connect(this, conn_it
->first
, conn_it
->second
, signal
);
2521 for (auto mon
: module
->design
->monitors
)
2522 mon
->notify_connect(this, conn_it
->first
, conn_it
->second
, signal
);
2525 log("#X# Unconnect %s.%s.%s\n", log_id(this->module
), log_id(this), log_id(portname
));
2526 log_backtrace("-X- ", yosys_xtrace
-1);
2529 connections_
.erase(conn_it
);
2533 void RTLIL::Cell::setPort(RTLIL::IdString portname
, RTLIL::SigSpec signal
)
2535 auto r
= connections_
.insert(portname
);
2536 auto conn_it
= r
.first
;
2537 if (!r
.second
&& conn_it
->second
== signal
)
2540 for (auto mon
: module
->monitors
)
2541 mon
->notify_connect(this, conn_it
->first
, conn_it
->second
, signal
);
2544 for (auto mon
: module
->design
->monitors
)
2545 mon
->notify_connect(this, conn_it
->first
, conn_it
->second
, signal
);
2548 log("#X# Connect %s.%s.%s = %s (%d)\n", log_id(this->module
), log_id(this), log_id(portname
), log_signal(signal
), GetSize(signal
));
2549 log_backtrace("-X- ", yosys_xtrace
-1);
2552 conn_it
->second
= std::move(signal
);
2555 const RTLIL::SigSpec
&RTLIL::Cell::getPort(RTLIL::IdString portname
) const
2557 return connections_
.at(portname
);
2560 const dict
<RTLIL::IdString
, RTLIL::SigSpec
> &RTLIL::Cell::connections() const
2562 return connections_
;
2565 bool RTLIL::Cell::known() const
2567 if (yosys_celltypes
.cell_known(type
))
2569 if (module
&& module
->design
&& module
->design
->module(type
))
2574 bool RTLIL::Cell::input(RTLIL::IdString portname
) const
2576 if (yosys_celltypes
.cell_known(type
))
2577 return yosys_celltypes
.cell_input(type
, portname
);
2578 if (module
&& module
->design
) {
2579 RTLIL::Module
*m
= module
->design
->module(type
);
2580 RTLIL::Wire
*w
= m
? m
->wire(portname
) : nullptr;
2581 return w
&& w
->port_input
;
2586 bool RTLIL::Cell::output(RTLIL::IdString portname
) const
2588 if (yosys_celltypes
.cell_known(type
))
2589 return yosys_celltypes
.cell_output(type
, portname
);
2590 if (module
&& module
->design
) {
2591 RTLIL::Module
*m
= module
->design
->module(type
);
2592 RTLIL::Wire
*w
= m
? m
->wire(portname
) : nullptr;
2593 return w
&& w
->port_output
;
2598 bool RTLIL::Cell::hasParam(RTLIL::IdString paramname
) const
2600 return parameters
.count(paramname
) != 0;
2603 void RTLIL::Cell::unsetParam(RTLIL::IdString paramname
)
2605 parameters
.erase(paramname
);
2608 void RTLIL::Cell::setParam(RTLIL::IdString paramname
, RTLIL::Const value
)
2610 parameters
[paramname
] = std::move(value
);
2613 const RTLIL::Const
&RTLIL::Cell::getParam(RTLIL::IdString paramname
) const
2615 return parameters
.at(paramname
);
2618 void RTLIL::Cell::sort()
2620 connections_
.sort(sort_by_id_str());
2621 parameters
.sort(sort_by_id_str());
2622 attributes
.sort(sort_by_id_str());
2625 void RTLIL::Cell::check()
2628 InternalCellChecker
checker(NULL
, this);
2633 void RTLIL::Cell::fixup_parameters(bool set_a_signed
, bool set_b_signed
)
2635 if (!type
.begins_with("$") || type
.begins_with("$_") || type
.begins_with("$paramod") || type
.begins_with("$fmcombine") ||
2636 type
.begins_with("$verific$") || type
.begins_with("$array:") || type
.begins_with("$extern:"))
2639 if (type
== ID($mux
) || type
== ID($pmux
)) {
2640 parameters
[ID::WIDTH
] = GetSize(connections_
[ID::Y
]);
2641 if (type
== ID($pmux
))
2642 parameters
[ID::S_WIDTH
] = GetSize(connections_
[ID::S
]);
2647 if (type
== ID($lut
) || type
== ID($sop
)) {
2648 parameters
[ID::WIDTH
] = GetSize(connections_
[ID::A
]);
2652 if (type
== ID($fa
)) {
2653 parameters
[ID::WIDTH
] = GetSize(connections_
[ID::Y
]);
2657 if (type
== ID($lcu
)) {
2658 parameters
[ID::WIDTH
] = GetSize(connections_
[ID::CO
]);
2662 bool signedness_ab
= !type
.in(ID($slice
), ID($concat
), ID($macc
));
2664 if (connections_
.count(ID::A
)) {
2665 if (signedness_ab
) {
2667 parameters
[ID::A_SIGNED
] = true;
2668 else if (parameters
.count(ID::A_SIGNED
) == 0)
2669 parameters
[ID::A_SIGNED
] = false;
2671 parameters
[ID::A_WIDTH
] = GetSize(connections_
[ID::A
]);
2674 if (connections_
.count(ID::B
)) {
2675 if (signedness_ab
) {
2677 parameters
[ID::B_SIGNED
] = true;
2678 else if (parameters
.count(ID::B_SIGNED
) == 0)
2679 parameters
[ID::B_SIGNED
] = false;
2681 parameters
[ID::B_WIDTH
] = GetSize(connections_
[ID::B
]);
2684 if (connections_
.count(ID::Y
))
2685 parameters
[ID::Y_WIDTH
] = GetSize(connections_
[ID::Y
]);
2687 if (connections_
.count(ID::Q
))
2688 parameters
[ID::WIDTH
] = GetSize(connections_
[ID::Q
]);
2693 RTLIL::SigChunk::SigChunk()
2700 RTLIL::SigChunk::SigChunk(const RTLIL::Const
&value
)
2704 width
= GetSize(data
);
2708 RTLIL::SigChunk::SigChunk(RTLIL::Wire
*wire
)
2710 log_assert(wire
!= nullptr);
2712 this->width
= wire
->width
;
2716 RTLIL::SigChunk::SigChunk(RTLIL::Wire
*wire
, int offset
, int width
)
2718 log_assert(wire
!= nullptr);
2720 this->width
= width
;
2721 this->offset
= offset
;
2724 RTLIL::SigChunk::SigChunk(const std::string
&str
)
2727 data
= RTLIL::Const(str
).bits
;
2728 width
= GetSize(data
);
2732 RTLIL::SigChunk::SigChunk(int val
, int width
)
2735 data
= RTLIL::Const(val
, width
).bits
;
2736 this->width
= GetSize(data
);
2740 RTLIL::SigChunk::SigChunk(RTLIL::State bit
, int width
)
2743 data
= RTLIL::Const(bit
, width
).bits
;
2744 this->width
= GetSize(data
);
2748 RTLIL::SigChunk::SigChunk(const RTLIL::SigBit
&bit
)
2753 data
= RTLIL::Const(bit
.data
).bits
;
2755 offset
= bit
.offset
;
2759 RTLIL::SigChunk::SigChunk(const RTLIL::SigChunk
&sigchunk
)
2764 RTLIL::SigChunk
RTLIL::SigChunk::extract(int offset
, int length
) const
2766 RTLIL::SigChunk ret
;
2769 ret
.offset
= this->offset
+ offset
;
2772 for (int i
= 0; i
< length
; i
++)
2773 ret
.data
.push_back(data
[offset
+i
]);
2779 bool RTLIL::SigChunk::operator <(const RTLIL::SigChunk
&other
) const
2781 if (wire
&& other
.wire
)
2782 if (wire
->name
!= other
.wire
->name
)
2783 return wire
->name
< other
.wire
->name
;
2785 if (wire
!= other
.wire
)
2786 return wire
< other
.wire
;
2788 if (offset
!= other
.offset
)
2789 return offset
< other
.offset
;
2791 if (width
!= other
.width
)
2792 return width
< other
.width
;
2794 return data
< other
.data
;
2797 bool RTLIL::SigChunk::operator ==(const RTLIL::SigChunk
&other
) const
2799 return wire
== other
.wire
&& width
== other
.width
&& offset
== other
.offset
&& data
== other
.data
;
2802 bool RTLIL::SigChunk::operator !=(const RTLIL::SigChunk
&other
) const
2809 RTLIL::SigSpec::SigSpec()
2815 RTLIL::SigSpec::SigSpec(const RTLIL::SigSpec
&other
)
2820 RTLIL::SigSpec::SigSpec(std::initializer_list
<RTLIL::SigSpec
> parts
)
2822 cover("kernel.rtlil.sigspec.init.list");
2827 log_assert(parts
.size() > 0);
2828 auto ie
= parts
.begin();
2829 auto it
= ie
+ parts
.size() - 1;
2834 RTLIL::SigSpec
&RTLIL::SigSpec::operator=(const RTLIL::SigSpec
&other
)
2836 cover("kernel.rtlil.sigspec.assign");
2838 width_
= other
.width_
;
2839 hash_
= other
.hash_
;
2840 chunks_
= other
.chunks_
;
2841 bits_
= other
.bits_
;
2845 RTLIL::SigSpec::SigSpec(const RTLIL::Const
&value
)
2847 cover("kernel.rtlil.sigspec.init.const");
2849 chunks_
.emplace_back(value
);
2850 width_
= chunks_
.back().width
;
2855 RTLIL::SigSpec::SigSpec(const RTLIL::SigChunk
&chunk
)
2857 cover("kernel.rtlil.sigspec.init.chunk");
2859 chunks_
.emplace_back(chunk
);
2860 width_
= chunks_
.back().width
;
2865 RTLIL::SigSpec::SigSpec(RTLIL::Wire
*wire
)
2867 cover("kernel.rtlil.sigspec.init.wire");
2869 chunks_
.emplace_back(wire
);
2870 width_
= chunks_
.back().width
;
2875 RTLIL::SigSpec::SigSpec(RTLIL::Wire
*wire
, int offset
, int width
)
2877 cover("kernel.rtlil.sigspec.init.wire_part");
2879 chunks_
.emplace_back(wire
, offset
, width
);
2880 width_
= chunks_
.back().width
;
2885 RTLIL::SigSpec::SigSpec(const std::string
&str
)
2887 cover("kernel.rtlil.sigspec.init.str");
2889 chunks_
.emplace_back(str
);
2890 width_
= chunks_
.back().width
;
2895 RTLIL::SigSpec::SigSpec(int val
, int width
)
2897 cover("kernel.rtlil.sigspec.init.int");
2899 chunks_
.emplace_back(val
, width
);
2905 RTLIL::SigSpec::SigSpec(RTLIL::State bit
, int width
)
2907 cover("kernel.rtlil.sigspec.init.state");
2909 chunks_
.emplace_back(bit
, width
);
2915 RTLIL::SigSpec::SigSpec(const RTLIL::SigBit
&bit
, int width
)
2917 cover("kernel.rtlil.sigspec.init.bit");
2919 if (bit
.wire
== NULL
)
2920 chunks_
.emplace_back(bit
.data
, width
);
2922 for (int i
= 0; i
< width
; i
++)
2923 chunks_
.push_back(bit
);
2929 RTLIL::SigSpec::SigSpec(const std::vector
<RTLIL::SigChunk
> &chunks
)
2931 cover("kernel.rtlil.sigspec.init.stdvec_chunks");
2935 for (const auto &c
: chunks
)
2940 RTLIL::SigSpec::SigSpec(const std::vector
<RTLIL::SigBit
> &bits
)
2942 cover("kernel.rtlil.sigspec.init.stdvec_bits");
2946 for (const auto &bit
: bits
)
2951 RTLIL::SigSpec::SigSpec(const pool
<RTLIL::SigBit
> &bits
)
2953 cover("kernel.rtlil.sigspec.init.pool_bits");
2957 for (const auto &bit
: bits
)
2962 RTLIL::SigSpec::SigSpec(const std::set
<RTLIL::SigBit
> &bits
)
2964 cover("kernel.rtlil.sigspec.init.stdset_bits");
2968 for (const auto &bit
: bits
)
2973 RTLIL::SigSpec::SigSpec(bool bit
)
2975 cover("kernel.rtlil.sigspec.init.bool");
2979 append(SigBit(bit
));
2983 void RTLIL::SigSpec::pack() const
2985 RTLIL::SigSpec
*that
= (RTLIL::SigSpec
*)this;
2987 if (that
->bits_
.empty())
2990 cover("kernel.rtlil.sigspec.convert.pack");
2991 log_assert(that
->chunks_
.empty());
2993 std::vector
<RTLIL::SigBit
> old_bits
;
2994 old_bits
.swap(that
->bits_
);
2996 RTLIL::SigChunk
*last
= NULL
;
2997 int last_end_offset
= 0;
2999 for (auto &bit
: old_bits
) {
3000 if (last
&& bit
.wire
== last
->wire
) {
3001 if (bit
.wire
== NULL
) {
3002 last
->data
.push_back(bit
.data
);
3005 } else if (last_end_offset
== bit
.offset
) {
3011 that
->chunks_
.push_back(bit
);
3012 last
= &that
->chunks_
.back();
3013 last_end_offset
= bit
.offset
+ 1;
3019 void RTLIL::SigSpec::unpack() const
3021 RTLIL::SigSpec
*that
= (RTLIL::SigSpec
*)this;
3023 if (that
->chunks_
.empty())
3026 cover("kernel.rtlil.sigspec.convert.unpack");
3027 log_assert(that
->bits_
.empty());
3029 that
->bits_
.reserve(that
->width_
);
3030 for (auto &c
: that
->chunks_
)
3031 for (int i
= 0; i
< c
.width
; i
++)
3032 that
->bits_
.emplace_back(c
, i
);
3034 that
->chunks_
.clear();
3038 void RTLIL::SigSpec::updhash() const
3040 RTLIL::SigSpec
*that
= (RTLIL::SigSpec
*)this;
3042 if (that
->hash_
!= 0)
3045 cover("kernel.rtlil.sigspec.hash");
3048 that
->hash_
= mkhash_init
;
3049 for (auto &c
: that
->chunks_
)
3050 if (c
.wire
== NULL
) {
3051 for (auto &v
: c
.data
)
3052 that
->hash_
= mkhash(that
->hash_
, v
);
3054 that
->hash_
= mkhash(that
->hash_
, c
.wire
->name
.index_
);
3055 that
->hash_
= mkhash(that
->hash_
, c
.offset
);
3056 that
->hash_
= mkhash(that
->hash_
, c
.width
);
3059 if (that
->hash_
== 0)
3063 void RTLIL::SigSpec::sort()
3066 cover("kernel.rtlil.sigspec.sort");
3067 std::sort(bits_
.begin(), bits_
.end());
3070 void RTLIL::SigSpec::sort_and_unify()
3073 cover("kernel.rtlil.sigspec.sort_and_unify");
3075 // A copy of the bits vector is used to prevent duplicating the logic from
3076 // SigSpec::SigSpec(std::vector<SigBit>). This incurrs an extra copy but
3077 // that isn't showing up as significant in profiles.
3078 std::vector
<SigBit
> unique_bits
= bits_
;
3079 std::sort(unique_bits
.begin(), unique_bits
.end());
3080 auto last
= std::unique(unique_bits
.begin(), unique_bits
.end());
3081 unique_bits
.erase(last
, unique_bits
.end());
3083 *this = unique_bits
;
3086 void RTLIL::SigSpec::replace(const RTLIL::SigSpec
&pattern
, const RTLIL::SigSpec
&with
)
3088 replace(pattern
, with
, this);
3091 void RTLIL::SigSpec::replace(const RTLIL::SigSpec
&pattern
, const RTLIL::SigSpec
&with
, RTLIL::SigSpec
*other
) const
3093 log_assert(other
!= NULL
);
3094 log_assert(width_
== other
->width_
);
3095 log_assert(pattern
.width_
== with
.width_
);
3102 for (int i
= 0; i
< GetSize(pattern
.bits_
); i
++) {
3103 if (pattern
.bits_
[i
].wire
!= NULL
) {
3104 for (int j
= 0; j
< GetSize(bits_
); j
++) {
3105 if (bits_
[j
] == pattern
.bits_
[i
]) {
3106 other
->bits_
[j
] = with
.bits_
[i
];
3115 void RTLIL::SigSpec::replace(const dict
<RTLIL::SigBit
, RTLIL::SigBit
> &rules
)
3117 replace(rules
, this);
3120 void RTLIL::SigSpec::replace(const dict
<RTLIL::SigBit
, RTLIL::SigBit
> &rules
, RTLIL::SigSpec
*other
) const
3122 cover("kernel.rtlil.sigspec.replace_dict");
3124 log_assert(other
!= NULL
);
3125 log_assert(width_
== other
->width_
);
3127 if (rules
.empty()) return;
3131 for (int i
= 0; i
< GetSize(bits_
); i
++) {
3132 auto it
= rules
.find(bits_
[i
]);
3133 if (it
!= rules
.end())
3134 other
->bits_
[i
] = it
->second
;
3140 void RTLIL::SigSpec::replace(const std::map
<RTLIL::SigBit
, RTLIL::SigBit
> &rules
)
3142 replace(rules
, this);
3145 void RTLIL::SigSpec::replace(const std::map
<RTLIL::SigBit
, RTLIL::SigBit
> &rules
, RTLIL::SigSpec
*other
) const
3147 cover("kernel.rtlil.sigspec.replace_map");
3149 log_assert(other
!= NULL
);
3150 log_assert(width_
== other
->width_
);
3152 if (rules
.empty()) return;
3156 for (int i
= 0; i
< GetSize(bits_
); i
++) {
3157 auto it
= rules
.find(bits_
[i
]);
3158 if (it
!= rules
.end())
3159 other
->bits_
[i
] = it
->second
;
3165 void RTLIL::SigSpec::remove(const RTLIL::SigSpec
&pattern
)
3167 remove2(pattern
, NULL
);
3170 void RTLIL::SigSpec::remove(const RTLIL::SigSpec
&pattern
, RTLIL::SigSpec
*other
) const
3172 RTLIL::SigSpec tmp
= *this;
3173 tmp
.remove2(pattern
, other
);
3176 void RTLIL::SigSpec::remove2(const RTLIL::SigSpec
&pattern
, RTLIL::SigSpec
*other
)
3179 cover("kernel.rtlil.sigspec.remove_other");
3181 cover("kernel.rtlil.sigspec.remove");
3184 if (other
!= NULL
) {
3185 log_assert(width_
== other
->width_
);
3189 for (int i
= GetSize(bits_
) - 1; i
>= 0; i
--)
3191 if (bits_
[i
].wire
== NULL
) continue;
3193 for (auto &pattern_chunk
: pattern
.chunks())
3194 if (bits_
[i
].wire
== pattern_chunk
.wire
&&
3195 bits_
[i
].offset
>= pattern_chunk
.offset
&&
3196 bits_
[i
].offset
< pattern_chunk
.offset
+ pattern_chunk
.width
) {
3197 bits_
.erase(bits_
.begin() + i
);
3199 if (other
!= NULL
) {
3200 other
->bits_
.erase(other
->bits_
.begin() + i
);
3210 void RTLIL::SigSpec::remove(const pool
<RTLIL::SigBit
> &pattern
)
3212 remove2(pattern
, NULL
);
3215 void RTLIL::SigSpec::remove(const pool
<RTLIL::SigBit
> &pattern
, RTLIL::SigSpec
*other
) const
3217 RTLIL::SigSpec tmp
= *this;
3218 tmp
.remove2(pattern
, other
);
3221 void RTLIL::SigSpec::remove2(const pool
<RTLIL::SigBit
> &pattern
, RTLIL::SigSpec
*other
)
3224 cover("kernel.rtlil.sigspec.remove_other");
3226 cover("kernel.rtlil.sigspec.remove");
3230 if (other
!= NULL
) {
3231 log_assert(width_
== other
->width_
);
3235 for (int i
= GetSize(bits_
) - 1; i
>= 0; i
--) {
3236 if (bits_
[i
].wire
!= NULL
&& pattern
.count(bits_
[i
])) {
3237 bits_
.erase(bits_
.begin() + i
);
3239 if (other
!= NULL
) {
3240 other
->bits_
.erase(other
->bits_
.begin() + i
);
3249 void RTLIL::SigSpec::remove2(const std::set
<RTLIL::SigBit
> &pattern
, RTLIL::SigSpec
*other
)
3252 cover("kernel.rtlil.sigspec.remove_other");
3254 cover("kernel.rtlil.sigspec.remove");
3258 if (other
!= NULL
) {
3259 log_assert(width_
== other
->width_
);
3263 for (int i
= GetSize(bits_
) - 1; i
>= 0; i
--) {
3264 if (bits_
[i
].wire
!= NULL
&& pattern
.count(bits_
[i
])) {
3265 bits_
.erase(bits_
.begin() + i
);
3267 if (other
!= NULL
) {
3268 other
->bits_
.erase(other
->bits_
.begin() + i
);
3277 RTLIL::SigSpec
RTLIL::SigSpec::extract(const RTLIL::SigSpec
&pattern
, const RTLIL::SigSpec
*other
) const
3280 cover("kernel.rtlil.sigspec.extract_other");
3282 cover("kernel.rtlil.sigspec.extract");
3284 log_assert(other
== NULL
|| width_
== other
->width_
);
3287 std::vector
<RTLIL::SigBit
> bits_match
= to_sigbit_vector();
3289 for (auto& pattern_chunk
: pattern
.chunks()) {
3291 std::vector
<RTLIL::SigBit
> bits_other
= other
->to_sigbit_vector();
3292 for (int i
= 0; i
< width_
; i
++)
3293 if (bits_match
[i
].wire
&&
3294 bits_match
[i
].wire
== pattern_chunk
.wire
&&
3295 bits_match
[i
].offset
>= pattern_chunk
.offset
&&
3296 bits_match
[i
].offset
< pattern_chunk
.offset
+ pattern_chunk
.width
)
3297 ret
.append(bits_other
[i
]);
3299 for (int i
= 0; i
< width_
; i
++)
3300 if (bits_match
[i
].wire
&&
3301 bits_match
[i
].wire
== pattern_chunk
.wire
&&
3302 bits_match
[i
].offset
>= pattern_chunk
.offset
&&
3303 bits_match
[i
].offset
< pattern_chunk
.offset
+ pattern_chunk
.width
)
3304 ret
.append(bits_match
[i
]);
3312 RTLIL::SigSpec
RTLIL::SigSpec::extract(const pool
<RTLIL::SigBit
> &pattern
, const RTLIL::SigSpec
*other
) const
3315 cover("kernel.rtlil.sigspec.extract_other");
3317 cover("kernel.rtlil.sigspec.extract");
3319 log_assert(other
== NULL
|| width_
== other
->width_
);
3321 std::vector
<RTLIL::SigBit
> bits_match
= to_sigbit_vector();
3325 std::vector
<RTLIL::SigBit
> bits_other
= other
->to_sigbit_vector();
3326 for (int i
= 0; i
< width_
; i
++)
3327 if (bits_match
[i
].wire
&& pattern
.count(bits_match
[i
]))
3328 ret
.append(bits_other
[i
]);
3330 for (int i
= 0; i
< width_
; i
++)
3331 if (bits_match
[i
].wire
&& pattern
.count(bits_match
[i
]))
3332 ret
.append(bits_match
[i
]);
3339 void RTLIL::SigSpec::replace(int offset
, const RTLIL::SigSpec
&with
)
3341 cover("kernel.rtlil.sigspec.replace_pos");
3346 log_assert(offset
>= 0);
3347 log_assert(with
.width_
>= 0);
3348 log_assert(offset
+with
.width_
<= width_
);
3350 for (int i
= 0; i
< with
.width_
; i
++)
3351 bits_
.at(offset
+ i
) = with
.bits_
.at(i
);
3356 void RTLIL::SigSpec::remove_const()
3360 cover("kernel.rtlil.sigspec.remove_const.packed");
3362 std::vector
<RTLIL::SigChunk
> new_chunks
;
3363 new_chunks
.reserve(GetSize(chunks_
));
3366 for (auto &chunk
: chunks_
)
3367 if (chunk
.wire
!= NULL
) {
3368 new_chunks
.push_back(chunk
);
3369 width_
+= chunk
.width
;
3372 chunks_
.swap(new_chunks
);
3376 cover("kernel.rtlil.sigspec.remove_const.unpacked");
3378 std::vector
<RTLIL::SigBit
> new_bits
;
3379 new_bits
.reserve(width_
);
3381 for (auto &bit
: bits_
)
3382 if (bit
.wire
!= NULL
)
3383 new_bits
.push_back(bit
);
3385 bits_
.swap(new_bits
);
3386 width_
= bits_
.size();
3392 void RTLIL::SigSpec::remove(int offset
, int length
)
3394 cover("kernel.rtlil.sigspec.remove_pos");
3398 log_assert(offset
>= 0);
3399 log_assert(length
>= 0);
3400 log_assert(offset
+ length
<= width_
);
3402 bits_
.erase(bits_
.begin() + offset
, bits_
.begin() + offset
+ length
);
3403 width_
= bits_
.size();
3408 RTLIL::SigSpec
RTLIL::SigSpec::extract(int offset
, int length
) const
3411 cover("kernel.rtlil.sigspec.extract_pos");
3412 return std::vector
<RTLIL::SigBit
>(bits_
.begin() + offset
, bits_
.begin() + offset
+ length
);
3415 void RTLIL::SigSpec::append(const RTLIL::SigSpec
&signal
)
3417 if (signal
.width_
== 0)
3425 cover("kernel.rtlil.sigspec.append");
3427 if (packed() != signal
.packed()) {
3433 for (auto &other_c
: signal
.chunks_
)
3435 auto &my_last_c
= chunks_
.back();
3436 if (my_last_c
.wire
== NULL
&& other_c
.wire
== NULL
) {
3437 auto &this_data
= my_last_c
.data
;
3438 auto &other_data
= other_c
.data
;
3439 this_data
.insert(this_data
.end(), other_data
.begin(), other_data
.end());
3440 my_last_c
.width
+= other_c
.width
;
3442 if (my_last_c
.wire
== other_c
.wire
&& my_last_c
.offset
+ my_last_c
.width
== other_c
.offset
) {
3443 my_last_c
.width
+= other_c
.width
;
3445 chunks_
.push_back(other_c
);
3448 bits_
.insert(bits_
.end(), signal
.bits_
.begin(), signal
.bits_
.end());
3450 width_
+= signal
.width_
;
3454 void RTLIL::SigSpec::append(const RTLIL::SigBit
&bit
)
3458 cover("kernel.rtlil.sigspec.append_bit.packed");
3460 if (chunks_
.size() == 0)
3461 chunks_
.push_back(bit
);
3463 if (bit
.wire
== NULL
)
3464 if (chunks_
.back().wire
== NULL
) {
3465 chunks_
.back().data
.push_back(bit
.data
);
3466 chunks_
.back().width
++;
3468 chunks_
.push_back(bit
);
3470 if (chunks_
.back().wire
== bit
.wire
&& chunks_
.back().offset
+ chunks_
.back().width
== bit
.offset
)
3471 chunks_
.back().width
++;
3473 chunks_
.push_back(bit
);
3477 cover("kernel.rtlil.sigspec.append_bit.unpacked");
3478 bits_
.push_back(bit
);
3485 void RTLIL::SigSpec::extend_u0(int width
, bool is_signed
)
3487 cover("kernel.rtlil.sigspec.extend_u0");
3492 remove(width
, width_
- width
);
3494 if (width_
< width
) {
3495 RTLIL::SigBit padding
= width_
> 0 ? (*this)[width_
- 1] : RTLIL::State::Sx
;
3497 padding
= RTLIL::State::S0
;
3498 while (width_
< width
)
3504 RTLIL::SigSpec
RTLIL::SigSpec::repeat(int num
) const
3506 cover("kernel.rtlil.sigspec.repeat");
3509 for (int i
= 0; i
< num
; i
++)
3515 void RTLIL::SigSpec::check() const
3519 cover("kernel.rtlil.sigspec.check.skip");
3523 cover("kernel.rtlil.sigspec.check.packed");
3526 for (size_t i
= 0; i
< chunks_
.size(); i
++) {
3527 const RTLIL::SigChunk
&chunk
= chunks_
[i
];
3528 if (chunk
.wire
== NULL
) {
3530 log_assert(chunks_
[i
-1].wire
!= NULL
);
3531 log_assert(chunk
.offset
== 0);
3532 log_assert(chunk
.data
.size() == (size_t)chunk
.width
);
3534 if (i
> 0 && chunks_
[i
-1].wire
== chunk
.wire
)
3535 log_assert(chunk
.offset
!= chunks_
[i
-1].offset
+ chunks_
[i
-1].width
);
3536 log_assert(chunk
.offset
>= 0);
3537 log_assert(chunk
.width
>= 0);
3538 log_assert(chunk
.offset
+ chunk
.width
<= chunk
.wire
->width
);
3539 log_assert(chunk
.data
.size() == 0);
3543 log_assert(w
== width_
);
3544 log_assert(bits_
.empty());
3548 cover("kernel.rtlil.sigspec.check.unpacked");
3550 log_assert(width_
== GetSize(bits_
));
3551 log_assert(chunks_
.empty());
3556 bool RTLIL::SigSpec::operator <(const RTLIL::SigSpec
&other
) const
3558 cover("kernel.rtlil.sigspec.comp_lt");
3563 if (width_
!= other
.width_
)
3564 return width_
< other
.width_
;
3569 if (chunks_
.size() != other
.chunks_
.size())
3570 return chunks_
.size() < other
.chunks_
.size();
3575 if (hash_
!= other
.hash_
)
3576 return hash_
< other
.hash_
;
3578 for (size_t i
= 0; i
< chunks_
.size(); i
++)
3579 if (chunks_
[i
] != other
.chunks_
[i
]) {
3580 cover("kernel.rtlil.sigspec.comp_lt.hash_collision");
3581 return chunks_
[i
] < other
.chunks_
[i
];
3584 cover("kernel.rtlil.sigspec.comp_lt.equal");
3588 bool RTLIL::SigSpec::operator ==(const RTLIL::SigSpec
&other
) const
3590 cover("kernel.rtlil.sigspec.comp_eq");
3595 if (width_
!= other
.width_
)
3598 // Without this, SigSpec() == SigSpec(State::S0, 0) will fail
3599 // since the RHS will contain one SigChunk of width 0 causing
3600 // the size check below to fail
3607 if (chunks_
.size() != other
.chunks_
.size())
3613 if (hash_
!= other
.hash_
)
3616 for (size_t i
= 0; i
< chunks_
.size(); i
++)
3617 if (chunks_
[i
] != other
.chunks_
[i
]) {
3618 cover("kernel.rtlil.sigspec.comp_eq.hash_collision");
3622 cover("kernel.rtlil.sigspec.comp_eq.equal");
3626 bool RTLIL::SigSpec::is_wire() const
3628 cover("kernel.rtlil.sigspec.is_wire");
3631 return GetSize(chunks_
) == 1 && chunks_
[0].wire
&& chunks_
[0].wire
->width
== width_
;
3634 bool RTLIL::SigSpec::is_chunk() const
3636 cover("kernel.rtlil.sigspec.is_chunk");
3639 return GetSize(chunks_
) == 1;
3642 bool RTLIL::SigSpec::is_fully_const() const
3644 cover("kernel.rtlil.sigspec.is_fully_const");
3647 for (auto it
= chunks_
.begin(); it
!= chunks_
.end(); it
++)
3648 if (it
->width
> 0 && it
->wire
!= NULL
)
3653 bool RTLIL::SigSpec::is_fully_zero() const
3655 cover("kernel.rtlil.sigspec.is_fully_zero");
3658 for (auto it
= chunks_
.begin(); it
!= chunks_
.end(); it
++) {
3659 if (it
->width
> 0 && it
->wire
!= NULL
)
3661 for (size_t i
= 0; i
< it
->data
.size(); i
++)
3662 if (it
->data
[i
] != RTLIL::State::S0
)
3668 bool RTLIL::SigSpec::is_fully_ones() const
3670 cover("kernel.rtlil.sigspec.is_fully_ones");
3673 for (auto it
= chunks_
.begin(); it
!= chunks_
.end(); it
++) {
3674 if (it
->width
> 0 && it
->wire
!= NULL
)
3676 for (size_t i
= 0; i
< it
->data
.size(); i
++)
3677 if (it
->data
[i
] != RTLIL::State::S1
)
3683 bool RTLIL::SigSpec::is_fully_def() const
3685 cover("kernel.rtlil.sigspec.is_fully_def");
3688 for (auto it
= chunks_
.begin(); it
!= chunks_
.end(); it
++) {
3689 if (it
->width
> 0 && it
->wire
!= NULL
)
3691 for (size_t i
= 0; i
< it
->data
.size(); i
++)
3692 if (it
->data
[i
] != RTLIL::State::S0
&& it
->data
[i
] != RTLIL::State::S1
)
3698 bool RTLIL::SigSpec::is_fully_undef() const
3700 cover("kernel.rtlil.sigspec.is_fully_undef");
3703 for (auto it
= chunks_
.begin(); it
!= chunks_
.end(); it
++) {
3704 if (it
->width
> 0 && it
->wire
!= NULL
)
3706 for (size_t i
= 0; i
< it
->data
.size(); i
++)
3707 if (it
->data
[i
] != RTLIL::State::Sx
&& it
->data
[i
] != RTLIL::State::Sz
)
3713 bool RTLIL::SigSpec::has_const() const
3715 cover("kernel.rtlil.sigspec.has_const");
3718 for (auto it
= chunks_
.begin(); it
!= chunks_
.end(); it
++)
3719 if (it
->width
> 0 && it
->wire
== NULL
)
3724 bool RTLIL::SigSpec::has_marked_bits() const
3726 cover("kernel.rtlil.sigspec.has_marked_bits");
3729 for (auto it
= chunks_
.begin(); it
!= chunks_
.end(); it
++)
3730 if (it
->width
> 0 && it
->wire
== NULL
) {
3731 for (size_t i
= 0; i
< it
->data
.size(); i
++)
3732 if (it
->data
[i
] == RTLIL::State::Sm
)
3738 bool RTLIL::SigSpec::as_bool() const
3740 cover("kernel.rtlil.sigspec.as_bool");
3743 log_assert(is_fully_const() && GetSize(chunks_
) <= 1);
3745 return RTLIL::Const(chunks_
[0].data
).as_bool();
3749 int RTLIL::SigSpec::as_int(bool is_signed
) const
3751 cover("kernel.rtlil.sigspec.as_int");
3754 log_assert(is_fully_const() && GetSize(chunks_
) <= 1);
3756 return RTLIL::Const(chunks_
[0].data
).as_int(is_signed
);
3760 std::string
RTLIL::SigSpec::as_string() const
3762 cover("kernel.rtlil.sigspec.as_string");
3766 str
.reserve(size());
3767 for (size_t i
= chunks_
.size(); i
> 0; i
--) {
3768 const RTLIL::SigChunk
&chunk
= chunks_
[i
-1];
3769 if (chunk
.wire
!= NULL
)
3770 str
.append(chunk
.width
, '?');
3772 str
+= RTLIL::Const(chunk
.data
).as_string();
3777 RTLIL::Const
RTLIL::SigSpec::as_const() const
3779 cover("kernel.rtlil.sigspec.as_const");
3782 log_assert(is_fully_const() && GetSize(chunks_
) <= 1);
3784 return chunks_
[0].data
;
3785 return RTLIL::Const();
3788 RTLIL::Wire
*RTLIL::SigSpec::as_wire() const
3790 cover("kernel.rtlil.sigspec.as_wire");
3793 log_assert(is_wire());
3794 return chunks_
[0].wire
;
3797 RTLIL::SigChunk
RTLIL::SigSpec::as_chunk() const
3799 cover("kernel.rtlil.sigspec.as_chunk");
3802 log_assert(is_chunk());
3806 RTLIL::SigBit
RTLIL::SigSpec::as_bit() const
3808 cover("kernel.rtlil.sigspec.as_bit");
3810 log_assert(width_
== 1);
3812 return RTLIL::SigBit(*chunks_
.begin());
3817 bool RTLIL::SigSpec::match(const char* pattern
) const
3819 cover("kernel.rtlil.sigspec.match");
3822 log_assert(int(strlen(pattern
)) == GetSize(bits_
));
3824 for (auto it
= bits_
.rbegin(); it
!= bits_
.rend(); it
++, pattern
++) {
3825 if (*pattern
== ' ')
3827 if (*pattern
== '*') {
3828 if (*it
!= State::Sz
&& *it
!= State::Sx
)
3832 if (*pattern
== '0') {
3833 if (*it
!= State::S0
)
3836 if (*pattern
== '1') {
3837 if (*it
!= State::S1
)
3846 std::set
<RTLIL::SigBit
> RTLIL::SigSpec::to_sigbit_set() const
3848 cover("kernel.rtlil.sigspec.to_sigbit_set");
3851 std::set
<RTLIL::SigBit
> sigbits
;
3852 for (auto &c
: chunks_
)
3853 for (int i
= 0; i
< c
.width
; i
++)
3854 sigbits
.insert(RTLIL::SigBit(c
, i
));
3858 pool
<RTLIL::SigBit
> RTLIL::SigSpec::to_sigbit_pool() const
3860 cover("kernel.rtlil.sigspec.to_sigbit_pool");
3863 pool
<RTLIL::SigBit
> sigbits
;
3864 sigbits
.reserve(size());
3865 for (auto &c
: chunks_
)
3866 for (int i
= 0; i
< c
.width
; i
++)
3867 sigbits
.insert(RTLIL::SigBit(c
, i
));
3871 std::vector
<RTLIL::SigBit
> RTLIL::SigSpec::to_sigbit_vector() const
3873 cover("kernel.rtlil.sigspec.to_sigbit_vector");
3879 std::map
<RTLIL::SigBit
, RTLIL::SigBit
> RTLIL::SigSpec::to_sigbit_map(const RTLIL::SigSpec
&other
) const
3881 cover("kernel.rtlil.sigspec.to_sigbit_map");
3886 log_assert(width_
== other
.width_
);
3888 std::map
<RTLIL::SigBit
, RTLIL::SigBit
> new_map
;
3889 for (int i
= 0; i
< width_
; i
++)
3890 new_map
[bits_
[i
]] = other
.bits_
[i
];
3895 dict
<RTLIL::SigBit
, RTLIL::SigBit
> RTLIL::SigSpec::to_sigbit_dict(const RTLIL::SigSpec
&other
) const
3897 cover("kernel.rtlil.sigspec.to_sigbit_dict");
3902 log_assert(width_
== other
.width_
);
3904 dict
<RTLIL::SigBit
, RTLIL::SigBit
> new_map
;
3905 new_map
.reserve(size());
3906 for (int i
= 0; i
< width_
; i
++)
3907 new_map
[bits_
[i
]] = other
.bits_
[i
];
3912 static void sigspec_parse_split(std::vector
<std::string
> &tokens
, const std::string
&text
, char sep
)
3914 size_t start
= 0, end
= 0;
3915 while ((end
= text
.find(sep
, start
)) != std::string::npos
) {
3916 tokens
.push_back(text
.substr(start
, end
- start
));
3919 tokens
.push_back(text
.substr(start
));
3922 static int sigspec_parse_get_dummy_line_num()
3927 bool RTLIL::SigSpec::parse(RTLIL::SigSpec
&sig
, RTLIL::Module
*module
, std::string str
)
3929 cover("kernel.rtlil.sigspec.parse");
3931 AST::current_filename
= "input";
3933 std::vector
<std::string
> tokens
;
3934 sigspec_parse_split(tokens
, str
, ',');
3936 sig
= RTLIL::SigSpec();
3937 for (int tokidx
= int(tokens
.size())-1; tokidx
>= 0; tokidx
--)
3939 std::string netname
= tokens
[tokidx
];
3940 std::string indices
;
3942 if (netname
.size() == 0)
3945 if (('0' <= netname
[0] && netname
[0] <= '9') || netname
[0] == '\'') {
3946 cover("kernel.rtlil.sigspec.parse.const");
3947 AST::get_line_num
= sigspec_parse_get_dummy_line_num
;
3948 AST::AstNode
*ast
= VERILOG_FRONTEND::const2ast(netname
);
3951 sig
.append(RTLIL::Const(ast
->bits
));
3959 cover("kernel.rtlil.sigspec.parse.net");
3961 if (netname
[0] != '$' && netname
[0] != '\\')
3962 netname
= "\\" + netname
;
3964 if (module
->wires_
.count(netname
) == 0) {
3965 size_t indices_pos
= netname
.size()-1;
3966 if (indices_pos
> 2 && netname
[indices_pos
] == ']')
3969 while (indices_pos
> 0 && ('0' <= netname
[indices_pos
] && netname
[indices_pos
] <= '9')) indices_pos
--;
3970 if (indices_pos
> 0 && netname
[indices_pos
] == ':') {
3972 while (indices_pos
> 0 && ('0' <= netname
[indices_pos
] && netname
[indices_pos
] <= '9')) indices_pos
--;
3974 if (indices_pos
> 0 && netname
[indices_pos
] == '[') {
3975 indices
= netname
.substr(indices_pos
);
3976 netname
= netname
.substr(0, indices_pos
);
3981 if (module
->wires_
.count(netname
) == 0)
3984 RTLIL::Wire
*wire
= module
->wires_
.at(netname
);
3985 if (!indices
.empty()) {
3986 std::vector
<std::string
> index_tokens
;
3987 sigspec_parse_split(index_tokens
, indices
.substr(1, indices
.size()-2), ':');
3988 if (index_tokens
.size() == 1) {
3989 cover("kernel.rtlil.sigspec.parse.bit_sel");
3990 int a
= atoi(index_tokens
.at(0).c_str());
3991 if (a
< 0 || a
>= wire
->width
)
3993 sig
.append(RTLIL::SigSpec(wire
, a
));
3995 cover("kernel.rtlil.sigspec.parse.part_sel");
3996 int a
= atoi(index_tokens
.at(0).c_str());
3997 int b
= atoi(index_tokens
.at(1).c_str());
4002 if (a
< 0 || a
>= wire
->width
)
4004 if (b
< 0 || b
>= wire
->width
)
4006 sig
.append(RTLIL::SigSpec(wire
, a
, b
-a
+1));
4015 bool RTLIL::SigSpec::parse_sel(RTLIL::SigSpec
&sig
, RTLIL::Design
*design
, RTLIL::Module
*module
, std::string str
)
4017 if (str
.empty() || str
[0] != '@')
4018 return parse(sig
, module
, str
);
4020 cover("kernel.rtlil.sigspec.parse.sel");
4022 str
= RTLIL::escape_id(str
.substr(1));
4023 if (design
->selection_vars
.count(str
) == 0)
4026 sig
= RTLIL::SigSpec();
4027 RTLIL::Selection
&sel
= design
->selection_vars
.at(str
);
4028 for (auto &it
: module
->wires_
)
4029 if (sel
.selected_member(module
->name
, it
.first
))
4030 sig
.append(it
.second
);
4035 bool RTLIL::SigSpec::parse_rhs(const RTLIL::SigSpec
&lhs
, RTLIL::SigSpec
&sig
, RTLIL::Module
*module
, std::string str
)
4038 cover("kernel.rtlil.sigspec.parse.rhs_zeros");
4039 sig
= RTLIL::SigSpec(RTLIL::State::S0
, lhs
.width_
);
4044 cover("kernel.rtlil.sigspec.parse.rhs_ones");
4045 sig
= RTLIL::SigSpec(RTLIL::State::S1
, lhs
.width_
);
4049 if (lhs
.chunks_
.size() == 1) {
4050 char *p
= (char*)str
.c_str(), *endptr
;
4051 long int val
= strtol(p
, &endptr
, 10);
4052 if (endptr
&& endptr
!= p
&& *endptr
== 0) {
4053 sig
= RTLIL::SigSpec(val
, lhs
.width_
);
4054 cover("kernel.rtlil.sigspec.parse.rhs_dec");
4059 return parse(sig
, module
, str
);
4062 RTLIL::CaseRule::~CaseRule()
4064 for (auto it
= switches
.begin(); it
!= switches
.end(); it
++)
4068 bool RTLIL::CaseRule::empty() const
4070 return actions
.empty() && switches
.empty();
4073 RTLIL::CaseRule
*RTLIL::CaseRule::clone() const
4075 RTLIL::CaseRule
*new_caserule
= new RTLIL::CaseRule
;
4076 new_caserule
->compare
= compare
;
4077 new_caserule
->actions
= actions
;
4078 for (auto &it
: switches
)
4079 new_caserule
->switches
.push_back(it
->clone());
4080 return new_caserule
;
4083 RTLIL::SwitchRule::~SwitchRule()
4085 for (auto it
= cases
.begin(); it
!= cases
.end(); it
++)
4089 bool RTLIL::SwitchRule::empty() const
4091 return cases
.empty();
4094 RTLIL::SwitchRule
*RTLIL::SwitchRule::clone() const
4096 RTLIL::SwitchRule
*new_switchrule
= new RTLIL::SwitchRule
;
4097 new_switchrule
->signal
= signal
;
4098 new_switchrule
->attributes
= attributes
;
4099 for (auto &it
: cases
)
4100 new_switchrule
->cases
.push_back(it
->clone());
4101 return new_switchrule
;
4105 RTLIL::SyncRule
*RTLIL::SyncRule::clone() const
4107 RTLIL::SyncRule
*new_syncrule
= new RTLIL::SyncRule
;
4108 new_syncrule
->type
= type
;
4109 new_syncrule
->signal
= signal
;
4110 new_syncrule
->actions
= actions
;
4111 return new_syncrule
;
4114 RTLIL::Process::~Process()
4116 for (auto it
= syncs
.begin(); it
!= syncs
.end(); it
++)
4120 RTLIL::Process
*RTLIL::Process::clone() const
4122 RTLIL::Process
*new_proc
= new RTLIL::Process
;
4124 new_proc
->name
= name
;
4125 new_proc
->attributes
= attributes
;
4127 RTLIL::CaseRule
*rc_ptr
= root_case
.clone();
4128 new_proc
->root_case
= *rc_ptr
;
4129 rc_ptr
->switches
.clear();
4132 for (auto &it
: syncs
)
4133 new_proc
->syncs
.push_back(it
->clone());
4139 RTLIL::Memory::~Memory()
4141 RTLIL::Memory::get_all_memorys()->erase(hashidx_
);
4143 static std::map
<unsigned int, RTLIL::Memory
*> all_memorys
;
4144 std::map
<unsigned int, RTLIL::Memory
*> *RTLIL::Memory::get_all_memorys(void)
4146 return &all_memorys
;